drivers/net/e1000/em_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_interrupts.h>
  13 #include <rte_byteorder.h>
  14 #include <rte_log.h>
  15 #include <rte_debug.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memory.h>
  22 #include <rte_eal.h>
  23 #include <rte_atomic.h>
  24 #include <rte_malloc.h>
  25 #include <rte_dev.h>
  26
  27 #include "e1000_logs.h"
  28 #include "base/e1000_api.h"
  29 #include "e1000_ethdev.h"
  30
  31 #define EM_EIAC                 0x000DC
  32
  33 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  34
  35
  36 static int eth_em_configure(struct rte_eth_dev *dev);
  37 static int eth_em_start(struct rte_eth_dev *dev);
  38 static void eth_em_stop(struct rte_eth_dev *dev);
  39 static void eth_em_close(struct rte_eth_dev *dev);
  40 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  41 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  42 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  43 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  44 static int eth_em_link_update(struct rte_eth_dev *dev,
  45                                 int wait_to_complete);
  46 static int eth_em_stats_get(struct rte_eth_dev *dev,
  47                                 struct rte_eth_stats *rte_stats);
  48 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  49 static void eth_em_infos_get(struct rte_eth_dev *dev,
  50                                 struct rte_eth_dev_info *dev_info);
  51 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  52                                 struct rte_eth_fc_conf *fc_conf);
  53 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  54                                 struct rte_eth_fc_conf *fc_conf);
  55 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  56 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  57 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  58 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
  59                                    struct rte_intr_handle *handle);
  60 static void eth_em_interrupt_handler(void *param);
  61
  62 static int em_hw_init(struct e1000_hw *hw);
  63 static int em_hardware_init(struct e1000_hw *hw);
  64 static void em_hw_control_acquire(struct e1000_hw *hw);
  65 static void em_hw_control_release(struct e1000_hw *hw);
  66 static void em_init_manageability(struct e1000_hw *hw);
  67 static void em_release_manageability(struct e1000_hw *hw);
  68
  69 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  70
  71 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  72                 uint16_t vlan_id, int on);
  73 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  74 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  75 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  76 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  77 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  78
  79 /*
  80 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  81                                         uint16_t vlan_id, int on);
  82 */
  83
  84 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
  85 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
  86 static void em_lsc_intr_disable(struct e1000_hw *hw);
  87 static void em_rxq_intr_enable(struct e1000_hw *hw);
  88 static void em_rxq_intr_disable(struct e1000_hw *hw);
  89
  90 static int eth_em_led_on(struct rte_eth_dev *dev);
  91 static int eth_em_led_off(struct rte_eth_dev *dev);
  92
  93 static int em_get_rx_buffer_size(struct e1000_hw *hw);
  94 static int eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
  95                           uint32_t index, uint32_t pool);
  96 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
  97
  98 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
  99                                    struct ether_addr *mc_addr_set,
 100                                    uint32_t nb_mc_addr);
 101
 102 #define EM_FC_PAUSE_TIME 0x0680
 103 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 104 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 105
 106 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 107
 108 int e1000_logtype_init;
 109 int e1000_logtype_driver;
 110
 111 /*
 112  * The set of PCI devices this driver supports
 113  */
 114 static const struct rte_pci_id pci_id_em_map[] = {
 115         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 116         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 117         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 118         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 119         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 120         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 121         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 122         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 123         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 124         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 125         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 126         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 127         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 128         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 129         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 130         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 131         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 132         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 133         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 134         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 135         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 136         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 137         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 138         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 139         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 140         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
 157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
 158         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
 159         { .vendor_id = 0, /* sentinel */ },
 160 };
 161
 162 static const struct eth_dev_ops eth_em_ops = {
 163         .dev_configure        = eth_em_configure,
 164         .dev_start            = eth_em_start,
 165         .dev_stop             = eth_em_stop,
 166         .dev_close            = eth_em_close,
 167         .promiscuous_enable   = eth_em_promiscuous_enable,
 168         .promiscuous_disable  = eth_em_promiscuous_disable,
 169         .allmulticast_enable  = eth_em_allmulticast_enable,
 170         .allmulticast_disable = eth_em_allmulticast_disable,
 171         .link_update          = eth_em_link_update,
 172         .stats_get            = eth_em_stats_get,
 173         .stats_reset          = eth_em_stats_reset,
 174         .dev_infos_get        = eth_em_infos_get,
 175         .mtu_set              = eth_em_mtu_set,
 176         .vlan_filter_set      = eth_em_vlan_filter_set,
 177         .vlan_offload_set     = eth_em_vlan_offload_set,
 178         .rx_queue_setup       = eth_em_rx_queue_setup,
 179         .rx_queue_release     = eth_em_rx_queue_release,
 180         .rx_queue_count       = eth_em_rx_queue_count,
 181         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 182         .rx_descriptor_status = eth_em_rx_descriptor_status,
 183         .tx_descriptor_status = eth_em_tx_descriptor_status,
 184         .tx_queue_setup       = eth_em_tx_queue_setup,
 185         .tx_queue_release     = eth_em_tx_queue_release,
 186         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 187         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 188         .dev_led_on           = eth_em_led_on,
 189         .dev_led_off          = eth_em_led_off,
 190         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 191         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 192         .mac_addr_add         = eth_em_rar_set,
 193         .mac_addr_remove      = eth_em_rar_clear,
 194         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 195         .rxq_info_get         = em_rxq_info_get,
 196         .txq_info_get         = em_txq_info_get,
 197 };
 198
 199 /**
 200  * Atomically reads the link status information from global
 201  * structure rte_eth_dev.
 202  *
 203  * @param dev
 204  *   - Pointer to the structure rte_eth_dev to read from.
 205  *   - Pointer to the buffer to be saved with the link status.
 206  *
 207  * @return
 208  *   - On success, zero.
 209  *   - On failure, negative value.
 210  */
 211 static inline int
 212 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 213                                 struct rte_eth_link *link)
 214 {
 215         struct rte_eth_link *dst = link;
 216         struct rte_eth_link *src = &(dev->data->dev_link);
 217
 218         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 219                                         *(uint64_t *)src) == 0)
 220                 return -1;
 221
 222         return 0;
 223 }
 224
 225 /**
 226  * Atomically writes the link status information into global
 227  * structure rte_eth_dev.
 228  *
 229  * @param dev
 230  *   - Pointer to the structure rte_eth_dev to read from.
 231  *   - Pointer to the buffer to be saved with the link status.
 232  *
 233  * @return
 234  *   - On success, zero.
 235  *   - On failure, negative value.
 236  */
 237 static inline int
 238 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 239                                 struct rte_eth_link *link)
 240 {
 241         struct rte_eth_link *dst = &(dev->data->dev_link);
 242         struct rte_eth_link *src = link;
 243
 244         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 245                                         *(uint64_t *)src) == 0)
 246                 return -1;
 247
 248         return 0;
 249 }
 250
 251 /**
 252  *  eth_em_dev_is_ich8 - Check for ICH8 device
 253  *  @hw: pointer to the HW structure
 254  *
 255  *  return TRUE for ICH8, otherwise FALSE
 256  **/
 257 static bool
 258 eth_em_dev_is_ich8(struct e1000_hw *hw)
 259 {
 260         DEBUGFUNC("eth_em_dev_is_ich8");
 261
 262         switch (hw->device_id) {
 263         case E1000_DEV_ID_PCH_LPT_I217_LM:
 264         case E1000_DEV_ID_PCH_LPT_I217_V:
 265         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 266         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 267         case E1000_DEV_ID_PCH_I218_V2:
 268         case E1000_DEV_ID_PCH_I218_LM2:
 269         case E1000_DEV_ID_PCH_I218_V3:
 270         case E1000_DEV_ID_PCH_I218_LM3:
 271         case E1000_DEV_ID_PCH_SPT_I219_LM:
 272         case E1000_DEV_ID_PCH_SPT_I219_V:
 273         case E1000_DEV_ID_PCH_SPT_I219_LM2:
 274         case E1000_DEV_ID_PCH_SPT_I219_V2:
 275         case E1000_DEV_ID_PCH_LBG_I219_LM3:
 276         case E1000_DEV_ID_PCH_SPT_I219_LM4:
 277         case E1000_DEV_ID_PCH_SPT_I219_V4:
 278         case E1000_DEV_ID_PCH_SPT_I219_LM5:
 279         case E1000_DEV_ID_PCH_SPT_I219_V5:
 280         case E1000_DEV_ID_PCH_CNP_I219_LM6:
 281         case E1000_DEV_ID_PCH_CNP_I219_V6:
 282         case E1000_DEV_ID_PCH_CNP_I219_LM7:
 283         case E1000_DEV_ID_PCH_CNP_I219_V7:
 284                 return 1;
 285         default:
 286                 return 0;
 287         }
 288 }
 289
 290 static int
 291 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 292 {
 293         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 294         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 295         struct e1000_adapter *adapter =
 296                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 297         struct e1000_hw *hw =
 298                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 299         struct e1000_vfta * shadow_vfta =
 300                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 301
 302         eth_dev->dev_ops = &eth_em_ops;
 303         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 304         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 305         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
 306
 307         /* for secondary processes, we don't initialise any further as primary
 308          * has already done this work. Only check we don't need a different
 309          * RX function */
 310         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 311                 if (eth_dev->data->scattered_rx)
 312                         eth_dev->rx_pkt_burst =
 313                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 314                 return 0;
 315         }
 316
 317         rte_eth_copy_pci_info(eth_dev, pci_dev);
 318
 319         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 320         hw->device_id = pci_dev->id.device_id;
 321         adapter->stopped = 0;
 322
 323         /* For ICH8 support we'll need to map the flash memory BAR */
 324         if (eth_em_dev_is_ich8(hw))
 325                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 326
 327         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 328                         em_hw_init(hw) != 0) {
 329                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 330                         "failed to init HW",
 331                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 332                         pci_dev->id.device_id);
 333                 return -ENODEV;
 334         }
 335
 336         /* Allocate memory for storing MAC addresses */
 337         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 338                         hw->mac.rar_entry_count, 0);
 339         if (eth_dev->data->mac_addrs == NULL) {
 340                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 341                         "store MAC addresses",
 342                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 343                 return -ENOMEM;
 344         }
 345
 346         /* Copy the permanent MAC address */
 347         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 348                 eth_dev->data->mac_addrs);
 349
 350         /* initialize the vfta */
 351         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 352
 353         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 354                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 355                      pci_dev->id.device_id);
 356
 357         rte_intr_callback_register(intr_handle,
 358                                    eth_em_interrupt_handler, eth_dev);
 359
 360         return 0;
 361 }
 362
 363 static int
 364 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 365 {
 366         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 367         struct e1000_adapter *adapter =
 368                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 369         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 370
 371         PMD_INIT_FUNC_TRACE();
 372
 373         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 374                 return -EPERM;
 375
 376         if (adapter->stopped == 0)
 377                 eth_em_close(eth_dev);
 378
 379         eth_dev->dev_ops = NULL;
 380         eth_dev->rx_pkt_burst = NULL;
 381         eth_dev->tx_pkt_burst = NULL;
 382
 383         rte_free(eth_dev->data->mac_addrs);
 384         eth_dev->data->mac_addrs = NULL;
 385
 386         /* disable uio intr before callback unregister */
 387         rte_intr_disable(intr_handle);
 388         rte_intr_callback_unregister(intr_handle,
 389                                      eth_em_interrupt_handler, eth_dev);
 390
 391         return 0;
 392 }
 393
 394 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 395         struct rte_pci_device *pci_dev)
 396 {
 397         return rte_eth_dev_pci_generic_probe(pci_dev,
 398                 sizeof(struct e1000_adapter), eth_em_dev_init);
 399 }
 400
 401 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
 402 {
 403         return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
 404 }
 405
 406 static struct rte_pci_driver rte_em_pmd = {
 407         .id_table = pci_id_em_map,
 408         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 409                      RTE_PCI_DRV_IOVA_AS_VA,
 410         .probe = eth_em_pci_probe,
 411         .remove = eth_em_pci_remove,
 412 };
 413
 414 static int
 415 em_hw_init(struct e1000_hw *hw)
 416 {
 417         int diag;
 418
 419         diag = hw->mac.ops.init_params(hw);
 420         if (diag != 0) {
 421                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 422                 return diag;
 423         }
 424         diag = hw->nvm.ops.init_params(hw);
 425         if (diag != 0) {
 426                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 427                 return diag;
 428         }
 429         diag = hw->phy.ops.init_params(hw);
 430         if (diag != 0) {
 431                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 432                 return diag;
 433         }
 434         (void) e1000_get_bus_info(hw);
 435
 436         hw->mac.autoneg = 1;
 437         hw->phy.autoneg_wait_to_complete = 0;
 438         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 439
 440         e1000_init_script_state_82541(hw, TRUE);
 441         e1000_set_tbi_compatibility_82543(hw, TRUE);
 442
 443         /* Copper options */
 444         if (hw->phy.media_type == e1000_media_type_copper) {
 445                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 446                 hw->phy.disable_polarity_correction = 0;
 447                 hw->phy.ms_type = e1000_ms_hw_default;
 448         }
 449
 450         /*
 451          * Start from a known state, this is important in reading the nvm
 452          * and mac from that.
 453          */
 454         e1000_reset_hw(hw);
 455
 456         /* Make sure we have a good EEPROM before we read from it */
 457         if (e1000_validate_nvm_checksum(hw) < 0) {
 458                 /*
 459                  * Some PCI-E parts fail the first check due to
 460                  * the link being in sleep state, call it again,
 461                  * if it fails a second time its a real issue.
 462                  */
 463                 diag = e1000_validate_nvm_checksum(hw);
 464                 if (diag < 0) {
 465                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 466                         goto error;
 467                 }
 468         }
 469
 470         /* Read the permanent MAC address out of the EEPROM */
 471         diag = e1000_read_mac_addr(hw);
 472         if (diag != 0) {
 473                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 474                 goto error;
 475         }
 476
 477         /* Now initialize the hardware */
 478         diag = em_hardware_init(hw);
 479         if (diag != 0) {
 480                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 481                 goto error;
 482         }
 483
 484         hw->mac.get_link_status = 1;
 485
 486         /* Indicate SOL/IDER usage */
 487         diag = e1000_check_reset_block(hw);
 488         if (diag < 0) {
 489                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 490                         "SOL/IDER session");
 491         }
 492         return 0;
 493
 494 error:
 495         em_hw_control_release(hw);
 496         return diag;
 497 }
 498
 499 static int
 500 eth_em_configure(struct rte_eth_dev *dev)
 501 {
 502         struct e1000_interrupt *intr =
 503                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 504
 505         PMD_INIT_FUNC_TRACE();
 506         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 507         PMD_INIT_FUNC_TRACE();
 508
 509         return 0;
 510 }
 511
 512 static void
 513 em_set_pba(struct e1000_hw *hw)
 514 {
 515         uint32_t pba;
 516
 517         /*
 518          * Packet Buffer Allocation (PBA)
 519          * Writing PBA sets the receive portion of the buffer
 520          * the remainder is used for the transmit buffer.
 521          * Devices before the 82547 had a Packet Buffer of 64K.
 522          * After the 82547 the buffer was reduced to 40K.
 523          */
 524         switch (hw->mac.type) {
 525                 case e1000_82547:
 526                 case e1000_82547_rev_2:
 527                 /* 82547: Total Packet Buffer is 40K */
 528                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 529                         break;
 530                 case e1000_82571:
 531                 case e1000_82572:
 532                 case e1000_80003es2lan:
 533                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 534                         break;
 535                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 536                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 537                         break;
 538                 case e1000_82574:
 539                 case e1000_82583:
 540                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 541                         break;
 542                 case e1000_ich8lan:
 543                         pba = E1000_PBA_8K;
 544                         break;
 545                 case e1000_ich9lan:
 546                 case e1000_ich10lan:
 547                         pba = E1000_PBA_10K;
 548                         break;
 549                 case e1000_pchlan:
 550                 case e1000_pch2lan:
 551                 case e1000_pch_lpt:
 552                 case e1000_pch_spt:
 553                 case e1000_pch_cnp:
 554                         pba = E1000_PBA_26K;
 555                         break;
 556                 default:
 557                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 558         }
 559
 560         E1000_WRITE_REG(hw, E1000_PBA, pba);
 561 }
 562
 563 static void
 564 eth_em_rxtx_control(struct rte_eth_dev *dev,
 565                     bool enable)
 566 {
 567         struct e1000_hw *hw =
 568                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 569         uint32_t tctl, rctl;
 570
 571         tctl = E1000_READ_REG(hw, E1000_TCTL);
 572         rctl = E1000_READ_REG(hw, E1000_RCTL);
 573         if (enable) {
 574                 /* enable Tx/Rx */
 575                 tctl |= E1000_TCTL_EN;
 576                 rctl |= E1000_RCTL_EN;
 577         } else {
 578                 /* disable Tx/Rx */
 579                 tctl &= ~E1000_TCTL_EN;
 580                 rctl &= ~E1000_RCTL_EN;
 581         }
 582         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
 583         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 584         E1000_WRITE_FLUSH(hw);
 585 }
 586
 587 static int
 588 eth_em_start(struct rte_eth_dev *dev)
 589 {
 590         struct e1000_adapter *adapter =
 591                 E1000_DEV_PRIVATE(dev->data->dev_private);
 592         struct e1000_hw *hw =
 593                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 594         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 595         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 596         int ret, mask;
 597         uint32_t intr_vector = 0;
 598         uint32_t *speeds;
 599         int num_speeds;
 600         bool autoneg;
 601
 602         PMD_INIT_FUNC_TRACE();
 603
 604         eth_em_stop(dev);
 605
 606         e1000_power_up_phy(hw);
 607
 608         /* Set default PBA value */
 609         em_set_pba(hw);
 610
 611         /* Put the address into the Receive Address Array */
 612         e1000_rar_set(hw, hw->mac.addr, 0);
 613
 614         /*
 615          * With the 82571 adapter, RAR[0] may be overwritten
 616          * when the other port is reset, we make a duplicate
 617          * in RAR[14] for that eventuality, this assures
 618          * the interface continues to function.
 619          */
 620         if (hw->mac.type == e1000_82571) {
 621                 e1000_set_laa_state_82571(hw, TRUE);
 622                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 623         }
 624
 625         /* Initialize the hardware */
 626         if (em_hardware_init(hw)) {
 627                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 628                 return -EIO;
 629         }
 630
 631         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 632
 633         /* Configure for OS presence */
 634         em_init_manageability(hw);
 635
 636         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 637                 intr_vector = dev->data->nb_rx_queues;
 638                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 639                         return -1;
 640         }
 641
 642         if (rte_intr_dp_is_en(intr_handle)) {
 643                 intr_handle->intr_vec =
 644                         rte_zmalloc("intr_vec",
 645                                         dev->data->nb_rx_queues * sizeof(int), 0);
 646                 if (intr_handle->intr_vec == NULL) {
 647                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 648                                                 " intr_vec", dev->data->nb_rx_queues);
 649                         return -ENOMEM;
 650                 }
 651
 652                 /* enable rx interrupt */
 653                 em_rxq_intr_enable(hw);
 654         }
 655
 656         eth_em_tx_init(dev);
 657
 658         ret = eth_em_rx_init(dev);
 659         if (ret) {
 660                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 661                 em_dev_clear_queues(dev);
 662                 return ret;
 663         }
 664
 665         e1000_clear_hw_cntrs_base_generic(hw);
 666
 667         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 668                         ETH_VLAN_EXTEND_MASK;
 669         ret = eth_em_vlan_offload_set(dev, mask);
 670         if (ret) {
 671                 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
 672                 em_dev_clear_queues(dev);
 673                 return ret;
 674         }
 675
 676         /* Set Interrupt Throttling Rate to maximum allowed value. */
 677         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 678
 679         /* Setup link speed and duplex */
 680         speeds = &dev->data->dev_conf.link_speeds;
 681         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 682                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 683                 hw->mac.autoneg = 1;
 684         } else {
 685                 num_speeds = 0;
 686                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 687
 688                 /* Reset */
 689                 hw->phy.autoneg_advertised = 0;
 690
 691                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 692                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 693                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 694                         num_speeds = -1;
 695                         goto error_invalid_config;
 696                 }
 697                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 698                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 699                         num_speeds++;
 700                 }
 701                 if (*speeds & ETH_LINK_SPEED_10M) {
 702                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 703                         num_speeds++;
 704                 }
 705                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 706                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 707                         num_speeds++;
 708                 }
 709                 if (*speeds & ETH_LINK_SPEED_100M) {
 710                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 711                         num_speeds++;
 712                 }
 713                 if (*speeds & ETH_LINK_SPEED_1G) {
 714                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 715                         num_speeds++;
 716                 }
 717                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 718                         goto error_invalid_config;
 719
 720                 /* Set/reset the mac.autoneg based on the link speed,
 721                  * fixed or not
 722                  */
 723                 if (!autoneg) {
 724                         hw->mac.autoneg = 0;
 725                         hw->mac.forced_speed_duplex =
 726                                         hw->phy.autoneg_advertised;
 727                 } else {
 728                         hw->mac.autoneg = 1;
 729                 }
 730         }
 731
 732         e1000_setup_link(hw);
 733
 734         if (rte_intr_allow_others(intr_handle)) {
 735                 /* check if lsc interrupt is enabled */
 736                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 737                         ret = eth_em_interrupt_setup(dev);
 738                         if (ret) {
 739                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 740                                 em_dev_clear_queues(dev);
 741                                 return ret;
 742                         }
 743                 }
 744         } else {
 745                 rte_intr_callback_unregister(intr_handle,
 746                                                 eth_em_interrupt_handler,
 747                                                 (void *)dev);
 748                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 749                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 750                                      " no intr multiplexn");
 751         }
 752         /* check if rxq interrupt is enabled */
 753         if (dev->data->dev_conf.intr_conf.rxq != 0)
 754                 eth_em_rxq_interrupt_setup(dev);
 755
 756         rte_intr_enable(intr_handle);
 757
 758         adapter->stopped = 0;
 759
 760         eth_em_rxtx_control(dev, true);
 761         eth_em_link_update(dev, 0);
 762
 763         PMD_INIT_LOG(DEBUG, "<<");
 764
 765         return 0;
 766
 767 error_invalid_config:
 768         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 769                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 770         em_dev_clear_queues(dev);
 771         return -EINVAL;
 772 }
 773
 774 /*********************************************************************
 775  *
 776  *  This routine disables all traffic on the adapter by issuing a
 777  *  global reset on the MAC.
 778  *
 779  **********************************************************************/
 780 static void
 781 eth_em_stop(struct rte_eth_dev *dev)
 782 {
 783         struct rte_eth_link link;
 784         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 785         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 786         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 787
 788         eth_em_rxtx_control(dev, false);
 789         em_rxq_intr_disable(hw);
 790         em_lsc_intr_disable(hw);
 791
 792         e1000_reset_hw(hw);
 793         if (hw->mac.type >= e1000_82544)
 794                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 795
 796         /* Power down the phy. Needed to make the link go down */
 797         e1000_power_down_phy(hw);
 798
 799         em_dev_clear_queues(dev);
 800
 801         /* clear the recorded link status */
 802         memset(&link, 0, sizeof(link));
 803         rte_em_dev_atomic_write_link_status(dev, &link);
 804
 805         if (!rte_intr_allow_others(intr_handle))
 806                 /* resume to the default handler */
 807                 rte_intr_callback_register(intr_handle,
 808                                            eth_em_interrupt_handler,
 809                                            (void *)dev);
 810
 811         /* Clean datapath event and queue/vec mapping */
 812         rte_intr_efd_disable(intr_handle);
 813         if (intr_handle->intr_vec != NULL) {
 814                 rte_free(intr_handle->intr_vec);
 815                 intr_handle->intr_vec = NULL;
 816         }
 817 }
 818
 819 static void
 820 eth_em_close(struct rte_eth_dev *dev)
 821 {
 822         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 823         struct e1000_adapter *adapter =
 824                 E1000_DEV_PRIVATE(dev->data->dev_private);
 825
 826         eth_em_stop(dev);
 827         adapter->stopped = 1;
 828         em_dev_free_queues(dev);
 829         e1000_phy_hw_reset(hw);
 830         em_release_manageability(hw);
 831         em_hw_control_release(hw);
 832 }
 833
 834 static int
 835 em_get_rx_buffer_size(struct e1000_hw *hw)
 836 {
 837         uint32_t rx_buf_size;
 838
 839         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 840         return rx_buf_size;
 841 }
 842
 843 /*********************************************************************
 844  *
 845  *  Initialize the hardware
 846  *
 847  **********************************************************************/
 848 static int
 849 em_hardware_init(struct e1000_hw *hw)
 850 {
 851         uint32_t rx_buf_size;
 852         int diag;
 853
 854         /* Issue a global reset */
 855         e1000_reset_hw(hw);
 856
 857         /* Let the firmware know the OS is in control */
 858         em_hw_control_acquire(hw);
 859
 860         /*
 861          * These parameters control the automatic generation (Tx) and
 862          * response (Rx) to Ethernet PAUSE frames.
 863          * - High water mark should allow for at least two standard size (1518)
 864          *   frames to be received after sending an XOFF.
 865          * - Low water mark works best when it is very near the high water mark.
 866          *   This allows the receiver to restart by sending XON when it has
 867          *   drained a bit. Here we use an arbitrary value of 1500 which will
 868          *   restart after one full frame is pulled from the buffer. There
 869          *   could be several smaller frames in the buffer and if so they will
 870          *   not trigger the XON until their total number reduces the buffer
 871          *   by 1500.
 872          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 873          */
 874         rx_buf_size = em_get_rx_buffer_size(hw);
 875
 876         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 877         hw->fc.low_water = hw->fc.high_water - 1500;
 878
 879         if (hw->mac.type == e1000_80003es2lan)
 880                 hw->fc.pause_time = UINT16_MAX;
 881         else
 882                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 883
 884         hw->fc.send_xon = 1;
 885
 886         /* Set Flow control, use the tunable location if sane */
 887         if (em_fc_setting <= e1000_fc_full)
 888                 hw->fc.requested_mode = em_fc_setting;
 889         else
 890                 hw->fc.requested_mode = e1000_fc_none;
 891
 892         /* Workaround: no TX flow ctrl for PCH */
 893         if (hw->mac.type == e1000_pchlan)
 894                 hw->fc.requested_mode = e1000_fc_rx_pause;
 895
 896         /* Override - settings for PCH2LAN, ya its magic :) */
 897         if (hw->mac.type == e1000_pch2lan) {
 898                 hw->fc.high_water = 0x5C20;
 899                 hw->fc.low_water = 0x5048;
 900                 hw->fc.pause_time = 0x0650;
 901                 hw->fc.refresh_time = 0x0400;
 902         } else if (hw->mac.type == e1000_pch_lpt ||
 903                    hw->mac.type == e1000_pch_spt ||
 904                    hw->mac.type == e1000_pch_cnp) {
 905                 hw->fc.requested_mode = e1000_fc_full;
 906         }
 907
 908         diag = e1000_init_hw(hw);
 909         if (diag < 0)
 910                 return diag;
 911         e1000_check_for_link(hw);
 912         return 0;
 913 }
 914
 915 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 916 static int
 917 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 918 {
 919         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 920         struct e1000_hw_stats *stats =
 921                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 922         int pause_frames;
 923
 924         if(hw->phy.media_type == e1000_media_type_copper ||
 925                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 926                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 927                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 928         }
 929
 930         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 931         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 932         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 933         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 934
 935         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 936         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 937         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 938         stats->dc += E1000_READ_REG(hw, E1000_DC);
 939         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 940         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 941         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 942
 943         /*
 944          * For watchdog management we need to know if we have been
 945          * paused during the last interval, so capture that here.
 946          */
 947         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 948         stats->xoffrxc += pause_frames;
 949         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 950         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 951         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 952         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 953         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 954         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 955         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 956         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 957         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 958         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 959         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 960         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 961
 962         /*
 963          * For the 64-bit byte counters the low dword must be read first.
 964          * Both registers clear on the read of the high dword.
 965          */
 966
 967         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 968         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 969         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 970         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 971
 972         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 973         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 974         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 975         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 976         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 977
 978         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 979         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 980
 981         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 982         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 983         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 984         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 985         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 986         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 987         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 988         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 989         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 990         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 991
 992         /* Interrupt Counts */
 993
 994         if (hw->mac.type >= e1000_82571) {
 995                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 996                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 997                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 998                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 999                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1000                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1001                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1002                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1003                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1004         }
1005
1006         if (hw->mac.type >= e1000_82543) {
1007                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1008                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1009                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1010                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1011                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1012                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1013         }
1014
1015         if (rte_stats == NULL)
1016                 return -EINVAL;
1017
1018         /* Rx Errors */
1019         rte_stats->imissed = stats->mpc;
1020         rte_stats->ierrors = stats->crcerrs +
1021                              stats->rlec + stats->ruc + stats->roc +
1022                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1023
1024         /* Tx Errors */
1025         rte_stats->oerrors = stats->ecol + stats->latecol;
1026
1027         rte_stats->ipackets = stats->gprc;
1028         rte_stats->opackets = stats->gptc;
1029         rte_stats->ibytes   = stats->gorc;
1030         rte_stats->obytes   = stats->gotc;
1031         return 0;
1032 }
1033
1034 static void
1035 eth_em_stats_reset(struct rte_eth_dev *dev)
1036 {
1037         struct e1000_hw_stats *hw_stats =
1038                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1039
1040         /* HW registers are cleared on read */
1041         eth_em_stats_get(dev, NULL);
1042
1043         /* Reset software totals */
1044         memset(hw_stats, 0, sizeof(*hw_stats));
1045 }
1046
1047 static int
1048 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1049 {
1050         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1051         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1052         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1053
1054         em_rxq_intr_enable(hw);
1055         rte_intr_enable(intr_handle);
1056
1057         return 0;
1058 }
1059
1060 static int
1061 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1062 {
1063         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1064
1065         em_rxq_intr_disable(hw);
1066
1067         return 0;
1068 }
1069
1070 static uint32_t
1071 em_get_max_pktlen(const struct e1000_hw *hw)
1072 {
1073         switch (hw->mac.type) {
1074         case e1000_82571:
1075         case e1000_82572:
1076         case e1000_ich9lan:
1077         case e1000_ich10lan:
1078         case e1000_pch2lan:
1079         case e1000_pch_lpt:
1080         case e1000_pch_spt:
1081         case e1000_pch_cnp:
1082         case e1000_82574:
1083         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1084         case e1000_82583:
1085                 return 0x2412;
1086         case e1000_pchlan:
1087                 return 0x1000;
1088         /* Adapters that do not support jumbo frames */
1089         case e1000_ich8lan:
1090                 return ETHER_MAX_LEN;
1091         default:
1092                 return MAX_JUMBO_FRAME_SIZE;
1093         }
1094 }
1095
1096 static void
1097 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1098 {
1099         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1100
1101         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1102         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1103         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1104         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1105         dev_info->rx_offload_capa =
1106                 DEV_RX_OFFLOAD_VLAN_STRIP |
1107                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1108                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1109                 DEV_RX_OFFLOAD_TCP_CKSUM;
1110         dev_info->tx_offload_capa =
1111                 DEV_TX_OFFLOAD_VLAN_INSERT |
1112                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1113                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1114                 DEV_TX_OFFLOAD_TCP_CKSUM;
1115
1116         /*
1117          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1118          * Unfortunatelly, all these nics have just one TX context.
1119          * So we have few choises for TX:
1120          * - Use just one TX queue.
1121          * - Allow cksum offload only for one TX queue.
1122          * - Don't allow TX cksum offload at all.
1123          * For now, option #1 was chosen.
1124          * To use second RX queue we have to use extended RX descriptor
1125          * (Multiple Receive Queues are mutually exclusive with UDP
1126          * fragmentation and are not supported when a legacy receive
1127          * descriptor format is used).
1128          * Which means separate RX routinies - as legacy nics (82540, 82545)
1129          * don't support extended RXD.
1130          * To avoid it we support just one RX queue for now (no RSS).
1131          */
1132
1133         dev_info->max_rx_queues = 1;
1134         dev_info->max_tx_queues = 1;
1135
1136         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1137                 .nb_max = E1000_MAX_RING_DESC,
1138                 .nb_min = E1000_MIN_RING_DESC,
1139                 .nb_align = EM_RXD_ALIGN,
1140         };
1141
1142         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1143                 .nb_max = E1000_MAX_RING_DESC,
1144                 .nb_min = E1000_MIN_RING_DESC,
1145                 .nb_align = EM_TXD_ALIGN,
1146                 .nb_seg_max = EM_TX_MAX_SEG,
1147                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1148         };
1149
1150         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1151                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1152                         ETH_LINK_SPEED_1G;
1153 }
1154
1155 /* return 0 means link status changed, -1 means not changed */
1156 static int
1157 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1158 {
1159         struct e1000_hw *hw =
1160                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1161         struct rte_eth_link link, old;
1162         int link_check, count;
1163
1164         link_check = 0;
1165         hw->mac.get_link_status = 1;
1166
1167         /* possible wait-to-complete in up to 9 seconds */
1168         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1169                 /* Read the real link status */
1170                 switch (hw->phy.media_type) {
1171                 case e1000_media_type_copper:
1172                         /* Do the work to read phy */
1173                         e1000_check_for_link(hw);
1174                         link_check = !hw->mac.get_link_status;
1175                         break;
1176
1177                 case e1000_media_type_fiber:
1178                         e1000_check_for_link(hw);
1179                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1180                                         E1000_STATUS_LU);
1181                         break;
1182
1183                 case e1000_media_type_internal_serdes:
1184                         e1000_check_for_link(hw);
1185                         link_check = hw->mac.serdes_has_link;
1186                         break;
1187
1188                 default:
1189                         break;
1190                 }
1191                 if (link_check || wait_to_complete == 0)
1192                         break;
1193                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1194         }
1195         memset(&link, 0, sizeof(link));
1196         rte_em_dev_atomic_read_link_status(dev, &link);
1197         old = link;
1198
1199         /* Now we check if a transition has happened */
1200         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1201                 uint16_t duplex, speed;
1202                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1203                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1204                                 ETH_LINK_FULL_DUPLEX :
1205                                 ETH_LINK_HALF_DUPLEX;
1206                 link.link_speed = speed;
1207                 link.link_status = ETH_LINK_UP;
1208                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1209                                 ETH_LINK_SPEED_FIXED);
1210         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1211                 link.link_speed = 0;
1212                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1213                 link.link_status = ETH_LINK_DOWN;
1214                 link.link_autoneg = ETH_LINK_FIXED;
1215         }
1216         rte_em_dev_atomic_write_link_status(dev, &link);
1217
1218         /* not changed */
1219         if (old.link_status == link.link_status)
1220                 return -1;
1221
1222         /* changed */
1223         return 0;
1224 }
1225
1226 /*
1227  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1228  * For ASF and Pass Through versions of f/w this means
1229  * that the driver is loaded. For AMT version type f/w
1230  * this means that the network i/f is open.
1231  */
1232 static void
1233 em_hw_control_acquire(struct e1000_hw *hw)
1234 {
1235         uint32_t ctrl_ext, swsm;
1236
1237         /* Let firmware know the driver has taken over */
1238         if (hw->mac.type == e1000_82573) {
1239                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1240                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1241
1242         } else {
1243                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1244                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1245                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1246         }
1247 }
1248
1249 /*
1250  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1251  * For ASF and Pass Through versions of f/w this means that the
1252  * driver is no longer loaded. For AMT versions of the
1253  * f/w this means that the network i/f is closed.
1254  */
1255 static void
1256 em_hw_control_release(struct e1000_hw *hw)
1257 {
1258         uint32_t ctrl_ext, swsm;
1259
1260         /* Let firmware taken over control of h/w */
1261         if (hw->mac.type == e1000_82573) {
1262                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1263                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1264         } else {
1265                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1266                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1267                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1268         }
1269 }
1270
1271 /*
1272  * Bit of a misnomer, what this really means is
1273  * to enable OS management of the system... aka
1274  * to disable special hardware management features.
1275  */
1276 static void
1277 em_init_manageability(struct e1000_hw *hw)
1278 {
1279         if (e1000_enable_mng_pass_thru(hw)) {
1280                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1281                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1282
1283                 /* disable hardware interception of ARP */
1284                 manc &= ~(E1000_MANC_ARP_EN);
1285
1286                 /* enable receiving management packets to the host */
1287                 manc |= E1000_MANC_EN_MNG2HOST;
1288                 manc2h |= 1 << 5;  /* Mng Port 623 */
1289                 manc2h |= 1 << 6;  /* Mng Port 664 */
1290                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1291                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1292         }
1293 }
1294
1295 /*
1296  * Give control back to hardware management
1297  * controller if there is one.
1298  */
1299 static void
1300 em_release_manageability(struct e1000_hw *hw)
1301 {
1302         uint32_t manc;
1303
1304         if (e1000_enable_mng_pass_thru(hw)) {
1305                 manc = E1000_READ_REG(hw, E1000_MANC);
1306
1307                 /* re-enable hardware interception of ARP */
1308                 manc |= E1000_MANC_ARP_EN;
1309                 manc &= ~E1000_MANC_EN_MNG2HOST;
1310
1311                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1312         }
1313 }
1314
1315 static void
1316 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1317 {
1318         struct e1000_hw *hw =
1319                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1320         uint32_t rctl;
1321
1322         rctl = E1000_READ_REG(hw, E1000_RCTL);
1323         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1324         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1325 }
1326
1327 static void
1328 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1329 {
1330         struct e1000_hw *hw =
1331                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1332         uint32_t rctl;
1333
1334         rctl = E1000_READ_REG(hw, E1000_RCTL);
1335         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1336         if (dev->data->all_multicast == 1)
1337                 rctl |= E1000_RCTL_MPE;
1338         else
1339                 rctl &= (~E1000_RCTL_MPE);
1340         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1341 }
1342
1343 static void
1344 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1345 {
1346         struct e1000_hw *hw =
1347                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348         uint32_t rctl;
1349
1350         rctl = E1000_READ_REG(hw, E1000_RCTL);
1351         rctl |= E1000_RCTL_MPE;
1352         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1353 }
1354
1355 static void
1356 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1357 {
1358         struct e1000_hw *hw =
1359                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1360         uint32_t rctl;
1361
1362         if (dev->data->promiscuous == 1)
1363                 return; /* must remain in all_multicast mode */
1364         rctl = E1000_READ_REG(hw, E1000_RCTL);
1365         rctl &= (~E1000_RCTL_MPE);
1366         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1367 }
1368
1369 static int
1370 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1371 {
1372         struct e1000_hw *hw =
1373                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1374         struct e1000_vfta * shadow_vfta =
1375                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1376         uint32_t vfta;
1377         uint32_t vid_idx;
1378         uint32_t vid_bit;
1379
1380         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1381                               E1000_VFTA_ENTRY_MASK);
1382         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1383         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1384         if (on)
1385                 vfta |= vid_bit;
1386         else
1387                 vfta &= ~vid_bit;
1388         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1389
1390         /* update local VFTA copy */
1391         shadow_vfta->vfta[vid_idx] = vfta;
1392
1393         return 0;
1394 }
1395
1396 static void
1397 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1398 {
1399         struct e1000_hw *hw =
1400                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1401         uint32_t reg;
1402
1403         /* Filter Table Disable */
1404         reg = E1000_READ_REG(hw, E1000_RCTL);
1405         reg &= ~E1000_RCTL_CFIEN;
1406         reg &= ~E1000_RCTL_VFE;
1407         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1408 }
1409
1410 static void
1411 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1412 {
1413         struct e1000_hw *hw =
1414                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1415         struct e1000_vfta * shadow_vfta =
1416                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1417         uint32_t reg;
1418         int i;
1419
1420         /* Filter Table Enable, CFI not used for packet acceptance */
1421         reg = E1000_READ_REG(hw, E1000_RCTL);
1422         reg &= ~E1000_RCTL_CFIEN;
1423         reg |= E1000_RCTL_VFE;
1424         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1425
1426         /* restore vfta from local copy */
1427         for (i = 0; i < IGB_VFTA_SIZE; i++)
1428                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1429 }
1430
1431 static void
1432 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1433 {
1434         struct e1000_hw *hw =
1435                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1436         uint32_t reg;
1437
1438         /* VLAN Mode Disable */
1439         reg = E1000_READ_REG(hw, E1000_CTRL);
1440         reg &= ~E1000_CTRL_VME;
1441         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1442
1443 }
1444
1445 static void
1446 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1447 {
1448         struct e1000_hw *hw =
1449                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1450         uint32_t reg;
1451
1452         /* VLAN Mode Enable */
1453         reg = E1000_READ_REG(hw, E1000_CTRL);
1454         reg |= E1000_CTRL_VME;
1455         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1456 }
1457
1458 static int
1459 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1460 {
1461         if(mask & ETH_VLAN_STRIP_MASK){
1462                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1463                         em_vlan_hw_strip_enable(dev);
1464                 else
1465                         em_vlan_hw_strip_disable(dev);
1466         }
1467
1468         if(mask & ETH_VLAN_FILTER_MASK){
1469                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1470                         em_vlan_hw_filter_enable(dev);
1471                 else
1472                         em_vlan_hw_filter_disable(dev);
1473         }
1474
1475         return 0;
1476 }
1477
1478 /*
1479  * It enables the interrupt mask and then enable the interrupt.
1480  *
1481  * @param dev
1482  *  Pointer to struct rte_eth_dev.
1483  *
1484  * @return
1485  *  - On success, zero.
1486  *  - On failure, a negative value.
1487  */
1488 static int
1489 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1490 {
1491         uint32_t regval;
1492         struct e1000_hw *hw =
1493                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1494
1495         /* clear interrupt */
1496         E1000_READ_REG(hw, E1000_ICR);
1497         regval = E1000_READ_REG(hw, E1000_IMS);
1498         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1499         return 0;
1500 }
1501
1502 /*
1503  * It clears the interrupt causes and enables the interrupt.
1504  * It will be called once only during nic initialized.
1505  *
1506  * @param dev
1507  *  Pointer to struct rte_eth_dev.
1508  *
1509  * @return
1510  *  - On success, zero.
1511  *  - On failure, a negative value.
1512  */
1513 static int
1514 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1515 {
1516         struct e1000_hw *hw =
1517         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518
1519         E1000_READ_REG(hw, E1000_ICR);
1520         em_rxq_intr_enable(hw);
1521         return 0;
1522 }
1523
1524 /*
1525  * It enable receive packet interrupt.
1526  * @param hw
1527  * Pointer to struct e1000_hw
1528  *
1529  * @return
1530  */
1531 static void
1532 em_rxq_intr_enable(struct e1000_hw *hw)
1533 {
1534         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1535         E1000_WRITE_FLUSH(hw);
1536 }
1537
1538 /*
1539  * It disabled lsc interrupt.
1540  * @param hw
1541  * Pointer to struct e1000_hw
1542  *
1543  * @return
1544  */
1545 static void
1546 em_lsc_intr_disable(struct e1000_hw *hw)
1547 {
1548         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1549         E1000_WRITE_FLUSH(hw);
1550 }
1551
1552 /*
1553  * It disabled receive packet interrupt.
1554  * @param hw
1555  * Pointer to struct e1000_hw
1556  *
1557  * @return
1558  */
1559 static void
1560 em_rxq_intr_disable(struct e1000_hw *hw)
1561 {
1562         E1000_READ_REG(hw, E1000_ICR);
1563         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1564         E1000_WRITE_FLUSH(hw);
1565 }
1566
1567 /*
1568  * It reads ICR and gets interrupt causes, check it and set a bit flag
1569  * to update link status.
1570  *
1571  * @param dev
1572  *  Pointer to struct rte_eth_dev.
1573  *
1574  * @return
1575  *  - On success, zero.
1576  *  - On failure, a negative value.
1577  */
1578 static int
1579 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1580 {
1581         uint32_t icr;
1582         struct e1000_hw *hw =
1583                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1584         struct e1000_interrupt *intr =
1585                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1586
1587         /* read-on-clear nic registers here */
1588         icr = E1000_READ_REG(hw, E1000_ICR);
1589         if (icr & E1000_ICR_LSC) {
1590                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1591         }
1592
1593         return 0;
1594 }
1595
1596 /*
1597  * It executes link_update after knowing an interrupt is prsent.
1598  *
1599  * @param dev
1600  *  Pointer to struct rte_eth_dev.
1601  *
1602  * @return
1603  *  - On success, zero.
1604  *  - On failure, a negative value.
1605  */
1606 static int
1607 eth_em_interrupt_action(struct rte_eth_dev *dev,
1608                         struct rte_intr_handle *intr_handle)
1609 {
1610         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1611         struct e1000_hw *hw =
1612                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613         struct e1000_interrupt *intr =
1614                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1615         struct rte_eth_link link;
1616         int ret;
1617
1618         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1619                 return -1;
1620
1621         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1622         rte_intr_enable(intr_handle);
1623
1624         /* set get_link_status to check register later */
1625         hw->mac.get_link_status = 1;
1626         ret = eth_em_link_update(dev, 0);
1627
1628         /* check if link has changed */
1629         if (ret < 0)
1630                 return 0;
1631
1632         memset(&link, 0, sizeof(link));
1633         rte_em_dev_atomic_read_link_status(dev, &link);
1634         if (link.link_status) {
1635                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1636                              dev->data->port_id, link.link_speed,
1637                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1638                              "full-duplex" : "half-duplex");
1639         } else {
1640                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1641         }
1642         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1643                      pci_dev->addr.domain, pci_dev->addr.bus,
1644                      pci_dev->addr.devid, pci_dev->addr.function);
1645
1646         return 0;
1647 }
1648
1649 /**
1650  * Interrupt handler which shall be registered at first.
1651  *
1652  * @param handle
1653  *  Pointer to interrupt handle.
1654  * @param param
1655  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1656  *
1657  * @return
1658  *  void
1659  */
1660 static void
1661 eth_em_interrupt_handler(void *param)
1662 {
1663         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1664
1665         eth_em_interrupt_get_status(dev);
1666         eth_em_interrupt_action(dev, dev->intr_handle);
1667         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1668 }
1669
1670 static int
1671 eth_em_led_on(struct rte_eth_dev *dev)
1672 {
1673         struct e1000_hw *hw;
1674
1675         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1676         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1677 }
1678
1679 static int
1680 eth_em_led_off(struct rte_eth_dev *dev)
1681 {
1682         struct e1000_hw *hw;
1683
1684         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1686 }
1687
1688 static int
1689 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1690 {
1691         struct e1000_hw *hw;
1692         uint32_t ctrl;
1693         int tx_pause;
1694         int rx_pause;
1695
1696         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1697         fc_conf->pause_time = hw->fc.pause_time;
1698         fc_conf->high_water = hw->fc.high_water;
1699         fc_conf->low_water = hw->fc.low_water;
1700         fc_conf->send_xon = hw->fc.send_xon;
1701         fc_conf->autoneg = hw->mac.autoneg;
1702
1703         /*
1704          * Return rx_pause and tx_pause status according to actual setting of
1705          * the TFCE and RFCE bits in the CTRL register.
1706          */
1707         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1708         if (ctrl & E1000_CTRL_TFCE)
1709                 tx_pause = 1;
1710         else
1711                 tx_pause = 0;
1712
1713         if (ctrl & E1000_CTRL_RFCE)
1714                 rx_pause = 1;
1715         else
1716                 rx_pause = 0;
1717
1718         if (rx_pause && tx_pause)
1719                 fc_conf->mode = RTE_FC_FULL;
1720         else if (rx_pause)
1721                 fc_conf->mode = RTE_FC_RX_PAUSE;
1722         else if (tx_pause)
1723                 fc_conf->mode = RTE_FC_TX_PAUSE;
1724         else
1725                 fc_conf->mode = RTE_FC_NONE;
1726
1727         return 0;
1728 }
1729
1730 static int
1731 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1732 {
1733         struct e1000_hw *hw;
1734         int err;
1735         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1736                 e1000_fc_none,
1737                 e1000_fc_rx_pause,
1738                 e1000_fc_tx_pause,
1739                 e1000_fc_full
1740         };
1741         uint32_t rx_buf_size;
1742         uint32_t max_high_water;
1743         uint32_t rctl;
1744
1745         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1746         if (fc_conf->autoneg != hw->mac.autoneg)
1747                 return -ENOTSUP;
1748         rx_buf_size = em_get_rx_buffer_size(hw);
1749         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1750
1751         /* At least reserve one Ethernet frame for watermark */
1752         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1753         if ((fc_conf->high_water > max_high_water) ||
1754             (fc_conf->high_water < fc_conf->low_water)) {
1755                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1756                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1757                 return -EINVAL;
1758         }
1759
1760         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1761         hw->fc.pause_time     = fc_conf->pause_time;
1762         hw->fc.high_water     = fc_conf->high_water;
1763         hw->fc.low_water      = fc_conf->low_water;
1764         hw->fc.send_xon       = fc_conf->send_xon;
1765
1766         err = e1000_setup_link_generic(hw);
1767         if (err == E1000_SUCCESS) {
1768
1769                 /* check if we want to forward MAC frames - driver doesn't have native
1770                  * capability to do that, so we'll write the registers ourselves */
1771
1772                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1773
1774                 /* set or clear MFLCN.PMCF bit depending on configuration */
1775                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1776                         rctl |= E1000_RCTL_PMCF;
1777                 else
1778                         rctl &= ~E1000_RCTL_PMCF;
1779
1780                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1781                 E1000_WRITE_FLUSH(hw);
1782
1783                 return 0;
1784         }
1785
1786         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1787         return -EIO;
1788 }
1789
1790 static int
1791 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1792                 uint32_t index, __rte_unused uint32_t pool)
1793 {
1794         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1795
1796         return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1797 }
1798
1799 static void
1800 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1801 {
1802         uint8_t addr[ETHER_ADDR_LEN];
1803         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1804
1805         memset(addr, 0, sizeof(addr));
1806
1807         e1000_rar_set(hw, addr, index);
1808 }
1809
1810 static int
1811 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1812 {
1813         struct rte_eth_dev_info dev_info;
1814         struct e1000_hw *hw;
1815         uint32_t frame_size;
1816         uint32_t rctl;
1817
1818         eth_em_infos_get(dev, &dev_info);
1819         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1820
1821         /* check that mtu is within the allowed range */
1822         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1823                 return -EINVAL;
1824
1825         /* refuse mtu that requires the support of scattered packets when this
1826          * feature has not been enabled before. */
1827         if (!dev->data->scattered_rx &&
1828             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1829                 return -EINVAL;
1830
1831         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1832         rctl = E1000_READ_REG(hw, E1000_RCTL);
1833
1834         /* switch to jumbo mode if needed */
1835         if (frame_size > ETHER_MAX_LEN) {
1836                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1837                 rctl |= E1000_RCTL_LPE;
1838         } else {
1839                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1840                 rctl &= ~E1000_RCTL_LPE;
1841         }
1842         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1843
1844         /* update max frame size */
1845         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1846         return 0;
1847 }
1848
1849 static int
1850 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1851                         struct ether_addr *mc_addr_set,
1852                         uint32_t nb_mc_addr)
1853 {
1854         struct e1000_hw *hw;
1855
1856         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1857         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1858         return 0;
1859 }
1860
1861 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1862 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1863 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
1864
1865 RTE_INIT(e1000_init_log);
1866 static void
1867 e1000_init_log(void)
1868 {
1869         e1000_logtype_init = rte_log_register("pmd.e1000.init");
1870         if (e1000_logtype_init >= 0)
1871                 rte_log_set_level(e1000_logtype_init, RTE_LOG_NOTICE);
1872         e1000_logtype_driver = rte_log_register("pmd.e1000.driver");
1873         if (e1000_logtype_driver >= 0)
1874                 rte_log_set_level(e1000_logtype_driver, RTE_LOG_NOTICE);
1875 }