drivers/net/e1000/em_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_interrupts.h>
  13 #include <rte_byteorder.h>
  14 #include <rte_log.h>
  15 #include <rte_debug.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memory.h>
  22 #include <rte_eal.h>
  23 #include <rte_malloc.h>
  24 #include <rte_dev.h>
  25
  26 #include "e1000_logs.h"
  27 #include "base/e1000_api.h"
  28 #include "e1000_ethdev.h"
  29
  30 #define EM_EIAC                 0x000DC
  31
  32 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  33
  34
  35 static int eth_em_configure(struct rte_eth_dev *dev);
  36 static int eth_em_start(struct rte_eth_dev *dev);
  37 static void eth_em_stop(struct rte_eth_dev *dev);
  38 static void eth_em_close(struct rte_eth_dev *dev);
  39 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  40 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  41 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  42 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  43 static int eth_em_link_update(struct rte_eth_dev *dev,
  44                                 int wait_to_complete);
  45 static int eth_em_stats_get(struct rte_eth_dev *dev,
  46                                 struct rte_eth_stats *rte_stats);
  47 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  48 static void eth_em_infos_get(struct rte_eth_dev *dev,
  49                                 struct rte_eth_dev_info *dev_info);
  50 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  51                                 struct rte_eth_fc_conf *fc_conf);
  52 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  53                                 struct rte_eth_fc_conf *fc_conf);
  54 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  55 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  56 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  57 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
  58                                    struct rte_intr_handle *handle);
  59 static void eth_em_interrupt_handler(void *param);
  60
  61 static int em_hw_init(struct e1000_hw *hw);
  62 static int em_hardware_init(struct e1000_hw *hw);
  63 static void em_hw_control_acquire(struct e1000_hw *hw);
  64 static void em_hw_control_release(struct e1000_hw *hw);
  65 static void em_init_manageability(struct e1000_hw *hw);
  66 static void em_release_manageability(struct e1000_hw *hw);
  67
  68 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  69
  70 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  71                 uint16_t vlan_id, int on);
  72 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  73 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  74 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  75 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  76 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  77
  78 /*
  79 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  80                                         uint16_t vlan_id, int on);
  81 */
  82
  83 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
  84 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
  85 static void em_lsc_intr_disable(struct e1000_hw *hw);
  86 static void em_rxq_intr_enable(struct e1000_hw *hw);
  87 static void em_rxq_intr_disable(struct e1000_hw *hw);
  88
  89 static int eth_em_led_on(struct rte_eth_dev *dev);
  90 static int eth_em_led_off(struct rte_eth_dev *dev);
  91
  92 static int em_get_rx_buffer_size(struct e1000_hw *hw);
  93 static int eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
  94                           uint32_t index, uint32_t pool);
  95 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
  96
  97 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
  98                                    struct ether_addr *mc_addr_set,
  99                                    uint32_t nb_mc_addr);
 100
 101 #define EM_FC_PAUSE_TIME 0x0680
 102 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 103 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 104
 105 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 106
 107 int e1000_logtype_init;
 108 int e1000_logtype_driver;
 109
 110 /*
 111  * The set of PCI devices this driver supports
 112  */
 113 static const struct rte_pci_id pci_id_em_map[] = {
 114         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 115         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 116         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 117         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 118         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 119         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 120         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 121         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 122         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 123         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 124         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 125         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 126         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 127         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 128         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 129         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 130         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 131         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 132         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 133         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 134         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 135         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 136         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 137         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH2_LV_LM) },
 138         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 139         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 140         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
 157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
 158         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
 159         { .vendor_id = 0, /* sentinel */ },
 160 };
 161
 162 static const struct eth_dev_ops eth_em_ops = {
 163         .dev_configure        = eth_em_configure,
 164         .dev_start            = eth_em_start,
 165         .dev_stop             = eth_em_stop,
 166         .dev_close            = eth_em_close,
 167         .promiscuous_enable   = eth_em_promiscuous_enable,
 168         .promiscuous_disable  = eth_em_promiscuous_disable,
 169         .allmulticast_enable  = eth_em_allmulticast_enable,
 170         .allmulticast_disable = eth_em_allmulticast_disable,
 171         .link_update          = eth_em_link_update,
 172         .stats_get            = eth_em_stats_get,
 173         .stats_reset          = eth_em_stats_reset,
 174         .dev_infos_get        = eth_em_infos_get,
 175         .mtu_set              = eth_em_mtu_set,
 176         .vlan_filter_set      = eth_em_vlan_filter_set,
 177         .vlan_offload_set     = eth_em_vlan_offload_set,
 178         .rx_queue_setup       = eth_em_rx_queue_setup,
 179         .rx_queue_release     = eth_em_rx_queue_release,
 180         .rx_queue_count       = eth_em_rx_queue_count,
 181         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 182         .rx_descriptor_status = eth_em_rx_descriptor_status,
 183         .tx_descriptor_status = eth_em_tx_descriptor_status,
 184         .tx_queue_setup       = eth_em_tx_queue_setup,
 185         .tx_queue_release     = eth_em_tx_queue_release,
 186         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 187         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 188         .dev_led_on           = eth_em_led_on,
 189         .dev_led_off          = eth_em_led_off,
 190         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 191         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 192         .mac_addr_add         = eth_em_rar_set,
 193         .mac_addr_remove      = eth_em_rar_clear,
 194         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 195         .rxq_info_get         = em_rxq_info_get,
 196         .txq_info_get         = em_txq_info_get,
 197 };
 198
 199
 200 /**
 201  *  eth_em_dev_is_ich8 - Check for ICH8 device
 202  *  @hw: pointer to the HW structure
 203  *
 204  *  return TRUE for ICH8, otherwise FALSE
 205  **/
 206 static bool
 207 eth_em_dev_is_ich8(struct e1000_hw *hw)
 208 {
 209         DEBUGFUNC("eth_em_dev_is_ich8");
 210
 211         switch (hw->device_id) {
 212         case E1000_DEV_ID_PCH2_LV_LM:
 213         case E1000_DEV_ID_PCH_LPT_I217_LM:
 214         case E1000_DEV_ID_PCH_LPT_I217_V:
 215         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 216         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 217         case E1000_DEV_ID_PCH_I218_V2:
 218         case E1000_DEV_ID_PCH_I218_LM2:
 219         case E1000_DEV_ID_PCH_I218_V3:
 220         case E1000_DEV_ID_PCH_I218_LM3:
 221         case E1000_DEV_ID_PCH_SPT_I219_LM:
 222         case E1000_DEV_ID_PCH_SPT_I219_V:
 223         case E1000_DEV_ID_PCH_SPT_I219_LM2:
 224         case E1000_DEV_ID_PCH_SPT_I219_V2:
 225         case E1000_DEV_ID_PCH_LBG_I219_LM3:
 226         case E1000_DEV_ID_PCH_SPT_I219_LM4:
 227         case E1000_DEV_ID_PCH_SPT_I219_V4:
 228         case E1000_DEV_ID_PCH_SPT_I219_LM5:
 229         case E1000_DEV_ID_PCH_SPT_I219_V5:
 230         case E1000_DEV_ID_PCH_CNP_I219_LM6:
 231         case E1000_DEV_ID_PCH_CNP_I219_V6:
 232         case E1000_DEV_ID_PCH_CNP_I219_LM7:
 233         case E1000_DEV_ID_PCH_CNP_I219_V7:
 234                 return 1;
 235         default:
 236                 return 0;
 237         }
 238 }
 239
 240 static int
 241 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 242 {
 243         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 244         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 245         struct e1000_adapter *adapter =
 246                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 247         struct e1000_hw *hw =
 248                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 249         struct e1000_vfta * shadow_vfta =
 250                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 251
 252         eth_dev->dev_ops = &eth_em_ops;
 253         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 254         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 255         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
 256
 257         /* for secondary processes, we don't initialise any further as primary
 258          * has already done this work. Only check we don't need a different
 259          * RX function */
 260         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 261                 if (eth_dev->data->scattered_rx)
 262                         eth_dev->rx_pkt_burst =
 263                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 264                 return 0;
 265         }
 266
 267         rte_eth_copy_pci_info(eth_dev, pci_dev);
 268
 269         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 270         hw->device_id = pci_dev->id.device_id;
 271         adapter->stopped = 0;
 272
 273         /* For ICH8 support we'll need to map the flash memory BAR */
 274         if (eth_em_dev_is_ich8(hw))
 275                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 276
 277         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 278                         em_hw_init(hw) != 0) {
 279                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 280                         "failed to init HW",
 281                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 282                         pci_dev->id.device_id);
 283                 return -ENODEV;
 284         }
 285
 286         /* Allocate memory for storing MAC addresses */
 287         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 288                         hw->mac.rar_entry_count, 0);
 289         if (eth_dev->data->mac_addrs == NULL) {
 290                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 291                         "store MAC addresses",
 292                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 293                 return -ENOMEM;
 294         }
 295
 296         /* Copy the permanent MAC address */
 297         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 298                 eth_dev->data->mac_addrs);
 299
 300         /* initialize the vfta */
 301         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 302
 303         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 304                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 305                      pci_dev->id.device_id);
 306
 307         rte_intr_callback_register(intr_handle,
 308                                    eth_em_interrupt_handler, eth_dev);
 309
 310         return 0;
 311 }
 312
 313 static int
 314 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 315 {
 316         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 317         struct e1000_adapter *adapter =
 318                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 319         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 320
 321         PMD_INIT_FUNC_TRACE();
 322
 323         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 324                 return -EPERM;
 325
 326         if (adapter->stopped == 0)
 327                 eth_em_close(eth_dev);
 328
 329         eth_dev->dev_ops = NULL;
 330         eth_dev->rx_pkt_burst = NULL;
 331         eth_dev->tx_pkt_burst = NULL;
 332
 333         rte_free(eth_dev->data->mac_addrs);
 334         eth_dev->data->mac_addrs = NULL;
 335
 336         /* disable uio intr before callback unregister */
 337         rte_intr_disable(intr_handle);
 338         rte_intr_callback_unregister(intr_handle,
 339                                      eth_em_interrupt_handler, eth_dev);
 340
 341         return 0;
 342 }
 343
 344 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 345         struct rte_pci_device *pci_dev)
 346 {
 347         return rte_eth_dev_pci_generic_probe(pci_dev,
 348                 sizeof(struct e1000_adapter), eth_em_dev_init);
 349 }
 350
 351 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
 352 {
 353         return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
 354 }
 355
 356 static struct rte_pci_driver rte_em_pmd = {
 357         .id_table = pci_id_em_map,
 358         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 359                      RTE_PCI_DRV_IOVA_AS_VA,
 360         .probe = eth_em_pci_probe,
 361         .remove = eth_em_pci_remove,
 362 };
 363
 364 static int
 365 em_hw_init(struct e1000_hw *hw)
 366 {
 367         int diag;
 368
 369         diag = hw->mac.ops.init_params(hw);
 370         if (diag != 0) {
 371                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 372                 return diag;
 373         }
 374         diag = hw->nvm.ops.init_params(hw);
 375         if (diag != 0) {
 376                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 377                 return diag;
 378         }
 379         diag = hw->phy.ops.init_params(hw);
 380         if (diag != 0) {
 381                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 382                 return diag;
 383         }
 384         (void) e1000_get_bus_info(hw);
 385
 386         hw->mac.autoneg = 1;
 387         hw->phy.autoneg_wait_to_complete = 0;
 388         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 389
 390         e1000_init_script_state_82541(hw, TRUE);
 391         e1000_set_tbi_compatibility_82543(hw, TRUE);
 392
 393         /* Copper options */
 394         if (hw->phy.media_type == e1000_media_type_copper) {
 395                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 396                 hw->phy.disable_polarity_correction = 0;
 397                 hw->phy.ms_type = e1000_ms_hw_default;
 398         }
 399
 400         /*
 401          * Start from a known state, this is important in reading the nvm
 402          * and mac from that.
 403          */
 404         e1000_reset_hw(hw);
 405
 406         /* Make sure we have a good EEPROM before we read from it */
 407         if (e1000_validate_nvm_checksum(hw) < 0) {
 408                 /*
 409                  * Some PCI-E parts fail the first check due to
 410                  * the link being in sleep state, call it again,
 411                  * if it fails a second time its a real issue.
 412                  */
 413                 diag = e1000_validate_nvm_checksum(hw);
 414                 if (diag < 0) {
 415                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 416                         goto error;
 417                 }
 418         }
 419
 420         /* Read the permanent MAC address out of the EEPROM */
 421         diag = e1000_read_mac_addr(hw);
 422         if (diag != 0) {
 423                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 424                 goto error;
 425         }
 426
 427         /* Now initialize the hardware */
 428         diag = em_hardware_init(hw);
 429         if (diag != 0) {
 430                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 431                 goto error;
 432         }
 433
 434         hw->mac.get_link_status = 1;
 435
 436         /* Indicate SOL/IDER usage */
 437         diag = e1000_check_reset_block(hw);
 438         if (diag < 0) {
 439                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 440                         "SOL/IDER session");
 441         }
 442         return 0;
 443
 444 error:
 445         em_hw_control_release(hw);
 446         return diag;
 447 }
 448
 449 static int
 450 eth_em_configure(struct rte_eth_dev *dev)
 451 {
 452         struct e1000_interrupt *intr =
 453                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 454         struct rte_eth_dev_info dev_info;
 455         uint64_t rx_offloads;
 456
 457         PMD_INIT_FUNC_TRACE();
 458         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 459
 460         eth_em_infos_get(dev, &dev_info);
 461         rx_offloads = dev->data->dev_conf.rxmode.offloads;
 462         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
 463                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
 464                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
 465                             rx_offloads, dev_info.rx_offload_capa);
 466                 return -ENOTSUP;
 467         }
 468
 469         PMD_INIT_FUNC_TRACE();
 470
 471         return 0;
 472 }
 473
 474 static void
 475 em_set_pba(struct e1000_hw *hw)
 476 {
 477         uint32_t pba;
 478
 479         /*
 480          * Packet Buffer Allocation (PBA)
 481          * Writing PBA sets the receive portion of the buffer
 482          * the remainder is used for the transmit buffer.
 483          * Devices before the 82547 had a Packet Buffer of 64K.
 484          * After the 82547 the buffer was reduced to 40K.
 485          */
 486         switch (hw->mac.type) {
 487                 case e1000_82547:
 488                 case e1000_82547_rev_2:
 489                 /* 82547: Total Packet Buffer is 40K */
 490                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 491                         break;
 492                 case e1000_82571:
 493                 case e1000_82572:
 494                 case e1000_80003es2lan:
 495                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 496                         break;
 497                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 498                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 499                         break;
 500                 case e1000_82574:
 501                 case e1000_82583:
 502                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 503                         break;
 504                 case e1000_ich8lan:
 505                         pba = E1000_PBA_8K;
 506                         break;
 507                 case e1000_ich9lan:
 508                 case e1000_ich10lan:
 509                         pba = E1000_PBA_10K;
 510                         break;
 511                 case e1000_pchlan:
 512                 case e1000_pch2lan:
 513                 case e1000_pch_lpt:
 514                 case e1000_pch_spt:
 515                 case e1000_pch_cnp:
 516                         pba = E1000_PBA_26K;
 517                         break;
 518                 default:
 519                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 520         }
 521
 522         E1000_WRITE_REG(hw, E1000_PBA, pba);
 523 }
 524
 525 static void
 526 eth_em_rxtx_control(struct rte_eth_dev *dev,
 527                     bool enable)
 528 {
 529         struct e1000_hw *hw =
 530                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 531         uint32_t tctl, rctl;
 532
 533         tctl = E1000_READ_REG(hw, E1000_TCTL);
 534         rctl = E1000_READ_REG(hw, E1000_RCTL);
 535         if (enable) {
 536                 /* enable Tx/Rx */
 537                 tctl |= E1000_TCTL_EN;
 538                 rctl |= E1000_RCTL_EN;
 539         } else {
 540                 /* disable Tx/Rx */
 541                 tctl &= ~E1000_TCTL_EN;
 542                 rctl &= ~E1000_RCTL_EN;
 543         }
 544         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
 545         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 546         E1000_WRITE_FLUSH(hw);
 547 }
 548
 549 static int
 550 eth_em_start(struct rte_eth_dev *dev)
 551 {
 552         struct e1000_adapter *adapter =
 553                 E1000_DEV_PRIVATE(dev->data->dev_private);
 554         struct e1000_hw *hw =
 555                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 556         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 557         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 558         int ret, mask;
 559         uint32_t intr_vector = 0;
 560         uint32_t *speeds;
 561         int num_speeds;
 562         bool autoneg;
 563
 564         PMD_INIT_FUNC_TRACE();
 565
 566         eth_em_stop(dev);
 567
 568         e1000_power_up_phy(hw);
 569
 570         /* Set default PBA value */
 571         em_set_pba(hw);
 572
 573         /* Put the address into the Receive Address Array */
 574         e1000_rar_set(hw, hw->mac.addr, 0);
 575
 576         /*
 577          * With the 82571 adapter, RAR[0] may be overwritten
 578          * when the other port is reset, we make a duplicate
 579          * in RAR[14] for that eventuality, this assures
 580          * the interface continues to function.
 581          */
 582         if (hw->mac.type == e1000_82571) {
 583                 e1000_set_laa_state_82571(hw, TRUE);
 584                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 585         }
 586
 587         /* Initialize the hardware */
 588         if (em_hardware_init(hw)) {
 589                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 590                 return -EIO;
 591         }
 592
 593         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 594
 595         /* Configure for OS presence */
 596         em_init_manageability(hw);
 597
 598         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 599                 intr_vector = dev->data->nb_rx_queues;
 600                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 601                         return -1;
 602         }
 603
 604         if (rte_intr_dp_is_en(intr_handle)) {
 605                 intr_handle->intr_vec =
 606                         rte_zmalloc("intr_vec",
 607                                         dev->data->nb_rx_queues * sizeof(int), 0);
 608                 if (intr_handle->intr_vec == NULL) {
 609                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 610                                                 " intr_vec", dev->data->nb_rx_queues);
 611                         return -ENOMEM;
 612                 }
 613
 614                 /* enable rx interrupt */
 615                 em_rxq_intr_enable(hw);
 616         }
 617
 618         eth_em_tx_init(dev);
 619
 620         ret = eth_em_rx_init(dev);
 621         if (ret) {
 622                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 623                 em_dev_clear_queues(dev);
 624                 return ret;
 625         }
 626
 627         e1000_clear_hw_cntrs_base_generic(hw);
 628
 629         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 630                         ETH_VLAN_EXTEND_MASK;
 631         ret = eth_em_vlan_offload_set(dev, mask);
 632         if (ret) {
 633                 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
 634                 em_dev_clear_queues(dev);
 635                 return ret;
 636         }
 637
 638         /* Set Interrupt Throttling Rate to maximum allowed value. */
 639         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 640
 641         /* Setup link speed and duplex */
 642         speeds = &dev->data->dev_conf.link_speeds;
 643         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 644                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 645                 hw->mac.autoneg = 1;
 646         } else {
 647                 num_speeds = 0;
 648                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 649
 650                 /* Reset */
 651                 hw->phy.autoneg_advertised = 0;
 652
 653                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 654                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 655                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 656                         num_speeds = -1;
 657                         goto error_invalid_config;
 658                 }
 659                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 660                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 661                         num_speeds++;
 662                 }
 663                 if (*speeds & ETH_LINK_SPEED_10M) {
 664                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 665                         num_speeds++;
 666                 }
 667                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 668                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 669                         num_speeds++;
 670                 }
 671                 if (*speeds & ETH_LINK_SPEED_100M) {
 672                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 673                         num_speeds++;
 674                 }
 675                 if (*speeds & ETH_LINK_SPEED_1G) {
 676                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 677                         num_speeds++;
 678                 }
 679                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 680                         goto error_invalid_config;
 681
 682                 /* Set/reset the mac.autoneg based on the link speed,
 683                  * fixed or not
 684                  */
 685                 if (!autoneg) {
 686                         hw->mac.autoneg = 0;
 687                         hw->mac.forced_speed_duplex =
 688                                         hw->phy.autoneg_advertised;
 689                 } else {
 690                         hw->mac.autoneg = 1;
 691                 }
 692         }
 693
 694         e1000_setup_link(hw);
 695
 696         if (rte_intr_allow_others(intr_handle)) {
 697                 /* check if lsc interrupt is enabled */
 698                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 699                         ret = eth_em_interrupt_setup(dev);
 700                         if (ret) {
 701                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 702                                 em_dev_clear_queues(dev);
 703                                 return ret;
 704                         }
 705                 }
 706         } else {
 707                 rte_intr_callback_unregister(intr_handle,
 708                                                 eth_em_interrupt_handler,
 709                                                 (void *)dev);
 710                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 711                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 712                                      " no intr multiplexn");
 713         }
 714         /* check if rxq interrupt is enabled */
 715         if (dev->data->dev_conf.intr_conf.rxq != 0)
 716                 eth_em_rxq_interrupt_setup(dev);
 717
 718         rte_intr_enable(intr_handle);
 719
 720         adapter->stopped = 0;
 721
 722         eth_em_rxtx_control(dev, true);
 723         eth_em_link_update(dev, 0);
 724
 725         PMD_INIT_LOG(DEBUG, "<<");
 726
 727         return 0;
 728
 729 error_invalid_config:
 730         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 731                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 732         em_dev_clear_queues(dev);
 733         return -EINVAL;
 734 }
 735
 736 /*********************************************************************
 737  *
 738  *  This routine disables all traffic on the adapter by issuing a
 739  *  global reset on the MAC.
 740  *
 741  **********************************************************************/
 742 static void
 743 eth_em_stop(struct rte_eth_dev *dev)
 744 {
 745         struct rte_eth_link link;
 746         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 747         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 748         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 749
 750         eth_em_rxtx_control(dev, false);
 751         em_rxq_intr_disable(hw);
 752         em_lsc_intr_disable(hw);
 753
 754         e1000_reset_hw(hw);
 755         if (hw->mac.type >= e1000_82544)
 756                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 757
 758         /* Power down the phy. Needed to make the link go down */
 759         e1000_power_down_phy(hw);
 760
 761         em_dev_clear_queues(dev);
 762
 763         /* clear the recorded link status */
 764         memset(&link, 0, sizeof(link));
 765         rte_eth_linkstatus_set(dev, &link);
 766
 767         if (!rte_intr_allow_others(intr_handle))
 768                 /* resume to the default handler */
 769                 rte_intr_callback_register(intr_handle,
 770                                            eth_em_interrupt_handler,
 771                                            (void *)dev);
 772
 773         /* Clean datapath event and queue/vec mapping */
 774         rte_intr_efd_disable(intr_handle);
 775         if (intr_handle->intr_vec != NULL) {
 776                 rte_free(intr_handle->intr_vec);
 777                 intr_handle->intr_vec = NULL;
 778         }
 779 }
 780
 781 static void
 782 eth_em_close(struct rte_eth_dev *dev)
 783 {
 784         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 785         struct e1000_adapter *adapter =
 786                 E1000_DEV_PRIVATE(dev->data->dev_private);
 787
 788         eth_em_stop(dev);
 789         adapter->stopped = 1;
 790         em_dev_free_queues(dev);
 791         e1000_phy_hw_reset(hw);
 792         em_release_manageability(hw);
 793         em_hw_control_release(hw);
 794 }
 795
 796 static int
 797 em_get_rx_buffer_size(struct e1000_hw *hw)
 798 {
 799         uint32_t rx_buf_size;
 800
 801         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 802         return rx_buf_size;
 803 }
 804
 805 /*********************************************************************
 806  *
 807  *  Initialize the hardware
 808  *
 809  **********************************************************************/
 810 static int
 811 em_hardware_init(struct e1000_hw *hw)
 812 {
 813         uint32_t rx_buf_size;
 814         int diag;
 815
 816         /* Issue a global reset */
 817         e1000_reset_hw(hw);
 818
 819         /* Let the firmware know the OS is in control */
 820         em_hw_control_acquire(hw);
 821
 822         /*
 823          * These parameters control the automatic generation (Tx) and
 824          * response (Rx) to Ethernet PAUSE frames.
 825          * - High water mark should allow for at least two standard size (1518)
 826          *   frames to be received after sending an XOFF.
 827          * - Low water mark works best when it is very near the high water mark.
 828          *   This allows the receiver to restart by sending XON when it has
 829          *   drained a bit. Here we use an arbitrary value of 1500 which will
 830          *   restart after one full frame is pulled from the buffer. There
 831          *   could be several smaller frames in the buffer and if so they will
 832          *   not trigger the XON until their total number reduces the buffer
 833          *   by 1500.
 834          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 835          */
 836         rx_buf_size = em_get_rx_buffer_size(hw);
 837
 838         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 839         hw->fc.low_water = hw->fc.high_water - 1500;
 840
 841         if (hw->mac.type == e1000_80003es2lan)
 842                 hw->fc.pause_time = UINT16_MAX;
 843         else
 844                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 845
 846         hw->fc.send_xon = 1;
 847
 848         /* Set Flow control, use the tunable location if sane */
 849         if (em_fc_setting <= e1000_fc_full)
 850                 hw->fc.requested_mode = em_fc_setting;
 851         else
 852                 hw->fc.requested_mode = e1000_fc_none;
 853
 854         /* Workaround: no TX flow ctrl for PCH */
 855         if (hw->mac.type == e1000_pchlan)
 856                 hw->fc.requested_mode = e1000_fc_rx_pause;
 857
 858         /* Override - settings for PCH2LAN, ya its magic :) */
 859         if (hw->mac.type == e1000_pch2lan) {
 860                 hw->fc.high_water = 0x5C20;
 861                 hw->fc.low_water = 0x5048;
 862                 hw->fc.pause_time = 0x0650;
 863                 hw->fc.refresh_time = 0x0400;
 864         } else if (hw->mac.type == e1000_pch_lpt ||
 865                    hw->mac.type == e1000_pch_spt ||
 866                    hw->mac.type == e1000_pch_cnp) {
 867                 hw->fc.requested_mode = e1000_fc_full;
 868         }
 869
 870         diag = e1000_init_hw(hw);
 871         if (diag < 0)
 872                 return diag;
 873         e1000_check_for_link(hw);
 874         return 0;
 875 }
 876
 877 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 878 static int
 879 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 880 {
 881         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 882         struct e1000_hw_stats *stats =
 883                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 884         int pause_frames;
 885
 886         if(hw->phy.media_type == e1000_media_type_copper ||
 887                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 888                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 889                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 890         }
 891
 892         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 893         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 894         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 895         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 896
 897         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 898         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 899         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 900         stats->dc += E1000_READ_REG(hw, E1000_DC);
 901         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 902         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 903         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 904
 905         /*
 906          * For watchdog management we need to know if we have been
 907          * paused during the last interval, so capture that here.
 908          */
 909         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 910         stats->xoffrxc += pause_frames;
 911         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 912         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 913         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 914         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 915         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 916         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 917         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 918         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 919         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 920         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 921         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 922         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 923
 924         /*
 925          * For the 64-bit byte counters the low dword must be read first.
 926          * Both registers clear on the read of the high dword.
 927          */
 928
 929         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 930         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 931         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 932         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 933
 934         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 935         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 936         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 937         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 938         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 939
 940         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 941         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 942
 943         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 944         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 945         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 946         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 947         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 948         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 949         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 950         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 951         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 952         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 953
 954         /* Interrupt Counts */
 955
 956         if (hw->mac.type >= e1000_82571) {
 957                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 958                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 959                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 960                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 961                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 962                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 963                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 964                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 965                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 966         }
 967
 968         if (hw->mac.type >= e1000_82543) {
 969                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 970                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 971                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 972                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 973                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 974                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 975         }
 976
 977         if (rte_stats == NULL)
 978                 return -EINVAL;
 979
 980         /* Rx Errors */
 981         rte_stats->imissed = stats->mpc;
 982         rte_stats->ierrors = stats->crcerrs +
 983                              stats->rlec + stats->ruc + stats->roc +
 984                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 985
 986         /* Tx Errors */
 987         rte_stats->oerrors = stats->ecol + stats->latecol;
 988
 989         rte_stats->ipackets = stats->gprc;
 990         rte_stats->opackets = stats->gptc;
 991         rte_stats->ibytes   = stats->gorc;
 992         rte_stats->obytes   = stats->gotc;
 993         return 0;
 994 }
 995
 996 static void
 997 eth_em_stats_reset(struct rte_eth_dev *dev)
 998 {
 999         struct e1000_hw_stats *hw_stats =
1000                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1001
1002         /* HW registers are cleared on read */
1003         eth_em_stats_get(dev, NULL);
1004
1005         /* Reset software totals */
1006         memset(hw_stats, 0, sizeof(*hw_stats));
1007 }
1008
1009 static int
1010 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1011 {
1012         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1013         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1014         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1015
1016         em_rxq_intr_enable(hw);
1017         rte_intr_enable(intr_handle);
1018
1019         return 0;
1020 }
1021
1022 static int
1023 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1024 {
1025         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1026
1027         em_rxq_intr_disable(hw);
1028
1029         return 0;
1030 }
1031
1032 uint32_t
1033 em_get_max_pktlen(struct rte_eth_dev *dev)
1034 {
1035         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1036
1037         switch (hw->mac.type) {
1038         case e1000_82571:
1039         case e1000_82572:
1040         case e1000_ich9lan:
1041         case e1000_ich10lan:
1042         case e1000_pch2lan:
1043         case e1000_pch_lpt:
1044         case e1000_pch_spt:
1045         case e1000_pch_cnp:
1046         case e1000_82574:
1047         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1048         case e1000_82583:
1049                 return 0x2412;
1050         case e1000_pchlan:
1051                 return 0x1000;
1052         /* Adapters that do not support jumbo frames */
1053         case e1000_ich8lan:
1054                 return ETHER_MAX_LEN;
1055         default:
1056                 return MAX_JUMBO_FRAME_SIZE;
1057         }
1058 }
1059
1060 static void
1061 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1062 {
1063         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1064
1065         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1066         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1067         dev_info->max_rx_pktlen = em_get_max_pktlen(dev);
1068         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1069         dev_info->tx_offload_capa =
1070                 DEV_TX_OFFLOAD_VLAN_INSERT |
1071                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1072                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1073                 DEV_TX_OFFLOAD_TCP_CKSUM;
1074
1075         /*
1076          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1077          * Unfortunatelly, all these nics have just one TX context.
1078          * So we have few choises for TX:
1079          * - Use just one TX queue.
1080          * - Allow cksum offload only for one TX queue.
1081          * - Don't allow TX cksum offload at all.
1082          * For now, option #1 was chosen.
1083          * To use second RX queue we have to use extended RX descriptor
1084          * (Multiple Receive Queues are mutually exclusive with UDP
1085          * fragmentation and are not supported when a legacy receive
1086          * descriptor format is used).
1087          * Which means separate RX routinies - as legacy nics (82540, 82545)
1088          * don't support extended RXD.
1089          * To avoid it we support just one RX queue for now (no RSS).
1090          */
1091
1092         dev_info->max_rx_queues = 1;
1093         dev_info->max_tx_queues = 1;
1094
1095         dev_info->rx_queue_offload_capa = em_get_rx_queue_offloads_capa(dev);
1096         dev_info->rx_offload_capa = em_get_rx_port_offloads_capa(dev) |
1097                                     dev_info->rx_queue_offload_capa;
1098
1099         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1100                 .nb_max = E1000_MAX_RING_DESC,
1101                 .nb_min = E1000_MIN_RING_DESC,
1102                 .nb_align = EM_RXD_ALIGN,
1103         };
1104
1105         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1106                 .nb_max = E1000_MAX_RING_DESC,
1107                 .nb_min = E1000_MIN_RING_DESC,
1108                 .nb_align = EM_TXD_ALIGN,
1109                 .nb_seg_max = EM_TX_MAX_SEG,
1110                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1111         };
1112
1113         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1114                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1115                         ETH_LINK_SPEED_1G;
1116 }
1117
1118 /* return 0 means link status changed, -1 means not changed */
1119 static int
1120 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1121 {
1122         struct e1000_hw *hw =
1123                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1124         struct rte_eth_link link;
1125         int link_check, count;
1126
1127         link_check = 0;
1128         hw->mac.get_link_status = 1;
1129
1130         /* possible wait-to-complete in up to 9 seconds */
1131         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1132                 /* Read the real link status */
1133                 switch (hw->phy.media_type) {
1134                 case e1000_media_type_copper:
1135                         /* Do the work to read phy */
1136                         e1000_check_for_link(hw);
1137                         link_check = !hw->mac.get_link_status;
1138                         break;
1139
1140                 case e1000_media_type_fiber:
1141                         e1000_check_for_link(hw);
1142                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1143                                         E1000_STATUS_LU);
1144                         break;
1145
1146                 case e1000_media_type_internal_serdes:
1147                         e1000_check_for_link(hw);
1148                         link_check = hw->mac.serdes_has_link;
1149                         break;
1150
1151                 default:
1152                         break;
1153                 }
1154                 if (link_check || wait_to_complete == 0)
1155                         break;
1156                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1157         }
1158         memset(&link, 0, sizeof(link));
1159
1160         /* Now we check if a transition has happened */
1161         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1162                 uint16_t duplex, speed;
1163                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1164                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1165                                 ETH_LINK_FULL_DUPLEX :
1166                                 ETH_LINK_HALF_DUPLEX;
1167                 link.link_speed = speed;
1168                 link.link_status = ETH_LINK_UP;
1169                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1170                                 ETH_LINK_SPEED_FIXED);
1171         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1172                 link.link_speed = 0;
1173                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1174                 link.link_status = ETH_LINK_DOWN;
1175                 link.link_autoneg = ETH_LINK_FIXED;
1176         }
1177
1178         return rte_eth_linkstatus_set(dev, &link);
1179 }
1180
1181 /*
1182  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1183  * For ASF and Pass Through versions of f/w this means
1184  * that the driver is loaded. For AMT version type f/w
1185  * this means that the network i/f is open.
1186  */
1187 static void
1188 em_hw_control_acquire(struct e1000_hw *hw)
1189 {
1190         uint32_t ctrl_ext, swsm;
1191
1192         /* Let firmware know the driver has taken over */
1193         if (hw->mac.type == e1000_82573) {
1194                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1195                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1196
1197         } else {
1198                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1199                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1200                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1201         }
1202 }
1203
1204 /*
1205  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1206  * For ASF and Pass Through versions of f/w this means that the
1207  * driver is no longer loaded. For AMT versions of the
1208  * f/w this means that the network i/f is closed.
1209  */
1210 static void
1211 em_hw_control_release(struct e1000_hw *hw)
1212 {
1213         uint32_t ctrl_ext, swsm;
1214
1215         /* Let firmware taken over control of h/w */
1216         if (hw->mac.type == e1000_82573) {
1217                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1218                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1219         } else {
1220                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1221                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1222                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1223         }
1224 }
1225
1226 /*
1227  * Bit of a misnomer, what this really means is
1228  * to enable OS management of the system... aka
1229  * to disable special hardware management features.
1230  */
1231 static void
1232 em_init_manageability(struct e1000_hw *hw)
1233 {
1234         if (e1000_enable_mng_pass_thru(hw)) {
1235                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1236                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1237
1238                 /* disable hardware interception of ARP */
1239                 manc &= ~(E1000_MANC_ARP_EN);
1240
1241                 /* enable receiving management packets to the host */
1242                 manc |= E1000_MANC_EN_MNG2HOST;
1243                 manc2h |= 1 << 5;  /* Mng Port 623 */
1244                 manc2h |= 1 << 6;  /* Mng Port 664 */
1245                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1246                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1247         }
1248 }
1249
1250 /*
1251  * Give control back to hardware management
1252  * controller if there is one.
1253  */
1254 static void
1255 em_release_manageability(struct e1000_hw *hw)
1256 {
1257         uint32_t manc;
1258
1259         if (e1000_enable_mng_pass_thru(hw)) {
1260                 manc = E1000_READ_REG(hw, E1000_MANC);
1261
1262                 /* re-enable hardware interception of ARP */
1263                 manc |= E1000_MANC_ARP_EN;
1264                 manc &= ~E1000_MANC_EN_MNG2HOST;
1265
1266                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1267         }
1268 }
1269
1270 static void
1271 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1272 {
1273         struct e1000_hw *hw =
1274                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1275         uint32_t rctl;
1276
1277         rctl = E1000_READ_REG(hw, E1000_RCTL);
1278         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1279         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1280 }
1281
1282 static void
1283 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1284 {
1285         struct e1000_hw *hw =
1286                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1287         uint32_t rctl;
1288
1289         rctl = E1000_READ_REG(hw, E1000_RCTL);
1290         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1291         if (dev->data->all_multicast == 1)
1292                 rctl |= E1000_RCTL_MPE;
1293         else
1294                 rctl &= (~E1000_RCTL_MPE);
1295         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1296 }
1297
1298 static void
1299 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1300 {
1301         struct e1000_hw *hw =
1302                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1303         uint32_t rctl;
1304
1305         rctl = E1000_READ_REG(hw, E1000_RCTL);
1306         rctl |= E1000_RCTL_MPE;
1307         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1308 }
1309
1310 static void
1311 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1312 {
1313         struct e1000_hw *hw =
1314                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1315         uint32_t rctl;
1316
1317         if (dev->data->promiscuous == 1)
1318                 return; /* must remain in all_multicast mode */
1319         rctl = E1000_READ_REG(hw, E1000_RCTL);
1320         rctl &= (~E1000_RCTL_MPE);
1321         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1322 }
1323
1324 static int
1325 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1326 {
1327         struct e1000_hw *hw =
1328                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1329         struct e1000_vfta * shadow_vfta =
1330                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1331         uint32_t vfta;
1332         uint32_t vid_idx;
1333         uint32_t vid_bit;
1334
1335         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1336                               E1000_VFTA_ENTRY_MASK);
1337         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1338         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1339         if (on)
1340                 vfta |= vid_bit;
1341         else
1342                 vfta &= ~vid_bit;
1343         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1344
1345         /* update local VFTA copy */
1346         shadow_vfta->vfta[vid_idx] = vfta;
1347
1348         return 0;
1349 }
1350
1351 static void
1352 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1353 {
1354         struct e1000_hw *hw =
1355                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1356         uint32_t reg;
1357
1358         /* Filter Table Disable */
1359         reg = E1000_READ_REG(hw, E1000_RCTL);
1360         reg &= ~E1000_RCTL_CFIEN;
1361         reg &= ~E1000_RCTL_VFE;
1362         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1363 }
1364
1365 static void
1366 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1367 {
1368         struct e1000_hw *hw =
1369                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1370         struct e1000_vfta * shadow_vfta =
1371                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1372         uint32_t reg;
1373         int i;
1374
1375         /* Filter Table Enable, CFI not used for packet acceptance */
1376         reg = E1000_READ_REG(hw, E1000_RCTL);
1377         reg &= ~E1000_RCTL_CFIEN;
1378         reg |= E1000_RCTL_VFE;
1379         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1380
1381         /* restore vfta from local copy */
1382         for (i = 0; i < IGB_VFTA_SIZE; i++)
1383                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1384 }
1385
1386 static void
1387 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1388 {
1389         struct e1000_hw *hw =
1390                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1391         uint32_t reg;
1392
1393         /* VLAN Mode Disable */
1394         reg = E1000_READ_REG(hw, E1000_CTRL);
1395         reg &= ~E1000_CTRL_VME;
1396         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1397
1398 }
1399
1400 static void
1401 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1402 {
1403         struct e1000_hw *hw =
1404                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1405         uint32_t reg;
1406
1407         /* VLAN Mode Enable */
1408         reg = E1000_READ_REG(hw, E1000_CTRL);
1409         reg |= E1000_CTRL_VME;
1410         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1411 }
1412
1413 static int
1414 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1415 {
1416         struct rte_eth_rxmode *rxmode;
1417
1418         rxmode = &dev->data->dev_conf.rxmode;
1419         if(mask & ETH_VLAN_STRIP_MASK){
1420                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1421                         em_vlan_hw_strip_enable(dev);
1422                 else
1423                         em_vlan_hw_strip_disable(dev);
1424         }
1425
1426         if(mask & ETH_VLAN_FILTER_MASK){
1427                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1428                         em_vlan_hw_filter_enable(dev);
1429                 else
1430                         em_vlan_hw_filter_disable(dev);
1431         }
1432
1433         return 0;
1434 }
1435
1436 /*
1437  * It enables the interrupt mask and then enable the interrupt.
1438  *
1439  * @param dev
1440  *  Pointer to struct rte_eth_dev.
1441  *
1442  * @return
1443  *  - On success, zero.
1444  *  - On failure, a negative value.
1445  */
1446 static int
1447 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1448 {
1449         uint32_t regval;
1450         struct e1000_hw *hw =
1451                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1452
1453         /* clear interrupt */
1454         E1000_READ_REG(hw, E1000_ICR);
1455         regval = E1000_READ_REG(hw, E1000_IMS);
1456         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1457         return 0;
1458 }
1459
1460 /*
1461  * It clears the interrupt causes and enables the interrupt.
1462  * It will be called once only during nic initialized.
1463  *
1464  * @param dev
1465  *  Pointer to struct rte_eth_dev.
1466  *
1467  * @return
1468  *  - On success, zero.
1469  *  - On failure, a negative value.
1470  */
1471 static int
1472 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1473 {
1474         struct e1000_hw *hw =
1475         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1476
1477         E1000_READ_REG(hw, E1000_ICR);
1478         em_rxq_intr_enable(hw);
1479         return 0;
1480 }
1481
1482 /*
1483  * It enable receive packet interrupt.
1484  * @param hw
1485  * Pointer to struct e1000_hw
1486  *
1487  * @return
1488  */
1489 static void
1490 em_rxq_intr_enable(struct e1000_hw *hw)
1491 {
1492         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1493         E1000_WRITE_FLUSH(hw);
1494 }
1495
1496 /*
1497  * It disabled lsc interrupt.
1498  * @param hw
1499  * Pointer to struct e1000_hw
1500  *
1501  * @return
1502  */
1503 static void
1504 em_lsc_intr_disable(struct e1000_hw *hw)
1505 {
1506         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1507         E1000_WRITE_FLUSH(hw);
1508 }
1509
1510 /*
1511  * It disabled receive packet interrupt.
1512  * @param hw
1513  * Pointer to struct e1000_hw
1514  *
1515  * @return
1516  */
1517 static void
1518 em_rxq_intr_disable(struct e1000_hw *hw)
1519 {
1520         E1000_READ_REG(hw, E1000_ICR);
1521         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1522         E1000_WRITE_FLUSH(hw);
1523 }
1524
1525 /*
1526  * It reads ICR and gets interrupt causes, check it and set a bit flag
1527  * to update link status.
1528  *
1529  * @param dev
1530  *  Pointer to struct rte_eth_dev.
1531  *
1532  * @return
1533  *  - On success, zero.
1534  *  - On failure, a negative value.
1535  */
1536 static int
1537 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1538 {
1539         uint32_t icr;
1540         struct e1000_hw *hw =
1541                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1542         struct e1000_interrupt *intr =
1543                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1544
1545         /* read-on-clear nic registers here */
1546         icr = E1000_READ_REG(hw, E1000_ICR);
1547         if (icr & E1000_ICR_LSC) {
1548                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1549         }
1550
1551         return 0;
1552 }
1553
1554 /*
1555  * It executes link_update after knowing an interrupt is prsent.
1556  *
1557  * @param dev
1558  *  Pointer to struct rte_eth_dev.
1559  *
1560  * @return
1561  *  - On success, zero.
1562  *  - On failure, a negative value.
1563  */
1564 static int
1565 eth_em_interrupt_action(struct rte_eth_dev *dev,
1566                         struct rte_intr_handle *intr_handle)
1567 {
1568         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1569         struct e1000_hw *hw =
1570                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1571         struct e1000_interrupt *intr =
1572                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1573         struct rte_eth_link link;
1574         int ret;
1575
1576         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1577                 return -1;
1578
1579         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1580         rte_intr_enable(intr_handle);
1581
1582         /* set get_link_status to check register later */
1583         hw->mac.get_link_status = 1;
1584         ret = eth_em_link_update(dev, 0);
1585
1586         /* check if link has changed */
1587         if (ret < 0)
1588                 return 0;
1589
1590         rte_eth_linkstatus_get(dev, &link);
1591
1592         if (link.link_status) {
1593                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1594                              dev->data->port_id, link.link_speed,
1595                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1596                              "full-duplex" : "half-duplex");
1597         } else {
1598                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1599         }
1600         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1601                      pci_dev->addr.domain, pci_dev->addr.bus,
1602                      pci_dev->addr.devid, pci_dev->addr.function);
1603
1604         return 0;
1605 }
1606
1607 /**
1608  * Interrupt handler which shall be registered at first.
1609  *
1610  * @param handle
1611  *  Pointer to interrupt handle.
1612  * @param param
1613  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1614  *
1615  * @return
1616  *  void
1617  */
1618 static void
1619 eth_em_interrupt_handler(void *param)
1620 {
1621         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1622
1623         eth_em_interrupt_get_status(dev);
1624         eth_em_interrupt_action(dev, dev->intr_handle);
1625         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1626 }
1627
1628 static int
1629 eth_em_led_on(struct rte_eth_dev *dev)
1630 {
1631         struct e1000_hw *hw;
1632
1633         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1634         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1635 }
1636
1637 static int
1638 eth_em_led_off(struct rte_eth_dev *dev)
1639 {
1640         struct e1000_hw *hw;
1641
1642         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1643         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1644 }
1645
1646 static int
1647 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1648 {
1649         struct e1000_hw *hw;
1650         uint32_t ctrl;
1651         int tx_pause;
1652         int rx_pause;
1653
1654         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655         fc_conf->pause_time = hw->fc.pause_time;
1656         fc_conf->high_water = hw->fc.high_water;
1657         fc_conf->low_water = hw->fc.low_water;
1658         fc_conf->send_xon = hw->fc.send_xon;
1659         fc_conf->autoneg = hw->mac.autoneg;
1660
1661         /*
1662          * Return rx_pause and tx_pause status according to actual setting of
1663          * the TFCE and RFCE bits in the CTRL register.
1664          */
1665         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1666         if (ctrl & E1000_CTRL_TFCE)
1667                 tx_pause = 1;
1668         else
1669                 tx_pause = 0;
1670
1671         if (ctrl & E1000_CTRL_RFCE)
1672                 rx_pause = 1;
1673         else
1674                 rx_pause = 0;
1675
1676         if (rx_pause && tx_pause)
1677                 fc_conf->mode = RTE_FC_FULL;
1678         else if (rx_pause)
1679                 fc_conf->mode = RTE_FC_RX_PAUSE;
1680         else if (tx_pause)
1681                 fc_conf->mode = RTE_FC_TX_PAUSE;
1682         else
1683                 fc_conf->mode = RTE_FC_NONE;
1684
1685         return 0;
1686 }
1687
1688 static int
1689 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1690 {
1691         struct e1000_hw *hw;
1692         int err;
1693         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1694                 e1000_fc_none,
1695                 e1000_fc_rx_pause,
1696                 e1000_fc_tx_pause,
1697                 e1000_fc_full
1698         };
1699         uint32_t rx_buf_size;
1700         uint32_t max_high_water;
1701         uint32_t rctl;
1702
1703         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704         if (fc_conf->autoneg != hw->mac.autoneg)
1705                 return -ENOTSUP;
1706         rx_buf_size = em_get_rx_buffer_size(hw);
1707         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1708
1709         /* At least reserve one Ethernet frame for watermark */
1710         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1711         if ((fc_conf->high_water > max_high_water) ||
1712             (fc_conf->high_water < fc_conf->low_water)) {
1713                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1714                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1715                 return -EINVAL;
1716         }
1717
1718         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1719         hw->fc.pause_time     = fc_conf->pause_time;
1720         hw->fc.high_water     = fc_conf->high_water;
1721         hw->fc.low_water      = fc_conf->low_water;
1722         hw->fc.send_xon       = fc_conf->send_xon;
1723
1724         err = e1000_setup_link_generic(hw);
1725         if (err == E1000_SUCCESS) {
1726
1727                 /* check if we want to forward MAC frames - driver doesn't have native
1728                  * capability to do that, so we'll write the registers ourselves */
1729
1730                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1731
1732                 /* set or clear MFLCN.PMCF bit depending on configuration */
1733                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1734                         rctl |= E1000_RCTL_PMCF;
1735                 else
1736                         rctl &= ~E1000_RCTL_PMCF;
1737
1738                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1739                 E1000_WRITE_FLUSH(hw);
1740
1741                 return 0;
1742         }
1743
1744         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1745         return -EIO;
1746 }
1747
1748 static int
1749 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1750                 uint32_t index, __rte_unused uint32_t pool)
1751 {
1752         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1753
1754         return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1755 }
1756
1757 static void
1758 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1759 {
1760         uint8_t addr[ETHER_ADDR_LEN];
1761         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1762
1763         memset(addr, 0, sizeof(addr));
1764
1765         e1000_rar_set(hw, addr, index);
1766 }
1767
1768 static int
1769 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1770 {
1771         struct rte_eth_dev_info dev_info;
1772         struct e1000_hw *hw;
1773         uint32_t frame_size;
1774         uint32_t rctl;
1775
1776         eth_em_infos_get(dev, &dev_info);
1777         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1778
1779         /* check that mtu is within the allowed range */
1780         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1781                 return -EINVAL;
1782
1783         /* refuse mtu that requires the support of scattered packets when this
1784          * feature has not been enabled before. */
1785         if (!dev->data->scattered_rx &&
1786             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1787                 return -EINVAL;
1788
1789         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1790         rctl = E1000_READ_REG(hw, E1000_RCTL);
1791
1792         /* switch to jumbo mode if needed */
1793         if (frame_size > ETHER_MAX_LEN) {
1794                 dev->data->dev_conf.rxmode.offloads |=
1795                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1796                 rctl |= E1000_RCTL_LPE;
1797         } else {
1798                 dev->data->dev_conf.rxmode.offloads &=
1799                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1800                 rctl &= ~E1000_RCTL_LPE;
1801         }
1802         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1803
1804         /* update max frame size */
1805         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1806         return 0;
1807 }
1808
1809 static int
1810 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1811                         struct ether_addr *mc_addr_set,
1812                         uint32_t nb_mc_addr)
1813 {
1814         struct e1000_hw *hw;
1815
1816         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1817         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1818         return 0;
1819 }
1820
1821 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1822 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1823 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
1824
1825 RTE_INIT(e1000_init_log);
1826 static void
1827 e1000_init_log(void)
1828 {
1829         e1000_logtype_init = rte_log_register("pmd.net.e1000.init");
1830         if (e1000_logtype_init >= 0)
1831                 rte_log_set_level(e1000_logtype_init, RTE_LOG_NOTICE);
1832         e1000_logtype_driver = rte_log_register("pmd.net.e1000.driver");
1833         if (e1000_logtype_driver >= 0)
1834                 rte_log_set_level(e1000_logtype_driver, RTE_LOG_NOTICE);
1835 }