1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
15 #include <rte_interrupts.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
19 #include <rte_debug.h>
21 #include <rte_bus_pci.h>
22 #include <rte_memory.h>
23 #include <rte_memcpy.h>
24 #include <rte_memzone.h>
25 #include <rte_launch.h>
27 #include <rte_per_lcore.h>
28 #include <rte_lcore.h>
29 #include <rte_atomic.h>
30 #include <rte_branch_prediction.h>
31 #include <rte_mempool.h>
32 #include <rte_malloc.h>
34 #include <rte_ether.h>
35 #include <ethdev_driver.h>
36 #include <rte_prefetch.h>
42 #include <rte_string_fns.h>
44 #include "e1000_logs.h"
45 #include "base/e1000_api.h"
46 #include "e1000_ethdev.h"
47 #include "base/e1000_osdep.h"
49 #define E1000_TXD_VLAN_SHIFT 16
51 #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
53 #define E1000_TX_OFFLOAD_MASK ( \
60 #define E1000_TX_OFFLOAD_NOTSUP_MASK \
61 (PKT_TX_OFFLOAD_MASK ^ E1000_TX_OFFLOAD_MASK)
63 /* PCI offset for querying configuration status register */
64 #define PCI_CFG_STATUS_REG 0x06
65 #define FLUSH_DESC_REQUIRED 0x100
69 * Structure associated with each descriptor of the RX ring of a RX queue.
72 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
76 * Structure associated with each descriptor of the TX ring of a TX queue.
79 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
80 uint16_t next_id; /**< Index of next descriptor in ring. */
81 uint16_t last_id; /**< Index of last scattered descriptor. */
85 * Structure associated with each RX queue.
88 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
89 volatile struct e1000_rx_desc *rx_ring; /**< RX ring virtual address. */
90 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
91 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
92 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
93 struct em_rx_entry *sw_ring; /**< address of RX software ring. */
94 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
95 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
96 uint64_t offloads; /**< Offloads of DEV_RX_OFFLOAD_* */
97 uint16_t nb_rx_desc; /**< number of RX descriptors. */
98 uint16_t rx_tail; /**< current value of RDT register. */
99 uint16_t nb_rx_hold; /**< number of held free RX desc. */
100 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
101 uint16_t queue_id; /**< RX queue index. */
102 uint16_t port_id; /**< Device port identifier. */
103 uint8_t pthresh; /**< Prefetch threshold register. */
104 uint8_t hthresh; /**< Host threshold register. */
105 uint8_t wthresh; /**< Write-back threshold register. */
106 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
107 const struct rte_memzone *mz;
111 * Hardware context number
114 EM_CTX_0 = 0, /**< CTX0 */
115 EM_CTX_NUM = 1, /**< CTX NUM */
118 /** Offload features */
119 union em_vlan_macip {
122 uint16_t l3_len:9; /**< L3 (IP) Header Length. */
123 uint16_t l2_len:7; /**< L2 (MAC) Header Length. */
125 /**< VLAN Tag Control Identifier (CPU order). */
130 * Compare mask for vlan_macip_len.data,
131 * should be in sync with em_vlan_macip.f layout.
133 #define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - 16-bits. */
134 #define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. */
135 #define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */
136 /** MAC+IP length. */
137 #define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK)
140 * Structure to check if new context need be built
143 uint64_t flags; /**< ol_flags related to context build. */
144 uint32_t cmp_mask; /**< compare mask */
145 union em_vlan_macip hdrlen; /**< L2 and L3 header lenghts */
149 * Structure associated with each TX queue.
152 volatile struct e1000_data_desc *tx_ring; /**< TX ring address */
153 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
154 struct em_tx_entry *sw_ring; /**< virtual address of SW ring. */
155 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
156 uint16_t nb_tx_desc; /**< number of TX descriptors. */
157 uint16_t tx_tail; /**< Current value of TDT register. */
158 /**< Start freeing TX buffers if there are less free descriptors than
160 uint16_t tx_free_thresh;
161 /**< Number of TX descriptors to use before RS bit is set. */
162 uint16_t tx_rs_thresh;
163 /** Number of TX descriptors used since RS bit was set. */
165 /** Index to last TX descriptor to have been cleaned. */
166 uint16_t last_desc_cleaned;
167 /** Total number of TX descriptors ready to be allocated. */
169 uint16_t queue_id; /**< TX queue index. */
170 uint16_t port_id; /**< Device port identifier. */
171 uint8_t pthresh; /**< Prefetch threshold register. */
172 uint8_t hthresh; /**< Host threshold register. */
173 uint8_t wthresh; /**< Write-back threshold register. */
174 struct em_ctx_info ctx_cache;
175 /**< Hardware context history.*/
176 uint64_t offloads; /**< offloads of DEV_TX_OFFLOAD_* */
177 const struct rte_memzone *mz;
181 #define RTE_PMD_USE_PREFETCH
184 #ifdef RTE_PMD_USE_PREFETCH
185 #define rte_em_prefetch(p) rte_prefetch0(p)
187 #define rte_em_prefetch(p) do {} while(0)
190 #ifdef RTE_PMD_PACKET_PREFETCH
191 #define rte_packet_prefetch(p) rte_prefetch1(p)
193 #define rte_packet_prefetch(p) do {} while(0)
196 #ifndef DEFAULT_TX_FREE_THRESH
197 #define DEFAULT_TX_FREE_THRESH 32
198 #endif /* DEFAULT_TX_FREE_THRESH */
200 #ifndef DEFAULT_TX_RS_THRESH
201 #define DEFAULT_TX_RS_THRESH 32
202 #endif /* DEFAULT_TX_RS_THRESH */
205 /*********************************************************************
209 **********************************************************************/
212 * Populates TX context descriptor.
215 em_set_xmit_ctx(struct em_tx_queue* txq,
216 volatile struct e1000_context_desc *ctx_txd,
218 union em_vlan_macip hdrlen)
220 uint32_t cmp_mask, cmd_len;
221 uint16_t ipcse, l2len;
222 struct e1000_context_desc ctx;
225 cmd_len = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C;
227 l2len = hdrlen.f.l2_len;
228 ipcse = (uint16_t)(l2len + hdrlen.f.l3_len);
230 /* setup IPCS* fields */
231 ctx.lower_setup.ip_fields.ipcss = (uint8_t)l2len;
232 ctx.lower_setup.ip_fields.ipcso = (uint8_t)(l2len +
233 offsetof(struct rte_ipv4_hdr, hdr_checksum));
236 * When doing checksum or TCP segmentation with IPv6 headers,
237 * IPCSE field should be set t0 0.
239 if (flags & PKT_TX_IP_CKSUM) {
240 ctx.lower_setup.ip_fields.ipcse =
241 (uint16_t)rte_cpu_to_le_16(ipcse - 1);
242 cmd_len |= E1000_TXD_CMD_IP;
243 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
245 ctx.lower_setup.ip_fields.ipcse = 0;
248 /* setup TUCS* fields */
249 ctx.upper_setup.tcp_fields.tucss = (uint8_t)ipcse;
250 ctx.upper_setup.tcp_fields.tucse = 0;
252 switch (flags & PKT_TX_L4_MASK) {
253 case PKT_TX_UDP_CKSUM:
254 ctx.upper_setup.tcp_fields.tucso = (uint8_t)(ipcse +
255 offsetof(struct rte_udp_hdr, dgram_cksum));
256 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
258 case PKT_TX_TCP_CKSUM:
259 ctx.upper_setup.tcp_fields.tucso = (uint8_t)(ipcse +
260 offsetof(struct rte_tcp_hdr, cksum));
261 cmd_len |= E1000_TXD_CMD_TCP;
262 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
265 ctx.upper_setup.tcp_fields.tucso = 0;
268 ctx.cmd_and_length = rte_cpu_to_le_32(cmd_len);
269 ctx.tcp_seg_setup.data = 0;
273 txq->ctx_cache.flags = flags;
274 txq->ctx_cache.cmp_mask = cmp_mask;
275 txq->ctx_cache.hdrlen = hdrlen;
279 * Check which hardware context can be used. Use the existing match
280 * or create a new context descriptor.
282 static inline uint32_t
283 what_ctx_update(struct em_tx_queue *txq, uint64_t flags,
284 union em_vlan_macip hdrlen)
286 /* If match with the current context */
287 if (likely (txq->ctx_cache.flags == flags &&
288 ((txq->ctx_cache.hdrlen.data ^ hdrlen.data) &
289 txq->ctx_cache.cmp_mask) == 0))
296 /* Reset transmit descriptors after they have been used */
298 em_xmit_cleanup(struct em_tx_queue *txq)
300 struct em_tx_entry *sw_ring = txq->sw_ring;
301 volatile struct e1000_data_desc *txr = txq->tx_ring;
302 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
303 uint16_t nb_tx_desc = txq->nb_tx_desc;
304 uint16_t desc_to_clean_to;
305 uint16_t nb_tx_to_clean;
307 /* Determine the last descriptor needing to be cleaned */
308 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
309 if (desc_to_clean_to >= nb_tx_desc)
310 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
312 /* Check to make sure the last descriptor to clean is done */
313 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
314 if (! (txr[desc_to_clean_to].upper.fields.status & E1000_TXD_STAT_DD))
317 "TX descriptor %4u is not done"
318 "(port=%d queue=%d)", desc_to_clean_to,
319 txq->port_id, txq->queue_id);
320 /* Failed to clean any descriptors, better luck next time */
324 /* Figure out how many descriptors will be cleaned */
325 if (last_desc_cleaned > desc_to_clean_to)
326 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
329 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
333 "Cleaning %4u TX descriptors: %4u to %4u "
334 "(port=%d queue=%d)", nb_tx_to_clean,
335 last_desc_cleaned, desc_to_clean_to, txq->port_id,
339 * The last descriptor to clean is done, so that means all the
340 * descriptors from the last descriptor that was cleaned
341 * up to the last descriptor with the RS bit set
342 * are done. Only reset the threshold descriptor.
344 txr[desc_to_clean_to].upper.fields.status = 0;
346 /* Update the txq to reflect the last descriptor that was cleaned */
347 txq->last_desc_cleaned = desc_to_clean_to;
348 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
354 static inline uint32_t
355 tx_desc_cksum_flags_to_upper(uint64_t ol_flags)
357 static const uint32_t l4_olinfo[2] = {0, E1000_TXD_POPTS_TXSM << 8};
358 static const uint32_t l3_olinfo[2] = {0, E1000_TXD_POPTS_IXSM << 8};
361 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
362 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
367 eth_em_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
370 struct em_tx_queue *txq;
371 struct em_tx_entry *sw_ring;
372 struct em_tx_entry *txe, *txn;
373 volatile struct e1000_data_desc *txr;
374 volatile struct e1000_data_desc *txd;
375 struct rte_mbuf *tx_pkt;
376 struct rte_mbuf *m_seg;
377 uint64_t buf_dma_addr;
379 uint32_t cmd_type_len;
389 union em_vlan_macip hdrlen;
392 sw_ring = txq->sw_ring;
394 tx_id = txq->tx_tail;
395 txe = &sw_ring[tx_id];
397 /* Determine if the descriptor ring needs to be cleaned. */
398 if (txq->nb_tx_free < txq->tx_free_thresh)
399 em_xmit_cleanup(txq);
402 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
406 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
409 * Determine how many (if any) context descriptors
410 * are needed for offload functionality.
412 ol_flags = tx_pkt->ol_flags;
414 /* If hardware offload required */
415 tx_ol_req = (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK));
417 hdrlen.f.vlan_tci = tx_pkt->vlan_tci;
418 hdrlen.f.l2_len = tx_pkt->l2_len;
419 hdrlen.f.l3_len = tx_pkt->l3_len;
420 /* If new context to be built or reuse the exist ctx. */
421 ctx = what_ctx_update(txq, tx_ol_req, hdrlen);
423 /* Only allocate context descriptor if required*/
424 new_ctx = (ctx == EM_CTX_NUM);
428 * Keep track of how many descriptors are used this loop
429 * This will always be the number of segments + the number of
430 * Context descriptors required to transmit the packet
432 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
435 * The number of descriptors that must be allocated for a
436 * packet is the number of segments of that packet, plus 1
437 * Context Descriptor for the hardware offload, if any.
438 * Determine the last TX descriptor to allocate in the TX ring
439 * for the packet, starting from the current position (tx_id)
442 tx_last = (uint16_t) (tx_id + nb_used - 1);
445 if (tx_last >= txq->nb_tx_desc)
446 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
448 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
449 " tx_first=%u tx_last=%u",
450 (unsigned) txq->port_id,
451 (unsigned) txq->queue_id,
452 (unsigned) tx_pkt->pkt_len,
457 * Make sure there are enough TX descriptors available to
458 * transmit the entire packet.
459 * nb_used better be less than or equal to txq->tx_rs_thresh
461 while (unlikely (nb_used > txq->nb_tx_free)) {
462 PMD_TX_LOG(DEBUG, "Not enough free TX descriptors "
463 "nb_used=%4u nb_free=%4u "
464 "(port=%d queue=%d)",
465 nb_used, txq->nb_tx_free,
466 txq->port_id, txq->queue_id);
468 if (em_xmit_cleanup(txq) != 0) {
469 /* Could not clean any descriptors */
477 * By now there are enough free TX descriptors to transmit
482 * Set common flags of all TX Data Descriptors.
484 * The following bits must be set in all Data Descriptors:
485 * - E1000_TXD_DTYP_DATA
486 * - E1000_TXD_DTYP_DEXT
488 * The following bits must be set in the first Data Descriptor
489 * and are ignored in the other ones:
490 * - E1000_TXD_POPTS_IXSM
491 * - E1000_TXD_POPTS_TXSM
493 * The following bits must be set in the last Data Descriptor
494 * and are ignored in the other ones:
495 * - E1000_TXD_CMD_VLE
496 * - E1000_TXD_CMD_IFCS
498 * The following bits must only be set in the last Data
500 * - E1000_TXD_CMD_EOP
502 * The following bits can be set in any Data Descriptor, but
503 * are only set in the last Data Descriptor:
506 cmd_type_len = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
510 /* Set VLAN Tag offload fields. */
511 if (ol_flags & PKT_TX_VLAN_PKT) {
512 cmd_type_len |= E1000_TXD_CMD_VLE;
513 popts_spec = tx_pkt->vlan_tci << E1000_TXD_VLAN_SHIFT;
518 * Setup the TX Context Descriptor if required
521 volatile struct e1000_context_desc *ctx_txd;
523 ctx_txd = (volatile struct e1000_context_desc *)
526 txn = &sw_ring[txe->next_id];
527 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
529 if (txe->mbuf != NULL) {
530 rte_pktmbuf_free_seg(txe->mbuf);
534 em_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
537 txe->last_id = tx_last;
538 tx_id = txe->next_id;
543 * Setup the TX Data Descriptor,
544 * This path will go through
545 * whatever new/reuse the context descriptor
547 popts_spec |= tx_desc_cksum_flags_to_upper(ol_flags);
553 txn = &sw_ring[txe->next_id];
555 if (txe->mbuf != NULL)
556 rte_pktmbuf_free_seg(txe->mbuf);
560 * Set up Transmit Data Descriptor.
562 slen = m_seg->data_len;
563 buf_dma_addr = rte_mbuf_data_iova(m_seg);
565 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
566 txd->lower.data = rte_cpu_to_le_32(cmd_type_len | slen);
567 txd->upper.data = rte_cpu_to_le_32(popts_spec);
569 txe->last_id = tx_last;
570 tx_id = txe->next_id;
573 } while (m_seg != NULL);
576 * The last packet data descriptor needs End Of Packet (EOP)
578 cmd_type_len |= E1000_TXD_CMD_EOP;
579 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
580 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
582 /* Set RS bit only on threshold packets' last descriptor */
583 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
585 "Setting RS bit on TXD id=%4u "
586 "(port=%d queue=%d)",
587 tx_last, txq->port_id, txq->queue_id);
589 cmd_type_len |= E1000_TXD_CMD_RS;
591 /* Update txq RS bit counters */
594 txd->lower.data |= rte_cpu_to_le_32(cmd_type_len);
600 * Set the Transmit Descriptor Tail (TDT)
602 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
603 (unsigned) txq->port_id, (unsigned) txq->queue_id,
604 (unsigned) tx_id, (unsigned) nb_tx);
605 E1000_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);
606 txq->tx_tail = tx_id;
611 /*********************************************************************
615 **********************************************************************/
617 eth_em_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
623 for (i = 0; i < nb_pkts; i++) {
626 if (m->ol_flags & E1000_TX_OFFLOAD_NOTSUP_MASK) {
631 #ifdef RTE_ETHDEV_DEBUG_TX
632 ret = rte_validate_tx_offload(m);
638 ret = rte_net_intel_cksum_prepare(m);
648 /*********************************************************************
652 **********************************************************************/
654 static inline uint64_t
655 rx_desc_status_to_pkt_flags(uint32_t rx_status)
659 /* Check if VLAN present */
660 pkt_flags = ((rx_status & E1000_RXD_STAT_VP) ?
661 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED : 0);
666 static inline uint64_t
667 rx_desc_error_to_pkt_flags(uint32_t rx_error)
669 uint64_t pkt_flags = 0;
671 if (rx_error & E1000_RXD_ERR_IPE)
672 pkt_flags |= PKT_RX_IP_CKSUM_BAD;
673 if (rx_error & E1000_RXD_ERR_TCPE)
674 pkt_flags |= PKT_RX_L4_CKSUM_BAD;
679 eth_em_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
682 volatile struct e1000_rx_desc *rx_ring;
683 volatile struct e1000_rx_desc *rxdp;
684 struct em_rx_queue *rxq;
685 struct em_rx_entry *sw_ring;
686 struct em_rx_entry *rxe;
687 struct rte_mbuf *rxm;
688 struct rte_mbuf *nmb;
689 struct e1000_rx_desc rxd;
701 rx_id = rxq->rx_tail;
702 rx_ring = rxq->rx_ring;
703 sw_ring = rxq->sw_ring;
704 while (nb_rx < nb_pkts) {
706 * The order of operations here is important as the DD status
707 * bit must not be read after any other descriptor fields.
708 * rx_ring and rxdp are pointing to volatile data so the order
709 * of accesses cannot be reordered by the compiler. If they were
710 * not volatile, they could be reordered which could lead to
711 * using invalid descriptor fields when read from rxd.
713 rxdp = &rx_ring[rx_id];
714 status = rxdp->status;
715 if (! (status & E1000_RXD_STAT_DD))
722 * If the E1000_RXD_STAT_EOP flag is not set, the RX packet is
723 * likely to be invalid and to be dropped by the various
724 * validation checks performed by the network stack.
726 * Allocate a new mbuf to replenish the RX ring descriptor.
727 * If the allocation fails:
728 * - arrange for that RX descriptor to be the first one
729 * being parsed the next time the receive function is
730 * invoked [on the same queue].
732 * - Stop parsing the RX ring and return immediately.
734 * This policy do not drop the packet received in the RX
735 * descriptor for which the allocation of a new mbuf failed.
736 * Thus, it allows that packet to be later retrieved if
737 * mbuf have been freed in the mean time.
738 * As a side effect, holding RX descriptors instead of
739 * systematically giving them back to the NIC may lead to
740 * RX ring exhaustion situations.
741 * However, the NIC can gracefully prevent such situations
742 * to happen by sending specific "back-pressure" flow control
743 * frames to its peer(s).
745 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
746 "status=0x%x pkt_len=%u",
747 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
748 (unsigned) rx_id, (unsigned) status,
749 (unsigned) rte_le_to_cpu_16(rxd.length));
751 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
753 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
755 (unsigned) rxq->port_id,
756 (unsigned) rxq->queue_id);
757 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
762 rxe = &sw_ring[rx_id];
764 if (rx_id == rxq->nb_rx_desc)
767 /* Prefetch next mbuf while processing current one. */
768 rte_em_prefetch(sw_ring[rx_id].mbuf);
771 * When next RX descriptor is on a cache-line boundary,
772 * prefetch the next 4 RX descriptors and the next 8 pointers
775 if ((rx_id & 0x3) == 0) {
776 rte_em_prefetch(&rx_ring[rx_id]);
777 rte_em_prefetch(&sw_ring[rx_id]);
780 /* Rearm RXD: attach new mbuf and reset status to zero. */
785 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
786 rxdp->buffer_addr = dma_addr;
790 * Initialize the returned mbuf.
791 * 1) setup generic mbuf fields:
792 * - number of segments,
795 * - RX port identifier.
796 * 2) integrate hardware offload data, if any:
798 * - IP checksum flag,
799 * - VLAN TCI, if any,
802 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.length) -
804 rxm->data_off = RTE_PKTMBUF_HEADROOM;
805 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
808 rxm->pkt_len = pkt_len;
809 rxm->data_len = pkt_len;
810 rxm->port = rxq->port_id;
812 rxm->ol_flags = rx_desc_status_to_pkt_flags(status);
813 rxm->ol_flags = rxm->ol_flags |
814 rx_desc_error_to_pkt_flags(rxd.errors);
816 /* Only valid if PKT_RX_VLAN set in pkt_flags */
817 rxm->vlan_tci = rte_le_to_cpu_16(rxd.special);
820 * Store the mbuf address into the next entry of the array
821 * of returned packets.
823 rx_pkts[nb_rx++] = rxm;
825 rxq->rx_tail = rx_id;
828 * If the number of free RX descriptors is greater than the RX free
829 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
831 * Update the RDT with the value of the last processed RX descriptor
832 * minus 1, to guarantee that the RDT register is never equal to the
833 * RDH register, which creates a "full" ring situtation from the
834 * hardware point of view...
836 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
837 if (nb_hold > rxq->rx_free_thresh) {
838 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
839 "nb_hold=%u nb_rx=%u",
840 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
841 (unsigned) rx_id, (unsigned) nb_hold,
843 rx_id = (uint16_t) ((rx_id == 0) ?
844 (rxq->nb_rx_desc - 1) : (rx_id - 1));
845 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
848 rxq->nb_rx_hold = nb_hold;
853 eth_em_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
856 struct em_rx_queue *rxq;
857 volatile struct e1000_rx_desc *rx_ring;
858 volatile struct e1000_rx_desc *rxdp;
859 struct em_rx_entry *sw_ring;
860 struct em_rx_entry *rxe;
861 struct rte_mbuf *first_seg;
862 struct rte_mbuf *last_seg;
863 struct rte_mbuf *rxm;
864 struct rte_mbuf *nmb;
865 struct e1000_rx_desc rxd;
866 uint64_t dma; /* Physical address of mbuf data buffer */
877 rx_id = rxq->rx_tail;
878 rx_ring = rxq->rx_ring;
879 sw_ring = rxq->sw_ring;
882 * Retrieve RX context of current packet, if any.
884 first_seg = rxq->pkt_first_seg;
885 last_seg = rxq->pkt_last_seg;
887 while (nb_rx < nb_pkts) {
890 * The order of operations here is important as the DD status
891 * bit must not be read after any other descriptor fields.
892 * rx_ring and rxdp are pointing to volatile data so the order
893 * of accesses cannot be reordered by the compiler. If they were
894 * not volatile, they could be reordered which could lead to
895 * using invalid descriptor fields when read from rxd.
897 rxdp = &rx_ring[rx_id];
898 status = rxdp->status;
899 if (! (status & E1000_RXD_STAT_DD))
906 * Allocate a new mbuf to replenish the RX ring descriptor.
907 * If the allocation fails:
908 * - arrange for that RX descriptor to be the first one
909 * being parsed the next time the receive function is
910 * invoked [on the same queue].
912 * - Stop parsing the RX ring and return immediately.
914 * This policy does not drop the packet received in the RX
915 * descriptor for which the allocation of a new mbuf failed.
916 * Thus, it allows that packet to be later retrieved if
917 * mbuf have been freed in the mean time.
918 * As a side effect, holding RX descriptors instead of
919 * systematically giving them back to the NIC may lead to
920 * RX ring exhaustion situations.
921 * However, the NIC can gracefully prevent such situations
922 * to happen by sending specific "back-pressure" flow control
923 * frames to its peer(s).
925 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
926 "status=0x%x data_len=%u",
927 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
928 (unsigned) rx_id, (unsigned) status,
929 (unsigned) rte_le_to_cpu_16(rxd.length));
931 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
933 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
934 "queue_id=%u", (unsigned) rxq->port_id,
935 (unsigned) rxq->queue_id);
936 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
941 rxe = &sw_ring[rx_id];
943 if (rx_id == rxq->nb_rx_desc)
946 /* Prefetch next mbuf while processing current one. */
947 rte_em_prefetch(sw_ring[rx_id].mbuf);
950 * When next RX descriptor is on a cache-line boundary,
951 * prefetch the next 4 RX descriptors and the next 8 pointers
954 if ((rx_id & 0x3) == 0) {
955 rte_em_prefetch(&rx_ring[rx_id]);
956 rte_em_prefetch(&sw_ring[rx_id]);
960 * Update RX descriptor with the physical address of the new
961 * data buffer of the new allocated mbuf.
965 dma = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
966 rxdp->buffer_addr = dma;
970 * Set data length & data buffer address of mbuf.
972 data_len = rte_le_to_cpu_16(rxd.length);
973 rxm->data_len = data_len;
974 rxm->data_off = RTE_PKTMBUF_HEADROOM;
977 * If this is the first buffer of the received packet,
978 * set the pointer to the first mbuf of the packet and
979 * initialize its context.
980 * Otherwise, update the total length and the number of segments
981 * of the current scattered packet, and update the pointer to
982 * the last mbuf of the current packet.
984 if (first_seg == NULL) {
986 first_seg->pkt_len = data_len;
987 first_seg->nb_segs = 1;
989 first_seg->pkt_len += data_len;
990 first_seg->nb_segs++;
991 last_seg->next = rxm;
995 * If this is not the last buffer of the received packet,
996 * update the pointer to the last mbuf of the current scattered
997 * packet and continue to parse the RX ring.
999 if (! (status & E1000_RXD_STAT_EOP)) {
1005 * This is the last buffer of the received packet.
1006 * If the CRC is not stripped by the hardware:
1007 * - Subtract the CRC length from the total packet length.
1008 * - If the last buffer only contains the whole CRC or a part
1009 * of it, free the mbuf associated to the last buffer.
1010 * If part of the CRC is also contained in the previous
1011 * mbuf, subtract the length of that CRC part from the
1012 * data length of the previous mbuf.
1015 if (unlikely(rxq->crc_len > 0)) {
1016 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1017 if (data_len <= RTE_ETHER_CRC_LEN) {
1018 rte_pktmbuf_free_seg(rxm);
1019 first_seg->nb_segs--;
1020 last_seg->data_len = (uint16_t)
1021 (last_seg->data_len -
1022 (RTE_ETHER_CRC_LEN - data_len));
1023 last_seg->next = NULL;
1025 rxm->data_len = (uint16_t)
1026 (data_len - RTE_ETHER_CRC_LEN);
1030 * Initialize the first mbuf of the returned packet:
1031 * - RX port identifier,
1032 * - hardware offload data, if any:
1033 * - IP checksum flag,
1036 first_seg->port = rxq->port_id;
1038 first_seg->ol_flags = rx_desc_status_to_pkt_flags(status);
1039 first_seg->ol_flags = first_seg->ol_flags |
1040 rx_desc_error_to_pkt_flags(rxd.errors);
1042 /* Only valid if PKT_RX_VLAN set in pkt_flags */
1043 rxm->vlan_tci = rte_le_to_cpu_16(rxd.special);
1045 /* Prefetch data of first segment, if configured to do so. */
1046 rte_packet_prefetch((char *)first_seg->buf_addr +
1047 first_seg->data_off);
1050 * Store the mbuf address into the next entry of the array
1051 * of returned packets.
1053 rx_pkts[nb_rx++] = first_seg;
1056 * Setup receipt context for a new packet.
1062 * Record index of the next RX descriptor to probe.
1064 rxq->rx_tail = rx_id;
1067 * Save receive context.
1069 rxq->pkt_first_seg = first_seg;
1070 rxq->pkt_last_seg = last_seg;
1073 * If the number of free RX descriptors is greater than the RX free
1074 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1076 * Update the RDT with the value of the last processed RX descriptor
1077 * minus 1, to guarantee that the RDT register is never equal to the
1078 * RDH register, which creates a "full" ring situtation from the
1079 * hardware point of view...
1081 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1082 if (nb_hold > rxq->rx_free_thresh) {
1083 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1084 "nb_hold=%u nb_rx=%u",
1085 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1086 (unsigned) rx_id, (unsigned) nb_hold,
1088 rx_id = (uint16_t) ((rx_id == 0) ?
1089 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1090 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1093 rxq->nb_rx_hold = nb_hold;
1097 #define EM_MAX_BUF_SIZE 16384
1098 #define EM_RCTL_FLXBUF_STEP 1024
1101 em_tx_queue_release_mbufs(struct em_tx_queue *txq)
1105 if (txq->sw_ring != NULL) {
1106 for (i = 0; i != txq->nb_tx_desc; i++) {
1107 if (txq->sw_ring[i].mbuf != NULL) {
1108 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1109 txq->sw_ring[i].mbuf = NULL;
1116 em_tx_queue_release(struct em_tx_queue *txq)
1119 em_tx_queue_release_mbufs(txq);
1120 rte_free(txq->sw_ring);
1121 rte_memzone_free(txq->mz);
1127 eth_em_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1129 em_tx_queue_release(dev->data->tx_queues[qid]);
1132 /* (Re)set dynamic em_tx_queue fields to defaults */
1134 em_reset_tx_queue(struct em_tx_queue *txq)
1136 uint16_t i, nb_desc, prev;
1137 static const struct e1000_data_desc txd_init = {
1138 .upper.fields = {.status = E1000_TXD_STAT_DD},
1141 nb_desc = txq->nb_tx_desc;
1143 /* Initialize ring entries */
1145 prev = (uint16_t) (nb_desc - 1);
1147 for (i = 0; i < nb_desc; i++) {
1148 txq->tx_ring[i] = txd_init;
1149 txq->sw_ring[i].mbuf = NULL;
1150 txq->sw_ring[i].last_id = i;
1151 txq->sw_ring[prev].next_id = i;
1156 * Always allow 1 descriptor to be un-allocated to avoid
1157 * a H/W race condition
1159 txq->nb_tx_free = (uint16_t)(nb_desc - 1);
1160 txq->last_desc_cleaned = (uint16_t)(nb_desc - 1);
1161 txq->nb_tx_used = 0;
1164 memset((void*)&txq->ctx_cache, 0, sizeof (txq->ctx_cache));
1168 em_get_tx_port_offloads_capa(struct rte_eth_dev *dev)
1170 uint64_t tx_offload_capa;
1174 DEV_TX_OFFLOAD_MULTI_SEGS |
1175 DEV_TX_OFFLOAD_VLAN_INSERT |
1176 DEV_TX_OFFLOAD_IPV4_CKSUM |
1177 DEV_TX_OFFLOAD_UDP_CKSUM |
1178 DEV_TX_OFFLOAD_TCP_CKSUM;
1180 return tx_offload_capa;
1184 em_get_tx_queue_offloads_capa(struct rte_eth_dev *dev)
1186 uint64_t tx_queue_offload_capa;
1189 * As only one Tx queue can be used, let per queue offloading
1190 * capability be same to per port queue offloading capability
1191 * for better convenience.
1193 tx_queue_offload_capa = em_get_tx_port_offloads_capa(dev);
1195 return tx_queue_offload_capa;
1199 eth_em_tx_queue_setup(struct rte_eth_dev *dev,
1202 unsigned int socket_id,
1203 const struct rte_eth_txconf *tx_conf)
1205 const struct rte_memzone *tz;
1206 struct em_tx_queue *txq;
1207 struct e1000_hw *hw;
1209 uint16_t tx_rs_thresh, tx_free_thresh;
1212 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1214 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1217 * Validate number of transmit descriptors.
1218 * It must not exceed hardware maximum, and must be multiple
1221 if (nb_desc % EM_TXD_ALIGN != 0 ||
1222 (nb_desc > E1000_MAX_RING_DESC) ||
1223 (nb_desc < E1000_MIN_RING_DESC)) {
1227 tx_free_thresh = tx_conf->tx_free_thresh;
1228 if (tx_free_thresh == 0)
1229 tx_free_thresh = (uint16_t)RTE_MIN(nb_desc / 4,
1230 DEFAULT_TX_FREE_THRESH);
1232 tx_rs_thresh = tx_conf->tx_rs_thresh;
1233 if (tx_rs_thresh == 0)
1234 tx_rs_thresh = (uint16_t)RTE_MIN(tx_free_thresh,
1235 DEFAULT_TX_RS_THRESH);
1237 if (tx_free_thresh >= (nb_desc - 3)) {
1238 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
1239 "number of TX descriptors minus 3. "
1240 "(tx_free_thresh=%u port=%d queue=%d)",
1241 (unsigned int)tx_free_thresh,
1242 (int)dev->data->port_id, (int)queue_idx);
1245 if (tx_rs_thresh > tx_free_thresh) {
1246 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
1247 "tx_free_thresh. (tx_free_thresh=%u "
1248 "tx_rs_thresh=%u port=%d queue=%d)",
1249 (unsigned int)tx_free_thresh,
1250 (unsigned int)tx_rs_thresh,
1251 (int)dev->data->port_id,
1257 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1258 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1259 * by the NIC and all descriptors are written back after the NIC
1260 * accumulates WTHRESH descriptors.
1262 if (tx_conf->tx_thresh.wthresh != 0 && tx_rs_thresh != 1) {
1263 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1264 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1265 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1266 (int)dev->data->port_id, (int)queue_idx);
1270 /* Free memory prior to re-allocation if needed... */
1271 if (dev->data->tx_queues[queue_idx] != NULL) {
1272 em_tx_queue_release(dev->data->tx_queues[queue_idx]);
1273 dev->data->tx_queues[queue_idx] = NULL;
1277 * Allocate TX ring hardware descriptors. A memzone large enough to
1278 * handle the maximum ring size is allocated in order to allow for
1279 * resizing in later calls to the queue setup function.
1281 tsize = sizeof(txq->tx_ring[0]) * E1000_MAX_RING_DESC;
1282 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx, tsize,
1283 RTE_CACHE_LINE_SIZE, socket_id);
1287 /* Allocate the tx queue data structure. */
1288 if ((txq = rte_zmalloc("ethdev TX queue", sizeof(*txq),
1289 RTE_CACHE_LINE_SIZE)) == NULL)
1293 /* Allocate software ring */
1294 if ((txq->sw_ring = rte_zmalloc("txq->sw_ring",
1295 sizeof(txq->sw_ring[0]) * nb_desc,
1296 RTE_CACHE_LINE_SIZE)) == NULL) {
1297 em_tx_queue_release(txq);
1301 txq->nb_tx_desc = nb_desc;
1302 txq->tx_free_thresh = tx_free_thresh;
1303 txq->tx_rs_thresh = tx_rs_thresh;
1304 txq->pthresh = tx_conf->tx_thresh.pthresh;
1305 txq->hthresh = tx_conf->tx_thresh.hthresh;
1306 txq->wthresh = tx_conf->tx_thresh.wthresh;
1307 txq->queue_id = queue_idx;
1308 txq->port_id = dev->data->port_id;
1310 txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(queue_idx));
1311 txq->tx_ring_phys_addr = tz->iova;
1312 txq->tx_ring = (struct e1000_data_desc *) tz->addr;
1314 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1315 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1317 em_reset_tx_queue(txq);
1319 dev->data->tx_queues[queue_idx] = txq;
1320 txq->offloads = offloads;
1325 em_rx_queue_release_mbufs(struct em_rx_queue *rxq)
1329 if (rxq->sw_ring != NULL) {
1330 for (i = 0; i != rxq->nb_rx_desc; i++) {
1331 if (rxq->sw_ring[i].mbuf != NULL) {
1332 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1333 rxq->sw_ring[i].mbuf = NULL;
1340 em_rx_queue_release(struct em_rx_queue *rxq)
1343 em_rx_queue_release_mbufs(rxq);
1344 rte_free(rxq->sw_ring);
1345 rte_memzone_free(rxq->mz);
1351 eth_em_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1353 em_rx_queue_release(dev->data->rx_queues[qid]);
1356 /* Reset dynamic em_rx_queue fields back to defaults */
1358 em_reset_rx_queue(struct em_rx_queue *rxq)
1361 rxq->nb_rx_hold = 0;
1362 rxq->pkt_first_seg = NULL;
1363 rxq->pkt_last_seg = NULL;
1367 em_get_rx_port_offloads_capa(struct rte_eth_dev *dev)
1369 uint64_t rx_offload_capa;
1370 uint32_t max_rx_pktlen;
1372 max_rx_pktlen = em_get_max_pktlen(dev);
1375 DEV_RX_OFFLOAD_VLAN_STRIP |
1376 DEV_RX_OFFLOAD_VLAN_FILTER |
1377 DEV_RX_OFFLOAD_IPV4_CKSUM |
1378 DEV_RX_OFFLOAD_UDP_CKSUM |
1379 DEV_RX_OFFLOAD_TCP_CKSUM |
1380 DEV_RX_OFFLOAD_KEEP_CRC |
1381 DEV_RX_OFFLOAD_SCATTER;
1382 if (max_rx_pktlen > RTE_ETHER_MAX_LEN)
1383 rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1385 return rx_offload_capa;
1389 em_get_rx_queue_offloads_capa(struct rte_eth_dev *dev)
1391 uint64_t rx_queue_offload_capa;
1394 * As only one Rx queue can be used, let per queue offloading
1395 * capability be same to per port queue offloading capability
1396 * for better convenience.
1398 rx_queue_offload_capa = em_get_rx_port_offloads_capa(dev);
1400 return rx_queue_offload_capa;
1404 eth_em_rx_queue_setup(struct rte_eth_dev *dev,
1407 unsigned int socket_id,
1408 const struct rte_eth_rxconf *rx_conf,
1409 struct rte_mempool *mp)
1411 const struct rte_memzone *rz;
1412 struct em_rx_queue *rxq;
1413 struct e1000_hw *hw;
1417 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1419 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1422 * Validate number of receive descriptors.
1423 * It must not exceed hardware maximum, and must be multiple
1426 if (nb_desc % EM_RXD_ALIGN != 0 ||
1427 (nb_desc > E1000_MAX_RING_DESC) ||
1428 (nb_desc < E1000_MIN_RING_DESC)) {
1433 * EM devices don't support drop_en functionality.
1434 * It's an optimization that does nothing on single-queue devices,
1435 * so just log the issue and carry on.
1437 if (rx_conf->rx_drop_en) {
1438 PMD_INIT_LOG(NOTICE, "drop_en functionality not supported by "
1442 /* Free memory prior to re-allocation if needed. */
1443 if (dev->data->rx_queues[queue_idx] != NULL) {
1444 em_rx_queue_release(dev->data->rx_queues[queue_idx]);
1445 dev->data->rx_queues[queue_idx] = NULL;
1448 /* Allocate RX ring for max possible mumber of hardware descriptors. */
1449 rsize = sizeof(rxq->rx_ring[0]) * E1000_MAX_RING_DESC;
1450 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, rsize,
1451 RTE_CACHE_LINE_SIZE, socket_id);
1455 /* Allocate the RX queue data structure. */
1456 if ((rxq = rte_zmalloc("ethdev RX queue", sizeof(*rxq),
1457 RTE_CACHE_LINE_SIZE)) == NULL)
1461 /* Allocate software ring. */
1462 if ((rxq->sw_ring = rte_zmalloc("rxq->sw_ring",
1463 sizeof (rxq->sw_ring[0]) * nb_desc,
1464 RTE_CACHE_LINE_SIZE)) == NULL) {
1465 em_rx_queue_release(rxq);
1470 rxq->nb_rx_desc = nb_desc;
1471 rxq->pthresh = rx_conf->rx_thresh.pthresh;
1472 rxq->hthresh = rx_conf->rx_thresh.hthresh;
1473 rxq->wthresh = rx_conf->rx_thresh.wthresh;
1474 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1475 rxq->queue_id = queue_idx;
1476 rxq->port_id = dev->data->port_id;
1477 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1478 rxq->crc_len = RTE_ETHER_CRC_LEN;
1482 rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(queue_idx));
1483 rxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(queue_idx));
1484 rxq->rx_ring_phys_addr = rz->iova;
1485 rxq->rx_ring = (struct e1000_rx_desc *) rz->addr;
1487 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1488 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
1490 dev->data->rx_queues[queue_idx] = rxq;
1491 em_reset_rx_queue(rxq);
1492 rxq->offloads = offloads;
1498 eth_em_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1500 #define EM_RXQ_SCAN_INTERVAL 4
1501 volatile struct e1000_rx_desc *rxdp;
1502 struct em_rx_queue *rxq;
1505 rxq = dev->data->rx_queues[rx_queue_id];
1506 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1508 while ((desc < rxq->nb_rx_desc) &&
1509 (rxdp->status & E1000_RXD_STAT_DD)) {
1510 desc += EM_RXQ_SCAN_INTERVAL;
1511 rxdp += EM_RXQ_SCAN_INTERVAL;
1512 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1513 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1514 desc - rxq->nb_rx_desc]);
1521 eth_em_rx_descriptor_status(void *rx_queue, uint16_t offset)
1523 struct em_rx_queue *rxq = rx_queue;
1524 volatile uint8_t *status;
1527 if (unlikely(offset >= rxq->nb_rx_desc))
1530 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1531 return RTE_ETH_RX_DESC_UNAVAIL;
1533 desc = rxq->rx_tail + offset;
1534 if (desc >= rxq->nb_rx_desc)
1535 desc -= rxq->nb_rx_desc;
1537 status = &rxq->rx_ring[desc].status;
1538 if (*status & E1000_RXD_STAT_DD)
1539 return RTE_ETH_RX_DESC_DONE;
1541 return RTE_ETH_RX_DESC_AVAIL;
1545 eth_em_tx_descriptor_status(void *tx_queue, uint16_t offset)
1547 struct em_tx_queue *txq = tx_queue;
1548 volatile uint8_t *status;
1551 if (unlikely(offset >= txq->nb_tx_desc))
1554 desc = txq->tx_tail + offset;
1555 /* go to next desc that has the RS bit */
1556 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1558 if (desc >= txq->nb_tx_desc) {
1559 desc -= txq->nb_tx_desc;
1560 if (desc >= txq->nb_tx_desc)
1561 desc -= txq->nb_tx_desc;
1564 status = &txq->tx_ring[desc].upper.fields.status;
1565 if (*status & E1000_TXD_STAT_DD)
1566 return RTE_ETH_TX_DESC_DONE;
1568 return RTE_ETH_TX_DESC_FULL;
1572 em_dev_clear_queues(struct rte_eth_dev *dev)
1575 struct em_tx_queue *txq;
1576 struct em_rx_queue *rxq;
1578 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1579 txq = dev->data->tx_queues[i];
1581 em_tx_queue_release_mbufs(txq);
1582 em_reset_tx_queue(txq);
1586 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1587 rxq = dev->data->rx_queues[i];
1589 em_rx_queue_release_mbufs(rxq);
1590 em_reset_rx_queue(rxq);
1596 em_dev_free_queues(struct rte_eth_dev *dev)
1600 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1601 eth_em_rx_queue_release(dev, i);
1602 dev->data->rx_queues[i] = NULL;
1604 dev->data->nb_rx_queues = 0;
1606 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1607 eth_em_tx_queue_release(dev, i);
1608 dev->data->tx_queues[i] = NULL;
1610 dev->data->nb_tx_queues = 0;
1614 * Takes as input/output parameter RX buffer size.
1615 * Returns (BSIZE | BSEX | FLXBUF) fields of RCTL register.
1618 em_rctl_bsize(__rte_unused enum e1000_mac_type hwtyp, uint32_t *bufsz)
1621 * For BSIZE & BSEX all configurable sizes are:
1622 * 16384: rctl |= (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX);
1623 * 8192: rctl |= (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX);
1624 * 4096: rctl |= (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX);
1625 * 2048: rctl |= E1000_RCTL_SZ_2048;
1626 * 1024: rctl |= E1000_RCTL_SZ_1024;
1627 * 512: rctl |= E1000_RCTL_SZ_512;
1628 * 256: rctl |= E1000_RCTL_SZ_256;
1630 static const struct {
1633 } bufsz_to_rctl[] = {
1634 {16384, (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX)},
1635 {8192, (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX)},
1636 {4096, (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX)},
1637 {2048, E1000_RCTL_SZ_2048},
1638 {1024, E1000_RCTL_SZ_1024},
1639 {512, E1000_RCTL_SZ_512},
1640 {256, E1000_RCTL_SZ_256},
1644 uint32_t rctl_bsize;
1646 rctl_bsize = *bufsz;
1649 * Starting from 82571 it is possible to specify RX buffer size
1650 * by RCTL.FLXBUF. When this field is different from zero, the
1651 * RX buffer size = RCTL.FLXBUF * 1K
1652 * (e.g. t is possible to specify RX buffer size 1,2,...,15KB).
1653 * It is working ok on real HW, but by some reason doesn't work
1654 * on VMware emulated 82574L.
1655 * So for now, always use BSIZE/BSEX to setup RX buffer size.
1656 * If you don't plan to use it on VMware emulated 82574L and
1657 * would like to specify RX buffer size in 1K granularity,
1658 * uncomment the following lines:
1659 * ***************************************************************
1660 * if (hwtyp >= e1000_82571 && hwtyp <= e1000_82574 &&
1661 * rctl_bsize >= EM_RCTL_FLXBUF_STEP) {
1662 * rctl_bsize /= EM_RCTL_FLXBUF_STEP;
1663 * *bufsz = rctl_bsize;
1664 * return (rctl_bsize << E1000_RCTL_FLXBUF_SHIFT &
1665 * E1000_RCTL_FLXBUF_MASK);
1667 * ***************************************************************
1670 for (i = 0; i != sizeof(bufsz_to_rctl) / sizeof(bufsz_to_rctl[0]);
1672 if (rctl_bsize >= bufsz_to_rctl[i].bufsz) {
1673 *bufsz = bufsz_to_rctl[i].bufsz;
1674 return bufsz_to_rctl[i].rctl;
1678 /* Should never happen. */
1683 em_alloc_rx_queue_mbufs(struct em_rx_queue *rxq)
1685 struct em_rx_entry *rxe = rxq->sw_ring;
1688 static const struct e1000_rx_desc rxd_init = {
1692 /* Initialize software ring entries */
1693 for (i = 0; i < rxq->nb_rx_desc; i++) {
1694 volatile struct e1000_rx_desc *rxd;
1695 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
1698 PMD_INIT_LOG(ERR, "RX mbuf alloc failed "
1699 "queue_id=%hu", rxq->queue_id);
1704 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
1706 /* Clear HW ring memory */
1707 rxq->rx_ring[i] = rxd_init;
1709 rxd = &rxq->rx_ring[i];
1710 rxd->buffer_addr = dma_addr;
1717 /*********************************************************************
1719 * Enable receive unit.
1721 **********************************************************************/
1723 eth_em_rx_init(struct rte_eth_dev *dev)
1725 struct e1000_hw *hw;
1726 struct em_rx_queue *rxq;
1727 struct rte_eth_rxmode *rxmode;
1731 uint32_t rctl_bsize;
1735 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1736 rxmode = &dev->data->dev_conf.rxmode;
1739 * Make sure receives are disabled while setting
1740 * up the descriptor ring.
1742 rctl = E1000_READ_REG(hw, E1000_RCTL);
1743 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
1745 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
1747 /* Disable extended descriptor type. */
1748 rfctl &= ~E1000_RFCTL_EXTEN;
1749 /* Disable accelerated acknowledge */
1750 if (hw->mac.type == e1000_82574)
1751 rfctl |= E1000_RFCTL_ACK_DIS;
1753 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
1756 * XXX TEMPORARY WORKAROUND: on some systems with 82573
1757 * long latencies are observed, like Lenovo X60. This
1758 * change eliminates the problem, but since having positive
1759 * values in RDTR is a known source of problems on other
1760 * platforms another solution is being sought.
1762 if (hw->mac.type == e1000_82573)
1763 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
1765 dev->rx_pkt_burst = (eth_rx_burst_t)eth_em_recv_pkts;
1767 /* Determine RX bufsize. */
1768 rctl_bsize = EM_MAX_BUF_SIZE;
1769 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1772 rxq = dev->data->rx_queues[i];
1773 buf_size = rte_pktmbuf_data_room_size(rxq->mb_pool) -
1774 RTE_PKTMBUF_HEADROOM;
1775 rctl_bsize = RTE_MIN(rctl_bsize, buf_size);
1778 rctl |= em_rctl_bsize(hw->mac.type, &rctl_bsize);
1780 /* Configure and enable each RX queue. */
1781 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1785 rxq = dev->data->rx_queues[i];
1787 /* Allocate buffers for descriptor rings and setup queue */
1788 ret = em_alloc_rx_queue_mbufs(rxq);
1793 * Reset crc_len in case it was changed after queue setup by a
1796 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1797 rxq->crc_len = RTE_ETHER_CRC_LEN;
1801 bus_addr = rxq->rx_ring_phys_addr;
1802 E1000_WRITE_REG(hw, E1000_RDLEN(i),
1804 sizeof(*rxq->rx_ring));
1805 E1000_WRITE_REG(hw, E1000_RDBAH(i),
1806 (uint32_t)(bus_addr >> 32));
1807 E1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);
1809 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
1810 E1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);
1812 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
1813 rxdctl &= 0xFE000000;
1814 rxdctl |= rxq->pthresh & 0x3F;
1815 rxdctl |= (rxq->hthresh & 0x3F) << 8;
1816 rxdctl |= (rxq->wthresh & 0x3F) << 16;
1817 rxdctl |= E1000_RXDCTL_GRAN;
1818 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
1821 * Due to EM devices not having any sort of hardware
1822 * limit for packet length, jumbo frame of any size
1823 * can be accepted, thus we have to enable scattered
1824 * rx if jumbo frames are enabled (or if buffer size
1825 * is too small to accommodate non-jumbo packets)
1826 * to avoid splitting packets that don't fit into
1829 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME ||
1830 rctl_bsize < RTE_ETHER_MAX_LEN) {
1831 if (!dev->data->scattered_rx)
1832 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
1834 (eth_rx_burst_t)eth_em_recv_scattered_pkts;
1835 dev->data->scattered_rx = 1;
1839 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) {
1840 if (!dev->data->scattered_rx)
1841 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
1842 dev->rx_pkt_burst = eth_em_recv_scattered_pkts;
1843 dev->data->scattered_rx = 1;
1847 * Setup the Checksum Register.
1848 * Receive Full-Packet Checksum Offload is mutually exclusive with RSS.
1850 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
1852 if (rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM)
1853 rxcsum |= E1000_RXCSUM_IPOFL;
1855 rxcsum &= ~E1000_RXCSUM_IPOFL;
1856 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
1858 /* No MRQ or RSS support for now */
1860 /* Set early receive threshold on appropriate hw */
1861 if ((hw->mac.type == e1000_ich9lan ||
1862 hw->mac.type == e1000_pch2lan ||
1863 hw->mac.type == e1000_ich10lan) &&
1864 rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1865 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
1866 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
1867 E1000_WRITE_REG(hw, E1000_ERT, 0x100 | (1 << 13));
1870 if (hw->mac.type == e1000_pch2lan) {
1871 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1872 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
1874 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
1877 /* Setup the Receive Control Register. */
1878 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1879 rctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */
1881 rctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC. */
1883 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1884 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
1885 E1000_RCTL_RDMTS_HALF |
1886 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1888 /* Make sure VLAN Filters are off. */
1889 rctl &= ~E1000_RCTL_VFE;
1890 /* Don't store bad packets. */
1891 rctl &= ~E1000_RCTL_SBP;
1892 /* Legacy descriptor type. */
1893 rctl &= ~E1000_RCTL_DTYP_MASK;
1896 * Configure support of jumbo frames, if any.
1898 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1899 rctl |= E1000_RCTL_LPE;
1901 rctl &= ~E1000_RCTL_LPE;
1903 /* Enable Receives. */
1904 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1909 /*********************************************************************
1911 * Enable transmit unit.
1913 **********************************************************************/
1915 eth_em_tx_init(struct rte_eth_dev *dev)
1917 struct e1000_hw *hw;
1918 struct em_tx_queue *txq;
1923 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1925 /* Setup the Base and Length of the Tx Descriptor Rings. */
1926 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1929 txq = dev->data->tx_queues[i];
1930 bus_addr = txq->tx_ring_phys_addr;
1931 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1933 sizeof(*txq->tx_ring));
1934 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1935 (uint32_t)(bus_addr >> 32));
1936 E1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);
1938 /* Setup the HW Tx Head and Tail descriptor pointers. */
1939 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1940 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1942 /* Setup Transmit threshold registers. */
1943 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));
1945 * bit 22 is reserved, on some models should always be 0,
1946 * on others - always 1.
1948 txdctl &= E1000_TXDCTL_COUNT_DESC;
1949 txdctl |= txq->pthresh & 0x3F;
1950 txdctl |= (txq->hthresh & 0x3F) << 8;
1951 txdctl |= (txq->wthresh & 0x3F) << 16;
1952 txdctl |= E1000_TXDCTL_GRAN;
1953 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1956 /* Program the Transmit Control Register. */
1957 tctl = E1000_READ_REG(hw, E1000_TCTL);
1958 tctl &= ~E1000_TCTL_CT;
1959 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1960 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1962 /* SPT and CNP Si errata workaround to avoid data corruption */
1963 if (hw->mac.type == e1000_pch_spt) {
1965 reg_val = E1000_READ_REG(hw, E1000_IOSFPC);
1966 reg_val |= E1000_RCTL_RDMTS_HEX;
1967 E1000_WRITE_REG(hw, E1000_IOSFPC, reg_val);
1969 /* Dropping the number of outstanding requests from
1970 * 3 to 2 in order to avoid a buffer overrun.
1972 reg_val = E1000_READ_REG(hw, E1000_TARC(0));
1973 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
1974 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
1975 E1000_WRITE_REG(hw, E1000_TARC(0), reg_val);
1978 /* This write will effectively turn on the transmit unit. */
1979 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1983 em_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1984 struct rte_eth_rxq_info *qinfo)
1986 struct em_rx_queue *rxq;
1988 rxq = dev->data->rx_queues[queue_id];
1990 qinfo->mp = rxq->mb_pool;
1991 qinfo->scattered_rx = dev->data->scattered_rx;
1992 qinfo->nb_desc = rxq->nb_rx_desc;
1993 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1994 qinfo->conf.offloads = rxq->offloads;
1998 em_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1999 struct rte_eth_txq_info *qinfo)
2001 struct em_tx_queue *txq;
2003 txq = dev->data->tx_queues[queue_id];
2005 qinfo->nb_desc = txq->nb_tx_desc;
2007 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2008 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2009 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2010 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2011 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2012 qinfo->conf.offloads = txq->offloads;
2016 e1000_flush_tx_ring(struct rte_eth_dev *dev)
2018 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2019 volatile struct e1000_data_desc *tx_desc;
2020 volatile uint32_t *tdt_reg_addr;
2021 uint32_t tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
2022 uint16_t size = 512;
2023 struct em_tx_queue *txq;
2026 if (dev->data->tx_queues == NULL)
2028 tctl = E1000_READ_REG(hw, E1000_TCTL);
2029 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN);
2030 for (i = 0; i < dev->data->nb_tx_queues &&
2031 i < E1000_I219_MAX_TX_QUEUE_NUM; i++) {
2032 txq = dev->data->tx_queues[i];
2033 tdt = E1000_READ_REG(hw, E1000_TDT(i));
2034 if (tdt != txq->tx_tail)
2036 tx_desc = &txq->tx_ring[txq->tx_tail];
2037 tx_desc->buffer_addr = rte_cpu_to_le_64(txq->tx_ring_phys_addr);
2038 tx_desc->lower.data = rte_cpu_to_le_32(txd_lower | size);
2039 tx_desc->upper.data = 0;
2043 if (txq->tx_tail == txq->nb_tx_desc)
2045 tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(i));
2046 E1000_PCI_REG_WRITE(tdt_reg_addr, txq->tx_tail);
2052 e1000_flush_rx_ring(struct rte_eth_dev *dev)
2054 uint32_t rctl, rxdctl;
2055 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2058 rctl = E1000_READ_REG(hw, E1000_RCTL);
2059 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2060 E1000_WRITE_FLUSH(hw);
2063 for (i = 0; i < dev->data->nb_rx_queues &&
2064 i < E1000_I219_MAX_RX_QUEUE_NUM; i++) {
2065 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2066 /* zero the lower 14 bits (prefetch and host thresholds) */
2067 rxdctl &= 0xffffc000;
2069 /* update thresholds: prefetch threshold to 31,
2070 * host threshold to 1 and make sure the granularity
2071 * is "descriptors" and not "cache lines"
2073 rxdctl |= (0x1F | (1UL << 8) | E1000_RXDCTL_THRESH_UNIT_DESC);
2075 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2077 /* momentarily enable the RX ring for the changes to take effect */
2078 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN);
2079 E1000_WRITE_FLUSH(hw);
2081 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2085 * em_flush_desc_rings - remove all descriptors from the descriptor rings
2087 * In i219, the descriptor rings must be emptied before resetting/closing the
2088 * HW. Failure to do this will cause the HW to enter a unit hang state which
2089 * can only be released by PCI reset on the device
2094 em_flush_desc_rings(struct rte_eth_dev *dev)
2096 uint32_t fextnvm11, tdlen;
2097 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2098 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2099 uint16_t pci_cfg_status = 0;
2102 fextnvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11);
2103 E1000_WRITE_REG(hw, E1000_FEXTNVM11,
2104 fextnvm11 | E1000_FEXTNVM11_DISABLE_MULR_FIX);
2105 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0));
2106 ret = rte_pci_read_config(pci_dev, &pci_cfg_status,
2107 sizeof(pci_cfg_status), PCI_CFG_STATUS_REG);
2109 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
2110 PCI_CFG_STATUS_REG);
2114 /* do nothing if we're not in faulty state, or if the queue is empty */
2115 if ((pci_cfg_status & FLUSH_DESC_REQUIRED) && tdlen) {
2116 /* flush desc ring */
2117 e1000_flush_tx_ring(dev);
2118 ret = rte_pci_read_config(pci_dev, &pci_cfg_status,
2119 sizeof(pci_cfg_status), PCI_CFG_STATUS_REG);
2121 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
2122 PCI_CFG_STATUS_REG);
2126 if (pci_cfg_status & FLUSH_DESC_REQUIRED)
2127 e1000_flush_rx_ring(dev);