4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
61 * Default values for port configuration
63 #define IGB_DEFAULT_RX_FREE_THRESH 32
64 #define IGB_DEFAULT_RX_PTHRESH 8
65 #define IGB_DEFAULT_RX_HTHRESH 8
66 #define IGB_DEFAULT_RX_WTHRESH 0
68 #define IGB_DEFAULT_TX_PTHRESH 32
69 #define IGB_DEFAULT_TX_HTHRESH 0
70 #define IGB_DEFAULT_TX_WTHRESH 0
72 #define IGB_HKEY_MAX_INDEX 10
74 /* Bit shift and mask */
75 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
76 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
77 #define IGB_8_BIT_WIDTH CHAR_BIT
78 #define IGB_8_BIT_MASK UINT8_MAX
80 /* Additional timesync values. */
81 #define E1000_ETQF_FILTER_1588 3
82 #define E1000_TIMINCA_INCVALUE 16000000
83 #define E1000_TIMINCA_INIT ((0x02 << E1000_TIMINCA_16NS_SHIFT) \
84 | E1000_TIMINCA_INCVALUE)
85 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
87 static int eth_igb_configure(struct rte_eth_dev *dev);
88 static int eth_igb_start(struct rte_eth_dev *dev);
89 static void eth_igb_stop(struct rte_eth_dev *dev);
90 static void eth_igb_close(struct rte_eth_dev *dev);
91 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
92 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
93 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
94 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
95 static int eth_igb_link_update(struct rte_eth_dev *dev,
96 int wait_to_complete);
97 static void eth_igb_stats_get(struct rte_eth_dev *dev,
98 struct rte_eth_stats *rte_stats);
99 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
100 struct rte_eth_xstats *xstats, unsigned n);
101 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
102 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
103 static void eth_igb_infos_get(struct rte_eth_dev *dev,
104 struct rte_eth_dev_info *dev_info);
105 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
108 struct rte_eth_fc_conf *fc_conf);
109 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
110 struct rte_eth_fc_conf *fc_conf);
111 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
112 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
113 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
114 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
115 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
117 static int igb_hardware_init(struct e1000_hw *hw);
118 static void igb_hw_control_acquire(struct e1000_hw *hw);
119 static void igb_hw_control_release(struct e1000_hw *hw);
120 static void igb_init_manageability(struct e1000_hw *hw);
121 static void igb_release_manageability(struct e1000_hw *hw);
123 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
125 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
126 uint16_t vlan_id, int on);
127 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
128 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
130 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
131 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
132 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
133 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
134 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
135 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
137 static int eth_igb_led_on(struct rte_eth_dev *dev);
138 static int eth_igb_led_off(struct rte_eth_dev *dev);
140 static void igb_intr_disable(struct e1000_hw *hw);
141 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
142 static void eth_igb_rar_set(struct rte_eth_dev *dev,
143 struct ether_addr *mac_addr,
144 uint32_t index, uint32_t pool);
145 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
146 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
147 struct ether_addr *addr);
149 static void igbvf_intr_disable(struct e1000_hw *hw);
150 static int igbvf_dev_configure(struct rte_eth_dev *dev);
151 static int igbvf_dev_start(struct rte_eth_dev *dev);
152 static void igbvf_dev_stop(struct rte_eth_dev *dev);
153 static void igbvf_dev_close(struct rte_eth_dev *dev);
154 static int eth_igbvf_link_update(struct e1000_hw *hw);
155 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
156 struct rte_eth_stats *rte_stats);
157 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
158 struct rte_eth_xstats *xstats, unsigned n);
159 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
160 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
161 uint16_t vlan_id, int on);
162 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
163 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
164 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
165 struct ether_addr *addr);
166 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
167 static int igbvf_get_regs(struct rte_eth_dev *dev,
168 struct rte_dev_reg_info *regs);
170 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
171 struct rte_eth_rss_reta_entry64 *reta_conf,
173 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
174 struct rte_eth_rss_reta_entry64 *reta_conf,
177 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
178 struct rte_eth_syn_filter *filter,
180 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
181 struct rte_eth_syn_filter *filter);
182 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
183 enum rte_filter_op filter_op,
185 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
186 struct rte_eth_ntuple_filter *ntuple_filter);
187 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
188 struct rte_eth_ntuple_filter *ntuple_filter);
189 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
190 struct rte_eth_flex_filter *filter,
192 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
193 struct rte_eth_flex_filter *filter);
194 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
195 enum rte_filter_op filter_op,
197 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
198 struct rte_eth_ntuple_filter *ntuple_filter);
199 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
200 struct rte_eth_ntuple_filter *ntuple_filter);
201 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
202 struct rte_eth_ntuple_filter *filter,
204 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
205 struct rte_eth_ntuple_filter *filter);
206 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
207 enum rte_filter_op filter_op,
209 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
210 struct rte_eth_ethertype_filter *filter,
212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
213 enum rte_filter_op filter_op,
215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
216 struct rte_eth_ethertype_filter *filter);
217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
218 enum rte_filter_type filter_type,
219 enum rte_filter_op filter_op,
221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
223 struct rte_dev_reg_info *regs);
224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
226 struct rte_dev_eeprom_info *eeprom);
227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
228 struct rte_dev_eeprom_info *eeprom);
229 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
230 struct ether_addr *mc_addr_set,
231 uint32_t nb_mc_addr);
232 static int igb_timesync_enable(struct rte_eth_dev *dev);
233 static int igb_timesync_disable(struct rte_eth_dev *dev);
234 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
235 struct timespec *timestamp,
237 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
238 struct timespec *timestamp);
239 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
241 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
243 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
244 uint8_t queue, uint8_t msix_vector);
245 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
246 uint8_t index, uint8_t offset);
247 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
250 * Define VF Stats MACRO for Non "cleared on read" register
252 #define UPDATE_VF_STAT(reg, last, cur) \
254 u32 latest = E1000_READ_REG(hw, reg); \
255 cur += (latest - last) & UINT_MAX; \
259 #define IGB_FC_PAUSE_TIME 0x0680
260 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
261 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
263 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
265 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
268 * The set of PCI devices this driver supports
270 static const struct rte_pci_id pci_id_igb_map[] = {
272 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
273 #include "rte_pci_dev_ids.h"
279 * The set of PCI devices this driver supports (for 82576&I350 VF)
281 static const struct rte_pci_id pci_id_igbvf_map[] = {
283 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
284 #include "rte_pci_dev_ids.h"
289 static const struct rte_eth_desc_lim rx_desc_lim = {
290 .nb_max = E1000_MAX_RING_DESC,
291 .nb_min = E1000_MIN_RING_DESC,
292 .nb_align = IGB_RXD_ALIGN,
295 static const struct rte_eth_desc_lim tx_desc_lim = {
296 .nb_max = E1000_MAX_RING_DESC,
297 .nb_min = E1000_MIN_RING_DESC,
298 .nb_align = IGB_RXD_ALIGN,
301 static const struct eth_dev_ops eth_igb_ops = {
302 .dev_configure = eth_igb_configure,
303 .dev_start = eth_igb_start,
304 .dev_stop = eth_igb_stop,
305 .dev_close = eth_igb_close,
306 .promiscuous_enable = eth_igb_promiscuous_enable,
307 .promiscuous_disable = eth_igb_promiscuous_disable,
308 .allmulticast_enable = eth_igb_allmulticast_enable,
309 .allmulticast_disable = eth_igb_allmulticast_disable,
310 .link_update = eth_igb_link_update,
311 .stats_get = eth_igb_stats_get,
312 .xstats_get = eth_igb_xstats_get,
313 .stats_reset = eth_igb_stats_reset,
314 .xstats_reset = eth_igb_xstats_reset,
315 .dev_infos_get = eth_igb_infos_get,
316 .mtu_set = eth_igb_mtu_set,
317 .vlan_filter_set = eth_igb_vlan_filter_set,
318 .vlan_tpid_set = eth_igb_vlan_tpid_set,
319 .vlan_offload_set = eth_igb_vlan_offload_set,
320 .rx_queue_setup = eth_igb_rx_queue_setup,
321 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
322 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
323 .rx_queue_release = eth_igb_rx_queue_release,
324 .rx_queue_count = eth_igb_rx_queue_count,
325 .rx_descriptor_done = eth_igb_rx_descriptor_done,
326 .tx_queue_setup = eth_igb_tx_queue_setup,
327 .tx_queue_release = eth_igb_tx_queue_release,
328 .dev_led_on = eth_igb_led_on,
329 .dev_led_off = eth_igb_led_off,
330 .flow_ctrl_get = eth_igb_flow_ctrl_get,
331 .flow_ctrl_set = eth_igb_flow_ctrl_set,
332 .mac_addr_add = eth_igb_rar_set,
333 .mac_addr_remove = eth_igb_rar_clear,
334 .mac_addr_set = eth_igb_default_mac_addr_set,
335 .reta_update = eth_igb_rss_reta_update,
336 .reta_query = eth_igb_rss_reta_query,
337 .rss_hash_update = eth_igb_rss_hash_update,
338 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
339 .filter_ctrl = eth_igb_filter_ctrl,
340 .set_mc_addr_list = eth_igb_set_mc_addr_list,
341 .rxq_info_get = igb_rxq_info_get,
342 .txq_info_get = igb_txq_info_get,
343 .timesync_enable = igb_timesync_enable,
344 .timesync_disable = igb_timesync_disable,
345 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
346 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
347 .get_reg_length = eth_igb_get_reg_length,
348 .get_reg = eth_igb_get_regs,
349 .get_eeprom_length = eth_igb_get_eeprom_length,
350 .get_eeprom = eth_igb_get_eeprom,
351 .set_eeprom = eth_igb_set_eeprom,
355 * dev_ops for virtual function, bare necessities for basic vf
356 * operation have been implemented
358 static const struct eth_dev_ops igbvf_eth_dev_ops = {
359 .dev_configure = igbvf_dev_configure,
360 .dev_start = igbvf_dev_start,
361 .dev_stop = igbvf_dev_stop,
362 .dev_close = igbvf_dev_close,
363 .link_update = eth_igb_link_update,
364 .stats_get = eth_igbvf_stats_get,
365 .xstats_get = eth_igbvf_xstats_get,
366 .stats_reset = eth_igbvf_stats_reset,
367 .xstats_reset = eth_igbvf_stats_reset,
368 .vlan_filter_set = igbvf_vlan_filter_set,
369 .dev_infos_get = eth_igbvf_infos_get,
370 .rx_queue_setup = eth_igb_rx_queue_setup,
371 .rx_queue_release = eth_igb_rx_queue_release,
372 .tx_queue_setup = eth_igb_tx_queue_setup,
373 .tx_queue_release = eth_igb_tx_queue_release,
374 .set_mc_addr_list = eth_igb_set_mc_addr_list,
375 .rxq_info_get = igb_rxq_info_get,
376 .txq_info_get = igb_txq_info_get,
377 .mac_addr_set = igbvf_default_mac_addr_set,
378 .get_reg_length = igbvf_get_reg_length,
379 .get_reg = igbvf_get_regs,
382 /* store statistics names and its offset in stats structure */
383 struct rte_igb_xstats_name_off {
384 char name[RTE_ETH_XSTATS_NAME_SIZE];
388 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
389 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
390 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
391 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
392 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
393 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
394 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
395 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
397 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
398 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
399 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
400 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
401 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
402 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
403 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
404 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
405 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
406 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
407 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
409 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
410 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
411 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
412 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
413 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
415 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
417 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
418 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
419 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
420 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
421 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
422 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
423 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
424 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
425 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
426 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
427 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
428 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
429 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
430 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
431 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
432 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
433 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
434 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
436 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
438 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
439 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
440 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
441 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
442 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
443 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
444 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
446 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
449 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
450 sizeof(rte_igb_stats_strings[0]))
452 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
453 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
454 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
455 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
456 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
457 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
460 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
461 sizeof(rte_igbvf_stats_strings[0]))
464 * Atomically reads the link status information from global
465 * structure rte_eth_dev.
468 * - Pointer to the structure rte_eth_dev to read from.
469 * - Pointer to the buffer to be saved with the link status.
472 * - On success, zero.
473 * - On failure, negative value.
476 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
477 struct rte_eth_link *link)
479 struct rte_eth_link *dst = link;
480 struct rte_eth_link *src = &(dev->data->dev_link);
482 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
483 *(uint64_t *)src) == 0)
490 * Atomically writes the link status information into global
491 * structure rte_eth_dev.
494 * - Pointer to the structure rte_eth_dev to read from.
495 * - Pointer to the buffer to be saved with the link status.
498 * - On success, zero.
499 * - On failure, negative value.
502 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
503 struct rte_eth_link *link)
505 struct rte_eth_link *dst = &(dev->data->dev_link);
506 struct rte_eth_link *src = link;
508 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
509 *(uint64_t *)src) == 0)
516 igb_intr_enable(struct rte_eth_dev *dev)
518 struct e1000_interrupt *intr =
519 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
520 struct e1000_hw *hw =
521 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
523 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
524 E1000_WRITE_FLUSH(hw);
528 igb_intr_disable(struct e1000_hw *hw)
530 E1000_WRITE_REG(hw, E1000_IMC, ~0);
531 E1000_WRITE_FLUSH(hw);
534 static inline int32_t
535 igb_pf_reset_hw(struct e1000_hw *hw)
540 status = e1000_reset_hw(hw);
542 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
543 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
544 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
545 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
546 E1000_WRITE_FLUSH(hw);
552 igb_identify_hardware(struct rte_eth_dev *dev)
554 struct e1000_hw *hw =
555 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
557 hw->vendor_id = dev->pci_dev->id.vendor_id;
558 hw->device_id = dev->pci_dev->id.device_id;
559 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
560 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
562 e1000_set_mac_type(hw);
564 /* need to check if it is a vf device below */
568 igb_reset_swfw_lock(struct e1000_hw *hw)
573 * Do mac ops initialization manually here, since we will need
574 * some function pointers set by this call.
576 ret_val = e1000_init_mac_params(hw);
581 * SMBI lock should not fail in this early stage. If this is the case,
582 * it is due to an improper exit of the application.
583 * So force the release of the faulty lock.
585 if (e1000_get_hw_semaphore_generic(hw) < 0) {
586 PMD_DRV_LOG(DEBUG, "SMBI lock released");
588 e1000_put_hw_semaphore_generic(hw);
590 if (hw->mac.ops.acquire_swfw_sync != NULL) {
594 * Phy lock should not fail in this early stage. If this is the case,
595 * it is due to an improper exit of the application.
596 * So force the release of the faulty lock.
598 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
599 if (hw->bus.func > E1000_FUNC_1)
601 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
602 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
605 hw->mac.ops.release_swfw_sync(hw, mask);
608 * This one is more tricky since it is common to all ports; but
609 * swfw_sync retries last long enough (1s) to be almost sure that if
610 * lock can not be taken it is due to an improper lock of the
613 mask = E1000_SWFW_EEP_SM;
614 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
615 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
617 hw->mac.ops.release_swfw_sync(hw, mask);
620 return E1000_SUCCESS;
624 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
627 struct rte_pci_device *pci_dev;
628 struct e1000_hw *hw =
629 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
630 struct e1000_vfta * shadow_vfta =
631 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
632 struct e1000_filter_info *filter_info =
633 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
634 struct e1000_adapter *adapter =
635 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
639 pci_dev = eth_dev->pci_dev;
641 rte_eth_copy_pci_info(eth_dev, pci_dev);
643 eth_dev->dev_ops = ð_igb_ops;
644 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
645 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
647 /* for secondary processes, we don't initialise any further as primary
648 * has already done this work. Only check we don't need a different
650 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
651 if (eth_dev->data->scattered_rx)
652 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
656 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
658 igb_identify_hardware(eth_dev);
659 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
664 e1000_get_bus_info(hw);
666 /* Reset any pending lock */
667 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
672 /* Finish initialization */
673 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
679 hw->phy.autoneg_wait_to_complete = 0;
680 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
683 if (hw->phy.media_type == e1000_media_type_copper) {
684 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
685 hw->phy.disable_polarity_correction = 0;
686 hw->phy.ms_type = e1000_ms_hw_default;
690 * Start from a known state, this is important in reading the nvm
695 /* Make sure we have a good EEPROM before we read from it */
696 if (e1000_validate_nvm_checksum(hw) < 0) {
698 * Some PCI-E parts fail the first check due to
699 * the link being in sleep state, call it again,
700 * if it fails a second time its a real issue.
702 if (e1000_validate_nvm_checksum(hw) < 0) {
703 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
709 /* Read the permanent MAC address out of the EEPROM */
710 if (e1000_read_mac_addr(hw) != 0) {
711 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
716 /* Allocate memory for storing MAC addresses */
717 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
718 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
719 if (eth_dev->data->mac_addrs == NULL) {
720 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
721 "store MAC addresses",
722 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
727 /* Copy the permanent MAC address */
728 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
730 /* initialize the vfta */
731 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
733 /* Now initialize the hardware */
734 if (igb_hardware_init(hw) != 0) {
735 PMD_INIT_LOG(ERR, "Hardware initialization failed");
736 rte_free(eth_dev->data->mac_addrs);
737 eth_dev->data->mac_addrs = NULL;
741 hw->mac.get_link_status = 1;
742 adapter->stopped = 0;
744 /* Indicate SOL/IDER usage */
745 if (e1000_check_reset_block(hw) < 0) {
746 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
750 /* initialize PF if max_vfs not zero */
751 igb_pf_host_init(eth_dev);
753 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
754 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
755 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
756 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
757 E1000_WRITE_FLUSH(hw);
759 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
760 eth_dev->data->port_id, pci_dev->id.vendor_id,
761 pci_dev->id.device_id);
763 /* enable support intr */
764 igb_intr_enable(eth_dev);
766 TAILQ_INIT(&filter_info->flex_list);
767 filter_info->flex_mask = 0;
768 TAILQ_INIT(&filter_info->twotuple_list);
769 filter_info->twotuple_mask = 0;
770 TAILQ_INIT(&filter_info->fivetuple_list);
771 filter_info->fivetuple_mask = 0;
776 igb_hw_control_release(hw);
782 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
784 struct rte_pci_device *pci_dev;
786 struct e1000_adapter *adapter =
787 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
789 PMD_INIT_FUNC_TRACE();
791 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
794 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
795 pci_dev = eth_dev->pci_dev;
797 if (adapter->stopped == 0)
798 eth_igb_close(eth_dev);
800 eth_dev->dev_ops = NULL;
801 eth_dev->rx_pkt_burst = NULL;
802 eth_dev->tx_pkt_burst = NULL;
804 /* Reset any pending lock */
805 igb_reset_swfw_lock(hw);
807 rte_free(eth_dev->data->mac_addrs);
808 eth_dev->data->mac_addrs = NULL;
810 /* uninitialize PF if max_vfs not zero */
811 igb_pf_host_uninit(eth_dev);
813 /* disable uio intr before callback unregister */
814 rte_intr_disable(&(pci_dev->intr_handle));
815 rte_intr_callback_unregister(&(pci_dev->intr_handle),
816 eth_igb_interrupt_handler, (void *)eth_dev);
822 * Virtual Function device init
825 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
827 struct rte_pci_device *pci_dev;
828 struct e1000_adapter *adapter =
829 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
830 struct e1000_hw *hw =
831 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
834 PMD_INIT_FUNC_TRACE();
836 eth_dev->dev_ops = &igbvf_eth_dev_ops;
837 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
838 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
840 /* for secondary processes, we don't initialise any further as primary
841 * has already done this work. Only check we don't need a different
843 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
844 if (eth_dev->data->scattered_rx)
845 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
849 pci_dev = eth_dev->pci_dev;
851 rte_eth_copy_pci_info(eth_dev, pci_dev);
853 hw->device_id = pci_dev->id.device_id;
854 hw->vendor_id = pci_dev->id.vendor_id;
855 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
856 adapter->stopped = 0;
858 /* Initialize the shared code (base driver) */
859 diag = e1000_setup_init_funcs(hw, TRUE);
861 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
866 /* init_mailbox_params */
867 hw->mbx.ops.init_params(hw);
869 /* Disable the interrupts for VF */
870 igbvf_intr_disable(hw);
872 diag = hw->mac.ops.reset_hw(hw);
874 /* Allocate memory for storing MAC addresses */
875 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
876 hw->mac.rar_entry_count, 0);
877 if (eth_dev->data->mac_addrs == NULL) {
879 "Failed to allocate %d bytes needed to store MAC "
881 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
885 /* Copy the permanent MAC address */
886 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
887 ð_dev->data->mac_addrs[0]);
889 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
891 eth_dev->data->port_id, pci_dev->id.vendor_id,
892 pci_dev->id.device_id, "igb_mac_82576_vf");
898 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
900 struct e1000_adapter *adapter =
901 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
903 PMD_INIT_FUNC_TRACE();
905 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
908 if (adapter->stopped == 0)
909 igbvf_dev_close(eth_dev);
911 eth_dev->dev_ops = NULL;
912 eth_dev->rx_pkt_burst = NULL;
913 eth_dev->tx_pkt_burst = NULL;
915 rte_free(eth_dev->data->mac_addrs);
916 eth_dev->data->mac_addrs = NULL;
921 static struct eth_driver rte_igb_pmd = {
923 .name = "rte_igb_pmd",
924 .id_table = pci_id_igb_map,
925 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
926 RTE_PCI_DRV_DETACHABLE,
928 .eth_dev_init = eth_igb_dev_init,
929 .eth_dev_uninit = eth_igb_dev_uninit,
930 .dev_private_size = sizeof(struct e1000_adapter),
934 * virtual function driver struct
936 static struct eth_driver rte_igbvf_pmd = {
938 .name = "rte_igbvf_pmd",
939 .id_table = pci_id_igbvf_map,
940 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
942 .eth_dev_init = eth_igbvf_dev_init,
943 .eth_dev_uninit = eth_igbvf_dev_uninit,
944 .dev_private_size = sizeof(struct e1000_adapter),
948 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
950 rte_eth_driver_register(&rte_igb_pmd);
955 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
957 struct e1000_hw *hw =
958 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
959 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
960 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
961 rctl |= E1000_RCTL_VFE;
962 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
966 * VF Driver initialization routine.
967 * Invoked one at EAL init time.
968 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
971 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
973 PMD_INIT_FUNC_TRACE();
975 rte_eth_driver_register(&rte_igbvf_pmd);
980 igb_check_mq_mode(struct rte_eth_dev *dev)
982 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
983 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
984 uint16_t nb_rx_q = dev->data->nb_rx_queues;
985 uint16_t nb_tx_q = dev->data->nb_rx_queues;
987 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
988 tx_mq_mode == ETH_MQ_TX_DCB ||
989 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
990 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
993 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
994 /* Check multi-queue mode.
995 * To no break software we accept ETH_MQ_RX_NONE as this might
996 * be used to turn off VLAN filter.
999 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1000 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1001 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1002 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1004 /* Only support one queue on VFs.
1005 * RSS together with SRIOV is not supported.
1007 PMD_INIT_LOG(ERR, "SRIOV is active,"
1008 " wrong mq_mode rx %d.",
1012 /* TX mode is not used here, so mode might be ignored.*/
1013 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1014 /* SRIOV only works in VMDq enable mode */
1015 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1016 " TX mode %d is not supported. "
1017 " Driver will behave as %d mode.",
1018 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1021 /* check valid queue number */
1022 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1023 PMD_INIT_LOG(ERR, "SRIOV is active,"
1024 " only support one queue on VFs.");
1028 /* To no break software that set invalid mode, only display
1029 * warning if invalid mode is used.
1031 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1032 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1033 rx_mq_mode != ETH_MQ_RX_RSS) {
1034 /* RSS together with VMDq not supported*/
1035 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1040 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1041 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1042 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1043 " Due to txmode is meaningless in this"
1044 " driver, just ignore.",
1052 eth_igb_configure(struct rte_eth_dev *dev)
1054 struct e1000_interrupt *intr =
1055 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1058 PMD_INIT_FUNC_TRACE();
1060 /* multipe queue mode checking */
1061 ret = igb_check_mq_mode(dev);
1063 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1068 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1069 PMD_INIT_FUNC_TRACE();
1075 eth_igb_start(struct rte_eth_dev *dev)
1077 struct e1000_hw *hw =
1078 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1079 struct e1000_adapter *adapter =
1080 E1000_DEV_PRIVATE(dev->data->dev_private);
1081 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1083 uint32_t intr_vector = 0;
1086 PMD_INIT_FUNC_TRACE();
1088 /* Power up the phy. Needed to make the link go Up */
1089 e1000_power_up_phy(hw);
1092 * Packet Buffer Allocation (PBA)
1093 * Writing PBA sets the receive portion of the buffer
1094 * the remainder is used for the transmit buffer.
1096 if (hw->mac.type == e1000_82575) {
1099 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1100 E1000_WRITE_REG(hw, E1000_PBA, pba);
1103 /* Put the address into the Receive Address Array */
1104 e1000_rar_set(hw, hw->mac.addr, 0);
1106 /* Initialize the hardware */
1107 if (igb_hardware_init(hw)) {
1108 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1111 adapter->stopped = 0;
1113 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1115 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1116 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1117 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1118 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1119 E1000_WRITE_FLUSH(hw);
1121 /* configure PF module if SRIOV enabled */
1122 igb_pf_host_configure(dev);
1124 /* check and configure queue intr-vector mapping */
1125 if (dev->data->dev_conf.intr_conf.rxq != 0)
1126 intr_vector = dev->data->nb_rx_queues;
1128 if (rte_intr_efd_enable(intr_handle, intr_vector))
1131 if (rte_intr_dp_is_en(intr_handle)) {
1132 intr_handle->intr_vec =
1133 rte_zmalloc("intr_vec",
1134 dev->data->nb_rx_queues * sizeof(int), 0);
1135 if (intr_handle->intr_vec == NULL) {
1136 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1137 " intr_vec\n", dev->data->nb_rx_queues);
1142 /* confiugre msix for rx interrupt */
1143 eth_igb_configure_msix_intr(dev);
1145 /* Configure for OS presence */
1146 igb_init_manageability(hw);
1148 eth_igb_tx_init(dev);
1150 /* This can fail when allocating mbufs for descriptor rings */
1151 ret = eth_igb_rx_init(dev);
1153 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1154 igb_dev_clear_queues(dev);
1158 e1000_clear_hw_cntrs_base_generic(hw);
1161 * VLAN Offload Settings
1163 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1164 ETH_VLAN_EXTEND_MASK;
1165 eth_igb_vlan_offload_set(dev, mask);
1167 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1168 /* Enable VLAN filter since VMDq always use VLAN filter */
1169 igb_vmdq_vlan_hw_filter_enable(dev);
1172 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1173 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1174 (hw->mac.type == e1000_i211)) {
1175 /* Configure EITR with the maximum possible value (0xFFFF) */
1176 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1179 /* Setup link speed and duplex */
1180 switch (dev->data->dev_conf.link_speed) {
1181 case ETH_LINK_SPEED_AUTONEG:
1182 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1183 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1184 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1185 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
1186 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1187 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
1189 goto error_invalid_config;
1191 case ETH_LINK_SPEED_10:
1192 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1193 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
1194 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1195 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
1196 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1197 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1199 goto error_invalid_config;
1201 case ETH_LINK_SPEED_100:
1202 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1203 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1204 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1205 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1206 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1207 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1209 goto error_invalid_config;
1211 case ETH_LINK_SPEED_1000:
1212 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1213 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1214 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1216 goto error_invalid_config;
1218 case ETH_LINK_SPEED_10000:
1220 goto error_invalid_config;
1222 e1000_setup_link(hw);
1224 /* check if lsc interrupt feature is enabled */
1225 if (dev->data->dev_conf.intr_conf.lsc != 0) {
1226 if (rte_intr_allow_others(intr_handle)) {
1227 rte_intr_callback_register(intr_handle,
1228 eth_igb_interrupt_handler,
1230 eth_igb_lsc_interrupt_setup(dev);
1232 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1233 " no intr multiplex\n");
1236 /* check if rxq interrupt is enabled */
1237 if (dev->data->dev_conf.intr_conf.rxq != 0)
1238 eth_igb_rxq_interrupt_setup(dev);
1240 /* enable uio/vfio intr/eventfd mapping */
1241 rte_intr_enable(intr_handle);
1243 /* resume enabled intr since hw reset */
1244 igb_intr_enable(dev);
1246 PMD_INIT_LOG(DEBUG, "<<");
1250 error_invalid_config:
1251 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1252 dev->data->dev_conf.link_speed,
1253 dev->data->dev_conf.link_duplex, dev->data->port_id);
1254 igb_dev_clear_queues(dev);
1258 /*********************************************************************
1260 * This routine disables all traffic on the adapter by issuing a
1261 * global reset on the MAC.
1263 **********************************************************************/
1265 eth_igb_stop(struct rte_eth_dev *dev)
1267 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1268 struct e1000_filter_info *filter_info =
1269 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1270 struct rte_eth_link link;
1271 struct e1000_flex_filter *p_flex;
1272 struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1273 struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1274 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1276 igb_intr_disable(hw);
1278 /* disable intr eventfd mapping */
1279 rte_intr_disable(intr_handle);
1281 igb_pf_reset_hw(hw);
1282 E1000_WRITE_REG(hw, E1000_WUC, 0);
1284 /* Set bit for Go Link disconnect */
1285 if (hw->mac.type >= e1000_82580) {
1288 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1289 phpm_reg |= E1000_82580_PM_GO_LINKD;
1290 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1293 /* Power down the phy. Needed to make the link go Down */
1294 if (hw->phy.media_type == e1000_media_type_copper)
1295 e1000_power_down_phy(hw);
1297 e1000_shutdown_fiber_serdes_link(hw);
1299 igb_dev_clear_queues(dev);
1301 /* clear the recorded link status */
1302 memset(&link, 0, sizeof(link));
1303 rte_igb_dev_atomic_write_link_status(dev, &link);
1305 /* Remove all flex filters of the device */
1306 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1307 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1310 filter_info->flex_mask = 0;
1312 /* Remove all ntuple filters of the device */
1313 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1314 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1315 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1316 TAILQ_REMOVE(&filter_info->fivetuple_list,
1320 filter_info->fivetuple_mask = 0;
1321 for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1322 p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1323 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1324 TAILQ_REMOVE(&filter_info->twotuple_list,
1328 filter_info->twotuple_mask = 0;
1330 /* Clean datapath event and queue/vec mapping */
1331 rte_intr_efd_disable(intr_handle);
1332 if (intr_handle->intr_vec != NULL) {
1333 rte_free(intr_handle->intr_vec);
1334 intr_handle->intr_vec = NULL;
1339 eth_igb_close(struct rte_eth_dev *dev)
1341 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1342 struct e1000_adapter *adapter =
1343 E1000_DEV_PRIVATE(dev->data->dev_private);
1344 struct rte_eth_link link;
1345 struct rte_pci_device *pci_dev;
1348 adapter->stopped = 1;
1350 e1000_phy_hw_reset(hw);
1351 igb_release_manageability(hw);
1352 igb_hw_control_release(hw);
1354 /* Clear bit for Go Link disconnect */
1355 if (hw->mac.type >= e1000_82580) {
1358 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1359 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1360 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1363 igb_dev_free_queues(dev);
1365 pci_dev = dev->pci_dev;
1366 if (pci_dev->intr_handle.intr_vec) {
1367 rte_free(pci_dev->intr_handle.intr_vec);
1368 pci_dev->intr_handle.intr_vec = NULL;
1371 memset(&link, 0, sizeof(link));
1372 rte_igb_dev_atomic_write_link_status(dev, &link);
1376 igb_get_rx_buffer_size(struct e1000_hw *hw)
1378 uint32_t rx_buf_size;
1379 if (hw->mac.type == e1000_82576) {
1380 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1381 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1382 /* PBS needs to be translated according to a lookup table */
1383 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1384 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1385 rx_buf_size = (rx_buf_size << 10);
1386 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1387 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1389 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1395 /*********************************************************************
1397 * Initialize the hardware
1399 **********************************************************************/
1401 igb_hardware_init(struct e1000_hw *hw)
1403 uint32_t rx_buf_size;
1406 /* Let the firmware know the OS is in control */
1407 igb_hw_control_acquire(hw);
1410 * These parameters control the automatic generation (Tx) and
1411 * response (Rx) to Ethernet PAUSE frames.
1412 * - High water mark should allow for at least two standard size (1518)
1413 * frames to be received after sending an XOFF.
1414 * - Low water mark works best when it is very near the high water mark.
1415 * This allows the receiver to restart by sending XON when it has
1416 * drained a bit. Here we use an arbitrary value of 1500 which will
1417 * restart after one full frame is pulled from the buffer. There
1418 * could be several smaller frames in the buffer and if so they will
1419 * not trigger the XON until their total number reduces the buffer
1421 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1423 rx_buf_size = igb_get_rx_buffer_size(hw);
1425 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1426 hw->fc.low_water = hw->fc.high_water - 1500;
1427 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1428 hw->fc.send_xon = 1;
1430 /* Set Flow control, use the tunable location if sane */
1431 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1432 hw->fc.requested_mode = igb_fc_setting;
1434 hw->fc.requested_mode = e1000_fc_none;
1436 /* Issue a global reset */
1437 igb_pf_reset_hw(hw);
1438 E1000_WRITE_REG(hw, E1000_WUC, 0);
1440 diag = e1000_init_hw(hw);
1444 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1445 e1000_get_phy_info(hw);
1446 e1000_check_for_link(hw);
1451 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1453 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1457 if(hw->phy.media_type == e1000_media_type_copper ||
1458 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1460 E1000_READ_REG(hw,E1000_SYMERRS);
1461 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1464 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1465 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1466 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1467 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1469 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1470 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1471 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1472 stats->dc += E1000_READ_REG(hw, E1000_DC);
1473 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1474 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1475 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1477 ** For watchdog management we need to know if we have been
1478 ** paused during the last interval, so capture that here.
1480 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1481 stats->xoffrxc += pause_frames;
1482 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1483 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1484 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1485 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1486 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1487 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1488 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1489 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1490 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1491 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1492 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1493 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1495 /* For the 64-bit byte counters the low dword must be read first. */
1496 /* Both registers clear on the read of the high dword */
1498 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1499 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1500 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1501 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1503 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1504 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1505 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1506 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1507 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1509 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1510 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1511 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1512 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1514 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1515 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1516 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1517 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1518 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1519 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1520 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1521 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1522 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1523 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1525 /* Interrupt Counts */
1527 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1528 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1529 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1530 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1531 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1532 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1533 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1534 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1535 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1537 /* Host to Card Statistics */
1539 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1540 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1541 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1542 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1543 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1544 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1545 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1546 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1547 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1548 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1549 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1550 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1551 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1552 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1554 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1555 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1556 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1557 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1558 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1559 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1563 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1565 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1566 struct e1000_hw_stats *stats =
1567 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1569 igb_read_stats_registers(hw, stats);
1571 if (rte_stats == NULL)
1575 rte_stats->ibadcrc = stats->crcerrs;
1576 rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1577 rte_stats->imissed = stats->mpc;
1578 rte_stats->ierrors = rte_stats->ibadcrc +
1579 rte_stats->ibadlen +
1580 rte_stats->imissed +
1581 stats->rxerrc + stats->algnerrc + stats->cexterr;
1584 rte_stats->oerrors = stats->ecol + stats->latecol;
1586 /* XON/XOFF pause frames */
1587 rte_stats->tx_pause_xon = stats->xontxc;
1588 rte_stats->rx_pause_xon = stats->xonrxc;
1589 rte_stats->tx_pause_xoff = stats->xofftxc;
1590 rte_stats->rx_pause_xoff = stats->xoffrxc;
1592 rte_stats->ipackets = stats->gprc;
1593 rte_stats->opackets = stats->gptc;
1594 rte_stats->ibytes = stats->gorc;
1595 rte_stats->obytes = stats->gotc;
1599 eth_igb_stats_reset(struct rte_eth_dev *dev)
1601 struct e1000_hw_stats *hw_stats =
1602 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1604 /* HW registers are cleared on read */
1605 eth_igb_stats_get(dev, NULL);
1607 /* Reset software totals */
1608 memset(hw_stats, 0, sizeof(*hw_stats));
1612 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1614 struct e1000_hw_stats *stats =
1615 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1617 /* HW registers are cleared on read */
1618 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1620 /* Reset software totals */
1621 memset(stats, 0, sizeof(*stats));
1625 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1628 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1629 struct e1000_hw_stats *hw_stats =
1630 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1633 if (n < IGB_NB_XSTATS)
1634 return IGB_NB_XSTATS;
1636 igb_read_stats_registers(hw, hw_stats);
1638 /* If this is a reset xstats is NULL, and we have cleared the
1639 * registers by reading them.
1644 /* Extended stats */
1645 for (i = 0; i < IGB_NB_XSTATS; i++) {
1646 snprintf(xstats[i].name, sizeof(xstats[i].name),
1647 "%s", rte_igb_stats_strings[i].name);
1648 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1649 rte_igb_stats_strings[i].offset);
1652 return IGB_NB_XSTATS;
1656 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1658 /* Good Rx packets, include VF loopback */
1659 UPDATE_VF_STAT(E1000_VFGPRC,
1660 hw_stats->last_gprc, hw_stats->gprc);
1662 /* Good Rx octets, include VF loopback */
1663 UPDATE_VF_STAT(E1000_VFGORC,
1664 hw_stats->last_gorc, hw_stats->gorc);
1666 /* Good Tx packets, include VF loopback */
1667 UPDATE_VF_STAT(E1000_VFGPTC,
1668 hw_stats->last_gptc, hw_stats->gptc);
1670 /* Good Tx octets, include VF loopback */
1671 UPDATE_VF_STAT(E1000_VFGOTC,
1672 hw_stats->last_gotc, hw_stats->gotc);
1674 /* Rx Multicst packets */
1675 UPDATE_VF_STAT(E1000_VFMPRC,
1676 hw_stats->last_mprc, hw_stats->mprc);
1678 /* Good Rx loopback packets */
1679 UPDATE_VF_STAT(E1000_VFGPRLBC,
1680 hw_stats->last_gprlbc, hw_stats->gprlbc);
1682 /* Good Rx loopback octets */
1683 UPDATE_VF_STAT(E1000_VFGORLBC,
1684 hw_stats->last_gorlbc, hw_stats->gorlbc);
1686 /* Good Tx loopback packets */
1687 UPDATE_VF_STAT(E1000_VFGPTLBC,
1688 hw_stats->last_gptlbc, hw_stats->gptlbc);
1690 /* Good Tx loopback octets */
1691 UPDATE_VF_STAT(E1000_VFGOTLBC,
1692 hw_stats->last_gotlbc, hw_stats->gotlbc);
1696 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1699 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1700 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1701 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1704 if (n < IGBVF_NB_XSTATS)
1705 return IGBVF_NB_XSTATS;
1707 igbvf_read_stats_registers(hw, hw_stats);
1712 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1713 snprintf(xstats[i].name, sizeof(xstats[i].name), "%s",
1714 rte_igbvf_stats_strings[i].name);
1715 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1716 rte_igbvf_stats_strings[i].offset);
1719 return IGBVF_NB_XSTATS;
1723 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1725 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1727 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1729 igbvf_read_stats_registers(hw, hw_stats);
1731 if (rte_stats == NULL)
1734 rte_stats->ipackets = hw_stats->gprc;
1735 rte_stats->ibytes = hw_stats->gorc;
1736 rte_stats->opackets = hw_stats->gptc;
1737 rte_stats->obytes = hw_stats->gotc;
1738 rte_stats->imcasts = hw_stats->mprc;
1739 rte_stats->ilbpackets = hw_stats->gprlbc;
1740 rte_stats->ilbbytes = hw_stats->gorlbc;
1741 rte_stats->olbpackets = hw_stats->gptlbc;
1742 rte_stats->olbbytes = hw_stats->gotlbc;
1746 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1748 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1749 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1751 /* Sync HW register to the last stats */
1752 eth_igbvf_stats_get(dev, NULL);
1754 /* reset HW current stats*/
1755 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1756 offsetof(struct e1000_vf_stats, gprc));
1760 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1762 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1764 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1765 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1766 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1767 dev_info->rx_offload_capa =
1768 DEV_RX_OFFLOAD_VLAN_STRIP |
1769 DEV_RX_OFFLOAD_IPV4_CKSUM |
1770 DEV_RX_OFFLOAD_UDP_CKSUM |
1771 DEV_RX_OFFLOAD_TCP_CKSUM;
1772 dev_info->tx_offload_capa =
1773 DEV_TX_OFFLOAD_VLAN_INSERT |
1774 DEV_TX_OFFLOAD_IPV4_CKSUM |
1775 DEV_TX_OFFLOAD_UDP_CKSUM |
1776 DEV_TX_OFFLOAD_TCP_CKSUM |
1777 DEV_TX_OFFLOAD_SCTP_CKSUM |
1778 DEV_TX_OFFLOAD_TCP_TSO;
1780 switch (hw->mac.type) {
1782 dev_info->max_rx_queues = 4;
1783 dev_info->max_tx_queues = 4;
1784 dev_info->max_vmdq_pools = 0;
1788 dev_info->max_rx_queues = 16;
1789 dev_info->max_tx_queues = 16;
1790 dev_info->max_vmdq_pools = ETH_8_POOLS;
1791 dev_info->vmdq_queue_num = 16;
1795 dev_info->max_rx_queues = 8;
1796 dev_info->max_tx_queues = 8;
1797 dev_info->max_vmdq_pools = ETH_8_POOLS;
1798 dev_info->vmdq_queue_num = 8;
1802 dev_info->max_rx_queues = 8;
1803 dev_info->max_tx_queues = 8;
1804 dev_info->max_vmdq_pools = ETH_8_POOLS;
1805 dev_info->vmdq_queue_num = 8;
1809 dev_info->max_rx_queues = 8;
1810 dev_info->max_tx_queues = 8;
1814 dev_info->max_rx_queues = 4;
1815 dev_info->max_tx_queues = 4;
1816 dev_info->max_vmdq_pools = 0;
1820 dev_info->max_rx_queues = 2;
1821 dev_info->max_tx_queues = 2;
1822 dev_info->max_vmdq_pools = 0;
1826 /* Should not happen */
1829 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1830 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1831 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1833 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1835 .pthresh = IGB_DEFAULT_RX_PTHRESH,
1836 .hthresh = IGB_DEFAULT_RX_HTHRESH,
1837 .wthresh = IGB_DEFAULT_RX_WTHRESH,
1839 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1843 dev_info->default_txconf = (struct rte_eth_txconf) {
1845 .pthresh = IGB_DEFAULT_TX_PTHRESH,
1846 .hthresh = IGB_DEFAULT_TX_HTHRESH,
1847 .wthresh = IGB_DEFAULT_TX_WTHRESH,
1852 dev_info->rx_desc_lim = rx_desc_lim;
1853 dev_info->tx_desc_lim = tx_desc_lim;
1857 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1859 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1861 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1862 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1863 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1864 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1865 DEV_RX_OFFLOAD_IPV4_CKSUM |
1866 DEV_RX_OFFLOAD_UDP_CKSUM |
1867 DEV_RX_OFFLOAD_TCP_CKSUM;
1868 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1869 DEV_TX_OFFLOAD_IPV4_CKSUM |
1870 DEV_TX_OFFLOAD_UDP_CKSUM |
1871 DEV_TX_OFFLOAD_TCP_CKSUM |
1872 DEV_TX_OFFLOAD_SCTP_CKSUM |
1873 DEV_TX_OFFLOAD_TCP_TSO;
1874 switch (hw->mac.type) {
1876 dev_info->max_rx_queues = 2;
1877 dev_info->max_tx_queues = 2;
1879 case e1000_vfadapt_i350:
1880 dev_info->max_rx_queues = 1;
1881 dev_info->max_tx_queues = 1;
1884 /* Should not happen */
1888 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1890 .pthresh = IGB_DEFAULT_RX_PTHRESH,
1891 .hthresh = IGB_DEFAULT_RX_HTHRESH,
1892 .wthresh = IGB_DEFAULT_RX_WTHRESH,
1894 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1898 dev_info->default_txconf = (struct rte_eth_txconf) {
1900 .pthresh = IGB_DEFAULT_TX_PTHRESH,
1901 .hthresh = IGB_DEFAULT_TX_HTHRESH,
1902 .wthresh = IGB_DEFAULT_TX_WTHRESH,
1907 dev_info->rx_desc_lim = rx_desc_lim;
1908 dev_info->tx_desc_lim = tx_desc_lim;
1911 /* return 0 means link status changed, -1 means not changed */
1913 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1915 struct e1000_hw *hw =
1916 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917 struct rte_eth_link link, old;
1918 int link_check, count;
1921 hw->mac.get_link_status = 1;
1923 /* possible wait-to-complete in up to 9 seconds */
1924 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1925 /* Read the real link status */
1926 switch (hw->phy.media_type) {
1927 case e1000_media_type_copper:
1928 /* Do the work to read phy */
1929 e1000_check_for_link(hw);
1930 link_check = !hw->mac.get_link_status;
1933 case e1000_media_type_fiber:
1934 e1000_check_for_link(hw);
1935 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1939 case e1000_media_type_internal_serdes:
1940 e1000_check_for_link(hw);
1941 link_check = hw->mac.serdes_has_link;
1944 /* VF device is type_unknown */
1945 case e1000_media_type_unknown:
1946 eth_igbvf_link_update(hw);
1947 link_check = !hw->mac.get_link_status;
1953 if (link_check || wait_to_complete == 0)
1955 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1957 memset(&link, 0, sizeof(link));
1958 rte_igb_dev_atomic_read_link_status(dev, &link);
1961 /* Now we check if a transition has happened */
1963 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1965 link.link_status = 1;
1966 } else if (!link_check) {
1967 link.link_speed = 0;
1968 link.link_duplex = 0;
1969 link.link_status = 0;
1971 rte_igb_dev_atomic_write_link_status(dev, &link);
1974 if (old.link_status == link.link_status)
1982 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1983 * For ASF and Pass Through versions of f/w this means
1984 * that the driver is loaded.
1987 igb_hw_control_acquire(struct e1000_hw *hw)
1991 /* Let firmware know the driver has taken over */
1992 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1993 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1997 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1998 * For ASF and Pass Through versions of f/w this means that the
1999 * driver is no longer loaded.
2002 igb_hw_control_release(struct e1000_hw *hw)
2006 /* Let firmware taken over control of h/w */
2007 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2008 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2009 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2013 * Bit of a misnomer, what this really means is
2014 * to enable OS management of the system... aka
2015 * to disable special hardware management features.
2018 igb_init_manageability(struct e1000_hw *hw)
2020 if (e1000_enable_mng_pass_thru(hw)) {
2021 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2022 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2024 /* disable hardware interception of ARP */
2025 manc &= ~(E1000_MANC_ARP_EN);
2027 /* enable receiving management packets to the host */
2028 manc |= E1000_MANC_EN_MNG2HOST;
2029 manc2h |= 1 << 5; /* Mng Port 623 */
2030 manc2h |= 1 << 6; /* Mng Port 664 */
2031 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2032 E1000_WRITE_REG(hw, E1000_MANC, manc);
2037 igb_release_manageability(struct e1000_hw *hw)
2039 if (e1000_enable_mng_pass_thru(hw)) {
2040 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2042 manc |= E1000_MANC_ARP_EN;
2043 manc &= ~E1000_MANC_EN_MNG2HOST;
2045 E1000_WRITE_REG(hw, E1000_MANC, manc);
2050 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2052 struct e1000_hw *hw =
2053 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2056 rctl = E1000_READ_REG(hw, E1000_RCTL);
2057 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2058 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2062 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2064 struct e1000_hw *hw =
2065 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2068 rctl = E1000_READ_REG(hw, E1000_RCTL);
2069 rctl &= (~E1000_RCTL_UPE);
2070 if (dev->data->all_multicast == 1)
2071 rctl |= E1000_RCTL_MPE;
2073 rctl &= (~E1000_RCTL_MPE);
2074 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2078 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2080 struct e1000_hw *hw =
2081 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084 rctl = E1000_READ_REG(hw, E1000_RCTL);
2085 rctl |= E1000_RCTL_MPE;
2086 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2090 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2092 struct e1000_hw *hw =
2093 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2096 if (dev->data->promiscuous == 1)
2097 return; /* must remain in all_multicast mode */
2098 rctl = E1000_READ_REG(hw, E1000_RCTL);
2099 rctl &= (~E1000_RCTL_MPE);
2100 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2104 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2106 struct e1000_hw *hw =
2107 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2108 struct e1000_vfta * shadow_vfta =
2109 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2114 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2115 E1000_VFTA_ENTRY_MASK);
2116 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2117 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2122 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2124 /* update local VFTA copy */
2125 shadow_vfta->vfta[vid_idx] = vfta;
2131 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
2133 struct e1000_hw *hw =
2134 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2135 uint32_t reg = ETHER_TYPE_VLAN ;
2137 reg |= (tpid << 16);
2138 E1000_WRITE_REG(hw, E1000_VET, reg);
2142 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2144 struct e1000_hw *hw =
2145 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148 /* Filter Table Disable */
2149 reg = E1000_READ_REG(hw, E1000_RCTL);
2150 reg &= ~E1000_RCTL_CFIEN;
2151 reg &= ~E1000_RCTL_VFE;
2152 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2156 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2158 struct e1000_hw *hw =
2159 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2160 struct e1000_vfta * shadow_vfta =
2161 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2165 /* Filter Table Enable, CFI not used for packet acceptance */
2166 reg = E1000_READ_REG(hw, E1000_RCTL);
2167 reg &= ~E1000_RCTL_CFIEN;
2168 reg |= E1000_RCTL_VFE;
2169 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2171 /* restore VFTA table */
2172 for (i = 0; i < IGB_VFTA_SIZE; i++)
2173 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2177 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2179 struct e1000_hw *hw =
2180 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2183 /* VLAN Mode Disable */
2184 reg = E1000_READ_REG(hw, E1000_CTRL);
2185 reg &= ~E1000_CTRL_VME;
2186 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2190 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2192 struct e1000_hw *hw =
2193 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2196 /* VLAN Mode Enable */
2197 reg = E1000_READ_REG(hw, E1000_CTRL);
2198 reg |= E1000_CTRL_VME;
2199 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2203 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2205 struct e1000_hw *hw =
2206 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2209 /* CTRL_EXT: Extended VLAN */
2210 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2211 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2212 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2214 /* Update maximum packet length */
2215 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2216 E1000_WRITE_REG(hw, E1000_RLPML,
2217 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2222 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2224 struct e1000_hw *hw =
2225 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2228 /* CTRL_EXT: Extended VLAN */
2229 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2230 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2231 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2233 /* Update maximum packet length */
2234 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2235 E1000_WRITE_REG(hw, E1000_RLPML,
2236 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2241 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2243 if(mask & ETH_VLAN_STRIP_MASK){
2244 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2245 igb_vlan_hw_strip_enable(dev);
2247 igb_vlan_hw_strip_disable(dev);
2250 if(mask & ETH_VLAN_FILTER_MASK){
2251 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2252 igb_vlan_hw_filter_enable(dev);
2254 igb_vlan_hw_filter_disable(dev);
2257 if(mask & ETH_VLAN_EXTEND_MASK){
2258 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2259 igb_vlan_hw_extend_enable(dev);
2261 igb_vlan_hw_extend_disable(dev);
2267 * It enables the interrupt mask and then enable the interrupt.
2270 * Pointer to struct rte_eth_dev.
2273 * - On success, zero.
2274 * - On failure, a negative value.
2277 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2279 struct e1000_interrupt *intr =
2280 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2282 intr->mask |= E1000_ICR_LSC;
2287 /* It clears the interrupt causes and enables the interrupt.
2288 * It will be called once only during nic initialized.
2291 * Pointer to struct rte_eth_dev.
2294 * - On success, zero.
2295 * - On failure, a negative value.
2297 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2299 uint32_t mask, regval;
2300 struct e1000_hw *hw =
2301 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2302 struct rte_eth_dev_info dev_info;
2304 memset(&dev_info, 0, sizeof(dev_info));
2305 eth_igb_infos_get(dev, &dev_info);
2307 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2308 regval = E1000_READ_REG(hw, E1000_EIMS);
2309 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2315 * It reads ICR and gets interrupt causes, check it and set a bit flag
2316 * to update link status.
2319 * Pointer to struct rte_eth_dev.
2322 * - On success, zero.
2323 * - On failure, a negative value.
2326 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2329 struct e1000_hw *hw =
2330 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2331 struct e1000_interrupt *intr =
2332 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2334 igb_intr_disable(hw);
2336 /* read-on-clear nic registers here */
2337 icr = E1000_READ_REG(hw, E1000_ICR);
2340 if (icr & E1000_ICR_LSC) {
2341 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2344 if (icr & E1000_ICR_VMMB)
2345 intr->flags |= E1000_FLAG_MAILBOX;
2351 * It executes link_update after knowing an interrupt is prsent.
2354 * Pointer to struct rte_eth_dev.
2357 * - On success, zero.
2358 * - On failure, a negative value.
2361 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2363 struct e1000_hw *hw =
2364 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2365 struct e1000_interrupt *intr =
2366 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2367 uint32_t tctl, rctl;
2368 struct rte_eth_link link;
2371 if (intr->flags & E1000_FLAG_MAILBOX) {
2372 igb_pf_mbx_process(dev);
2373 intr->flags &= ~E1000_FLAG_MAILBOX;
2376 igb_intr_enable(dev);
2377 rte_intr_enable(&(dev->pci_dev->intr_handle));
2379 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2380 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2382 /* set get_link_status to check register later */
2383 hw->mac.get_link_status = 1;
2384 ret = eth_igb_link_update(dev, 0);
2386 /* check if link has changed */
2390 memset(&link, 0, sizeof(link));
2391 rte_igb_dev_atomic_read_link_status(dev, &link);
2392 if (link.link_status) {
2394 " Port %d: Link Up - speed %u Mbps - %s",
2396 (unsigned)link.link_speed,
2397 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2398 "full-duplex" : "half-duplex");
2400 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2401 dev->data->port_id);
2404 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2405 dev->pci_dev->addr.domain,
2406 dev->pci_dev->addr.bus,
2407 dev->pci_dev->addr.devid,
2408 dev->pci_dev->addr.function);
2409 tctl = E1000_READ_REG(hw, E1000_TCTL);
2410 rctl = E1000_READ_REG(hw, E1000_RCTL);
2411 if (link.link_status) {
2413 tctl |= E1000_TCTL_EN;
2414 rctl |= E1000_RCTL_EN;
2417 tctl &= ~E1000_TCTL_EN;
2418 rctl &= ~E1000_RCTL_EN;
2420 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2421 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2422 E1000_WRITE_FLUSH(hw);
2423 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2430 * Interrupt handler which shall be registered at first.
2433 * Pointer to interrupt handle.
2435 * The address of parameter (struct rte_eth_dev *) regsitered before.
2441 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2444 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2446 eth_igb_interrupt_get_status(dev);
2447 eth_igb_interrupt_action(dev);
2451 eth_igb_led_on(struct rte_eth_dev *dev)
2453 struct e1000_hw *hw;
2455 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2460 eth_igb_led_off(struct rte_eth_dev *dev)
2462 struct e1000_hw *hw;
2464 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2469 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2471 struct e1000_hw *hw;
2476 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2477 fc_conf->pause_time = hw->fc.pause_time;
2478 fc_conf->high_water = hw->fc.high_water;
2479 fc_conf->low_water = hw->fc.low_water;
2480 fc_conf->send_xon = hw->fc.send_xon;
2481 fc_conf->autoneg = hw->mac.autoneg;
2484 * Return rx_pause and tx_pause status according to actual setting of
2485 * the TFCE and RFCE bits in the CTRL register.
2487 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2488 if (ctrl & E1000_CTRL_TFCE)
2493 if (ctrl & E1000_CTRL_RFCE)
2498 if (rx_pause && tx_pause)
2499 fc_conf->mode = RTE_FC_FULL;
2501 fc_conf->mode = RTE_FC_RX_PAUSE;
2503 fc_conf->mode = RTE_FC_TX_PAUSE;
2505 fc_conf->mode = RTE_FC_NONE;
2511 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2513 struct e1000_hw *hw;
2515 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2521 uint32_t rx_buf_size;
2522 uint32_t max_high_water;
2525 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2526 if (fc_conf->autoneg != hw->mac.autoneg)
2528 rx_buf_size = igb_get_rx_buffer_size(hw);
2529 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2531 /* At least reserve one Ethernet frame for watermark */
2532 max_high_water = rx_buf_size - ETHER_MAX_LEN;
2533 if ((fc_conf->high_water > max_high_water) ||
2534 (fc_conf->high_water < fc_conf->low_water)) {
2535 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2536 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
2540 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2541 hw->fc.pause_time = fc_conf->pause_time;
2542 hw->fc.high_water = fc_conf->high_water;
2543 hw->fc.low_water = fc_conf->low_water;
2544 hw->fc.send_xon = fc_conf->send_xon;
2546 err = e1000_setup_link_generic(hw);
2547 if (err == E1000_SUCCESS) {
2549 /* check if we want to forward MAC frames - driver doesn't have native
2550 * capability to do that, so we'll write the registers ourselves */
2552 rctl = E1000_READ_REG(hw, E1000_RCTL);
2554 /* set or clear MFLCN.PMCF bit depending on configuration */
2555 if (fc_conf->mac_ctrl_frame_fwd != 0)
2556 rctl |= E1000_RCTL_PMCF;
2558 rctl &= ~E1000_RCTL_PMCF;
2560 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2561 E1000_WRITE_FLUSH(hw);
2566 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2570 #define E1000_RAH_POOLSEL_SHIFT (18)
2572 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2573 uint32_t index, __rte_unused uint32_t pool)
2575 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2578 e1000_rar_set(hw, mac_addr->addr_bytes, index);
2579 rah = E1000_READ_REG(hw, E1000_RAH(index));
2580 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2581 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2585 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2587 uint8_t addr[ETHER_ADDR_LEN];
2588 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2590 memset(addr, 0, sizeof(addr));
2592 e1000_rar_set(hw, addr, index);
2596 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2597 struct ether_addr *addr)
2599 eth_igb_rar_clear(dev, 0);
2601 eth_igb_rar_set(dev, (void *)addr, 0, 0);
2604 * Virtual Function operations
2607 igbvf_intr_disable(struct e1000_hw *hw)
2609 PMD_INIT_FUNC_TRACE();
2611 /* Clear interrupt mask to stop from interrupts being generated */
2612 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2614 E1000_WRITE_FLUSH(hw);
2618 igbvf_stop_adapter(struct rte_eth_dev *dev)
2622 struct rte_eth_dev_info dev_info;
2623 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2625 memset(&dev_info, 0, sizeof(dev_info));
2626 eth_igbvf_infos_get(dev, &dev_info);
2628 /* Clear interrupt mask to stop from interrupts being generated */
2629 igbvf_intr_disable(hw);
2631 /* Clear any pending interrupts, flush previous writes */
2632 E1000_READ_REG(hw, E1000_EICR);
2634 /* Disable the transmit unit. Each queue must be disabled. */
2635 for (i = 0; i < dev_info.max_tx_queues; i++)
2636 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2638 /* Disable the receive unit by stopping each queue */
2639 for (i = 0; i < dev_info.max_rx_queues; i++) {
2640 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2641 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2642 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2643 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2647 /* flush all queues disables */
2648 E1000_WRITE_FLUSH(hw);
2652 static int eth_igbvf_link_update(struct e1000_hw *hw)
2654 struct e1000_mbx_info *mbx = &hw->mbx;
2655 struct e1000_mac_info *mac = &hw->mac;
2656 int ret_val = E1000_SUCCESS;
2658 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2661 * We only want to run this if there has been a rst asserted.
2662 * in this case that could mean a link change, device reset,
2663 * or a virtual function reset
2666 /* If we were hit with a reset or timeout drop the link */
2667 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2668 mac->get_link_status = TRUE;
2670 if (!mac->get_link_status)
2673 /* if link status is down no point in checking to see if pf is up */
2674 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2677 /* if we passed all the tests above then the link is up and we no
2678 * longer need to check for link */
2679 mac->get_link_status = FALSE;
2687 igbvf_dev_configure(struct rte_eth_dev *dev)
2689 struct rte_eth_conf* conf = &dev->data->dev_conf;
2691 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2692 dev->data->port_id);
2695 * VF has no ability to enable/disable HW CRC
2696 * Keep the persistent behavior the same as Host PF
2698 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2699 if (!conf->rxmode.hw_strip_crc) {
2700 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2701 conf->rxmode.hw_strip_crc = 1;
2704 if (conf->rxmode.hw_strip_crc) {
2705 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2706 conf->rxmode.hw_strip_crc = 0;
2714 igbvf_dev_start(struct rte_eth_dev *dev)
2716 struct e1000_hw *hw =
2717 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2718 struct e1000_adapter *adapter =
2719 E1000_DEV_PRIVATE(dev->data->dev_private);
2722 PMD_INIT_FUNC_TRACE();
2724 hw->mac.ops.reset_hw(hw);
2725 adapter->stopped = 0;
2728 igbvf_set_vfta_all(dev,1);
2730 eth_igbvf_tx_init(dev);
2732 /* This can fail when allocating mbufs for descriptor rings */
2733 ret = eth_igbvf_rx_init(dev);
2735 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2736 igb_dev_clear_queues(dev);
2744 igbvf_dev_stop(struct rte_eth_dev *dev)
2746 PMD_INIT_FUNC_TRACE();
2748 igbvf_stop_adapter(dev);
2751 * Clear what we set, but we still keep shadow_vfta to
2752 * restore after device starts
2754 igbvf_set_vfta_all(dev,0);
2756 igb_dev_clear_queues(dev);
2760 igbvf_dev_close(struct rte_eth_dev *dev)
2762 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2763 struct e1000_adapter *adapter =
2764 E1000_DEV_PRIVATE(dev->data->dev_private);
2766 PMD_INIT_FUNC_TRACE();
2770 igbvf_dev_stop(dev);
2771 adapter->stopped = 1;
2772 igb_dev_free_queues(dev);
2775 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2777 struct e1000_mbx_info *mbx = &hw->mbx;
2780 /* After set vlan, vlan strip will also be enabled in igb driver*/
2781 msgbuf[0] = E1000_VF_SET_VLAN;
2783 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2785 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2787 return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2790 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2792 struct e1000_hw *hw =
2793 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2794 struct e1000_vfta * shadow_vfta =
2795 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2796 int i = 0, j = 0, vfta = 0, mask = 1;
2798 for (i = 0; i < IGB_VFTA_SIZE; i++){
2799 vfta = shadow_vfta->vfta[i];
2802 for (j = 0; j < 32; j++){
2805 (uint16_t)((i<<5)+j), on);
2814 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2816 struct e1000_hw *hw =
2817 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2818 struct e1000_vfta * shadow_vfta =
2819 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2820 uint32_t vid_idx = 0;
2821 uint32_t vid_bit = 0;
2824 PMD_INIT_FUNC_TRACE();
2826 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2827 ret = igbvf_set_vfta(hw, vlan_id, !!on);
2829 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2832 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2833 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2835 /*Save what we set and retore it after device reset*/
2837 shadow_vfta->vfta[vid_idx] |= vid_bit;
2839 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2845 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
2847 struct e1000_hw *hw =
2848 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2850 /* index is not used by rar_set() */
2851 hw->mac.ops.rar_set(hw, (void *)addr, 0);
2856 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2857 struct rte_eth_rss_reta_entry64 *reta_conf,
2862 uint16_t idx, shift;
2863 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2865 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2866 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2867 "(%d) doesn't match the number hardware can supported "
2868 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2872 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2873 idx = i / RTE_RETA_GROUP_SIZE;
2874 shift = i % RTE_RETA_GROUP_SIZE;
2875 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2879 if (mask == IGB_4_BIT_MASK)
2882 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2883 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2884 if (mask & (0x1 << j))
2885 reta |= reta_conf[idx].reta[shift + j] <<
2888 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2890 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2897 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2898 struct rte_eth_rss_reta_entry64 *reta_conf,
2903 uint16_t idx, shift;
2904 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2906 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2907 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2908 "(%d) doesn't match the number hardware can supported "
2909 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2913 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2914 idx = i / RTE_RETA_GROUP_SIZE;
2915 shift = i % RTE_RETA_GROUP_SIZE;
2916 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2920 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2921 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2922 if (mask & (0x1 << j))
2923 reta_conf[idx].reta[shift + j] =
2924 ((reta >> (CHAR_BIT * j)) &
2932 #define MAC_TYPE_FILTER_SUP(type) do {\
2933 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2934 (type) != e1000_82576)\
2939 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2940 struct rte_eth_syn_filter *filter,
2943 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2944 uint32_t synqf, rfctl;
2946 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2949 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2952 if (synqf & E1000_SYN_FILTER_ENABLE)
2955 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2956 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2958 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2959 if (filter->hig_pri)
2960 rfctl |= E1000_RFCTL_SYNQFP;
2962 rfctl &= ~E1000_RFCTL_SYNQFP;
2964 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2966 if (!(synqf & E1000_SYN_FILTER_ENABLE))
2971 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2972 E1000_WRITE_FLUSH(hw);
2977 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
2978 struct rte_eth_syn_filter *filter)
2980 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2981 uint32_t synqf, rfctl;
2983 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2984 if (synqf & E1000_SYN_FILTER_ENABLE) {
2985 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2986 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2987 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2988 E1000_SYN_FILTER_QUEUE_SHIFT);
2996 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
2997 enum rte_filter_op filter_op,
3000 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3003 MAC_TYPE_FILTER_SUP(hw->mac.type);
3005 if (filter_op == RTE_ETH_FILTER_NOP)
3009 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3014 switch (filter_op) {
3015 case RTE_ETH_FILTER_ADD:
3016 ret = eth_igb_syn_filter_set(dev,
3017 (struct rte_eth_syn_filter *)arg,
3020 case RTE_ETH_FILTER_DELETE:
3021 ret = eth_igb_syn_filter_set(dev,
3022 (struct rte_eth_syn_filter *)arg,
3025 case RTE_ETH_FILTER_GET:
3026 ret = eth_igb_syn_filter_get(dev,
3027 (struct rte_eth_syn_filter *)arg);
3030 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3038 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
3039 if ((type) != e1000_82580 && (type) != e1000_i350)\
3043 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3045 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3046 struct e1000_2tuple_filter_info *filter_info)
3048 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3050 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3051 return -EINVAL; /* filter index is out of range. */
3052 if (filter->tcp_flags > TCP_FLAG_ALL)
3053 return -EINVAL; /* flags is invalid. */
3055 switch (filter->dst_port_mask) {
3057 filter_info->dst_port_mask = 0;
3058 filter_info->dst_port = filter->dst_port;
3061 filter_info->dst_port_mask = 1;
3064 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3068 switch (filter->proto_mask) {
3070 filter_info->proto_mask = 0;
3071 filter_info->proto = filter->proto;
3074 filter_info->proto_mask = 1;
3077 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3081 filter_info->priority = (uint8_t)filter->priority;
3082 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3083 filter_info->tcp_flags = filter->tcp_flags;
3085 filter_info->tcp_flags = 0;
3090 static inline struct e1000_2tuple_filter *
3091 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3092 struct e1000_2tuple_filter_info *key)
3094 struct e1000_2tuple_filter *it;
3096 TAILQ_FOREACH(it, filter_list, entries) {
3097 if (memcmp(key, &it->filter_info,
3098 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3106 * igb_add_2tuple_filter - add a 2tuple filter
3109 * dev: Pointer to struct rte_eth_dev.
3110 * ntuple_filter: ponter to the filter that will be added.
3113 * - On success, zero.
3114 * - On failure, a negative value.
3117 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3118 struct rte_eth_ntuple_filter *ntuple_filter)
3120 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3121 struct e1000_filter_info *filter_info =
3122 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3123 struct e1000_2tuple_filter *filter;
3124 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3125 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3128 filter = rte_zmalloc("e1000_2tuple_filter",
3129 sizeof(struct e1000_2tuple_filter), 0);
3133 ret = ntuple_filter_to_2tuple(ntuple_filter,
3134 &filter->filter_info);
3139 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3140 &filter->filter_info) != NULL) {
3141 PMD_DRV_LOG(ERR, "filter exists.");
3145 filter->queue = ntuple_filter->queue;
3148 * look for an unused 2tuple filter index,
3149 * and insert the filter to list.
3151 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3152 if (!(filter_info->twotuple_mask & (1 << i))) {
3153 filter_info->twotuple_mask |= 1 << i;
3155 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3161 if (i >= E1000_MAX_TTQF_FILTERS) {
3162 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3167 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3168 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3169 imir |= E1000_IMIR_PORT_BP;
3171 imir &= ~E1000_IMIR_PORT_BP;
3173 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3175 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3176 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3177 ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3178 if (filter->filter_info.proto_mask == 0)
3179 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3181 /* tcp flags bits setting. */
3182 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3183 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3184 imir_ext |= E1000_IMIREXT_CTRL_URG;
3185 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3186 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3187 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3188 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3189 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3190 imir_ext |= E1000_IMIREXT_CTRL_RST;
3191 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3192 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3193 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3194 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3196 imir_ext |= E1000_IMIREXT_CTRL_BP;
3197 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3198 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3199 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3204 * igb_remove_2tuple_filter - remove a 2tuple filter
3207 * dev: Pointer to struct rte_eth_dev.
3208 * ntuple_filter: ponter to the filter that will be removed.
3211 * - On success, zero.
3212 * - On failure, a negative value.
3215 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3216 struct rte_eth_ntuple_filter *ntuple_filter)
3218 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3219 struct e1000_filter_info *filter_info =
3220 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3221 struct e1000_2tuple_filter_info filter_2tuple;
3222 struct e1000_2tuple_filter *filter;
3225 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3226 ret = ntuple_filter_to_2tuple(ntuple_filter,
3231 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3233 if (filter == NULL) {
3234 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3238 filter_info->twotuple_mask &= ~(1 << filter->index);
3239 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3242 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3243 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3244 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3248 static inline struct e1000_flex_filter *
3249 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3250 struct e1000_flex_filter_info *key)
3252 struct e1000_flex_filter *it;
3254 TAILQ_FOREACH(it, filter_list, entries) {
3255 if (memcmp(key, &it->filter_info,
3256 sizeof(struct e1000_flex_filter_info)) == 0)
3264 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3265 struct rte_eth_flex_filter *filter,
3268 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3269 struct e1000_filter_info *filter_info =
3270 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3271 struct e1000_flex_filter *flex_filter, *it;
3272 uint32_t wufc, queueing, mask;
3274 uint8_t shift, i, j = 0;
3276 flex_filter = rte_zmalloc("e1000_flex_filter",
3277 sizeof(struct e1000_flex_filter), 0);
3278 if (flex_filter == NULL)
3281 flex_filter->filter_info.len = filter->len;
3282 flex_filter->filter_info.priority = filter->priority;
3283 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3284 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3286 /* reverse bits in flex filter's mask*/
3287 for (shift = 0; shift < CHAR_BIT; shift++) {
3288 if (filter->mask[i] & (0x01 << shift))
3289 mask |= (0x80 >> shift);
3291 flex_filter->filter_info.mask[i] = mask;
3294 wufc = E1000_READ_REG(hw, E1000_WUFC);
3295 if (flex_filter->index < E1000_MAX_FHFT)
3296 reg_off = E1000_FHFT(flex_filter->index);
3298 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3301 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3302 &flex_filter->filter_info) != NULL) {
3303 PMD_DRV_LOG(ERR, "filter exists.");
3304 rte_free(flex_filter);
3307 flex_filter->queue = filter->queue;
3309 * look for an unused flex filter index
3310 * and insert the filter into the list.
3312 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3313 if (!(filter_info->flex_mask & (1 << i))) {
3314 filter_info->flex_mask |= 1 << i;
3315 flex_filter->index = i;
3316 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3322 if (i >= E1000_MAX_FLEX_FILTERS) {
3323 PMD_DRV_LOG(ERR, "flex filters are full.");
3324 rte_free(flex_filter);
3328 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3329 (E1000_WUFC_FLX0 << flex_filter->index));
3330 queueing = filter->len |
3331 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3332 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3333 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3335 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3336 E1000_WRITE_REG(hw, reg_off,
3337 flex_filter->filter_info.dwords[j]);
3338 reg_off += sizeof(uint32_t);
3339 E1000_WRITE_REG(hw, reg_off,
3340 flex_filter->filter_info.dwords[++j]);
3341 reg_off += sizeof(uint32_t);
3342 E1000_WRITE_REG(hw, reg_off,
3343 (uint32_t)flex_filter->filter_info.mask[i]);
3344 reg_off += sizeof(uint32_t) * 2;
3348 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3349 &flex_filter->filter_info);
3351 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3352 rte_free(flex_filter);
3356 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3357 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3358 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3359 (~(E1000_WUFC_FLX0 << it->index)));
3361 filter_info->flex_mask &= ~(1 << it->index);
3362 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3364 rte_free(flex_filter);
3371 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3372 struct rte_eth_flex_filter *filter)
3374 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3375 struct e1000_filter_info *filter_info =
3376 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3377 struct e1000_flex_filter flex_filter, *it;
3378 uint32_t wufc, queueing, wufc_en = 0;
3380 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3381 flex_filter.filter_info.len = filter->len;
3382 flex_filter.filter_info.priority = filter->priority;
3383 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3384 memcpy(flex_filter.filter_info.mask, filter->mask,
3385 RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3387 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3388 &flex_filter.filter_info);
3390 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3394 wufc = E1000_READ_REG(hw, E1000_WUFC);
3395 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3397 if ((wufc & wufc_en) == wufc_en) {
3398 uint32_t reg_off = 0;
3399 if (it->index < E1000_MAX_FHFT)
3400 reg_off = E1000_FHFT(it->index);
3402 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3404 queueing = E1000_READ_REG(hw,
3405 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3406 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3407 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3408 E1000_FHFT_QUEUEING_PRIO_SHIFT;
3409 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3410 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3417 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3418 enum rte_filter_op filter_op,
3421 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3422 struct rte_eth_flex_filter *filter;
3425 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3427 if (filter_op == RTE_ETH_FILTER_NOP)
3431 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3436 filter = (struct rte_eth_flex_filter *)arg;
3437 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3438 || filter->len % sizeof(uint64_t) != 0) {
3439 PMD_DRV_LOG(ERR, "filter's length is out of range");
3442 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3443 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3447 switch (filter_op) {
3448 case RTE_ETH_FILTER_ADD:
3449 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3451 case RTE_ETH_FILTER_DELETE:
3452 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3454 case RTE_ETH_FILTER_GET:
3455 ret = eth_igb_get_flex_filter(dev, filter);
3458 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3466 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3468 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3469 struct e1000_5tuple_filter_info *filter_info)
3471 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3473 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3474 return -EINVAL; /* filter index is out of range. */
3475 if (filter->tcp_flags > TCP_FLAG_ALL)
3476 return -EINVAL; /* flags is invalid. */
3478 switch (filter->dst_ip_mask) {
3480 filter_info->dst_ip_mask = 0;
3481 filter_info->dst_ip = filter->dst_ip;
3484 filter_info->dst_ip_mask = 1;
3487 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3491 switch (filter->src_ip_mask) {
3493 filter_info->src_ip_mask = 0;
3494 filter_info->src_ip = filter->src_ip;
3497 filter_info->src_ip_mask = 1;
3500 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3504 switch (filter->dst_port_mask) {
3506 filter_info->dst_port_mask = 0;
3507 filter_info->dst_port = filter->dst_port;
3510 filter_info->dst_port_mask = 1;
3513 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3517 switch (filter->src_port_mask) {
3519 filter_info->src_port_mask = 0;
3520 filter_info->src_port = filter->src_port;
3523 filter_info->src_port_mask = 1;
3526 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3530 switch (filter->proto_mask) {
3532 filter_info->proto_mask = 0;
3533 filter_info->proto = filter->proto;
3536 filter_info->proto_mask = 1;
3539 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3543 filter_info->priority = (uint8_t)filter->priority;
3544 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3545 filter_info->tcp_flags = filter->tcp_flags;
3547 filter_info->tcp_flags = 0;
3552 static inline struct e1000_5tuple_filter *
3553 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3554 struct e1000_5tuple_filter_info *key)
3556 struct e1000_5tuple_filter *it;
3558 TAILQ_FOREACH(it, filter_list, entries) {
3559 if (memcmp(key, &it->filter_info,
3560 sizeof(struct e1000_5tuple_filter_info)) == 0) {
3568 * igb_add_5tuple_filter_82576 - add a 5tuple filter
3571 * dev: Pointer to struct rte_eth_dev.
3572 * ntuple_filter: ponter to the filter that will be added.
3575 * - On success, zero.
3576 * - On failure, a negative value.
3579 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3580 struct rte_eth_ntuple_filter *ntuple_filter)
3582 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3583 struct e1000_filter_info *filter_info =
3584 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3585 struct e1000_5tuple_filter *filter;
3586 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3587 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3591 filter = rte_zmalloc("e1000_5tuple_filter",
3592 sizeof(struct e1000_5tuple_filter), 0);
3596 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3597 &filter->filter_info);
3603 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3604 &filter->filter_info) != NULL) {
3605 PMD_DRV_LOG(ERR, "filter exists.");
3609 filter->queue = ntuple_filter->queue;
3612 * look for an unused 5tuple filter index,
3613 * and insert the filter to list.
3615 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3616 if (!(filter_info->fivetuple_mask & (1 << i))) {
3617 filter_info->fivetuple_mask |= 1 << i;
3619 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3625 if (i >= E1000_MAX_FTQF_FILTERS) {
3626 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3631 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3632 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3633 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3634 if (filter->filter_info.dst_ip_mask == 0)
3635 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3636 if (filter->filter_info.src_port_mask == 0)
3637 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3638 if (filter->filter_info.proto_mask == 0)
3639 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3640 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3641 E1000_FTQF_QUEUE_MASK;
3642 ftqf |= E1000_FTQF_QUEUE_ENABLE;
3643 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3644 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3645 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3647 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3648 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3650 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3651 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3652 imir |= E1000_IMIR_PORT_BP;
3654 imir &= ~E1000_IMIR_PORT_BP;
3655 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3657 /* tcp flags bits setting. */
3658 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3659 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3660 imir_ext |= E1000_IMIREXT_CTRL_URG;
3661 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3662 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3663 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3664 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3665 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3666 imir_ext |= E1000_IMIREXT_CTRL_RST;
3667 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3668 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3669 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3670 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3672 imir_ext |= E1000_IMIREXT_CTRL_BP;
3673 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3674 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3679 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3682 * dev: Pointer to struct rte_eth_dev.
3683 * ntuple_filter: ponter to the filter that will be removed.
3686 * - On success, zero.
3687 * - On failure, a negative value.
3690 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3691 struct rte_eth_ntuple_filter *ntuple_filter)
3693 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3694 struct e1000_filter_info *filter_info =
3695 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3696 struct e1000_5tuple_filter_info filter_5tuple;
3697 struct e1000_5tuple_filter *filter;
3700 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3701 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3706 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3708 if (filter == NULL) {
3709 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3713 filter_info->fivetuple_mask &= ~(1 << filter->index);
3714 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3717 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3718 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3719 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3720 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3721 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3722 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3723 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3728 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3731 struct e1000_hw *hw;
3732 struct rte_eth_dev_info dev_info;
3733 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3736 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3738 #ifdef RTE_LIBRTE_82571_SUPPORT
3739 /* XXX: not bigger than max_rx_pktlen */
3740 if (hw->mac.type == e1000_82571)
3743 eth_igb_infos_get(dev, &dev_info);
3745 /* check that mtu is within the allowed range */
3746 if ((mtu < ETHER_MIN_MTU) ||
3747 (frame_size > dev_info.max_rx_pktlen))
3750 /* refuse mtu that requires the support of scattered packets when this
3751 * feature has not been enabled before. */
3752 if (!dev->data->scattered_rx &&
3753 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3756 rctl = E1000_READ_REG(hw, E1000_RCTL);
3758 /* switch to jumbo mode if needed */
3759 if (frame_size > ETHER_MAX_LEN) {
3760 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3761 rctl |= E1000_RCTL_LPE;
3763 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3764 rctl &= ~E1000_RCTL_LPE;
3766 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3768 /* update max frame size */
3769 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3771 E1000_WRITE_REG(hw, E1000_RLPML,
3772 dev->data->dev_conf.rxmode.max_rx_pkt_len);
3778 * igb_add_del_ntuple_filter - add or delete a ntuple filter
3781 * dev: Pointer to struct rte_eth_dev.
3782 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3783 * add: if true, add filter, if false, remove filter
3786 * - On success, zero.
3787 * - On failure, a negative value.
3790 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3791 struct rte_eth_ntuple_filter *ntuple_filter,
3794 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3797 switch (ntuple_filter->flags) {
3798 case RTE_5TUPLE_FLAGS:
3799 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3800 if (hw->mac.type != e1000_82576)
3803 ret = igb_add_5tuple_filter_82576(dev,
3806 ret = igb_remove_5tuple_filter_82576(dev,
3809 case RTE_2TUPLE_FLAGS:
3810 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3811 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3814 ret = igb_add_2tuple_filter(dev, ntuple_filter);
3816 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3827 * igb_get_ntuple_filter - get a ntuple filter
3830 * dev: Pointer to struct rte_eth_dev.
3831 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3834 * - On success, zero.
3835 * - On failure, a negative value.
3838 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3839 struct rte_eth_ntuple_filter *ntuple_filter)
3841 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3842 struct e1000_filter_info *filter_info =
3843 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3844 struct e1000_5tuple_filter_info filter_5tuple;
3845 struct e1000_2tuple_filter_info filter_2tuple;
3846 struct e1000_5tuple_filter *p_5tuple_filter;
3847 struct e1000_2tuple_filter *p_2tuple_filter;
3850 switch (ntuple_filter->flags) {
3851 case RTE_5TUPLE_FLAGS:
3852 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3853 if (hw->mac.type != e1000_82576)
3855 memset(&filter_5tuple,
3857 sizeof(struct e1000_5tuple_filter_info));
3858 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3862 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3863 &filter_info->fivetuple_list,
3865 if (p_5tuple_filter == NULL) {
3866 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3869 ntuple_filter->queue = p_5tuple_filter->queue;
3871 case RTE_2TUPLE_FLAGS:
3872 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3873 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3875 memset(&filter_2tuple,
3877 sizeof(struct e1000_2tuple_filter_info));
3878 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3881 p_2tuple_filter = igb_2tuple_filter_lookup(
3882 &filter_info->twotuple_list,
3884 if (p_2tuple_filter == NULL) {
3885 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3888 ntuple_filter->queue = p_2tuple_filter->queue;
3899 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3900 * @dev: pointer to rte_eth_dev structure
3901 * @filter_op:operation will be taken.
3902 * @arg: a pointer to specific structure corresponding to the filter_op
3905 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3906 enum rte_filter_op filter_op,
3909 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3912 MAC_TYPE_FILTER_SUP(hw->mac.type);
3914 if (filter_op == RTE_ETH_FILTER_NOP)
3918 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3923 switch (filter_op) {
3924 case RTE_ETH_FILTER_ADD:
3925 ret = igb_add_del_ntuple_filter(dev,
3926 (struct rte_eth_ntuple_filter *)arg,
3929 case RTE_ETH_FILTER_DELETE:
3930 ret = igb_add_del_ntuple_filter(dev,
3931 (struct rte_eth_ntuple_filter *)arg,
3934 case RTE_ETH_FILTER_GET:
3935 ret = igb_get_ntuple_filter(dev,
3936 (struct rte_eth_ntuple_filter *)arg);
3939 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3947 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3952 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3953 if (filter_info->ethertype_filters[i] == ethertype &&
3954 (filter_info->ethertype_mask & (1 << i)))
3961 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3966 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3967 if (!(filter_info->ethertype_mask & (1 << i))) {
3968 filter_info->ethertype_mask |= 1 << i;
3969 filter_info->ethertype_filters[i] = ethertype;
3977 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3980 if (idx >= E1000_MAX_ETQF_FILTERS)
3982 filter_info->ethertype_mask &= ~(1 << idx);
3983 filter_info->ethertype_filters[idx] = 0;
3989 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
3990 struct rte_eth_ethertype_filter *filter,
3993 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3994 struct e1000_filter_info *filter_info =
3995 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3999 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4000 filter->ether_type == ETHER_TYPE_IPv6) {
4001 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4002 " ethertype filter.", filter->ether_type);
4006 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4007 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4010 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4011 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4015 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4016 if (ret >= 0 && add) {
4017 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4018 filter->ether_type);
4021 if (ret < 0 && !add) {
4022 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4023 filter->ether_type);
4028 ret = igb_ethertype_filter_insert(filter_info,
4029 filter->ether_type);
4031 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4035 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4036 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4037 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4039 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4043 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4044 E1000_WRITE_FLUSH(hw);
4050 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4051 struct rte_eth_ethertype_filter *filter)
4053 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4054 struct e1000_filter_info *filter_info =
4055 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4059 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4061 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4062 filter->ether_type);
4066 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4067 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4068 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4070 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4071 E1000_ETQF_QUEUE_SHIFT;
4079 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4080 * @dev: pointer to rte_eth_dev structure
4081 * @filter_op:operation will be taken.
4082 * @arg: a pointer to specific structure corresponding to the filter_op
4085 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4086 enum rte_filter_op filter_op,
4089 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4092 MAC_TYPE_FILTER_SUP(hw->mac.type);
4094 if (filter_op == RTE_ETH_FILTER_NOP)
4098 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4103 switch (filter_op) {
4104 case RTE_ETH_FILTER_ADD:
4105 ret = igb_add_del_ethertype_filter(dev,
4106 (struct rte_eth_ethertype_filter *)arg,
4109 case RTE_ETH_FILTER_DELETE:
4110 ret = igb_add_del_ethertype_filter(dev,
4111 (struct rte_eth_ethertype_filter *)arg,
4114 case RTE_ETH_FILTER_GET:
4115 ret = igb_get_ethertype_filter(dev,
4116 (struct rte_eth_ethertype_filter *)arg);
4119 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4127 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4128 enum rte_filter_type filter_type,
4129 enum rte_filter_op filter_op,
4134 switch (filter_type) {
4135 case RTE_ETH_FILTER_NTUPLE:
4136 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4138 case RTE_ETH_FILTER_ETHERTYPE:
4139 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4141 case RTE_ETH_FILTER_SYN:
4142 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4144 case RTE_ETH_FILTER_FLEXIBLE:
4145 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4148 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4157 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4158 struct ether_addr *mc_addr_set,
4159 uint32_t nb_mc_addr)
4161 struct e1000_hw *hw;
4163 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4164 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4169 igb_timesync_enable(struct rte_eth_dev *dev)
4171 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4175 /* Enable system time for it isn't on by default. */
4176 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4177 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4178 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4180 /* Start incrementing the register used to timestamp PTP packets. */
4181 E1000_WRITE_REG(hw, E1000_TIMINCA, E1000_TIMINCA_INIT);
4183 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4184 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4186 E1000_ETQF_FILTER_ENABLE |
4189 /* Enable timestamping of received PTP packets. */
4190 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4191 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4192 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4194 /* Enable Timestamping of transmitted PTP packets. */
4195 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4196 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4197 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4203 igb_timesync_disable(struct rte_eth_dev *dev)
4205 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4208 /* Disable timestamping of transmitted PTP packets. */
4209 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4210 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4211 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4213 /* Disable timestamping of received PTP packets. */
4214 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4215 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4216 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4218 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4219 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4221 /* Stop incrementating the System Time registers. */
4222 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4228 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4229 struct timespec *timestamp,
4230 uint32_t flags __rte_unused)
4232 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4233 uint32_t tsync_rxctl;
4237 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4238 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4241 rx_stmpl = E1000_READ_REG(hw, E1000_RXSTMPL);
4242 rx_stmph = E1000_READ_REG(hw, E1000_RXSTMPH);
4244 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
4245 timestamp->tv_nsec = 0;
4251 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4252 struct timespec *timestamp)
4254 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4255 uint32_t tsync_txctl;
4259 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4260 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4263 tx_stmpl = E1000_READ_REG(hw, E1000_TXSTMPL);
4264 tx_stmph = E1000_READ_REG(hw, E1000_TXSTMPH);
4266 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
4267 timestamp->tv_nsec = 0;
4273 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4277 const struct reg_info *reg_group;
4279 while ((reg_group = igb_regs[g_ind++]))
4280 count += igb_reg_group_count(reg_group);
4286 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4290 const struct reg_info *reg_group;
4292 while ((reg_group = igbvf_regs[g_ind++]))
4293 count += igb_reg_group_count(reg_group);
4299 eth_igb_get_regs(struct rte_eth_dev *dev,
4300 struct rte_dev_reg_info *regs)
4302 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4303 uint32_t *data = regs->data;
4306 const struct reg_info *reg_group;
4308 /* Support only full register dump */
4309 if ((regs->length == 0) ||
4310 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4311 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4313 while ((reg_group = igb_regs[g_ind++]))
4314 count += igb_read_regs_group(dev, &data[count],
4323 igbvf_get_regs(struct rte_eth_dev *dev,
4324 struct rte_dev_reg_info *regs)
4326 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4327 uint32_t *data = regs->data;
4330 const struct reg_info *reg_group;
4332 /* Support only full register dump */
4333 if ((regs->length == 0) ||
4334 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4335 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4337 while ((reg_group = igbvf_regs[g_ind++]))
4338 count += igb_read_regs_group(dev, &data[count],
4347 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4349 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4351 /* Return unit is byte count */
4352 return hw->nvm.word_size * 2;
4356 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4357 struct rte_dev_eeprom_info *in_eeprom)
4359 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4360 struct e1000_nvm_info *nvm = &hw->nvm;
4361 uint16_t *data = in_eeprom->data;
4364 first = in_eeprom->offset >> 1;
4365 length = in_eeprom->length >> 1;
4366 if ((first >= hw->nvm.word_size) ||
4367 ((first + length) >= hw->nvm.word_size))
4370 in_eeprom->magic = hw->vendor_id |
4371 ((uint32_t)hw->device_id << 16);
4373 if ((nvm->ops.read) == NULL)
4376 return nvm->ops.read(hw, first, length, data);
4380 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4381 struct rte_dev_eeprom_info *in_eeprom)
4383 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4384 struct e1000_nvm_info *nvm = &hw->nvm;
4385 uint16_t *data = in_eeprom->data;
4388 first = in_eeprom->offset >> 1;
4389 length = in_eeprom->length >> 1;
4390 if ((first >= hw->nvm.word_size) ||
4391 ((first + length) >= hw->nvm.word_size))
4394 in_eeprom->magic = (uint32_t)hw->vendor_id |
4395 ((uint32_t)hw->device_id << 16);
4397 if ((nvm->ops.write) == NULL)
4399 return nvm->ops.write(hw, first, length, data);
4402 static struct rte_driver pmd_igb_drv = {
4404 .init = rte_igb_pmd_init,
4407 static struct rte_driver pmd_igbvf_drv = {
4409 .init = rte_igbvf_pmd_init,
4413 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4415 struct e1000_hw *hw =
4416 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4417 uint32_t mask = 1 << queue_id;
4419 E1000_WRITE_REG(hw, E1000_EIMC, mask);
4420 E1000_WRITE_FLUSH(hw);
4426 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4428 struct e1000_hw *hw =
4429 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4430 uint32_t mask = 1 << queue_id;
4433 regval = E1000_READ_REG(hw, E1000_EIMS);
4434 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4435 E1000_WRITE_FLUSH(hw);
4437 rte_intr_enable(&dev->pci_dev->intr_handle);
4443 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
4444 uint8_t index, uint8_t offset)
4446 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4449 val &= ~((uint32_t)0xFF << offset);
4451 /* write vector and valid bit */
4452 val |= (msix_vector | E1000_IVAR_VALID) << offset;
4454 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4458 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4459 uint8_t queue, uint8_t msix_vector)
4463 if (hw->mac.type == e1000_82575) {
4465 tmp = E1000_EICR_RX_QUEUE0 << queue;
4466 else if (direction == 1)
4467 tmp = E1000_EICR_TX_QUEUE0 << queue;
4468 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4469 } else if (hw->mac.type == e1000_82576) {
4470 if ((direction == 0) || (direction == 1))
4471 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4472 ((queue & 0x8) << 1) +
4474 } else if ((hw->mac.type == e1000_82580) ||
4475 (hw->mac.type == e1000_i350) ||
4476 (hw->mac.type == e1000_i354) ||
4477 (hw->mac.type == e1000_i210) ||
4478 (hw->mac.type == e1000_i211)) {
4479 if ((direction == 0) || (direction == 1))
4480 eth_igb_write_ivar(hw, msix_vector,
4482 ((queue & 0x1) << 4) +
4487 /* Sets up the hardware to generate MSI-X interrupts properly
4489 * board private structure
4492 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4495 uint32_t tmpval, regval, intr_mask;
4496 struct e1000_hw *hw =
4497 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4498 uint32_t vec = E1000_MISC_VEC_ID;
4499 uint32_t base = E1000_MISC_VEC_ID;
4500 uint32_t misc_shift = 0;
4502 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4504 /* won't configure msix register if no mapping is done
4505 * between intr vector and event fd
4507 if (!rte_intr_dp_is_en(intr_handle))
4510 if (rte_intr_allow_others(intr_handle)) {
4511 vec = base = E1000_RX_VEC_START;
4515 /* set interrupt vector for other causes */
4516 if (hw->mac.type == e1000_82575) {
4517 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4518 /* enable MSI-X PBA support */
4519 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4521 /* Auto-Mask interrupts upon ICR read */
4522 tmpval |= E1000_CTRL_EXT_EIAME;
4523 tmpval |= E1000_CTRL_EXT_IRCA;
4525 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4527 /* enable msix_other interrupt */
4528 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4529 regval = E1000_READ_REG(hw, E1000_EIAC);
4530 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4531 regval = E1000_READ_REG(hw, E1000_EIAM);
4532 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4533 } else if ((hw->mac.type == e1000_82576) ||
4534 (hw->mac.type == e1000_82580) ||
4535 (hw->mac.type == e1000_i350) ||
4536 (hw->mac.type == e1000_i354) ||
4537 (hw->mac.type == e1000_i210) ||
4538 (hw->mac.type == e1000_i211)) {
4539 /* turn on MSI-X capability first */
4540 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4541 E1000_GPIE_PBA | E1000_GPIE_EIAME |
4543 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4545 regval = E1000_READ_REG(hw, E1000_EIAC);
4546 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4548 /* enable msix_other interrupt */
4549 regval = E1000_READ_REG(hw, E1000_EIMS);
4550 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4551 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4552 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4555 /* use EIAM to auto-mask when MSI-X interrupt
4556 * is asserted, this saves a register write for every interrupt
4558 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4560 regval = E1000_READ_REG(hw, E1000_EIAM);
4561 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4563 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4564 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4565 intr_handle->intr_vec[queue_id] = vec;
4566 if (vec < base + intr_handle->nb_efd - 1)
4570 E1000_WRITE_FLUSH(hw);
4573 PMD_REGISTER_DRIVER(pmd_igb_drv);
4574 PMD_REGISTER_DRIVER(pmd_igbvf_drv);