drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 #define IGB_HKEY_MAX_INDEX 10
  73
  74 /* Bit shift and mask */
  75 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  76 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  77 #define IGB_8_BIT_WIDTH  CHAR_BIT
  78 #define IGB_8_BIT_MASK   UINT8_MAX
  79
  80 /* Additional timesync values. */
  81 #define E1000_ETQF_FILTER_1588 3
  82 #define E1000_TIMINCA_INCVALUE 16000000
  83 #define E1000_TIMINCA_INIT     ((0x02 << E1000_TIMINCA_16NS_SHIFT) \
  84                                 | E1000_TIMINCA_INCVALUE)
  85 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  86
  87 static int  eth_igb_configure(struct rte_eth_dev *dev);
  88 static int  eth_igb_start(struct rte_eth_dev *dev);
  89 static void eth_igb_stop(struct rte_eth_dev *dev);
  90 static void eth_igb_close(struct rte_eth_dev *dev);
  91 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  92 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  93 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  94 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  95 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  96                                 int wait_to_complete);
  97 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  98                                 struct rte_eth_stats *rte_stats);
  99 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 100 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 101                               struct rte_eth_dev_info *dev_info);
 102 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 103                                 struct rte_eth_dev_info *dev_info);
 104 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 105                                 struct rte_eth_fc_conf *fc_conf);
 106 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 107                                 struct rte_eth_fc_conf *fc_conf);
 108 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 109 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 110 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 111 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 112 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 113                                                         void *param);
 114 static int  igb_hardware_init(struct e1000_hw *hw);
 115 static void igb_hw_control_acquire(struct e1000_hw *hw);
 116 static void igb_hw_control_release(struct e1000_hw *hw);
 117 static void igb_init_manageability(struct e1000_hw *hw);
 118 static void igb_release_manageability(struct e1000_hw *hw);
 119
 120 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 121
 122 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 123                 uint16_t vlan_id, int on);
 124 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 125 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 126
 127 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 128 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 129 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 130 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 131 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 132 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 133
 134 static int eth_igb_led_on(struct rte_eth_dev *dev);
 135 static int eth_igb_led_off(struct rte_eth_dev *dev);
 136
 137 static void igb_intr_disable(struct e1000_hw *hw);
 138 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 139 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 140                 struct ether_addr *mac_addr,
 141                 uint32_t index, uint32_t pool);
 142 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 143 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 144                 struct ether_addr *addr);
 145
 146 static void igbvf_intr_disable(struct e1000_hw *hw);
 147 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 148 static int igbvf_dev_start(struct rte_eth_dev *dev);
 149 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 150 static void igbvf_dev_close(struct rte_eth_dev *dev);
 151 static int eth_igbvf_link_update(struct e1000_hw *hw);
 152 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 153 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 154 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 155                 uint16_t vlan_id, int on);
 156 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 157 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 158 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 159                 struct ether_addr *addr);
 160 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 161 static int igbvf_get_regs(struct rte_eth_dev *dev,
 162                 struct rte_dev_reg_info *regs);
 163
 164 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 165                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 166                                    uint16_t reta_size);
 167 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 168                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 169                                   uint16_t reta_size);
 170
 171 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 172                         struct rte_eth_syn_filter *filter,
 173                         bool add);
 174 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 175                         struct rte_eth_syn_filter *filter);
 176 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 177                         enum rte_filter_op filter_op,
 178                         void *arg);
 179 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 180                         struct rte_eth_ntuple_filter *ntuple_filter);
 181 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 182                         struct rte_eth_ntuple_filter *ntuple_filter);
 183 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 184                         struct rte_eth_flex_filter *filter,
 185                         bool add);
 186 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 187                         struct rte_eth_flex_filter *filter);
 188 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 189                         enum rte_filter_op filter_op,
 190                         void *arg);
 191 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 192                         struct rte_eth_ntuple_filter *ntuple_filter);
 193 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 194                         struct rte_eth_ntuple_filter *ntuple_filter);
 195 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 196                         struct rte_eth_ntuple_filter *filter,
 197                         bool add);
 198 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 199                         struct rte_eth_ntuple_filter *filter);
 200 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 201                                 enum rte_filter_op filter_op,
 202                                 void *arg);
 203 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 204                         struct rte_eth_ethertype_filter *filter,
 205                         bool add);
 206 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 207                                 enum rte_filter_op filter_op,
 208                                 void *arg);
 209 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 210                         struct rte_eth_ethertype_filter *filter);
 211 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 212                      enum rte_filter_type filter_type,
 213                      enum rte_filter_op filter_op,
 214                      void *arg);
 215 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 216 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 217                 struct rte_dev_reg_info *regs);
 218 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 219 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 220                 struct rte_dev_eeprom_info *eeprom);
 221 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 222                 struct rte_dev_eeprom_info *eeprom);
 223 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 224                                     struct ether_addr *mc_addr_set,
 225                                     uint32_t nb_mc_addr);
 226 static int igb_timesync_enable(struct rte_eth_dev *dev);
 227 static int igb_timesync_disable(struct rte_eth_dev *dev);
 228 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 229                                           struct timespec *timestamp,
 230                                           uint32_t flags);
 231 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 232                                           struct timespec *timestamp);
 233 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 234                                         uint16_t queue_id);
 235 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 236                                          uint16_t queue_id);
 237 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 238                                        uint8_t queue, uint8_t msix_vector);
 239 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 240                                uint8_t index, uint8_t offset);
 241 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 242
 243 /*
 244  * Define VF Stats MACRO for Non "cleared on read" register
 245  */
 246 #define UPDATE_VF_STAT(reg, last, cur)            \
 247 {                                                 \
 248         u32 latest = E1000_READ_REG(hw, reg);     \
 249         cur += latest - last;                     \
 250         last = latest;                            \
 251 }
 252
 253
 254 #define IGB_FC_PAUSE_TIME 0x0680
 255 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 256 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 257
 258 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 259
 260 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 261
 262 /*
 263  * The set of PCI devices this driver supports
 264  */
 265 static const struct rte_pci_id pci_id_igb_map[] = {
 266
 267 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 268 #include "rte_pci_dev_ids.h"
 269
 270 {0},
 271 };
 272
 273 /*
 274  * The set of PCI devices this driver supports (for 82576&I350 VF)
 275  */
 276 static const struct rte_pci_id pci_id_igbvf_map[] = {
 277
 278 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 279 #include "rte_pci_dev_ids.h"
 280
 281 {0},
 282 };
 283
 284 static const struct eth_dev_ops eth_igb_ops = {
 285         .dev_configure        = eth_igb_configure,
 286         .dev_start            = eth_igb_start,
 287         .dev_stop             = eth_igb_stop,
 288         .dev_close            = eth_igb_close,
 289         .promiscuous_enable   = eth_igb_promiscuous_enable,
 290         .promiscuous_disable  = eth_igb_promiscuous_disable,
 291         .allmulticast_enable  = eth_igb_allmulticast_enable,
 292         .allmulticast_disable = eth_igb_allmulticast_disable,
 293         .link_update          = eth_igb_link_update,
 294         .stats_get            = eth_igb_stats_get,
 295         .stats_reset          = eth_igb_stats_reset,
 296         .dev_infos_get        = eth_igb_infos_get,
 297         .mtu_set              = eth_igb_mtu_set,
 298         .vlan_filter_set      = eth_igb_vlan_filter_set,
 299         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 300         .vlan_offload_set     = eth_igb_vlan_offload_set,
 301         .rx_queue_setup       = eth_igb_rx_queue_setup,
 302         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 303         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 304         .rx_queue_release     = eth_igb_rx_queue_release,
 305         .rx_queue_count       = eth_igb_rx_queue_count,
 306         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 307         .tx_queue_setup       = eth_igb_tx_queue_setup,
 308         .tx_queue_release     = eth_igb_tx_queue_release,
 309         .dev_led_on           = eth_igb_led_on,
 310         .dev_led_off          = eth_igb_led_off,
 311         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 312         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 313         .mac_addr_add         = eth_igb_rar_set,
 314         .mac_addr_remove      = eth_igb_rar_clear,
 315         .mac_addr_set         = eth_igb_default_mac_addr_set,
 316         .reta_update          = eth_igb_rss_reta_update,
 317         .reta_query           = eth_igb_rss_reta_query,
 318         .rss_hash_update      = eth_igb_rss_hash_update,
 319         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 320         .filter_ctrl          = eth_igb_filter_ctrl,
 321         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 322         .timesync_enable      = igb_timesync_enable,
 323         .timesync_disable     = igb_timesync_disable,
 324         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 325         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 326         .get_reg_length       = eth_igb_get_reg_length,
 327         .get_reg              = eth_igb_get_regs,
 328         .get_eeprom_length    = eth_igb_get_eeprom_length,
 329         .get_eeprom           = eth_igb_get_eeprom,
 330         .set_eeprom           = eth_igb_set_eeprom,
 331 };
 332
 333 /*
 334  * dev_ops for virtual function, bare necessities for basic vf
 335  * operation have been implemented
 336  */
 337 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 338         .dev_configure        = igbvf_dev_configure,
 339         .dev_start            = igbvf_dev_start,
 340         .dev_stop             = igbvf_dev_stop,
 341         .dev_close            = igbvf_dev_close,
 342         .link_update          = eth_igb_link_update,
 343         .stats_get            = eth_igbvf_stats_get,
 344         .stats_reset          = eth_igbvf_stats_reset,
 345         .vlan_filter_set      = igbvf_vlan_filter_set,
 346         .dev_infos_get        = eth_igbvf_infos_get,
 347         .rx_queue_setup       = eth_igb_rx_queue_setup,
 348         .rx_queue_release     = eth_igb_rx_queue_release,
 349         .tx_queue_setup       = eth_igb_tx_queue_setup,
 350         .tx_queue_release     = eth_igb_tx_queue_release,
 351         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 352         .mac_addr_set         = igbvf_default_mac_addr_set,
 353         .get_reg_length       = igbvf_get_reg_length,
 354         .get_reg              = igbvf_get_regs,
 355 };
 356
 357 /**
 358  * Atomically reads the link status information from global
 359  * structure rte_eth_dev.
 360  *
 361  * @param dev
 362  *   - Pointer to the structure rte_eth_dev to read from.
 363  *   - Pointer to the buffer to be saved with the link status.
 364  *
 365  * @return
 366  *   - On success, zero.
 367  *   - On failure, negative value.
 368  */
 369 static inline int
 370 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 371                                 struct rte_eth_link *link)
 372 {
 373         struct rte_eth_link *dst = link;
 374         struct rte_eth_link *src = &(dev->data->dev_link);
 375
 376         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 377                                         *(uint64_t *)src) == 0)
 378                 return -1;
 379
 380         return 0;
 381 }
 382
 383 /**
 384  * Atomically writes the link status information into global
 385  * structure rte_eth_dev.
 386  *
 387  * @param dev
 388  *   - Pointer to the structure rte_eth_dev to read from.
 389  *   - Pointer to the buffer to be saved with the link status.
 390  *
 391  * @return
 392  *   - On success, zero.
 393  *   - On failure, negative value.
 394  */
 395 static inline int
 396 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 397                                 struct rte_eth_link *link)
 398 {
 399         struct rte_eth_link *dst = &(dev->data->dev_link);
 400         struct rte_eth_link *src = link;
 401
 402         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 403                                         *(uint64_t *)src) == 0)
 404                 return -1;
 405
 406         return 0;
 407 }
 408
 409 static inline void
 410 igb_intr_enable(struct rte_eth_dev *dev)
 411 {
 412         struct e1000_interrupt *intr =
 413                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 414         struct e1000_hw *hw =
 415                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 416
 417         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 418         E1000_WRITE_FLUSH(hw);
 419 }
 420
 421 static void
 422 igb_intr_disable(struct e1000_hw *hw)
 423 {
 424         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 425         E1000_WRITE_FLUSH(hw);
 426 }
 427
 428 static inline int32_t
 429 igb_pf_reset_hw(struct e1000_hw *hw)
 430 {
 431         uint32_t ctrl_ext;
 432         int32_t status;
 433
 434         status = e1000_reset_hw(hw);
 435
 436         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 437         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 438         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 439         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 440         E1000_WRITE_FLUSH(hw);
 441
 442         return status;
 443 }
 444
 445 static void
 446 igb_identify_hardware(struct rte_eth_dev *dev)
 447 {
 448         struct e1000_hw *hw =
 449                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 450
 451         hw->vendor_id = dev->pci_dev->id.vendor_id;
 452         hw->device_id = dev->pci_dev->id.device_id;
 453         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 454         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 455
 456         e1000_set_mac_type(hw);
 457
 458         /* need to check if it is a vf device below */
 459 }
 460
 461 static int
 462 igb_reset_swfw_lock(struct e1000_hw *hw)
 463 {
 464         int ret_val;
 465
 466         /*
 467          * Do mac ops initialization manually here, since we will need
 468          * some function pointers set by this call.
 469          */
 470         ret_val = e1000_init_mac_params(hw);
 471         if (ret_val)
 472                 return ret_val;
 473
 474         /*
 475          * SMBI lock should not fail in this early stage. If this is the case,
 476          * it is due to an improper exit of the application.
 477          * So force the release of the faulty lock.
 478          */
 479         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 480                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 481         }
 482         e1000_put_hw_semaphore_generic(hw);
 483
 484         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 485                 uint16_t mask;
 486
 487                 /*
 488                  * Phy lock should not fail in this early stage. If this is the case,
 489                  * it is due to an improper exit of the application.
 490                  * So force the release of the faulty lock.
 491                  */
 492                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 493                 if (hw->bus.func > E1000_FUNC_1)
 494                         mask <<= 2;
 495                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 496                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 497                                     hw->bus.func);
 498                 }
 499                 hw->mac.ops.release_swfw_sync(hw, mask);
 500
 501                 /*
 502                  * This one is more tricky since it is common to all ports; but
 503                  * swfw_sync retries last long enough (1s) to be almost sure that if
 504                  * lock can not be taken it is due to an improper lock of the
 505                  * semaphore.
 506                  */
 507                 mask = E1000_SWFW_EEP_SM;
 508                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 509                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 510                 }
 511                 hw->mac.ops.release_swfw_sync(hw, mask);
 512         }
 513
 514         return E1000_SUCCESS;
 515 }
 516
 517 static int
 518 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 519 {
 520         int error = 0;
 521         struct rte_pci_device *pci_dev;
 522         struct e1000_hw *hw =
 523                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 524         struct e1000_vfta * shadow_vfta =
 525                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 526         struct e1000_filter_info *filter_info =
 527                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 528         struct e1000_adapter *adapter =
 529                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 530
 531         uint32_t ctrl_ext;
 532
 533         pci_dev = eth_dev->pci_dev;
 534         eth_dev->dev_ops = &eth_igb_ops;
 535         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 536         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 537
 538         /* for secondary processes, we don't initialise any further as primary
 539          * has already done this work. Only check we don't need a different
 540          * RX function */
 541         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 542                 if (eth_dev->data->scattered_rx)
 543                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 544                 return 0;
 545         }
 546
 547         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 548
 549         igb_identify_hardware(eth_dev);
 550         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 551                 error = -EIO;
 552                 goto err_late;
 553         }
 554
 555         e1000_get_bus_info(hw);
 556
 557         /* Reset any pending lock */
 558         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 559                 error = -EIO;
 560                 goto err_late;
 561         }
 562
 563         /* Finish initialization */
 564         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 565                 error = -EIO;
 566                 goto err_late;
 567         }
 568
 569         hw->mac.autoneg = 1;
 570         hw->phy.autoneg_wait_to_complete = 0;
 571         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 572
 573         /* Copper options */
 574         if (hw->phy.media_type == e1000_media_type_copper) {
 575                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 576                 hw->phy.disable_polarity_correction = 0;
 577                 hw->phy.ms_type = e1000_ms_hw_default;
 578         }
 579
 580         /*
 581          * Start from a known state, this is important in reading the nvm
 582          * and mac from that.
 583          */
 584         igb_pf_reset_hw(hw);
 585
 586         /* Make sure we have a good EEPROM before we read from it */
 587         if (e1000_validate_nvm_checksum(hw) < 0) {
 588                 /*
 589                  * Some PCI-E parts fail the first check due to
 590                  * the link being in sleep state, call it again,
 591                  * if it fails a second time its a real issue.
 592                  */
 593                 if (e1000_validate_nvm_checksum(hw) < 0) {
 594                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 595                         error = -EIO;
 596                         goto err_late;
 597                 }
 598         }
 599
 600         /* Read the permanent MAC address out of the EEPROM */
 601         if (e1000_read_mac_addr(hw) != 0) {
 602                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 603                 error = -EIO;
 604                 goto err_late;
 605         }
 606
 607         /* Allocate memory for storing MAC addresses */
 608         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 609                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 610         if (eth_dev->data->mac_addrs == NULL) {
 611                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 612                                                 "store MAC addresses",
 613                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 614                 error = -ENOMEM;
 615                 goto err_late;
 616         }
 617
 618         /* Copy the permanent MAC address */
 619         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 620
 621         /* initialize the vfta */
 622         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 623
 624         /* Now initialize the hardware */
 625         if (igb_hardware_init(hw) != 0) {
 626                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 627                 rte_free(eth_dev->data->mac_addrs);
 628                 eth_dev->data->mac_addrs = NULL;
 629                 error = -ENODEV;
 630                 goto err_late;
 631         }
 632         hw->mac.get_link_status = 1;
 633         adapter->stopped = 0;
 634
 635         /* Indicate SOL/IDER usage */
 636         if (e1000_check_reset_block(hw) < 0) {
 637                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 638                                         "SOL/IDER session");
 639         }
 640
 641         /* initialize PF if max_vfs not zero */
 642         igb_pf_host_init(eth_dev);
 643
 644         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 645         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 646         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 647         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 648         E1000_WRITE_FLUSH(hw);
 649
 650         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 651                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 652                      pci_dev->id.device_id);
 653
 654         /* enable support intr */
 655         igb_intr_enable(eth_dev);
 656
 657         TAILQ_INIT(&filter_info->flex_list);
 658         filter_info->flex_mask = 0;
 659         TAILQ_INIT(&filter_info->twotuple_list);
 660         filter_info->twotuple_mask = 0;
 661         TAILQ_INIT(&filter_info->fivetuple_list);
 662         filter_info->fivetuple_mask = 0;
 663
 664         return 0;
 665
 666 err_late:
 667         igb_hw_control_release(hw);
 668
 669         return (error);
 670 }
 671
 672 static int
 673 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 674 {
 675         struct rte_pci_device *pci_dev;
 676         struct e1000_hw *hw;
 677         struct e1000_adapter *adapter =
 678                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 679
 680         PMD_INIT_FUNC_TRACE();
 681
 682         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 683                 return -EPERM;
 684
 685         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 686         pci_dev = eth_dev->pci_dev;
 687
 688         if (adapter->stopped == 0)
 689                 eth_igb_close(eth_dev);
 690
 691         eth_dev->dev_ops = NULL;
 692         eth_dev->rx_pkt_burst = NULL;
 693         eth_dev->tx_pkt_burst = NULL;
 694
 695         /* Reset any pending lock */
 696         igb_reset_swfw_lock(hw);
 697
 698         rte_free(eth_dev->data->mac_addrs);
 699         eth_dev->data->mac_addrs = NULL;
 700
 701         /* uninitialize PF if max_vfs not zero */
 702         igb_pf_host_uninit(eth_dev);
 703
 704         /* disable uio intr before callback unregister */
 705         rte_intr_disable(&(pci_dev->intr_handle));
 706         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 707                 eth_igb_interrupt_handler, (void *)eth_dev);
 708
 709         return 0;
 710 }
 711
 712 /*
 713  * Virtual Function device init
 714  */
 715 static int
 716 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 717 {
 718         struct rte_pci_device *pci_dev;
 719         struct e1000_adapter *adapter =
 720                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 721         struct e1000_hw *hw =
 722                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 723         int diag;
 724
 725         PMD_INIT_FUNC_TRACE();
 726
 727         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 728         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 729         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 730
 731         /* for secondary processes, we don't initialise any further as primary
 732          * has already done this work. Only check we don't need a different
 733          * RX function */
 734         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 735                 if (eth_dev->data->scattered_rx)
 736                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 737                 return 0;
 738         }
 739
 740         pci_dev = eth_dev->pci_dev;
 741
 742         hw->device_id = pci_dev->id.device_id;
 743         hw->vendor_id = pci_dev->id.vendor_id;
 744         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 745         adapter->stopped = 0;
 746
 747         /* Initialize the shared code (base driver) */
 748         diag = e1000_setup_init_funcs(hw, TRUE);
 749         if (diag != 0) {
 750                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 751                         diag);
 752                 return -EIO;
 753         }
 754
 755         /* init_mailbox_params */
 756         hw->mbx.ops.init_params(hw);
 757
 758         /* Disable the interrupts for VF */
 759         igbvf_intr_disable(hw);
 760
 761         diag = hw->mac.ops.reset_hw(hw);
 762
 763         /* Allocate memory for storing MAC addresses */
 764         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 765                 hw->mac.rar_entry_count, 0);
 766         if (eth_dev->data->mac_addrs == NULL) {
 767                 PMD_INIT_LOG(ERR,
 768                         "Failed to allocate %d bytes needed to store MAC "
 769                         "addresses",
 770                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 771                 return -ENOMEM;
 772         }
 773
 774         /* Copy the permanent MAC address */
 775         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 776                         &eth_dev->data->mac_addrs[0]);
 777
 778         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 779                      "mac.type=%s",
 780                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 781                      pci_dev->id.device_id, "igb_mac_82576_vf");
 782
 783         return 0;
 784 }
 785
 786 static int
 787 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
 788 {
 789         struct e1000_adapter *adapter =
 790                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 791
 792         PMD_INIT_FUNC_TRACE();
 793
 794         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 795                 return -EPERM;
 796
 797         if (adapter->stopped == 0)
 798                 igbvf_dev_close(eth_dev);
 799
 800         eth_dev->dev_ops = NULL;
 801         eth_dev->rx_pkt_burst = NULL;
 802         eth_dev->tx_pkt_burst = NULL;
 803
 804         rte_free(eth_dev->data->mac_addrs);
 805         eth_dev->data->mac_addrs = NULL;
 806
 807         return 0;
 808 }
 809
 810 static struct eth_driver rte_igb_pmd = {
 811         .pci_drv = {
 812                 .name = "rte_igb_pmd",
 813                 .id_table = pci_id_igb_map,
 814                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 815                         RTE_PCI_DRV_DETACHABLE,
 816         },
 817         .eth_dev_init = eth_igb_dev_init,
 818         .eth_dev_uninit = eth_igb_dev_uninit,
 819         .dev_private_size = sizeof(struct e1000_adapter),
 820 };
 821
 822 /*
 823  * virtual function driver struct
 824  */
 825 static struct eth_driver rte_igbvf_pmd = {
 826         .pci_drv = {
 827                 .name = "rte_igbvf_pmd",
 828                 .id_table = pci_id_igbvf_map,
 829                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
 830         },
 831         .eth_dev_init = eth_igbvf_dev_init,
 832         .eth_dev_uninit = eth_igbvf_dev_uninit,
 833         .dev_private_size = sizeof(struct e1000_adapter),
 834 };
 835
 836 static int
 837 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 838 {
 839         rte_eth_driver_register(&rte_igb_pmd);
 840         return 0;
 841 }
 842
 843 static void
 844 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 845 {
 846         struct e1000_hw *hw =
 847                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 848         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 849         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 850         rctl |= E1000_RCTL_VFE;
 851         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 852 }
 853
 854 /*
 855  * VF Driver initialization routine.
 856  * Invoked one at EAL init time.
 857  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 858  */
 859 static int
 860 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 861 {
 862         PMD_INIT_FUNC_TRACE();
 863
 864         rte_eth_driver_register(&rte_igbvf_pmd);
 865         return (0);
 866 }
 867
 868 static int
 869 eth_igb_configure(struct rte_eth_dev *dev)
 870 {
 871         struct e1000_interrupt *intr =
 872                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 873
 874         PMD_INIT_FUNC_TRACE();
 875         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 876         PMD_INIT_FUNC_TRACE();
 877
 878         return (0);
 879 }
 880
 881 static int
 882 eth_igb_start(struct rte_eth_dev *dev)
 883 {
 884         struct e1000_hw *hw =
 885                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 886         struct e1000_adapter *adapter =
 887                 E1000_DEV_PRIVATE(dev->data->dev_private);
 888         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 889         int ret, mask;
 890         uint32_t intr_vector = 0;
 891         uint32_t ctrl_ext;
 892
 893         PMD_INIT_FUNC_TRACE();
 894
 895         /* Power up the phy. Needed to make the link go Up */
 896         e1000_power_up_phy(hw);
 897
 898         /*
 899          * Packet Buffer Allocation (PBA)
 900          * Writing PBA sets the receive portion of the buffer
 901          * the remainder is used for the transmit buffer.
 902          */
 903         if (hw->mac.type == e1000_82575) {
 904                 uint32_t pba;
 905
 906                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 907                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 908         }
 909
 910         /* Put the address into the Receive Address Array */
 911         e1000_rar_set(hw, hw->mac.addr, 0);
 912
 913         /* Initialize the hardware */
 914         if (igb_hardware_init(hw)) {
 915                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 916                 return (-EIO);
 917         }
 918         adapter->stopped = 0;
 919
 920         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 921
 922         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 923         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 924         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 925         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 926         E1000_WRITE_FLUSH(hw);
 927
 928         /* configure PF module if SRIOV enabled */
 929         igb_pf_host_configure(dev);
 930
 931         /* check and configure queue intr-vector mapping */
 932         if (dev->data->dev_conf.intr_conf.rxq != 0)
 933                 intr_vector = dev->data->nb_rx_queues;
 934
 935         if (rte_intr_efd_enable(intr_handle, intr_vector))
 936                 return -1;
 937
 938         if (rte_intr_dp_is_en(intr_handle)) {
 939                 intr_handle->intr_vec =
 940                         rte_zmalloc("intr_vec",
 941                                     dev->data->nb_rx_queues * sizeof(int), 0);
 942                 if (intr_handle->intr_vec == NULL) {
 943                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 944                                      " intr_vec\n", dev->data->nb_rx_queues);
 945                         return -ENOMEM;
 946                 }
 947         }
 948
 949         /* confiugre msix for rx interrupt */
 950         eth_igb_configure_msix_intr(dev);
 951
 952         /* Configure for OS presence */
 953         igb_init_manageability(hw);
 954
 955         eth_igb_tx_init(dev);
 956
 957         /* This can fail when allocating mbufs for descriptor rings */
 958         ret = eth_igb_rx_init(dev);
 959         if (ret) {
 960                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 961                 igb_dev_clear_queues(dev);
 962                 return ret;
 963         }
 964
 965         e1000_clear_hw_cntrs_base_generic(hw);
 966
 967         /*
 968          * VLAN Offload Settings
 969          */
 970         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 971                         ETH_VLAN_EXTEND_MASK;
 972         eth_igb_vlan_offload_set(dev, mask);
 973
 974         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 975                 /* Enable VLAN filter since VMDq always use VLAN filter */
 976                 igb_vmdq_vlan_hw_filter_enable(dev);
 977         }
 978
 979         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 980                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
 981                 (hw->mac.type == e1000_i211)) {
 982                 /* Configure EITR with the maximum possible value (0xFFFF) */
 983                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 984         }
 985
 986         /* Setup link speed and duplex */
 987         switch (dev->data->dev_conf.link_speed) {
 988         case ETH_LINK_SPEED_AUTONEG:
 989                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 990                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 991                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 992                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 993                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 994                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 995                 else
 996                         goto error_invalid_config;
 997                 break;
 998         case ETH_LINK_SPEED_10:
 999                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1000                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
1001                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1002                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
1003                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1004                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1005                 else
1006                         goto error_invalid_config;
1007                 break;
1008         case ETH_LINK_SPEED_100:
1009                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1010                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1011                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1012                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1013                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1014                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1015                 else
1016                         goto error_invalid_config;
1017                 break;
1018         case ETH_LINK_SPEED_1000:
1019                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1020                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1021                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1022                 else
1023                         goto error_invalid_config;
1024                 break;
1025         case ETH_LINK_SPEED_10000:
1026         default:
1027                 goto error_invalid_config;
1028         }
1029         e1000_setup_link(hw);
1030
1031         /* check if lsc interrupt feature is enabled */
1032         if (dev->data->dev_conf.intr_conf.lsc != 0) {
1033                 if (rte_intr_allow_others(intr_handle)) {
1034                         rte_intr_callback_register(intr_handle,
1035                                                    eth_igb_interrupt_handler,
1036                                                    (void *)dev);
1037                         eth_igb_lsc_interrupt_setup(dev);
1038                 } else
1039                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1040                                      " no intr multiplex\n");
1041         }
1042
1043         /* check if rxq interrupt is enabled */
1044         if (dev->data->dev_conf.intr_conf.rxq != 0)
1045                 eth_igb_rxq_interrupt_setup(dev);
1046
1047         /* enable uio/vfio intr/eventfd mapping */
1048         rte_intr_enable(intr_handle);
1049
1050         /* resume enabled intr since hw reset */
1051         igb_intr_enable(dev);
1052
1053         PMD_INIT_LOG(DEBUG, "<<");
1054
1055         return (0);
1056
1057 error_invalid_config:
1058         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1059                      dev->data->dev_conf.link_speed,
1060                      dev->data->dev_conf.link_duplex, dev->data->port_id);
1061         igb_dev_clear_queues(dev);
1062         return (-EINVAL);
1063 }
1064
1065 /*********************************************************************
1066  *
1067  *  This routine disables all traffic on the adapter by issuing a
1068  *  global reset on the MAC.
1069  *
1070  **********************************************************************/
1071 static void
1072 eth_igb_stop(struct rte_eth_dev *dev)
1073 {
1074         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1075         struct e1000_filter_info *filter_info =
1076                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1077         struct rte_eth_link link;
1078         struct e1000_flex_filter *p_flex;
1079         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1080         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1081         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1082
1083         igb_intr_disable(hw);
1084
1085         /* disable intr eventfd mapping */
1086         rte_intr_disable(intr_handle);
1087
1088         igb_pf_reset_hw(hw);
1089         E1000_WRITE_REG(hw, E1000_WUC, 0);
1090
1091         /* Set bit for Go Link disconnect */
1092         if (hw->mac.type >= e1000_82580) {
1093                 uint32_t phpm_reg;
1094
1095                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1096                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1097                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1098         }
1099
1100         /* Power down the phy. Needed to make the link go Down */
1101         if (hw->phy.media_type == e1000_media_type_copper)
1102                 e1000_power_down_phy(hw);
1103         else
1104                 e1000_shutdown_fiber_serdes_link(hw);
1105
1106         igb_dev_clear_queues(dev);
1107
1108         /* clear the recorded link status */
1109         memset(&link, 0, sizeof(link));
1110         rte_igb_dev_atomic_write_link_status(dev, &link);
1111
1112         /* Remove all flex filters of the device */
1113         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1114                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1115                 rte_free(p_flex);
1116         }
1117         filter_info->flex_mask = 0;
1118
1119         /* Remove all ntuple filters of the device */
1120         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1121              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1122                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1123                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1124                              p_5tuple, entries);
1125                 rte_free(p_5tuple);
1126         }
1127         filter_info->fivetuple_mask = 0;
1128         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1129              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1130                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1131                 TAILQ_REMOVE(&filter_info->twotuple_list,
1132                              p_2tuple, entries);
1133                 rte_free(p_2tuple);
1134         }
1135         filter_info->twotuple_mask = 0;
1136
1137         /* Clean datapath event and queue/vec mapping */
1138         rte_intr_efd_disable(intr_handle);
1139         if (intr_handle->intr_vec != NULL) {
1140                 rte_free(intr_handle->intr_vec);
1141                 intr_handle->intr_vec = NULL;
1142         }
1143 }
1144
1145 static void
1146 eth_igb_close(struct rte_eth_dev *dev)
1147 {
1148         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1149         struct e1000_adapter *adapter =
1150                 E1000_DEV_PRIVATE(dev->data->dev_private);
1151         struct rte_eth_link link;
1152         struct rte_pci_device *pci_dev;
1153
1154         eth_igb_stop(dev);
1155         adapter->stopped = 1;
1156
1157         e1000_phy_hw_reset(hw);
1158         igb_release_manageability(hw);
1159         igb_hw_control_release(hw);
1160
1161         /* Clear bit for Go Link disconnect */
1162         if (hw->mac.type >= e1000_82580) {
1163                 uint32_t phpm_reg;
1164
1165                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1166                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1167                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1168         }
1169
1170         igb_dev_free_queues(dev);
1171
1172         pci_dev = dev->pci_dev;
1173         if (pci_dev->intr_handle.intr_vec) {
1174                 rte_free(pci_dev->intr_handle.intr_vec);
1175                 pci_dev->intr_handle.intr_vec = NULL;
1176         }
1177
1178         memset(&link, 0, sizeof(link));
1179         rte_igb_dev_atomic_write_link_status(dev, &link);
1180 }
1181
1182 static int
1183 igb_get_rx_buffer_size(struct e1000_hw *hw)
1184 {
1185         uint32_t rx_buf_size;
1186         if (hw->mac.type == e1000_82576) {
1187                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1188         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1189                 /* PBS needs to be translated according to a lookup table */
1190                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1191                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1192                 rx_buf_size = (rx_buf_size << 10);
1193         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1194                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1195         } else {
1196                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1197         }
1198
1199         return rx_buf_size;
1200 }
1201
1202 /*********************************************************************
1203  *
1204  *  Initialize the hardware
1205  *
1206  **********************************************************************/
1207 static int
1208 igb_hardware_init(struct e1000_hw *hw)
1209 {
1210         uint32_t rx_buf_size;
1211         int diag;
1212
1213         /* Let the firmware know the OS is in control */
1214         igb_hw_control_acquire(hw);
1215
1216         /*
1217          * These parameters control the automatic generation (Tx) and
1218          * response (Rx) to Ethernet PAUSE frames.
1219          * - High water mark should allow for at least two standard size (1518)
1220          *   frames to be received after sending an XOFF.
1221          * - Low water mark works best when it is very near the high water mark.
1222          *   This allows the receiver to restart by sending XON when it has
1223          *   drained a bit. Here we use an arbitrary value of 1500 which will
1224          *   restart after one full frame is pulled from the buffer. There
1225          *   could be several smaller frames in the buffer and if so they will
1226          *   not trigger the XON until their total number reduces the buffer
1227          *   by 1500.
1228          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1229          */
1230         rx_buf_size = igb_get_rx_buffer_size(hw);
1231
1232         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1233         hw->fc.low_water = hw->fc.high_water - 1500;
1234         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1235         hw->fc.send_xon = 1;
1236
1237         /* Set Flow control, use the tunable location if sane */
1238         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1239                 hw->fc.requested_mode = igb_fc_setting;
1240         else
1241                 hw->fc.requested_mode = e1000_fc_none;
1242
1243         /* Issue a global reset */
1244         igb_pf_reset_hw(hw);
1245         E1000_WRITE_REG(hw, E1000_WUC, 0);
1246
1247         diag = e1000_init_hw(hw);
1248         if (diag < 0)
1249                 return (diag);
1250
1251         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1252         e1000_get_phy_info(hw);
1253         e1000_check_for_link(hw);
1254
1255         return (0);
1256 }
1257
1258 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1259 static void
1260 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1261 {
1262         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1263         struct e1000_hw_stats *stats =
1264                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1265         int pause_frames;
1266
1267         if(hw->phy.media_type == e1000_media_type_copper ||
1268             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1269                 stats->symerrs +=
1270                     E1000_READ_REG(hw,E1000_SYMERRS);
1271                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1272         }
1273
1274         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1275         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1276         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1277         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1278
1279         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1280         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1281         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1282         stats->dc += E1000_READ_REG(hw, E1000_DC);
1283         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1284         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1285         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1286         /*
1287         ** For watchdog management we need to know if we have been
1288         ** paused during the last interval, so capture that here.
1289         */
1290         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1291         stats->xoffrxc += pause_frames;
1292         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1293         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1294         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1295         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1296         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1297         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1298         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1299         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1300         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1301         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1302         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1303         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1304
1305         /* For the 64-bit byte counters the low dword must be read first. */
1306         /* Both registers clear on the read of the high dword */
1307
1308         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1309         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1310         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1311         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1312
1313         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1314         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1315         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1316         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1317         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1318
1319         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1320         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1321         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1322         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1323
1324         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1325         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1326         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1327         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1328         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1329         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1330         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1331         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1332         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1333         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1334
1335         /* Interrupt Counts */
1336
1337         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1338         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1339         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1340         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1341         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1342         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1343         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1344         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1345         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1346
1347         /* Host to Card Statistics */
1348
1349         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1350         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1351         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1352         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1353         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1354         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1355         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1356         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1357         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1358         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1359         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1360         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1361         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1362         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1363
1364         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1365         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1366         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1367         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1368         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1369         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1370
1371         if (rte_stats == NULL)
1372                 return;
1373
1374         /* Rx Errors */
1375         rte_stats->ibadcrc = stats->crcerrs;
1376         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1377         rte_stats->imissed = stats->mpc;
1378         rte_stats->ierrors = rte_stats->ibadcrc +
1379                              rte_stats->ibadlen +
1380                              rte_stats->imissed +
1381                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1382
1383         /* Tx Errors */
1384         rte_stats->oerrors = stats->ecol + stats->latecol;
1385
1386         /* XON/XOFF pause frames */
1387         rte_stats->tx_pause_xon  = stats->xontxc;
1388         rte_stats->rx_pause_xon  = stats->xonrxc;
1389         rte_stats->tx_pause_xoff = stats->xofftxc;
1390         rte_stats->rx_pause_xoff = stats->xoffrxc;
1391
1392         rte_stats->ipackets = stats->gprc;
1393         rte_stats->opackets = stats->gptc;
1394         rte_stats->ibytes   = stats->gorc;
1395         rte_stats->obytes   = stats->gotc;
1396 }
1397
1398 static void
1399 eth_igb_stats_reset(struct rte_eth_dev *dev)
1400 {
1401         struct e1000_hw_stats *hw_stats =
1402                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1403
1404         /* HW registers are cleared on read */
1405         eth_igb_stats_get(dev, NULL);
1406
1407         /* Reset software totals */
1408         memset(hw_stats, 0, sizeof(*hw_stats));
1409 }
1410
1411 static void
1412 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1413 {
1414         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1415         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1416                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1417
1418         /* Good Rx packets, include VF loopback */
1419         UPDATE_VF_STAT(E1000_VFGPRC,
1420             hw_stats->last_gprc, hw_stats->gprc);
1421
1422         /* Good Rx octets, include VF loopback */
1423         UPDATE_VF_STAT(E1000_VFGORC,
1424             hw_stats->last_gorc, hw_stats->gorc);
1425
1426         /* Good Tx packets, include VF loopback */
1427         UPDATE_VF_STAT(E1000_VFGPTC,
1428             hw_stats->last_gptc, hw_stats->gptc);
1429
1430         /* Good Tx octets, include VF loopback */
1431         UPDATE_VF_STAT(E1000_VFGOTC,
1432             hw_stats->last_gotc, hw_stats->gotc);
1433
1434         /* Rx Multicst packets */
1435         UPDATE_VF_STAT(E1000_VFMPRC,
1436             hw_stats->last_mprc, hw_stats->mprc);
1437
1438         /* Good Rx loopback packets */
1439         UPDATE_VF_STAT(E1000_VFGPRLBC,
1440             hw_stats->last_gprlbc, hw_stats->gprlbc);
1441
1442         /* Good Rx loopback octets */
1443         UPDATE_VF_STAT(E1000_VFGORLBC,
1444             hw_stats->last_gorlbc, hw_stats->gorlbc);
1445
1446         /* Good Tx loopback packets */
1447         UPDATE_VF_STAT(E1000_VFGPTLBC,
1448             hw_stats->last_gptlbc, hw_stats->gptlbc);
1449
1450         /* Good Tx loopback octets */
1451         UPDATE_VF_STAT(E1000_VFGOTLBC,
1452             hw_stats->last_gotlbc, hw_stats->gotlbc);
1453
1454         if (rte_stats == NULL)
1455                 return;
1456
1457         rte_stats->ipackets = hw_stats->gprc;
1458         rte_stats->ibytes = hw_stats->gorc;
1459         rte_stats->opackets = hw_stats->gptc;
1460         rte_stats->obytes = hw_stats->gotc;
1461         rte_stats->imcasts = hw_stats->mprc;
1462         rte_stats->ilbpackets = hw_stats->gprlbc;
1463         rte_stats->ilbbytes = hw_stats->gorlbc;
1464         rte_stats->olbpackets = hw_stats->gptlbc;
1465         rte_stats->olbbytes = hw_stats->gotlbc;
1466
1467 }
1468
1469 static void
1470 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1471 {
1472         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1473                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1474
1475         /* Sync HW register to the last stats */
1476         eth_igbvf_stats_get(dev, NULL);
1477
1478         /* reset HW current stats*/
1479         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1480                offsetof(struct e1000_vf_stats, gprc));
1481
1482 }
1483
1484 static void
1485 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1486 {
1487         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1488
1489         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1490         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1491         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1492         dev_info->rx_offload_capa =
1493                 DEV_RX_OFFLOAD_VLAN_STRIP |
1494                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1495                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1496                 DEV_RX_OFFLOAD_TCP_CKSUM;
1497         dev_info->tx_offload_capa =
1498                 DEV_TX_OFFLOAD_VLAN_INSERT |
1499                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1500                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1501                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1502                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1503
1504         switch (hw->mac.type) {
1505         case e1000_82575:
1506                 dev_info->max_rx_queues = 4;
1507                 dev_info->max_tx_queues = 4;
1508                 dev_info->max_vmdq_pools = 0;
1509                 break;
1510
1511         case e1000_82576:
1512                 dev_info->max_rx_queues = 16;
1513                 dev_info->max_tx_queues = 16;
1514                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1515                 dev_info->vmdq_queue_num = 16;
1516                 break;
1517
1518         case e1000_82580:
1519                 dev_info->max_rx_queues = 8;
1520                 dev_info->max_tx_queues = 8;
1521                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1522                 dev_info->vmdq_queue_num = 8;
1523                 break;
1524
1525         case e1000_i350:
1526                 dev_info->max_rx_queues = 8;
1527                 dev_info->max_tx_queues = 8;
1528                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1529                 dev_info->vmdq_queue_num = 8;
1530                 break;
1531
1532         case e1000_i354:
1533                 dev_info->max_rx_queues = 8;
1534                 dev_info->max_tx_queues = 8;
1535                 break;
1536
1537         case e1000_i210:
1538                 dev_info->max_rx_queues = 4;
1539                 dev_info->max_tx_queues = 4;
1540                 dev_info->max_vmdq_pools = 0;
1541                 break;
1542
1543         case e1000_i211:
1544                 dev_info->max_rx_queues = 2;
1545                 dev_info->max_tx_queues = 2;
1546                 dev_info->max_vmdq_pools = 0;
1547                 break;
1548
1549         default:
1550                 /* Should not happen */
1551                 break;
1552         }
1553         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1554         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1555         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1556
1557         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1558                 .rx_thresh = {
1559                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1560                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1561                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1562                 },
1563                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1564                 .rx_drop_en = 0,
1565         };
1566
1567         dev_info->default_txconf = (struct rte_eth_txconf) {
1568                 .tx_thresh = {
1569                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1570                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1571                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1572                 },
1573                 .txq_flags = 0,
1574         };
1575 }
1576
1577 static void
1578 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1579 {
1580         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1581
1582         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1583         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1584         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1585         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1586                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1587                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1588                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1589         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1590                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1591                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1592                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1593                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1594         switch (hw->mac.type) {
1595         case e1000_vfadapt:
1596                 dev_info->max_rx_queues = 2;
1597                 dev_info->max_tx_queues = 2;
1598                 break;
1599         case e1000_vfadapt_i350:
1600                 dev_info->max_rx_queues = 1;
1601                 dev_info->max_tx_queues = 1;
1602                 break;
1603         default:
1604                 /* Should not happen */
1605                 break;
1606         }
1607
1608         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1609                 .rx_thresh = {
1610                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1611                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1612                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1613                 },
1614                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1615                 .rx_drop_en = 0,
1616         };
1617
1618         dev_info->default_txconf = (struct rte_eth_txconf) {
1619                 .tx_thresh = {
1620                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1621                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1622                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1623                 },
1624                 .txq_flags = 0,
1625         };
1626 }
1627
1628 /* return 0 means link status changed, -1 means not changed */
1629 static int
1630 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1631 {
1632         struct e1000_hw *hw =
1633                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1634         struct rte_eth_link link, old;
1635         int link_check, count;
1636
1637         link_check = 0;
1638         hw->mac.get_link_status = 1;
1639
1640         /* possible wait-to-complete in up to 9 seconds */
1641         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1642                 /* Read the real link status */
1643                 switch (hw->phy.media_type) {
1644                 case e1000_media_type_copper:
1645                         /* Do the work to read phy */
1646                         e1000_check_for_link(hw);
1647                         link_check = !hw->mac.get_link_status;
1648                         break;
1649
1650                 case e1000_media_type_fiber:
1651                         e1000_check_for_link(hw);
1652                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1653                                       E1000_STATUS_LU);
1654                         break;
1655
1656                 case e1000_media_type_internal_serdes:
1657                         e1000_check_for_link(hw);
1658                         link_check = hw->mac.serdes_has_link;
1659                         break;
1660
1661                 /* VF device is type_unknown */
1662                 case e1000_media_type_unknown:
1663                         eth_igbvf_link_update(hw);
1664                         link_check = !hw->mac.get_link_status;
1665                         break;
1666
1667                 default:
1668                         break;
1669                 }
1670                 if (link_check || wait_to_complete == 0)
1671                         break;
1672                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1673         }
1674         memset(&link, 0, sizeof(link));
1675         rte_igb_dev_atomic_read_link_status(dev, &link);
1676         old = link;
1677
1678         /* Now we check if a transition has happened */
1679         if (link_check) {
1680                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1681                                           &link.link_duplex);
1682                 link.link_status = 1;
1683         } else if (!link_check) {
1684                 link.link_speed = 0;
1685                 link.link_duplex = 0;
1686                 link.link_status = 0;
1687         }
1688         rte_igb_dev_atomic_write_link_status(dev, &link);
1689
1690         /* not changed */
1691         if (old.link_status == link.link_status)
1692                 return -1;
1693
1694         /* changed */
1695         return 0;
1696 }
1697
1698 /*
1699  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1700  * For ASF and Pass Through versions of f/w this means
1701  * that the driver is loaded.
1702  */
1703 static void
1704 igb_hw_control_acquire(struct e1000_hw *hw)
1705 {
1706         uint32_t ctrl_ext;
1707
1708         /* Let firmware know the driver has taken over */
1709         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1710         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1711 }
1712
1713 /*
1714  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1715  * For ASF and Pass Through versions of f/w this means that the
1716  * driver is no longer loaded.
1717  */
1718 static void
1719 igb_hw_control_release(struct e1000_hw *hw)
1720 {
1721         uint32_t ctrl_ext;
1722
1723         /* Let firmware taken over control of h/w */
1724         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1725         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1726                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1727 }
1728
1729 /*
1730  * Bit of a misnomer, what this really means is
1731  * to enable OS management of the system... aka
1732  * to disable special hardware management features.
1733  */
1734 static void
1735 igb_init_manageability(struct e1000_hw *hw)
1736 {
1737         if (e1000_enable_mng_pass_thru(hw)) {
1738                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1739                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1740
1741                 /* disable hardware interception of ARP */
1742                 manc &= ~(E1000_MANC_ARP_EN);
1743
1744                 /* enable receiving management packets to the host */
1745                 manc |= E1000_MANC_EN_MNG2HOST;
1746                 manc2h |= 1 << 5;  /* Mng Port 623 */
1747                 manc2h |= 1 << 6;  /* Mng Port 664 */
1748                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1749                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1750         }
1751 }
1752
1753 static void
1754 igb_release_manageability(struct e1000_hw *hw)
1755 {
1756         if (e1000_enable_mng_pass_thru(hw)) {
1757                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1758
1759                 manc |= E1000_MANC_ARP_EN;
1760                 manc &= ~E1000_MANC_EN_MNG2HOST;
1761
1762                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1763         }
1764 }
1765
1766 static void
1767 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1768 {
1769         struct e1000_hw *hw =
1770                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1771         uint32_t rctl;
1772
1773         rctl = E1000_READ_REG(hw, E1000_RCTL);
1774         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1775         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1776 }
1777
1778 static void
1779 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1780 {
1781         struct e1000_hw *hw =
1782                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1783         uint32_t rctl;
1784
1785         rctl = E1000_READ_REG(hw, E1000_RCTL);
1786         rctl &= (~E1000_RCTL_UPE);
1787         if (dev->data->all_multicast == 1)
1788                 rctl |= E1000_RCTL_MPE;
1789         else
1790                 rctl &= (~E1000_RCTL_MPE);
1791         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1792 }
1793
1794 static void
1795 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1796 {
1797         struct e1000_hw *hw =
1798                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1799         uint32_t rctl;
1800
1801         rctl = E1000_READ_REG(hw, E1000_RCTL);
1802         rctl |= E1000_RCTL_MPE;
1803         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1804 }
1805
1806 static void
1807 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1808 {
1809         struct e1000_hw *hw =
1810                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1811         uint32_t rctl;
1812
1813         if (dev->data->promiscuous == 1)
1814                 return; /* must remain in all_multicast mode */
1815         rctl = E1000_READ_REG(hw, E1000_RCTL);
1816         rctl &= (~E1000_RCTL_MPE);
1817         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1818 }
1819
1820 static int
1821 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1822 {
1823         struct e1000_hw *hw =
1824                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1825         struct e1000_vfta * shadow_vfta =
1826                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1827         uint32_t vfta;
1828         uint32_t vid_idx;
1829         uint32_t vid_bit;
1830
1831         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1832                               E1000_VFTA_ENTRY_MASK);
1833         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1834         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1835         if (on)
1836                 vfta |= vid_bit;
1837         else
1838                 vfta &= ~vid_bit;
1839         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1840
1841         /* update local VFTA copy */
1842         shadow_vfta->vfta[vid_idx] = vfta;
1843
1844         return 0;
1845 }
1846
1847 static void
1848 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1849 {
1850         struct e1000_hw *hw =
1851                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1852         uint32_t reg = ETHER_TYPE_VLAN ;
1853
1854         reg |= (tpid << 16);
1855         E1000_WRITE_REG(hw, E1000_VET, reg);
1856 }
1857
1858 static void
1859 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1860 {
1861         struct e1000_hw *hw =
1862                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1863         uint32_t reg;
1864
1865         /* Filter Table Disable */
1866         reg = E1000_READ_REG(hw, E1000_RCTL);
1867         reg &= ~E1000_RCTL_CFIEN;
1868         reg &= ~E1000_RCTL_VFE;
1869         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1870 }
1871
1872 static void
1873 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1874 {
1875         struct e1000_hw *hw =
1876                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1877         struct e1000_vfta * shadow_vfta =
1878                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1879         uint32_t reg;
1880         int i;
1881
1882         /* Filter Table Enable, CFI not used for packet acceptance */
1883         reg = E1000_READ_REG(hw, E1000_RCTL);
1884         reg &= ~E1000_RCTL_CFIEN;
1885         reg |= E1000_RCTL_VFE;
1886         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1887
1888         /* restore VFTA table */
1889         for (i = 0; i < IGB_VFTA_SIZE; i++)
1890                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1891 }
1892
1893 static void
1894 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1895 {
1896         struct e1000_hw *hw =
1897                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1898         uint32_t reg;
1899
1900         /* VLAN Mode Disable */
1901         reg = E1000_READ_REG(hw, E1000_CTRL);
1902         reg &= ~E1000_CTRL_VME;
1903         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1904 }
1905
1906 static void
1907 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1908 {
1909         struct e1000_hw *hw =
1910                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1911         uint32_t reg;
1912
1913         /* VLAN Mode Enable */
1914         reg = E1000_READ_REG(hw, E1000_CTRL);
1915         reg |= E1000_CTRL_VME;
1916         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1917 }
1918
1919 static void
1920 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1921 {
1922         struct e1000_hw *hw =
1923                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924         uint32_t reg;
1925
1926         /* CTRL_EXT: Extended VLAN */
1927         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1928         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1929         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1930
1931         /* Update maximum packet length */
1932         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1933                 E1000_WRITE_REG(hw, E1000_RLPML,
1934                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1935                                                 VLAN_TAG_SIZE);
1936 }
1937
1938 static void
1939 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1940 {
1941         struct e1000_hw *hw =
1942                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943         uint32_t reg;
1944
1945         /* CTRL_EXT: Extended VLAN */
1946         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1947         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1948         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1949
1950         /* Update maximum packet length */
1951         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1952                 E1000_WRITE_REG(hw, E1000_RLPML,
1953                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1954                                                 2 * VLAN_TAG_SIZE);
1955 }
1956
1957 static void
1958 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1959 {
1960         if(mask & ETH_VLAN_STRIP_MASK){
1961                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1962                         igb_vlan_hw_strip_enable(dev);
1963                 else
1964                         igb_vlan_hw_strip_disable(dev);
1965         }
1966
1967         if(mask & ETH_VLAN_FILTER_MASK){
1968                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1969                         igb_vlan_hw_filter_enable(dev);
1970                 else
1971                         igb_vlan_hw_filter_disable(dev);
1972         }
1973
1974         if(mask & ETH_VLAN_EXTEND_MASK){
1975                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1976                         igb_vlan_hw_extend_enable(dev);
1977                 else
1978                         igb_vlan_hw_extend_disable(dev);
1979         }
1980 }
1981
1982
1983 /**
1984  * It enables the interrupt mask and then enable the interrupt.
1985  *
1986  * @param dev
1987  *  Pointer to struct rte_eth_dev.
1988  *
1989  * @return
1990  *  - On success, zero.
1991  *  - On failure, a negative value.
1992  */
1993 static int
1994 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1995 {
1996         struct e1000_interrupt *intr =
1997                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1998
1999         intr->mask |= E1000_ICR_LSC;
2000
2001         return 0;
2002 }
2003
2004 /* It clears the interrupt causes and enables the interrupt.
2005  * It will be called once only during nic initialized.
2006  *
2007  * @param dev
2008  *  Pointer to struct rte_eth_dev.
2009  *
2010  * @return
2011  *  - On success, zero.
2012  *  - On failure, a negative value.
2013  */
2014 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2015 {
2016         uint32_t mask, regval;
2017         struct e1000_hw *hw =
2018                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2019         struct rte_eth_dev_info dev_info;
2020
2021         memset(&dev_info, 0, sizeof(dev_info));
2022         eth_igb_infos_get(dev, &dev_info);
2023
2024         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2025         regval = E1000_READ_REG(hw, E1000_EIMS);
2026         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2027
2028         return 0;
2029 }
2030
2031 /*
2032  * It reads ICR and gets interrupt causes, check it and set a bit flag
2033  * to update link status.
2034  *
2035  * @param dev
2036  *  Pointer to struct rte_eth_dev.
2037  *
2038  * @return
2039  *  - On success, zero.
2040  *  - On failure, a negative value.
2041  */
2042 static int
2043 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2044 {
2045         uint32_t icr;
2046         struct e1000_hw *hw =
2047                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2048         struct e1000_interrupt *intr =
2049                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2050
2051         igb_intr_disable(hw);
2052
2053         /* read-on-clear nic registers here */
2054         icr = E1000_READ_REG(hw, E1000_ICR);
2055
2056         intr->flags = 0;
2057         if (icr & E1000_ICR_LSC) {
2058                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2059         }
2060
2061         if (icr & E1000_ICR_VMMB)
2062                 intr->flags |= E1000_FLAG_MAILBOX;
2063
2064         return 0;
2065 }
2066
2067 /*
2068  * It executes link_update after knowing an interrupt is prsent.
2069  *
2070  * @param dev
2071  *  Pointer to struct rte_eth_dev.
2072  *
2073  * @return
2074  *  - On success, zero.
2075  *  - On failure, a negative value.
2076  */
2077 static int
2078 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2079 {
2080         struct e1000_hw *hw =
2081                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2082         struct e1000_interrupt *intr =
2083                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2084         uint32_t tctl, rctl;
2085         struct rte_eth_link link;
2086         int ret;
2087
2088         if (intr->flags & E1000_FLAG_MAILBOX) {
2089                 igb_pf_mbx_process(dev);
2090                 intr->flags &= ~E1000_FLAG_MAILBOX;
2091         }
2092
2093         igb_intr_enable(dev);
2094         rte_intr_enable(&(dev->pci_dev->intr_handle));
2095
2096         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2097                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2098
2099                 /* set get_link_status to check register later */
2100                 hw->mac.get_link_status = 1;
2101                 ret = eth_igb_link_update(dev, 0);
2102
2103                 /* check if link has changed */
2104                 if (ret < 0)
2105                         return 0;
2106
2107                 memset(&link, 0, sizeof(link));
2108                 rte_igb_dev_atomic_read_link_status(dev, &link);
2109                 if (link.link_status) {
2110                         PMD_INIT_LOG(INFO,
2111                                      " Port %d: Link Up - speed %u Mbps - %s",
2112                                      dev->data->port_id,
2113                                      (unsigned)link.link_speed,
2114                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2115                                      "full-duplex" : "half-duplex");
2116                 } else {
2117                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2118                                      dev->data->port_id);
2119                 }
2120
2121                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2122                              dev->pci_dev->addr.domain,
2123                              dev->pci_dev->addr.bus,
2124                              dev->pci_dev->addr.devid,
2125                              dev->pci_dev->addr.function);
2126                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2127                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2128                 if (link.link_status) {
2129                         /* enable Tx/Rx */
2130                         tctl |= E1000_TCTL_EN;
2131                         rctl |= E1000_RCTL_EN;
2132                 } else {
2133                         /* disable Tx/Rx */
2134                         tctl &= ~E1000_TCTL_EN;
2135                         rctl &= ~E1000_RCTL_EN;
2136                 }
2137                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2138                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2139                 E1000_WRITE_FLUSH(hw);
2140                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2141         }
2142
2143         return 0;
2144 }
2145
2146 /**
2147  * Interrupt handler which shall be registered at first.
2148  *
2149  * @param handle
2150  *  Pointer to interrupt handle.
2151  * @param param
2152  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2153  *
2154  * @return
2155  *  void
2156  */
2157 static void
2158 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2159                                                         void *param)
2160 {
2161         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2162
2163         eth_igb_interrupt_get_status(dev);
2164         eth_igb_interrupt_action(dev);
2165 }
2166
2167 static int
2168 eth_igb_led_on(struct rte_eth_dev *dev)
2169 {
2170         struct e1000_hw *hw;
2171
2172         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2174 }
2175
2176 static int
2177 eth_igb_led_off(struct rte_eth_dev *dev)
2178 {
2179         struct e1000_hw *hw;
2180
2181         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2182         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2183 }
2184
2185 static int
2186 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2187 {
2188         struct e1000_hw *hw;
2189         uint32_t ctrl;
2190         int tx_pause;
2191         int rx_pause;
2192
2193         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2194         fc_conf->pause_time = hw->fc.pause_time;
2195         fc_conf->high_water = hw->fc.high_water;
2196         fc_conf->low_water = hw->fc.low_water;
2197         fc_conf->send_xon = hw->fc.send_xon;
2198         fc_conf->autoneg = hw->mac.autoneg;
2199
2200         /*
2201          * Return rx_pause and tx_pause status according to actual setting of
2202          * the TFCE and RFCE bits in the CTRL register.
2203          */
2204         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2205         if (ctrl & E1000_CTRL_TFCE)
2206                 tx_pause = 1;
2207         else
2208                 tx_pause = 0;
2209
2210         if (ctrl & E1000_CTRL_RFCE)
2211                 rx_pause = 1;
2212         else
2213                 rx_pause = 0;
2214
2215         if (rx_pause && tx_pause)
2216                 fc_conf->mode = RTE_FC_FULL;
2217         else if (rx_pause)
2218                 fc_conf->mode = RTE_FC_RX_PAUSE;
2219         else if (tx_pause)
2220                 fc_conf->mode = RTE_FC_TX_PAUSE;
2221         else
2222                 fc_conf->mode = RTE_FC_NONE;
2223
2224         return 0;
2225 }
2226
2227 static int
2228 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2229 {
2230         struct e1000_hw *hw;
2231         int err;
2232         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2233                 e1000_fc_none,
2234                 e1000_fc_rx_pause,
2235                 e1000_fc_tx_pause,
2236                 e1000_fc_full
2237         };
2238         uint32_t rx_buf_size;
2239         uint32_t max_high_water;
2240         uint32_t rctl;
2241
2242         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2243         if (fc_conf->autoneg != hw->mac.autoneg)
2244                 return -ENOTSUP;
2245         rx_buf_size = igb_get_rx_buffer_size(hw);
2246         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2247
2248         /* At least reserve one Ethernet frame for watermark */
2249         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2250         if ((fc_conf->high_water > max_high_water) ||
2251             (fc_conf->high_water < fc_conf->low_water)) {
2252                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2253                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2254                 return (-EINVAL);
2255         }
2256
2257         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2258         hw->fc.pause_time     = fc_conf->pause_time;
2259         hw->fc.high_water     = fc_conf->high_water;
2260         hw->fc.low_water      = fc_conf->low_water;
2261         hw->fc.send_xon       = fc_conf->send_xon;
2262
2263         err = e1000_setup_link_generic(hw);
2264         if (err == E1000_SUCCESS) {
2265
2266                 /* check if we want to forward MAC frames - driver doesn't have native
2267                  * capability to do that, so we'll write the registers ourselves */
2268
2269                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2270
2271                 /* set or clear MFLCN.PMCF bit depending on configuration */
2272                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2273                         rctl |= E1000_RCTL_PMCF;
2274                 else
2275                         rctl &= ~E1000_RCTL_PMCF;
2276
2277                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2278                 E1000_WRITE_FLUSH(hw);
2279
2280                 return 0;
2281         }
2282
2283         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2284         return (-EIO);
2285 }
2286
2287 #define E1000_RAH_POOLSEL_SHIFT      (18)
2288 static void
2289 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2290                 uint32_t index, __rte_unused uint32_t pool)
2291 {
2292         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2293         uint32_t rah;
2294
2295         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2296         rah = E1000_READ_REG(hw, E1000_RAH(index));
2297         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2298         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2299 }
2300
2301 static void
2302 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2303 {
2304         uint8_t addr[ETHER_ADDR_LEN];
2305         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2306
2307         memset(addr, 0, sizeof(addr));
2308
2309         e1000_rar_set(hw, addr, index);
2310 }
2311
2312 static void
2313 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2314                                 struct ether_addr *addr)
2315 {
2316         eth_igb_rar_clear(dev, 0);
2317
2318         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2319 }
2320 /*
2321  * Virtual Function operations
2322  */
2323 static void
2324 igbvf_intr_disable(struct e1000_hw *hw)
2325 {
2326         PMD_INIT_FUNC_TRACE();
2327
2328         /* Clear interrupt mask to stop from interrupts being generated */
2329         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2330
2331         E1000_WRITE_FLUSH(hw);
2332 }
2333
2334 static void
2335 igbvf_stop_adapter(struct rte_eth_dev *dev)
2336 {
2337         u32 reg_val;
2338         u16 i;
2339         struct rte_eth_dev_info dev_info;
2340         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2341
2342         memset(&dev_info, 0, sizeof(dev_info));
2343         eth_igbvf_infos_get(dev, &dev_info);
2344
2345         /* Clear interrupt mask to stop from interrupts being generated */
2346         igbvf_intr_disable(hw);
2347
2348         /* Clear any pending interrupts, flush previous writes */
2349         E1000_READ_REG(hw, E1000_EICR);
2350
2351         /* Disable the transmit unit.  Each queue must be disabled. */
2352         for (i = 0; i < dev_info.max_tx_queues; i++)
2353                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2354
2355         /* Disable the receive unit by stopping each queue */
2356         for (i = 0; i < dev_info.max_rx_queues; i++) {
2357                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2358                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2359                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2360                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2361                         ;
2362         }
2363
2364         /* flush all queues disables */
2365         E1000_WRITE_FLUSH(hw);
2366         msec_delay(2);
2367 }
2368
2369 static int eth_igbvf_link_update(struct e1000_hw *hw)
2370 {
2371         struct e1000_mbx_info *mbx = &hw->mbx;
2372         struct e1000_mac_info *mac = &hw->mac;
2373         int ret_val = E1000_SUCCESS;
2374
2375         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2376
2377         /*
2378          * We only want to run this if there has been a rst asserted.
2379          * in this case that could mean a link change, device reset,
2380          * or a virtual function reset
2381          */
2382
2383         /* If we were hit with a reset or timeout drop the link */
2384         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2385                 mac->get_link_status = TRUE;
2386
2387         if (!mac->get_link_status)
2388                 goto out;
2389
2390         /* if link status is down no point in checking to see if pf is up */
2391         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2392                 goto out;
2393
2394         /* if we passed all the tests above then the link is up and we no
2395          * longer need to check for link */
2396         mac->get_link_status = FALSE;
2397
2398 out:
2399         return ret_val;
2400 }
2401
2402
2403 static int
2404 igbvf_dev_configure(struct rte_eth_dev *dev)
2405 {
2406         struct rte_eth_conf* conf = &dev->data->dev_conf;
2407
2408         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2409                      dev->data->port_id);
2410
2411         /*
2412          * VF has no ability to enable/disable HW CRC
2413          * Keep the persistent behavior the same as Host PF
2414          */
2415 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2416         if (!conf->rxmode.hw_strip_crc) {
2417                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2418                 conf->rxmode.hw_strip_crc = 1;
2419         }
2420 #else
2421         if (conf->rxmode.hw_strip_crc) {
2422                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2423                 conf->rxmode.hw_strip_crc = 0;
2424         }
2425 #endif
2426
2427         return 0;
2428 }
2429
2430 static int
2431 igbvf_dev_start(struct rte_eth_dev *dev)
2432 {
2433         struct e1000_hw *hw =
2434                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435         struct e1000_adapter *adapter =
2436                 E1000_DEV_PRIVATE(dev->data->dev_private);
2437         int ret;
2438
2439         PMD_INIT_FUNC_TRACE();
2440
2441         hw->mac.ops.reset_hw(hw);
2442         adapter->stopped = 0;
2443
2444         /* Set all vfta */
2445         igbvf_set_vfta_all(dev,1);
2446
2447         eth_igbvf_tx_init(dev);
2448
2449         /* This can fail when allocating mbufs for descriptor rings */
2450         ret = eth_igbvf_rx_init(dev);
2451         if (ret) {
2452                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2453                 igb_dev_clear_queues(dev);
2454                 return ret;
2455         }
2456
2457         return 0;
2458 }
2459
2460 static void
2461 igbvf_dev_stop(struct rte_eth_dev *dev)
2462 {
2463         PMD_INIT_FUNC_TRACE();
2464
2465         igbvf_stop_adapter(dev);
2466
2467         /*
2468           * Clear what we set, but we still keep shadow_vfta to
2469           * restore after device starts
2470           */
2471         igbvf_set_vfta_all(dev,0);
2472
2473         igb_dev_clear_queues(dev);
2474 }
2475
2476 static void
2477 igbvf_dev_close(struct rte_eth_dev *dev)
2478 {
2479         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2480         struct e1000_adapter *adapter =
2481                 E1000_DEV_PRIVATE(dev->data->dev_private);
2482
2483         PMD_INIT_FUNC_TRACE();
2484
2485         e1000_reset_hw(hw);
2486
2487         igbvf_dev_stop(dev);
2488         adapter->stopped = 1;
2489         igb_dev_free_queues(dev);
2490 }
2491
2492 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2493 {
2494         struct e1000_mbx_info *mbx = &hw->mbx;
2495         uint32_t msgbuf[2];
2496
2497         /* After set vlan, vlan strip will also be enabled in igb driver*/
2498         msgbuf[0] = E1000_VF_SET_VLAN;
2499         msgbuf[1] = vid;
2500         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2501         if (on)
2502                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2503
2504         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2505 }
2506
2507 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2508 {
2509         struct e1000_hw *hw =
2510                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2511         struct e1000_vfta * shadow_vfta =
2512                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2513         int i = 0, j = 0, vfta = 0, mask = 1;
2514
2515         for (i = 0; i < IGB_VFTA_SIZE; i++){
2516                 vfta = shadow_vfta->vfta[i];
2517                 if(vfta){
2518                         mask = 1;
2519                         for (j = 0; j < 32; j++){
2520                                 if(vfta & mask)
2521                                         igbvf_set_vfta(hw,
2522                                                 (uint16_t)((i<<5)+j), on);
2523                                 mask<<=1;
2524                         }
2525                 }
2526         }
2527
2528 }
2529
2530 static int
2531 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2532 {
2533         struct e1000_hw *hw =
2534                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2535         struct e1000_vfta * shadow_vfta =
2536                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2537         uint32_t vid_idx = 0;
2538         uint32_t vid_bit = 0;
2539         int ret = 0;
2540
2541         PMD_INIT_FUNC_TRACE();
2542
2543         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2544         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2545         if(ret){
2546                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2547                 return ret;
2548         }
2549         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2550         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2551
2552         /*Save what we set and retore it after device reset*/
2553         if (on)
2554                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2555         else
2556                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2557
2558         return 0;
2559 }
2560
2561 static void
2562 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
2563 {
2564         struct e1000_hw *hw =
2565                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2566
2567         /* index is not used by rar_set() */
2568         hw->mac.ops.rar_set(hw, (void *)addr, 0);
2569 }
2570
2571
2572 static int
2573 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2574                         struct rte_eth_rss_reta_entry64 *reta_conf,
2575                         uint16_t reta_size)
2576 {
2577         uint8_t i, j, mask;
2578         uint32_t reta, r;
2579         uint16_t idx, shift;
2580         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2581
2582         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2583                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2584                         "(%d) doesn't match the number hardware can supported "
2585                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2586                 return -EINVAL;
2587         }
2588
2589         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2590                 idx = i / RTE_RETA_GROUP_SIZE;
2591                 shift = i % RTE_RETA_GROUP_SIZE;
2592                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2593                                                 IGB_4_BIT_MASK);
2594                 if (!mask)
2595                         continue;
2596                 if (mask == IGB_4_BIT_MASK)
2597                         r = 0;
2598                 else
2599                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2600                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2601                         if (mask & (0x1 << j))
2602                                 reta |= reta_conf[idx].reta[shift + j] <<
2603                                                         (CHAR_BIT * j);
2604                         else
2605                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2606                 }
2607                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2608         }
2609
2610         return 0;
2611 }
2612
2613 static int
2614 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2615                        struct rte_eth_rss_reta_entry64 *reta_conf,
2616                        uint16_t reta_size)
2617 {
2618         uint8_t i, j, mask;
2619         uint32_t reta;
2620         uint16_t idx, shift;
2621         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2622
2623         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2624                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2625                         "(%d) doesn't match the number hardware can supported "
2626                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2627                 return -EINVAL;
2628         }
2629
2630         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2631                 idx = i / RTE_RETA_GROUP_SIZE;
2632                 shift = i % RTE_RETA_GROUP_SIZE;
2633                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2634                                                 IGB_4_BIT_MASK);
2635                 if (!mask)
2636                         continue;
2637                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2638                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2639                         if (mask & (0x1 << j))
2640                                 reta_conf[idx].reta[shift + j] =
2641                                         ((reta >> (CHAR_BIT * j)) &
2642                                                 IGB_8_BIT_MASK);
2643                 }
2644         }
2645
2646         return 0;
2647 }
2648
2649 #define MAC_TYPE_FILTER_SUP(type)    do {\
2650         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2651                 (type) != e1000_82576)\
2652                 return -ENOTSUP;\
2653 } while (0)
2654
2655 static int
2656 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2657                         struct rte_eth_syn_filter *filter,
2658                         bool add)
2659 {
2660         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2661         uint32_t synqf, rfctl;
2662
2663         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2664                 return -EINVAL;
2665
2666         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2667
2668         if (add) {
2669                 if (synqf & E1000_SYN_FILTER_ENABLE)
2670                         return -EINVAL;
2671
2672                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2673                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2674
2675                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2676                 if (filter->hig_pri)
2677                         rfctl |= E1000_RFCTL_SYNQFP;
2678                 else
2679                         rfctl &= ~E1000_RFCTL_SYNQFP;
2680
2681                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2682         } else {
2683                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
2684                         return -ENOENT;
2685                 synqf = 0;
2686         }
2687
2688         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2689         E1000_WRITE_FLUSH(hw);
2690         return 0;
2691 }
2692
2693 static int
2694 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
2695                         struct rte_eth_syn_filter *filter)
2696 {
2697         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2698         uint32_t synqf, rfctl;
2699
2700         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2701         if (synqf & E1000_SYN_FILTER_ENABLE) {
2702                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2703                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2704                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2705                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2706                 return 0;
2707         }
2708
2709         return -ENOENT;
2710 }
2711
2712 static int
2713 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
2714                         enum rte_filter_op filter_op,
2715                         void *arg)
2716 {
2717         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2718         int ret;
2719
2720         MAC_TYPE_FILTER_SUP(hw->mac.type);
2721
2722         if (filter_op == RTE_ETH_FILTER_NOP)
2723                 return 0;
2724
2725         if (arg == NULL) {
2726                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2727                             filter_op);
2728                 return -EINVAL;
2729         }
2730
2731         switch (filter_op) {
2732         case RTE_ETH_FILTER_ADD:
2733                 ret = eth_igb_syn_filter_set(dev,
2734                                 (struct rte_eth_syn_filter *)arg,
2735                                 TRUE);
2736                 break;
2737         case RTE_ETH_FILTER_DELETE:
2738                 ret = eth_igb_syn_filter_set(dev,
2739                                 (struct rte_eth_syn_filter *)arg,
2740                                 FALSE);
2741                 break;
2742         case RTE_ETH_FILTER_GET:
2743                 ret = eth_igb_syn_filter_get(dev,
2744                                 (struct rte_eth_syn_filter *)arg);
2745                 break;
2746         default:
2747                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
2748                 ret = -EINVAL;
2749                 break;
2750         }
2751
2752         return ret;
2753 }
2754
2755 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
2756         if ((type) != e1000_82580 && (type) != e1000_i350)\
2757                 return -ENOSYS; \
2758 } while (0)
2759
2760 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
2761 static inline int
2762 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
2763                         struct e1000_2tuple_filter_info *filter_info)
2764 {
2765         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2766                 return -EINVAL;
2767         if (filter->priority > E1000_2TUPLE_MAX_PRI)
2768                 return -EINVAL;  /* filter index is out of range. */
2769         if (filter->tcp_flags > TCP_FLAG_ALL)
2770                 return -EINVAL;  /* flags is invalid. */
2771
2772         switch (filter->dst_port_mask) {
2773         case UINT16_MAX:
2774                 filter_info->dst_port_mask = 0;
2775                 filter_info->dst_port = filter->dst_port;
2776                 break;
2777         case 0:
2778                 filter_info->dst_port_mask = 1;
2779                 break;
2780         default:
2781                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2782                 return -EINVAL;
2783         }
2784
2785         switch (filter->proto_mask) {
2786         case UINT8_MAX:
2787                 filter_info->proto_mask = 0;
2788                 filter_info->proto = filter->proto;
2789                 break;
2790         case 0:
2791                 filter_info->proto_mask = 1;
2792                 break;
2793         default:
2794                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2795                 return -EINVAL;
2796         }
2797
2798         filter_info->priority = (uint8_t)filter->priority;
2799         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
2800                 filter_info->tcp_flags = filter->tcp_flags;
2801         else
2802                 filter_info->tcp_flags = 0;
2803
2804         return 0;
2805 }
2806
2807 static inline struct e1000_2tuple_filter *
2808 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
2809                         struct e1000_2tuple_filter_info *key)
2810 {
2811         struct e1000_2tuple_filter *it;
2812
2813         TAILQ_FOREACH(it, filter_list, entries) {
2814                 if (memcmp(key, &it->filter_info,
2815                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
2816                         return it;
2817                 }
2818         }
2819         return NULL;
2820 }
2821
2822 /*
2823  * igb_add_2tuple_filter - add a 2tuple filter
2824  *
2825  * @param
2826  * dev: Pointer to struct rte_eth_dev.
2827  * ntuple_filter: ponter to the filter that will be added.
2828  *
2829  * @return
2830  *    - On success, zero.
2831  *    - On failure, a negative value.
2832  */
2833 static int
2834 igb_add_2tuple_filter(struct rte_eth_dev *dev,
2835                         struct rte_eth_ntuple_filter *ntuple_filter)
2836 {
2837         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2838         struct e1000_filter_info *filter_info =
2839                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2840         struct e1000_2tuple_filter *filter;
2841         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
2842         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
2843         int i, ret;
2844
2845         filter = rte_zmalloc("e1000_2tuple_filter",
2846                         sizeof(struct e1000_2tuple_filter), 0);
2847         if (filter == NULL)
2848                 return -ENOMEM;
2849
2850         ret = ntuple_filter_to_2tuple(ntuple_filter,
2851                                       &filter->filter_info);
2852         if (ret < 0) {
2853                 rte_free(filter);
2854                 return ret;
2855         }
2856         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2857                                          &filter->filter_info) != NULL) {
2858                 PMD_DRV_LOG(ERR, "filter exists.");
2859                 rte_free(filter);
2860                 return -EEXIST;
2861         }
2862         filter->queue = ntuple_filter->queue;
2863
2864         /*
2865          * look for an unused 2tuple filter index,
2866          * and insert the filter to list.
2867          */
2868         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
2869                 if (!(filter_info->twotuple_mask & (1 << i))) {
2870                         filter_info->twotuple_mask |= 1 << i;
2871                         filter->index = i;
2872                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
2873                                           filter,
2874                                           entries);
2875                         break;
2876                 }
2877         }
2878         if (i >= E1000_MAX_TTQF_FILTERS) {
2879                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
2880                 rte_free(filter);
2881                 return -ENOSYS;
2882         }
2883
2884         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
2885         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
2886                 imir |= E1000_IMIR_PORT_BP;
2887         else
2888                 imir &= ~E1000_IMIR_PORT_BP;
2889
2890         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
2891
2892         ttqf |= E1000_TTQF_QUEUE_ENABLE;
2893         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
2894         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
2895         if (filter->filter_info.proto_mask == 0)
2896                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2897
2898         /* tcp flags bits setting. */
2899         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
2900                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
2901                         imir_ext |= E1000_IMIREXT_CTRL_URG;
2902                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
2903                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
2904                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
2905                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
2906                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
2907                         imir_ext |= E1000_IMIREXT_CTRL_RST;
2908                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
2909                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
2910                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
2911                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
2912         } else
2913                 imir_ext |= E1000_IMIREXT_CTRL_BP;
2914         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
2915         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
2916         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
2917         return 0;
2918 }
2919
2920 /*
2921  * igb_remove_2tuple_filter - remove a 2tuple filter
2922  *
2923  * @param
2924  * dev: Pointer to struct rte_eth_dev.
2925  * ntuple_filter: ponter to the filter that will be removed.
2926  *
2927  * @return
2928  *    - On success, zero.
2929  *    - On failure, a negative value.
2930  */
2931 static int
2932 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2933                         struct rte_eth_ntuple_filter *ntuple_filter)
2934 {
2935         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2936         struct e1000_filter_info *filter_info =
2937                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2938         struct e1000_2tuple_filter_info filter_2tuple;
2939         struct e1000_2tuple_filter *filter;
2940         int ret;
2941
2942         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
2943         ret = ntuple_filter_to_2tuple(ntuple_filter,
2944                                       &filter_2tuple);
2945         if (ret < 0)
2946                 return ret;
2947
2948         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2949                                          &filter_2tuple);
2950         if (filter == NULL) {
2951                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2952                 return -ENOENT;
2953         }
2954
2955         filter_info->twotuple_mask &= ~(1 << filter->index);
2956         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
2957         rte_free(filter);
2958
2959         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
2960         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
2961         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
2962         return 0;
2963 }
2964
2965 static inline struct e1000_flex_filter *
2966 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
2967                         struct e1000_flex_filter_info *key)
2968 {
2969         struct e1000_flex_filter *it;
2970
2971         TAILQ_FOREACH(it, filter_list, entries) {
2972                 if (memcmp(key, &it->filter_info,
2973                         sizeof(struct e1000_flex_filter_info)) == 0)
2974                         return it;
2975         }
2976
2977         return NULL;
2978 }
2979
2980 static int
2981 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
2982                         struct rte_eth_flex_filter *filter,
2983                         bool add)
2984 {
2985         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2986         struct e1000_filter_info *filter_info =
2987                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2988         struct e1000_flex_filter *flex_filter, *it;
2989         uint32_t wufc, queueing, mask;
2990         uint32_t reg_off;
2991         uint8_t shift, i, j = 0;
2992
2993         flex_filter = rte_zmalloc("e1000_flex_filter",
2994                         sizeof(struct e1000_flex_filter), 0);
2995         if (flex_filter == NULL)
2996                 return -ENOMEM;
2997
2998         flex_filter->filter_info.len = filter->len;
2999         flex_filter->filter_info.priority = filter->priority;
3000         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3001         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3002                 mask = 0;
3003                 /* reverse bits in flex filter's mask*/
3004                 for (shift = 0; shift < CHAR_BIT; shift++) {
3005                         if (filter->mask[i] & (0x01 << shift))
3006                                 mask |= (0x80 >> shift);
3007                 }
3008                 flex_filter->filter_info.mask[i] = mask;
3009         }
3010
3011         wufc = E1000_READ_REG(hw, E1000_WUFC);
3012         if (flex_filter->index < E1000_MAX_FHFT)
3013                 reg_off = E1000_FHFT(flex_filter->index);
3014         else
3015                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3016
3017         if (add) {
3018                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3019                                 &flex_filter->filter_info) != NULL) {
3020                         PMD_DRV_LOG(ERR, "filter exists.");
3021                         rte_free(flex_filter);
3022                         return -EEXIST;
3023                 }
3024                 flex_filter->queue = filter->queue;
3025                 /*
3026                  * look for an unused flex filter index
3027                  * and insert the filter into the list.
3028                  */
3029                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3030                         if (!(filter_info->flex_mask & (1 << i))) {
3031                                 filter_info->flex_mask |= 1 << i;
3032                                 flex_filter->index = i;
3033                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3034                                         flex_filter,
3035                                         entries);
3036                                 break;
3037                         }
3038                 }
3039                 if (i >= E1000_MAX_FLEX_FILTERS) {
3040                         PMD_DRV_LOG(ERR, "flex filters are full.");
3041                         rte_free(flex_filter);
3042                         return -ENOSYS;
3043                 }
3044
3045                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3046                                 (E1000_WUFC_FLX0 << flex_filter->index));
3047                 queueing = filter->len |
3048                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3049                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3050                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3051                                 queueing);
3052                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3053                         E1000_WRITE_REG(hw, reg_off,
3054                                         flex_filter->filter_info.dwords[j]);
3055                         reg_off += sizeof(uint32_t);
3056                         E1000_WRITE_REG(hw, reg_off,
3057                                         flex_filter->filter_info.dwords[++j]);
3058                         reg_off += sizeof(uint32_t);
3059                         E1000_WRITE_REG(hw, reg_off,
3060                                 (uint32_t)flex_filter->filter_info.mask[i]);
3061                         reg_off += sizeof(uint32_t) * 2;
3062                         ++j;
3063                 }
3064         } else {
3065                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3066                                 &flex_filter->filter_info);
3067                 if (it == NULL) {
3068                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3069                         rte_free(flex_filter);
3070                         return -ENOENT;
3071                 }
3072
3073                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3074                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3075                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3076                         (~(E1000_WUFC_FLX0 << it->index)));
3077
3078                 filter_info->flex_mask &= ~(1 << it->index);
3079                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3080                 rte_free(it);
3081                 rte_free(flex_filter);
3082         }
3083
3084         return 0;
3085 }
3086
3087 static int
3088 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3089                         struct rte_eth_flex_filter *filter)
3090 {
3091         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3092         struct e1000_filter_info *filter_info =
3093                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3094         struct e1000_flex_filter flex_filter, *it;
3095         uint32_t wufc, queueing, wufc_en = 0;
3096
3097         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3098         flex_filter.filter_info.len = filter->len;
3099         flex_filter.filter_info.priority = filter->priority;
3100         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3101         memcpy(flex_filter.filter_info.mask, filter->mask,
3102                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3103
3104         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3105                                 &flex_filter.filter_info);
3106         if (it == NULL) {
3107                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3108                 return -ENOENT;
3109         }
3110
3111         wufc = E1000_READ_REG(hw, E1000_WUFC);
3112         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3113
3114         if ((wufc & wufc_en) == wufc_en) {
3115                 uint32_t reg_off = 0;
3116                 if (it->index < E1000_MAX_FHFT)
3117                         reg_off = E1000_FHFT(it->index);
3118                 else
3119                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3120
3121                 queueing = E1000_READ_REG(hw,
3122                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3123                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3124                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3125                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3126                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3127                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3128                 return 0;
3129         }
3130         return -ENOENT;
3131 }
3132
3133 static int
3134 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3135                         enum rte_filter_op filter_op,
3136                         void *arg)
3137 {
3138         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3139         struct rte_eth_flex_filter *filter;
3140         int ret = 0;
3141
3142         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3143
3144         if (filter_op == RTE_ETH_FILTER_NOP)
3145                 return ret;
3146
3147         if (arg == NULL) {
3148                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3149                             filter_op);
3150                 return -EINVAL;
3151         }
3152
3153         filter = (struct rte_eth_flex_filter *)arg;
3154         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3155             || filter->len % sizeof(uint64_t) != 0) {
3156                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3157                 return -EINVAL;
3158         }
3159         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3160                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3161                 return -EINVAL;
3162         }
3163
3164         switch (filter_op) {
3165         case RTE_ETH_FILTER_ADD:
3166                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3167                 break;
3168         case RTE_ETH_FILTER_DELETE:
3169                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3170                 break;
3171         case RTE_ETH_FILTER_GET:
3172                 ret = eth_igb_get_flex_filter(dev, filter);
3173                 break;
3174         default:
3175                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3176                 ret = -EINVAL;
3177                 break;
3178         }
3179
3180         return ret;
3181 }
3182
3183 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3184 static inline int
3185 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3186                         struct e1000_5tuple_filter_info *filter_info)
3187 {
3188         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3189                 return -EINVAL;
3190         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3191                 return -EINVAL;  /* filter index is out of range. */
3192         if (filter->tcp_flags > TCP_FLAG_ALL)
3193                 return -EINVAL;  /* flags is invalid. */
3194
3195         switch (filter->dst_ip_mask) {
3196         case UINT32_MAX:
3197                 filter_info->dst_ip_mask = 0;
3198                 filter_info->dst_ip = filter->dst_ip;
3199                 break;
3200         case 0:
3201                 filter_info->dst_ip_mask = 1;
3202                 break;
3203         default:
3204                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3205                 return -EINVAL;
3206         }
3207
3208         switch (filter->src_ip_mask) {
3209         case UINT32_MAX:
3210                 filter_info->src_ip_mask = 0;
3211                 filter_info->src_ip = filter->src_ip;
3212                 break;
3213         case 0:
3214                 filter_info->src_ip_mask = 1;
3215                 break;
3216         default:
3217                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3218                 return -EINVAL;
3219         }
3220
3221         switch (filter->dst_port_mask) {
3222         case UINT16_MAX:
3223                 filter_info->dst_port_mask = 0;
3224                 filter_info->dst_port = filter->dst_port;
3225                 break;
3226         case 0:
3227                 filter_info->dst_port_mask = 1;
3228                 break;
3229         default:
3230                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3231                 return -EINVAL;
3232         }
3233
3234         switch (filter->src_port_mask) {
3235         case UINT16_MAX:
3236                 filter_info->src_port_mask = 0;
3237                 filter_info->src_port = filter->src_port;
3238                 break;
3239         case 0:
3240                 filter_info->src_port_mask = 1;
3241                 break;
3242         default:
3243                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3244                 return -EINVAL;
3245         }
3246
3247         switch (filter->proto_mask) {
3248         case UINT8_MAX:
3249                 filter_info->proto_mask = 0;
3250                 filter_info->proto = filter->proto;
3251                 break;
3252         case 0:
3253                 filter_info->proto_mask = 1;
3254                 break;
3255         default:
3256                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3257                 return -EINVAL;
3258         }
3259
3260         filter_info->priority = (uint8_t)filter->priority;
3261         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3262                 filter_info->tcp_flags = filter->tcp_flags;
3263         else
3264                 filter_info->tcp_flags = 0;
3265
3266         return 0;
3267 }
3268
3269 static inline struct e1000_5tuple_filter *
3270 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3271                         struct e1000_5tuple_filter_info *key)
3272 {
3273         struct e1000_5tuple_filter *it;
3274
3275         TAILQ_FOREACH(it, filter_list, entries) {
3276                 if (memcmp(key, &it->filter_info,
3277                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3278                         return it;
3279                 }
3280         }
3281         return NULL;
3282 }
3283
3284 /*
3285  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3286  *
3287  * @param
3288  * dev: Pointer to struct rte_eth_dev.
3289  * ntuple_filter: ponter to the filter that will be added.
3290  *
3291  * @return
3292  *    - On success, zero.
3293  *    - On failure, a negative value.
3294  */
3295 static int
3296 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3297                         struct rte_eth_ntuple_filter *ntuple_filter)
3298 {
3299         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300         struct e1000_filter_info *filter_info =
3301                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3302         struct e1000_5tuple_filter *filter;
3303         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3304         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3305         uint8_t i;
3306         int ret;
3307
3308         filter = rte_zmalloc("e1000_5tuple_filter",
3309                         sizeof(struct e1000_5tuple_filter), 0);
3310         if (filter == NULL)
3311                 return -ENOMEM;
3312
3313         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3314                                             &filter->filter_info);
3315         if (ret < 0) {
3316                 rte_free(filter);
3317                 return ret;
3318         }
3319
3320         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3321                                          &filter->filter_info) != NULL) {
3322                 PMD_DRV_LOG(ERR, "filter exists.");
3323                 rte_free(filter);
3324                 return -EEXIST;
3325         }
3326         filter->queue = ntuple_filter->queue;
3327
3328         /*
3329          * look for an unused 5tuple filter index,
3330          * and insert the filter to list.
3331          */
3332         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3333                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3334                         filter_info->fivetuple_mask |= 1 << i;
3335                         filter->index = i;
3336                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3337                                           filter,
3338                                           entries);
3339                         break;
3340                 }
3341         }
3342         if (i >= E1000_MAX_FTQF_FILTERS) {
3343                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3344                 rte_free(filter);
3345                 return -ENOSYS;
3346         }
3347
3348         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3349         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3350                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3351         if (filter->filter_info.dst_ip_mask == 0)
3352                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3353         if (filter->filter_info.src_port_mask == 0)
3354                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3355         if (filter->filter_info.proto_mask == 0)
3356                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3357         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3358                 E1000_FTQF_QUEUE_MASK;
3359         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3360         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3361         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3362         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3363
3364         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3365         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3366
3367         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3368         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3369                 imir |= E1000_IMIR_PORT_BP;
3370         else
3371                 imir &= ~E1000_IMIR_PORT_BP;
3372         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3373
3374         /* tcp flags bits setting. */
3375         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3376                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3377                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3378                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3379                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3380                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3381                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3382                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3383                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3384                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3385                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3386                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3387                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3388         } else
3389                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3390         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3391         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3392         return 0;
3393 }
3394
3395 /*
3396  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3397  *
3398  * @param
3399  * dev: Pointer to struct rte_eth_dev.
3400  * ntuple_filter: ponter to the filter that will be removed.
3401  *
3402  * @return
3403  *    - On success, zero.
3404  *    - On failure, a negative value.
3405  */
3406 static int
3407 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3408                                 struct rte_eth_ntuple_filter *ntuple_filter)
3409 {
3410         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3411         struct e1000_filter_info *filter_info =
3412                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3413         struct e1000_5tuple_filter_info filter_5tuple;
3414         struct e1000_5tuple_filter *filter;
3415         int ret;
3416
3417         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3418         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3419                                             &filter_5tuple);
3420         if (ret < 0)
3421                 return ret;
3422
3423         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3424                                          &filter_5tuple);
3425         if (filter == NULL) {
3426                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3427                 return -ENOENT;
3428         }
3429
3430         filter_info->fivetuple_mask &= ~(1 << filter->index);
3431         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3432         rte_free(filter);
3433
3434         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3435                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3436         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3437         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3438         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3439         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3440         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3441         return 0;
3442 }
3443
3444 static int
3445 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3446 {
3447         uint32_t rctl;
3448         struct e1000_hw *hw;
3449         struct rte_eth_dev_info dev_info;
3450         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3451                                      VLAN_TAG_SIZE);
3452
3453         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3454
3455 #ifdef RTE_LIBRTE_82571_SUPPORT
3456         /* XXX: not bigger than max_rx_pktlen */
3457         if (hw->mac.type == e1000_82571)
3458                 return -ENOTSUP;
3459 #endif
3460         eth_igb_infos_get(dev, &dev_info);
3461
3462         /* check that mtu is within the allowed range */
3463         if ((mtu < ETHER_MIN_MTU) ||
3464             (frame_size > dev_info.max_rx_pktlen))
3465                 return -EINVAL;
3466
3467         /* refuse mtu that requires the support of scattered packets when this
3468          * feature has not been enabled before. */
3469         if (!dev->data->scattered_rx &&
3470             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3471                 return -EINVAL;
3472
3473         rctl = E1000_READ_REG(hw, E1000_RCTL);
3474
3475         /* switch to jumbo mode if needed */
3476         if (frame_size > ETHER_MAX_LEN) {
3477                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3478                 rctl |= E1000_RCTL_LPE;
3479         } else {
3480                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3481                 rctl &= ~E1000_RCTL_LPE;
3482         }
3483         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3484
3485         /* update max frame size */
3486         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3487
3488         E1000_WRITE_REG(hw, E1000_RLPML,
3489                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3490
3491         return 0;
3492 }
3493
3494 /*
3495  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3496  *
3497  * @param
3498  * dev: Pointer to struct rte_eth_dev.
3499  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3500  * add: if true, add filter, if false, remove filter
3501  *
3502  * @return
3503  *    - On success, zero.
3504  *    - On failure, a negative value.
3505  */
3506 static int
3507 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3508                         struct rte_eth_ntuple_filter *ntuple_filter,
3509                         bool add)
3510 {
3511         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3512         int ret;
3513
3514         switch (ntuple_filter->flags) {
3515         case RTE_5TUPLE_FLAGS:
3516         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3517                 if (hw->mac.type != e1000_82576)
3518                         return -ENOTSUP;
3519                 if (add)
3520                         ret = igb_add_5tuple_filter_82576(dev,
3521                                                           ntuple_filter);
3522                 else
3523                         ret = igb_remove_5tuple_filter_82576(dev,
3524                                                              ntuple_filter);
3525                 break;
3526         case RTE_2TUPLE_FLAGS:
3527         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3528                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3529                         return -ENOTSUP;
3530                 if (add)
3531                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3532                 else
3533                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3534                 break;
3535         default:
3536                 ret = -EINVAL;
3537                 break;
3538         }
3539
3540         return ret;
3541 }
3542
3543 /*
3544  * igb_get_ntuple_filter - get a ntuple filter
3545  *
3546  * @param
3547  * dev: Pointer to struct rte_eth_dev.
3548  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3549  *
3550  * @return
3551  *    - On success, zero.
3552  *    - On failure, a negative value.
3553  */
3554 static int
3555 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3556                         struct rte_eth_ntuple_filter *ntuple_filter)
3557 {
3558         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3559         struct e1000_filter_info *filter_info =
3560                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3561         struct e1000_5tuple_filter_info filter_5tuple;
3562         struct e1000_2tuple_filter_info filter_2tuple;
3563         struct e1000_5tuple_filter *p_5tuple_filter;
3564         struct e1000_2tuple_filter *p_2tuple_filter;
3565         int ret;
3566
3567         switch (ntuple_filter->flags) {
3568         case RTE_5TUPLE_FLAGS:
3569         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3570                 if (hw->mac.type != e1000_82576)
3571                         return -ENOTSUP;
3572                 memset(&filter_5tuple,
3573                         0,
3574                         sizeof(struct e1000_5tuple_filter_info));
3575                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3576                                                     &filter_5tuple);
3577                 if (ret < 0)
3578                         return ret;
3579                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3580                                         &filter_info->fivetuple_list,
3581                                         &filter_5tuple);
3582                 if (p_5tuple_filter == NULL) {
3583                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3584                         return -ENOENT;
3585                 }
3586                 ntuple_filter->queue = p_5tuple_filter->queue;
3587                 break;
3588         case RTE_2TUPLE_FLAGS:
3589         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3590                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3591                         return -ENOTSUP;
3592                 memset(&filter_2tuple,
3593                         0,
3594                         sizeof(struct e1000_2tuple_filter_info));
3595                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3596                 if (ret < 0)
3597                         return ret;
3598                 p_2tuple_filter = igb_2tuple_filter_lookup(
3599                                         &filter_info->twotuple_list,
3600                                         &filter_2tuple);
3601                 if (p_2tuple_filter == NULL) {
3602                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3603                         return -ENOENT;
3604                 }
3605                 ntuple_filter->queue = p_2tuple_filter->queue;
3606                 break;
3607         default:
3608                 ret = -EINVAL;
3609                 break;
3610         }
3611
3612         return 0;
3613 }
3614
3615 /*
3616  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3617  * @dev: pointer to rte_eth_dev structure
3618  * @filter_op:operation will be taken.
3619  * @arg: a pointer to specific structure corresponding to the filter_op
3620  */
3621 static int
3622 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3623                                 enum rte_filter_op filter_op,
3624                                 void *arg)
3625 {
3626         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3627         int ret;
3628
3629         MAC_TYPE_FILTER_SUP(hw->mac.type);
3630
3631         if (filter_op == RTE_ETH_FILTER_NOP)
3632                 return 0;
3633
3634         if (arg == NULL) {
3635                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3636                             filter_op);
3637                 return -EINVAL;
3638         }
3639
3640         switch (filter_op) {
3641         case RTE_ETH_FILTER_ADD:
3642                 ret = igb_add_del_ntuple_filter(dev,
3643                         (struct rte_eth_ntuple_filter *)arg,
3644                         TRUE);
3645                 break;
3646         case RTE_ETH_FILTER_DELETE:
3647                 ret = igb_add_del_ntuple_filter(dev,
3648                         (struct rte_eth_ntuple_filter *)arg,
3649                         FALSE);
3650                 break;
3651         case RTE_ETH_FILTER_GET:
3652                 ret = igb_get_ntuple_filter(dev,
3653                         (struct rte_eth_ntuple_filter *)arg);
3654                 break;
3655         default:
3656                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3657                 ret = -EINVAL;
3658                 break;
3659         }
3660         return ret;
3661 }
3662
3663 static inline int
3664 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3665                         uint16_t ethertype)
3666 {
3667         int i;
3668
3669         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3670                 if (filter_info->ethertype_filters[i] == ethertype &&
3671                     (filter_info->ethertype_mask & (1 << i)))
3672                         return i;
3673         }
3674         return -1;
3675 }
3676
3677 static inline int
3678 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3679                         uint16_t ethertype)
3680 {
3681         int i;
3682
3683         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3684                 if (!(filter_info->ethertype_mask & (1 << i))) {
3685                         filter_info->ethertype_mask |= 1 << i;
3686                         filter_info->ethertype_filters[i] = ethertype;
3687                         return i;
3688                 }
3689         }
3690         return -1;
3691 }
3692
3693 static inline int
3694 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3695                         uint8_t idx)
3696 {
3697         if (idx >= E1000_MAX_ETQF_FILTERS)
3698                 return -1;
3699         filter_info->ethertype_mask &= ~(1 << idx);
3700         filter_info->ethertype_filters[idx] = 0;
3701         return idx;
3702 }
3703
3704
3705 static int
3706 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
3707                         struct rte_eth_ethertype_filter *filter,
3708                         bool add)
3709 {
3710         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3711         struct e1000_filter_info *filter_info =
3712                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3713         uint32_t etqf = 0;
3714         int ret;
3715
3716         if (filter->ether_type == ETHER_TYPE_IPv4 ||
3717                 filter->ether_type == ETHER_TYPE_IPv6) {
3718                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3719                         " ethertype filter.", filter->ether_type);
3720                 return -EINVAL;
3721         }
3722
3723         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3724                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3725                 return -EINVAL;
3726         }
3727         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3728                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3729                 return -EINVAL;
3730         }
3731
3732         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3733         if (ret >= 0 && add) {
3734                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3735                             filter->ether_type);
3736                 return -EEXIST;
3737         }
3738         if (ret < 0 && !add) {
3739                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3740                             filter->ether_type);
3741                 return -ENOENT;
3742         }
3743
3744         if (add) {
3745                 ret = igb_ethertype_filter_insert(filter_info,
3746                         filter->ether_type);
3747                 if (ret < 0) {
3748                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
3749                         return -ENOSYS;
3750                 }
3751
3752                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
3753                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
3754                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
3755         } else {
3756                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
3757                 if (ret < 0)
3758                         return -ENOSYS;
3759         }
3760         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
3761         E1000_WRITE_FLUSH(hw);
3762
3763         return 0;
3764 }
3765
3766 static int
3767 igb_get_ethertype_filter(struct rte_eth_dev *dev,
3768                         struct rte_eth_ethertype_filter *filter)
3769 {
3770         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3771         struct e1000_filter_info *filter_info =
3772                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3773         uint32_t etqf;
3774         int ret;
3775
3776         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3777         if (ret < 0) {
3778                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3779                             filter->ether_type);
3780                 return -ENOENT;
3781         }
3782
3783         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
3784         if (etqf & E1000_ETQF_FILTER_ENABLE) {
3785                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
3786                 filter->flags = 0;
3787                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
3788                                 E1000_ETQF_QUEUE_SHIFT;
3789                 return 0;
3790         }
3791
3792         return -ENOENT;
3793 }
3794
3795 /*
3796  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
3797  * @dev: pointer to rte_eth_dev structure
3798  * @filter_op:operation will be taken.
3799  * @arg: a pointer to specific structure corresponding to the filter_op
3800  */
3801 static int
3802 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
3803                                 enum rte_filter_op filter_op,
3804                                 void *arg)
3805 {
3806         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3807         int ret;
3808
3809         MAC_TYPE_FILTER_SUP(hw->mac.type);
3810
3811         if (filter_op == RTE_ETH_FILTER_NOP)
3812                 return 0;
3813
3814         if (arg == NULL) {
3815                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3816                             filter_op);
3817                 return -EINVAL;
3818         }
3819
3820         switch (filter_op) {
3821         case RTE_ETH_FILTER_ADD:
3822                 ret = igb_add_del_ethertype_filter(dev,
3823                         (struct rte_eth_ethertype_filter *)arg,
3824                         TRUE);
3825                 break;
3826         case RTE_ETH_FILTER_DELETE:
3827                 ret = igb_add_del_ethertype_filter(dev,
3828                         (struct rte_eth_ethertype_filter *)arg,
3829                         FALSE);
3830                 break;
3831         case RTE_ETH_FILTER_GET:
3832                 ret = igb_get_ethertype_filter(dev,
3833                         (struct rte_eth_ethertype_filter *)arg);
3834                 break;
3835         default:
3836                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3837                 ret = -EINVAL;
3838                 break;
3839         }
3840         return ret;
3841 }
3842
3843 static int
3844 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
3845                      enum rte_filter_type filter_type,
3846                      enum rte_filter_op filter_op,
3847                      void *arg)
3848 {
3849         int ret = -EINVAL;
3850
3851         switch (filter_type) {
3852         case RTE_ETH_FILTER_NTUPLE:
3853                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
3854                 break;
3855         case RTE_ETH_FILTER_ETHERTYPE:
3856                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
3857                 break;
3858         case RTE_ETH_FILTER_SYN:
3859                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
3860                 break;
3861         case RTE_ETH_FILTER_FLEXIBLE:
3862                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
3863                 break;
3864         default:
3865                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3866                                                         filter_type);
3867                 break;
3868         }
3869
3870         return ret;
3871 }
3872
3873 static int
3874 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
3875                          struct ether_addr *mc_addr_set,
3876                          uint32_t nb_mc_addr)
3877 {
3878         struct e1000_hw *hw;
3879
3880         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3881         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
3882         return 0;
3883 }
3884
3885 static int
3886 igb_timesync_enable(struct rte_eth_dev *dev)
3887 {
3888         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3889         uint32_t tsync_ctl;
3890         uint32_t tsauxc;
3891
3892         /* Enable system time for it isn't on by default. */
3893         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
3894         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
3895         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
3896
3897         /* Start incrementing the register used to timestamp PTP packets. */
3898         E1000_WRITE_REG(hw, E1000_TIMINCA, E1000_TIMINCA_INIT);
3899
3900         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
3901         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
3902                         (ETHER_TYPE_1588 |
3903                          E1000_ETQF_FILTER_ENABLE |
3904                          E1000_ETQF_1588));
3905
3906         /* Enable timestamping of received PTP packets. */
3907         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
3908         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
3909         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
3910
3911         /* Enable Timestamping of transmitted PTP packets. */
3912         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
3913         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
3914         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
3915
3916         return 0;
3917 }
3918
3919 static int
3920 igb_timesync_disable(struct rte_eth_dev *dev)
3921 {
3922         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3923         uint32_t tsync_ctl;
3924
3925         /* Disable timestamping of transmitted PTP packets. */
3926         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
3927         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
3928         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
3929
3930         /* Disable timestamping of received PTP packets. */
3931         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
3932         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
3933         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
3934
3935         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
3936         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
3937
3938         /* Stop incrementating the System Time registers. */
3939         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
3940
3941         return 0;
3942 }
3943
3944 static int
3945 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3946                                struct timespec *timestamp,
3947                                uint32_t flags __rte_unused)
3948 {
3949         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3950         uint32_t tsync_rxctl;
3951         uint32_t rx_stmpl;
3952         uint32_t rx_stmph;
3953
3954         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
3955         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
3956                 return -EINVAL;
3957
3958         rx_stmpl = E1000_READ_REG(hw, E1000_RXSTMPL);
3959         rx_stmph = E1000_READ_REG(hw, E1000_RXSTMPH);
3960
3961         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
3962         timestamp->tv_nsec = 0;
3963
3964         return  0;
3965 }
3966
3967 static int
3968 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3969                                struct timespec *timestamp)
3970 {
3971         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3972         uint32_t tsync_txctl;
3973         uint32_t tx_stmpl;
3974         uint32_t tx_stmph;
3975
3976         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
3977         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
3978                 return -EINVAL;
3979
3980         tx_stmpl = E1000_READ_REG(hw, E1000_TXSTMPL);
3981         tx_stmph = E1000_READ_REG(hw, E1000_TXSTMPH);
3982
3983         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
3984         timestamp->tv_nsec = 0;
3985
3986         return  0;
3987 }
3988
3989 static int
3990 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
3991 {
3992         int count = 0;
3993         int g_ind = 0;
3994         const struct reg_info *reg_group;
3995
3996         while ((reg_group = igb_regs[g_ind++]))
3997                 count += igb_reg_group_count(reg_group);
3998
3999         return count;
4000 }
4001
4002 static int
4003 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4004 {
4005         int count = 0;
4006         int g_ind = 0;
4007         const struct reg_info *reg_group;
4008
4009         while ((reg_group = igbvf_regs[g_ind++]))
4010                 count += igb_reg_group_count(reg_group);
4011
4012         return count;
4013 }
4014
4015 static int
4016 eth_igb_get_regs(struct rte_eth_dev *dev,
4017         struct rte_dev_reg_info *regs)
4018 {
4019         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4020         uint32_t *data = regs->data;
4021         int g_ind = 0;
4022         int count = 0;
4023         const struct reg_info *reg_group;
4024
4025         /* Support only full register dump */
4026         if ((regs->length == 0) ||
4027             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4028                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4029                         hw->device_id;
4030                 while ((reg_group = igb_regs[g_ind++]))
4031                         count += igb_read_regs_group(dev, &data[count],
4032                                                         reg_group);
4033                 return 0;
4034         }
4035
4036         return -ENOTSUP;
4037 }
4038
4039 static int
4040 igbvf_get_regs(struct rte_eth_dev *dev,
4041         struct rte_dev_reg_info *regs)
4042 {
4043         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4044         uint32_t *data = regs->data;
4045         int g_ind = 0;
4046         int count = 0;
4047         const struct reg_info *reg_group;
4048
4049         /* Support only full register dump */
4050         if ((regs->length == 0) ||
4051             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4052                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4053                         hw->device_id;
4054                 while ((reg_group = igbvf_regs[g_ind++]))
4055                         count += igb_read_regs_group(dev, &data[count],
4056                                                         reg_group);
4057                 return 0;
4058         }
4059
4060         return -ENOTSUP;
4061 }
4062
4063 static int
4064 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4065 {
4066         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4067
4068         /* Return unit is byte count */
4069         return hw->nvm.word_size * 2;
4070 }
4071
4072 static int
4073 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4074         struct rte_dev_eeprom_info *in_eeprom)
4075 {
4076         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4077         struct e1000_nvm_info *nvm = &hw->nvm;
4078         uint16_t *data = in_eeprom->data;
4079         int first, length;
4080
4081         first = in_eeprom->offset >> 1;
4082         length = in_eeprom->length >> 1;
4083         if ((first >= hw->nvm.word_size) ||
4084             ((first + length) >= hw->nvm.word_size))
4085                 return -EINVAL;
4086
4087         in_eeprom->magic = hw->vendor_id |
4088                 ((uint32_t)hw->device_id << 16);
4089
4090         if ((nvm->ops.read) == NULL)
4091                 return -ENOTSUP;
4092
4093         return nvm->ops.read(hw, first, length, data);
4094 }
4095
4096 static int
4097 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4098         struct rte_dev_eeprom_info *in_eeprom)
4099 {
4100         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4101         struct e1000_nvm_info *nvm = &hw->nvm;
4102         uint16_t *data = in_eeprom->data;
4103         int first, length;
4104
4105         first = in_eeprom->offset >> 1;
4106         length = in_eeprom->length >> 1;
4107         if ((first >= hw->nvm.word_size) ||
4108             ((first + length) >= hw->nvm.word_size))
4109                 return -EINVAL;
4110
4111         in_eeprom->magic = (uint32_t)hw->vendor_id |
4112                 ((uint32_t)hw->device_id << 16);
4113
4114         if ((nvm->ops.write) == NULL)
4115                 return -ENOTSUP;
4116         return nvm->ops.write(hw,  first, length, data);
4117 }
4118
4119 static struct rte_driver pmd_igb_drv = {
4120         .type = PMD_PDEV,
4121         .init = rte_igb_pmd_init,
4122 };
4123
4124 static struct rte_driver pmd_igbvf_drv = {
4125         .type = PMD_PDEV,
4126         .init = rte_igbvf_pmd_init,
4127 };
4128
4129 static int
4130 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4131 {
4132         struct e1000_hw *hw =
4133                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4134         uint32_t mask = 1 << queue_id;
4135
4136         E1000_WRITE_REG(hw, E1000_EIMC, mask);
4137         E1000_WRITE_FLUSH(hw);
4138
4139         return 0;
4140 }
4141
4142 static int
4143 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4144 {
4145         struct e1000_hw *hw =
4146                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4147         uint32_t mask = 1 << queue_id;
4148         uint32_t regval;
4149
4150         regval = E1000_READ_REG(hw, E1000_EIMS);
4151         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4152         E1000_WRITE_FLUSH(hw);
4153
4154         rte_intr_enable(&dev->pci_dev->intr_handle);
4155
4156         return 0;
4157 }
4158
4159 static void
4160 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
4161                    uint8_t index, uint8_t offset)
4162 {
4163         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4164
4165         /* clear bits */
4166         val &= ~((uint32_t)0xFF << offset);
4167
4168         /* write vector and valid bit */
4169         val |= (msix_vector | E1000_IVAR_VALID) << offset;
4170
4171         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4172 }
4173
4174 static void
4175 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4176                            uint8_t queue, uint8_t msix_vector)
4177 {
4178         uint32_t tmp = 0;
4179
4180         if (hw->mac.type == e1000_82575) {
4181                 if (direction == 0)
4182                         tmp = E1000_EICR_RX_QUEUE0 << queue;
4183                 else if (direction == 1)
4184                         tmp = E1000_EICR_TX_QUEUE0 << queue;
4185                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4186         } else if (hw->mac.type == e1000_82576) {
4187                 if ((direction == 0) || (direction == 1))
4188                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4189                                            ((queue & 0x8) << 1) +
4190                                            8 * direction);
4191         } else if ((hw->mac.type == e1000_82580) ||
4192                         (hw->mac.type == e1000_i350) ||
4193                         (hw->mac.type == e1000_i354) ||
4194                         (hw->mac.type == e1000_i210) ||
4195                         (hw->mac.type == e1000_i211)) {
4196                 if ((direction == 0) || (direction == 1))
4197                         eth_igb_write_ivar(hw, msix_vector,
4198                                            queue >> 1,
4199                                            ((queue & 0x1) << 4) +
4200                                            8 * direction);
4201         }
4202 }
4203
4204 /* Sets up the hardware to generate MSI-X interrupts properly
4205  * @hw
4206  *  board private structure
4207  */
4208 static void
4209 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4210 {
4211         int queue_id;
4212         uint32_t tmpval, regval, intr_mask;
4213         struct e1000_hw *hw =
4214                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4215         uint32_t vec = 0;
4216         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4217
4218         /* won't configure msix register if no mapping is done
4219          * between intr vector and event fd
4220          */
4221         if (!rte_intr_dp_is_en(intr_handle))
4222                 return;
4223
4224         /* set interrupt vector for other causes */
4225         if (hw->mac.type == e1000_82575) {
4226                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4227                 /* enable MSI-X PBA support */
4228                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4229
4230                 /* Auto-Mask interrupts upon ICR read */
4231                 tmpval |= E1000_CTRL_EXT_EIAME;
4232                 tmpval |= E1000_CTRL_EXT_IRCA;
4233
4234                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4235
4236                 /* enable msix_other interrupt */
4237                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4238                 regval = E1000_READ_REG(hw, E1000_EIAC);
4239                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4240                 regval = E1000_READ_REG(hw, E1000_EIAM);
4241                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4242         } else if ((hw->mac.type == e1000_82576) ||
4243                         (hw->mac.type == e1000_82580) ||
4244                         (hw->mac.type == e1000_i350) ||
4245                         (hw->mac.type == e1000_i354) ||
4246                         (hw->mac.type == e1000_i210) ||
4247                         (hw->mac.type == e1000_i211)) {
4248                 /* turn on MSI-X capability first */
4249                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4250                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
4251                                         E1000_GPIE_NSICR);
4252
4253                 intr_mask = (1 << intr_handle->max_intr) - 1;
4254                 regval = E1000_READ_REG(hw, E1000_EIAC);
4255                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4256
4257                 /* enable msix_other interrupt */
4258                 regval = E1000_READ_REG(hw, E1000_EIMS);
4259                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4260                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4261                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4262         }
4263
4264         /* use EIAM to auto-mask when MSI-X interrupt
4265          * is asserted, this saves a register write for every interrupt
4266          */
4267         intr_mask = (1 << intr_handle->nb_efd) - 1;
4268         regval = E1000_READ_REG(hw, E1000_EIAM);
4269         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4270
4271         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4272                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4273                 intr_handle->intr_vec[queue_id] = vec;
4274                 if (vec < intr_handle->nb_efd - 1)
4275                         vec++;
4276         }
4277
4278         E1000_WRITE_FLUSH(hw);
4279 }
4280
4281 PMD_REGISTER_DRIVER(pmd_igb_drv);
4282 PMD_REGISTER_DRIVER(pmd_igbvf_drv);