drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 #define IGB_HKEY_MAX_INDEX 10
  73
  74 /* Bit shift and mask */
  75 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  76 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  77 #define IGB_8_BIT_WIDTH  CHAR_BIT
  78 #define IGB_8_BIT_MASK   UINT8_MAX
  79
  80 /* Additional timesync values. */
  81 #define E1000_ETQF_FILTER_1588 3
  82 #define E1000_TIMINCA_INCVALUE 16000000
  83 #define E1000_TIMINCA_INIT     ((0x02 << E1000_TIMINCA_16NS_SHIFT) \
  84                                 | E1000_TIMINCA_INCVALUE)
  85 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  86
  87 static int  eth_igb_configure(struct rte_eth_dev *dev);
  88 static int  eth_igb_start(struct rte_eth_dev *dev);
  89 static void eth_igb_stop(struct rte_eth_dev *dev);
  90 static void eth_igb_close(struct rte_eth_dev *dev);
  91 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  92 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  93 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  94 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  95 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  96                                 int wait_to_complete);
  97 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  98                                 struct rte_eth_stats *rte_stats);
  99 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 100                               struct rte_eth_xstats *xstats, unsigned n);
 101 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 102 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 103 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 104                               struct rte_eth_dev_info *dev_info);
 105 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 106                                 struct rte_eth_dev_info *dev_info);
 107 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_fc_conf *fc_conf);
 109 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 110                                 struct rte_eth_fc_conf *fc_conf);
 111 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 112 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 113 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 114 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 115 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 116                                                         void *param);
 117 static int  igb_hardware_init(struct e1000_hw *hw);
 118 static void igb_hw_control_acquire(struct e1000_hw *hw);
 119 static void igb_hw_control_release(struct e1000_hw *hw);
 120 static void igb_init_manageability(struct e1000_hw *hw);
 121 static void igb_release_manageability(struct e1000_hw *hw);
 122
 123 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 124
 125 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 126                 uint16_t vlan_id, int on);
 127 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 128 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 129
 130 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 131 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 132 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 133 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 134 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 135 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 136
 137 static int eth_igb_led_on(struct rte_eth_dev *dev);
 138 static int eth_igb_led_off(struct rte_eth_dev *dev);
 139
 140 static void igb_intr_disable(struct e1000_hw *hw);
 141 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 142 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 143                 struct ether_addr *mac_addr,
 144                 uint32_t index, uint32_t pool);
 145 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 146 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 147                 struct ether_addr *addr);
 148
 149 static void igbvf_intr_disable(struct e1000_hw *hw);
 150 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 151 static int igbvf_dev_start(struct rte_eth_dev *dev);
 152 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 153 static void igbvf_dev_close(struct rte_eth_dev *dev);
 154 static int eth_igbvf_link_update(struct e1000_hw *hw);
 155 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 156                                 struct rte_eth_stats *rte_stats);
 157 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 158                                 struct rte_eth_xstats *xstats, unsigned n);
 159 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 160 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 161                 uint16_t vlan_id, int on);
 162 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 163 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 164 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 165                 struct ether_addr *addr);
 166 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 167 static int igbvf_get_regs(struct rte_eth_dev *dev,
 168                 struct rte_dev_reg_info *regs);
 169
 170 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 171                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 172                                    uint16_t reta_size);
 173 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 174                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 175                                   uint16_t reta_size);
 176
 177 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 178                         struct rte_eth_syn_filter *filter,
 179                         bool add);
 180 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 181                         struct rte_eth_syn_filter *filter);
 182 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 183                         enum rte_filter_op filter_op,
 184                         void *arg);
 185 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 186                         struct rte_eth_ntuple_filter *ntuple_filter);
 187 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 188                         struct rte_eth_ntuple_filter *ntuple_filter);
 189 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 190                         struct rte_eth_flex_filter *filter,
 191                         bool add);
 192 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 193                         struct rte_eth_flex_filter *filter);
 194 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 195                         enum rte_filter_op filter_op,
 196                         void *arg);
 197 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 198                         struct rte_eth_ntuple_filter *ntuple_filter);
 199 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 200                         struct rte_eth_ntuple_filter *ntuple_filter);
 201 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 202                         struct rte_eth_ntuple_filter *filter,
 203                         bool add);
 204 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 205                         struct rte_eth_ntuple_filter *filter);
 206 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 207                                 enum rte_filter_op filter_op,
 208                                 void *arg);
 209 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 210                         struct rte_eth_ethertype_filter *filter,
 211                         bool add);
 212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 213                                 enum rte_filter_op filter_op,
 214                                 void *arg);
 215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ethertype_filter *filter);
 217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 218                      enum rte_filter_type filter_type,
 219                      enum rte_filter_op filter_op,
 220                      void *arg);
 221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 223                 struct rte_dev_reg_info *regs);
 224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 226                 struct rte_dev_eeprom_info *eeprom);
 227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 228                 struct rte_dev_eeprom_info *eeprom);
 229 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 230                                     struct ether_addr *mc_addr_set,
 231                                     uint32_t nb_mc_addr);
 232 static int igb_timesync_enable(struct rte_eth_dev *dev);
 233 static int igb_timesync_disable(struct rte_eth_dev *dev);
 234 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 235                                           struct timespec *timestamp,
 236                                           uint32_t flags);
 237 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 238                                           struct timespec *timestamp);
 239 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 240                                         uint16_t queue_id);
 241 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 242                                          uint16_t queue_id);
 243 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 244                                        uint8_t queue, uint8_t msix_vector);
 245 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 246                                uint8_t index, uint8_t offset);
 247 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 248
 249 /*
 250  * Define VF Stats MACRO for Non "cleared on read" register
 251  */
 252 #define UPDATE_VF_STAT(reg, last, cur)            \
 253 {                                                 \
 254         u32 latest = E1000_READ_REG(hw, reg);     \
 255         cur += (latest - last) & UINT_MAX;        \
 256         last = latest;                            \
 257 }
 258
 259 #define IGB_FC_PAUSE_TIME 0x0680
 260 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 261 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 262
 263 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 264
 265 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 266
 267 /*
 268  * The set of PCI devices this driver supports
 269  */
 270 static const struct rte_pci_id pci_id_igb_map[] = {
 271
 272 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 273 #include "rte_pci_dev_ids.h"
 274
 275 {0},
 276 };
 277
 278 /*
 279  * The set of PCI devices this driver supports (for 82576&I350 VF)
 280  */
 281 static const struct rte_pci_id pci_id_igbvf_map[] = {
 282
 283 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 284 #include "rte_pci_dev_ids.h"
 285
 286 {0},
 287 };
 288
 289 static const struct rte_eth_desc_lim rx_desc_lim = {
 290         .nb_max = E1000_MAX_RING_DESC,
 291         .nb_min = E1000_MIN_RING_DESC,
 292         .nb_align = IGB_RXD_ALIGN,
 293 };
 294
 295 static const struct rte_eth_desc_lim tx_desc_lim = {
 296         .nb_max = E1000_MAX_RING_DESC,
 297         .nb_min = E1000_MIN_RING_DESC,
 298         .nb_align = IGB_RXD_ALIGN,
 299 };
 300
 301 static const struct eth_dev_ops eth_igb_ops = {
 302         .dev_configure        = eth_igb_configure,
 303         .dev_start            = eth_igb_start,
 304         .dev_stop             = eth_igb_stop,
 305         .dev_close            = eth_igb_close,
 306         .promiscuous_enable   = eth_igb_promiscuous_enable,
 307         .promiscuous_disable  = eth_igb_promiscuous_disable,
 308         .allmulticast_enable  = eth_igb_allmulticast_enable,
 309         .allmulticast_disable = eth_igb_allmulticast_disable,
 310         .link_update          = eth_igb_link_update,
 311         .stats_get            = eth_igb_stats_get,
 312         .xstats_get           = eth_igb_xstats_get,
 313         .stats_reset          = eth_igb_stats_reset,
 314         .xstats_reset         = eth_igb_xstats_reset,
 315         .dev_infos_get        = eth_igb_infos_get,
 316         .mtu_set              = eth_igb_mtu_set,
 317         .vlan_filter_set      = eth_igb_vlan_filter_set,
 318         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 319         .vlan_offload_set     = eth_igb_vlan_offload_set,
 320         .rx_queue_setup       = eth_igb_rx_queue_setup,
 321         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 322         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 323         .rx_queue_release     = eth_igb_rx_queue_release,
 324         .rx_queue_count       = eth_igb_rx_queue_count,
 325         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 326         .tx_queue_setup       = eth_igb_tx_queue_setup,
 327         .tx_queue_release     = eth_igb_tx_queue_release,
 328         .dev_led_on           = eth_igb_led_on,
 329         .dev_led_off          = eth_igb_led_off,
 330         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 331         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 332         .mac_addr_add         = eth_igb_rar_set,
 333         .mac_addr_remove      = eth_igb_rar_clear,
 334         .mac_addr_set         = eth_igb_default_mac_addr_set,
 335         .reta_update          = eth_igb_rss_reta_update,
 336         .reta_query           = eth_igb_rss_reta_query,
 337         .rss_hash_update      = eth_igb_rss_hash_update,
 338         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 339         .filter_ctrl          = eth_igb_filter_ctrl,
 340         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 341         .rxq_info_get         = igb_rxq_info_get,
 342         .txq_info_get         = igb_txq_info_get,
 343         .timesync_enable      = igb_timesync_enable,
 344         .timesync_disable     = igb_timesync_disable,
 345         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 346         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 347         .get_reg_length       = eth_igb_get_reg_length,
 348         .get_reg              = eth_igb_get_regs,
 349         .get_eeprom_length    = eth_igb_get_eeprom_length,
 350         .get_eeprom           = eth_igb_get_eeprom,
 351         .set_eeprom           = eth_igb_set_eeprom,
 352 };
 353
 354 /*
 355  * dev_ops for virtual function, bare necessities for basic vf
 356  * operation have been implemented
 357  */
 358 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 359         .dev_configure        = igbvf_dev_configure,
 360         .dev_start            = igbvf_dev_start,
 361         .dev_stop             = igbvf_dev_stop,
 362         .dev_close            = igbvf_dev_close,
 363         .link_update          = eth_igb_link_update,
 364         .stats_get            = eth_igbvf_stats_get,
 365         .xstats_get           = eth_igbvf_xstats_get,
 366         .stats_reset          = eth_igbvf_stats_reset,
 367         .xstats_reset         = eth_igbvf_stats_reset,
 368         .vlan_filter_set      = igbvf_vlan_filter_set,
 369         .dev_infos_get        = eth_igbvf_infos_get,
 370         .rx_queue_setup       = eth_igb_rx_queue_setup,
 371         .rx_queue_release     = eth_igb_rx_queue_release,
 372         .tx_queue_setup       = eth_igb_tx_queue_setup,
 373         .tx_queue_release     = eth_igb_tx_queue_release,
 374         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 375         .rxq_info_get         = igb_rxq_info_get,
 376         .txq_info_get         = igb_txq_info_get,
 377         .mac_addr_set         = igbvf_default_mac_addr_set,
 378         .get_reg_length       = igbvf_get_reg_length,
 379         .get_reg              = igbvf_get_regs,
 380 };
 381
 382 /* store statistics names and its offset in stats structure */
 383 struct rte_igb_xstats_name_off {
 384         char name[RTE_ETH_XSTATS_NAME_SIZE];
 385         unsigned offset;
 386 };
 387
 388 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 389         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 390         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 391         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 392         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 393         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 394         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 395         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 396                 ecol)},
 397         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 398         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 399         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 400         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 401         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 402         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 403         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 404         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 405         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 406         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 407         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 408                 fcruc)},
 409         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 410         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 411         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 412         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 413         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 414                 prc1023)},
 415         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 416                 prc1522)},
 417         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 418         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 419         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 420         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 421         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 422         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 423         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 424         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 425         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 426         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 427         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 428         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 429         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 430         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 431         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 432         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 433         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 434         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 435                 ptc1023)},
 436         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 437                 ptc1522)},
 438         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 439         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 440         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 441         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 442         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 443         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 444         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 445
 446         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 447 };
 448
 449 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 450                 sizeof(rte_igb_stats_strings[0]))
 451
 452 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 453         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 454         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 455         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 456         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 457         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 458 };
 459
 460 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 461                 sizeof(rte_igbvf_stats_strings[0]))
 462
 463 /**
 464  * Atomically reads the link status information from global
 465  * structure rte_eth_dev.
 466  *
 467  * @param dev
 468  *   - Pointer to the structure rte_eth_dev to read from.
 469  *   - Pointer to the buffer to be saved with the link status.
 470  *
 471  * @return
 472  *   - On success, zero.
 473  *   - On failure, negative value.
 474  */
 475 static inline int
 476 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 477                                 struct rte_eth_link *link)
 478 {
 479         struct rte_eth_link *dst = link;
 480         struct rte_eth_link *src = &(dev->data->dev_link);
 481
 482         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 483                                         *(uint64_t *)src) == 0)
 484                 return -1;
 485
 486         return 0;
 487 }
 488
 489 /**
 490  * Atomically writes the link status information into global
 491  * structure rte_eth_dev.
 492  *
 493  * @param dev
 494  *   - Pointer to the structure rte_eth_dev to read from.
 495  *   - Pointer to the buffer to be saved with the link status.
 496  *
 497  * @return
 498  *   - On success, zero.
 499  *   - On failure, negative value.
 500  */
 501 static inline int
 502 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 503                                 struct rte_eth_link *link)
 504 {
 505         struct rte_eth_link *dst = &(dev->data->dev_link);
 506         struct rte_eth_link *src = link;
 507
 508         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 509                                         *(uint64_t *)src) == 0)
 510                 return -1;
 511
 512         return 0;
 513 }
 514
 515 static inline void
 516 igb_intr_enable(struct rte_eth_dev *dev)
 517 {
 518         struct e1000_interrupt *intr =
 519                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 520         struct e1000_hw *hw =
 521                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 522
 523         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 524         E1000_WRITE_FLUSH(hw);
 525 }
 526
 527 static void
 528 igb_intr_disable(struct e1000_hw *hw)
 529 {
 530         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 531         E1000_WRITE_FLUSH(hw);
 532 }
 533
 534 static inline int32_t
 535 igb_pf_reset_hw(struct e1000_hw *hw)
 536 {
 537         uint32_t ctrl_ext;
 538         int32_t status;
 539
 540         status = e1000_reset_hw(hw);
 541
 542         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 543         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 544         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 545         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 546         E1000_WRITE_FLUSH(hw);
 547
 548         return status;
 549 }
 550
 551 static void
 552 igb_identify_hardware(struct rte_eth_dev *dev)
 553 {
 554         struct e1000_hw *hw =
 555                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 556
 557         hw->vendor_id = dev->pci_dev->id.vendor_id;
 558         hw->device_id = dev->pci_dev->id.device_id;
 559         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 560         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 561
 562         e1000_set_mac_type(hw);
 563
 564         /* need to check if it is a vf device below */
 565 }
 566
 567 static int
 568 igb_reset_swfw_lock(struct e1000_hw *hw)
 569 {
 570         int ret_val;
 571
 572         /*
 573          * Do mac ops initialization manually here, since we will need
 574          * some function pointers set by this call.
 575          */
 576         ret_val = e1000_init_mac_params(hw);
 577         if (ret_val)
 578                 return ret_val;
 579
 580         /*
 581          * SMBI lock should not fail in this early stage. If this is the case,
 582          * it is due to an improper exit of the application.
 583          * So force the release of the faulty lock.
 584          */
 585         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 586                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 587         }
 588         e1000_put_hw_semaphore_generic(hw);
 589
 590         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 591                 uint16_t mask;
 592
 593                 /*
 594                  * Phy lock should not fail in this early stage. If this is the case,
 595                  * it is due to an improper exit of the application.
 596                  * So force the release of the faulty lock.
 597                  */
 598                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 599                 if (hw->bus.func > E1000_FUNC_1)
 600                         mask <<= 2;
 601                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 602                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 603                                     hw->bus.func);
 604                 }
 605                 hw->mac.ops.release_swfw_sync(hw, mask);
 606
 607                 /*
 608                  * This one is more tricky since it is common to all ports; but
 609                  * swfw_sync retries last long enough (1s) to be almost sure that if
 610                  * lock can not be taken it is due to an improper lock of the
 611                  * semaphore.
 612                  */
 613                 mask = E1000_SWFW_EEP_SM;
 614                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 615                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 616                 }
 617                 hw->mac.ops.release_swfw_sync(hw, mask);
 618         }
 619
 620         return E1000_SUCCESS;
 621 }
 622
 623 static int
 624 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 625 {
 626         int error = 0;
 627         struct rte_pci_device *pci_dev;
 628         struct e1000_hw *hw =
 629                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 630         struct e1000_vfta * shadow_vfta =
 631                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 632         struct e1000_filter_info *filter_info =
 633                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 634         struct e1000_adapter *adapter =
 635                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 636
 637         uint32_t ctrl_ext;
 638
 639         pci_dev = eth_dev->pci_dev;
 640
 641         rte_eth_copy_pci_info(eth_dev, pci_dev);
 642
 643         eth_dev->dev_ops = &eth_igb_ops;
 644         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 645         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 646
 647         /* for secondary processes, we don't initialise any further as primary
 648          * has already done this work. Only check we don't need a different
 649          * RX function */
 650         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 651                 if (eth_dev->data->scattered_rx)
 652                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 653                 return 0;
 654         }
 655
 656         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 657
 658         igb_identify_hardware(eth_dev);
 659         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 660                 error = -EIO;
 661                 goto err_late;
 662         }
 663
 664         e1000_get_bus_info(hw);
 665
 666         /* Reset any pending lock */
 667         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 668                 error = -EIO;
 669                 goto err_late;
 670         }
 671
 672         /* Finish initialization */
 673         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 674                 error = -EIO;
 675                 goto err_late;
 676         }
 677
 678         hw->mac.autoneg = 1;
 679         hw->phy.autoneg_wait_to_complete = 0;
 680         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 681
 682         /* Copper options */
 683         if (hw->phy.media_type == e1000_media_type_copper) {
 684                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 685                 hw->phy.disable_polarity_correction = 0;
 686                 hw->phy.ms_type = e1000_ms_hw_default;
 687         }
 688
 689         /*
 690          * Start from a known state, this is important in reading the nvm
 691          * and mac from that.
 692          */
 693         igb_pf_reset_hw(hw);
 694
 695         /* Make sure we have a good EEPROM before we read from it */
 696         if (e1000_validate_nvm_checksum(hw) < 0) {
 697                 /*
 698                  * Some PCI-E parts fail the first check due to
 699                  * the link being in sleep state, call it again,
 700                  * if it fails a second time its a real issue.
 701                  */
 702                 if (e1000_validate_nvm_checksum(hw) < 0) {
 703                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 704                         error = -EIO;
 705                         goto err_late;
 706                 }
 707         }
 708
 709         /* Read the permanent MAC address out of the EEPROM */
 710         if (e1000_read_mac_addr(hw) != 0) {
 711                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 712                 error = -EIO;
 713                 goto err_late;
 714         }
 715
 716         /* Allocate memory for storing MAC addresses */
 717         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 718                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 719         if (eth_dev->data->mac_addrs == NULL) {
 720                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 721                                                 "store MAC addresses",
 722                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 723                 error = -ENOMEM;
 724                 goto err_late;
 725         }
 726
 727         /* Copy the permanent MAC address */
 728         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 729
 730         /* initialize the vfta */
 731         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 732
 733         /* Now initialize the hardware */
 734         if (igb_hardware_init(hw) != 0) {
 735                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 736                 rte_free(eth_dev->data->mac_addrs);
 737                 eth_dev->data->mac_addrs = NULL;
 738                 error = -ENODEV;
 739                 goto err_late;
 740         }
 741         hw->mac.get_link_status = 1;
 742         adapter->stopped = 0;
 743
 744         /* Indicate SOL/IDER usage */
 745         if (e1000_check_reset_block(hw) < 0) {
 746                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 747                                         "SOL/IDER session");
 748         }
 749
 750         /* initialize PF if max_vfs not zero */
 751         igb_pf_host_init(eth_dev);
 752
 753         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 754         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 755         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 756         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 757         E1000_WRITE_FLUSH(hw);
 758
 759         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 760                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 761                      pci_dev->id.device_id);
 762
 763         rte_intr_callback_register(&pci_dev->intr_handle,
 764                                    eth_igb_interrupt_handler,
 765                                    (void *)eth_dev);
 766
 767         /* enable uio/vfio intr/eventfd mapping */
 768         rte_intr_enable(&pci_dev->intr_handle);
 769
 770         /* enable support intr */
 771         igb_intr_enable(eth_dev);
 772
 773         TAILQ_INIT(&filter_info->flex_list);
 774         filter_info->flex_mask = 0;
 775         TAILQ_INIT(&filter_info->twotuple_list);
 776         filter_info->twotuple_mask = 0;
 777         TAILQ_INIT(&filter_info->fivetuple_list);
 778         filter_info->fivetuple_mask = 0;
 779
 780         return 0;
 781
 782 err_late:
 783         igb_hw_control_release(hw);
 784
 785         return (error);
 786 }
 787
 788 static int
 789 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 790 {
 791         struct rte_pci_device *pci_dev;
 792         struct e1000_hw *hw;
 793         struct e1000_adapter *adapter =
 794                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 795
 796         PMD_INIT_FUNC_TRACE();
 797
 798         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 799                 return -EPERM;
 800
 801         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 802         pci_dev = eth_dev->pci_dev;
 803
 804         if (adapter->stopped == 0)
 805                 eth_igb_close(eth_dev);
 806
 807         eth_dev->dev_ops = NULL;
 808         eth_dev->rx_pkt_burst = NULL;
 809         eth_dev->tx_pkt_burst = NULL;
 810
 811         /* Reset any pending lock */
 812         igb_reset_swfw_lock(hw);
 813
 814         rte_free(eth_dev->data->mac_addrs);
 815         eth_dev->data->mac_addrs = NULL;
 816
 817         /* uninitialize PF if max_vfs not zero */
 818         igb_pf_host_uninit(eth_dev);
 819
 820         /* disable uio intr before callback unregister */
 821         rte_intr_disable(&(pci_dev->intr_handle));
 822         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 823                 eth_igb_interrupt_handler, (void *)eth_dev);
 824
 825         return 0;
 826 }
 827
 828 /*
 829  * Virtual Function device init
 830  */
 831 static int
 832 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 833 {
 834         struct rte_pci_device *pci_dev;
 835         struct e1000_adapter *adapter =
 836                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 837         struct e1000_hw *hw =
 838                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 839         int diag;
 840
 841         PMD_INIT_FUNC_TRACE();
 842
 843         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 844         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 845         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 846
 847         /* for secondary processes, we don't initialise any further as primary
 848          * has already done this work. Only check we don't need a different
 849          * RX function */
 850         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 851                 if (eth_dev->data->scattered_rx)
 852                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 853                 return 0;
 854         }
 855
 856         pci_dev = eth_dev->pci_dev;
 857
 858         rte_eth_copy_pci_info(eth_dev, pci_dev);
 859
 860         hw->device_id = pci_dev->id.device_id;
 861         hw->vendor_id = pci_dev->id.vendor_id;
 862         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 863         adapter->stopped = 0;
 864
 865         /* Initialize the shared code (base driver) */
 866         diag = e1000_setup_init_funcs(hw, TRUE);
 867         if (diag != 0) {
 868                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 869                         diag);
 870                 return -EIO;
 871         }
 872
 873         /* init_mailbox_params */
 874         hw->mbx.ops.init_params(hw);
 875
 876         /* Disable the interrupts for VF */
 877         igbvf_intr_disable(hw);
 878
 879         diag = hw->mac.ops.reset_hw(hw);
 880
 881         /* Allocate memory for storing MAC addresses */
 882         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 883                 hw->mac.rar_entry_count, 0);
 884         if (eth_dev->data->mac_addrs == NULL) {
 885                 PMD_INIT_LOG(ERR,
 886                         "Failed to allocate %d bytes needed to store MAC "
 887                         "addresses",
 888                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 889                 return -ENOMEM;
 890         }
 891
 892         /* Copy the permanent MAC address */
 893         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 894                         &eth_dev->data->mac_addrs[0]);
 895
 896         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 897                      "mac.type=%s",
 898                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 899                      pci_dev->id.device_id, "igb_mac_82576_vf");
 900
 901         return 0;
 902 }
 903
 904 static int
 905 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
 906 {
 907         struct e1000_adapter *adapter =
 908                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 909
 910         PMD_INIT_FUNC_TRACE();
 911
 912         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 913                 return -EPERM;
 914
 915         if (adapter->stopped == 0)
 916                 igbvf_dev_close(eth_dev);
 917
 918         eth_dev->dev_ops = NULL;
 919         eth_dev->rx_pkt_burst = NULL;
 920         eth_dev->tx_pkt_burst = NULL;
 921
 922         rte_free(eth_dev->data->mac_addrs);
 923         eth_dev->data->mac_addrs = NULL;
 924
 925         return 0;
 926 }
 927
 928 static struct eth_driver rte_igb_pmd = {
 929         .pci_drv = {
 930                 .name = "rte_igb_pmd",
 931                 .id_table = pci_id_igb_map,
 932                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 933                         RTE_PCI_DRV_DETACHABLE,
 934         },
 935         .eth_dev_init = eth_igb_dev_init,
 936         .eth_dev_uninit = eth_igb_dev_uninit,
 937         .dev_private_size = sizeof(struct e1000_adapter),
 938 };
 939
 940 /*
 941  * virtual function driver struct
 942  */
 943 static struct eth_driver rte_igbvf_pmd = {
 944         .pci_drv = {
 945                 .name = "rte_igbvf_pmd",
 946                 .id_table = pci_id_igbvf_map,
 947                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
 948         },
 949         .eth_dev_init = eth_igbvf_dev_init,
 950         .eth_dev_uninit = eth_igbvf_dev_uninit,
 951         .dev_private_size = sizeof(struct e1000_adapter),
 952 };
 953
 954 static int
 955 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 956 {
 957         rte_eth_driver_register(&rte_igb_pmd);
 958         return 0;
 959 }
 960
 961 static void
 962 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 963 {
 964         struct e1000_hw *hw =
 965                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 966         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 967         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 968         rctl |= E1000_RCTL_VFE;
 969         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 970 }
 971
 972 /*
 973  * VF Driver initialization routine.
 974  * Invoked one at EAL init time.
 975  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 976  */
 977 static int
 978 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 979 {
 980         PMD_INIT_FUNC_TRACE();
 981
 982         rte_eth_driver_register(&rte_igbvf_pmd);
 983         return (0);
 984 }
 985
 986 static int
 987 igb_check_mq_mode(struct rte_eth_dev *dev)
 988 {
 989         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 990         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
 991         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 992         uint16_t nb_tx_q = dev->data->nb_rx_queues;
 993
 994         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
 995             tx_mq_mode == ETH_MQ_TX_DCB ||
 996             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
 997                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
 998                 return -EINVAL;
 999         }
1000         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1001                 /* Check multi-queue mode.
1002                  * To no break software we accept ETH_MQ_RX_NONE as this might
1003                  * be used to turn off VLAN filter.
1004                  */
1005
1006                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1007                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1008                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1009                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1010                 } else {
1011                         /* Only support one queue on VFs.
1012                          * RSS together with SRIOV is not supported.
1013                          */
1014                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1015                                         " wrong mq_mode rx %d.",
1016                                         rx_mq_mode);
1017                         return -EINVAL;
1018                 }
1019                 /* TX mode is not used here, so mode might be ignored.*/
1020                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1021                         /* SRIOV only works in VMDq enable mode */
1022                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1023                                         " TX mode %d is not supported. "
1024                                         " Driver will behave as %d mode.",
1025                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1026                 }
1027
1028                 /* check valid queue number */
1029                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1030                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1031                                         " only support one queue on VFs.");
1032                         return -EINVAL;
1033                 }
1034         } else {
1035                 /* To no break software that set invalid mode, only display
1036                  * warning if invalid mode is used.
1037                  */
1038                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1039                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1040                     rx_mq_mode != ETH_MQ_RX_RSS) {
1041                         /* RSS together with VMDq not supported*/
1042                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1043                                      rx_mq_mode);
1044                         return -EINVAL;
1045                 }
1046
1047                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1048                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1049                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1050                                         " Due to txmode is meaningless in this"
1051                                         " driver, just ignore.",
1052                                         tx_mq_mode);
1053                 }
1054         }
1055         return 0;
1056 }
1057
1058 static int
1059 eth_igb_configure(struct rte_eth_dev *dev)
1060 {
1061         struct e1000_interrupt *intr =
1062                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1063         int ret;
1064
1065         PMD_INIT_FUNC_TRACE();
1066
1067         /* multipe queue mode checking */
1068         ret  = igb_check_mq_mode(dev);
1069         if (ret != 0) {
1070                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1071                             ret);
1072                 return ret;
1073         }
1074
1075         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1076         PMD_INIT_FUNC_TRACE();
1077
1078         return 0;
1079 }
1080
1081 static int
1082 eth_igb_start(struct rte_eth_dev *dev)
1083 {
1084         struct e1000_hw *hw =
1085                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1086         struct e1000_adapter *adapter =
1087                 E1000_DEV_PRIVATE(dev->data->dev_private);
1088         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1089         int ret, mask;
1090         uint32_t intr_vector = 0;
1091         uint32_t ctrl_ext;
1092
1093         PMD_INIT_FUNC_TRACE();
1094
1095         /* Power up the phy. Needed to make the link go Up */
1096         e1000_power_up_phy(hw);
1097
1098         /*
1099          * Packet Buffer Allocation (PBA)
1100          * Writing PBA sets the receive portion of the buffer
1101          * the remainder is used for the transmit buffer.
1102          */
1103         if (hw->mac.type == e1000_82575) {
1104                 uint32_t pba;
1105
1106                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1107                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1108         }
1109
1110         /* Put the address into the Receive Address Array */
1111         e1000_rar_set(hw, hw->mac.addr, 0);
1112
1113         /* Initialize the hardware */
1114         if (igb_hardware_init(hw)) {
1115                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1116                 return (-EIO);
1117         }
1118         adapter->stopped = 0;
1119
1120         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1121
1122         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1123         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1124         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1125         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1126         E1000_WRITE_FLUSH(hw);
1127
1128         /* configure PF module if SRIOV enabled */
1129         igb_pf_host_configure(dev);
1130
1131         /* check and configure queue intr-vector mapping */
1132         if ((rte_intr_cap_multiple(intr_handle) ||
1133              !RTE_ETH_DEV_SRIOV(dev).active) &&
1134             dev->data->dev_conf.intr_conf.rxq != 0) {
1135                 intr_vector = dev->data->nb_rx_queues;
1136                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1137                         return -1;
1138         }
1139
1140         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1141                 intr_handle->intr_vec =
1142                         rte_zmalloc("intr_vec",
1143                                     dev->data->nb_rx_queues * sizeof(int), 0);
1144                 if (intr_handle->intr_vec == NULL) {
1145                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1146                                      " intr_vec\n", dev->data->nb_rx_queues);
1147                         return -ENOMEM;
1148                 }
1149         }
1150
1151         /* confiugre msix for rx interrupt */
1152         eth_igb_configure_msix_intr(dev);
1153
1154         /* Configure for OS presence */
1155         igb_init_manageability(hw);
1156
1157         eth_igb_tx_init(dev);
1158
1159         /* This can fail when allocating mbufs for descriptor rings */
1160         ret = eth_igb_rx_init(dev);
1161         if (ret) {
1162                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1163                 igb_dev_clear_queues(dev);
1164                 return ret;
1165         }
1166
1167         e1000_clear_hw_cntrs_base_generic(hw);
1168
1169         /*
1170          * VLAN Offload Settings
1171          */
1172         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1173                         ETH_VLAN_EXTEND_MASK;
1174         eth_igb_vlan_offload_set(dev, mask);
1175
1176         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1177                 /* Enable VLAN filter since VMDq always use VLAN filter */
1178                 igb_vmdq_vlan_hw_filter_enable(dev);
1179         }
1180
1181         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1182                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1183                 (hw->mac.type == e1000_i211)) {
1184                 /* Configure EITR with the maximum possible value (0xFFFF) */
1185                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1186         }
1187
1188         /* Setup link speed and duplex */
1189         switch (dev->data->dev_conf.link_speed) {
1190         case ETH_LINK_SPEED_AUTONEG:
1191                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1192                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1193                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1194                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
1195                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1196                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
1197                 else
1198                         goto error_invalid_config;
1199                 break;
1200         case ETH_LINK_SPEED_10:
1201                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1202                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
1203                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1204                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
1205                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1206                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1207                 else
1208                         goto error_invalid_config;
1209                 break;
1210         case ETH_LINK_SPEED_100:
1211                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1212                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1213                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1214                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1215                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1216                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1217                 else
1218                         goto error_invalid_config;
1219                 break;
1220         case ETH_LINK_SPEED_1000:
1221                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1222                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1223                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1224                 else
1225                         goto error_invalid_config;
1226                 break;
1227         case ETH_LINK_SPEED_10000:
1228         default:
1229                 goto error_invalid_config;
1230         }
1231         e1000_setup_link(hw);
1232
1233         if (rte_intr_allow_others(intr_handle)) {
1234                 /* check if lsc interrupt is enabled */
1235                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1236                         eth_igb_lsc_interrupt_setup(dev);
1237         } else {
1238                 rte_intr_callback_unregister(intr_handle,
1239                                              eth_igb_interrupt_handler,
1240                                              (void *)dev);
1241                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1242                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1243                                      " no intr multiplex\n");
1244         }
1245
1246         /* check if rxq interrupt is enabled */
1247         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1248             rte_intr_dp_is_en(intr_handle))
1249                 eth_igb_rxq_interrupt_setup(dev);
1250
1251         /* enable uio/vfio intr/eventfd mapping */
1252         rte_intr_enable(intr_handle);
1253
1254         /* resume enabled intr since hw reset */
1255         igb_intr_enable(dev);
1256
1257         PMD_INIT_LOG(DEBUG, "<<");
1258
1259         return (0);
1260
1261 error_invalid_config:
1262         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1263                      dev->data->dev_conf.link_speed,
1264                      dev->data->dev_conf.link_duplex, dev->data->port_id);
1265         igb_dev_clear_queues(dev);
1266         return (-EINVAL);
1267 }
1268
1269 /*********************************************************************
1270  *
1271  *  This routine disables all traffic on the adapter by issuing a
1272  *  global reset on the MAC.
1273  *
1274  **********************************************************************/
1275 static void
1276 eth_igb_stop(struct rte_eth_dev *dev)
1277 {
1278         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1279         struct e1000_filter_info *filter_info =
1280                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1281         struct rte_eth_link link;
1282         struct e1000_flex_filter *p_flex;
1283         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1284         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1285         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1286
1287         igb_intr_disable(hw);
1288
1289         /* disable intr eventfd mapping */
1290         rte_intr_disable(intr_handle);
1291
1292         igb_pf_reset_hw(hw);
1293         E1000_WRITE_REG(hw, E1000_WUC, 0);
1294
1295         /* Set bit for Go Link disconnect */
1296         if (hw->mac.type >= e1000_82580) {
1297                 uint32_t phpm_reg;
1298
1299                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1300                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1301                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1302         }
1303
1304         /* Power down the phy. Needed to make the link go Down */
1305         if (hw->phy.media_type == e1000_media_type_copper)
1306                 e1000_power_down_phy(hw);
1307         else
1308                 e1000_shutdown_fiber_serdes_link(hw);
1309
1310         igb_dev_clear_queues(dev);
1311
1312         /* clear the recorded link status */
1313         memset(&link, 0, sizeof(link));
1314         rte_igb_dev_atomic_write_link_status(dev, &link);
1315
1316         /* Remove all flex filters of the device */
1317         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1318                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1319                 rte_free(p_flex);
1320         }
1321         filter_info->flex_mask = 0;
1322
1323         /* Remove all ntuple filters of the device */
1324         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1325              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1326                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1327                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1328                              p_5tuple, entries);
1329                 rte_free(p_5tuple);
1330         }
1331         filter_info->fivetuple_mask = 0;
1332         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1333              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1334                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1335                 TAILQ_REMOVE(&filter_info->twotuple_list,
1336                              p_2tuple, entries);
1337                 rte_free(p_2tuple);
1338         }
1339         filter_info->twotuple_mask = 0;
1340
1341         if (!rte_intr_allow_others(intr_handle))
1342                 /* resume to the default handler */
1343                 rte_intr_callback_register(intr_handle,
1344                                            eth_igb_interrupt_handler,
1345                                            (void *)dev);
1346
1347         /* Clean datapath event and queue/vec mapping */
1348         rte_intr_efd_disable(intr_handle);
1349         if (intr_handle->intr_vec != NULL) {
1350                 rte_free(intr_handle->intr_vec);
1351                 intr_handle->intr_vec = NULL;
1352         }
1353 }
1354
1355 static void
1356 eth_igb_close(struct rte_eth_dev *dev)
1357 {
1358         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1359         struct e1000_adapter *adapter =
1360                 E1000_DEV_PRIVATE(dev->data->dev_private);
1361         struct rte_eth_link link;
1362         struct rte_pci_device *pci_dev;
1363
1364         eth_igb_stop(dev);
1365         adapter->stopped = 1;
1366
1367         e1000_phy_hw_reset(hw);
1368         igb_release_manageability(hw);
1369         igb_hw_control_release(hw);
1370
1371         /* Clear bit for Go Link disconnect */
1372         if (hw->mac.type >= e1000_82580) {
1373                 uint32_t phpm_reg;
1374
1375                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1376                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1377                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1378         }
1379
1380         igb_dev_free_queues(dev);
1381
1382         pci_dev = dev->pci_dev;
1383         if (pci_dev->intr_handle.intr_vec) {
1384                 rte_free(pci_dev->intr_handle.intr_vec);
1385                 pci_dev->intr_handle.intr_vec = NULL;
1386         }
1387
1388         memset(&link, 0, sizeof(link));
1389         rte_igb_dev_atomic_write_link_status(dev, &link);
1390 }
1391
1392 static int
1393 igb_get_rx_buffer_size(struct e1000_hw *hw)
1394 {
1395         uint32_t rx_buf_size;
1396         if (hw->mac.type == e1000_82576) {
1397                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1398         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1399                 /* PBS needs to be translated according to a lookup table */
1400                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1401                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1402                 rx_buf_size = (rx_buf_size << 10);
1403         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1404                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1405         } else {
1406                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1407         }
1408
1409         return rx_buf_size;
1410 }
1411
1412 /*********************************************************************
1413  *
1414  *  Initialize the hardware
1415  *
1416  **********************************************************************/
1417 static int
1418 igb_hardware_init(struct e1000_hw *hw)
1419 {
1420         uint32_t rx_buf_size;
1421         int diag;
1422
1423         /* Let the firmware know the OS is in control */
1424         igb_hw_control_acquire(hw);
1425
1426         /*
1427          * These parameters control the automatic generation (Tx) and
1428          * response (Rx) to Ethernet PAUSE frames.
1429          * - High water mark should allow for at least two standard size (1518)
1430          *   frames to be received after sending an XOFF.
1431          * - Low water mark works best when it is very near the high water mark.
1432          *   This allows the receiver to restart by sending XON when it has
1433          *   drained a bit. Here we use an arbitrary value of 1500 which will
1434          *   restart after one full frame is pulled from the buffer. There
1435          *   could be several smaller frames in the buffer and if so they will
1436          *   not trigger the XON until their total number reduces the buffer
1437          *   by 1500.
1438          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1439          */
1440         rx_buf_size = igb_get_rx_buffer_size(hw);
1441
1442         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1443         hw->fc.low_water = hw->fc.high_water - 1500;
1444         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1445         hw->fc.send_xon = 1;
1446
1447         /* Set Flow control, use the tunable location if sane */
1448         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1449                 hw->fc.requested_mode = igb_fc_setting;
1450         else
1451                 hw->fc.requested_mode = e1000_fc_none;
1452
1453         /* Issue a global reset */
1454         igb_pf_reset_hw(hw);
1455         E1000_WRITE_REG(hw, E1000_WUC, 0);
1456
1457         diag = e1000_init_hw(hw);
1458         if (diag < 0)
1459                 return (diag);
1460
1461         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1462         e1000_get_phy_info(hw);
1463         e1000_check_for_link(hw);
1464
1465         return (0);
1466 }
1467
1468 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1469 static void
1470 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1471 {
1472         int pause_frames;
1473
1474         if(hw->phy.media_type == e1000_media_type_copper ||
1475             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1476                 stats->symerrs +=
1477                     E1000_READ_REG(hw,E1000_SYMERRS);
1478                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1479         }
1480
1481         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1482         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1483         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1484         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1485
1486         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1487         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1488         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1489         stats->dc += E1000_READ_REG(hw, E1000_DC);
1490         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1491         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1492         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1493         /*
1494         ** For watchdog management we need to know if we have been
1495         ** paused during the last interval, so capture that here.
1496         */
1497         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1498         stats->xoffrxc += pause_frames;
1499         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1500         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1501         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1502         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1503         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1504         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1505         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1506         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1507         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1508         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1509         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1510         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1511
1512         /* For the 64-bit byte counters the low dword must be read first. */
1513         /* Both registers clear on the read of the high dword */
1514
1515         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1516         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1517         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1518         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1519
1520         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1521         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1522         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1523         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1524         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1525
1526         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1527         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1528         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1529         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1530
1531         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1532         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1533         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1534         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1535         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1536         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1537         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1538         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1539         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1540         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1541
1542         /* Interrupt Counts */
1543
1544         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1545         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1546         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1547         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1548         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1549         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1550         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1551         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1552         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1553
1554         /* Host to Card Statistics */
1555
1556         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1557         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1558         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1559         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1560         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1561         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1562         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1563         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1564         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1565         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1566         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1567         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1568         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1569         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1570
1571         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1572         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1573         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1574         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1575         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1576         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1577 }
1578
1579 static void
1580 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1581 {
1582         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1583         struct e1000_hw_stats *stats =
1584                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1585
1586         igb_read_stats_registers(hw, stats);
1587
1588         if (rte_stats == NULL)
1589                 return;
1590
1591         /* Rx Errors */
1592         rte_stats->ibadcrc = stats->crcerrs;
1593         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1594         rte_stats->imissed = stats->mpc;
1595         rte_stats->ierrors = rte_stats->ibadcrc +
1596                              rte_stats->ibadlen +
1597                              rte_stats->imissed +
1598                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1599
1600         /* Tx Errors */
1601         rte_stats->oerrors = stats->ecol + stats->latecol;
1602
1603         /* XON/XOFF pause frames */
1604         rte_stats->tx_pause_xon  = stats->xontxc;
1605         rte_stats->rx_pause_xon  = stats->xonrxc;
1606         rte_stats->tx_pause_xoff = stats->xofftxc;
1607         rte_stats->rx_pause_xoff = stats->xoffrxc;
1608
1609         rte_stats->ipackets = stats->gprc;
1610         rte_stats->opackets = stats->gptc;
1611         rte_stats->ibytes   = stats->gorc;
1612         rte_stats->obytes   = stats->gotc;
1613 }
1614
1615 static void
1616 eth_igb_stats_reset(struct rte_eth_dev *dev)
1617 {
1618         struct e1000_hw_stats *hw_stats =
1619                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1620
1621         /* HW registers are cleared on read */
1622         eth_igb_stats_get(dev, NULL);
1623
1624         /* Reset software totals */
1625         memset(hw_stats, 0, sizeof(*hw_stats));
1626 }
1627
1628 static void
1629 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1630 {
1631         struct e1000_hw_stats *stats =
1632                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1633
1634         /* HW registers are cleared on read */
1635         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1636
1637         /* Reset software totals */
1638         memset(stats, 0, sizeof(*stats));
1639 }
1640
1641 static int
1642 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1643                    unsigned n)
1644 {
1645         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1646         struct e1000_hw_stats *hw_stats =
1647                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1648         unsigned i;
1649
1650         if (n < IGB_NB_XSTATS)
1651                 return IGB_NB_XSTATS;
1652
1653         igb_read_stats_registers(hw, hw_stats);
1654
1655         /* If this is a reset xstats is NULL, and we have cleared the
1656          * registers by reading them.
1657          */
1658         if (!xstats)
1659                 return 0;
1660
1661         /* Extended stats */
1662         for (i = 0; i < IGB_NB_XSTATS; i++) {
1663                 snprintf(xstats[i].name, sizeof(xstats[i].name),
1664                          "%s", rte_igb_stats_strings[i].name);
1665                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1666                         rte_igb_stats_strings[i].offset);
1667         }
1668
1669         return IGB_NB_XSTATS;
1670 }
1671
1672 static void
1673 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1674 {
1675         /* Good Rx packets, include VF loopback */
1676         UPDATE_VF_STAT(E1000_VFGPRC,
1677             hw_stats->last_gprc, hw_stats->gprc);
1678
1679         /* Good Rx octets, include VF loopback */
1680         UPDATE_VF_STAT(E1000_VFGORC,
1681             hw_stats->last_gorc, hw_stats->gorc);
1682
1683         /* Good Tx packets, include VF loopback */
1684         UPDATE_VF_STAT(E1000_VFGPTC,
1685             hw_stats->last_gptc, hw_stats->gptc);
1686
1687         /* Good Tx octets, include VF loopback */
1688         UPDATE_VF_STAT(E1000_VFGOTC,
1689             hw_stats->last_gotc, hw_stats->gotc);
1690
1691         /* Rx Multicst packets */
1692         UPDATE_VF_STAT(E1000_VFMPRC,
1693             hw_stats->last_mprc, hw_stats->mprc);
1694
1695         /* Good Rx loopback packets */
1696         UPDATE_VF_STAT(E1000_VFGPRLBC,
1697             hw_stats->last_gprlbc, hw_stats->gprlbc);
1698
1699         /* Good Rx loopback octets */
1700         UPDATE_VF_STAT(E1000_VFGORLBC,
1701             hw_stats->last_gorlbc, hw_stats->gorlbc);
1702
1703         /* Good Tx loopback packets */
1704         UPDATE_VF_STAT(E1000_VFGPTLBC,
1705             hw_stats->last_gptlbc, hw_stats->gptlbc);
1706
1707         /* Good Tx loopback octets */
1708         UPDATE_VF_STAT(E1000_VFGOTLBC,
1709             hw_stats->last_gotlbc, hw_stats->gotlbc);
1710 }
1711
1712 static int
1713 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1714                      unsigned n)
1715 {
1716         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1717         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1718                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1719         unsigned i;
1720
1721         if (n < IGBVF_NB_XSTATS)
1722                 return IGBVF_NB_XSTATS;
1723
1724         igbvf_read_stats_registers(hw, hw_stats);
1725
1726         if (!xstats)
1727                 return 0;
1728
1729         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1730                 snprintf(xstats[i].name, sizeof(xstats[i].name), "%s",
1731                          rte_igbvf_stats_strings[i].name);
1732                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1733                         rte_igbvf_stats_strings[i].offset);
1734         }
1735
1736         return IGBVF_NB_XSTATS;
1737 }
1738
1739 static void
1740 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1741 {
1742         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1743         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1744                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1745
1746         igbvf_read_stats_registers(hw, hw_stats);
1747
1748         if (rte_stats == NULL)
1749                 return;
1750
1751         rte_stats->ipackets = hw_stats->gprc;
1752         rte_stats->ibytes = hw_stats->gorc;
1753         rte_stats->opackets = hw_stats->gptc;
1754         rte_stats->obytes = hw_stats->gotc;
1755         rte_stats->imcasts = hw_stats->mprc;
1756         rte_stats->ilbpackets = hw_stats->gprlbc;
1757         rte_stats->ilbbytes = hw_stats->gorlbc;
1758         rte_stats->olbpackets = hw_stats->gptlbc;
1759         rte_stats->olbbytes = hw_stats->gotlbc;
1760 }
1761
1762 static void
1763 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1764 {
1765         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1766                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1767
1768         /* Sync HW register to the last stats */
1769         eth_igbvf_stats_get(dev, NULL);
1770
1771         /* reset HW current stats*/
1772         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1773                offsetof(struct e1000_vf_stats, gprc));
1774 }
1775
1776 static void
1777 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1778 {
1779         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1780
1781         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1782         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1783         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1784         dev_info->rx_offload_capa =
1785                 DEV_RX_OFFLOAD_VLAN_STRIP |
1786                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1787                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1788                 DEV_RX_OFFLOAD_TCP_CKSUM;
1789         dev_info->tx_offload_capa =
1790                 DEV_TX_OFFLOAD_VLAN_INSERT |
1791                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1792                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1793                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1794                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1795                 DEV_TX_OFFLOAD_TCP_TSO;
1796
1797         switch (hw->mac.type) {
1798         case e1000_82575:
1799                 dev_info->max_rx_queues = 4;
1800                 dev_info->max_tx_queues = 4;
1801                 dev_info->max_vmdq_pools = 0;
1802                 break;
1803
1804         case e1000_82576:
1805                 dev_info->max_rx_queues = 16;
1806                 dev_info->max_tx_queues = 16;
1807                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1808                 dev_info->vmdq_queue_num = 16;
1809                 break;
1810
1811         case e1000_82580:
1812                 dev_info->max_rx_queues = 8;
1813                 dev_info->max_tx_queues = 8;
1814                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1815                 dev_info->vmdq_queue_num = 8;
1816                 break;
1817
1818         case e1000_i350:
1819                 dev_info->max_rx_queues = 8;
1820                 dev_info->max_tx_queues = 8;
1821                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1822                 dev_info->vmdq_queue_num = 8;
1823                 break;
1824
1825         case e1000_i354:
1826                 dev_info->max_rx_queues = 8;
1827                 dev_info->max_tx_queues = 8;
1828                 break;
1829
1830         case e1000_i210:
1831                 dev_info->max_rx_queues = 4;
1832                 dev_info->max_tx_queues = 4;
1833                 dev_info->max_vmdq_pools = 0;
1834                 break;
1835
1836         case e1000_i211:
1837                 dev_info->max_rx_queues = 2;
1838                 dev_info->max_tx_queues = 2;
1839                 dev_info->max_vmdq_pools = 0;
1840                 break;
1841
1842         default:
1843                 /* Should not happen */
1844                 break;
1845         }
1846         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1847         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1848         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1849
1850         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1851                 .rx_thresh = {
1852                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1853                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1854                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1855                 },
1856                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1857                 .rx_drop_en = 0,
1858         };
1859
1860         dev_info->default_txconf = (struct rte_eth_txconf) {
1861                 .tx_thresh = {
1862                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1863                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1864                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1865                 },
1866                 .txq_flags = 0,
1867         };
1868
1869         dev_info->rx_desc_lim = rx_desc_lim;
1870         dev_info->tx_desc_lim = tx_desc_lim;
1871 }
1872
1873 static void
1874 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1875 {
1876         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1877
1878         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1879         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1880         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1881         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1882                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1883                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1884                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1885         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1886                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1887                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1888                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1889                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1890                                 DEV_TX_OFFLOAD_TCP_TSO;
1891         switch (hw->mac.type) {
1892         case e1000_vfadapt:
1893                 dev_info->max_rx_queues = 2;
1894                 dev_info->max_tx_queues = 2;
1895                 break;
1896         case e1000_vfadapt_i350:
1897                 dev_info->max_rx_queues = 1;
1898                 dev_info->max_tx_queues = 1;
1899                 break;
1900         default:
1901                 /* Should not happen */
1902                 break;
1903         }
1904
1905         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1906                 .rx_thresh = {
1907                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1908                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1909                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1910                 },
1911                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1912                 .rx_drop_en = 0,
1913         };
1914
1915         dev_info->default_txconf = (struct rte_eth_txconf) {
1916                 .tx_thresh = {
1917                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1918                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1919                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1920                 },
1921                 .txq_flags = 0,
1922         };
1923
1924         dev_info->rx_desc_lim = rx_desc_lim;
1925         dev_info->tx_desc_lim = tx_desc_lim;
1926 }
1927
1928 /* return 0 means link status changed, -1 means not changed */
1929 static int
1930 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1931 {
1932         struct e1000_hw *hw =
1933                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1934         struct rte_eth_link link, old;
1935         int link_check, count;
1936
1937         link_check = 0;
1938         hw->mac.get_link_status = 1;
1939
1940         /* possible wait-to-complete in up to 9 seconds */
1941         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1942                 /* Read the real link status */
1943                 switch (hw->phy.media_type) {
1944                 case e1000_media_type_copper:
1945                         /* Do the work to read phy */
1946                         e1000_check_for_link(hw);
1947                         link_check = !hw->mac.get_link_status;
1948                         break;
1949
1950                 case e1000_media_type_fiber:
1951                         e1000_check_for_link(hw);
1952                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1953                                       E1000_STATUS_LU);
1954                         break;
1955
1956                 case e1000_media_type_internal_serdes:
1957                         e1000_check_for_link(hw);
1958                         link_check = hw->mac.serdes_has_link;
1959                         break;
1960
1961                 /* VF device is type_unknown */
1962                 case e1000_media_type_unknown:
1963                         eth_igbvf_link_update(hw);
1964                         link_check = !hw->mac.get_link_status;
1965                         break;
1966
1967                 default:
1968                         break;
1969                 }
1970                 if (link_check || wait_to_complete == 0)
1971                         break;
1972                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1973         }
1974         memset(&link, 0, sizeof(link));
1975         rte_igb_dev_atomic_read_link_status(dev, &link);
1976         old = link;
1977
1978         /* Now we check if a transition has happened */
1979         if (link_check) {
1980                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1981                                           &link.link_duplex);
1982                 link.link_status = 1;
1983         } else if (!link_check) {
1984                 link.link_speed = 0;
1985                 link.link_duplex = 0;
1986                 link.link_status = 0;
1987         }
1988         rte_igb_dev_atomic_write_link_status(dev, &link);
1989
1990         /* not changed */
1991         if (old.link_status == link.link_status)
1992                 return -1;
1993
1994         /* changed */
1995         return 0;
1996 }
1997
1998 /*
1999  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2000  * For ASF and Pass Through versions of f/w this means
2001  * that the driver is loaded.
2002  */
2003 static void
2004 igb_hw_control_acquire(struct e1000_hw *hw)
2005 {
2006         uint32_t ctrl_ext;
2007
2008         /* Let firmware know the driver has taken over */
2009         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2010         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2011 }
2012
2013 /*
2014  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2015  * For ASF and Pass Through versions of f/w this means that the
2016  * driver is no longer loaded.
2017  */
2018 static void
2019 igb_hw_control_release(struct e1000_hw *hw)
2020 {
2021         uint32_t ctrl_ext;
2022
2023         /* Let firmware taken over control of h/w */
2024         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2025         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2026                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2027 }
2028
2029 /*
2030  * Bit of a misnomer, what this really means is
2031  * to enable OS management of the system... aka
2032  * to disable special hardware management features.
2033  */
2034 static void
2035 igb_init_manageability(struct e1000_hw *hw)
2036 {
2037         if (e1000_enable_mng_pass_thru(hw)) {
2038                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2039                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2040
2041                 /* disable hardware interception of ARP */
2042                 manc &= ~(E1000_MANC_ARP_EN);
2043
2044                 /* enable receiving management packets to the host */
2045                 manc |= E1000_MANC_EN_MNG2HOST;
2046                 manc2h |= 1 << 5;  /* Mng Port 623 */
2047                 manc2h |= 1 << 6;  /* Mng Port 664 */
2048                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2049                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2050         }
2051 }
2052
2053 static void
2054 igb_release_manageability(struct e1000_hw *hw)
2055 {
2056         if (e1000_enable_mng_pass_thru(hw)) {
2057                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2058
2059                 manc |= E1000_MANC_ARP_EN;
2060                 manc &= ~E1000_MANC_EN_MNG2HOST;
2061
2062                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2063         }
2064 }
2065
2066 static void
2067 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2068 {
2069         struct e1000_hw *hw =
2070                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2071         uint32_t rctl;
2072
2073         rctl = E1000_READ_REG(hw, E1000_RCTL);
2074         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2075         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2076 }
2077
2078 static void
2079 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2080 {
2081         struct e1000_hw *hw =
2082                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2083         uint32_t rctl;
2084
2085         rctl = E1000_READ_REG(hw, E1000_RCTL);
2086         rctl &= (~E1000_RCTL_UPE);
2087         if (dev->data->all_multicast == 1)
2088                 rctl |= E1000_RCTL_MPE;
2089         else
2090                 rctl &= (~E1000_RCTL_MPE);
2091         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2092 }
2093
2094 static void
2095 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2096 {
2097         struct e1000_hw *hw =
2098                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099         uint32_t rctl;
2100
2101         rctl = E1000_READ_REG(hw, E1000_RCTL);
2102         rctl |= E1000_RCTL_MPE;
2103         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2104 }
2105
2106 static void
2107 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2108 {
2109         struct e1000_hw *hw =
2110                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2111         uint32_t rctl;
2112
2113         if (dev->data->promiscuous == 1)
2114                 return; /* must remain in all_multicast mode */
2115         rctl = E1000_READ_REG(hw, E1000_RCTL);
2116         rctl &= (~E1000_RCTL_MPE);
2117         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2118 }
2119
2120 static int
2121 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2122 {
2123         struct e1000_hw *hw =
2124                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125         struct e1000_vfta * shadow_vfta =
2126                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2127         uint32_t vfta;
2128         uint32_t vid_idx;
2129         uint32_t vid_bit;
2130
2131         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2132                               E1000_VFTA_ENTRY_MASK);
2133         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2134         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2135         if (on)
2136                 vfta |= vid_bit;
2137         else
2138                 vfta &= ~vid_bit;
2139         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2140
2141         /* update local VFTA copy */
2142         shadow_vfta->vfta[vid_idx] = vfta;
2143
2144         return 0;
2145 }
2146
2147 static void
2148 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
2149 {
2150         struct e1000_hw *hw =
2151                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2152         uint32_t reg = ETHER_TYPE_VLAN ;
2153
2154         reg |= (tpid << 16);
2155         E1000_WRITE_REG(hw, E1000_VET, reg);
2156 }
2157
2158 static void
2159 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2160 {
2161         struct e1000_hw *hw =
2162                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163         uint32_t reg;
2164
2165         /* Filter Table Disable */
2166         reg = E1000_READ_REG(hw, E1000_RCTL);
2167         reg &= ~E1000_RCTL_CFIEN;
2168         reg &= ~E1000_RCTL_VFE;
2169         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2170 }
2171
2172 static void
2173 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2174 {
2175         struct e1000_hw *hw =
2176                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2177         struct e1000_vfta * shadow_vfta =
2178                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2179         uint32_t reg;
2180         int i;
2181
2182         /* Filter Table Enable, CFI not used for packet acceptance */
2183         reg = E1000_READ_REG(hw, E1000_RCTL);
2184         reg &= ~E1000_RCTL_CFIEN;
2185         reg |= E1000_RCTL_VFE;
2186         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2187
2188         /* restore VFTA table */
2189         for (i = 0; i < IGB_VFTA_SIZE; i++)
2190                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2191 }
2192
2193 static void
2194 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2195 {
2196         struct e1000_hw *hw =
2197                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2198         uint32_t reg;
2199
2200         /* VLAN Mode Disable */
2201         reg = E1000_READ_REG(hw, E1000_CTRL);
2202         reg &= ~E1000_CTRL_VME;
2203         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2204 }
2205
2206 static void
2207 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2208 {
2209         struct e1000_hw *hw =
2210                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2211         uint32_t reg;
2212
2213         /* VLAN Mode Enable */
2214         reg = E1000_READ_REG(hw, E1000_CTRL);
2215         reg |= E1000_CTRL_VME;
2216         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2217 }
2218
2219 static void
2220 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2221 {
2222         struct e1000_hw *hw =
2223                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2224         uint32_t reg;
2225
2226         /* CTRL_EXT: Extended VLAN */
2227         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2228         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2229         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2230
2231         /* Update maximum packet length */
2232         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2233                 E1000_WRITE_REG(hw, E1000_RLPML,
2234                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2235                                                 VLAN_TAG_SIZE);
2236 }
2237
2238 static void
2239 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2240 {
2241         struct e1000_hw *hw =
2242                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2243         uint32_t reg;
2244
2245         /* CTRL_EXT: Extended VLAN */
2246         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2247         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2248         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2249
2250         /* Update maximum packet length */
2251         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2252                 E1000_WRITE_REG(hw, E1000_RLPML,
2253                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2254                                                 2 * VLAN_TAG_SIZE);
2255 }
2256
2257 static void
2258 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2259 {
2260         if(mask & ETH_VLAN_STRIP_MASK){
2261                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2262                         igb_vlan_hw_strip_enable(dev);
2263                 else
2264                         igb_vlan_hw_strip_disable(dev);
2265         }
2266
2267         if(mask & ETH_VLAN_FILTER_MASK){
2268                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2269                         igb_vlan_hw_filter_enable(dev);
2270                 else
2271                         igb_vlan_hw_filter_disable(dev);
2272         }
2273
2274         if(mask & ETH_VLAN_EXTEND_MASK){
2275                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2276                         igb_vlan_hw_extend_enable(dev);
2277                 else
2278                         igb_vlan_hw_extend_disable(dev);
2279         }
2280 }
2281
2282
2283 /**
2284  * It enables the interrupt mask and then enable the interrupt.
2285  *
2286  * @param dev
2287  *  Pointer to struct rte_eth_dev.
2288  *
2289  * @return
2290  *  - On success, zero.
2291  *  - On failure, a negative value.
2292  */
2293 static int
2294 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2295 {
2296         struct e1000_interrupt *intr =
2297                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2298
2299         intr->mask |= E1000_ICR_LSC;
2300
2301         return 0;
2302 }
2303
2304 /* It clears the interrupt causes and enables the interrupt.
2305  * It will be called once only during nic initialized.
2306  *
2307  * @param dev
2308  *  Pointer to struct rte_eth_dev.
2309  *
2310  * @return
2311  *  - On success, zero.
2312  *  - On failure, a negative value.
2313  */
2314 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2315 {
2316         uint32_t mask, regval;
2317         struct e1000_hw *hw =
2318                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2319         struct rte_eth_dev_info dev_info;
2320
2321         memset(&dev_info, 0, sizeof(dev_info));
2322         eth_igb_infos_get(dev, &dev_info);
2323
2324         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2325         regval = E1000_READ_REG(hw, E1000_EIMS);
2326         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2327
2328         return 0;
2329 }
2330
2331 /*
2332  * It reads ICR and gets interrupt causes, check it and set a bit flag
2333  * to update link status.
2334  *
2335  * @param dev
2336  *  Pointer to struct rte_eth_dev.
2337  *
2338  * @return
2339  *  - On success, zero.
2340  *  - On failure, a negative value.
2341  */
2342 static int
2343 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2344 {
2345         uint32_t icr;
2346         struct e1000_hw *hw =
2347                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2348         struct e1000_interrupt *intr =
2349                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2350
2351         igb_intr_disable(hw);
2352
2353         /* read-on-clear nic registers here */
2354         icr = E1000_READ_REG(hw, E1000_ICR);
2355
2356         intr->flags = 0;
2357         if (icr & E1000_ICR_LSC) {
2358                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2359         }
2360
2361         if (icr & E1000_ICR_VMMB)
2362                 intr->flags |= E1000_FLAG_MAILBOX;
2363
2364         return 0;
2365 }
2366
2367 /*
2368  * It executes link_update after knowing an interrupt is prsent.
2369  *
2370  * @param dev
2371  *  Pointer to struct rte_eth_dev.
2372  *
2373  * @return
2374  *  - On success, zero.
2375  *  - On failure, a negative value.
2376  */
2377 static int
2378 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2379 {
2380         struct e1000_hw *hw =
2381                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2382         struct e1000_interrupt *intr =
2383                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2384         uint32_t tctl, rctl;
2385         struct rte_eth_link link;
2386         int ret;
2387
2388         if (intr->flags & E1000_FLAG_MAILBOX) {
2389                 igb_pf_mbx_process(dev);
2390                 intr->flags &= ~E1000_FLAG_MAILBOX;
2391         }
2392
2393         igb_intr_enable(dev);
2394         rte_intr_enable(&(dev->pci_dev->intr_handle));
2395
2396         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2397                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2398
2399                 /* set get_link_status to check register later */
2400                 hw->mac.get_link_status = 1;
2401                 ret = eth_igb_link_update(dev, 0);
2402
2403                 /* check if link has changed */
2404                 if (ret < 0)
2405                         return 0;
2406
2407                 memset(&link, 0, sizeof(link));
2408                 rte_igb_dev_atomic_read_link_status(dev, &link);
2409                 if (link.link_status) {
2410                         PMD_INIT_LOG(INFO,
2411                                      " Port %d: Link Up - speed %u Mbps - %s",
2412                                      dev->data->port_id,
2413                                      (unsigned)link.link_speed,
2414                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2415                                      "full-duplex" : "half-duplex");
2416                 } else {
2417                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2418                                      dev->data->port_id);
2419                 }
2420
2421                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2422                              dev->pci_dev->addr.domain,
2423                              dev->pci_dev->addr.bus,
2424                              dev->pci_dev->addr.devid,
2425                              dev->pci_dev->addr.function);
2426                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2427                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2428                 if (link.link_status) {
2429                         /* enable Tx/Rx */
2430                         tctl |= E1000_TCTL_EN;
2431                         rctl |= E1000_RCTL_EN;
2432                 } else {
2433                         /* disable Tx/Rx */
2434                         tctl &= ~E1000_TCTL_EN;
2435                         rctl &= ~E1000_RCTL_EN;
2436                 }
2437                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2438                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2439                 E1000_WRITE_FLUSH(hw);
2440                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2441         }
2442
2443         return 0;
2444 }
2445
2446 /**
2447  * Interrupt handler which shall be registered at first.
2448  *
2449  * @param handle
2450  *  Pointer to interrupt handle.
2451  * @param param
2452  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2453  *
2454  * @return
2455  *  void
2456  */
2457 static void
2458 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2459                                                         void *param)
2460 {
2461         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2462
2463         eth_igb_interrupt_get_status(dev);
2464         eth_igb_interrupt_action(dev);
2465 }
2466
2467 static int
2468 eth_igb_led_on(struct rte_eth_dev *dev)
2469 {
2470         struct e1000_hw *hw;
2471
2472         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2473         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2474 }
2475
2476 static int
2477 eth_igb_led_off(struct rte_eth_dev *dev)
2478 {
2479         struct e1000_hw *hw;
2480
2481         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2482         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2483 }
2484
2485 static int
2486 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2487 {
2488         struct e1000_hw *hw;
2489         uint32_t ctrl;
2490         int tx_pause;
2491         int rx_pause;
2492
2493         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2494         fc_conf->pause_time = hw->fc.pause_time;
2495         fc_conf->high_water = hw->fc.high_water;
2496         fc_conf->low_water = hw->fc.low_water;
2497         fc_conf->send_xon = hw->fc.send_xon;
2498         fc_conf->autoneg = hw->mac.autoneg;
2499
2500         /*
2501          * Return rx_pause and tx_pause status according to actual setting of
2502          * the TFCE and RFCE bits in the CTRL register.
2503          */
2504         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2505         if (ctrl & E1000_CTRL_TFCE)
2506                 tx_pause = 1;
2507         else
2508                 tx_pause = 0;
2509
2510         if (ctrl & E1000_CTRL_RFCE)
2511                 rx_pause = 1;
2512         else
2513                 rx_pause = 0;
2514
2515         if (rx_pause && tx_pause)
2516                 fc_conf->mode = RTE_FC_FULL;
2517         else if (rx_pause)
2518                 fc_conf->mode = RTE_FC_RX_PAUSE;
2519         else if (tx_pause)
2520                 fc_conf->mode = RTE_FC_TX_PAUSE;
2521         else
2522                 fc_conf->mode = RTE_FC_NONE;
2523
2524         return 0;
2525 }
2526
2527 static int
2528 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2529 {
2530         struct e1000_hw *hw;
2531         int err;
2532         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2533                 e1000_fc_none,
2534                 e1000_fc_rx_pause,
2535                 e1000_fc_tx_pause,
2536                 e1000_fc_full
2537         };
2538         uint32_t rx_buf_size;
2539         uint32_t max_high_water;
2540         uint32_t rctl;
2541
2542         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2543         if (fc_conf->autoneg != hw->mac.autoneg)
2544                 return -ENOTSUP;
2545         rx_buf_size = igb_get_rx_buffer_size(hw);
2546         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2547
2548         /* At least reserve one Ethernet frame for watermark */
2549         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2550         if ((fc_conf->high_water > max_high_water) ||
2551             (fc_conf->high_water < fc_conf->low_water)) {
2552                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2553                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2554                 return (-EINVAL);
2555         }
2556
2557         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2558         hw->fc.pause_time     = fc_conf->pause_time;
2559         hw->fc.high_water     = fc_conf->high_water;
2560         hw->fc.low_water      = fc_conf->low_water;
2561         hw->fc.send_xon       = fc_conf->send_xon;
2562
2563         err = e1000_setup_link_generic(hw);
2564         if (err == E1000_SUCCESS) {
2565
2566                 /* check if we want to forward MAC frames - driver doesn't have native
2567                  * capability to do that, so we'll write the registers ourselves */
2568
2569                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2570
2571                 /* set or clear MFLCN.PMCF bit depending on configuration */
2572                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2573                         rctl |= E1000_RCTL_PMCF;
2574                 else
2575                         rctl &= ~E1000_RCTL_PMCF;
2576
2577                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2578                 E1000_WRITE_FLUSH(hw);
2579
2580                 return 0;
2581         }
2582
2583         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2584         return (-EIO);
2585 }
2586
2587 #define E1000_RAH_POOLSEL_SHIFT      (18)
2588 static void
2589 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2590                 uint32_t index, __rte_unused uint32_t pool)
2591 {
2592         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2593         uint32_t rah;
2594
2595         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2596         rah = E1000_READ_REG(hw, E1000_RAH(index));
2597         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2598         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2599 }
2600
2601 static void
2602 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2603 {
2604         uint8_t addr[ETHER_ADDR_LEN];
2605         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2606
2607         memset(addr, 0, sizeof(addr));
2608
2609         e1000_rar_set(hw, addr, index);
2610 }
2611
2612 static void
2613 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2614                                 struct ether_addr *addr)
2615 {
2616         eth_igb_rar_clear(dev, 0);
2617
2618         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2619 }
2620 /*
2621  * Virtual Function operations
2622  */
2623 static void
2624 igbvf_intr_disable(struct e1000_hw *hw)
2625 {
2626         PMD_INIT_FUNC_TRACE();
2627
2628         /* Clear interrupt mask to stop from interrupts being generated */
2629         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2630
2631         E1000_WRITE_FLUSH(hw);
2632 }
2633
2634 static void
2635 igbvf_stop_adapter(struct rte_eth_dev *dev)
2636 {
2637         u32 reg_val;
2638         u16 i;
2639         struct rte_eth_dev_info dev_info;
2640         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2641
2642         memset(&dev_info, 0, sizeof(dev_info));
2643         eth_igbvf_infos_get(dev, &dev_info);
2644
2645         /* Clear interrupt mask to stop from interrupts being generated */
2646         igbvf_intr_disable(hw);
2647
2648         /* Clear any pending interrupts, flush previous writes */
2649         E1000_READ_REG(hw, E1000_EICR);
2650
2651         /* Disable the transmit unit.  Each queue must be disabled. */
2652         for (i = 0; i < dev_info.max_tx_queues; i++)
2653                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2654
2655         /* Disable the receive unit by stopping each queue */
2656         for (i = 0; i < dev_info.max_rx_queues; i++) {
2657                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2658                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2659                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2660                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2661                         ;
2662         }
2663
2664         /* flush all queues disables */
2665         E1000_WRITE_FLUSH(hw);
2666         msec_delay(2);
2667 }
2668
2669 static int eth_igbvf_link_update(struct e1000_hw *hw)
2670 {
2671         struct e1000_mbx_info *mbx = &hw->mbx;
2672         struct e1000_mac_info *mac = &hw->mac;
2673         int ret_val = E1000_SUCCESS;
2674
2675         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2676
2677         /*
2678          * We only want to run this if there has been a rst asserted.
2679          * in this case that could mean a link change, device reset,
2680          * or a virtual function reset
2681          */
2682
2683         /* If we were hit with a reset or timeout drop the link */
2684         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2685                 mac->get_link_status = TRUE;
2686
2687         if (!mac->get_link_status)
2688                 goto out;
2689
2690         /* if link status is down no point in checking to see if pf is up */
2691         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2692                 goto out;
2693
2694         /* if we passed all the tests above then the link is up and we no
2695          * longer need to check for link */
2696         mac->get_link_status = FALSE;
2697
2698 out:
2699         return ret_val;
2700 }
2701
2702
2703 static int
2704 igbvf_dev_configure(struct rte_eth_dev *dev)
2705 {
2706         struct rte_eth_conf* conf = &dev->data->dev_conf;
2707
2708         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2709                      dev->data->port_id);
2710
2711         /*
2712          * VF has no ability to enable/disable HW CRC
2713          * Keep the persistent behavior the same as Host PF
2714          */
2715 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2716         if (!conf->rxmode.hw_strip_crc) {
2717                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2718                 conf->rxmode.hw_strip_crc = 1;
2719         }
2720 #else
2721         if (conf->rxmode.hw_strip_crc) {
2722                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2723                 conf->rxmode.hw_strip_crc = 0;
2724         }
2725 #endif
2726
2727         return 0;
2728 }
2729
2730 static int
2731 igbvf_dev_start(struct rte_eth_dev *dev)
2732 {
2733         struct e1000_hw *hw =
2734                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2735         struct e1000_adapter *adapter =
2736                 E1000_DEV_PRIVATE(dev->data->dev_private);
2737         int ret;
2738
2739         PMD_INIT_FUNC_TRACE();
2740
2741         hw->mac.ops.reset_hw(hw);
2742         adapter->stopped = 0;
2743
2744         /* Set all vfta */
2745         igbvf_set_vfta_all(dev,1);
2746
2747         eth_igbvf_tx_init(dev);
2748
2749         /* This can fail when allocating mbufs for descriptor rings */
2750         ret = eth_igbvf_rx_init(dev);
2751         if (ret) {
2752                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2753                 igb_dev_clear_queues(dev);
2754                 return ret;
2755         }
2756
2757         return 0;
2758 }
2759
2760 static void
2761 igbvf_dev_stop(struct rte_eth_dev *dev)
2762 {
2763         PMD_INIT_FUNC_TRACE();
2764
2765         igbvf_stop_adapter(dev);
2766
2767         /*
2768           * Clear what we set, but we still keep shadow_vfta to
2769           * restore after device starts
2770           */
2771         igbvf_set_vfta_all(dev,0);
2772
2773         igb_dev_clear_queues(dev);
2774 }
2775
2776 static void
2777 igbvf_dev_close(struct rte_eth_dev *dev)
2778 {
2779         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2780         struct e1000_adapter *adapter =
2781                 E1000_DEV_PRIVATE(dev->data->dev_private);
2782
2783         PMD_INIT_FUNC_TRACE();
2784
2785         e1000_reset_hw(hw);
2786
2787         igbvf_dev_stop(dev);
2788         adapter->stopped = 1;
2789         igb_dev_free_queues(dev);
2790 }
2791
2792 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2793 {
2794         struct e1000_mbx_info *mbx = &hw->mbx;
2795         uint32_t msgbuf[2];
2796
2797         /* After set vlan, vlan strip will also be enabled in igb driver*/
2798         msgbuf[0] = E1000_VF_SET_VLAN;
2799         msgbuf[1] = vid;
2800         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2801         if (on)
2802                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2803
2804         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2805 }
2806
2807 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2808 {
2809         struct e1000_hw *hw =
2810                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2811         struct e1000_vfta * shadow_vfta =
2812                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2813         int i = 0, j = 0, vfta = 0, mask = 1;
2814
2815         for (i = 0; i < IGB_VFTA_SIZE; i++){
2816                 vfta = shadow_vfta->vfta[i];
2817                 if(vfta){
2818                         mask = 1;
2819                         for (j = 0; j < 32; j++){
2820                                 if(vfta & mask)
2821                                         igbvf_set_vfta(hw,
2822                                                 (uint16_t)((i<<5)+j), on);
2823                                 mask<<=1;
2824                         }
2825                 }
2826         }
2827
2828 }
2829
2830 static int
2831 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2832 {
2833         struct e1000_hw *hw =
2834                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2835         struct e1000_vfta * shadow_vfta =
2836                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2837         uint32_t vid_idx = 0;
2838         uint32_t vid_bit = 0;
2839         int ret = 0;
2840
2841         PMD_INIT_FUNC_TRACE();
2842
2843         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2844         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2845         if(ret){
2846                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2847                 return ret;
2848         }
2849         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2850         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2851
2852         /*Save what we set and retore it after device reset*/
2853         if (on)
2854                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2855         else
2856                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2857
2858         return 0;
2859 }
2860
2861 static void
2862 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
2863 {
2864         struct e1000_hw *hw =
2865                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2866
2867         /* index is not used by rar_set() */
2868         hw->mac.ops.rar_set(hw, (void *)addr, 0);
2869 }
2870
2871
2872 static int
2873 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2874                         struct rte_eth_rss_reta_entry64 *reta_conf,
2875                         uint16_t reta_size)
2876 {
2877         uint8_t i, j, mask;
2878         uint32_t reta, r;
2879         uint16_t idx, shift;
2880         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2881
2882         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2883                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2884                         "(%d) doesn't match the number hardware can supported "
2885                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2886                 return -EINVAL;
2887         }
2888
2889         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2890                 idx = i / RTE_RETA_GROUP_SIZE;
2891                 shift = i % RTE_RETA_GROUP_SIZE;
2892                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2893                                                 IGB_4_BIT_MASK);
2894                 if (!mask)
2895                         continue;
2896                 if (mask == IGB_4_BIT_MASK)
2897                         r = 0;
2898                 else
2899                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2900                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2901                         if (mask & (0x1 << j))
2902                                 reta |= reta_conf[idx].reta[shift + j] <<
2903                                                         (CHAR_BIT * j);
2904                         else
2905                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2906                 }
2907                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2908         }
2909
2910         return 0;
2911 }
2912
2913 static int
2914 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2915                        struct rte_eth_rss_reta_entry64 *reta_conf,
2916                        uint16_t reta_size)
2917 {
2918         uint8_t i, j, mask;
2919         uint32_t reta;
2920         uint16_t idx, shift;
2921         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2922
2923         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2924                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2925                         "(%d) doesn't match the number hardware can supported "
2926                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2927                 return -EINVAL;
2928         }
2929
2930         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2931                 idx = i / RTE_RETA_GROUP_SIZE;
2932                 shift = i % RTE_RETA_GROUP_SIZE;
2933                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2934                                                 IGB_4_BIT_MASK);
2935                 if (!mask)
2936                         continue;
2937                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2938                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2939                         if (mask & (0x1 << j))
2940                                 reta_conf[idx].reta[shift + j] =
2941                                         ((reta >> (CHAR_BIT * j)) &
2942                                                 IGB_8_BIT_MASK);
2943                 }
2944         }
2945
2946         return 0;
2947 }
2948
2949 #define MAC_TYPE_FILTER_SUP(type)    do {\
2950         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2951                 (type) != e1000_82576)\
2952                 return -ENOTSUP;\
2953 } while (0)
2954
2955 static int
2956 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2957                         struct rte_eth_syn_filter *filter,
2958                         bool add)
2959 {
2960         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2961         uint32_t synqf, rfctl;
2962
2963         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2964                 return -EINVAL;
2965
2966         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2967
2968         if (add) {
2969                 if (synqf & E1000_SYN_FILTER_ENABLE)
2970                         return -EINVAL;
2971
2972                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2973                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2974
2975                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2976                 if (filter->hig_pri)
2977                         rfctl |= E1000_RFCTL_SYNQFP;
2978                 else
2979                         rfctl &= ~E1000_RFCTL_SYNQFP;
2980
2981                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2982         } else {
2983                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
2984                         return -ENOENT;
2985                 synqf = 0;
2986         }
2987
2988         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2989         E1000_WRITE_FLUSH(hw);
2990         return 0;
2991 }
2992
2993 static int
2994 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
2995                         struct rte_eth_syn_filter *filter)
2996 {
2997         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2998         uint32_t synqf, rfctl;
2999
3000         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3001         if (synqf & E1000_SYN_FILTER_ENABLE) {
3002                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3003                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3004                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3005                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3006                 return 0;
3007         }
3008
3009         return -ENOENT;
3010 }
3011
3012 static int
3013 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3014                         enum rte_filter_op filter_op,
3015                         void *arg)
3016 {
3017         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3018         int ret;
3019
3020         MAC_TYPE_FILTER_SUP(hw->mac.type);
3021
3022         if (filter_op == RTE_ETH_FILTER_NOP)
3023                 return 0;
3024
3025         if (arg == NULL) {
3026                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3027                             filter_op);
3028                 return -EINVAL;
3029         }
3030
3031         switch (filter_op) {
3032         case RTE_ETH_FILTER_ADD:
3033                 ret = eth_igb_syn_filter_set(dev,
3034                                 (struct rte_eth_syn_filter *)arg,
3035                                 TRUE);
3036                 break;
3037         case RTE_ETH_FILTER_DELETE:
3038                 ret = eth_igb_syn_filter_set(dev,
3039                                 (struct rte_eth_syn_filter *)arg,
3040                                 FALSE);
3041                 break;
3042         case RTE_ETH_FILTER_GET:
3043                 ret = eth_igb_syn_filter_get(dev,
3044                                 (struct rte_eth_syn_filter *)arg);
3045                 break;
3046         default:
3047                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3048                 ret = -EINVAL;
3049                 break;
3050         }
3051
3052         return ret;
3053 }
3054
3055 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3056         if ((type) != e1000_82580 && (type) != e1000_i350)\
3057                 return -ENOSYS; \
3058 } while (0)
3059
3060 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3061 static inline int
3062 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3063                         struct e1000_2tuple_filter_info *filter_info)
3064 {
3065         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3066                 return -EINVAL;
3067         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3068                 return -EINVAL;  /* filter index is out of range. */
3069         if (filter->tcp_flags > TCP_FLAG_ALL)
3070                 return -EINVAL;  /* flags is invalid. */
3071
3072         switch (filter->dst_port_mask) {
3073         case UINT16_MAX:
3074                 filter_info->dst_port_mask = 0;
3075                 filter_info->dst_port = filter->dst_port;
3076                 break;
3077         case 0:
3078                 filter_info->dst_port_mask = 1;
3079                 break;
3080         default:
3081                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3082                 return -EINVAL;
3083         }
3084
3085         switch (filter->proto_mask) {
3086         case UINT8_MAX:
3087                 filter_info->proto_mask = 0;
3088                 filter_info->proto = filter->proto;
3089                 break;
3090         case 0:
3091                 filter_info->proto_mask = 1;
3092                 break;
3093         default:
3094                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3095                 return -EINVAL;
3096         }
3097
3098         filter_info->priority = (uint8_t)filter->priority;
3099         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3100                 filter_info->tcp_flags = filter->tcp_flags;
3101         else
3102                 filter_info->tcp_flags = 0;
3103
3104         return 0;
3105 }
3106
3107 static inline struct e1000_2tuple_filter *
3108 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3109                         struct e1000_2tuple_filter_info *key)
3110 {
3111         struct e1000_2tuple_filter *it;
3112
3113         TAILQ_FOREACH(it, filter_list, entries) {
3114                 if (memcmp(key, &it->filter_info,
3115                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3116                         return it;
3117                 }
3118         }
3119         return NULL;
3120 }
3121
3122 /*
3123  * igb_add_2tuple_filter - add a 2tuple filter
3124  *
3125  * @param
3126  * dev: Pointer to struct rte_eth_dev.
3127  * ntuple_filter: ponter to the filter that will be added.
3128  *
3129  * @return
3130  *    - On success, zero.
3131  *    - On failure, a negative value.
3132  */
3133 static int
3134 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3135                         struct rte_eth_ntuple_filter *ntuple_filter)
3136 {
3137         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3138         struct e1000_filter_info *filter_info =
3139                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3140         struct e1000_2tuple_filter *filter;
3141         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3142         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3143         int i, ret;
3144
3145         filter = rte_zmalloc("e1000_2tuple_filter",
3146                         sizeof(struct e1000_2tuple_filter), 0);
3147         if (filter == NULL)
3148                 return -ENOMEM;
3149
3150         ret = ntuple_filter_to_2tuple(ntuple_filter,
3151                                       &filter->filter_info);
3152         if (ret < 0) {
3153                 rte_free(filter);
3154                 return ret;
3155         }
3156         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3157                                          &filter->filter_info) != NULL) {
3158                 PMD_DRV_LOG(ERR, "filter exists.");
3159                 rte_free(filter);
3160                 return -EEXIST;
3161         }
3162         filter->queue = ntuple_filter->queue;
3163
3164         /*
3165          * look for an unused 2tuple filter index,
3166          * and insert the filter to list.
3167          */
3168         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3169                 if (!(filter_info->twotuple_mask & (1 << i))) {
3170                         filter_info->twotuple_mask |= 1 << i;
3171                         filter->index = i;
3172                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3173                                           filter,
3174                                           entries);
3175                         break;
3176                 }
3177         }
3178         if (i >= E1000_MAX_TTQF_FILTERS) {
3179                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3180                 rte_free(filter);
3181                 return -ENOSYS;
3182         }
3183
3184         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3185         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3186                 imir |= E1000_IMIR_PORT_BP;
3187         else
3188                 imir &= ~E1000_IMIR_PORT_BP;
3189
3190         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3191
3192         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3193         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3194         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3195         if (filter->filter_info.proto_mask == 0)
3196                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3197
3198         /* tcp flags bits setting. */
3199         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3200                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3201                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3202                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3203                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3204                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3205                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3206                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3207                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3208                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3209                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3210                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3211                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3212         } else
3213                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3214         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3215         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3216         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3217         return 0;
3218 }
3219
3220 /*
3221  * igb_remove_2tuple_filter - remove a 2tuple filter
3222  *
3223  * @param
3224  * dev: Pointer to struct rte_eth_dev.
3225  * ntuple_filter: ponter to the filter that will be removed.
3226  *
3227  * @return
3228  *    - On success, zero.
3229  *    - On failure, a negative value.
3230  */
3231 static int
3232 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3233                         struct rte_eth_ntuple_filter *ntuple_filter)
3234 {
3235         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3236         struct e1000_filter_info *filter_info =
3237                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3238         struct e1000_2tuple_filter_info filter_2tuple;
3239         struct e1000_2tuple_filter *filter;
3240         int ret;
3241
3242         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3243         ret = ntuple_filter_to_2tuple(ntuple_filter,
3244                                       &filter_2tuple);
3245         if (ret < 0)
3246                 return ret;
3247
3248         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3249                                          &filter_2tuple);
3250         if (filter == NULL) {
3251                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3252                 return -ENOENT;
3253         }
3254
3255         filter_info->twotuple_mask &= ~(1 << filter->index);
3256         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3257         rte_free(filter);
3258
3259         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3260         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3261         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3262         return 0;
3263 }
3264
3265 static inline struct e1000_flex_filter *
3266 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3267                         struct e1000_flex_filter_info *key)
3268 {
3269         struct e1000_flex_filter *it;
3270
3271         TAILQ_FOREACH(it, filter_list, entries) {
3272                 if (memcmp(key, &it->filter_info,
3273                         sizeof(struct e1000_flex_filter_info)) == 0)
3274                         return it;
3275         }
3276
3277         return NULL;
3278 }
3279
3280 static int
3281 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3282                         struct rte_eth_flex_filter *filter,
3283                         bool add)
3284 {
3285         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3286         struct e1000_filter_info *filter_info =
3287                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3288         struct e1000_flex_filter *flex_filter, *it;
3289         uint32_t wufc, queueing, mask;
3290         uint32_t reg_off;
3291         uint8_t shift, i, j = 0;
3292
3293         flex_filter = rte_zmalloc("e1000_flex_filter",
3294                         sizeof(struct e1000_flex_filter), 0);
3295         if (flex_filter == NULL)
3296                 return -ENOMEM;
3297
3298         flex_filter->filter_info.len = filter->len;
3299         flex_filter->filter_info.priority = filter->priority;
3300         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3301         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3302                 mask = 0;
3303                 /* reverse bits in flex filter's mask*/
3304                 for (shift = 0; shift < CHAR_BIT; shift++) {
3305                         if (filter->mask[i] & (0x01 << shift))
3306                                 mask |= (0x80 >> shift);
3307                 }
3308                 flex_filter->filter_info.mask[i] = mask;
3309         }
3310
3311         wufc = E1000_READ_REG(hw, E1000_WUFC);
3312         if (flex_filter->index < E1000_MAX_FHFT)
3313                 reg_off = E1000_FHFT(flex_filter->index);
3314         else
3315                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3316
3317         if (add) {
3318                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3319                                 &flex_filter->filter_info) != NULL) {
3320                         PMD_DRV_LOG(ERR, "filter exists.");
3321                         rte_free(flex_filter);
3322                         return -EEXIST;
3323                 }
3324                 flex_filter->queue = filter->queue;
3325                 /*
3326                  * look for an unused flex filter index
3327                  * and insert the filter into the list.
3328                  */
3329                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3330                         if (!(filter_info->flex_mask & (1 << i))) {
3331                                 filter_info->flex_mask |= 1 << i;
3332                                 flex_filter->index = i;
3333                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3334                                         flex_filter,
3335                                         entries);
3336                                 break;
3337                         }
3338                 }
3339                 if (i >= E1000_MAX_FLEX_FILTERS) {
3340                         PMD_DRV_LOG(ERR, "flex filters are full.");
3341                         rte_free(flex_filter);
3342                         return -ENOSYS;
3343                 }
3344
3345                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3346                                 (E1000_WUFC_FLX0 << flex_filter->index));
3347                 queueing = filter->len |
3348                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3349                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3350                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3351                                 queueing);
3352                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3353                         E1000_WRITE_REG(hw, reg_off,
3354                                         flex_filter->filter_info.dwords[j]);
3355                         reg_off += sizeof(uint32_t);
3356                         E1000_WRITE_REG(hw, reg_off,
3357                                         flex_filter->filter_info.dwords[++j]);
3358                         reg_off += sizeof(uint32_t);
3359                         E1000_WRITE_REG(hw, reg_off,
3360                                 (uint32_t)flex_filter->filter_info.mask[i]);
3361                         reg_off += sizeof(uint32_t) * 2;
3362                         ++j;
3363                 }
3364         } else {
3365                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3366                                 &flex_filter->filter_info);
3367                 if (it == NULL) {
3368                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3369                         rte_free(flex_filter);
3370                         return -ENOENT;
3371                 }
3372
3373                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3374                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3375                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3376                         (~(E1000_WUFC_FLX0 << it->index)));
3377
3378                 filter_info->flex_mask &= ~(1 << it->index);
3379                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3380                 rte_free(it);
3381                 rte_free(flex_filter);
3382         }
3383
3384         return 0;
3385 }
3386
3387 static int
3388 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3389                         struct rte_eth_flex_filter *filter)
3390 {
3391         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3392         struct e1000_filter_info *filter_info =
3393                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3394         struct e1000_flex_filter flex_filter, *it;
3395         uint32_t wufc, queueing, wufc_en = 0;
3396
3397         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3398         flex_filter.filter_info.len = filter->len;
3399         flex_filter.filter_info.priority = filter->priority;
3400         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3401         memcpy(flex_filter.filter_info.mask, filter->mask,
3402                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3403
3404         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3405                                 &flex_filter.filter_info);
3406         if (it == NULL) {
3407                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3408                 return -ENOENT;
3409         }
3410
3411         wufc = E1000_READ_REG(hw, E1000_WUFC);
3412         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3413
3414         if ((wufc & wufc_en) == wufc_en) {
3415                 uint32_t reg_off = 0;
3416                 if (it->index < E1000_MAX_FHFT)
3417                         reg_off = E1000_FHFT(it->index);
3418                 else
3419                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3420
3421                 queueing = E1000_READ_REG(hw,
3422                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3423                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3424                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3425                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3426                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3427                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3428                 return 0;
3429         }
3430         return -ENOENT;
3431 }
3432
3433 static int
3434 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3435                         enum rte_filter_op filter_op,
3436                         void *arg)
3437 {
3438         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3439         struct rte_eth_flex_filter *filter;
3440         int ret = 0;
3441
3442         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3443
3444         if (filter_op == RTE_ETH_FILTER_NOP)
3445                 return ret;
3446
3447         if (arg == NULL) {
3448                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3449                             filter_op);
3450                 return -EINVAL;
3451         }
3452
3453         filter = (struct rte_eth_flex_filter *)arg;
3454         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3455             || filter->len % sizeof(uint64_t) != 0) {
3456                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3457                 return -EINVAL;
3458         }
3459         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3460                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3461                 return -EINVAL;
3462         }
3463
3464         switch (filter_op) {
3465         case RTE_ETH_FILTER_ADD:
3466                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3467                 break;
3468         case RTE_ETH_FILTER_DELETE:
3469                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3470                 break;
3471         case RTE_ETH_FILTER_GET:
3472                 ret = eth_igb_get_flex_filter(dev, filter);
3473                 break;
3474         default:
3475                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3476                 ret = -EINVAL;
3477                 break;
3478         }
3479
3480         return ret;
3481 }
3482
3483 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3484 static inline int
3485 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3486                         struct e1000_5tuple_filter_info *filter_info)
3487 {
3488         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3489                 return -EINVAL;
3490         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3491                 return -EINVAL;  /* filter index is out of range. */
3492         if (filter->tcp_flags > TCP_FLAG_ALL)
3493                 return -EINVAL;  /* flags is invalid. */
3494
3495         switch (filter->dst_ip_mask) {
3496         case UINT32_MAX:
3497                 filter_info->dst_ip_mask = 0;
3498                 filter_info->dst_ip = filter->dst_ip;
3499                 break;
3500         case 0:
3501                 filter_info->dst_ip_mask = 1;
3502                 break;
3503         default:
3504                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3505                 return -EINVAL;
3506         }
3507
3508         switch (filter->src_ip_mask) {
3509         case UINT32_MAX:
3510                 filter_info->src_ip_mask = 0;
3511                 filter_info->src_ip = filter->src_ip;
3512                 break;
3513         case 0:
3514                 filter_info->src_ip_mask = 1;
3515                 break;
3516         default:
3517                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3518                 return -EINVAL;
3519         }
3520
3521         switch (filter->dst_port_mask) {
3522         case UINT16_MAX:
3523                 filter_info->dst_port_mask = 0;
3524                 filter_info->dst_port = filter->dst_port;
3525                 break;
3526         case 0:
3527                 filter_info->dst_port_mask = 1;
3528                 break;
3529         default:
3530                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3531                 return -EINVAL;
3532         }
3533
3534         switch (filter->src_port_mask) {
3535         case UINT16_MAX:
3536                 filter_info->src_port_mask = 0;
3537                 filter_info->src_port = filter->src_port;
3538                 break;
3539         case 0:
3540                 filter_info->src_port_mask = 1;
3541                 break;
3542         default:
3543                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3544                 return -EINVAL;
3545         }
3546
3547         switch (filter->proto_mask) {
3548         case UINT8_MAX:
3549                 filter_info->proto_mask = 0;
3550                 filter_info->proto = filter->proto;
3551                 break;
3552         case 0:
3553                 filter_info->proto_mask = 1;
3554                 break;
3555         default:
3556                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3557                 return -EINVAL;
3558         }
3559
3560         filter_info->priority = (uint8_t)filter->priority;
3561         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3562                 filter_info->tcp_flags = filter->tcp_flags;
3563         else
3564                 filter_info->tcp_flags = 0;
3565
3566         return 0;
3567 }
3568
3569 static inline struct e1000_5tuple_filter *
3570 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3571                         struct e1000_5tuple_filter_info *key)
3572 {
3573         struct e1000_5tuple_filter *it;
3574
3575         TAILQ_FOREACH(it, filter_list, entries) {
3576                 if (memcmp(key, &it->filter_info,
3577                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3578                         return it;
3579                 }
3580         }
3581         return NULL;
3582 }
3583
3584 /*
3585  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3586  *
3587  * @param
3588  * dev: Pointer to struct rte_eth_dev.
3589  * ntuple_filter: ponter to the filter that will be added.
3590  *
3591  * @return
3592  *    - On success, zero.
3593  *    - On failure, a negative value.
3594  */
3595 static int
3596 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3597                         struct rte_eth_ntuple_filter *ntuple_filter)
3598 {
3599         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3600         struct e1000_filter_info *filter_info =
3601                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3602         struct e1000_5tuple_filter *filter;
3603         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3604         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3605         uint8_t i;
3606         int ret;
3607
3608         filter = rte_zmalloc("e1000_5tuple_filter",
3609                         sizeof(struct e1000_5tuple_filter), 0);
3610         if (filter == NULL)
3611                 return -ENOMEM;
3612
3613         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3614                                             &filter->filter_info);
3615         if (ret < 0) {
3616                 rte_free(filter);
3617                 return ret;
3618         }
3619
3620         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3621                                          &filter->filter_info) != NULL) {
3622                 PMD_DRV_LOG(ERR, "filter exists.");
3623                 rte_free(filter);
3624                 return -EEXIST;
3625         }
3626         filter->queue = ntuple_filter->queue;
3627
3628         /*
3629          * look for an unused 5tuple filter index,
3630          * and insert the filter to list.
3631          */
3632         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3633                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3634                         filter_info->fivetuple_mask |= 1 << i;
3635                         filter->index = i;
3636                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3637                                           filter,
3638                                           entries);
3639                         break;
3640                 }
3641         }
3642         if (i >= E1000_MAX_FTQF_FILTERS) {
3643                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3644                 rte_free(filter);
3645                 return -ENOSYS;
3646         }
3647
3648         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3649         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3650                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3651         if (filter->filter_info.dst_ip_mask == 0)
3652                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3653         if (filter->filter_info.src_port_mask == 0)
3654                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3655         if (filter->filter_info.proto_mask == 0)
3656                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3657         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3658                 E1000_FTQF_QUEUE_MASK;
3659         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3660         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3661         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3662         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3663
3664         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3665         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3666
3667         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3668         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3669                 imir |= E1000_IMIR_PORT_BP;
3670         else
3671                 imir &= ~E1000_IMIR_PORT_BP;
3672         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3673
3674         /* tcp flags bits setting. */
3675         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3676                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3677                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3678                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3679                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3680                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3681                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3682                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3683                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3684                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3685                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3686                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3687                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3688         } else
3689                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3690         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3691         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3692         return 0;
3693 }
3694
3695 /*
3696  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3697  *
3698  * @param
3699  * dev: Pointer to struct rte_eth_dev.
3700  * ntuple_filter: ponter to the filter that will be removed.
3701  *
3702  * @return
3703  *    - On success, zero.
3704  *    - On failure, a negative value.
3705  */
3706 static int
3707 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3708                                 struct rte_eth_ntuple_filter *ntuple_filter)
3709 {
3710         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3711         struct e1000_filter_info *filter_info =
3712                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3713         struct e1000_5tuple_filter_info filter_5tuple;
3714         struct e1000_5tuple_filter *filter;
3715         int ret;
3716
3717         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3718         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3719                                             &filter_5tuple);
3720         if (ret < 0)
3721                 return ret;
3722
3723         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3724                                          &filter_5tuple);
3725         if (filter == NULL) {
3726                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3727                 return -ENOENT;
3728         }
3729
3730         filter_info->fivetuple_mask &= ~(1 << filter->index);
3731         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3732         rte_free(filter);
3733
3734         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3735                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3736         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3737         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3738         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3739         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3740         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3741         return 0;
3742 }
3743
3744 static int
3745 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3746 {
3747         uint32_t rctl;
3748         struct e1000_hw *hw;
3749         struct rte_eth_dev_info dev_info;
3750         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3751                                      VLAN_TAG_SIZE);
3752
3753         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3754
3755 #ifdef RTE_LIBRTE_82571_SUPPORT
3756         /* XXX: not bigger than max_rx_pktlen */
3757         if (hw->mac.type == e1000_82571)
3758                 return -ENOTSUP;
3759 #endif
3760         eth_igb_infos_get(dev, &dev_info);
3761
3762         /* check that mtu is within the allowed range */
3763         if ((mtu < ETHER_MIN_MTU) ||
3764             (frame_size > dev_info.max_rx_pktlen))
3765                 return -EINVAL;
3766
3767         /* refuse mtu that requires the support of scattered packets when this
3768          * feature has not been enabled before. */
3769         if (!dev->data->scattered_rx &&
3770             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3771                 return -EINVAL;
3772
3773         rctl = E1000_READ_REG(hw, E1000_RCTL);
3774
3775         /* switch to jumbo mode if needed */
3776         if (frame_size > ETHER_MAX_LEN) {
3777                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3778                 rctl |= E1000_RCTL_LPE;
3779         } else {
3780                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3781                 rctl &= ~E1000_RCTL_LPE;
3782         }
3783         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3784
3785         /* update max frame size */
3786         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3787
3788         E1000_WRITE_REG(hw, E1000_RLPML,
3789                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3790
3791         return 0;
3792 }
3793
3794 /*
3795  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3796  *
3797  * @param
3798  * dev: Pointer to struct rte_eth_dev.
3799  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3800  * add: if true, add filter, if false, remove filter
3801  *
3802  * @return
3803  *    - On success, zero.
3804  *    - On failure, a negative value.
3805  */
3806 static int
3807 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3808                         struct rte_eth_ntuple_filter *ntuple_filter,
3809                         bool add)
3810 {
3811         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3812         int ret;
3813
3814         switch (ntuple_filter->flags) {
3815         case RTE_5TUPLE_FLAGS:
3816         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3817                 if (hw->mac.type != e1000_82576)
3818                         return -ENOTSUP;
3819                 if (add)
3820                         ret = igb_add_5tuple_filter_82576(dev,
3821                                                           ntuple_filter);
3822                 else
3823                         ret = igb_remove_5tuple_filter_82576(dev,
3824                                                              ntuple_filter);
3825                 break;
3826         case RTE_2TUPLE_FLAGS:
3827         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3828                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3829                         return -ENOTSUP;
3830                 if (add)
3831                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3832                 else
3833                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3834                 break;
3835         default:
3836                 ret = -EINVAL;
3837                 break;
3838         }
3839
3840         return ret;
3841 }
3842
3843 /*
3844  * igb_get_ntuple_filter - get a ntuple filter
3845  *
3846  * @param
3847  * dev: Pointer to struct rte_eth_dev.
3848  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3849  *
3850  * @return
3851  *    - On success, zero.
3852  *    - On failure, a negative value.
3853  */
3854 static int
3855 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3856                         struct rte_eth_ntuple_filter *ntuple_filter)
3857 {
3858         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3859         struct e1000_filter_info *filter_info =
3860                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3861         struct e1000_5tuple_filter_info filter_5tuple;
3862         struct e1000_2tuple_filter_info filter_2tuple;
3863         struct e1000_5tuple_filter *p_5tuple_filter;
3864         struct e1000_2tuple_filter *p_2tuple_filter;
3865         int ret;
3866
3867         switch (ntuple_filter->flags) {
3868         case RTE_5TUPLE_FLAGS:
3869         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3870                 if (hw->mac.type != e1000_82576)
3871                         return -ENOTSUP;
3872                 memset(&filter_5tuple,
3873                         0,
3874                         sizeof(struct e1000_5tuple_filter_info));
3875                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3876                                                     &filter_5tuple);
3877                 if (ret < 0)
3878                         return ret;
3879                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3880                                         &filter_info->fivetuple_list,
3881                                         &filter_5tuple);
3882                 if (p_5tuple_filter == NULL) {
3883                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3884                         return -ENOENT;
3885                 }
3886                 ntuple_filter->queue = p_5tuple_filter->queue;
3887                 break;
3888         case RTE_2TUPLE_FLAGS:
3889         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3890                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3891                         return -ENOTSUP;
3892                 memset(&filter_2tuple,
3893                         0,
3894                         sizeof(struct e1000_2tuple_filter_info));
3895                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3896                 if (ret < 0)
3897                         return ret;
3898                 p_2tuple_filter = igb_2tuple_filter_lookup(
3899                                         &filter_info->twotuple_list,
3900                                         &filter_2tuple);
3901                 if (p_2tuple_filter == NULL) {
3902                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3903                         return -ENOENT;
3904                 }
3905                 ntuple_filter->queue = p_2tuple_filter->queue;
3906                 break;
3907         default:
3908                 ret = -EINVAL;
3909                 break;
3910         }
3911
3912         return 0;
3913 }
3914
3915 /*
3916  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3917  * @dev: pointer to rte_eth_dev structure
3918  * @filter_op:operation will be taken.
3919  * @arg: a pointer to specific structure corresponding to the filter_op
3920  */
3921 static int
3922 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3923                                 enum rte_filter_op filter_op,
3924                                 void *arg)
3925 {
3926         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3927         int ret;
3928
3929         MAC_TYPE_FILTER_SUP(hw->mac.type);
3930
3931         if (filter_op == RTE_ETH_FILTER_NOP)
3932                 return 0;
3933
3934         if (arg == NULL) {
3935                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3936                             filter_op);
3937                 return -EINVAL;
3938         }
3939
3940         switch (filter_op) {
3941         case RTE_ETH_FILTER_ADD:
3942                 ret = igb_add_del_ntuple_filter(dev,
3943                         (struct rte_eth_ntuple_filter *)arg,
3944                         TRUE);
3945                 break;
3946         case RTE_ETH_FILTER_DELETE:
3947                 ret = igb_add_del_ntuple_filter(dev,
3948                         (struct rte_eth_ntuple_filter *)arg,
3949                         FALSE);
3950                 break;
3951         case RTE_ETH_FILTER_GET:
3952                 ret = igb_get_ntuple_filter(dev,
3953                         (struct rte_eth_ntuple_filter *)arg);
3954                 break;
3955         default:
3956                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3957                 ret = -EINVAL;
3958                 break;
3959         }
3960         return ret;
3961 }
3962
3963 static inline int
3964 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3965                         uint16_t ethertype)
3966 {
3967         int i;
3968
3969         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3970                 if (filter_info->ethertype_filters[i] == ethertype &&
3971                     (filter_info->ethertype_mask & (1 << i)))
3972                         return i;
3973         }
3974         return -1;
3975 }
3976
3977 static inline int
3978 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3979                         uint16_t ethertype)
3980 {
3981         int i;
3982
3983         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3984                 if (!(filter_info->ethertype_mask & (1 << i))) {
3985                         filter_info->ethertype_mask |= 1 << i;
3986                         filter_info->ethertype_filters[i] = ethertype;
3987                         return i;
3988                 }
3989         }
3990         return -1;
3991 }
3992
3993 static inline int
3994 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3995                         uint8_t idx)
3996 {
3997         if (idx >= E1000_MAX_ETQF_FILTERS)
3998                 return -1;
3999         filter_info->ethertype_mask &= ~(1 << idx);
4000         filter_info->ethertype_filters[idx] = 0;
4001         return idx;
4002 }
4003
4004
4005 static int
4006 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4007                         struct rte_eth_ethertype_filter *filter,
4008                         bool add)
4009 {
4010         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4011         struct e1000_filter_info *filter_info =
4012                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4013         uint32_t etqf = 0;
4014         int ret;
4015
4016         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4017                 filter->ether_type == ETHER_TYPE_IPv6) {
4018                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4019                         " ethertype filter.", filter->ether_type);
4020                 return -EINVAL;
4021         }
4022
4023         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4024                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4025                 return -EINVAL;
4026         }
4027         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4028                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4029                 return -EINVAL;
4030         }
4031
4032         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4033         if (ret >= 0 && add) {
4034                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4035                             filter->ether_type);
4036                 return -EEXIST;
4037         }
4038         if (ret < 0 && !add) {
4039                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4040                             filter->ether_type);
4041                 return -ENOENT;
4042         }
4043
4044         if (add) {
4045                 ret = igb_ethertype_filter_insert(filter_info,
4046                         filter->ether_type);
4047                 if (ret < 0) {
4048                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4049                         return -ENOSYS;
4050                 }
4051
4052                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4053                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4054                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4055         } else {
4056                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4057                 if (ret < 0)
4058                         return -ENOSYS;
4059         }
4060         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4061         E1000_WRITE_FLUSH(hw);
4062
4063         return 0;
4064 }
4065
4066 static int
4067 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4068                         struct rte_eth_ethertype_filter *filter)
4069 {
4070         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4071         struct e1000_filter_info *filter_info =
4072                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4073         uint32_t etqf;
4074         int ret;
4075
4076         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4077         if (ret < 0) {
4078                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4079                             filter->ether_type);
4080                 return -ENOENT;
4081         }
4082
4083         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4084         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4085                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4086                 filter->flags = 0;
4087                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4088                                 E1000_ETQF_QUEUE_SHIFT;
4089                 return 0;
4090         }
4091
4092         return -ENOENT;
4093 }
4094
4095 /*
4096  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4097  * @dev: pointer to rte_eth_dev structure
4098  * @filter_op:operation will be taken.
4099  * @arg: a pointer to specific structure corresponding to the filter_op
4100  */
4101 static int
4102 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4103                                 enum rte_filter_op filter_op,
4104                                 void *arg)
4105 {
4106         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4107         int ret;
4108
4109         MAC_TYPE_FILTER_SUP(hw->mac.type);
4110
4111         if (filter_op == RTE_ETH_FILTER_NOP)
4112                 return 0;
4113
4114         if (arg == NULL) {
4115                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4116                             filter_op);
4117                 return -EINVAL;
4118         }
4119
4120         switch (filter_op) {
4121         case RTE_ETH_FILTER_ADD:
4122                 ret = igb_add_del_ethertype_filter(dev,
4123                         (struct rte_eth_ethertype_filter *)arg,
4124                         TRUE);
4125                 break;
4126         case RTE_ETH_FILTER_DELETE:
4127                 ret = igb_add_del_ethertype_filter(dev,
4128                         (struct rte_eth_ethertype_filter *)arg,
4129                         FALSE);
4130                 break;
4131         case RTE_ETH_FILTER_GET:
4132                 ret = igb_get_ethertype_filter(dev,
4133                         (struct rte_eth_ethertype_filter *)arg);
4134                 break;
4135         default:
4136                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4137                 ret = -EINVAL;
4138                 break;
4139         }
4140         return ret;
4141 }
4142
4143 static int
4144 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4145                      enum rte_filter_type filter_type,
4146                      enum rte_filter_op filter_op,
4147                      void *arg)
4148 {
4149         int ret = -EINVAL;
4150
4151         switch (filter_type) {
4152         case RTE_ETH_FILTER_NTUPLE:
4153                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4154                 break;
4155         case RTE_ETH_FILTER_ETHERTYPE:
4156                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4157                 break;
4158         case RTE_ETH_FILTER_SYN:
4159                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4160                 break;
4161         case RTE_ETH_FILTER_FLEXIBLE:
4162                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4163                 break;
4164         default:
4165                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4166                                                         filter_type);
4167                 break;
4168         }
4169
4170         return ret;
4171 }
4172
4173 static int
4174 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4175                          struct ether_addr *mc_addr_set,
4176                          uint32_t nb_mc_addr)
4177 {
4178         struct e1000_hw *hw;
4179
4180         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4181         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4182         return 0;
4183 }
4184
4185 static int
4186 igb_timesync_enable(struct rte_eth_dev *dev)
4187 {
4188         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4189         uint32_t tsync_ctl;
4190         uint32_t tsauxc;
4191
4192         /* Enable system time for it isn't on by default. */
4193         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4194         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4195         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4196
4197         /* Start incrementing the register used to timestamp PTP packets. */
4198         E1000_WRITE_REG(hw, E1000_TIMINCA, E1000_TIMINCA_INIT);
4199
4200         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4201         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4202                         (ETHER_TYPE_1588 |
4203                          E1000_ETQF_FILTER_ENABLE |
4204                          E1000_ETQF_1588));
4205
4206         /* Enable timestamping of received PTP packets. */
4207         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4208         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4209         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4210
4211         /* Enable Timestamping of transmitted PTP packets. */
4212         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4213         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4214         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4215
4216         return 0;
4217 }
4218
4219 static int
4220 igb_timesync_disable(struct rte_eth_dev *dev)
4221 {
4222         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4223         uint32_t tsync_ctl;
4224
4225         /* Disable timestamping of transmitted PTP packets. */
4226         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4227         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4228         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4229
4230         /* Disable timestamping of received PTP packets. */
4231         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4232         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4233         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4234
4235         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4236         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4237
4238         /* Stop incrementating the System Time registers. */
4239         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4240
4241         return 0;
4242 }
4243
4244 static int
4245 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4246                                struct timespec *timestamp,
4247                                uint32_t flags __rte_unused)
4248 {
4249         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4250         uint32_t tsync_rxctl;
4251         uint32_t rx_stmpl;
4252         uint32_t rx_stmph;
4253
4254         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4255         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4256                 return -EINVAL;
4257
4258         rx_stmpl = E1000_READ_REG(hw, E1000_RXSTMPL);
4259         rx_stmph = E1000_READ_REG(hw, E1000_RXSTMPH);
4260
4261         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
4262         timestamp->tv_nsec = 0;
4263
4264         return  0;
4265 }
4266
4267 static int
4268 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4269                                struct timespec *timestamp)
4270 {
4271         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4272         uint32_t tsync_txctl;
4273         uint32_t tx_stmpl;
4274         uint32_t tx_stmph;
4275
4276         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4277         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4278                 return -EINVAL;
4279
4280         tx_stmpl = E1000_READ_REG(hw, E1000_TXSTMPL);
4281         tx_stmph = E1000_READ_REG(hw, E1000_TXSTMPH);
4282
4283         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
4284         timestamp->tv_nsec = 0;
4285
4286         return  0;
4287 }
4288
4289 static int
4290 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4291 {
4292         int count = 0;
4293         int g_ind = 0;
4294         const struct reg_info *reg_group;
4295
4296         while ((reg_group = igb_regs[g_ind++]))
4297                 count += igb_reg_group_count(reg_group);
4298
4299         return count;
4300 }
4301
4302 static int
4303 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4304 {
4305         int count = 0;
4306         int g_ind = 0;
4307         const struct reg_info *reg_group;
4308
4309         while ((reg_group = igbvf_regs[g_ind++]))
4310                 count += igb_reg_group_count(reg_group);
4311
4312         return count;
4313 }
4314
4315 static int
4316 eth_igb_get_regs(struct rte_eth_dev *dev,
4317         struct rte_dev_reg_info *regs)
4318 {
4319         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4320         uint32_t *data = regs->data;
4321         int g_ind = 0;
4322         int count = 0;
4323         const struct reg_info *reg_group;
4324
4325         /* Support only full register dump */
4326         if ((regs->length == 0) ||
4327             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4328                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4329                         hw->device_id;
4330                 while ((reg_group = igb_regs[g_ind++]))
4331                         count += igb_read_regs_group(dev, &data[count],
4332                                                         reg_group);
4333                 return 0;
4334         }
4335
4336         return -ENOTSUP;
4337 }
4338
4339 static int
4340 igbvf_get_regs(struct rte_eth_dev *dev,
4341         struct rte_dev_reg_info *regs)
4342 {
4343         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4344         uint32_t *data = regs->data;
4345         int g_ind = 0;
4346         int count = 0;
4347         const struct reg_info *reg_group;
4348
4349         /* Support only full register dump */
4350         if ((regs->length == 0) ||
4351             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4352                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4353                         hw->device_id;
4354                 while ((reg_group = igbvf_regs[g_ind++]))
4355                         count += igb_read_regs_group(dev, &data[count],
4356                                                         reg_group);
4357                 return 0;
4358         }
4359
4360         return -ENOTSUP;
4361 }
4362
4363 static int
4364 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4365 {
4366         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4367
4368         /* Return unit is byte count */
4369         return hw->nvm.word_size * 2;
4370 }
4371
4372 static int
4373 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4374         struct rte_dev_eeprom_info *in_eeprom)
4375 {
4376         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4377         struct e1000_nvm_info *nvm = &hw->nvm;
4378         uint16_t *data = in_eeprom->data;
4379         int first, length;
4380
4381         first = in_eeprom->offset >> 1;
4382         length = in_eeprom->length >> 1;
4383         if ((first >= hw->nvm.word_size) ||
4384             ((first + length) >= hw->nvm.word_size))
4385                 return -EINVAL;
4386
4387         in_eeprom->magic = hw->vendor_id |
4388                 ((uint32_t)hw->device_id << 16);
4389
4390         if ((nvm->ops.read) == NULL)
4391                 return -ENOTSUP;
4392
4393         return nvm->ops.read(hw, first, length, data);
4394 }
4395
4396 static int
4397 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4398         struct rte_dev_eeprom_info *in_eeprom)
4399 {
4400         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4401         struct e1000_nvm_info *nvm = &hw->nvm;
4402         uint16_t *data = in_eeprom->data;
4403         int first, length;
4404
4405         first = in_eeprom->offset >> 1;
4406         length = in_eeprom->length >> 1;
4407         if ((first >= hw->nvm.word_size) ||
4408             ((first + length) >= hw->nvm.word_size))
4409                 return -EINVAL;
4410
4411         in_eeprom->magic = (uint32_t)hw->vendor_id |
4412                 ((uint32_t)hw->device_id << 16);
4413
4414         if ((nvm->ops.write) == NULL)
4415                 return -ENOTSUP;
4416         return nvm->ops.write(hw,  first, length, data);
4417 }
4418
4419 static struct rte_driver pmd_igb_drv = {
4420         .type = PMD_PDEV,
4421         .init = rte_igb_pmd_init,
4422 };
4423
4424 static struct rte_driver pmd_igbvf_drv = {
4425         .type = PMD_PDEV,
4426         .init = rte_igbvf_pmd_init,
4427 };
4428
4429 static int
4430 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4431 {
4432         struct e1000_hw *hw =
4433                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4434         uint32_t mask = 1 << queue_id;
4435
4436         E1000_WRITE_REG(hw, E1000_EIMC, mask);
4437         E1000_WRITE_FLUSH(hw);
4438
4439         return 0;
4440 }
4441
4442 static int
4443 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4444 {
4445         struct e1000_hw *hw =
4446                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4447         uint32_t mask = 1 << queue_id;
4448         uint32_t regval;
4449
4450         regval = E1000_READ_REG(hw, E1000_EIMS);
4451         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4452         E1000_WRITE_FLUSH(hw);
4453
4454         rte_intr_enable(&dev->pci_dev->intr_handle);
4455
4456         return 0;
4457 }
4458
4459 static void
4460 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
4461                    uint8_t index, uint8_t offset)
4462 {
4463         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4464
4465         /* clear bits */
4466         val &= ~((uint32_t)0xFF << offset);
4467
4468         /* write vector and valid bit */
4469         val |= (msix_vector | E1000_IVAR_VALID) << offset;
4470
4471         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4472 }
4473
4474 static void
4475 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4476                            uint8_t queue, uint8_t msix_vector)
4477 {
4478         uint32_t tmp = 0;
4479
4480         if (hw->mac.type == e1000_82575) {
4481                 if (direction == 0)
4482                         tmp = E1000_EICR_RX_QUEUE0 << queue;
4483                 else if (direction == 1)
4484                         tmp = E1000_EICR_TX_QUEUE0 << queue;
4485                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4486         } else if (hw->mac.type == e1000_82576) {
4487                 if ((direction == 0) || (direction == 1))
4488                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4489                                            ((queue & 0x8) << 1) +
4490                                            8 * direction);
4491         } else if ((hw->mac.type == e1000_82580) ||
4492                         (hw->mac.type == e1000_i350) ||
4493                         (hw->mac.type == e1000_i354) ||
4494                         (hw->mac.type == e1000_i210) ||
4495                         (hw->mac.type == e1000_i211)) {
4496                 if ((direction == 0) || (direction == 1))
4497                         eth_igb_write_ivar(hw, msix_vector,
4498                                            queue >> 1,
4499                                            ((queue & 0x1) << 4) +
4500                                            8 * direction);
4501         }
4502 }
4503
4504 /* Sets up the hardware to generate MSI-X interrupts properly
4505  * @hw
4506  *  board private structure
4507  */
4508 static void
4509 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4510 {
4511         int queue_id;
4512         uint32_t tmpval, regval, intr_mask;
4513         struct e1000_hw *hw =
4514                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4515         uint32_t vec = E1000_MISC_VEC_ID;
4516         uint32_t base = E1000_MISC_VEC_ID;
4517         uint32_t misc_shift = 0;
4518
4519         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4520
4521         /* won't configure msix register if no mapping is done
4522          * between intr vector and event fd
4523          */
4524         if (!rte_intr_dp_is_en(intr_handle))
4525                 return;
4526
4527         if (rte_intr_allow_others(intr_handle)) {
4528                 vec = base = E1000_RX_VEC_START;
4529                 misc_shift = 1;
4530         }
4531
4532         /* set interrupt vector for other causes */
4533         if (hw->mac.type == e1000_82575) {
4534                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4535                 /* enable MSI-X PBA support */
4536                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4537
4538                 /* Auto-Mask interrupts upon ICR read */
4539                 tmpval |= E1000_CTRL_EXT_EIAME;
4540                 tmpval |= E1000_CTRL_EXT_IRCA;
4541
4542                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4543
4544                 /* enable msix_other interrupt */
4545                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4546                 regval = E1000_READ_REG(hw, E1000_EIAC);
4547                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4548                 regval = E1000_READ_REG(hw, E1000_EIAM);
4549                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4550         } else if ((hw->mac.type == e1000_82576) ||
4551                         (hw->mac.type == e1000_82580) ||
4552                         (hw->mac.type == e1000_i350) ||
4553                         (hw->mac.type == e1000_i354) ||
4554                         (hw->mac.type == e1000_i210) ||
4555                         (hw->mac.type == e1000_i211)) {
4556                 /* turn on MSI-X capability first */
4557                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4558                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
4559                                         E1000_GPIE_NSICR);
4560                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4561                         misc_shift;
4562                 regval = E1000_READ_REG(hw, E1000_EIAC);
4563                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4564
4565                 /* enable msix_other interrupt */
4566                 regval = E1000_READ_REG(hw, E1000_EIMS);
4567                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4568                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4569                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4570         }
4571
4572         /* use EIAM to auto-mask when MSI-X interrupt
4573          * is asserted, this saves a register write for every interrupt
4574          */
4575         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4576                 misc_shift;
4577         regval = E1000_READ_REG(hw, E1000_EIAM);
4578         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4579
4580         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4581                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4582                 intr_handle->intr_vec[queue_id] = vec;
4583                 if (vec < base + intr_handle->nb_efd - 1)
4584                         vec++;
4585         }
4586
4587         E1000_WRITE_FLUSH(hw);
4588 }
4589
4590 PMD_REGISTER_DRIVER(pmd_igb_drv);
4591 PMD_REGISTER_DRIVER(pmd_igbvf_drv);