drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_string_fns.h>
  12 #include <rte_common.h>
  13 #include <rte_interrupts.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_log.h>
  16 #include <rte_debug.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memory.h>
  23 #include <rte_eal.h>
  24 #include <rte_malloc.h>
  25 #include <rte_dev.h>
  26
  27 #include "e1000_logs.h"
  28 #include "base/e1000_api.h"
  29 #include "e1000_ethdev.h"
  30 #include "igb_regs.h"
  31
  32 /*
  33  * Default values for port configuration
  34  */
  35 #define IGB_DEFAULT_RX_FREE_THRESH  32
  36
  37 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  38 #define IGB_DEFAULT_RX_HTHRESH      8
  39 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  40
  41 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  42 #define IGB_DEFAULT_TX_HTHRESH      1
  43 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  44
  45 /* Bit shift and mask */
  46 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  47 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  48 #define IGB_8_BIT_WIDTH  CHAR_BIT
  49 #define IGB_8_BIT_MASK   UINT8_MAX
  50
  51 /* Additional timesync values. */
  52 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  53 #define E1000_ETQF_FILTER_1588       3
  54 #define IGB_82576_TSYNC_SHIFT        16
  55 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  56 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  58
  59 #define E1000_VTIVAR_MISC                0x01740
  60 #define E1000_VTIVAR_MISC_MASK           0xFF
  61 #define E1000_VTIVAR_VALID               0x80
  62 #define E1000_VTIVAR_MISC_MAILBOX        0
  63 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  64
  65 /* External VLAN Enable bit mask */
  66 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  67
  68 /* External VLAN Ether Type bit mask and shift */
  69 #define E1000_VET_VET_EXT            0xFFFF0000
  70 #define E1000_VET_VET_EXT_SHIFT      16
  71
  72 /* MSI-X other interrupt vector */
  73 #define IGB_MSIX_OTHER_INTR_VEC      0
  74
  75 static int  eth_igb_configure(struct rte_eth_dev *dev);
  76 static int  eth_igb_start(struct rte_eth_dev *dev);
  77 static void eth_igb_stop(struct rte_eth_dev *dev);
  78 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  79 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  80 static void eth_igb_close(struct rte_eth_dev *dev);
  81 static int eth_igb_reset(struct rte_eth_dev *dev);
  82 static int  eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  83 static int  eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  84 static int  eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  85 static int  eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  87                                 int wait_to_complete);
  88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  89                                 struct rte_eth_stats *rte_stats);
  90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  91                               struct rte_eth_xstat *xstats, unsigned n);
  92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  93                 const uint64_t *ids,
  94                 uint64_t *values, unsigned int n);
  95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  96                                     struct rte_eth_xstat_name *xstats_names,
  97                                     unsigned int size);
  98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  99                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 100                 unsigned int limit);
 101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
 102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
 103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 104                                    char *fw_version, size_t fw_size);
 105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
 106                               struct rte_eth_dev_info *dev_info);
 107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_dev_info *dev_info);
 110 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 113                                 struct rte_eth_fc_conf *fc_conf);
 114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 118                                     struct rte_intr_handle *handle);
 119 static void eth_igb_interrupt_handler(void *param);
 120 static int  igb_hardware_init(struct e1000_hw *hw);
 121 static void igb_hw_control_acquire(struct e1000_hw *hw);
 122 static void igb_hw_control_release(struct e1000_hw *hw);
 123 static void igb_init_manageability(struct e1000_hw *hw);
 124 static void igb_release_manageability(struct e1000_hw *hw);
 125
 126 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 127
 128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 129                 uint16_t vlan_id, int on);
 130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 131                                  enum rte_vlan_type vlan_type,
 132                                  uint16_t tpid_id);
 133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134
 135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 141
 142 static int eth_igb_led_on(struct rte_eth_dev *dev);
 143 static int eth_igb_led_off(struct rte_eth_dev *dev);
 144
 145 static void igb_intr_disable(struct rte_eth_dev *dev);
 146 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 148                            struct rte_ether_addr *mac_addr,
 149                            uint32_t index, uint32_t pool);
 150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 152                 struct rte_ether_addr *addr);
 153
 154 static void igbvf_intr_disable(struct e1000_hw *hw);
 155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 156 static int igbvf_dev_start(struct rte_eth_dev *dev);
 157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 158 static void igbvf_dev_close(struct rte_eth_dev *dev);
 159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 163 static int eth_igbvf_link_update(struct e1000_hw *hw);
 164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_stats *rte_stats);
 166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 167                                 struct rte_eth_xstat *xstats, unsigned n);
 168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 169                                       struct rte_eth_xstat_name *xstats_names,
 170                                       unsigned limit);
 171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 173                 uint16_t vlan_id, int on);
 174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 177                 struct rte_ether_addr *addr);
 178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 179 static int igbvf_get_regs(struct rte_eth_dev *dev,
 180                 struct rte_dev_reg_info *regs);
 181
 182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 183                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                    uint16_t reta_size);
 185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 186                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 187                                   uint16_t reta_size);
 188
 189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 190                         struct rte_eth_syn_filter *filter);
 191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 192                         enum rte_filter_op filter_op,
 193                         void *arg);
 194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_ntuple_filter *ntuple_filter);
 198 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 199                         struct rte_eth_flex_filter *filter);
 200 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 201                         enum rte_filter_op filter_op,
 202                         void *arg);
 203 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 204                         struct rte_eth_ntuple_filter *ntuple_filter);
 205 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 206                         struct rte_eth_ntuple_filter *ntuple_filter);
 207 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 208                         struct rte_eth_ntuple_filter *filter);
 209 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 213                                 enum rte_filter_op filter_op,
 214                                 void *arg);
 215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ethertype_filter *filter);
 217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 218                      enum rte_filter_type filter_type,
 219                      enum rte_filter_op filter_op,
 220                      void *arg);
 221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 223                 struct rte_dev_reg_info *regs);
 224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 226                 struct rte_dev_eeprom_info *eeprom);
 227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 228                 struct rte_dev_eeprom_info *eeprom);
 229 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
 230                                    struct rte_eth_dev_module_info *modinfo);
 231 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
 232                                      struct rte_dev_eeprom_info *info);
 233 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 234                                     struct rte_ether_addr *mc_addr_set,
 235                                     uint32_t nb_mc_addr);
 236 static int igb_timesync_enable(struct rte_eth_dev *dev);
 237 static int igb_timesync_disable(struct rte_eth_dev *dev);
 238 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 239                                           struct timespec *timestamp,
 240                                           uint32_t flags);
 241 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 242                                           struct timespec *timestamp);
 243 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 244 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 245                                   struct timespec *timestamp);
 246 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 247                                    const struct timespec *timestamp);
 248 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 249                                         uint16_t queue_id);
 250 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 251                                          uint16_t queue_id);
 252 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 253                                        uint8_t queue, uint8_t msix_vector);
 254 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 255                                uint8_t index, uint8_t offset);
 256 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 257 static void eth_igbvf_interrupt_handler(void *param);
 258 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 259 static int igb_filter_restore(struct rte_eth_dev *dev);
 260
 261 /*
 262  * Define VF Stats MACRO for Non "cleared on read" register
 263  */
 264 #define UPDATE_VF_STAT(reg, last, cur)            \
 265 {                                                 \
 266         u32 latest = E1000_READ_REG(hw, reg);     \
 267         cur += (latest - last) & UINT_MAX;        \
 268         last = latest;                            \
 269 }
 270
 271 #define IGB_FC_PAUSE_TIME 0x0680
 272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 274
 275 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 276
 277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 278
 279 /*
 280  * The set of PCI devices this driver supports
 281  */
 282 static const struct rte_pci_id pci_id_igb_map[] = {
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 284         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 285         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 286         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 287         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 288         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 289         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 290         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 291
 292         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 295
 296         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 297         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 302
 303         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 304         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 305         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 324         { .vendor_id = 0, /* sentinel */ },
 325 };
 326
 327 /*
 328  * The set of PCI devices this driver supports (for 82576&I350 VF)
 329  */
 330 static const struct rte_pci_id pci_id_igbvf_map[] = {
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 335         { .vendor_id = 0, /* sentinel */ },
 336 };
 337
 338 static const struct rte_eth_desc_lim rx_desc_lim = {
 339         .nb_max = E1000_MAX_RING_DESC,
 340         .nb_min = E1000_MIN_RING_DESC,
 341         .nb_align = IGB_RXD_ALIGN,
 342 };
 343
 344 static const struct rte_eth_desc_lim tx_desc_lim = {
 345         .nb_max = E1000_MAX_RING_DESC,
 346         .nb_min = E1000_MIN_RING_DESC,
 347         .nb_align = IGB_RXD_ALIGN,
 348         .nb_seg_max = IGB_TX_MAX_SEG,
 349         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 350 };
 351
 352 static const struct eth_dev_ops eth_igb_ops = {
 353         .dev_configure        = eth_igb_configure,
 354         .dev_start            = eth_igb_start,
 355         .dev_stop             = eth_igb_stop,
 356         .dev_set_link_up      = eth_igb_dev_set_link_up,
 357         .dev_set_link_down    = eth_igb_dev_set_link_down,
 358         .dev_close            = eth_igb_close,
 359         .dev_reset            = eth_igb_reset,
 360         .promiscuous_enable   = eth_igb_promiscuous_enable,
 361         .promiscuous_disable  = eth_igb_promiscuous_disable,
 362         .allmulticast_enable  = eth_igb_allmulticast_enable,
 363         .allmulticast_disable = eth_igb_allmulticast_disable,
 364         .link_update          = eth_igb_link_update,
 365         .stats_get            = eth_igb_stats_get,
 366         .xstats_get           = eth_igb_xstats_get,
 367         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 368         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 369         .xstats_get_names     = eth_igb_xstats_get_names,
 370         .stats_reset          = eth_igb_stats_reset,
 371         .xstats_reset         = eth_igb_xstats_reset,
 372         .fw_version_get       = eth_igb_fw_version_get,
 373         .dev_infos_get        = eth_igb_infos_get,
 374         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 375         .mtu_set              = eth_igb_mtu_set,
 376         .vlan_filter_set      = eth_igb_vlan_filter_set,
 377         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 378         .vlan_offload_set     = eth_igb_vlan_offload_set,
 379         .rx_queue_setup       = eth_igb_rx_queue_setup,
 380         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 381         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 382         .rx_queue_release     = eth_igb_rx_queue_release,
 383         .rx_queue_count       = eth_igb_rx_queue_count,
 384         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 385         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 386         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 387         .tx_queue_setup       = eth_igb_tx_queue_setup,
 388         .tx_queue_release     = eth_igb_tx_queue_release,
 389         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 390         .dev_led_on           = eth_igb_led_on,
 391         .dev_led_off          = eth_igb_led_off,
 392         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 393         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 394         .mac_addr_add         = eth_igb_rar_set,
 395         .mac_addr_remove      = eth_igb_rar_clear,
 396         .mac_addr_set         = eth_igb_default_mac_addr_set,
 397         .reta_update          = eth_igb_rss_reta_update,
 398         .reta_query           = eth_igb_rss_reta_query,
 399         .rss_hash_update      = eth_igb_rss_hash_update,
 400         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 401         .filter_ctrl          = eth_igb_filter_ctrl,
 402         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 403         .rxq_info_get         = igb_rxq_info_get,
 404         .txq_info_get         = igb_txq_info_get,
 405         .timesync_enable      = igb_timesync_enable,
 406         .timesync_disable     = igb_timesync_disable,
 407         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 408         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 409         .get_reg              = eth_igb_get_regs,
 410         .get_eeprom_length    = eth_igb_get_eeprom_length,
 411         .get_eeprom           = eth_igb_get_eeprom,
 412         .set_eeprom           = eth_igb_set_eeprom,
 413         .get_module_info      = eth_igb_get_module_info,
 414         .get_module_eeprom    = eth_igb_get_module_eeprom,
 415         .timesync_adjust_time = igb_timesync_adjust_time,
 416         .timesync_read_time   = igb_timesync_read_time,
 417         .timesync_write_time  = igb_timesync_write_time,
 418 };
 419
 420 /*
 421  * dev_ops for virtual function, bare necessities for basic vf
 422  * operation have been implemented
 423  */
 424 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 425         .dev_configure        = igbvf_dev_configure,
 426         .dev_start            = igbvf_dev_start,
 427         .dev_stop             = igbvf_dev_stop,
 428         .dev_close            = igbvf_dev_close,
 429         .promiscuous_enable   = igbvf_promiscuous_enable,
 430         .promiscuous_disable  = igbvf_promiscuous_disable,
 431         .allmulticast_enable  = igbvf_allmulticast_enable,
 432         .allmulticast_disable = igbvf_allmulticast_disable,
 433         .link_update          = eth_igb_link_update,
 434         .stats_get            = eth_igbvf_stats_get,
 435         .xstats_get           = eth_igbvf_xstats_get,
 436         .xstats_get_names     = eth_igbvf_xstats_get_names,
 437         .stats_reset          = eth_igbvf_stats_reset,
 438         .xstats_reset         = eth_igbvf_stats_reset,
 439         .vlan_filter_set      = igbvf_vlan_filter_set,
 440         .dev_infos_get        = eth_igbvf_infos_get,
 441         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 442         .rx_queue_setup       = eth_igb_rx_queue_setup,
 443         .rx_queue_release     = eth_igb_rx_queue_release,
 444         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 445         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 446         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 447         .tx_queue_setup       = eth_igb_tx_queue_setup,
 448         .tx_queue_release     = eth_igb_tx_queue_release,
 449         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 450         .rxq_info_get         = igb_rxq_info_get,
 451         .txq_info_get         = igb_txq_info_get,
 452         .mac_addr_set         = igbvf_default_mac_addr_set,
 453         .get_reg              = igbvf_get_regs,
 454 };
 455
 456 /* store statistics names and its offset in stats structure */
 457 struct rte_igb_xstats_name_off {
 458         char name[RTE_ETH_XSTATS_NAME_SIZE];
 459         unsigned offset;
 460 };
 461
 462 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 463         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 464         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 465         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 466         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 467         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 468         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 469         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 470                 ecol)},
 471         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 472         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 473         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 474         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 475         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 476         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 477         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 478         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 479         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 480         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 481         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 482                 fcruc)},
 483         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 484         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 485         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 486         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 487         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 488                 prc1023)},
 489         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 490                 prc1522)},
 491         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 492         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 493         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 494         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 495         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 496         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 497         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 498         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 499         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 500         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 501         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 502         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 503         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 504         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 505         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 506         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 507         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 508         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 509                 ptc1023)},
 510         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 511                 ptc1522)},
 512         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 513         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 514         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 515         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 516         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 517         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 518         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 519
 520         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 521 };
 522
 523 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 524                 sizeof(rte_igb_stats_strings[0]))
 525
 526 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 527         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 528         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 529         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 530         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 531         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 532 };
 533
 534 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 535                 sizeof(rte_igbvf_stats_strings[0]))
 536
 537
 538 static inline void
 539 igb_intr_enable(struct rte_eth_dev *dev)
 540 {
 541         struct e1000_interrupt *intr =
 542                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 543         struct e1000_hw *hw =
 544                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 545         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 546         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 547
 548         if (rte_intr_allow_others(intr_handle) &&
 549                 dev->data->dev_conf.intr_conf.lsc != 0) {
 550                 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
 551         }
 552
 553         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 554         E1000_WRITE_FLUSH(hw);
 555 }
 556
 557 static void
 558 igb_intr_disable(struct rte_eth_dev *dev)
 559 {
 560         struct e1000_hw *hw =
 561                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 562         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 563         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 564
 565         if (rte_intr_allow_others(intr_handle) &&
 566                 dev->data->dev_conf.intr_conf.lsc != 0) {
 567                 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
 568         }
 569
 570         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 571         E1000_WRITE_FLUSH(hw);
 572 }
 573
 574 static inline void
 575 igbvf_intr_enable(struct rte_eth_dev *dev)
 576 {
 577         struct e1000_hw *hw =
 578                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 579
 580         /* only for mailbox */
 581         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 582         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 583         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 584         E1000_WRITE_FLUSH(hw);
 585 }
 586
 587 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 588 static void
 589 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 590 {
 591         uint32_t tmp = 0;
 592
 593         /* mailbox */
 594         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 595         tmp |= E1000_VTIVAR_VALID;
 596         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 597 }
 598
 599 static void
 600 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 601 {
 602         struct e1000_hw *hw =
 603                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 604
 605         /* Configure VF other cause ivar */
 606         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 607 }
 608
 609 static inline int32_t
 610 igb_pf_reset_hw(struct e1000_hw *hw)
 611 {
 612         uint32_t ctrl_ext;
 613         int32_t status;
 614
 615         status = e1000_reset_hw(hw);
 616
 617         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 618         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 619         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 620         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 621         E1000_WRITE_FLUSH(hw);
 622
 623         return status;
 624 }
 625
 626 static void
 627 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 628 {
 629         struct e1000_hw *hw =
 630                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 631
 632
 633         hw->vendor_id = pci_dev->id.vendor_id;
 634         hw->device_id = pci_dev->id.device_id;
 635         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 636         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 637
 638         e1000_set_mac_type(hw);
 639
 640         /* need to check if it is a vf device below */
 641 }
 642
 643 static int
 644 igb_reset_swfw_lock(struct e1000_hw *hw)
 645 {
 646         int ret_val;
 647
 648         /*
 649          * Do mac ops initialization manually here, since we will need
 650          * some function pointers set by this call.
 651          */
 652         ret_val = e1000_init_mac_params(hw);
 653         if (ret_val)
 654                 return ret_val;
 655
 656         /*
 657          * SMBI lock should not fail in this early stage. If this is the case,
 658          * it is due to an improper exit of the application.
 659          * So force the release of the faulty lock.
 660          */
 661         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 662                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 663         }
 664         e1000_put_hw_semaphore_generic(hw);
 665
 666         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 667                 uint16_t mask;
 668
 669                 /*
 670                  * Phy lock should not fail in this early stage. If this is the case,
 671                  * it is due to an improper exit of the application.
 672                  * So force the release of the faulty lock.
 673                  */
 674                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 675                 if (hw->bus.func > E1000_FUNC_1)
 676                         mask <<= 2;
 677                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 678                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 679                                     hw->bus.func);
 680                 }
 681                 hw->mac.ops.release_swfw_sync(hw, mask);
 682
 683                 /*
 684                  * This one is more tricky since it is common to all ports; but
 685                  * swfw_sync retries last long enough (1s) to be almost sure that if
 686                  * lock can not be taken it is due to an improper lock of the
 687                  * semaphore.
 688                  */
 689                 mask = E1000_SWFW_EEP_SM;
 690                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 691                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 692                 }
 693                 hw->mac.ops.release_swfw_sync(hw, mask);
 694         }
 695
 696         return E1000_SUCCESS;
 697 }
 698
 699 /* Remove all ntuple filters of the device */
 700 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 701 {
 702         struct e1000_filter_info *filter_info =
 703                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 704         struct e1000_5tuple_filter *p_5tuple;
 705         struct e1000_2tuple_filter *p_2tuple;
 706
 707         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 708                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 709                         p_5tuple, entries);
 710                         rte_free(p_5tuple);
 711         }
 712         filter_info->fivetuple_mask = 0;
 713         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 714                 TAILQ_REMOVE(&filter_info->twotuple_list,
 715                         p_2tuple, entries);
 716                         rte_free(p_2tuple);
 717         }
 718         filter_info->twotuple_mask = 0;
 719
 720         return 0;
 721 }
 722
 723 /* Remove all flex filters of the device */
 724 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 725 {
 726         struct e1000_filter_info *filter_info =
 727                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 728         struct e1000_flex_filter *p_flex;
 729
 730         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 731                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 732                 rte_free(p_flex);
 733         }
 734         filter_info->flex_mask = 0;
 735
 736         return 0;
 737 }
 738
 739 static int
 740 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 741 {
 742         int error = 0;
 743         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 744         struct e1000_hw *hw =
 745                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 746         struct e1000_vfta * shadow_vfta =
 747                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 748         struct e1000_filter_info *filter_info =
 749                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 750         struct e1000_adapter *adapter =
 751                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 752
 753         uint32_t ctrl_ext;
 754
 755         eth_dev->dev_ops = &eth_igb_ops;
 756         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 757         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 758         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 759
 760         /* for secondary processes, we don't initialise any further as primary
 761          * has already done this work. Only check we don't need a different
 762          * RX function */
 763         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 764                 if (eth_dev->data->scattered_rx)
 765                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 766                 return 0;
 767         }
 768
 769         rte_eth_copy_pci_info(eth_dev, pci_dev);
 770
 771         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 772
 773         igb_identify_hardware(eth_dev, pci_dev);
 774         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 775                 error = -EIO;
 776                 goto err_late;
 777         }
 778
 779         e1000_get_bus_info(hw);
 780
 781         /* Reset any pending lock */
 782         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 783                 error = -EIO;
 784                 goto err_late;
 785         }
 786
 787         /* Finish initialization */
 788         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 789                 error = -EIO;
 790                 goto err_late;
 791         }
 792
 793         hw->mac.autoneg = 1;
 794         hw->phy.autoneg_wait_to_complete = 0;
 795         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 796
 797         /* Copper options */
 798         if (hw->phy.media_type == e1000_media_type_copper) {
 799                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 800                 hw->phy.disable_polarity_correction = 0;
 801                 hw->phy.ms_type = e1000_ms_hw_default;
 802         }
 803
 804         /*
 805          * Start from a known state, this is important in reading the nvm
 806          * and mac from that.
 807          */
 808         igb_pf_reset_hw(hw);
 809
 810         /* Make sure we have a good EEPROM before we read from it */
 811         if (e1000_validate_nvm_checksum(hw) < 0) {
 812                 /*
 813                  * Some PCI-E parts fail the first check due to
 814                  * the link being in sleep state, call it again,
 815                  * if it fails a second time its a real issue.
 816                  */
 817                 if (e1000_validate_nvm_checksum(hw) < 0) {
 818                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 819                         error = -EIO;
 820                         goto err_late;
 821                 }
 822         }
 823
 824         /* Read the permanent MAC address out of the EEPROM */
 825         if (e1000_read_mac_addr(hw) != 0) {
 826                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 827                 error = -EIO;
 828                 goto err_late;
 829         }
 830
 831         /* Allocate memory for storing MAC addresses */
 832         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 833                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 834         if (eth_dev->data->mac_addrs == NULL) {
 835                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 836                                                 "store MAC addresses",
 837                                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 838                 error = -ENOMEM;
 839                 goto err_late;
 840         }
 841
 842         /* Copy the permanent MAC address */
 843         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 844                         &eth_dev->data->mac_addrs[0]);
 845
 846         /* Pass the information to the rte_eth_dev_close() that it should also
 847          * release the private port resources.
 848          */
 849         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
 850
 851         /* initialize the vfta */
 852         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 853
 854         /* Now initialize the hardware */
 855         if (igb_hardware_init(hw) != 0) {
 856                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 857                 rte_free(eth_dev->data->mac_addrs);
 858                 eth_dev->data->mac_addrs = NULL;
 859                 error = -ENODEV;
 860                 goto err_late;
 861         }
 862         hw->mac.get_link_status = 1;
 863         adapter->stopped = 0;
 864
 865         /* Indicate SOL/IDER usage */
 866         if (e1000_check_reset_block(hw) < 0) {
 867                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 868                                         "SOL/IDER session");
 869         }
 870
 871         /* initialize PF if max_vfs not zero */
 872         igb_pf_host_init(eth_dev);
 873
 874         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 875         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 876         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 877         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 878         E1000_WRITE_FLUSH(hw);
 879
 880         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 881                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 882                      pci_dev->id.device_id);
 883
 884         rte_intr_callback_register(&pci_dev->intr_handle,
 885                                    eth_igb_interrupt_handler,
 886                                    (void *)eth_dev);
 887
 888         /* enable uio/vfio intr/eventfd mapping */
 889         rte_intr_enable(&pci_dev->intr_handle);
 890
 891         /* enable support intr */
 892         igb_intr_enable(eth_dev);
 893
 894         /* initialize filter info */
 895         memset(filter_info, 0,
 896                sizeof(struct e1000_filter_info));
 897
 898         TAILQ_INIT(&filter_info->flex_list);
 899         TAILQ_INIT(&filter_info->twotuple_list);
 900         TAILQ_INIT(&filter_info->fivetuple_list);
 901
 902         TAILQ_INIT(&igb_filter_ntuple_list);
 903         TAILQ_INIT(&igb_filter_ethertype_list);
 904         TAILQ_INIT(&igb_filter_syn_list);
 905         TAILQ_INIT(&igb_filter_flex_list);
 906         TAILQ_INIT(&igb_filter_rss_list);
 907         TAILQ_INIT(&igb_flow_list);
 908
 909         return 0;
 910
 911 err_late:
 912         igb_hw_control_release(hw);
 913
 914         return error;
 915 }
 916
 917 static int
 918 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 919 {
 920         PMD_INIT_FUNC_TRACE();
 921
 922         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 923                 return -EPERM;
 924
 925         eth_igb_close(eth_dev);
 926
 927         return 0;
 928 }
 929
 930 /*
 931  * Virtual Function device init
 932  */
 933 static int
 934 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 935 {
 936         struct rte_pci_device *pci_dev;
 937         struct rte_intr_handle *intr_handle;
 938         struct e1000_adapter *adapter =
 939                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 940         struct e1000_hw *hw =
 941                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 942         int diag;
 943         struct rte_ether_addr *perm_addr =
 944                 (struct rte_ether_addr *)hw->mac.perm_addr;
 945
 946         PMD_INIT_FUNC_TRACE();
 947
 948         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 949         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 950         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 951         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 952
 953         /* for secondary processes, we don't initialise any further as primary
 954          * has already done this work. Only check we don't need a different
 955          * RX function */
 956         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 957                 if (eth_dev->data->scattered_rx)
 958                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 959                 return 0;
 960         }
 961
 962         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 963         rte_eth_copy_pci_info(eth_dev, pci_dev);
 964
 965         hw->device_id = pci_dev->id.device_id;
 966         hw->vendor_id = pci_dev->id.vendor_id;
 967         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 968         adapter->stopped = 0;
 969
 970         /* Initialize the shared code (base driver) */
 971         diag = e1000_setup_init_funcs(hw, TRUE);
 972         if (diag != 0) {
 973                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 974                         diag);
 975                 return -EIO;
 976         }
 977
 978         /* init_mailbox_params */
 979         hw->mbx.ops.init_params(hw);
 980
 981         /* Disable the interrupts for VF */
 982         igbvf_intr_disable(hw);
 983
 984         diag = hw->mac.ops.reset_hw(hw);
 985
 986         /* Allocate memory for storing MAC addresses */
 987         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
 988                 hw->mac.rar_entry_count, 0);
 989         if (eth_dev->data->mac_addrs == NULL) {
 990                 PMD_INIT_LOG(ERR,
 991                         "Failed to allocate %d bytes needed to store MAC "
 992                         "addresses",
 993                         RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 994                 return -ENOMEM;
 995         }
 996
 997         /* Pass the information to the rte_eth_dev_close() that it should also
 998          * release the private port resources.
 999          */
1000         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1001
1002         /* Generate a random MAC address, if none was assigned by PF. */
1003         if (rte_is_zero_ether_addr(perm_addr)) {
1004                 rte_eth_random_addr(perm_addr->addr_bytes);
1005                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1006                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1007                              "%02x:%02x:%02x:%02x:%02x:%02x",
1008                              perm_addr->addr_bytes[0],
1009                              perm_addr->addr_bytes[1],
1010                              perm_addr->addr_bytes[2],
1011                              perm_addr->addr_bytes[3],
1012                              perm_addr->addr_bytes[4],
1013                              perm_addr->addr_bytes[5]);
1014         }
1015
1016         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1017         if (diag) {
1018                 rte_free(eth_dev->data->mac_addrs);
1019                 eth_dev->data->mac_addrs = NULL;
1020                 return diag;
1021         }
1022         /* Copy the permanent MAC address */
1023         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1024                         &eth_dev->data->mac_addrs[0]);
1025
1026         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1027                      "mac.type=%s",
1028                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1029                      pci_dev->id.device_id, "igb_mac_82576_vf");
1030
1031         intr_handle = &pci_dev->intr_handle;
1032         rte_intr_callback_register(intr_handle,
1033                                    eth_igbvf_interrupt_handler, eth_dev);
1034
1035         return 0;
1036 }
1037
1038 static int
1039 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1040 {
1041         PMD_INIT_FUNC_TRACE();
1042
1043         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1044                 return -EPERM;
1045
1046         igbvf_dev_close(eth_dev);
1047
1048         return 0;
1049 }
1050
1051 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1052         struct rte_pci_device *pci_dev)
1053 {
1054         return rte_eth_dev_pci_generic_probe(pci_dev,
1055                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1056 }
1057
1058 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1059 {
1060         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1061 }
1062
1063 static struct rte_pci_driver rte_igb_pmd = {
1064         .id_table = pci_id_igb_map,
1065         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1066         .probe = eth_igb_pci_probe,
1067         .remove = eth_igb_pci_remove,
1068 };
1069
1070
1071 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1072         struct rte_pci_device *pci_dev)
1073 {
1074         return rte_eth_dev_pci_generic_probe(pci_dev,
1075                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1076 }
1077
1078 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1079 {
1080         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1081 }
1082
1083 /*
1084  * virtual function driver struct
1085  */
1086 static struct rte_pci_driver rte_igbvf_pmd = {
1087         .id_table = pci_id_igbvf_map,
1088         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1089         .probe = eth_igbvf_pci_probe,
1090         .remove = eth_igbvf_pci_remove,
1091 };
1092
1093 static void
1094 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1095 {
1096         struct e1000_hw *hw =
1097                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1098         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1099         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1100         rctl |= E1000_RCTL_VFE;
1101         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1102 }
1103
1104 static int
1105 igb_check_mq_mode(struct rte_eth_dev *dev)
1106 {
1107         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1108         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1109         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1110         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1111
1112         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1113             tx_mq_mode == ETH_MQ_TX_DCB ||
1114             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1115                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1116                 return -EINVAL;
1117         }
1118         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1119                 /* Check multi-queue mode.
1120                  * To no break software we accept ETH_MQ_RX_NONE as this might
1121                  * be used to turn off VLAN filter.
1122                  */
1123
1124                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1125                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1126                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1127                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1128                 } else {
1129                         /* Only support one queue on VFs.
1130                          * RSS together with SRIOV is not supported.
1131                          */
1132                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1133                                         " wrong mq_mode rx %d.",
1134                                         rx_mq_mode);
1135                         return -EINVAL;
1136                 }
1137                 /* TX mode is not used here, so mode might be ignored.*/
1138                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1139                         /* SRIOV only works in VMDq enable mode */
1140                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1141                                         " TX mode %d is not supported. "
1142                                         " Driver will behave as %d mode.",
1143                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1144                 }
1145
1146                 /* check valid queue number */
1147                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1148                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1149                                         " only support one queue on VFs.");
1150                         return -EINVAL;
1151                 }
1152         } else {
1153                 /* To no break software that set invalid mode, only display
1154                  * warning if invalid mode is used.
1155                  */
1156                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1157                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1158                     rx_mq_mode != ETH_MQ_RX_RSS) {
1159                         /* RSS together with VMDq not supported*/
1160                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1161                                      rx_mq_mode);
1162                         return -EINVAL;
1163                 }
1164
1165                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1166                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1167                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1168                                         " Due to txmode is meaningless in this"
1169                                         " driver, just ignore.",
1170                                         tx_mq_mode);
1171                 }
1172         }
1173         return 0;
1174 }
1175
1176 static int
1177 eth_igb_configure(struct rte_eth_dev *dev)
1178 {
1179         struct e1000_interrupt *intr =
1180                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1181         int ret;
1182
1183         PMD_INIT_FUNC_TRACE();
1184
1185         dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1186
1187         /* multipe queue mode checking */
1188         ret  = igb_check_mq_mode(dev);
1189         if (ret != 0) {
1190                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1191                             ret);
1192                 return ret;
1193         }
1194
1195         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1196         PMD_INIT_FUNC_TRACE();
1197
1198         return 0;
1199 }
1200
1201 static void
1202 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1203                      bool enable)
1204 {
1205         struct e1000_hw *hw =
1206                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1207         uint32_t tctl, rctl;
1208
1209         tctl = E1000_READ_REG(hw, E1000_TCTL);
1210         rctl = E1000_READ_REG(hw, E1000_RCTL);
1211
1212         if (enable) {
1213                 /* enable Tx/Rx */
1214                 tctl |= E1000_TCTL_EN;
1215                 rctl |= E1000_RCTL_EN;
1216         } else {
1217                 /* disable Tx/Rx */
1218                 tctl &= ~E1000_TCTL_EN;
1219                 rctl &= ~E1000_RCTL_EN;
1220         }
1221         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1222         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1223         E1000_WRITE_FLUSH(hw);
1224 }
1225
1226 static int
1227 eth_igb_start(struct rte_eth_dev *dev)
1228 {
1229         struct e1000_hw *hw =
1230                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1231         struct e1000_adapter *adapter =
1232                 E1000_DEV_PRIVATE(dev->data->dev_private);
1233         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1234         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1235         int ret, mask;
1236         uint32_t intr_vector = 0;
1237         uint32_t ctrl_ext;
1238         uint32_t *speeds;
1239         int num_speeds;
1240         bool autoneg;
1241
1242         PMD_INIT_FUNC_TRACE();
1243
1244         /* disable uio/vfio intr/eventfd mapping */
1245         rte_intr_disable(intr_handle);
1246
1247         /* Power up the phy. Needed to make the link go Up */
1248         eth_igb_dev_set_link_up(dev);
1249
1250         /*
1251          * Packet Buffer Allocation (PBA)
1252          * Writing PBA sets the receive portion of the buffer
1253          * the remainder is used for the transmit buffer.
1254          */
1255         if (hw->mac.type == e1000_82575) {
1256                 uint32_t pba;
1257
1258                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1259                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1260         }
1261
1262         /* Put the address into the Receive Address Array */
1263         e1000_rar_set(hw, hw->mac.addr, 0);
1264
1265         /* Initialize the hardware */
1266         if (igb_hardware_init(hw)) {
1267                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1268                 return -EIO;
1269         }
1270         adapter->stopped = 0;
1271
1272         E1000_WRITE_REG(hw, E1000_VET,
1273                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1274
1275         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1276         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1277         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1278         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1279         E1000_WRITE_FLUSH(hw);
1280
1281         /* configure PF module if SRIOV enabled */
1282         igb_pf_host_configure(dev);
1283
1284         /* check and configure queue intr-vector mapping */
1285         if ((rte_intr_cap_multiple(intr_handle) ||
1286              !RTE_ETH_DEV_SRIOV(dev).active) &&
1287             dev->data->dev_conf.intr_conf.rxq != 0) {
1288                 intr_vector = dev->data->nb_rx_queues;
1289                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1290                         return -1;
1291         }
1292
1293         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1294                 intr_handle->intr_vec =
1295                         rte_zmalloc("intr_vec",
1296                                     dev->data->nb_rx_queues * sizeof(int), 0);
1297                 if (intr_handle->intr_vec == NULL) {
1298                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1299                                      " intr_vec", dev->data->nb_rx_queues);
1300                         return -ENOMEM;
1301                 }
1302         }
1303
1304         /* confiugre msix for rx interrupt */
1305         eth_igb_configure_msix_intr(dev);
1306
1307         /* Configure for OS presence */
1308         igb_init_manageability(hw);
1309
1310         eth_igb_tx_init(dev);
1311
1312         /* This can fail when allocating mbufs for descriptor rings */
1313         ret = eth_igb_rx_init(dev);
1314         if (ret) {
1315                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1316                 igb_dev_clear_queues(dev);
1317                 return ret;
1318         }
1319
1320         e1000_clear_hw_cntrs_base_generic(hw);
1321
1322         /*
1323          * VLAN Offload Settings
1324          */
1325         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1326                         ETH_VLAN_EXTEND_MASK;
1327         ret = eth_igb_vlan_offload_set(dev, mask);
1328         if (ret) {
1329                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1330                 igb_dev_clear_queues(dev);
1331                 return ret;
1332         }
1333
1334         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1335                 /* Enable VLAN filter since VMDq always use VLAN filter */
1336                 igb_vmdq_vlan_hw_filter_enable(dev);
1337         }
1338
1339         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1340                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1341                 (hw->mac.type == e1000_i211)) {
1342                 /* Configure EITR with the maximum possible value (0xFFFF) */
1343                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1344         }
1345
1346         /* Setup link speed and duplex */
1347         speeds = &dev->data->dev_conf.link_speeds;
1348         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1349                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1350                 hw->mac.autoneg = 1;
1351         } else {
1352                 num_speeds = 0;
1353                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1354
1355                 /* Reset */
1356                 hw->phy.autoneg_advertised = 0;
1357
1358                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1359                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1360                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1361                         num_speeds = -1;
1362                         goto error_invalid_config;
1363                 }
1364                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1365                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1366                         num_speeds++;
1367                 }
1368                 if (*speeds & ETH_LINK_SPEED_10M) {
1369                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1370                         num_speeds++;
1371                 }
1372                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1373                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1374                         num_speeds++;
1375                 }
1376                 if (*speeds & ETH_LINK_SPEED_100M) {
1377                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1378                         num_speeds++;
1379                 }
1380                 if (*speeds & ETH_LINK_SPEED_1G) {
1381                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1382                         num_speeds++;
1383                 }
1384                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1385                         goto error_invalid_config;
1386
1387                 /* Set/reset the mac.autoneg based on the link speed,
1388                  * fixed or not
1389                  */
1390                 if (!autoneg) {
1391                         hw->mac.autoneg = 0;
1392                         hw->mac.forced_speed_duplex =
1393                                         hw->phy.autoneg_advertised;
1394                 } else {
1395                         hw->mac.autoneg = 1;
1396                 }
1397         }
1398
1399         e1000_setup_link(hw);
1400
1401         if (rte_intr_allow_others(intr_handle)) {
1402                 /* check if lsc interrupt is enabled */
1403                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1404                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1405                 else
1406                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1407         } else {
1408                 rte_intr_callback_unregister(intr_handle,
1409                                              eth_igb_interrupt_handler,
1410                                              (void *)dev);
1411                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1412                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1413                                      " no intr multiplex");
1414         }
1415
1416         /* check if rxq interrupt is enabled */
1417         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1418             rte_intr_dp_is_en(intr_handle))
1419                 eth_igb_rxq_interrupt_setup(dev);
1420
1421         /* enable uio/vfio intr/eventfd mapping */
1422         rte_intr_enable(intr_handle);
1423
1424         /* resume enabled intr since hw reset */
1425         igb_intr_enable(dev);
1426
1427         /* restore all types filter */
1428         igb_filter_restore(dev);
1429
1430         eth_igb_rxtx_control(dev, true);
1431         eth_igb_link_update(dev, 0);
1432
1433         PMD_INIT_LOG(DEBUG, "<<");
1434
1435         return 0;
1436
1437 error_invalid_config:
1438         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1439                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1440         igb_dev_clear_queues(dev);
1441         return -EINVAL;
1442 }
1443
1444 /*********************************************************************
1445  *
1446  *  This routine disables all traffic on the adapter by issuing a
1447  *  global reset on the MAC.
1448  *
1449  **********************************************************************/
1450 static void
1451 eth_igb_stop(struct rte_eth_dev *dev)
1452 {
1453         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1454         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1455         struct rte_eth_link link;
1456         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1457         struct e1000_adapter *adapter =
1458                 E1000_DEV_PRIVATE(dev->data->dev_private);
1459
1460         if (adapter->stopped)
1461                 return;
1462
1463         eth_igb_rxtx_control(dev, false);
1464
1465         igb_intr_disable(dev);
1466
1467         /* disable intr eventfd mapping */
1468         rte_intr_disable(intr_handle);
1469
1470         igb_pf_reset_hw(hw);
1471         E1000_WRITE_REG(hw, E1000_WUC, 0);
1472
1473         /* Set bit for Go Link disconnect if PHY reset is not blocked */
1474         if (hw->mac.type >= e1000_82580 &&
1475             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1476                 uint32_t phpm_reg;
1477
1478                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1479                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1480                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1481         }
1482
1483         /* Power down the phy. Needed to make the link go Down */
1484         eth_igb_dev_set_link_down(dev);
1485
1486         igb_dev_clear_queues(dev);
1487
1488         /* clear the recorded link status */
1489         memset(&link, 0, sizeof(link));
1490         rte_eth_linkstatus_set(dev, &link);
1491
1492         if (!rte_intr_allow_others(intr_handle))
1493                 /* resume to the default handler */
1494                 rte_intr_callback_register(intr_handle,
1495                                            eth_igb_interrupt_handler,
1496                                            (void *)dev);
1497
1498         /* Clean datapath event and queue/vec mapping */
1499         rte_intr_efd_disable(intr_handle);
1500         if (intr_handle->intr_vec != NULL) {
1501                 rte_free(intr_handle->intr_vec);
1502                 intr_handle->intr_vec = NULL;
1503         }
1504
1505         adapter->stopped = true;
1506 }
1507
1508 static int
1509 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1510 {
1511         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1512
1513         if (hw->phy.media_type == e1000_media_type_copper)
1514                 e1000_power_up_phy(hw);
1515         else
1516                 e1000_power_up_fiber_serdes_link(hw);
1517
1518         return 0;
1519 }
1520
1521 static int
1522 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1523 {
1524         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1525
1526         if (hw->phy.media_type == e1000_media_type_copper)
1527                 e1000_power_down_phy(hw);
1528         else
1529                 e1000_shutdown_fiber_serdes_link(hw);
1530
1531         return 0;
1532 }
1533
1534 static void
1535 eth_igb_close(struct rte_eth_dev *dev)
1536 {
1537         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1538         struct rte_eth_link link;
1539         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1540         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1541         struct e1000_filter_info *filter_info =
1542                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1543
1544         eth_igb_stop(dev);
1545
1546         e1000_phy_hw_reset(hw);
1547         igb_release_manageability(hw);
1548         igb_hw_control_release(hw);
1549
1550         /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1551         if (hw->mac.type >= e1000_82580 &&
1552             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1553                 uint32_t phpm_reg;
1554
1555                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1556                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1557                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1558         }
1559
1560         igb_dev_free_queues(dev);
1561
1562         if (intr_handle->intr_vec) {
1563                 rte_free(intr_handle->intr_vec);
1564                 intr_handle->intr_vec = NULL;
1565         }
1566
1567         memset(&link, 0, sizeof(link));
1568         rte_eth_linkstatus_set(dev, &link);
1569
1570         dev->dev_ops = NULL;
1571         dev->rx_pkt_burst = NULL;
1572         dev->tx_pkt_burst = NULL;
1573
1574         /* Reset any pending lock */
1575         igb_reset_swfw_lock(hw);
1576
1577         /* uninitialize PF if max_vfs not zero */
1578         igb_pf_host_uninit(dev);
1579
1580         rte_intr_callback_unregister(intr_handle,
1581                                      eth_igb_interrupt_handler, dev);
1582
1583         /* clear the SYN filter info */
1584         filter_info->syn_info = 0;
1585
1586         /* clear the ethertype filters info */
1587         filter_info->ethertype_mask = 0;
1588         memset(filter_info->ethertype_filters, 0,
1589                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1590
1591         /* clear the rss filter info */
1592         memset(&filter_info->rss_info, 0,
1593                 sizeof(struct igb_rte_flow_rss_conf));
1594
1595         /* remove all ntuple filters of the device */
1596         igb_ntuple_filter_uninit(dev);
1597
1598         /* remove all flex filters of the device */
1599         igb_flex_filter_uninit(dev);
1600
1601         /* clear all the filters list */
1602         igb_filterlist_flush(dev);
1603 }
1604
1605 /*
1606  * Reset PF device.
1607  */
1608 static int
1609 eth_igb_reset(struct rte_eth_dev *dev)
1610 {
1611         int ret;
1612
1613         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1614          * its VF to make them align with it. The detailed notification
1615          * mechanism is PMD specific and is currently not implemented.
1616          * To avoid unexpected behavior in VF, currently reset of PF with
1617          * SR-IOV activation is not supported. It might be supported later.
1618          */
1619         if (dev->data->sriov.active)
1620                 return -ENOTSUP;
1621
1622         ret = eth_igb_dev_uninit(dev);
1623         if (ret)
1624                 return ret;
1625
1626         ret = eth_igb_dev_init(dev);
1627
1628         return ret;
1629 }
1630
1631
1632 static int
1633 igb_get_rx_buffer_size(struct e1000_hw *hw)
1634 {
1635         uint32_t rx_buf_size;
1636         if (hw->mac.type == e1000_82576) {
1637                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1638         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1639                 /* PBS needs to be translated according to a lookup table */
1640                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1641                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1642                 rx_buf_size = (rx_buf_size << 10);
1643         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1644                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1645         } else {
1646                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1647         }
1648
1649         return rx_buf_size;
1650 }
1651
1652 /*********************************************************************
1653  *
1654  *  Initialize the hardware
1655  *
1656  **********************************************************************/
1657 static int
1658 igb_hardware_init(struct e1000_hw *hw)
1659 {
1660         uint32_t rx_buf_size;
1661         int diag;
1662
1663         /* Let the firmware know the OS is in control */
1664         igb_hw_control_acquire(hw);
1665
1666         /*
1667          * These parameters control the automatic generation (Tx) and
1668          * response (Rx) to Ethernet PAUSE frames.
1669          * - High water mark should allow for at least two standard size (1518)
1670          *   frames to be received after sending an XOFF.
1671          * - Low water mark works best when it is very near the high water mark.
1672          *   This allows the receiver to restart by sending XON when it has
1673          *   drained a bit. Here we use an arbitrary value of 1500 which will
1674          *   restart after one full frame is pulled from the buffer. There
1675          *   could be several smaller frames in the buffer and if so they will
1676          *   not trigger the XON until their total number reduces the buffer
1677          *   by 1500.
1678          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1679          */
1680         rx_buf_size = igb_get_rx_buffer_size(hw);
1681
1682         hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1683         hw->fc.low_water = hw->fc.high_water - 1500;
1684         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1685         hw->fc.send_xon = 1;
1686
1687         /* Set Flow control, use the tunable location if sane */
1688         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1689                 hw->fc.requested_mode = igb_fc_setting;
1690         else
1691                 hw->fc.requested_mode = e1000_fc_none;
1692
1693         /* Issue a global reset */
1694         igb_pf_reset_hw(hw);
1695         E1000_WRITE_REG(hw, E1000_WUC, 0);
1696
1697         diag = e1000_init_hw(hw);
1698         if (diag < 0)
1699                 return diag;
1700
1701         E1000_WRITE_REG(hw, E1000_VET,
1702                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1703         e1000_get_phy_info(hw);
1704         e1000_check_for_link(hw);
1705
1706         return 0;
1707 }
1708
1709 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1710 static void
1711 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1712 {
1713         int pause_frames;
1714
1715         uint64_t old_gprc  = stats->gprc;
1716         uint64_t old_gptc  = stats->gptc;
1717         uint64_t old_tpr   = stats->tpr;
1718         uint64_t old_tpt   = stats->tpt;
1719         uint64_t old_rpthc = stats->rpthc;
1720         uint64_t old_hgptc = stats->hgptc;
1721
1722         if(hw->phy.media_type == e1000_media_type_copper ||
1723             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1724                 stats->symerrs +=
1725                     E1000_READ_REG(hw,E1000_SYMERRS);
1726                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1727         }
1728
1729         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1730         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1731         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1732         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1733
1734         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1735         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1736         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1737         stats->dc += E1000_READ_REG(hw, E1000_DC);
1738         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1739         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1740         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1741         /*
1742         ** For watchdog management we need to know if we have been
1743         ** paused during the last interval, so capture that here.
1744         */
1745         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1746         stats->xoffrxc += pause_frames;
1747         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1748         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1749         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1750         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1751         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1752         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1753         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1754         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1755         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1756         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1757         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1758         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1759
1760         /* For the 64-bit byte counters the low dword must be read first. */
1761         /* Both registers clear on the read of the high dword */
1762
1763         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1764         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1765         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1766         stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1767         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1768         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1769         stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1770
1771         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1772         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1773         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1774         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1775         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1776
1777         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1778         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1779
1780         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1781         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1782         stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1783         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1784         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1785         stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1786
1787         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1788         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1789         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1790         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1791         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1792         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1793         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1794         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1795
1796         /* Interrupt Counts */
1797
1798         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1799         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1800         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1801         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1802         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1803         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1804         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1805         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1806         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1807
1808         /* Host to Card Statistics */
1809
1810         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1811         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1812         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1813         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1814         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1815         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1816         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1817         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1818         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1819         stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1820         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1821         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1822         stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1823         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1824         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1825         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1826
1827         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1828         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1829         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1830         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1831         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1832         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1833 }
1834
1835 static int
1836 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1837 {
1838         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1839         struct e1000_hw_stats *stats =
1840                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1841
1842         igb_read_stats_registers(hw, stats);
1843
1844         if (rte_stats == NULL)
1845                 return -EINVAL;
1846
1847         /* Rx Errors */
1848         rte_stats->imissed = stats->mpc;
1849         rte_stats->ierrors = stats->crcerrs +
1850                              stats->rlec + stats->ruc + stats->roc +
1851                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1852
1853         /* Tx Errors */
1854         rte_stats->oerrors = stats->ecol + stats->latecol;
1855
1856         rte_stats->ipackets = stats->gprc;
1857         rte_stats->opackets = stats->gptc;
1858         rte_stats->ibytes   = stats->gorc;
1859         rte_stats->obytes   = stats->gotc;
1860         return 0;
1861 }
1862
1863 static int
1864 eth_igb_stats_reset(struct rte_eth_dev *dev)
1865 {
1866         struct e1000_hw_stats *hw_stats =
1867                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1868
1869         /* HW registers are cleared on read */
1870         eth_igb_stats_get(dev, NULL);
1871
1872         /* Reset software totals */
1873         memset(hw_stats, 0, sizeof(*hw_stats));
1874
1875         return 0;
1876 }
1877
1878 static int
1879 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1880 {
1881         struct e1000_hw_stats *stats =
1882                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1883
1884         /* HW registers are cleared on read */
1885         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1886
1887         /* Reset software totals */
1888         memset(stats, 0, sizeof(*stats));
1889
1890         return 0;
1891 }
1892
1893 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1894         struct rte_eth_xstat_name *xstats_names,
1895         __rte_unused unsigned int size)
1896 {
1897         unsigned i;
1898
1899         if (xstats_names == NULL)
1900                 return IGB_NB_XSTATS;
1901
1902         /* Note: limit checked in rte_eth_xstats_names() */
1903
1904         for (i = 0; i < IGB_NB_XSTATS; i++) {
1905                 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1906                         sizeof(xstats_names[i].name));
1907         }
1908
1909         return IGB_NB_XSTATS;
1910 }
1911
1912 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1913                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1914                 unsigned int limit)
1915 {
1916         unsigned int i;
1917
1918         if (!ids) {
1919                 if (xstats_names == NULL)
1920                         return IGB_NB_XSTATS;
1921
1922                 for (i = 0; i < IGB_NB_XSTATS; i++)
1923                         strlcpy(xstats_names[i].name,
1924                                 rte_igb_stats_strings[i].name,
1925                                 sizeof(xstats_names[i].name));
1926
1927                 return IGB_NB_XSTATS;
1928
1929         } else {
1930                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1931
1932                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1933                                 IGB_NB_XSTATS);
1934
1935                 for (i = 0; i < limit; i++) {
1936                         if (ids[i] >= IGB_NB_XSTATS) {
1937                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1938                                 return -1;
1939                         }
1940                         strcpy(xstats_names[i].name,
1941                                         xstats_names_copy[ids[i]].name);
1942                 }
1943                 return limit;
1944         }
1945 }
1946
1947 static int
1948 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1949                    unsigned n)
1950 {
1951         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1952         struct e1000_hw_stats *hw_stats =
1953                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1954         unsigned i;
1955
1956         if (n < IGB_NB_XSTATS)
1957                 return IGB_NB_XSTATS;
1958
1959         igb_read_stats_registers(hw, hw_stats);
1960
1961         /* If this is a reset xstats is NULL, and we have cleared the
1962          * registers by reading them.
1963          */
1964         if (!xstats)
1965                 return 0;
1966
1967         /* Extended stats */
1968         for (i = 0; i < IGB_NB_XSTATS; i++) {
1969                 xstats[i].id = i;
1970                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1971                         rte_igb_stats_strings[i].offset);
1972         }
1973
1974         return IGB_NB_XSTATS;
1975 }
1976
1977 static int
1978 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1979                 uint64_t *values, unsigned int n)
1980 {
1981         unsigned int i;
1982
1983         if (!ids) {
1984                 struct e1000_hw *hw =
1985                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1986                 struct e1000_hw_stats *hw_stats =
1987                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1988
1989                 if (n < IGB_NB_XSTATS)
1990                         return IGB_NB_XSTATS;
1991
1992                 igb_read_stats_registers(hw, hw_stats);
1993
1994                 /* If this is a reset xstats is NULL, and we have cleared the
1995                  * registers by reading them.
1996                  */
1997                 if (!values)
1998                         return 0;
1999
2000                 /* Extended stats */
2001                 for (i = 0; i < IGB_NB_XSTATS; i++)
2002                         values[i] = *(uint64_t *)(((char *)hw_stats) +
2003                                         rte_igb_stats_strings[i].offset);
2004
2005                 return IGB_NB_XSTATS;
2006
2007         } else {
2008                 uint64_t values_copy[IGB_NB_XSTATS];
2009
2010                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2011                                 IGB_NB_XSTATS);
2012
2013                 for (i = 0; i < n; i++) {
2014                         if (ids[i] >= IGB_NB_XSTATS) {
2015                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2016                                 return -1;
2017                         }
2018                         values[i] = values_copy[ids[i]];
2019                 }
2020                 return n;
2021         }
2022 }
2023
2024 static void
2025 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2026 {
2027         /* Good Rx packets, include VF loopback */
2028         UPDATE_VF_STAT(E1000_VFGPRC,
2029             hw_stats->last_gprc, hw_stats->gprc);
2030
2031         /* Good Rx octets, include VF loopback */
2032         UPDATE_VF_STAT(E1000_VFGORC,
2033             hw_stats->last_gorc, hw_stats->gorc);
2034
2035         /* Good Tx packets, include VF loopback */
2036         UPDATE_VF_STAT(E1000_VFGPTC,
2037             hw_stats->last_gptc, hw_stats->gptc);
2038
2039         /* Good Tx octets, include VF loopback */
2040         UPDATE_VF_STAT(E1000_VFGOTC,
2041             hw_stats->last_gotc, hw_stats->gotc);
2042
2043         /* Rx Multicst packets */
2044         UPDATE_VF_STAT(E1000_VFMPRC,
2045             hw_stats->last_mprc, hw_stats->mprc);
2046
2047         /* Good Rx loopback packets */
2048         UPDATE_VF_STAT(E1000_VFGPRLBC,
2049             hw_stats->last_gprlbc, hw_stats->gprlbc);
2050
2051         /* Good Rx loopback octets */
2052         UPDATE_VF_STAT(E1000_VFGORLBC,
2053             hw_stats->last_gorlbc, hw_stats->gorlbc);
2054
2055         /* Good Tx loopback packets */
2056         UPDATE_VF_STAT(E1000_VFGPTLBC,
2057             hw_stats->last_gptlbc, hw_stats->gptlbc);
2058
2059         /* Good Tx loopback octets */
2060         UPDATE_VF_STAT(E1000_VFGOTLBC,
2061             hw_stats->last_gotlbc, hw_stats->gotlbc);
2062 }
2063
2064 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2065                                      struct rte_eth_xstat_name *xstats_names,
2066                                      __rte_unused unsigned limit)
2067 {
2068         unsigned i;
2069
2070         if (xstats_names != NULL)
2071                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2072                         strlcpy(xstats_names[i].name,
2073                                 rte_igbvf_stats_strings[i].name,
2074                                 sizeof(xstats_names[i].name));
2075                 }
2076         return IGBVF_NB_XSTATS;
2077 }
2078
2079 static int
2080 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2081                      unsigned n)
2082 {
2083         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2085                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2086         unsigned i;
2087
2088         if (n < IGBVF_NB_XSTATS)
2089                 return IGBVF_NB_XSTATS;
2090
2091         igbvf_read_stats_registers(hw, hw_stats);
2092
2093         if (!xstats)
2094                 return 0;
2095
2096         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2097                 xstats[i].id = i;
2098                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2099                         rte_igbvf_stats_strings[i].offset);
2100         }
2101
2102         return IGBVF_NB_XSTATS;
2103 }
2104
2105 static int
2106 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2107 {
2108         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2109         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2110                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2111
2112         igbvf_read_stats_registers(hw, hw_stats);
2113
2114         if (rte_stats == NULL)
2115                 return -EINVAL;
2116
2117         rte_stats->ipackets = hw_stats->gprc;
2118         rte_stats->ibytes = hw_stats->gorc;
2119         rte_stats->opackets = hw_stats->gptc;
2120         rte_stats->obytes = hw_stats->gotc;
2121         return 0;
2122 }
2123
2124 static int
2125 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2126 {
2127         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2128                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2129
2130         /* Sync HW register to the last stats */
2131         eth_igbvf_stats_get(dev, NULL);
2132
2133         /* reset HW current stats*/
2134         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2135                offsetof(struct e1000_vf_stats, gprc));
2136
2137         return 0;
2138 }
2139
2140 static int
2141 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2142                        size_t fw_size)
2143 {
2144         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2145         struct e1000_fw_version fw;
2146         int ret;
2147
2148         e1000_get_fw_version(hw, &fw);
2149
2150         switch (hw->mac.type) {
2151         case e1000_i210:
2152         case e1000_i211:
2153                 if (!(e1000_get_flash_presence_i210(hw))) {
2154                         ret = snprintf(fw_version, fw_size,
2155                                  "%2d.%2d-%d",
2156                                  fw.invm_major, fw.invm_minor,
2157                                  fw.invm_img_type);
2158                         break;
2159                 }
2160                 /* fall through */
2161         default:
2162                 /* if option rom is valid, display its version too */
2163                 if (fw.or_valid) {
2164                         ret = snprintf(fw_version, fw_size,
2165                                  "%d.%d, 0x%08x, %d.%d.%d",
2166                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2167                                  fw.or_major, fw.or_build, fw.or_patch);
2168                 /* no option rom */
2169                 } else {
2170                         if (fw.etrack_id != 0X0000) {
2171                                 ret = snprintf(fw_version, fw_size,
2172                                          "%d.%d, 0x%08x",
2173                                          fw.eep_major, fw.eep_minor,
2174                                          fw.etrack_id);
2175                         } else {
2176                                 ret = snprintf(fw_version, fw_size,
2177                                          "%d.%d.%d",
2178                                          fw.eep_major, fw.eep_minor,
2179                                          fw.eep_build);
2180                         }
2181                 }
2182                 break;
2183         }
2184
2185         ret += 1; /* add the size of '\0' */
2186         if (fw_size < (u32)ret)
2187                 return ret;
2188         else
2189                 return 0;
2190 }
2191
2192 static int
2193 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2194 {
2195         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2196
2197         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2198         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2199         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2200         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2201         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2202                                     dev_info->rx_queue_offload_capa;
2203         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2204         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2205                                     dev_info->tx_queue_offload_capa;
2206
2207         switch (hw->mac.type) {
2208         case e1000_82575:
2209                 dev_info->max_rx_queues = 4;
2210                 dev_info->max_tx_queues = 4;
2211                 dev_info->max_vmdq_pools = 0;
2212                 break;
2213
2214         case e1000_82576:
2215                 dev_info->max_rx_queues = 16;
2216                 dev_info->max_tx_queues = 16;
2217                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2218                 dev_info->vmdq_queue_num = 16;
2219                 break;
2220
2221         case e1000_82580:
2222                 dev_info->max_rx_queues = 8;
2223                 dev_info->max_tx_queues = 8;
2224                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2225                 dev_info->vmdq_queue_num = 8;
2226                 break;
2227
2228         case e1000_i350:
2229                 dev_info->max_rx_queues = 8;
2230                 dev_info->max_tx_queues = 8;
2231                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2232                 dev_info->vmdq_queue_num = 8;
2233                 break;
2234
2235         case e1000_i354:
2236                 dev_info->max_rx_queues = 8;
2237                 dev_info->max_tx_queues = 8;
2238                 break;
2239
2240         case e1000_i210:
2241                 dev_info->max_rx_queues = 4;
2242                 dev_info->max_tx_queues = 4;
2243                 dev_info->max_vmdq_pools = 0;
2244                 break;
2245
2246         case e1000_i211:
2247                 dev_info->max_rx_queues = 2;
2248                 dev_info->max_tx_queues = 2;
2249                 dev_info->max_vmdq_pools = 0;
2250                 break;
2251
2252         default:
2253                 /* Should not happen */
2254                 return -EINVAL;
2255         }
2256         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2257         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2258         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2259
2260         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2261                 .rx_thresh = {
2262                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2263                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2264                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2265                 },
2266                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2267                 .rx_drop_en = 0,
2268                 .offloads = 0,
2269         };
2270
2271         dev_info->default_txconf = (struct rte_eth_txconf) {
2272                 .tx_thresh = {
2273                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2274                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2275                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2276                 },
2277                 .offloads = 0,
2278         };
2279
2280         dev_info->rx_desc_lim = rx_desc_lim;
2281         dev_info->tx_desc_lim = tx_desc_lim;
2282
2283         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2284                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2285                         ETH_LINK_SPEED_1G;
2286
2287         dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2288         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2289
2290         return 0;
2291 }
2292
2293 static const uint32_t *
2294 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2295 {
2296         static const uint32_t ptypes[] = {
2297                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2298                 RTE_PTYPE_L2_ETHER,
2299                 RTE_PTYPE_L3_IPV4,
2300                 RTE_PTYPE_L3_IPV4_EXT,
2301                 RTE_PTYPE_L3_IPV6,
2302                 RTE_PTYPE_L3_IPV6_EXT,
2303                 RTE_PTYPE_L4_TCP,
2304                 RTE_PTYPE_L4_UDP,
2305                 RTE_PTYPE_L4_SCTP,
2306                 RTE_PTYPE_TUNNEL_IP,
2307                 RTE_PTYPE_INNER_L3_IPV6,
2308                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2309                 RTE_PTYPE_INNER_L4_TCP,
2310                 RTE_PTYPE_INNER_L4_UDP,
2311                 RTE_PTYPE_UNKNOWN
2312         };
2313
2314         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2315             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2316                 return ptypes;
2317         return NULL;
2318 }
2319
2320 static int
2321 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2322 {
2323         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2324
2325         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2326         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2327         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2328         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2329                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2330                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2331                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2332                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2333                                 DEV_TX_OFFLOAD_TCP_TSO;
2334         switch (hw->mac.type) {
2335         case e1000_vfadapt:
2336                 dev_info->max_rx_queues = 2;
2337                 dev_info->max_tx_queues = 2;
2338                 break;
2339         case e1000_vfadapt_i350:
2340                 dev_info->max_rx_queues = 1;
2341                 dev_info->max_tx_queues = 1;
2342                 break;
2343         default:
2344                 /* Should not happen */
2345                 return -EINVAL;
2346         }
2347
2348         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2349         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2350                                     dev_info->rx_queue_offload_capa;
2351         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2352         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2353                                     dev_info->tx_queue_offload_capa;
2354
2355         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2356                 .rx_thresh = {
2357                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2358                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2359                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2360                 },
2361                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2362                 .rx_drop_en = 0,
2363                 .offloads = 0,
2364         };
2365
2366         dev_info->default_txconf = (struct rte_eth_txconf) {
2367                 .tx_thresh = {
2368                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2369                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2370                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2371                 },
2372                 .offloads = 0,
2373         };
2374
2375         dev_info->rx_desc_lim = rx_desc_lim;
2376         dev_info->tx_desc_lim = tx_desc_lim;
2377
2378         return 0;
2379 }
2380
2381 /* return 0 means link status changed, -1 means not changed */
2382 static int
2383 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2384 {
2385         struct e1000_hw *hw =
2386                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2387         struct rte_eth_link link;
2388         int link_check, count;
2389
2390         link_check = 0;
2391         hw->mac.get_link_status = 1;
2392
2393         /* possible wait-to-complete in up to 9 seconds */
2394         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2395                 /* Read the real link status */
2396                 switch (hw->phy.media_type) {
2397                 case e1000_media_type_copper:
2398                         /* Do the work to read phy */
2399                         e1000_check_for_link(hw);
2400                         link_check = !hw->mac.get_link_status;
2401                         break;
2402
2403                 case e1000_media_type_fiber:
2404                         e1000_check_for_link(hw);
2405                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2406                                       E1000_STATUS_LU);
2407                         break;
2408
2409                 case e1000_media_type_internal_serdes:
2410                         e1000_check_for_link(hw);
2411                         link_check = hw->mac.serdes_has_link;
2412                         break;
2413
2414                 /* VF device is type_unknown */
2415                 case e1000_media_type_unknown:
2416                         eth_igbvf_link_update(hw);
2417                         link_check = !hw->mac.get_link_status;
2418                         break;
2419
2420                 default:
2421                         break;
2422                 }
2423                 if (link_check || wait_to_complete == 0)
2424                         break;
2425                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2426         }
2427         memset(&link, 0, sizeof(link));
2428
2429         /* Now we check if a transition has happened */
2430         if (link_check) {
2431                 uint16_t duplex, speed;
2432                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2433                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2434                                 ETH_LINK_FULL_DUPLEX :
2435                                 ETH_LINK_HALF_DUPLEX;
2436                 link.link_speed = speed;
2437                 link.link_status = ETH_LINK_UP;
2438                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2439                                 ETH_LINK_SPEED_FIXED);
2440         } else if (!link_check) {
2441                 link.link_speed = 0;
2442                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2443                 link.link_status = ETH_LINK_DOWN;
2444                 link.link_autoneg = ETH_LINK_FIXED;
2445         }
2446
2447         return rte_eth_linkstatus_set(dev, &link);
2448 }
2449
2450 /*
2451  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2452  * For ASF and Pass Through versions of f/w this means
2453  * that the driver is loaded.
2454  */
2455 static void
2456 igb_hw_control_acquire(struct e1000_hw *hw)
2457 {
2458         uint32_t ctrl_ext;
2459
2460         /* Let firmware know the driver has taken over */
2461         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2462         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2463 }
2464
2465 /*
2466  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2467  * For ASF and Pass Through versions of f/w this means that the
2468  * driver is no longer loaded.
2469  */
2470 static void
2471 igb_hw_control_release(struct e1000_hw *hw)
2472 {
2473         uint32_t ctrl_ext;
2474
2475         /* Let firmware taken over control of h/w */
2476         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2477         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2478                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2479 }
2480
2481 /*
2482  * Bit of a misnomer, what this really means is
2483  * to enable OS management of the system... aka
2484  * to disable special hardware management features.
2485  */
2486 static void
2487 igb_init_manageability(struct e1000_hw *hw)
2488 {
2489         if (e1000_enable_mng_pass_thru(hw)) {
2490                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2491                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2492
2493                 /* disable hardware interception of ARP */
2494                 manc &= ~(E1000_MANC_ARP_EN);
2495
2496                 /* enable receiving management packets to the host */
2497                 manc |= E1000_MANC_EN_MNG2HOST;
2498                 manc2h |= 1 << 5;  /* Mng Port 623 */
2499                 manc2h |= 1 << 6;  /* Mng Port 664 */
2500                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2501                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2502         }
2503 }
2504
2505 static void
2506 igb_release_manageability(struct e1000_hw *hw)
2507 {
2508         if (e1000_enable_mng_pass_thru(hw)) {
2509                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2510
2511                 manc |= E1000_MANC_ARP_EN;
2512                 manc &= ~E1000_MANC_EN_MNG2HOST;
2513
2514                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2515         }
2516 }
2517
2518 static int
2519 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2520 {
2521         struct e1000_hw *hw =
2522                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523         uint32_t rctl;
2524
2525         rctl = E1000_READ_REG(hw, E1000_RCTL);
2526         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2527         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2528
2529         return 0;
2530 }
2531
2532 static int
2533 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2534 {
2535         struct e1000_hw *hw =
2536                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2537         uint32_t rctl;
2538
2539         rctl = E1000_READ_REG(hw, E1000_RCTL);
2540         rctl &= (~E1000_RCTL_UPE);
2541         if (dev->data->all_multicast == 1)
2542                 rctl |= E1000_RCTL_MPE;
2543         else
2544                 rctl &= (~E1000_RCTL_MPE);
2545         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2546
2547         return 0;
2548 }
2549
2550 static int
2551 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2552 {
2553         struct e1000_hw *hw =
2554                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2555         uint32_t rctl;
2556
2557         rctl = E1000_READ_REG(hw, E1000_RCTL);
2558         rctl |= E1000_RCTL_MPE;
2559         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2560
2561         return 0;
2562 }
2563
2564 static int
2565 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2566 {
2567         struct e1000_hw *hw =
2568                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2569         uint32_t rctl;
2570
2571         if (dev->data->promiscuous == 1)
2572                 return 0; /* must remain in all_multicast mode */
2573         rctl = E1000_READ_REG(hw, E1000_RCTL);
2574         rctl &= (~E1000_RCTL_MPE);
2575         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2576
2577         return 0;
2578 }
2579
2580 static int
2581 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2582 {
2583         struct e1000_hw *hw =
2584                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2585         struct e1000_vfta * shadow_vfta =
2586                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2587         uint32_t vfta;
2588         uint32_t vid_idx;
2589         uint32_t vid_bit;
2590
2591         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2592                               E1000_VFTA_ENTRY_MASK);
2593         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2594         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2595         if (on)
2596                 vfta |= vid_bit;
2597         else
2598                 vfta &= ~vid_bit;
2599         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2600
2601         /* update local VFTA copy */
2602         shadow_vfta->vfta[vid_idx] = vfta;
2603
2604         return 0;
2605 }
2606
2607 static int
2608 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2609                       enum rte_vlan_type vlan_type,
2610                       uint16_t tpid)
2611 {
2612         struct e1000_hw *hw =
2613                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2614         uint32_t reg, qinq;
2615
2616         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2617         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2618
2619         /* only outer TPID of double VLAN can be configured*/
2620         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2621                 reg = E1000_READ_REG(hw, E1000_VET);
2622                 reg = (reg & (~E1000_VET_VET_EXT)) |
2623                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2624                 E1000_WRITE_REG(hw, E1000_VET, reg);
2625
2626                 return 0;
2627         }
2628
2629         /* all other TPID values are read-only*/
2630         PMD_DRV_LOG(ERR, "Not supported");
2631
2632         return -ENOTSUP;
2633 }
2634
2635 static void
2636 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2637 {
2638         struct e1000_hw *hw =
2639                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640         uint32_t reg;
2641
2642         /* Filter Table Disable */
2643         reg = E1000_READ_REG(hw, E1000_RCTL);
2644         reg &= ~E1000_RCTL_CFIEN;
2645         reg &= ~E1000_RCTL_VFE;
2646         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2647 }
2648
2649 static void
2650 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2651 {
2652         struct e1000_hw *hw =
2653                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2654         struct e1000_vfta * shadow_vfta =
2655                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2656         uint32_t reg;
2657         int i;
2658
2659         /* Filter Table Enable, CFI not used for packet acceptance */
2660         reg = E1000_READ_REG(hw, E1000_RCTL);
2661         reg &= ~E1000_RCTL_CFIEN;
2662         reg |= E1000_RCTL_VFE;
2663         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2664
2665         /* restore VFTA table */
2666         for (i = 0; i < IGB_VFTA_SIZE; i++)
2667                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2668 }
2669
2670 static void
2671 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2672 {
2673         struct e1000_hw *hw =
2674                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2675         uint32_t reg;
2676
2677         /* VLAN Mode Disable */
2678         reg = E1000_READ_REG(hw, E1000_CTRL);
2679         reg &= ~E1000_CTRL_VME;
2680         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2681 }
2682
2683 static void
2684 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2685 {
2686         struct e1000_hw *hw =
2687                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2688         uint32_t reg;
2689
2690         /* VLAN Mode Enable */
2691         reg = E1000_READ_REG(hw, E1000_CTRL);
2692         reg |= E1000_CTRL_VME;
2693         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2694 }
2695
2696 static void
2697 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2698 {
2699         struct e1000_hw *hw =
2700                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2701         uint32_t reg;
2702
2703         /* CTRL_EXT: Extended VLAN */
2704         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2705         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2706         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2707
2708         /* Update maximum packet length */
2709         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2710                 E1000_WRITE_REG(hw, E1000_RLPML,
2711                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2712                                                 VLAN_TAG_SIZE);
2713 }
2714
2715 static void
2716 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2717 {
2718         struct e1000_hw *hw =
2719                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2720         uint32_t reg;
2721
2722         /* CTRL_EXT: Extended VLAN */
2723         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2724         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2725         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2726
2727         /* Update maximum packet length */
2728         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2729                 E1000_WRITE_REG(hw, E1000_RLPML,
2730                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2731                                                 2 * VLAN_TAG_SIZE);
2732 }
2733
2734 static int
2735 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2736 {
2737         struct rte_eth_rxmode *rxmode;
2738
2739         rxmode = &dev->data->dev_conf.rxmode;
2740         if(mask & ETH_VLAN_STRIP_MASK){
2741                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2742                         igb_vlan_hw_strip_enable(dev);
2743                 else
2744                         igb_vlan_hw_strip_disable(dev);
2745         }
2746
2747         if(mask & ETH_VLAN_FILTER_MASK){
2748                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2749                         igb_vlan_hw_filter_enable(dev);
2750                 else
2751                         igb_vlan_hw_filter_disable(dev);
2752         }
2753
2754         if(mask & ETH_VLAN_EXTEND_MASK){
2755                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2756                         igb_vlan_hw_extend_enable(dev);
2757                 else
2758                         igb_vlan_hw_extend_disable(dev);
2759         }
2760
2761         return 0;
2762 }
2763
2764
2765 /**
2766  * It enables the interrupt mask and then enable the interrupt.
2767  *
2768  * @param dev
2769  *  Pointer to struct rte_eth_dev.
2770  * @param on
2771  *  Enable or Disable
2772  *
2773  * @return
2774  *  - On success, zero.
2775  *  - On failure, a negative value.
2776  */
2777 static int
2778 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2779 {
2780         struct e1000_interrupt *intr =
2781                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2782
2783         if (on)
2784                 intr->mask |= E1000_ICR_LSC;
2785         else
2786                 intr->mask &= ~E1000_ICR_LSC;
2787
2788         return 0;
2789 }
2790
2791 /* It clears the interrupt causes and enables the interrupt.
2792  * It will be called once only during nic initialized.
2793  *
2794  * @param dev
2795  *  Pointer to struct rte_eth_dev.
2796  *
2797  * @return
2798  *  - On success, zero.
2799  *  - On failure, a negative value.
2800  */
2801 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2802 {
2803         uint32_t mask, regval;
2804         int ret;
2805         struct e1000_hw *hw =
2806                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2808         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2809         int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2810         struct rte_eth_dev_info dev_info;
2811
2812         memset(&dev_info, 0, sizeof(dev_info));
2813         ret = eth_igb_infos_get(dev, &dev_info);
2814         if (ret != 0)
2815                 return ret;
2816
2817         mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2818         regval = E1000_READ_REG(hw, E1000_EIMS);
2819         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2820
2821         return 0;
2822 }
2823
2824 /*
2825  * It reads ICR and gets interrupt causes, check it and set a bit flag
2826  * to update link status.
2827  *
2828  * @param dev
2829  *  Pointer to struct rte_eth_dev.
2830  *
2831  * @return
2832  *  - On success, zero.
2833  *  - On failure, a negative value.
2834  */
2835 static int
2836 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2837 {
2838         uint32_t icr;
2839         struct e1000_hw *hw =
2840                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2841         struct e1000_interrupt *intr =
2842                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2843
2844         igb_intr_disable(dev);
2845
2846         /* read-on-clear nic registers here */
2847         icr = E1000_READ_REG(hw, E1000_ICR);
2848
2849         intr->flags = 0;
2850         if (icr & E1000_ICR_LSC) {
2851                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2852         }
2853
2854         if (icr & E1000_ICR_VMMB)
2855                 intr->flags |= E1000_FLAG_MAILBOX;
2856
2857         return 0;
2858 }
2859
2860 /*
2861  * It executes link_update after knowing an interrupt is prsent.
2862  *
2863  * @param dev
2864  *  Pointer to struct rte_eth_dev.
2865  *
2866  * @return
2867  *  - On success, zero.
2868  *  - On failure, a negative value.
2869  */
2870 static int
2871 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2872                          struct rte_intr_handle *intr_handle)
2873 {
2874         struct e1000_hw *hw =
2875                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876         struct e1000_interrupt *intr =
2877                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2878         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2879         struct rte_eth_link link;
2880         int ret;
2881
2882         if (intr->flags & E1000_FLAG_MAILBOX) {
2883                 igb_pf_mbx_process(dev);
2884                 intr->flags &= ~E1000_FLAG_MAILBOX;
2885         }
2886
2887         igb_intr_enable(dev);
2888         rte_intr_ack(intr_handle);
2889
2890         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2891                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2892
2893                 /* set get_link_status to check register later */
2894                 hw->mac.get_link_status = 1;
2895                 ret = eth_igb_link_update(dev, 0);
2896
2897                 /* check if link has changed */
2898                 if (ret < 0)
2899                         return 0;
2900
2901                 rte_eth_linkstatus_get(dev, &link);
2902                 if (link.link_status) {
2903                         PMD_INIT_LOG(INFO,
2904                                      " Port %d: Link Up - speed %u Mbps - %s",
2905                                      dev->data->port_id,
2906                                      (unsigned)link.link_speed,
2907                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2908                                      "full-duplex" : "half-duplex");
2909                 } else {
2910                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2911                                      dev->data->port_id);
2912                 }
2913
2914                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2915                              pci_dev->addr.domain,
2916                              pci_dev->addr.bus,
2917                              pci_dev->addr.devid,
2918                              pci_dev->addr.function);
2919                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2920                                               NULL);
2921         }
2922
2923         return 0;
2924 }
2925
2926 /**
2927  * Interrupt handler which shall be registered at first.
2928  *
2929  * @param handle
2930  *  Pointer to interrupt handle.
2931  * @param param
2932  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2933  *
2934  * @return
2935  *  void
2936  */
2937 static void
2938 eth_igb_interrupt_handler(void *param)
2939 {
2940         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2941
2942         eth_igb_interrupt_get_status(dev);
2943         eth_igb_interrupt_action(dev, dev->intr_handle);
2944 }
2945
2946 static int
2947 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2948 {
2949         uint32_t eicr;
2950         struct e1000_hw *hw =
2951                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952         struct e1000_interrupt *intr =
2953                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2954
2955         igbvf_intr_disable(hw);
2956
2957         /* read-on-clear nic registers here */
2958         eicr = E1000_READ_REG(hw, E1000_EICR);
2959         intr->flags = 0;
2960
2961         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2962                 intr->flags |= E1000_FLAG_MAILBOX;
2963
2964         return 0;
2965 }
2966
2967 void igbvf_mbx_process(struct rte_eth_dev *dev)
2968 {
2969         struct e1000_hw *hw =
2970                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971         struct e1000_mbx_info *mbx = &hw->mbx;
2972         u32 in_msg = 0;
2973
2974         /* peek the message first */
2975         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2976
2977         /* PF reset VF event */
2978         if (in_msg == E1000_PF_CONTROL_MSG) {
2979                 /* dummy mbx read to ack pf */
2980                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2981                         return;
2982                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2983                                               NULL);
2984         }
2985 }
2986
2987 static int
2988 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2989 {
2990         struct e1000_interrupt *intr =
2991                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2992
2993         if (intr->flags & E1000_FLAG_MAILBOX) {
2994                 igbvf_mbx_process(dev);
2995                 intr->flags &= ~E1000_FLAG_MAILBOX;
2996         }
2997
2998         igbvf_intr_enable(dev);
2999         rte_intr_ack(intr_handle);
3000
3001         return 0;
3002 }
3003
3004 static void
3005 eth_igbvf_interrupt_handler(void *param)
3006 {
3007         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3008
3009         eth_igbvf_interrupt_get_status(dev);
3010         eth_igbvf_interrupt_action(dev, dev->intr_handle);
3011 }
3012
3013 static int
3014 eth_igb_led_on(struct rte_eth_dev *dev)
3015 {
3016         struct e1000_hw *hw;
3017
3018         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3019         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3020 }
3021
3022 static int
3023 eth_igb_led_off(struct rte_eth_dev *dev)
3024 {
3025         struct e1000_hw *hw;
3026
3027         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3028         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3029 }
3030
3031 static int
3032 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3033 {
3034         struct e1000_hw *hw;
3035         uint32_t ctrl;
3036         int tx_pause;
3037         int rx_pause;
3038
3039         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3040         fc_conf->pause_time = hw->fc.pause_time;
3041         fc_conf->high_water = hw->fc.high_water;
3042         fc_conf->low_water = hw->fc.low_water;
3043         fc_conf->send_xon = hw->fc.send_xon;
3044         fc_conf->autoneg = hw->mac.autoneg;
3045
3046         /*
3047          * Return rx_pause and tx_pause status according to actual setting of
3048          * the TFCE and RFCE bits in the CTRL register.
3049          */
3050         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3051         if (ctrl & E1000_CTRL_TFCE)
3052                 tx_pause = 1;
3053         else
3054                 tx_pause = 0;
3055
3056         if (ctrl & E1000_CTRL_RFCE)
3057                 rx_pause = 1;
3058         else
3059                 rx_pause = 0;
3060
3061         if (rx_pause && tx_pause)
3062                 fc_conf->mode = RTE_FC_FULL;
3063         else if (rx_pause)
3064                 fc_conf->mode = RTE_FC_RX_PAUSE;
3065         else if (tx_pause)
3066                 fc_conf->mode = RTE_FC_TX_PAUSE;
3067         else
3068                 fc_conf->mode = RTE_FC_NONE;
3069
3070         return 0;
3071 }
3072
3073 static int
3074 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3075 {
3076         struct e1000_hw *hw;
3077         int err;
3078         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3079                 e1000_fc_none,
3080                 e1000_fc_rx_pause,
3081                 e1000_fc_tx_pause,
3082                 e1000_fc_full
3083         };
3084         uint32_t rx_buf_size;
3085         uint32_t max_high_water;
3086         uint32_t rctl;
3087
3088         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3089         if (fc_conf->autoneg != hw->mac.autoneg)
3090                 return -ENOTSUP;
3091         rx_buf_size = igb_get_rx_buffer_size(hw);
3092         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3093
3094         /* At least reserve one Ethernet frame for watermark */
3095         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3096         if ((fc_conf->high_water > max_high_water) ||
3097             (fc_conf->high_water < fc_conf->low_water)) {
3098                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3099                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3100                 return -EINVAL;
3101         }
3102
3103         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3104         hw->fc.pause_time     = fc_conf->pause_time;
3105         hw->fc.high_water     = fc_conf->high_water;
3106         hw->fc.low_water      = fc_conf->low_water;
3107         hw->fc.send_xon       = fc_conf->send_xon;
3108
3109         err = e1000_setup_link_generic(hw);
3110         if (err == E1000_SUCCESS) {
3111
3112                 /* check if we want to forward MAC frames - driver doesn't have native
3113                  * capability to do that, so we'll write the registers ourselves */
3114
3115                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3116
3117                 /* set or clear MFLCN.PMCF bit depending on configuration */
3118                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3119                         rctl |= E1000_RCTL_PMCF;
3120                 else
3121                         rctl &= ~E1000_RCTL_PMCF;
3122
3123                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3124                 E1000_WRITE_FLUSH(hw);
3125
3126                 return 0;
3127         }
3128
3129         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3130         return -EIO;
3131 }
3132
3133 #define E1000_RAH_POOLSEL_SHIFT      (18)
3134 static int
3135 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3136                 uint32_t index, uint32_t pool)
3137 {
3138         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3139         uint32_t rah;
3140
3141         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3142         rah = E1000_READ_REG(hw, E1000_RAH(index));
3143         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3144         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3145         return 0;
3146 }
3147
3148 static void
3149 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3150 {
3151         uint8_t addr[RTE_ETHER_ADDR_LEN];
3152         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3153
3154         memset(addr, 0, sizeof(addr));
3155
3156         e1000_rar_set(hw, addr, index);
3157 }
3158
3159 static int
3160 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3161                                 struct rte_ether_addr *addr)
3162 {
3163         eth_igb_rar_clear(dev, 0);
3164         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3165
3166         return 0;
3167 }
3168 /*
3169  * Virtual Function operations
3170  */
3171 static void
3172 igbvf_intr_disable(struct e1000_hw *hw)
3173 {
3174         PMD_INIT_FUNC_TRACE();
3175
3176         /* Clear interrupt mask to stop from interrupts being generated */
3177         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3178
3179         E1000_WRITE_FLUSH(hw);
3180 }
3181
3182 static void
3183 igbvf_stop_adapter(struct rte_eth_dev *dev)
3184 {
3185         u32 reg_val;
3186         u16 i;
3187         struct rte_eth_dev_info dev_info;
3188         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3189         int ret;
3190
3191         memset(&dev_info, 0, sizeof(dev_info));
3192         ret = eth_igbvf_infos_get(dev, &dev_info);
3193         if (ret != 0)
3194                 return;
3195
3196         /* Clear interrupt mask to stop from interrupts being generated */
3197         igbvf_intr_disable(hw);
3198
3199         /* Clear any pending interrupts, flush previous writes */
3200         E1000_READ_REG(hw, E1000_EICR);
3201
3202         /* Disable the transmit unit.  Each queue must be disabled. */
3203         for (i = 0; i < dev_info.max_tx_queues; i++)
3204                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3205
3206         /* Disable the receive unit by stopping each queue */
3207         for (i = 0; i < dev_info.max_rx_queues; i++) {
3208                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3209                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3210                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3211                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3212                         ;
3213         }
3214
3215         /* flush all queues disables */
3216         E1000_WRITE_FLUSH(hw);
3217         msec_delay(2);
3218 }
3219
3220 static int eth_igbvf_link_update(struct e1000_hw *hw)
3221 {
3222         struct e1000_mbx_info *mbx = &hw->mbx;
3223         struct e1000_mac_info *mac = &hw->mac;
3224         int ret_val = E1000_SUCCESS;
3225
3226         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3227
3228         /*
3229          * We only want to run this if there has been a rst asserted.
3230          * in this case that could mean a link change, device reset,
3231          * or a virtual function reset
3232          */
3233
3234         /* If we were hit with a reset or timeout drop the link */
3235         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3236                 mac->get_link_status = TRUE;
3237
3238         if (!mac->get_link_status)
3239                 goto out;
3240
3241         /* if link status is down no point in checking to see if pf is up */
3242         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3243                 goto out;
3244
3245         /* if we passed all the tests above then the link is up and we no
3246          * longer need to check for link */
3247         mac->get_link_status = FALSE;
3248
3249 out:
3250         return ret_val;
3251 }
3252
3253
3254 static int
3255 igbvf_dev_configure(struct rte_eth_dev *dev)
3256 {
3257         struct rte_eth_conf* conf = &dev->data->dev_conf;
3258
3259         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3260                      dev->data->port_id);
3261
3262         dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3263
3264         /*
3265          * VF has no ability to enable/disable HW CRC
3266          * Keep the persistent behavior the same as Host PF
3267          */
3268 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3269         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3270                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3271                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3272         }
3273 #else
3274         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3275                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3276                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3277         }
3278 #endif
3279
3280         return 0;
3281 }
3282
3283 static int
3284 igbvf_dev_start(struct rte_eth_dev *dev)
3285 {
3286         struct e1000_hw *hw =
3287                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288         struct e1000_adapter *adapter =
3289                 E1000_DEV_PRIVATE(dev->data->dev_private);
3290         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3291         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3292         int ret;
3293         uint32_t intr_vector = 0;
3294
3295         PMD_INIT_FUNC_TRACE();
3296
3297         hw->mac.ops.reset_hw(hw);
3298         adapter->stopped = 0;
3299
3300         /* Set all vfta */
3301         igbvf_set_vfta_all(dev,1);
3302
3303         eth_igbvf_tx_init(dev);
3304
3305         /* This can fail when allocating mbufs for descriptor rings */
3306         ret = eth_igbvf_rx_init(dev);
3307         if (ret) {
3308                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3309                 igb_dev_clear_queues(dev);
3310                 return ret;
3311         }
3312
3313         /* check and configure queue intr-vector mapping */
3314         if (rte_intr_cap_multiple(intr_handle) &&
3315             dev->data->dev_conf.intr_conf.rxq) {
3316                 intr_vector = dev->data->nb_rx_queues;
3317                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3318                 if (ret)
3319                         return ret;
3320         }
3321
3322         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3323                 intr_handle->intr_vec =
3324                         rte_zmalloc("intr_vec",
3325                                     dev->data->nb_rx_queues * sizeof(int), 0);
3326                 if (!intr_handle->intr_vec) {
3327                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3328                                      " intr_vec", dev->data->nb_rx_queues);
3329                         return -ENOMEM;
3330                 }
3331         }
3332
3333         eth_igbvf_configure_msix_intr(dev);
3334
3335         /* enable uio/vfio intr/eventfd mapping */
3336         rte_intr_enable(intr_handle);
3337
3338         /* resume enabled intr since hw reset */
3339         igbvf_intr_enable(dev);
3340
3341         return 0;
3342 }
3343
3344 static void
3345 igbvf_dev_stop(struct rte_eth_dev *dev)
3346 {
3347         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3348         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3349         struct e1000_adapter *adapter =
3350                 E1000_DEV_PRIVATE(dev->data->dev_private);
3351
3352         if (adapter->stopped)
3353                 return;
3354
3355         PMD_INIT_FUNC_TRACE();
3356
3357         igbvf_stop_adapter(dev);
3358
3359         /*
3360           * Clear what we set, but we still keep shadow_vfta to
3361           * restore after device starts
3362           */
3363         igbvf_set_vfta_all(dev,0);
3364
3365         igb_dev_clear_queues(dev);
3366
3367         /* disable intr eventfd mapping */
3368         rte_intr_disable(intr_handle);
3369
3370         /* Clean datapath event and queue/vec mapping */
3371         rte_intr_efd_disable(intr_handle);
3372         if (intr_handle->intr_vec) {
3373                 rte_free(intr_handle->intr_vec);
3374                 intr_handle->intr_vec = NULL;
3375         }
3376
3377         adapter->stopped = true;
3378 }
3379
3380 static void
3381 igbvf_dev_close(struct rte_eth_dev *dev)
3382 {
3383         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3384         struct rte_ether_addr addr;
3385         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3386
3387         PMD_INIT_FUNC_TRACE();
3388
3389         e1000_reset_hw(hw);
3390
3391         igbvf_dev_stop(dev);
3392
3393         igb_dev_free_queues(dev);
3394
3395         /**
3396          * reprogram the RAR with a zero mac address,
3397          * to ensure that the VF traffic goes to the PF
3398          * after stop, close and detach of the VF.
3399          **/
3400
3401         memset(&addr, 0, sizeof(addr));
3402         igbvf_default_mac_addr_set(dev, &addr);
3403
3404         dev->dev_ops = NULL;
3405         dev->rx_pkt_burst = NULL;
3406         dev->tx_pkt_burst = NULL;
3407
3408         rte_intr_callback_unregister(&pci_dev->intr_handle,
3409                                      eth_igbvf_interrupt_handler,
3410                                      (void *)dev);
3411 }
3412
3413 static int
3414 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3415 {
3416         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3417
3418         /* Set both unicast and multicast promisc */
3419         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3420
3421         return 0;
3422 }
3423
3424 static int
3425 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3426 {
3427         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3428
3429         /* If in allmulticast mode leave multicast promisc */
3430         if (dev->data->all_multicast == 1)
3431                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3432         else
3433                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3434
3435         return 0;
3436 }
3437
3438 static int
3439 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3440 {
3441         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3442
3443         /* In promiscuous mode multicast promisc already set */
3444         if (dev->data->promiscuous == 0)
3445                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3446
3447         return 0;
3448 }
3449
3450 static int
3451 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3452 {
3453         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3454
3455         /* In promiscuous mode leave multicast promisc enabled */
3456         if (dev->data->promiscuous == 0)
3457                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3458
3459         return 0;
3460 }
3461
3462 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3463 {
3464         struct e1000_mbx_info *mbx = &hw->mbx;
3465         uint32_t msgbuf[2];
3466         s32 err;
3467
3468         /* After set vlan, vlan strip will also be enabled in igb driver*/
3469         msgbuf[0] = E1000_VF_SET_VLAN;
3470         msgbuf[1] = vid;
3471         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3472         if (on)
3473                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3474
3475         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3476         if (err)
3477                 goto mbx_err;
3478
3479         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3480         if (err)
3481                 goto mbx_err;
3482
3483         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3484         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3485                 err = -EINVAL;
3486
3487 mbx_err:
3488         return err;
3489 }
3490
3491 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3492 {
3493         struct e1000_hw *hw =
3494                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3495         struct e1000_vfta * shadow_vfta =
3496                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3497         int i = 0, j = 0, vfta = 0, mask = 1;
3498
3499         for (i = 0; i < IGB_VFTA_SIZE; i++){
3500                 vfta = shadow_vfta->vfta[i];
3501                 if(vfta){
3502                         mask = 1;
3503                         for (j = 0; j < 32; j++){
3504                                 if(vfta & mask)
3505                                         igbvf_set_vfta(hw,
3506                                                 (uint16_t)((i<<5)+j), on);
3507                                 mask<<=1;
3508                         }
3509                 }
3510         }
3511
3512 }
3513
3514 static int
3515 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3516 {
3517         struct e1000_hw *hw =
3518                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3519         struct e1000_vfta * shadow_vfta =
3520                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3521         uint32_t vid_idx = 0;
3522         uint32_t vid_bit = 0;
3523         int ret = 0;
3524
3525         PMD_INIT_FUNC_TRACE();
3526
3527         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3528         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3529         if(ret){
3530                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3531                 return ret;
3532         }
3533         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3534         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3535
3536         /*Save what we set and retore it after device reset*/
3537         if (on)
3538                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3539         else
3540                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3541
3542         return 0;
3543 }
3544
3545 static int
3546 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3547 {
3548         struct e1000_hw *hw =
3549                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3550
3551         /* index is not used by rar_set() */
3552         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3553         return 0;
3554 }
3555
3556
3557 static int
3558 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3559                         struct rte_eth_rss_reta_entry64 *reta_conf,
3560                         uint16_t reta_size)
3561 {
3562         uint8_t i, j, mask;
3563         uint32_t reta, r;
3564         uint16_t idx, shift;
3565         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3566
3567         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3568                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3569                         "(%d) doesn't match the number hardware can supported "
3570                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3571                 return -EINVAL;
3572         }
3573
3574         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3575                 idx = i / RTE_RETA_GROUP_SIZE;
3576                 shift = i % RTE_RETA_GROUP_SIZE;
3577                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3578                                                 IGB_4_BIT_MASK);
3579                 if (!mask)
3580                         continue;
3581                 if (mask == IGB_4_BIT_MASK)
3582                         r = 0;
3583                 else
3584                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3585                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3586                         if (mask & (0x1 << j))
3587                                 reta |= reta_conf[idx].reta[shift + j] <<
3588                                                         (CHAR_BIT * j);
3589                         else
3590                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3591                 }
3592                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3593         }
3594
3595         return 0;
3596 }
3597
3598 static int
3599 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3600                        struct rte_eth_rss_reta_entry64 *reta_conf,
3601                        uint16_t reta_size)
3602 {
3603         uint8_t i, j, mask;
3604         uint32_t reta;
3605         uint16_t idx, shift;
3606         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3607
3608         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3609                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3610                         "(%d) doesn't match the number hardware can supported "
3611                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3612                 return -EINVAL;
3613         }
3614
3615         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3616                 idx = i / RTE_RETA_GROUP_SIZE;
3617                 shift = i % RTE_RETA_GROUP_SIZE;
3618                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3619                                                 IGB_4_BIT_MASK);
3620                 if (!mask)
3621                         continue;
3622                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3623                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3624                         if (mask & (0x1 << j))
3625                                 reta_conf[idx].reta[shift + j] =
3626                                         ((reta >> (CHAR_BIT * j)) &
3627                                                 IGB_8_BIT_MASK);
3628                 }
3629         }
3630
3631         return 0;
3632 }
3633
3634 int
3635 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3636                         struct rte_eth_syn_filter *filter,
3637                         bool add)
3638 {
3639         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3640         struct e1000_filter_info *filter_info =
3641                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3642         uint32_t synqf, rfctl;
3643
3644         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3645                 return -EINVAL;
3646
3647         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3648
3649         if (add) {
3650                 if (synqf & E1000_SYN_FILTER_ENABLE)
3651                         return -EINVAL;
3652
3653                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3654                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3655
3656                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3657                 if (filter->hig_pri)
3658                         rfctl |= E1000_RFCTL_SYNQFP;
3659                 else
3660                         rfctl &= ~E1000_RFCTL_SYNQFP;
3661
3662                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3663         } else {
3664                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3665                         return -ENOENT;
3666                 synqf = 0;
3667         }
3668
3669         filter_info->syn_info = synqf;
3670         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3671         E1000_WRITE_FLUSH(hw);
3672         return 0;
3673 }
3674
3675 static int
3676 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3677                         struct rte_eth_syn_filter *filter)
3678 {
3679         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3680         uint32_t synqf, rfctl;
3681
3682         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3683         if (synqf & E1000_SYN_FILTER_ENABLE) {
3684                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3685                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3686                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3687                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3688                 return 0;
3689         }
3690
3691         return -ENOENT;
3692 }
3693
3694 static int
3695 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3696                         enum rte_filter_op filter_op,
3697                         void *arg)
3698 {
3699         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3700         int ret;
3701
3702         MAC_TYPE_FILTER_SUP(hw->mac.type);
3703
3704         if (filter_op == RTE_ETH_FILTER_NOP)
3705                 return 0;
3706
3707         if (arg == NULL) {
3708                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3709                             filter_op);
3710                 return -EINVAL;
3711         }
3712
3713         switch (filter_op) {
3714         case RTE_ETH_FILTER_ADD:
3715                 ret = eth_igb_syn_filter_set(dev,
3716                                 (struct rte_eth_syn_filter *)arg,
3717                                 TRUE);
3718                 break;
3719         case RTE_ETH_FILTER_DELETE:
3720                 ret = eth_igb_syn_filter_set(dev,
3721                                 (struct rte_eth_syn_filter *)arg,
3722                                 FALSE);
3723                 break;
3724         case RTE_ETH_FILTER_GET:
3725                 ret = eth_igb_syn_filter_get(dev,
3726                                 (struct rte_eth_syn_filter *)arg);
3727                 break;
3728         default:
3729                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3730                 ret = -EINVAL;
3731                 break;
3732         }
3733
3734         return ret;
3735 }
3736
3737 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3738 static inline int
3739 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3740                         struct e1000_2tuple_filter_info *filter_info)
3741 {
3742         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3743                 return -EINVAL;
3744         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3745                 return -EINVAL;  /* filter index is out of range. */
3746         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3747                 return -EINVAL;  /* flags is invalid. */
3748
3749         switch (filter->dst_port_mask) {
3750         case UINT16_MAX:
3751                 filter_info->dst_port_mask = 0;
3752                 filter_info->dst_port = filter->dst_port;
3753                 break;
3754         case 0:
3755                 filter_info->dst_port_mask = 1;
3756                 break;
3757         default:
3758                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3759                 return -EINVAL;
3760         }
3761
3762         switch (filter->proto_mask) {
3763         case UINT8_MAX:
3764                 filter_info->proto_mask = 0;
3765                 filter_info->proto = filter->proto;
3766                 break;
3767         case 0:
3768                 filter_info->proto_mask = 1;
3769                 break;
3770         default:
3771                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3772                 return -EINVAL;
3773         }
3774
3775         filter_info->priority = (uint8_t)filter->priority;
3776         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3777                 filter_info->tcp_flags = filter->tcp_flags;
3778         else
3779                 filter_info->tcp_flags = 0;
3780
3781         return 0;
3782 }
3783
3784 static inline struct e1000_2tuple_filter *
3785 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3786                         struct e1000_2tuple_filter_info *key)
3787 {
3788         struct e1000_2tuple_filter *it;
3789
3790         TAILQ_FOREACH(it, filter_list, entries) {
3791                 if (memcmp(key, &it->filter_info,
3792                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3793                         return it;
3794                 }
3795         }
3796         return NULL;
3797 }
3798
3799 /* inject a igb 2tuple filter to HW */
3800 static inline void
3801 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3802                            struct e1000_2tuple_filter *filter)
3803 {
3804         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3805         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3806         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3807         int i;
3808
3809         i = filter->index;
3810         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3811         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3812                 imir |= E1000_IMIR_PORT_BP;
3813         else
3814                 imir &= ~E1000_IMIR_PORT_BP;
3815
3816         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3817
3818         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3819         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3820         ttqf |= (uint32_t)(filter->filter_info.proto &
3821                                                 E1000_TTQF_PROTOCOL_MASK);
3822         if (filter->filter_info.proto_mask == 0)
3823                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3824
3825         /* tcp flags bits setting. */
3826         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3827                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3828                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3829                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3830                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3831                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3832                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3833                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3834                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3835                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3836                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3837                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3838                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3839         } else {
3840                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3841         }
3842         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3843         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3844         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3845 }
3846
3847 /*
3848  * igb_add_2tuple_filter - add a 2tuple filter
3849  *
3850  * @param
3851  * dev: Pointer to struct rte_eth_dev.
3852  * ntuple_filter: ponter to the filter that will be added.
3853  *
3854  * @return
3855  *    - On success, zero.
3856  *    - On failure, a negative value.
3857  */
3858 static int
3859 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3860                         struct rte_eth_ntuple_filter *ntuple_filter)
3861 {
3862         struct e1000_filter_info *filter_info =
3863                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3864         struct e1000_2tuple_filter *filter;
3865         int i, ret;
3866
3867         filter = rte_zmalloc("e1000_2tuple_filter",
3868                         sizeof(struct e1000_2tuple_filter), 0);
3869         if (filter == NULL)
3870                 return -ENOMEM;
3871
3872         ret = ntuple_filter_to_2tuple(ntuple_filter,
3873                                       &filter->filter_info);
3874         if (ret < 0) {
3875                 rte_free(filter);
3876                 return ret;
3877         }
3878         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3879                                          &filter->filter_info) != NULL) {
3880                 PMD_DRV_LOG(ERR, "filter exists.");
3881                 rte_free(filter);
3882                 return -EEXIST;
3883         }
3884         filter->queue = ntuple_filter->queue;
3885
3886         /*
3887          * look for an unused 2tuple filter index,
3888          * and insert the filter to list.
3889          */
3890         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3891                 if (!(filter_info->twotuple_mask & (1 << i))) {
3892                         filter_info->twotuple_mask |= 1 << i;
3893                         filter->index = i;
3894                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3895                                           filter,
3896                                           entries);
3897                         break;
3898                 }
3899         }
3900         if (i >= E1000_MAX_TTQF_FILTERS) {
3901                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3902                 rte_free(filter);
3903                 return -ENOSYS;
3904         }
3905
3906         igb_inject_2uple_filter(dev, filter);
3907         return 0;
3908 }
3909
3910 int
3911 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3912                         struct e1000_2tuple_filter *filter)
3913 {
3914         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3915         struct e1000_filter_info *filter_info =
3916                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3917
3918         filter_info->twotuple_mask &= ~(1 << filter->index);
3919         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3920         rte_free(filter);
3921
3922         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3923         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3924         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3925         return 0;
3926 }
3927
3928 /*
3929  * igb_remove_2tuple_filter - remove a 2tuple filter
3930  *
3931  * @param
3932  * dev: Pointer to struct rte_eth_dev.
3933  * ntuple_filter: ponter to the filter that will be removed.
3934  *
3935  * @return
3936  *    - On success, zero.
3937  *    - On failure, a negative value.
3938  */
3939 static int
3940 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3941                         struct rte_eth_ntuple_filter *ntuple_filter)
3942 {
3943         struct e1000_filter_info *filter_info =
3944                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3945         struct e1000_2tuple_filter_info filter_2tuple;
3946         struct e1000_2tuple_filter *filter;
3947         int ret;
3948
3949         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3950         ret = ntuple_filter_to_2tuple(ntuple_filter,
3951                                       &filter_2tuple);
3952         if (ret < 0)
3953                 return ret;
3954
3955         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3956                                          &filter_2tuple);
3957         if (filter == NULL) {
3958                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3959                 return -ENOENT;
3960         }
3961
3962         igb_delete_2tuple_filter(dev, filter);
3963
3964         return 0;
3965 }
3966
3967 /* inject a igb flex filter to HW */
3968 static inline void
3969 igb_inject_flex_filter(struct rte_eth_dev *dev,
3970                            struct e1000_flex_filter *filter)
3971 {
3972         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3973         uint32_t wufc, queueing;
3974         uint32_t reg_off;
3975         uint8_t i, j = 0;
3976
3977         wufc = E1000_READ_REG(hw, E1000_WUFC);
3978         if (filter->index < E1000_MAX_FHFT)
3979                 reg_off = E1000_FHFT(filter->index);
3980         else
3981                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3982
3983         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3984                         (E1000_WUFC_FLX0 << filter->index));
3985         queueing = filter->filter_info.len |
3986                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3987                 (filter->filter_info.priority <<
3988                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3989         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3990                         queueing);
3991
3992         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3993                 E1000_WRITE_REG(hw, reg_off,
3994                                 filter->filter_info.dwords[j]);
3995                 reg_off += sizeof(uint32_t);
3996                 E1000_WRITE_REG(hw, reg_off,
3997                                 filter->filter_info.dwords[++j]);
3998                 reg_off += sizeof(uint32_t);
3999                 E1000_WRITE_REG(hw, reg_off,
4000                         (uint32_t)filter->filter_info.mask[i]);
4001                 reg_off += sizeof(uint32_t) * 2;
4002                 ++j;
4003         }
4004 }
4005
4006 static inline struct e1000_flex_filter *
4007 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
4008                         struct e1000_flex_filter_info *key)
4009 {
4010         struct e1000_flex_filter *it;
4011
4012         TAILQ_FOREACH(it, filter_list, entries) {
4013                 if (memcmp(key, &it->filter_info,
4014                         sizeof(struct e1000_flex_filter_info)) == 0)
4015                         return it;
4016         }
4017
4018         return NULL;
4019 }
4020
4021 /* remove a flex byte filter
4022  * @param
4023  * dev: Pointer to struct rte_eth_dev.
4024  * filter: the pointer of the filter will be removed.
4025  */
4026 void
4027 igb_remove_flex_filter(struct rte_eth_dev *dev,
4028                         struct e1000_flex_filter *filter)
4029 {
4030         struct e1000_filter_info *filter_info =
4031                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4032         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4033         uint32_t wufc, i;
4034         uint32_t reg_off;
4035
4036         wufc = E1000_READ_REG(hw, E1000_WUFC);
4037         if (filter->index < E1000_MAX_FHFT)
4038                 reg_off = E1000_FHFT(filter->index);
4039         else
4040                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4041
4042         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4043                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4044
4045         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4046                 (~(E1000_WUFC_FLX0 << filter->index)));
4047
4048         filter_info->flex_mask &= ~(1 << filter->index);
4049         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4050         rte_free(filter);
4051 }
4052
4053 int
4054 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4055                         struct rte_eth_flex_filter *filter,
4056                         bool add)
4057 {
4058         struct e1000_filter_info *filter_info =
4059                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4060         struct e1000_flex_filter *flex_filter, *it;
4061         uint32_t mask;
4062         uint8_t shift, i;
4063
4064         flex_filter = rte_zmalloc("e1000_flex_filter",
4065                         sizeof(struct e1000_flex_filter), 0);
4066         if (flex_filter == NULL)
4067                 return -ENOMEM;
4068
4069         flex_filter->filter_info.len = filter->len;
4070         flex_filter->filter_info.priority = filter->priority;
4071         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4072         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4073                 mask = 0;
4074                 /* reverse bits in flex filter's mask*/
4075                 for (shift = 0; shift < CHAR_BIT; shift++) {
4076                         if (filter->mask[i] & (0x01 << shift))
4077                                 mask |= (0x80 >> shift);
4078                 }
4079                 flex_filter->filter_info.mask[i] = mask;
4080         }
4081
4082         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4083                                 &flex_filter->filter_info);
4084         if (it == NULL && !add) {
4085                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4086                 rte_free(flex_filter);
4087                 return -ENOENT;
4088         }
4089         if (it != NULL && add) {
4090                 PMD_DRV_LOG(ERR, "filter exists.");
4091                 rte_free(flex_filter);
4092                 return -EEXIST;
4093         }
4094
4095         if (add) {
4096                 flex_filter->queue = filter->queue;
4097                 /*
4098                  * look for an unused flex filter index
4099                  * and insert the filter into the list.
4100                  */
4101                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4102                         if (!(filter_info->flex_mask & (1 << i))) {
4103                                 filter_info->flex_mask |= 1 << i;
4104                                 flex_filter->index = i;
4105                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4106                                         flex_filter,
4107                                         entries);
4108                                 break;
4109                         }
4110                 }
4111                 if (i >= E1000_MAX_FLEX_FILTERS) {
4112                         PMD_DRV_LOG(ERR, "flex filters are full.");
4113                         rte_free(flex_filter);
4114                         return -ENOSYS;
4115                 }
4116
4117                 igb_inject_flex_filter(dev, flex_filter);
4118
4119         } else {
4120                 igb_remove_flex_filter(dev, it);
4121                 rte_free(flex_filter);
4122         }
4123
4124         return 0;
4125 }
4126
4127 static int
4128 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4129                         struct rte_eth_flex_filter *filter)
4130 {
4131         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4132         struct e1000_filter_info *filter_info =
4133                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4134         struct e1000_flex_filter flex_filter, *it;
4135         uint32_t wufc, queueing, wufc_en = 0;
4136
4137         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4138         flex_filter.filter_info.len = filter->len;
4139         flex_filter.filter_info.priority = filter->priority;
4140         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4141         memcpy(flex_filter.filter_info.mask, filter->mask,
4142                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4143
4144         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4145                                 &flex_filter.filter_info);
4146         if (it == NULL) {
4147                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4148                 return -ENOENT;
4149         }
4150
4151         wufc = E1000_READ_REG(hw, E1000_WUFC);
4152         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4153
4154         if ((wufc & wufc_en) == wufc_en) {
4155                 uint32_t reg_off = 0;
4156                 if (it->index < E1000_MAX_FHFT)
4157                         reg_off = E1000_FHFT(it->index);
4158                 else
4159                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4160
4161                 queueing = E1000_READ_REG(hw,
4162                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4163                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4164                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4165                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4166                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4167                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4168                 return 0;
4169         }
4170         return -ENOENT;
4171 }
4172
4173 static int
4174 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4175                         enum rte_filter_op filter_op,
4176                         void *arg)
4177 {
4178         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4179         struct rte_eth_flex_filter *filter;
4180         int ret = 0;
4181
4182         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4183
4184         if (filter_op == RTE_ETH_FILTER_NOP)
4185                 return ret;
4186
4187         if (arg == NULL) {
4188                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4189                             filter_op);
4190                 return -EINVAL;
4191         }
4192
4193         filter = (struct rte_eth_flex_filter *)arg;
4194         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4195             || filter->len % sizeof(uint64_t) != 0) {
4196                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4197                 return -EINVAL;
4198         }
4199         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4200                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4201                 return -EINVAL;
4202         }
4203
4204         switch (filter_op) {
4205         case RTE_ETH_FILTER_ADD:
4206                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4207                 break;
4208         case RTE_ETH_FILTER_DELETE:
4209                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4210                 break;
4211         case RTE_ETH_FILTER_GET:
4212                 ret = eth_igb_get_flex_filter(dev, filter);
4213                 break;
4214         default:
4215                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4216                 ret = -EINVAL;
4217                 break;
4218         }
4219
4220         return ret;
4221 }
4222
4223 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4224 static inline int
4225 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4226                         struct e1000_5tuple_filter_info *filter_info)
4227 {
4228         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4229                 return -EINVAL;
4230         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4231                 return -EINVAL;  /* filter index is out of range. */
4232         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4233                 return -EINVAL;  /* flags is invalid. */
4234
4235         switch (filter->dst_ip_mask) {
4236         case UINT32_MAX:
4237                 filter_info->dst_ip_mask = 0;
4238                 filter_info->dst_ip = filter->dst_ip;
4239                 break;
4240         case 0:
4241                 filter_info->dst_ip_mask = 1;
4242                 break;
4243         default:
4244                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4245                 return -EINVAL;
4246         }
4247
4248         switch (filter->src_ip_mask) {
4249         case UINT32_MAX:
4250                 filter_info->src_ip_mask = 0;
4251                 filter_info->src_ip = filter->src_ip;
4252                 break;
4253         case 0:
4254                 filter_info->src_ip_mask = 1;
4255                 break;
4256         default:
4257                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4258                 return -EINVAL;
4259         }
4260
4261         switch (filter->dst_port_mask) {
4262         case UINT16_MAX:
4263                 filter_info->dst_port_mask = 0;
4264                 filter_info->dst_port = filter->dst_port;
4265                 break;
4266         case 0:
4267                 filter_info->dst_port_mask = 1;
4268                 break;
4269         default:
4270                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4271                 return -EINVAL;
4272         }
4273
4274         switch (filter->src_port_mask) {
4275         case UINT16_MAX:
4276                 filter_info->src_port_mask = 0;
4277                 filter_info->src_port = filter->src_port;
4278                 break;
4279         case 0:
4280                 filter_info->src_port_mask = 1;
4281                 break;
4282         default:
4283                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4284                 return -EINVAL;
4285         }
4286
4287         switch (filter->proto_mask) {
4288         case UINT8_MAX:
4289                 filter_info->proto_mask = 0;
4290                 filter_info->proto = filter->proto;
4291                 break;
4292         case 0:
4293                 filter_info->proto_mask = 1;
4294                 break;
4295         default:
4296                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4297                 return -EINVAL;
4298         }
4299
4300         filter_info->priority = (uint8_t)filter->priority;
4301         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4302                 filter_info->tcp_flags = filter->tcp_flags;
4303         else
4304                 filter_info->tcp_flags = 0;
4305
4306         return 0;
4307 }
4308
4309 static inline struct e1000_5tuple_filter *
4310 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4311                         struct e1000_5tuple_filter_info *key)
4312 {
4313         struct e1000_5tuple_filter *it;
4314
4315         TAILQ_FOREACH(it, filter_list, entries) {
4316                 if (memcmp(key, &it->filter_info,
4317                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4318                         return it;
4319                 }
4320         }
4321         return NULL;
4322 }
4323
4324 /* inject a igb 5-tuple filter to HW */
4325 static inline void
4326 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4327                            struct e1000_5tuple_filter *filter)
4328 {
4329         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4330         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4331         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4332         uint8_t i;
4333
4334         i = filter->index;
4335         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4336         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4337                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4338         if (filter->filter_info.dst_ip_mask == 0)
4339                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4340         if (filter->filter_info.src_port_mask == 0)
4341                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4342         if (filter->filter_info.proto_mask == 0)
4343                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4344         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4345                 E1000_FTQF_QUEUE_MASK;
4346         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4347         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4348         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4349         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4350
4351         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4352         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4353
4354         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4355         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4356                 imir |= E1000_IMIR_PORT_BP;
4357         else
4358                 imir &= ~E1000_IMIR_PORT_BP;
4359         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4360
4361         /* tcp flags bits setting. */
4362         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4363                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4364                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4365                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4366                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4367                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4368                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4369                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4370                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4371                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4372                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4373                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4374                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4375         } else {
4376                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4377         }
4378         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4379         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4380 }
4381
4382 /*
4383  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4384  *
4385  * @param
4386  * dev: Pointer to struct rte_eth_dev.
4387  * ntuple_filter: ponter to the filter that will be added.
4388  *
4389  * @return
4390  *    - On success, zero.
4391  *    - On failure, a negative value.
4392  */
4393 static int
4394 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4395                         struct rte_eth_ntuple_filter *ntuple_filter)
4396 {
4397         struct e1000_filter_info *filter_info =
4398                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4399         struct e1000_5tuple_filter *filter;
4400         uint8_t i;
4401         int ret;
4402
4403         filter = rte_zmalloc("e1000_5tuple_filter",
4404                         sizeof(struct e1000_5tuple_filter), 0);
4405         if (filter == NULL)
4406                 return -ENOMEM;
4407
4408         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4409                                             &filter->filter_info);
4410         if (ret < 0) {
4411                 rte_free(filter);
4412                 return ret;
4413         }
4414
4415         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4416                                          &filter->filter_info) != NULL) {
4417                 PMD_DRV_LOG(ERR, "filter exists.");
4418                 rte_free(filter);
4419                 return -EEXIST;
4420         }
4421         filter->queue = ntuple_filter->queue;
4422
4423         /*
4424          * look for an unused 5tuple filter index,
4425          * and insert the filter to list.
4426          */
4427         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4428                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4429                         filter_info->fivetuple_mask |= 1 << i;
4430                         filter->index = i;
4431                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4432                                           filter,
4433                                           entries);
4434                         break;
4435                 }
4436         }
4437         if (i >= E1000_MAX_FTQF_FILTERS) {
4438                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4439                 rte_free(filter);
4440                 return -ENOSYS;
4441         }
4442
4443         igb_inject_5tuple_filter_82576(dev, filter);
4444         return 0;
4445 }
4446
4447 int
4448 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4449                                 struct e1000_5tuple_filter *filter)
4450 {
4451         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4452         struct e1000_filter_info *filter_info =
4453                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4454
4455         filter_info->fivetuple_mask &= ~(1 << filter->index);
4456         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4457         rte_free(filter);
4458
4459         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4460                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4461         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4462         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4463         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4464         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4465         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4466         return 0;
4467 }
4468
4469 /*
4470  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4471  *
4472  * @param
4473  * dev: Pointer to struct rte_eth_dev.
4474  * ntuple_filter: ponter to the filter that will be removed.
4475  *
4476  * @return
4477  *    - On success, zero.
4478  *    - On failure, a negative value.
4479  */
4480 static int
4481 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4482                                 struct rte_eth_ntuple_filter *ntuple_filter)
4483 {
4484         struct e1000_filter_info *filter_info =
4485                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4486         struct e1000_5tuple_filter_info filter_5tuple;
4487         struct e1000_5tuple_filter *filter;
4488         int ret;
4489
4490         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4491         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4492                                             &filter_5tuple);
4493         if (ret < 0)
4494                 return ret;
4495
4496         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4497                                          &filter_5tuple);
4498         if (filter == NULL) {
4499                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4500                 return -ENOENT;
4501         }
4502
4503         igb_delete_5tuple_filter_82576(dev, filter);
4504
4505         return 0;
4506 }
4507
4508 static int
4509 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4510 {
4511         uint32_t rctl;
4512         struct e1000_hw *hw;
4513         struct rte_eth_dev_info dev_info;
4514         uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4515         int ret;
4516
4517         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4518
4519 #ifdef RTE_LIBRTE_82571_SUPPORT
4520         /* XXX: not bigger than max_rx_pktlen */
4521         if (hw->mac.type == e1000_82571)
4522                 return -ENOTSUP;
4523 #endif
4524         ret = eth_igb_infos_get(dev, &dev_info);
4525         if (ret != 0)
4526                 return ret;
4527
4528         /* check that mtu is within the allowed range */
4529         if (mtu < RTE_ETHER_MIN_MTU ||
4530                         frame_size > dev_info.max_rx_pktlen)
4531                 return -EINVAL;
4532
4533         /* refuse mtu that requires the support of scattered packets when this
4534          * feature has not been enabled before. */
4535         if (!dev->data->scattered_rx &&
4536             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4537                 return -EINVAL;
4538
4539         rctl = E1000_READ_REG(hw, E1000_RCTL);
4540
4541         /* switch to jumbo mode if needed */
4542         if (frame_size > RTE_ETHER_MAX_LEN) {
4543                 dev->data->dev_conf.rxmode.offloads |=
4544                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4545                 rctl |= E1000_RCTL_LPE;
4546         } else {
4547                 dev->data->dev_conf.rxmode.offloads &=
4548                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4549                 rctl &= ~E1000_RCTL_LPE;
4550         }
4551         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4552
4553         /* update max frame size */
4554         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4555
4556         E1000_WRITE_REG(hw, E1000_RLPML,
4557                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4558
4559         return 0;
4560 }
4561
4562 /*
4563  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4564  *
4565  * @param
4566  * dev: Pointer to struct rte_eth_dev.
4567  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4568  * add: if true, add filter, if false, remove filter
4569  *
4570  * @return
4571  *    - On success, zero.
4572  *    - On failure, a negative value.
4573  */
4574 int
4575 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4576                         struct rte_eth_ntuple_filter *ntuple_filter,
4577                         bool add)
4578 {
4579         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4580         int ret;
4581
4582         switch (ntuple_filter->flags) {
4583         case RTE_5TUPLE_FLAGS:
4584         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4585                 if (hw->mac.type != e1000_82576)
4586                         return -ENOTSUP;
4587                 if (add)
4588                         ret = igb_add_5tuple_filter_82576(dev,
4589                                                           ntuple_filter);
4590                 else
4591                         ret = igb_remove_5tuple_filter_82576(dev,
4592                                                              ntuple_filter);
4593                 break;
4594         case RTE_2TUPLE_FLAGS:
4595         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4596                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4597                         hw->mac.type != e1000_i210 &&
4598                         hw->mac.type != e1000_i211)
4599                         return -ENOTSUP;
4600                 if (add)
4601                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4602                 else
4603                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4604                 break;
4605         default:
4606                 ret = -EINVAL;
4607                 break;
4608         }
4609
4610         return ret;
4611 }
4612
4613 /*
4614  * igb_get_ntuple_filter - get a ntuple filter
4615  *
4616  * @param
4617  * dev: Pointer to struct rte_eth_dev.
4618  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4619  *
4620  * @return
4621  *    - On success, zero.
4622  *    - On failure, a negative value.
4623  */
4624 static int
4625 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4626                         struct rte_eth_ntuple_filter *ntuple_filter)
4627 {
4628         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4629         struct e1000_filter_info *filter_info =
4630                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4631         struct e1000_5tuple_filter_info filter_5tuple;
4632         struct e1000_2tuple_filter_info filter_2tuple;
4633         struct e1000_5tuple_filter *p_5tuple_filter;
4634         struct e1000_2tuple_filter *p_2tuple_filter;
4635         int ret;
4636
4637         switch (ntuple_filter->flags) {
4638         case RTE_5TUPLE_FLAGS:
4639         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4640                 if (hw->mac.type != e1000_82576)
4641                         return -ENOTSUP;
4642                 memset(&filter_5tuple,
4643                         0,
4644                         sizeof(struct e1000_5tuple_filter_info));
4645                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4646                                                     &filter_5tuple);
4647                 if (ret < 0)
4648                         return ret;
4649                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4650                                         &filter_info->fivetuple_list,
4651                                         &filter_5tuple);
4652                 if (p_5tuple_filter == NULL) {
4653                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4654                         return -ENOENT;
4655                 }
4656                 ntuple_filter->queue = p_5tuple_filter->queue;
4657                 break;
4658         case RTE_2TUPLE_FLAGS:
4659         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4660                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4661                         return -ENOTSUP;
4662                 memset(&filter_2tuple,
4663                         0,
4664                         sizeof(struct e1000_2tuple_filter_info));
4665                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4666                 if (ret < 0)
4667                         return ret;
4668                 p_2tuple_filter = igb_2tuple_filter_lookup(
4669                                         &filter_info->twotuple_list,
4670                                         &filter_2tuple);
4671                 if (p_2tuple_filter == NULL) {
4672                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4673                         return -ENOENT;
4674                 }
4675                 ntuple_filter->queue = p_2tuple_filter->queue;
4676                 break;
4677         default:
4678                 ret = -EINVAL;
4679                 break;
4680         }
4681
4682         return 0;
4683 }
4684
4685 /*
4686  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4687  * @dev: pointer to rte_eth_dev structure
4688  * @filter_op:operation will be taken.
4689  * @arg: a pointer to specific structure corresponding to the filter_op
4690  */
4691 static int
4692 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4693                                 enum rte_filter_op filter_op,
4694                                 void *arg)
4695 {
4696         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4697         int ret;
4698
4699         MAC_TYPE_FILTER_SUP(hw->mac.type);
4700
4701         if (filter_op == RTE_ETH_FILTER_NOP)
4702                 return 0;
4703
4704         if (arg == NULL) {
4705                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4706                             filter_op);
4707                 return -EINVAL;
4708         }
4709
4710         switch (filter_op) {
4711         case RTE_ETH_FILTER_ADD:
4712                 ret = igb_add_del_ntuple_filter(dev,
4713                         (struct rte_eth_ntuple_filter *)arg,
4714                         TRUE);
4715                 break;
4716         case RTE_ETH_FILTER_DELETE:
4717                 ret = igb_add_del_ntuple_filter(dev,
4718                         (struct rte_eth_ntuple_filter *)arg,
4719                         FALSE);
4720                 break;
4721         case RTE_ETH_FILTER_GET:
4722                 ret = igb_get_ntuple_filter(dev,
4723                         (struct rte_eth_ntuple_filter *)arg);
4724                 break;
4725         default:
4726                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4727                 ret = -EINVAL;
4728                 break;
4729         }
4730         return ret;
4731 }
4732
4733 static inline int
4734 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4735                         uint16_t ethertype)
4736 {
4737         int i;
4738
4739         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4740                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4741                     (filter_info->ethertype_mask & (1 << i)))
4742                         return i;
4743         }
4744         return -1;
4745 }
4746
4747 static inline int
4748 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4749                         uint16_t ethertype, uint32_t etqf)
4750 {
4751         int i;
4752
4753         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4754                 if (!(filter_info->ethertype_mask & (1 << i))) {
4755                         filter_info->ethertype_mask |= 1 << i;
4756                         filter_info->ethertype_filters[i].ethertype = ethertype;
4757                         filter_info->ethertype_filters[i].etqf = etqf;
4758                         return i;
4759                 }
4760         }
4761         return -1;
4762 }
4763
4764 int
4765 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4766                         uint8_t idx)
4767 {
4768         if (idx >= E1000_MAX_ETQF_FILTERS)
4769                 return -1;
4770         filter_info->ethertype_mask &= ~(1 << idx);
4771         filter_info->ethertype_filters[idx].ethertype = 0;
4772         filter_info->ethertype_filters[idx].etqf = 0;
4773         return idx;
4774 }
4775
4776
4777 int
4778 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4779                         struct rte_eth_ethertype_filter *filter,
4780                         bool add)
4781 {
4782         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4783         struct e1000_filter_info *filter_info =
4784                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4785         uint32_t etqf = 0;
4786         int ret;
4787
4788         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4789                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4790                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4791                         " ethertype filter.", filter->ether_type);
4792                 return -EINVAL;
4793         }
4794
4795         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4796                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4797                 return -EINVAL;
4798         }
4799         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4800                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4801                 return -EINVAL;
4802         }
4803
4804         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4805         if (ret >= 0 && add) {
4806                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4807                             filter->ether_type);
4808                 return -EEXIST;
4809         }
4810         if (ret < 0 && !add) {
4811                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4812                             filter->ether_type);
4813                 return -ENOENT;
4814         }
4815
4816         if (add) {
4817                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4818                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4819                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4820                 ret = igb_ethertype_filter_insert(filter_info,
4821                                 filter->ether_type, etqf);
4822                 if (ret < 0) {
4823                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4824                         return -ENOSYS;
4825                 }
4826         } else {
4827                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4828                 if (ret < 0)
4829                         return -ENOSYS;
4830         }
4831         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4832         E1000_WRITE_FLUSH(hw);
4833
4834         return 0;
4835 }
4836
4837 static int
4838 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4839                         struct rte_eth_ethertype_filter *filter)
4840 {
4841         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4842         struct e1000_filter_info *filter_info =
4843                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4844         uint32_t etqf;
4845         int ret;
4846
4847         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4848         if (ret < 0) {
4849                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4850                             filter->ether_type);
4851                 return -ENOENT;
4852         }
4853
4854         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4855         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4856                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4857                 filter->flags = 0;
4858                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4859                                 E1000_ETQF_QUEUE_SHIFT;
4860                 return 0;
4861         }
4862
4863         return -ENOENT;
4864 }
4865
4866 /*
4867  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4868  * @dev: pointer to rte_eth_dev structure
4869  * @filter_op:operation will be taken.
4870  * @arg: a pointer to specific structure corresponding to the filter_op
4871  */
4872 static int
4873 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4874                                 enum rte_filter_op filter_op,
4875                                 void *arg)
4876 {
4877         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4878         int ret;
4879
4880         MAC_TYPE_FILTER_SUP(hw->mac.type);
4881
4882         if (filter_op == RTE_ETH_FILTER_NOP)
4883                 return 0;
4884
4885         if (arg == NULL) {
4886                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4887                             filter_op);
4888                 return -EINVAL;
4889         }
4890
4891         switch (filter_op) {
4892         case RTE_ETH_FILTER_ADD:
4893                 ret = igb_add_del_ethertype_filter(dev,
4894                         (struct rte_eth_ethertype_filter *)arg,
4895                         TRUE);
4896                 break;
4897         case RTE_ETH_FILTER_DELETE:
4898                 ret = igb_add_del_ethertype_filter(dev,
4899                         (struct rte_eth_ethertype_filter *)arg,
4900                         FALSE);
4901                 break;
4902         case RTE_ETH_FILTER_GET:
4903                 ret = igb_get_ethertype_filter(dev,
4904                         (struct rte_eth_ethertype_filter *)arg);
4905                 break;
4906         default:
4907                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4908                 ret = -EINVAL;
4909                 break;
4910         }
4911         return ret;
4912 }
4913
4914 static int
4915 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4916                      enum rte_filter_type filter_type,
4917                      enum rte_filter_op filter_op,
4918                      void *arg)
4919 {
4920         int ret = 0;
4921
4922         switch (filter_type) {
4923         case RTE_ETH_FILTER_NTUPLE:
4924                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4925                 break;
4926         case RTE_ETH_FILTER_ETHERTYPE:
4927                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4928                 break;
4929         case RTE_ETH_FILTER_SYN:
4930                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4931                 break;
4932         case RTE_ETH_FILTER_FLEXIBLE:
4933                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4934                 break;
4935         case RTE_ETH_FILTER_GENERIC:
4936                 if (filter_op != RTE_ETH_FILTER_GET)
4937                         return -EINVAL;
4938                 *(const void **)arg = &igb_flow_ops;
4939                 break;
4940         default:
4941                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4942                                                         filter_type);
4943                 break;
4944         }
4945
4946         return ret;
4947 }
4948
4949 static int
4950 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4951                          struct rte_ether_addr *mc_addr_set,
4952                          uint32_t nb_mc_addr)
4953 {
4954         struct e1000_hw *hw;
4955
4956         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4957         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4958         return 0;
4959 }
4960
4961 static uint64_t
4962 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4963 {
4964         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4965         uint64_t systime_cycles;
4966
4967         switch (hw->mac.type) {
4968         case e1000_i210:
4969         case e1000_i211:
4970                 /*
4971                  * Need to read System Time Residue Register to be able
4972                  * to read the other two registers.
4973                  */
4974                 E1000_READ_REG(hw, E1000_SYSTIMR);
4975                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4976                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4977                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4978                                 * NSEC_PER_SEC;
4979                 break;
4980         case e1000_82580:
4981         case e1000_i350:
4982         case e1000_i354:
4983                 /*
4984                  * Need to read System Time Residue Register to be able
4985                  * to read the other two registers.
4986                  */
4987                 E1000_READ_REG(hw, E1000_SYSTIMR);
4988                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4989                 /* Only the 8 LSB are valid. */
4990                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4991                                 & 0xff) << 32;
4992                 break;
4993         default:
4994                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4995                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4996                                 << 32;
4997                 break;
4998         }
4999
5000         return systime_cycles;
5001 }
5002
5003 static uint64_t
5004 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5005 {
5006         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5007         uint64_t rx_tstamp_cycles;
5008
5009         switch (hw->mac.type) {
5010         case e1000_i210:
5011         case e1000_i211:
5012                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5013                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5014                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5015                                 * NSEC_PER_SEC;
5016                 break;
5017         case e1000_82580:
5018         case e1000_i350:
5019         case e1000_i354:
5020                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5021                 /* Only the 8 LSB are valid. */
5022                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
5023                                 & 0xff) << 32;
5024                 break;
5025         default:
5026                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5027                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5028                                 << 32;
5029                 break;
5030         }
5031
5032         return rx_tstamp_cycles;
5033 }
5034
5035 static uint64_t
5036 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5037 {
5038         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5039         uint64_t tx_tstamp_cycles;
5040
5041         switch (hw->mac.type) {
5042         case e1000_i210:
5043         case e1000_i211:
5044                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5045                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5046                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5047                                 * NSEC_PER_SEC;
5048                 break;
5049         case e1000_82580:
5050         case e1000_i350:
5051         case e1000_i354:
5052                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5053                 /* Only the 8 LSB are valid. */
5054                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5055                                 & 0xff) << 32;
5056                 break;
5057         default:
5058                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5059                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5060                                 << 32;
5061                 break;
5062         }
5063
5064         return tx_tstamp_cycles;
5065 }
5066
5067 static void
5068 igb_start_timecounters(struct rte_eth_dev *dev)
5069 {
5070         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5071         struct e1000_adapter *adapter = dev->data->dev_private;
5072         uint32_t incval = 1;
5073         uint32_t shift = 0;
5074         uint64_t mask = E1000_CYCLECOUNTER_MASK;
5075
5076         switch (hw->mac.type) {
5077         case e1000_82580:
5078         case e1000_i350:
5079         case e1000_i354:
5080                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5081                 mask = (1ULL << 40) - 1;
5082                 /* fall-through */
5083         case e1000_i210:
5084         case e1000_i211:
5085                 /*
5086                  * Start incrementing the register
5087                  * used to timestamp PTP packets.
5088                  */
5089                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5090                 break;
5091         case e1000_82576:
5092                 incval = E1000_INCVALUE_82576;
5093                 shift = IGB_82576_TSYNC_SHIFT;
5094                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5095                                 E1000_INCPERIOD_82576 | incval);
5096                 break;
5097         default:
5098                 /* Not supported */
5099                 return;
5100         }
5101
5102         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5103         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5104         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5105
5106         adapter->systime_tc.cc_mask = mask;
5107         adapter->systime_tc.cc_shift = shift;
5108         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5109
5110         adapter->rx_tstamp_tc.cc_mask = mask;
5111         adapter->rx_tstamp_tc.cc_shift = shift;
5112         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5113
5114         adapter->tx_tstamp_tc.cc_mask = mask;
5115         adapter->tx_tstamp_tc.cc_shift = shift;
5116         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5117 }
5118
5119 static int
5120 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5121 {
5122         struct e1000_adapter *adapter = dev->data->dev_private;
5123
5124         adapter->systime_tc.nsec += delta;
5125         adapter->rx_tstamp_tc.nsec += delta;
5126         adapter->tx_tstamp_tc.nsec += delta;
5127
5128         return 0;
5129 }
5130
5131 static int
5132 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5133 {
5134         uint64_t ns;
5135         struct e1000_adapter *adapter = dev->data->dev_private;
5136
5137         ns = rte_timespec_to_ns(ts);
5138
5139         /* Set the timecounters to a new value. */
5140         adapter->systime_tc.nsec = ns;
5141         adapter->rx_tstamp_tc.nsec = ns;
5142         adapter->tx_tstamp_tc.nsec = ns;
5143
5144         return 0;
5145 }
5146
5147 static int
5148 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5149 {
5150         uint64_t ns, systime_cycles;
5151         struct e1000_adapter *adapter = dev->data->dev_private;
5152
5153         systime_cycles = igb_read_systime_cyclecounter(dev);
5154         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5155         *ts = rte_ns_to_timespec(ns);
5156
5157         return 0;
5158 }
5159
5160 static int
5161 igb_timesync_enable(struct rte_eth_dev *dev)
5162 {
5163         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5164         uint32_t tsync_ctl;
5165         uint32_t tsauxc;
5166
5167         /* Stop the timesync system time. */
5168         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5169         /* Reset the timesync system time value. */
5170         switch (hw->mac.type) {
5171         case e1000_82580:
5172         case e1000_i350:
5173         case e1000_i354:
5174         case e1000_i210:
5175         case e1000_i211:
5176                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5177                 /* fall-through */
5178         case e1000_82576:
5179                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5180                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5181                 break;
5182         default:
5183                 /* Not supported. */
5184                 return -ENOTSUP;
5185         }
5186
5187         /* Enable system time for it isn't on by default. */
5188         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5189         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5190         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5191
5192         igb_start_timecounters(dev);
5193
5194         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5195         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5196                         (RTE_ETHER_TYPE_1588 |
5197                          E1000_ETQF_FILTER_ENABLE |
5198                          E1000_ETQF_1588));
5199
5200         /* Enable timestamping of received PTP packets. */
5201         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5202         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5203         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5204
5205         /* Enable Timestamping of transmitted PTP packets. */
5206         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5207         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5208         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5209
5210         return 0;
5211 }
5212
5213 static int
5214 igb_timesync_disable(struct rte_eth_dev *dev)
5215 {
5216         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5217         uint32_t tsync_ctl;
5218
5219         /* Disable timestamping of transmitted PTP packets. */
5220         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5221         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5222         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5223
5224         /* Disable timestamping of received PTP packets. */
5225         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5226         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5227         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5228
5229         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5230         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5231
5232         /* Stop incrementating the System Time registers. */
5233         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5234
5235         return 0;
5236 }
5237
5238 static int
5239 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5240                                struct timespec *timestamp,
5241                                uint32_t flags __rte_unused)
5242 {
5243         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5244         struct e1000_adapter *adapter = dev->data->dev_private;
5245         uint32_t tsync_rxctl;
5246         uint64_t rx_tstamp_cycles;
5247         uint64_t ns;
5248
5249         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5250         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5251                 return -EINVAL;
5252
5253         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5254         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5255         *timestamp = rte_ns_to_timespec(ns);
5256
5257         return  0;
5258 }
5259
5260 static int
5261 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5262                                struct timespec *timestamp)
5263 {
5264         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5265         struct e1000_adapter *adapter = dev->data->dev_private;
5266         uint32_t tsync_txctl;
5267         uint64_t tx_tstamp_cycles;
5268         uint64_t ns;
5269
5270         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5271         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5272                 return -EINVAL;
5273
5274         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5275         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5276         *timestamp = rte_ns_to_timespec(ns);
5277
5278         return  0;
5279 }
5280
5281 static int
5282 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5283 {
5284         int count = 0;
5285         int g_ind = 0;
5286         const struct reg_info *reg_group;
5287
5288         while ((reg_group = igb_regs[g_ind++]))
5289                 count += igb_reg_group_count(reg_group);
5290
5291         return count;
5292 }
5293
5294 static int
5295 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5296 {
5297         int count = 0;
5298         int g_ind = 0;
5299         const struct reg_info *reg_group;
5300
5301         while ((reg_group = igbvf_regs[g_ind++]))
5302                 count += igb_reg_group_count(reg_group);
5303
5304         return count;
5305 }
5306
5307 static int
5308 eth_igb_get_regs(struct rte_eth_dev *dev,
5309         struct rte_dev_reg_info *regs)
5310 {
5311         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5312         uint32_t *data = regs->data;
5313         int g_ind = 0;
5314         int count = 0;
5315         const struct reg_info *reg_group;
5316
5317         if (data == NULL) {
5318                 regs->length = eth_igb_get_reg_length(dev);
5319                 regs->width = sizeof(uint32_t);
5320                 return 0;
5321         }
5322
5323         /* Support only full register dump */
5324         if ((regs->length == 0) ||
5325             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5326                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5327                         hw->device_id;
5328                 while ((reg_group = igb_regs[g_ind++]))
5329                         count += igb_read_regs_group(dev, &data[count],
5330                                                         reg_group);
5331                 return 0;
5332         }
5333
5334         return -ENOTSUP;
5335 }
5336
5337 static int
5338 igbvf_get_regs(struct rte_eth_dev *dev,
5339         struct rte_dev_reg_info *regs)
5340 {
5341         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5342         uint32_t *data = regs->data;
5343         int g_ind = 0;
5344         int count = 0;
5345         const struct reg_info *reg_group;
5346
5347         if (data == NULL) {
5348                 regs->length = igbvf_get_reg_length(dev);
5349                 regs->width = sizeof(uint32_t);
5350                 return 0;
5351         }
5352
5353         /* Support only full register dump */
5354         if ((regs->length == 0) ||
5355             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5356                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5357                         hw->device_id;
5358                 while ((reg_group = igbvf_regs[g_ind++]))
5359                         count += igb_read_regs_group(dev, &data[count],
5360                                                         reg_group);
5361                 return 0;
5362         }
5363
5364         return -ENOTSUP;
5365 }
5366
5367 static int
5368 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5369 {
5370         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5371
5372         /* Return unit is byte count */
5373         return hw->nvm.word_size * 2;
5374 }
5375
5376 static int
5377 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5378         struct rte_dev_eeprom_info *in_eeprom)
5379 {
5380         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5381         struct e1000_nvm_info *nvm = &hw->nvm;
5382         uint16_t *data = in_eeprom->data;
5383         int first, length;
5384
5385         first = in_eeprom->offset >> 1;
5386         length = in_eeprom->length >> 1;
5387         if ((first >= hw->nvm.word_size) ||
5388             ((first + length) >= hw->nvm.word_size))
5389                 return -EINVAL;
5390
5391         in_eeprom->magic = hw->vendor_id |
5392                 ((uint32_t)hw->device_id << 16);
5393
5394         if ((nvm->ops.read) == NULL)
5395                 return -ENOTSUP;
5396
5397         return nvm->ops.read(hw, first, length, data);
5398 }
5399
5400 static int
5401 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5402         struct rte_dev_eeprom_info *in_eeprom)
5403 {
5404         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5405         struct e1000_nvm_info *nvm = &hw->nvm;
5406         uint16_t *data = in_eeprom->data;
5407         int first, length;
5408
5409         first = in_eeprom->offset >> 1;
5410         length = in_eeprom->length >> 1;
5411         if ((first >= hw->nvm.word_size) ||
5412             ((first + length) >= hw->nvm.word_size))
5413                 return -EINVAL;
5414
5415         in_eeprom->magic = (uint32_t)hw->vendor_id |
5416                 ((uint32_t)hw->device_id << 16);
5417
5418         if ((nvm->ops.write) == NULL)
5419                 return -ENOTSUP;
5420         return nvm->ops.write(hw,  first, length, data);
5421 }
5422
5423 static int
5424 eth_igb_get_module_info(struct rte_eth_dev *dev,
5425                         struct rte_eth_dev_module_info *modinfo)
5426 {
5427         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5428
5429         uint32_t status = 0;
5430         uint16_t sff8472_rev, addr_mode;
5431         bool page_swap = false;
5432
5433         if (hw->phy.media_type == e1000_media_type_copper ||
5434             hw->phy.media_type == e1000_media_type_unknown)
5435                 return -EOPNOTSUPP;
5436
5437         /* Check whether we support SFF-8472 or not */
5438         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5439         if (status)
5440                 return -EIO;
5441
5442         /* addressing mode is not supported */
5443         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5444         if (status)
5445                 return -EIO;
5446
5447         /* addressing mode is not supported */
5448         if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5449                 PMD_DRV_LOG(ERR,
5450                             "Address change required to access page 0xA2, "
5451                             "but not supported. Please report the module "
5452                             "type to the driver maintainers.\n");
5453                 page_swap = true;
5454         }
5455
5456         if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5457                 /* We have an SFP, but it does not support SFF-8472 */
5458                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5459                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5460         } else {
5461                 /* We have an SFP which supports a revision of SFF-8472 */
5462                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5463                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5464         }
5465
5466         return 0;
5467 }
5468
5469 static int
5470 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5471                           struct rte_dev_eeprom_info *info)
5472 {
5473         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5474
5475         uint32_t status = 0;
5476         uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5477         u16 first_word, last_word;
5478         int i = 0;
5479
5480         if (info->length == 0)
5481                 return -EINVAL;
5482
5483         first_word = info->offset >> 1;
5484         last_word = (info->offset + info->length - 1) >> 1;
5485
5486         /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5487         for (i = 0; i < last_word - first_word + 1; i++) {
5488                 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5489                                                 &dataword[i]);
5490                 if (status) {
5491                         /* Error occurred while reading module */
5492                         return -EIO;
5493                 }
5494
5495                 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5496         }
5497
5498         memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5499
5500         return 0;
5501 }
5502
5503 static int
5504 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5505 {
5506         struct e1000_hw *hw =
5507                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5508         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5509         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5510         uint32_t vec = E1000_MISC_VEC_ID;
5511
5512         if (rte_intr_allow_others(intr_handle))
5513                 vec = E1000_RX_VEC_START;
5514
5515         uint32_t mask = 1 << (queue_id + vec);
5516
5517         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5518         E1000_WRITE_FLUSH(hw);
5519
5520         return 0;
5521 }
5522
5523 static int
5524 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5525 {
5526         struct e1000_hw *hw =
5527                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5528         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5529         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5530         uint32_t vec = E1000_MISC_VEC_ID;
5531
5532         if (rte_intr_allow_others(intr_handle))
5533                 vec = E1000_RX_VEC_START;
5534
5535         uint32_t mask = 1 << (queue_id + vec);
5536         uint32_t regval;
5537
5538         regval = E1000_READ_REG(hw, E1000_EIMS);
5539         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5540         E1000_WRITE_FLUSH(hw);
5541
5542         rte_intr_ack(intr_handle);
5543
5544         return 0;
5545 }
5546
5547 static void
5548 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5549                    uint8_t index, uint8_t offset)
5550 {
5551         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5552
5553         /* clear bits */
5554         val &= ~((uint32_t)0xFF << offset);
5555
5556         /* write vector and valid bit */
5557         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5558
5559         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5560 }
5561
5562 static void
5563 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5564                            uint8_t queue, uint8_t msix_vector)
5565 {
5566         uint32_t tmp = 0;
5567
5568         if (hw->mac.type == e1000_82575) {
5569                 if (direction == 0)
5570                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5571                 else if (direction == 1)
5572                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5573                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5574         } else if (hw->mac.type == e1000_82576) {
5575                 if ((direction == 0) || (direction == 1))
5576                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5577                                            ((queue & 0x8) << 1) +
5578                                            8 * direction);
5579         } else if ((hw->mac.type == e1000_82580) ||
5580                         (hw->mac.type == e1000_i350) ||
5581                         (hw->mac.type == e1000_i354) ||
5582                         (hw->mac.type == e1000_i210) ||
5583                         (hw->mac.type == e1000_i211)) {
5584                 if ((direction == 0) || (direction == 1))
5585                         eth_igb_write_ivar(hw, msix_vector,
5586                                            queue >> 1,
5587                                            ((queue & 0x1) << 4) +
5588                                            8 * direction);
5589         }
5590 }
5591
5592 /* Sets up the hardware to generate MSI-X interrupts properly
5593  * @hw
5594  *  board private structure
5595  */
5596 static void
5597 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5598 {
5599         int queue_id;
5600         uint32_t tmpval, regval, intr_mask;
5601         struct e1000_hw *hw =
5602                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5603         uint32_t vec = E1000_MISC_VEC_ID;
5604         uint32_t base = E1000_MISC_VEC_ID;
5605         uint32_t misc_shift = 0;
5606         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5607         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5608
5609         /* won't configure msix register if no mapping is done
5610          * between intr vector and event fd
5611          */
5612         if (!rte_intr_dp_is_en(intr_handle))
5613                 return;
5614
5615         if (rte_intr_allow_others(intr_handle)) {
5616                 vec = base = E1000_RX_VEC_START;
5617                 misc_shift = 1;
5618         }
5619
5620         /* set interrupt vector for other causes */
5621         if (hw->mac.type == e1000_82575) {
5622                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5623                 /* enable MSI-X PBA support */
5624                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5625
5626                 /* Auto-Mask interrupts upon ICR read */
5627                 tmpval |= E1000_CTRL_EXT_EIAME;
5628                 tmpval |= E1000_CTRL_EXT_IRCA;
5629
5630                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5631
5632                 /* enable msix_other interrupt */
5633                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5634                 regval = E1000_READ_REG(hw, E1000_EIAC);
5635                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5636                 regval = E1000_READ_REG(hw, E1000_EIAM);
5637                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5638         } else if ((hw->mac.type == e1000_82576) ||
5639                         (hw->mac.type == e1000_82580) ||
5640                         (hw->mac.type == e1000_i350) ||
5641                         (hw->mac.type == e1000_i354) ||
5642                         (hw->mac.type == e1000_i210) ||
5643                         (hw->mac.type == e1000_i211)) {
5644                 /* turn on MSI-X capability first */
5645                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5646                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5647                                         E1000_GPIE_NSICR);
5648                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5649                         misc_shift;
5650
5651                 if (dev->data->dev_conf.intr_conf.lsc != 0)
5652                         intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5653
5654                 regval = E1000_READ_REG(hw, E1000_EIAC);
5655                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5656
5657                 /* enable msix_other interrupt */
5658                 regval = E1000_READ_REG(hw, E1000_EIMS);
5659                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5660                 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5661                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5662         }
5663
5664         /* use EIAM to auto-mask when MSI-X interrupt
5665          * is asserted, this saves a register write for every interrupt
5666          */
5667         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5668                 misc_shift;
5669
5670         if (dev->data->dev_conf.intr_conf.lsc != 0)
5671                 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5672
5673         regval = E1000_READ_REG(hw, E1000_EIAM);
5674         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5675
5676         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5677                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5678                 intr_handle->intr_vec[queue_id] = vec;
5679                 if (vec < base + intr_handle->nb_efd - 1)
5680                         vec++;
5681         }
5682
5683         E1000_WRITE_FLUSH(hw);
5684 }
5685
5686 /* restore n-tuple filter */
5687 static inline void
5688 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5689 {
5690         struct e1000_filter_info *filter_info =
5691                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5692         struct e1000_5tuple_filter *p_5tuple;
5693         struct e1000_2tuple_filter *p_2tuple;
5694
5695         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5696                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5697         }
5698
5699         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5700                 igb_inject_2uple_filter(dev, p_2tuple);
5701         }
5702 }
5703
5704 /* restore SYN filter */
5705 static inline void
5706 igb_syn_filter_restore(struct rte_eth_dev *dev)
5707 {
5708         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5709         struct e1000_filter_info *filter_info =
5710                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5711         uint32_t synqf;
5712
5713         synqf = filter_info->syn_info;
5714
5715         if (synqf & E1000_SYN_FILTER_ENABLE) {
5716                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5717                 E1000_WRITE_FLUSH(hw);
5718         }
5719 }
5720
5721 /* restore ethernet type filter */
5722 static inline void
5723 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5724 {
5725         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5726         struct e1000_filter_info *filter_info =
5727                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5728         int i;
5729
5730         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5731                 if (filter_info->ethertype_mask & (1 << i)) {
5732                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5733                                 filter_info->ethertype_filters[i].etqf);
5734                         E1000_WRITE_FLUSH(hw);
5735                 }
5736         }
5737 }
5738
5739 /* restore flex byte filter */
5740 static inline void
5741 igb_flex_filter_restore(struct rte_eth_dev *dev)
5742 {
5743         struct e1000_filter_info *filter_info =
5744                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5745         struct e1000_flex_filter *flex_filter;
5746
5747         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5748                 igb_inject_flex_filter(dev, flex_filter);
5749         }
5750 }
5751
5752 /* restore rss filter */
5753 static inline void
5754 igb_rss_filter_restore(struct rte_eth_dev *dev)
5755 {
5756         struct e1000_filter_info *filter_info =
5757                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5758
5759         if (filter_info->rss_info.conf.queue_num)
5760                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5761 }
5762
5763 /* restore all types filter */
5764 static int
5765 igb_filter_restore(struct rte_eth_dev *dev)
5766 {
5767         igb_ntuple_filter_restore(dev);
5768         igb_ethertype_filter_restore(dev);
5769         igb_syn_filter_restore(dev);
5770         igb_flex_filter_restore(dev);
5771         igb_rss_filter_restore(dev);
5772
5773         return 0;
5774 }
5775
5776 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5777 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5778 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5779 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5780 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5781 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5782
5783 /* see e1000_logs.c */
5784 RTE_INIT(e1000_init_log)
5785 {
5786         e1000_igb_init_log();
5787 }