drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_string_fns.h>
  12 #include <rte_common.h>
  13 #include <rte_interrupts.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_log.h>
  16 #include <rte_debug.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memory.h>
  23 #include <rte_eal.h>
  24 #include <rte_malloc.h>
  25 #include <rte_dev.h>
  26
  27 #include "e1000_logs.h"
  28 #include "base/e1000_api.h"
  29 #include "e1000_ethdev.h"
  30 #include "igb_regs.h"
  31
  32 /*
  33  * Default values for port configuration
  34  */
  35 #define IGB_DEFAULT_RX_FREE_THRESH  32
  36
  37 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  38 #define IGB_DEFAULT_RX_HTHRESH      8
  39 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  40
  41 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  42 #define IGB_DEFAULT_TX_HTHRESH      1
  43 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  44
  45 /* Bit shift and mask */
  46 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  47 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  48 #define IGB_8_BIT_WIDTH  CHAR_BIT
  49 #define IGB_8_BIT_MASK   UINT8_MAX
  50
  51 /* Additional timesync values. */
  52 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  53 #define E1000_ETQF_FILTER_1588       3
  54 #define IGB_82576_TSYNC_SHIFT        16
  55 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  56 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  58
  59 #define E1000_VTIVAR_MISC                0x01740
  60 #define E1000_VTIVAR_MISC_MASK           0xFF
  61 #define E1000_VTIVAR_VALID               0x80
  62 #define E1000_VTIVAR_MISC_MAILBOX        0
  63 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  64
  65 /* External VLAN Enable bit mask */
  66 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  67
  68 /* External VLAN Ether Type bit mask and shift */
  69 #define E1000_VET_VET_EXT            0xFFFF0000
  70 #define E1000_VET_VET_EXT_SHIFT      16
  71
  72 /* MSI-X other interrupt vector */
  73 #define IGB_MSIX_OTHER_INTR_VEC      0
  74
  75 static int  eth_igb_configure(struct rte_eth_dev *dev);
  76 static int  eth_igb_start(struct rte_eth_dev *dev);
  77 static int  eth_igb_stop(struct rte_eth_dev *dev);
  78 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  79 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  80 static int eth_igb_close(struct rte_eth_dev *dev);
  81 static int eth_igb_reset(struct rte_eth_dev *dev);
  82 static int  eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  83 static int  eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  84 static int  eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  85 static int  eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  87                                 int wait_to_complete);
  88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  89                                 struct rte_eth_stats *rte_stats);
  90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  91                               struct rte_eth_xstat *xstats, unsigned n);
  92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  93                 const uint64_t *ids,
  94                 uint64_t *values, unsigned int n);
  95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  96                                     struct rte_eth_xstat_name *xstats_names,
  97                                     unsigned int size);
  98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  99                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 100                 unsigned int limit);
 101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
 102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
 103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 104                                    char *fw_version, size_t fw_size);
 105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
 106                               struct rte_eth_dev_info *dev_info);
 107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_dev_info *dev_info);
 110 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 113                                 struct rte_eth_fc_conf *fc_conf);
 114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 118                                     struct rte_intr_handle *handle);
 119 static void eth_igb_interrupt_handler(void *param);
 120 static int  igb_hardware_init(struct e1000_hw *hw);
 121 static void igb_hw_control_acquire(struct e1000_hw *hw);
 122 static void igb_hw_control_release(struct e1000_hw *hw);
 123 static void igb_init_manageability(struct e1000_hw *hw);
 124 static void igb_release_manageability(struct e1000_hw *hw);
 125
 126 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 127
 128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 129                 uint16_t vlan_id, int on);
 130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 131                                  enum rte_vlan_type vlan_type,
 132                                  uint16_t tpid_id);
 133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134
 135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 141
 142 static int eth_igb_led_on(struct rte_eth_dev *dev);
 143 static int eth_igb_led_off(struct rte_eth_dev *dev);
 144
 145 static void igb_intr_disable(struct rte_eth_dev *dev);
 146 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 148                            struct rte_ether_addr *mac_addr,
 149                            uint32_t index, uint32_t pool);
 150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 152                 struct rte_ether_addr *addr);
 153
 154 static void igbvf_intr_disable(struct e1000_hw *hw);
 155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 156 static int igbvf_dev_start(struct rte_eth_dev *dev);
 157 static int igbvf_dev_stop(struct rte_eth_dev *dev);
 158 static int igbvf_dev_close(struct rte_eth_dev *dev);
 159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 163 static int eth_igbvf_link_update(struct e1000_hw *hw);
 164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_stats *rte_stats);
 166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 167                                 struct rte_eth_xstat *xstats, unsigned n);
 168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 169                                       struct rte_eth_xstat_name *xstats_names,
 170                                       unsigned limit);
 171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 173                 uint16_t vlan_id, int on);
 174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 177                 struct rte_ether_addr *addr);
 178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 179 static int igbvf_get_regs(struct rte_eth_dev *dev,
 180                 struct rte_dev_reg_info *regs);
 181
 182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 183                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                    uint16_t reta_size);
 185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 186                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 187                                   uint16_t reta_size);
 188
 189 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 190                         struct rte_eth_ntuple_filter *ntuple_filter);
 191 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 192                         struct rte_eth_ntuple_filter *ntuple_filter);
 193 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 194                         struct rte_eth_ntuple_filter *ntuple_filter);
 195 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 196                         struct rte_eth_ntuple_filter *ntuple_filter);
 197 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 198                         struct rte_eth_ntuple_filter *filter);
 199 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 200                                 enum rte_filter_op filter_op,
 201                                 void *arg);
 202 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 203                      enum rte_filter_type filter_type,
 204                      enum rte_filter_op filter_op,
 205                      void *arg);
 206 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 207 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 208                 struct rte_dev_reg_info *regs);
 209 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 210 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 211                 struct rte_dev_eeprom_info *eeprom);
 212 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 213                 struct rte_dev_eeprom_info *eeprom);
 214 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
 215                                    struct rte_eth_dev_module_info *modinfo);
 216 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
 217                                      struct rte_dev_eeprom_info *info);
 218 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 219                                     struct rte_ether_addr *mc_addr_set,
 220                                     uint32_t nb_mc_addr);
 221 static int igb_timesync_enable(struct rte_eth_dev *dev);
 222 static int igb_timesync_disable(struct rte_eth_dev *dev);
 223 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 224                                           struct timespec *timestamp,
 225                                           uint32_t flags);
 226 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 227                                           struct timespec *timestamp);
 228 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 229 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 230                                   struct timespec *timestamp);
 231 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 232                                    const struct timespec *timestamp);
 233 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 234                                         uint16_t queue_id);
 235 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 236                                          uint16_t queue_id);
 237 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 238                                        uint8_t queue, uint8_t msix_vector);
 239 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 240                                uint8_t index, uint8_t offset);
 241 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 242 static void eth_igbvf_interrupt_handler(void *param);
 243 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 244 static int igb_filter_restore(struct rte_eth_dev *dev);
 245
 246 /*
 247  * Define VF Stats MACRO for Non "cleared on read" register
 248  */
 249 #define UPDATE_VF_STAT(reg, last, cur)            \
 250 {                                                 \
 251         u32 latest = E1000_READ_REG(hw, reg);     \
 252         cur += (latest - last) & UINT_MAX;        \
 253         last = latest;                            \
 254 }
 255
 256 #define IGB_FC_PAUSE_TIME 0x0680
 257 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 258 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 259
 260 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 261
 262 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 263
 264 /*
 265  * The set of PCI devices this driver supports
 266  */
 267 static const struct rte_pci_id pci_id_igb_map[] = {
 268         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 269         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 270         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 271         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 272         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 273         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 274         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 275         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 276
 277         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 278         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 279         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 280
 281         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 282         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 284         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 285         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 286         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 287
 288         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 289         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 290         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 291         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 292         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 295         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 296         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 297         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 302         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 303         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 304         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 305         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 309         { .vendor_id = 0, /* sentinel */ },
 310 };
 311
 312 /*
 313  * The set of PCI devices this driver supports (for 82576&I350 VF)
 314  */
 315 static const struct rte_pci_id pci_id_igbvf_map[] = {
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 320         { .vendor_id = 0, /* sentinel */ },
 321 };
 322
 323 static const struct rte_eth_desc_lim rx_desc_lim = {
 324         .nb_max = E1000_MAX_RING_DESC,
 325         .nb_min = E1000_MIN_RING_DESC,
 326         .nb_align = IGB_RXD_ALIGN,
 327 };
 328
 329 static const struct rte_eth_desc_lim tx_desc_lim = {
 330         .nb_max = E1000_MAX_RING_DESC,
 331         .nb_min = E1000_MIN_RING_DESC,
 332         .nb_align = IGB_RXD_ALIGN,
 333         .nb_seg_max = IGB_TX_MAX_SEG,
 334         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 335 };
 336
 337 static const struct eth_dev_ops eth_igb_ops = {
 338         .dev_configure        = eth_igb_configure,
 339         .dev_start            = eth_igb_start,
 340         .dev_stop             = eth_igb_stop,
 341         .dev_set_link_up      = eth_igb_dev_set_link_up,
 342         .dev_set_link_down    = eth_igb_dev_set_link_down,
 343         .dev_close            = eth_igb_close,
 344         .dev_reset            = eth_igb_reset,
 345         .promiscuous_enable   = eth_igb_promiscuous_enable,
 346         .promiscuous_disable  = eth_igb_promiscuous_disable,
 347         .allmulticast_enable  = eth_igb_allmulticast_enable,
 348         .allmulticast_disable = eth_igb_allmulticast_disable,
 349         .link_update          = eth_igb_link_update,
 350         .stats_get            = eth_igb_stats_get,
 351         .xstats_get           = eth_igb_xstats_get,
 352         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 353         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 354         .xstats_get_names     = eth_igb_xstats_get_names,
 355         .stats_reset          = eth_igb_stats_reset,
 356         .xstats_reset         = eth_igb_xstats_reset,
 357         .fw_version_get       = eth_igb_fw_version_get,
 358         .dev_infos_get        = eth_igb_infos_get,
 359         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 360         .mtu_set              = eth_igb_mtu_set,
 361         .vlan_filter_set      = eth_igb_vlan_filter_set,
 362         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 363         .vlan_offload_set     = eth_igb_vlan_offload_set,
 364         .rx_queue_setup       = eth_igb_rx_queue_setup,
 365         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 366         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 367         .rx_queue_release     = eth_igb_rx_queue_release,
 368         .tx_queue_setup       = eth_igb_tx_queue_setup,
 369         .tx_queue_release     = eth_igb_tx_queue_release,
 370         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 371         .dev_led_on           = eth_igb_led_on,
 372         .dev_led_off          = eth_igb_led_off,
 373         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 374         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 375         .mac_addr_add         = eth_igb_rar_set,
 376         .mac_addr_remove      = eth_igb_rar_clear,
 377         .mac_addr_set         = eth_igb_default_mac_addr_set,
 378         .reta_update          = eth_igb_rss_reta_update,
 379         .reta_query           = eth_igb_rss_reta_query,
 380         .rss_hash_update      = eth_igb_rss_hash_update,
 381         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 382         .filter_ctrl          = eth_igb_filter_ctrl,
 383         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 384         .rxq_info_get         = igb_rxq_info_get,
 385         .txq_info_get         = igb_txq_info_get,
 386         .timesync_enable      = igb_timesync_enable,
 387         .timesync_disable     = igb_timesync_disable,
 388         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 389         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 390         .get_reg              = eth_igb_get_regs,
 391         .get_eeprom_length    = eth_igb_get_eeprom_length,
 392         .get_eeprom           = eth_igb_get_eeprom,
 393         .set_eeprom           = eth_igb_set_eeprom,
 394         .get_module_info      = eth_igb_get_module_info,
 395         .get_module_eeprom    = eth_igb_get_module_eeprom,
 396         .timesync_adjust_time = igb_timesync_adjust_time,
 397         .timesync_read_time   = igb_timesync_read_time,
 398         .timesync_write_time  = igb_timesync_write_time,
 399 };
 400
 401 /*
 402  * dev_ops for virtual function, bare necessities for basic vf
 403  * operation have been implemented
 404  */
 405 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 406         .dev_configure        = igbvf_dev_configure,
 407         .dev_start            = igbvf_dev_start,
 408         .dev_stop             = igbvf_dev_stop,
 409         .dev_close            = igbvf_dev_close,
 410         .promiscuous_enable   = igbvf_promiscuous_enable,
 411         .promiscuous_disable  = igbvf_promiscuous_disable,
 412         .allmulticast_enable  = igbvf_allmulticast_enable,
 413         .allmulticast_disable = igbvf_allmulticast_disable,
 414         .link_update          = eth_igb_link_update,
 415         .stats_get            = eth_igbvf_stats_get,
 416         .xstats_get           = eth_igbvf_xstats_get,
 417         .xstats_get_names     = eth_igbvf_xstats_get_names,
 418         .stats_reset          = eth_igbvf_stats_reset,
 419         .xstats_reset         = eth_igbvf_stats_reset,
 420         .vlan_filter_set      = igbvf_vlan_filter_set,
 421         .dev_infos_get        = eth_igbvf_infos_get,
 422         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 423         .rx_queue_setup       = eth_igb_rx_queue_setup,
 424         .rx_queue_release     = eth_igb_rx_queue_release,
 425         .tx_queue_setup       = eth_igb_tx_queue_setup,
 426         .tx_queue_release     = eth_igb_tx_queue_release,
 427         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 428         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 429         .rxq_info_get         = igb_rxq_info_get,
 430         .txq_info_get         = igb_txq_info_get,
 431         .mac_addr_set         = igbvf_default_mac_addr_set,
 432         .get_reg              = igbvf_get_regs,
 433 };
 434
 435 /* store statistics names and its offset in stats structure */
 436 struct rte_igb_xstats_name_off {
 437         char name[RTE_ETH_XSTATS_NAME_SIZE];
 438         unsigned offset;
 439 };
 440
 441 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 442         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 443         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 444         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 445         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 446         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 447         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 448         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 449                 ecol)},
 450         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 451         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 452         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 453         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 454         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 455         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 456         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 457         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 458         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 459         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 460         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 461                 fcruc)},
 462         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 463         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 464         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 465         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 466         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 467                 prc1023)},
 468         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 469                 prc1522)},
 470         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 471         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 472         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 473         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 474         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 475         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 476         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 477         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 478         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 479         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 480         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 481         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 482         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 483         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 484         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 485         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 486         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 487         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 488                 ptc1023)},
 489         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 490                 ptc1522)},
 491         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 492         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 493         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 494         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 495         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 496         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 497         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 498
 499         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 500 };
 501
 502 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 503                 sizeof(rte_igb_stats_strings[0]))
 504
 505 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 506         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 507         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 508         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 509         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 510         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 511 };
 512
 513 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 514                 sizeof(rte_igbvf_stats_strings[0]))
 515
 516
 517 static inline void
 518 igb_intr_enable(struct rte_eth_dev *dev)
 519 {
 520         struct e1000_interrupt *intr =
 521                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 522         struct e1000_hw *hw =
 523                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 524         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 525         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 526
 527         if (rte_intr_allow_others(intr_handle) &&
 528                 dev->data->dev_conf.intr_conf.lsc != 0) {
 529                 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
 530         }
 531
 532         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 533         E1000_WRITE_FLUSH(hw);
 534 }
 535
 536 static void
 537 igb_intr_disable(struct rte_eth_dev *dev)
 538 {
 539         struct e1000_hw *hw =
 540                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 541         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 542         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 543
 544         if (rte_intr_allow_others(intr_handle) &&
 545                 dev->data->dev_conf.intr_conf.lsc != 0) {
 546                 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
 547         }
 548
 549         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 550         E1000_WRITE_FLUSH(hw);
 551 }
 552
 553 static inline void
 554 igbvf_intr_enable(struct rte_eth_dev *dev)
 555 {
 556         struct e1000_hw *hw =
 557                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 558
 559         /* only for mailbox */
 560         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 561         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 562         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 563         E1000_WRITE_FLUSH(hw);
 564 }
 565
 566 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 567 static void
 568 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 569 {
 570         uint32_t tmp = 0;
 571
 572         /* mailbox */
 573         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 574         tmp |= E1000_VTIVAR_VALID;
 575         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 576 }
 577
 578 static void
 579 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 580 {
 581         struct e1000_hw *hw =
 582                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 583
 584         /* Configure VF other cause ivar */
 585         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 586 }
 587
 588 static inline int32_t
 589 igb_pf_reset_hw(struct e1000_hw *hw)
 590 {
 591         uint32_t ctrl_ext;
 592         int32_t status;
 593
 594         status = e1000_reset_hw(hw);
 595
 596         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 597         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 598         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 599         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 600         E1000_WRITE_FLUSH(hw);
 601
 602         return status;
 603 }
 604
 605 static void
 606 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 607 {
 608         struct e1000_hw *hw =
 609                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 610
 611
 612         hw->vendor_id = pci_dev->id.vendor_id;
 613         hw->device_id = pci_dev->id.device_id;
 614         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 615         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 616
 617         e1000_set_mac_type(hw);
 618
 619         /* need to check if it is a vf device below */
 620 }
 621
 622 static int
 623 igb_reset_swfw_lock(struct e1000_hw *hw)
 624 {
 625         int ret_val;
 626
 627         /*
 628          * Do mac ops initialization manually here, since we will need
 629          * some function pointers set by this call.
 630          */
 631         ret_val = e1000_init_mac_params(hw);
 632         if (ret_val)
 633                 return ret_val;
 634
 635         /*
 636          * SMBI lock should not fail in this early stage. If this is the case,
 637          * it is due to an improper exit of the application.
 638          * So force the release of the faulty lock.
 639          */
 640         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 641                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 642         }
 643         e1000_put_hw_semaphore_generic(hw);
 644
 645         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 646                 uint16_t mask;
 647
 648                 /*
 649                  * Phy lock should not fail in this early stage. If this is the case,
 650                  * it is due to an improper exit of the application.
 651                  * So force the release of the faulty lock.
 652                  */
 653                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 654                 if (hw->bus.func > E1000_FUNC_1)
 655                         mask <<= 2;
 656                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 657                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 658                                     hw->bus.func);
 659                 }
 660                 hw->mac.ops.release_swfw_sync(hw, mask);
 661
 662                 /*
 663                  * This one is more tricky since it is common to all ports; but
 664                  * swfw_sync retries last long enough (1s) to be almost sure that if
 665                  * lock can not be taken it is due to an improper lock of the
 666                  * semaphore.
 667                  */
 668                 mask = E1000_SWFW_EEP_SM;
 669                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 670                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 671                 }
 672                 hw->mac.ops.release_swfw_sync(hw, mask);
 673         }
 674
 675         return E1000_SUCCESS;
 676 }
 677
 678 /* Remove all ntuple filters of the device */
 679 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 680 {
 681         struct e1000_filter_info *filter_info =
 682                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 683         struct e1000_5tuple_filter *p_5tuple;
 684         struct e1000_2tuple_filter *p_2tuple;
 685
 686         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 687                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 688                         p_5tuple, entries);
 689                         rte_free(p_5tuple);
 690         }
 691         filter_info->fivetuple_mask = 0;
 692         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 693                 TAILQ_REMOVE(&filter_info->twotuple_list,
 694                         p_2tuple, entries);
 695                         rte_free(p_2tuple);
 696         }
 697         filter_info->twotuple_mask = 0;
 698
 699         return 0;
 700 }
 701
 702 /* Remove all flex filters of the device */
 703 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 704 {
 705         struct e1000_filter_info *filter_info =
 706                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 707         struct e1000_flex_filter *p_flex;
 708
 709         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 710                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 711                 rte_free(p_flex);
 712         }
 713         filter_info->flex_mask = 0;
 714
 715         return 0;
 716 }
 717
 718 static int
 719 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 720 {
 721         int error = 0;
 722         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 723         struct e1000_hw *hw =
 724                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 725         struct e1000_vfta * shadow_vfta =
 726                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 727         struct e1000_filter_info *filter_info =
 728                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 729         struct e1000_adapter *adapter =
 730                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 731
 732         uint32_t ctrl_ext;
 733
 734         eth_dev->dev_ops = &eth_igb_ops;
 735         eth_dev->rx_queue_count = eth_igb_rx_queue_count;
 736         eth_dev->rx_descriptor_done   = eth_igb_rx_descriptor_done;
 737         eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
 738         eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
 739         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 740         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 741         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 742
 743         /* for secondary processes, we don't initialise any further as primary
 744          * has already done this work. Only check we don't need a different
 745          * RX function */
 746         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 747                 if (eth_dev->data->scattered_rx)
 748                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 749                 return 0;
 750         }
 751
 752         rte_eth_copy_pci_info(eth_dev, pci_dev);
 753         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 754
 755         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 756
 757         igb_identify_hardware(eth_dev, pci_dev);
 758         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 759                 error = -EIO;
 760                 goto err_late;
 761         }
 762
 763         e1000_get_bus_info(hw);
 764
 765         /* Reset any pending lock */
 766         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 767                 error = -EIO;
 768                 goto err_late;
 769         }
 770
 771         /* Finish initialization */
 772         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 773                 error = -EIO;
 774                 goto err_late;
 775         }
 776
 777         hw->mac.autoneg = 1;
 778         hw->phy.autoneg_wait_to_complete = 0;
 779         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 780
 781         /* Copper options */
 782         if (hw->phy.media_type == e1000_media_type_copper) {
 783                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 784                 hw->phy.disable_polarity_correction = 0;
 785                 hw->phy.ms_type = e1000_ms_hw_default;
 786         }
 787
 788         /*
 789          * Start from a known state, this is important in reading the nvm
 790          * and mac from that.
 791          */
 792         igb_pf_reset_hw(hw);
 793
 794         /* Make sure we have a good EEPROM before we read from it */
 795         if (e1000_validate_nvm_checksum(hw) < 0) {
 796                 /*
 797                  * Some PCI-E parts fail the first check due to
 798                  * the link being in sleep state, call it again,
 799                  * if it fails a second time its a real issue.
 800                  */
 801                 if (e1000_validate_nvm_checksum(hw) < 0) {
 802                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 803                         error = -EIO;
 804                         goto err_late;
 805                 }
 806         }
 807
 808         /* Read the permanent MAC address out of the EEPROM */
 809         if (e1000_read_mac_addr(hw) != 0) {
 810                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 811                 error = -EIO;
 812                 goto err_late;
 813         }
 814
 815         /* Allocate memory for storing MAC addresses */
 816         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 817                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 818         if (eth_dev->data->mac_addrs == NULL) {
 819                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 820                                                 "store MAC addresses",
 821                                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 822                 error = -ENOMEM;
 823                 goto err_late;
 824         }
 825
 826         /* Copy the permanent MAC address */
 827         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 828                         &eth_dev->data->mac_addrs[0]);
 829
 830         /* initialize the vfta */
 831         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 832
 833         /* Now initialize the hardware */
 834         if (igb_hardware_init(hw) != 0) {
 835                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 836                 rte_free(eth_dev->data->mac_addrs);
 837                 eth_dev->data->mac_addrs = NULL;
 838                 error = -ENODEV;
 839                 goto err_late;
 840         }
 841         hw->mac.get_link_status = 1;
 842         adapter->stopped = 0;
 843
 844         /* Indicate SOL/IDER usage */
 845         if (e1000_check_reset_block(hw) < 0) {
 846                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 847                                         "SOL/IDER session");
 848         }
 849
 850         /* initialize PF if max_vfs not zero */
 851         igb_pf_host_init(eth_dev);
 852
 853         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 854         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 855         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 856         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 857         E1000_WRITE_FLUSH(hw);
 858
 859         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 860                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 861                      pci_dev->id.device_id);
 862
 863         rte_intr_callback_register(&pci_dev->intr_handle,
 864                                    eth_igb_interrupt_handler,
 865                                    (void *)eth_dev);
 866
 867         /* enable uio/vfio intr/eventfd mapping */
 868         rte_intr_enable(&pci_dev->intr_handle);
 869
 870         /* enable support intr */
 871         igb_intr_enable(eth_dev);
 872
 873         eth_igb_dev_set_link_down(eth_dev);
 874
 875         /* initialize filter info */
 876         memset(filter_info, 0,
 877                sizeof(struct e1000_filter_info));
 878
 879         TAILQ_INIT(&filter_info->flex_list);
 880         TAILQ_INIT(&filter_info->twotuple_list);
 881         TAILQ_INIT(&filter_info->fivetuple_list);
 882
 883         TAILQ_INIT(&igb_filter_ntuple_list);
 884         TAILQ_INIT(&igb_filter_ethertype_list);
 885         TAILQ_INIT(&igb_filter_syn_list);
 886         TAILQ_INIT(&igb_filter_flex_list);
 887         TAILQ_INIT(&igb_filter_rss_list);
 888         TAILQ_INIT(&igb_flow_list);
 889
 890         return 0;
 891
 892 err_late:
 893         igb_hw_control_release(hw);
 894
 895         return error;
 896 }
 897
 898 static int
 899 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 900 {
 901         PMD_INIT_FUNC_TRACE();
 902
 903         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 904                 return 0;
 905
 906         eth_igb_close(eth_dev);
 907
 908         return 0;
 909 }
 910
 911 /*
 912  * Virtual Function device init
 913  */
 914 static int
 915 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 916 {
 917         struct rte_pci_device *pci_dev;
 918         struct rte_intr_handle *intr_handle;
 919         struct e1000_adapter *adapter =
 920                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 921         struct e1000_hw *hw =
 922                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 923         int diag;
 924         struct rte_ether_addr *perm_addr =
 925                 (struct rte_ether_addr *)hw->mac.perm_addr;
 926
 927         PMD_INIT_FUNC_TRACE();
 928
 929         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 930         eth_dev->rx_descriptor_done   = eth_igb_rx_descriptor_done;
 931         eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
 932         eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
 933         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 934         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 935         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 936
 937         /* for secondary processes, we don't initialise any further as primary
 938          * has already done this work. Only check we don't need a different
 939          * RX function */
 940         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 941                 if (eth_dev->data->scattered_rx)
 942                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 943                 return 0;
 944         }
 945
 946         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 947         rte_eth_copy_pci_info(eth_dev, pci_dev);
 948         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 949
 950         hw->device_id = pci_dev->id.device_id;
 951         hw->vendor_id = pci_dev->id.vendor_id;
 952         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 953         adapter->stopped = 0;
 954
 955         /* Initialize the shared code (base driver) */
 956         diag = e1000_setup_init_funcs(hw, TRUE);
 957         if (diag != 0) {
 958                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 959                         diag);
 960                 return -EIO;
 961         }
 962
 963         /* init_mailbox_params */
 964         hw->mbx.ops.init_params(hw);
 965
 966         /* Disable the interrupts for VF */
 967         igbvf_intr_disable(hw);
 968
 969         diag = hw->mac.ops.reset_hw(hw);
 970
 971         /* Allocate memory for storing MAC addresses */
 972         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
 973                 hw->mac.rar_entry_count, 0);
 974         if (eth_dev->data->mac_addrs == NULL) {
 975                 PMD_INIT_LOG(ERR,
 976                         "Failed to allocate %d bytes needed to store MAC "
 977                         "addresses",
 978                         RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 979                 return -ENOMEM;
 980         }
 981
 982         /* Generate a random MAC address, if none was assigned by PF. */
 983         if (rte_is_zero_ether_addr(perm_addr)) {
 984                 rte_eth_random_addr(perm_addr->addr_bytes);
 985                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
 986                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
 987                              "%02x:%02x:%02x:%02x:%02x:%02x",
 988                              perm_addr->addr_bytes[0],
 989                              perm_addr->addr_bytes[1],
 990                              perm_addr->addr_bytes[2],
 991                              perm_addr->addr_bytes[3],
 992                              perm_addr->addr_bytes[4],
 993                              perm_addr->addr_bytes[5]);
 994         }
 995
 996         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
 997         if (diag) {
 998                 rte_free(eth_dev->data->mac_addrs);
 999                 eth_dev->data->mac_addrs = NULL;
1000                 return diag;
1001         }
1002         /* Copy the permanent MAC address */
1003         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1004                         &eth_dev->data->mac_addrs[0]);
1005
1006         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1007                      "mac.type=%s",
1008                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1009                      pci_dev->id.device_id, "igb_mac_82576_vf");
1010
1011         intr_handle = &pci_dev->intr_handle;
1012         rte_intr_callback_register(intr_handle,
1013                                    eth_igbvf_interrupt_handler, eth_dev);
1014
1015         return 0;
1016 }
1017
1018 static int
1019 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1020 {
1021         PMD_INIT_FUNC_TRACE();
1022
1023         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1024                 return 0;
1025
1026         igbvf_dev_close(eth_dev);
1027
1028         return 0;
1029 }
1030
1031 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1032         struct rte_pci_device *pci_dev)
1033 {
1034         return rte_eth_dev_pci_generic_probe(pci_dev,
1035                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1036 }
1037
1038 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1039 {
1040         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1041 }
1042
1043 static struct rte_pci_driver rte_igb_pmd = {
1044         .id_table = pci_id_igb_map,
1045         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1046         .probe = eth_igb_pci_probe,
1047         .remove = eth_igb_pci_remove,
1048 };
1049
1050
1051 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1052         struct rte_pci_device *pci_dev)
1053 {
1054         return rte_eth_dev_pci_generic_probe(pci_dev,
1055                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1056 }
1057
1058 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1059 {
1060         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1061 }
1062
1063 /*
1064  * virtual function driver struct
1065  */
1066 static struct rte_pci_driver rte_igbvf_pmd = {
1067         .id_table = pci_id_igbvf_map,
1068         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1069         .probe = eth_igbvf_pci_probe,
1070         .remove = eth_igbvf_pci_remove,
1071 };
1072
1073 static void
1074 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1075 {
1076         struct e1000_hw *hw =
1077                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1078         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1079         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1080         rctl |= E1000_RCTL_VFE;
1081         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1082 }
1083
1084 static int
1085 igb_check_mq_mode(struct rte_eth_dev *dev)
1086 {
1087         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1088         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1089         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1090         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1091
1092         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1093             tx_mq_mode == ETH_MQ_TX_DCB ||
1094             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1095                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1096                 return -EINVAL;
1097         }
1098         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1099                 /* Check multi-queue mode.
1100                  * To no break software we accept ETH_MQ_RX_NONE as this might
1101                  * be used to turn off VLAN filter.
1102                  */
1103
1104                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1105                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1106                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1107                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1108                 } else {
1109                         /* Only support one queue on VFs.
1110                          * RSS together with SRIOV is not supported.
1111                          */
1112                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1113                                         " wrong mq_mode rx %d.",
1114                                         rx_mq_mode);
1115                         return -EINVAL;
1116                 }
1117                 /* TX mode is not used here, so mode might be ignored.*/
1118                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1119                         /* SRIOV only works in VMDq enable mode */
1120                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1121                                         " TX mode %d is not supported. "
1122                                         " Driver will behave as %d mode.",
1123                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1124                 }
1125
1126                 /* check valid queue number */
1127                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1128                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1129                                         " only support one queue on VFs.");
1130                         return -EINVAL;
1131                 }
1132         } else {
1133                 /* To no break software that set invalid mode, only display
1134                  * warning if invalid mode is used.
1135                  */
1136                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1137                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1138                     rx_mq_mode != ETH_MQ_RX_RSS) {
1139                         /* RSS together with VMDq not supported*/
1140                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1141                                      rx_mq_mode);
1142                         return -EINVAL;
1143                 }
1144
1145                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1146                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1147                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1148                                         " Due to txmode is meaningless in this"
1149                                         " driver, just ignore.",
1150                                         tx_mq_mode);
1151                 }
1152         }
1153         return 0;
1154 }
1155
1156 static int
1157 eth_igb_configure(struct rte_eth_dev *dev)
1158 {
1159         struct e1000_interrupt *intr =
1160                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1161         int ret;
1162
1163         PMD_INIT_FUNC_TRACE();
1164
1165         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1166                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1167
1168         /* multipe queue mode checking */
1169         ret  = igb_check_mq_mode(dev);
1170         if (ret != 0) {
1171                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1172                             ret);
1173                 return ret;
1174         }
1175
1176         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1177         PMD_INIT_FUNC_TRACE();
1178
1179         return 0;
1180 }
1181
1182 static void
1183 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1184                      bool enable)
1185 {
1186         struct e1000_hw *hw =
1187                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1188         uint32_t tctl, rctl;
1189
1190         tctl = E1000_READ_REG(hw, E1000_TCTL);
1191         rctl = E1000_READ_REG(hw, E1000_RCTL);
1192
1193         if (enable) {
1194                 /* enable Tx/Rx */
1195                 tctl |= E1000_TCTL_EN;
1196                 rctl |= E1000_RCTL_EN;
1197         } else {
1198                 /* disable Tx/Rx */
1199                 tctl &= ~E1000_TCTL_EN;
1200                 rctl &= ~E1000_RCTL_EN;
1201         }
1202         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1203         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1204         E1000_WRITE_FLUSH(hw);
1205 }
1206
1207 static int
1208 eth_igb_start(struct rte_eth_dev *dev)
1209 {
1210         struct e1000_hw *hw =
1211                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1212         struct e1000_adapter *adapter =
1213                 E1000_DEV_PRIVATE(dev->data->dev_private);
1214         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1215         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1216         int ret, mask;
1217         uint32_t intr_vector = 0;
1218         uint32_t ctrl_ext;
1219         uint32_t *speeds;
1220         int num_speeds;
1221         bool autoneg;
1222
1223         PMD_INIT_FUNC_TRACE();
1224
1225         /* disable uio/vfio intr/eventfd mapping */
1226         rte_intr_disable(intr_handle);
1227
1228         /* Power up the phy. Needed to make the link go Up */
1229         eth_igb_dev_set_link_up(dev);
1230
1231         /*
1232          * Packet Buffer Allocation (PBA)
1233          * Writing PBA sets the receive portion of the buffer
1234          * the remainder is used for the transmit buffer.
1235          */
1236         if (hw->mac.type == e1000_82575) {
1237                 uint32_t pba;
1238
1239                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1240                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1241         }
1242
1243         /* Put the address into the Receive Address Array */
1244         e1000_rar_set(hw, hw->mac.addr, 0);
1245
1246         /* Initialize the hardware */
1247         if (igb_hardware_init(hw)) {
1248                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1249                 return -EIO;
1250         }
1251         adapter->stopped = 0;
1252
1253         E1000_WRITE_REG(hw, E1000_VET,
1254                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1255
1256         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1257         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1258         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1259         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1260         E1000_WRITE_FLUSH(hw);
1261
1262         /* configure PF module if SRIOV enabled */
1263         igb_pf_host_configure(dev);
1264
1265         /* check and configure queue intr-vector mapping */
1266         if ((rte_intr_cap_multiple(intr_handle) ||
1267              !RTE_ETH_DEV_SRIOV(dev).active) &&
1268             dev->data->dev_conf.intr_conf.rxq != 0) {
1269                 intr_vector = dev->data->nb_rx_queues;
1270                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1271                         return -1;
1272         }
1273
1274         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1275                 intr_handle->intr_vec =
1276                         rte_zmalloc("intr_vec",
1277                                     dev->data->nb_rx_queues * sizeof(int), 0);
1278                 if (intr_handle->intr_vec == NULL) {
1279                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1280                                      " intr_vec", dev->data->nb_rx_queues);
1281                         return -ENOMEM;
1282                 }
1283         }
1284
1285         /* confiugre msix for rx interrupt */
1286         eth_igb_configure_msix_intr(dev);
1287
1288         /* Configure for OS presence */
1289         igb_init_manageability(hw);
1290
1291         eth_igb_tx_init(dev);
1292
1293         /* This can fail when allocating mbufs for descriptor rings */
1294         ret = eth_igb_rx_init(dev);
1295         if (ret) {
1296                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1297                 igb_dev_clear_queues(dev);
1298                 return ret;
1299         }
1300
1301         e1000_clear_hw_cntrs_base_generic(hw);
1302
1303         /*
1304          * VLAN Offload Settings
1305          */
1306         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1307                         ETH_VLAN_EXTEND_MASK;
1308         ret = eth_igb_vlan_offload_set(dev, mask);
1309         if (ret) {
1310                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1311                 igb_dev_clear_queues(dev);
1312                 return ret;
1313         }
1314
1315         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1316                 /* Enable VLAN filter since VMDq always use VLAN filter */
1317                 igb_vmdq_vlan_hw_filter_enable(dev);
1318         }
1319
1320         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1321                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1322                 (hw->mac.type == e1000_i211)) {
1323                 /* Configure EITR with the maximum possible value (0xFFFF) */
1324                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1325         }
1326
1327         /* Setup link speed and duplex */
1328         speeds = &dev->data->dev_conf.link_speeds;
1329         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1330                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1331                 hw->mac.autoneg = 1;
1332         } else {
1333                 num_speeds = 0;
1334                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1335
1336                 /* Reset */
1337                 hw->phy.autoneg_advertised = 0;
1338
1339                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1340                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1341                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1342                         num_speeds = -1;
1343                         goto error_invalid_config;
1344                 }
1345                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1346                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1347                         num_speeds++;
1348                 }
1349                 if (*speeds & ETH_LINK_SPEED_10M) {
1350                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1351                         num_speeds++;
1352                 }
1353                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1354                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1355                         num_speeds++;
1356                 }
1357                 if (*speeds & ETH_LINK_SPEED_100M) {
1358                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1359                         num_speeds++;
1360                 }
1361                 if (*speeds & ETH_LINK_SPEED_1G) {
1362                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1363                         num_speeds++;
1364                 }
1365                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1366                         goto error_invalid_config;
1367
1368                 /* Set/reset the mac.autoneg based on the link speed,
1369                  * fixed or not
1370                  */
1371                 if (!autoneg) {
1372                         hw->mac.autoneg = 0;
1373                         hw->mac.forced_speed_duplex =
1374                                         hw->phy.autoneg_advertised;
1375                 } else {
1376                         hw->mac.autoneg = 1;
1377                 }
1378         }
1379
1380         e1000_setup_link(hw);
1381
1382         if (rte_intr_allow_others(intr_handle)) {
1383                 /* check if lsc interrupt is enabled */
1384                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1385                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1386                 else
1387                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1388         } else {
1389                 rte_intr_callback_unregister(intr_handle,
1390                                              eth_igb_interrupt_handler,
1391                                              (void *)dev);
1392                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1393                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1394                                      " no intr multiplex");
1395         }
1396
1397         /* check if rxq interrupt is enabled */
1398         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1399             rte_intr_dp_is_en(intr_handle))
1400                 eth_igb_rxq_interrupt_setup(dev);
1401
1402         /* enable uio/vfio intr/eventfd mapping */
1403         rte_intr_enable(intr_handle);
1404
1405         /* resume enabled intr since hw reset */
1406         igb_intr_enable(dev);
1407
1408         /* restore all types filter */
1409         igb_filter_restore(dev);
1410
1411         eth_igb_rxtx_control(dev, true);
1412         eth_igb_link_update(dev, 0);
1413
1414         PMD_INIT_LOG(DEBUG, "<<");
1415
1416         return 0;
1417
1418 error_invalid_config:
1419         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1420                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1421         igb_dev_clear_queues(dev);
1422         return -EINVAL;
1423 }
1424
1425 /*********************************************************************
1426  *
1427  *  This routine disables all traffic on the adapter by issuing a
1428  *  global reset on the MAC.
1429  *
1430  **********************************************************************/
1431 static int
1432 eth_igb_stop(struct rte_eth_dev *dev)
1433 {
1434         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1435         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1436         struct rte_eth_link link;
1437         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1438         struct e1000_adapter *adapter =
1439                 E1000_DEV_PRIVATE(dev->data->dev_private);
1440
1441         if (adapter->stopped)
1442                 return 0;
1443
1444         eth_igb_rxtx_control(dev, false);
1445
1446         igb_intr_disable(dev);
1447
1448         /* disable intr eventfd mapping */
1449         rte_intr_disable(intr_handle);
1450
1451         igb_pf_reset_hw(hw);
1452         E1000_WRITE_REG(hw, E1000_WUC, 0);
1453
1454         /* Set bit for Go Link disconnect if PHY reset is not blocked */
1455         if (hw->mac.type >= e1000_82580 &&
1456             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1457                 uint32_t phpm_reg;
1458
1459                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1460                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1461                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1462         }
1463
1464         /* Power down the phy. Needed to make the link go Down */
1465         eth_igb_dev_set_link_down(dev);
1466
1467         igb_dev_clear_queues(dev);
1468
1469         /* clear the recorded link status */
1470         memset(&link, 0, sizeof(link));
1471         rte_eth_linkstatus_set(dev, &link);
1472
1473         if (!rte_intr_allow_others(intr_handle))
1474                 /* resume to the default handler */
1475                 rte_intr_callback_register(intr_handle,
1476                                            eth_igb_interrupt_handler,
1477                                            (void *)dev);
1478
1479         /* Clean datapath event and queue/vec mapping */
1480         rte_intr_efd_disable(intr_handle);
1481         if (intr_handle->intr_vec != NULL) {
1482                 rte_free(intr_handle->intr_vec);
1483                 intr_handle->intr_vec = NULL;
1484         }
1485
1486         adapter->stopped = true;
1487         dev->data->dev_started = 0;
1488
1489         return 0;
1490 }
1491
1492 static int
1493 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1494 {
1495         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1496
1497         if (hw->phy.media_type == e1000_media_type_copper)
1498                 e1000_power_up_phy(hw);
1499         else
1500                 e1000_power_up_fiber_serdes_link(hw);
1501
1502         return 0;
1503 }
1504
1505 static int
1506 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1507 {
1508         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1509
1510         if (hw->phy.media_type == e1000_media_type_copper)
1511                 e1000_power_down_phy(hw);
1512         else
1513                 e1000_shutdown_fiber_serdes_link(hw);
1514
1515         return 0;
1516 }
1517
1518 static int
1519 eth_igb_close(struct rte_eth_dev *dev)
1520 {
1521         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1522         struct rte_eth_link link;
1523         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1524         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1525         struct e1000_filter_info *filter_info =
1526                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1527         int ret;
1528
1529         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1530                 return 0;
1531
1532         ret = eth_igb_stop(dev);
1533
1534         e1000_phy_hw_reset(hw);
1535         igb_release_manageability(hw);
1536         igb_hw_control_release(hw);
1537
1538         /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1539         if (hw->mac.type >= e1000_82580 &&
1540             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1541                 uint32_t phpm_reg;
1542
1543                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1544                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1545                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1546         }
1547
1548         igb_dev_free_queues(dev);
1549
1550         if (intr_handle->intr_vec) {
1551                 rte_free(intr_handle->intr_vec);
1552                 intr_handle->intr_vec = NULL;
1553         }
1554
1555         memset(&link, 0, sizeof(link));
1556         rte_eth_linkstatus_set(dev, &link);
1557
1558         /* Reset any pending lock */
1559         igb_reset_swfw_lock(hw);
1560
1561         /* uninitialize PF if max_vfs not zero */
1562         igb_pf_host_uninit(dev);
1563
1564         rte_intr_callback_unregister(intr_handle,
1565                                      eth_igb_interrupt_handler, dev);
1566
1567         /* clear the SYN filter info */
1568         filter_info->syn_info = 0;
1569
1570         /* clear the ethertype filters info */
1571         filter_info->ethertype_mask = 0;
1572         memset(filter_info->ethertype_filters, 0,
1573                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1574
1575         /* clear the rss filter info */
1576         memset(&filter_info->rss_info, 0,
1577                 sizeof(struct igb_rte_flow_rss_conf));
1578
1579         /* remove all ntuple filters of the device */
1580         igb_ntuple_filter_uninit(dev);
1581
1582         /* remove all flex filters of the device */
1583         igb_flex_filter_uninit(dev);
1584
1585         /* clear all the filters list */
1586         igb_filterlist_flush(dev);
1587
1588         return ret;
1589 }
1590
1591 /*
1592  * Reset PF device.
1593  */
1594 static int
1595 eth_igb_reset(struct rte_eth_dev *dev)
1596 {
1597         int ret;
1598
1599         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1600          * its VF to make them align with it. The detailed notification
1601          * mechanism is PMD specific and is currently not implemented.
1602          * To avoid unexpected behavior in VF, currently reset of PF with
1603          * SR-IOV activation is not supported. It might be supported later.
1604          */
1605         if (dev->data->sriov.active)
1606                 return -ENOTSUP;
1607
1608         ret = eth_igb_dev_uninit(dev);
1609         if (ret)
1610                 return ret;
1611
1612         ret = eth_igb_dev_init(dev);
1613
1614         return ret;
1615 }
1616
1617
1618 static int
1619 igb_get_rx_buffer_size(struct e1000_hw *hw)
1620 {
1621         uint32_t rx_buf_size;
1622         if (hw->mac.type == e1000_82576) {
1623                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1624         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1625                 /* PBS needs to be translated according to a lookup table */
1626                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1627                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1628                 rx_buf_size = (rx_buf_size << 10);
1629         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1630                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1631         } else {
1632                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1633         }
1634
1635         return rx_buf_size;
1636 }
1637
1638 /*********************************************************************
1639  *
1640  *  Initialize the hardware
1641  *
1642  **********************************************************************/
1643 static int
1644 igb_hardware_init(struct e1000_hw *hw)
1645 {
1646         uint32_t rx_buf_size;
1647         int diag;
1648
1649         /* Let the firmware know the OS is in control */
1650         igb_hw_control_acquire(hw);
1651
1652         /*
1653          * These parameters control the automatic generation (Tx) and
1654          * response (Rx) to Ethernet PAUSE frames.
1655          * - High water mark should allow for at least two standard size (1518)
1656          *   frames to be received after sending an XOFF.
1657          * - Low water mark works best when it is very near the high water mark.
1658          *   This allows the receiver to restart by sending XON when it has
1659          *   drained a bit. Here we use an arbitrary value of 1500 which will
1660          *   restart after one full frame is pulled from the buffer. There
1661          *   could be several smaller frames in the buffer and if so they will
1662          *   not trigger the XON until their total number reduces the buffer
1663          *   by 1500.
1664          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1665          */
1666         rx_buf_size = igb_get_rx_buffer_size(hw);
1667
1668         hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1669         hw->fc.low_water = hw->fc.high_water - 1500;
1670         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1671         hw->fc.send_xon = 1;
1672
1673         /* Set Flow control, use the tunable location if sane */
1674         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1675                 hw->fc.requested_mode = igb_fc_setting;
1676         else
1677                 hw->fc.requested_mode = e1000_fc_none;
1678
1679         /* Issue a global reset */
1680         igb_pf_reset_hw(hw);
1681         E1000_WRITE_REG(hw, E1000_WUC, 0);
1682
1683         diag = e1000_init_hw(hw);
1684         if (diag < 0)
1685                 return diag;
1686
1687         E1000_WRITE_REG(hw, E1000_VET,
1688                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1689         e1000_get_phy_info(hw);
1690         e1000_check_for_link(hw);
1691
1692         return 0;
1693 }
1694
1695 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1696 static void
1697 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1698 {
1699         int pause_frames;
1700
1701         uint64_t old_gprc  = stats->gprc;
1702         uint64_t old_gptc  = stats->gptc;
1703         uint64_t old_tpr   = stats->tpr;
1704         uint64_t old_tpt   = stats->tpt;
1705         uint64_t old_rpthc = stats->rpthc;
1706         uint64_t old_hgptc = stats->hgptc;
1707
1708         if(hw->phy.media_type == e1000_media_type_copper ||
1709             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1710                 stats->symerrs +=
1711                     E1000_READ_REG(hw,E1000_SYMERRS);
1712                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1713         }
1714
1715         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1716         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1717         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1718         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1719
1720         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1721         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1722         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1723         stats->dc += E1000_READ_REG(hw, E1000_DC);
1724         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1725         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1726         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1727         /*
1728         ** For watchdog management we need to know if we have been
1729         ** paused during the last interval, so capture that here.
1730         */
1731         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1732         stats->xoffrxc += pause_frames;
1733         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1734         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1735         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1736         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1737         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1738         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1739         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1740         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1741         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1742         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1743         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1744         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1745
1746         /* For the 64-bit byte counters the low dword must be read first. */
1747         /* Both registers clear on the read of the high dword */
1748
1749         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1750         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1751         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1752         stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1753         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1754         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1755         stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1756
1757         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1758         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1759         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1760         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1761         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1762
1763         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1764         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1765
1766         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1767         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1768         stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1769         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1770         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1771         stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1772
1773         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1774         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1775         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1776         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1777         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1778         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1779         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1780         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1781
1782         /* Interrupt Counts */
1783
1784         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1785         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1786         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1787         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1788         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1789         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1790         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1791         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1792         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1793
1794         /* Host to Card Statistics */
1795
1796         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1797         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1798         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1799         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1800         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1801         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1802         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1803         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1804         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1805         stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1806         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1807         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1808         stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1809         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1810         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1811         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1812
1813         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1814         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1815         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1816         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1817         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1818         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1819 }
1820
1821 static int
1822 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1823 {
1824         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1825         struct e1000_hw_stats *stats =
1826                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1827
1828         igb_read_stats_registers(hw, stats);
1829
1830         if (rte_stats == NULL)
1831                 return -EINVAL;
1832
1833         /* Rx Errors */
1834         rte_stats->imissed = stats->mpc;
1835         rte_stats->ierrors = stats->crcerrs +
1836                              stats->rlec + stats->ruc + stats->roc +
1837                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1838
1839         /* Tx Errors */
1840         rte_stats->oerrors = stats->ecol + stats->latecol;
1841
1842         rte_stats->ipackets = stats->gprc;
1843         rte_stats->opackets = stats->gptc;
1844         rte_stats->ibytes   = stats->gorc;
1845         rte_stats->obytes   = stats->gotc;
1846         return 0;
1847 }
1848
1849 static int
1850 eth_igb_stats_reset(struct rte_eth_dev *dev)
1851 {
1852         struct e1000_hw_stats *hw_stats =
1853                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1854
1855         /* HW registers are cleared on read */
1856         eth_igb_stats_get(dev, NULL);
1857
1858         /* Reset software totals */
1859         memset(hw_stats, 0, sizeof(*hw_stats));
1860
1861         return 0;
1862 }
1863
1864 static int
1865 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1866 {
1867         struct e1000_hw_stats *stats =
1868                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1869
1870         /* HW registers are cleared on read */
1871         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1872
1873         /* Reset software totals */
1874         memset(stats, 0, sizeof(*stats));
1875
1876         return 0;
1877 }
1878
1879 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1880         struct rte_eth_xstat_name *xstats_names,
1881         __rte_unused unsigned int size)
1882 {
1883         unsigned i;
1884
1885         if (xstats_names == NULL)
1886                 return IGB_NB_XSTATS;
1887
1888         /* Note: limit checked in rte_eth_xstats_names() */
1889
1890         for (i = 0; i < IGB_NB_XSTATS; i++) {
1891                 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1892                         sizeof(xstats_names[i].name));
1893         }
1894
1895         return IGB_NB_XSTATS;
1896 }
1897
1898 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1899                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1900                 unsigned int limit)
1901 {
1902         unsigned int i;
1903
1904         if (!ids) {
1905                 if (xstats_names == NULL)
1906                         return IGB_NB_XSTATS;
1907
1908                 for (i = 0; i < IGB_NB_XSTATS; i++)
1909                         strlcpy(xstats_names[i].name,
1910                                 rte_igb_stats_strings[i].name,
1911                                 sizeof(xstats_names[i].name));
1912
1913                 return IGB_NB_XSTATS;
1914
1915         } else {
1916                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1917
1918                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1919                                 IGB_NB_XSTATS);
1920
1921                 for (i = 0; i < limit; i++) {
1922                         if (ids[i] >= IGB_NB_XSTATS) {
1923                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1924                                 return -1;
1925                         }
1926                         strcpy(xstats_names[i].name,
1927                                         xstats_names_copy[ids[i]].name);
1928                 }
1929                 return limit;
1930         }
1931 }
1932
1933 static int
1934 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1935                    unsigned n)
1936 {
1937         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938         struct e1000_hw_stats *hw_stats =
1939                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1940         unsigned i;
1941
1942         if (n < IGB_NB_XSTATS)
1943                 return IGB_NB_XSTATS;
1944
1945         igb_read_stats_registers(hw, hw_stats);
1946
1947         /* If this is a reset xstats is NULL, and we have cleared the
1948          * registers by reading them.
1949          */
1950         if (!xstats)
1951                 return 0;
1952
1953         /* Extended stats */
1954         for (i = 0; i < IGB_NB_XSTATS; i++) {
1955                 xstats[i].id = i;
1956                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1957                         rte_igb_stats_strings[i].offset);
1958         }
1959
1960         return IGB_NB_XSTATS;
1961 }
1962
1963 static int
1964 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1965                 uint64_t *values, unsigned int n)
1966 {
1967         unsigned int i;
1968
1969         if (!ids) {
1970                 struct e1000_hw *hw =
1971                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972                 struct e1000_hw_stats *hw_stats =
1973                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1974
1975                 if (n < IGB_NB_XSTATS)
1976                         return IGB_NB_XSTATS;
1977
1978                 igb_read_stats_registers(hw, hw_stats);
1979
1980                 /* If this is a reset xstats is NULL, and we have cleared the
1981                  * registers by reading them.
1982                  */
1983                 if (!values)
1984                         return 0;
1985
1986                 /* Extended stats */
1987                 for (i = 0; i < IGB_NB_XSTATS; i++)
1988                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1989                                         rte_igb_stats_strings[i].offset);
1990
1991                 return IGB_NB_XSTATS;
1992
1993         } else {
1994                 uint64_t values_copy[IGB_NB_XSTATS];
1995
1996                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1997                                 IGB_NB_XSTATS);
1998
1999                 for (i = 0; i < n; i++) {
2000                         if (ids[i] >= IGB_NB_XSTATS) {
2001                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2002                                 return -1;
2003                         }
2004                         values[i] = values_copy[ids[i]];
2005                 }
2006                 return n;
2007         }
2008 }
2009
2010 static void
2011 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2012 {
2013         /* Good Rx packets, include VF loopback */
2014         UPDATE_VF_STAT(E1000_VFGPRC,
2015             hw_stats->last_gprc, hw_stats->gprc);
2016
2017         /* Good Rx octets, include VF loopback */
2018         UPDATE_VF_STAT(E1000_VFGORC,
2019             hw_stats->last_gorc, hw_stats->gorc);
2020
2021         /* Good Tx packets, include VF loopback */
2022         UPDATE_VF_STAT(E1000_VFGPTC,
2023             hw_stats->last_gptc, hw_stats->gptc);
2024
2025         /* Good Tx octets, include VF loopback */
2026         UPDATE_VF_STAT(E1000_VFGOTC,
2027             hw_stats->last_gotc, hw_stats->gotc);
2028
2029         /* Rx Multicst packets */
2030         UPDATE_VF_STAT(E1000_VFMPRC,
2031             hw_stats->last_mprc, hw_stats->mprc);
2032
2033         /* Good Rx loopback packets */
2034         UPDATE_VF_STAT(E1000_VFGPRLBC,
2035             hw_stats->last_gprlbc, hw_stats->gprlbc);
2036
2037         /* Good Rx loopback octets */
2038         UPDATE_VF_STAT(E1000_VFGORLBC,
2039             hw_stats->last_gorlbc, hw_stats->gorlbc);
2040
2041         /* Good Tx loopback packets */
2042         UPDATE_VF_STAT(E1000_VFGPTLBC,
2043             hw_stats->last_gptlbc, hw_stats->gptlbc);
2044
2045         /* Good Tx loopback octets */
2046         UPDATE_VF_STAT(E1000_VFGOTLBC,
2047             hw_stats->last_gotlbc, hw_stats->gotlbc);
2048 }
2049
2050 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2051                                      struct rte_eth_xstat_name *xstats_names,
2052                                      __rte_unused unsigned limit)
2053 {
2054         unsigned i;
2055
2056         if (xstats_names != NULL)
2057                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2058                         strlcpy(xstats_names[i].name,
2059                                 rte_igbvf_stats_strings[i].name,
2060                                 sizeof(xstats_names[i].name));
2061                 }
2062         return IGBVF_NB_XSTATS;
2063 }
2064
2065 static int
2066 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2067                      unsigned n)
2068 {
2069         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2070         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2071                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2072         unsigned i;
2073
2074         if (n < IGBVF_NB_XSTATS)
2075                 return IGBVF_NB_XSTATS;
2076
2077         igbvf_read_stats_registers(hw, hw_stats);
2078
2079         if (!xstats)
2080                 return 0;
2081
2082         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2083                 xstats[i].id = i;
2084                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2085                         rte_igbvf_stats_strings[i].offset);
2086         }
2087
2088         return IGBVF_NB_XSTATS;
2089 }
2090
2091 static int
2092 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2093 {
2094         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2096                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2097
2098         igbvf_read_stats_registers(hw, hw_stats);
2099
2100         if (rte_stats == NULL)
2101                 return -EINVAL;
2102
2103         rte_stats->ipackets = hw_stats->gprc;
2104         rte_stats->ibytes = hw_stats->gorc;
2105         rte_stats->opackets = hw_stats->gptc;
2106         rte_stats->obytes = hw_stats->gotc;
2107         return 0;
2108 }
2109
2110 static int
2111 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2112 {
2113         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2114                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2115
2116         /* Sync HW register to the last stats */
2117         eth_igbvf_stats_get(dev, NULL);
2118
2119         /* reset HW current stats*/
2120         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2121                offsetof(struct e1000_vf_stats, gprc));
2122
2123         return 0;
2124 }
2125
2126 static int
2127 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2128                        size_t fw_size)
2129 {
2130         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2131         struct e1000_fw_version fw;
2132         int ret;
2133
2134         e1000_get_fw_version(hw, &fw);
2135
2136         switch (hw->mac.type) {
2137         case e1000_i210:
2138         case e1000_i211:
2139                 if (!(e1000_get_flash_presence_i210(hw))) {
2140                         ret = snprintf(fw_version, fw_size,
2141                                  "%2d.%2d-%d",
2142                                  fw.invm_major, fw.invm_minor,
2143                                  fw.invm_img_type);
2144                         break;
2145                 }
2146                 /* fall through */
2147         default:
2148                 /* if option rom is valid, display its version too */
2149                 if (fw.or_valid) {
2150                         ret = snprintf(fw_version, fw_size,
2151                                  "%d.%d, 0x%08x, %d.%d.%d",
2152                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2153                                  fw.or_major, fw.or_build, fw.or_patch);
2154                 /* no option rom */
2155                 } else {
2156                         if (fw.etrack_id != 0X0000) {
2157                                 ret = snprintf(fw_version, fw_size,
2158                                          "%d.%d, 0x%08x",
2159                                          fw.eep_major, fw.eep_minor,
2160                                          fw.etrack_id);
2161                         } else {
2162                                 ret = snprintf(fw_version, fw_size,
2163                                          "%d.%d.%d",
2164                                          fw.eep_major, fw.eep_minor,
2165                                          fw.eep_build);
2166                         }
2167                 }
2168                 break;
2169         }
2170
2171         ret += 1; /* add the size of '\0' */
2172         if (fw_size < (u32)ret)
2173                 return ret;
2174         else
2175                 return 0;
2176 }
2177
2178 static int
2179 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2180 {
2181         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2182
2183         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2184         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2185         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2186         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2187         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2188                                     dev_info->rx_queue_offload_capa;
2189         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2190         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2191                                     dev_info->tx_queue_offload_capa;
2192
2193         switch (hw->mac.type) {
2194         case e1000_82575:
2195                 dev_info->max_rx_queues = 4;
2196                 dev_info->max_tx_queues = 4;
2197                 dev_info->max_vmdq_pools = 0;
2198                 break;
2199
2200         case e1000_82576:
2201                 dev_info->max_rx_queues = 16;
2202                 dev_info->max_tx_queues = 16;
2203                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2204                 dev_info->vmdq_queue_num = 16;
2205                 break;
2206
2207         case e1000_82580:
2208                 dev_info->max_rx_queues = 8;
2209                 dev_info->max_tx_queues = 8;
2210                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2211                 dev_info->vmdq_queue_num = 8;
2212                 break;
2213
2214         case e1000_i350:
2215                 dev_info->max_rx_queues = 8;
2216                 dev_info->max_tx_queues = 8;
2217                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2218                 dev_info->vmdq_queue_num = 8;
2219                 break;
2220
2221         case e1000_i354:
2222                 dev_info->max_rx_queues = 8;
2223                 dev_info->max_tx_queues = 8;
2224                 break;
2225
2226         case e1000_i210:
2227                 dev_info->max_rx_queues = 4;
2228                 dev_info->max_tx_queues = 4;
2229                 dev_info->max_vmdq_pools = 0;
2230                 break;
2231
2232         case e1000_i211:
2233                 dev_info->max_rx_queues = 2;
2234                 dev_info->max_tx_queues = 2;
2235                 dev_info->max_vmdq_pools = 0;
2236                 break;
2237
2238         default:
2239                 /* Should not happen */
2240                 return -EINVAL;
2241         }
2242         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2243         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2244         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2245
2246         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2247                 .rx_thresh = {
2248                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2249                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2250                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2251                 },
2252                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2253                 .rx_drop_en = 0,
2254                 .offloads = 0,
2255         };
2256
2257         dev_info->default_txconf = (struct rte_eth_txconf) {
2258                 .tx_thresh = {
2259                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2260                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2261                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2262                 },
2263                 .offloads = 0,
2264         };
2265
2266         dev_info->rx_desc_lim = rx_desc_lim;
2267         dev_info->tx_desc_lim = tx_desc_lim;
2268
2269         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2270                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2271                         ETH_LINK_SPEED_1G;
2272
2273         dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2274         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2275
2276         return 0;
2277 }
2278
2279 static const uint32_t *
2280 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2281 {
2282         static const uint32_t ptypes[] = {
2283                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2284                 RTE_PTYPE_L2_ETHER,
2285                 RTE_PTYPE_L3_IPV4,
2286                 RTE_PTYPE_L3_IPV4_EXT,
2287                 RTE_PTYPE_L3_IPV6,
2288                 RTE_PTYPE_L3_IPV6_EXT,
2289                 RTE_PTYPE_L4_TCP,
2290                 RTE_PTYPE_L4_UDP,
2291                 RTE_PTYPE_L4_SCTP,
2292                 RTE_PTYPE_TUNNEL_IP,
2293                 RTE_PTYPE_INNER_L3_IPV6,
2294                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2295                 RTE_PTYPE_INNER_L4_TCP,
2296                 RTE_PTYPE_INNER_L4_UDP,
2297                 RTE_PTYPE_UNKNOWN
2298         };
2299
2300         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2301             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2302                 return ptypes;
2303         return NULL;
2304 }
2305
2306 static int
2307 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2308 {
2309         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2310
2311         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2312         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2313         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2314         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2315                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2316                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2317                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2318                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2319                                 DEV_TX_OFFLOAD_TCP_TSO;
2320         switch (hw->mac.type) {
2321         case e1000_vfadapt:
2322                 dev_info->max_rx_queues = 2;
2323                 dev_info->max_tx_queues = 2;
2324                 break;
2325         case e1000_vfadapt_i350:
2326                 dev_info->max_rx_queues = 1;
2327                 dev_info->max_tx_queues = 1;
2328                 break;
2329         default:
2330                 /* Should not happen */
2331                 return -EINVAL;
2332         }
2333
2334         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2335         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2336                                     dev_info->rx_queue_offload_capa;
2337         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2338         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2339                                     dev_info->tx_queue_offload_capa;
2340
2341         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2342                 .rx_thresh = {
2343                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2344                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2345                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2346                 },
2347                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2348                 .rx_drop_en = 0,
2349                 .offloads = 0,
2350         };
2351
2352         dev_info->default_txconf = (struct rte_eth_txconf) {
2353                 .tx_thresh = {
2354                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2355                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2356                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2357                 },
2358                 .offloads = 0,
2359         };
2360
2361         dev_info->rx_desc_lim = rx_desc_lim;
2362         dev_info->tx_desc_lim = tx_desc_lim;
2363
2364         return 0;
2365 }
2366
2367 /* return 0 means link status changed, -1 means not changed */
2368 static int
2369 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2370 {
2371         struct e1000_hw *hw =
2372                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2373         struct rte_eth_link link;
2374         int link_check, count;
2375
2376         link_check = 0;
2377         hw->mac.get_link_status = 1;
2378
2379         /* possible wait-to-complete in up to 9 seconds */
2380         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2381                 /* Read the real link status */
2382                 switch (hw->phy.media_type) {
2383                 case e1000_media_type_copper:
2384                         /* Do the work to read phy */
2385                         e1000_check_for_link(hw);
2386                         link_check = !hw->mac.get_link_status;
2387                         break;
2388
2389                 case e1000_media_type_fiber:
2390                         e1000_check_for_link(hw);
2391                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2392                                       E1000_STATUS_LU);
2393                         break;
2394
2395                 case e1000_media_type_internal_serdes:
2396                         e1000_check_for_link(hw);
2397                         link_check = hw->mac.serdes_has_link;
2398                         break;
2399
2400                 /* VF device is type_unknown */
2401                 case e1000_media_type_unknown:
2402                         eth_igbvf_link_update(hw);
2403                         link_check = !hw->mac.get_link_status;
2404                         break;
2405
2406                 default:
2407                         break;
2408                 }
2409                 if (link_check || wait_to_complete == 0)
2410                         break;
2411                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2412         }
2413         memset(&link, 0, sizeof(link));
2414
2415         /* Now we check if a transition has happened */
2416         if (link_check) {
2417                 uint16_t duplex, speed;
2418                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2419                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2420                                 ETH_LINK_FULL_DUPLEX :
2421                                 ETH_LINK_HALF_DUPLEX;
2422                 link.link_speed = speed;
2423                 link.link_status = ETH_LINK_UP;
2424                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2425                                 ETH_LINK_SPEED_FIXED);
2426         } else if (!link_check) {
2427                 link.link_speed = 0;
2428                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2429                 link.link_status = ETH_LINK_DOWN;
2430                 link.link_autoneg = ETH_LINK_FIXED;
2431         }
2432
2433         return rte_eth_linkstatus_set(dev, &link);
2434 }
2435
2436 /*
2437  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2438  * For ASF and Pass Through versions of f/w this means
2439  * that the driver is loaded.
2440  */
2441 static void
2442 igb_hw_control_acquire(struct e1000_hw *hw)
2443 {
2444         uint32_t ctrl_ext;
2445
2446         /* Let firmware know the driver has taken over */
2447         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2448         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2449 }
2450
2451 /*
2452  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2453  * For ASF and Pass Through versions of f/w this means that the
2454  * driver is no longer loaded.
2455  */
2456 static void
2457 igb_hw_control_release(struct e1000_hw *hw)
2458 {
2459         uint32_t ctrl_ext;
2460
2461         /* Let firmware taken over control of h/w */
2462         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2463         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2464                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2465 }
2466
2467 /*
2468  * Bit of a misnomer, what this really means is
2469  * to enable OS management of the system... aka
2470  * to disable special hardware management features.
2471  */
2472 static void
2473 igb_init_manageability(struct e1000_hw *hw)
2474 {
2475         if (e1000_enable_mng_pass_thru(hw)) {
2476                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2477                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2478
2479                 /* disable hardware interception of ARP */
2480                 manc &= ~(E1000_MANC_ARP_EN);
2481
2482                 /* enable receiving management packets to the host */
2483                 manc |= E1000_MANC_EN_MNG2HOST;
2484                 manc2h |= 1 << 5;  /* Mng Port 623 */
2485                 manc2h |= 1 << 6;  /* Mng Port 664 */
2486                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2487                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2488         }
2489 }
2490
2491 static void
2492 igb_release_manageability(struct e1000_hw *hw)
2493 {
2494         if (e1000_enable_mng_pass_thru(hw)) {
2495                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2496
2497                 manc |= E1000_MANC_ARP_EN;
2498                 manc &= ~E1000_MANC_EN_MNG2HOST;
2499
2500                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2501         }
2502 }
2503
2504 static int
2505 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2506 {
2507         struct e1000_hw *hw =
2508                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2509         uint32_t rctl;
2510
2511         rctl = E1000_READ_REG(hw, E1000_RCTL);
2512         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2513         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2514
2515         return 0;
2516 }
2517
2518 static int
2519 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2520 {
2521         struct e1000_hw *hw =
2522                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523         uint32_t rctl;
2524
2525         rctl = E1000_READ_REG(hw, E1000_RCTL);
2526         rctl &= (~E1000_RCTL_UPE);
2527         if (dev->data->all_multicast == 1)
2528                 rctl |= E1000_RCTL_MPE;
2529         else
2530                 rctl &= (~E1000_RCTL_MPE);
2531         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2532
2533         return 0;
2534 }
2535
2536 static int
2537 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2538 {
2539         struct e1000_hw *hw =
2540                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541         uint32_t rctl;
2542
2543         rctl = E1000_READ_REG(hw, E1000_RCTL);
2544         rctl |= E1000_RCTL_MPE;
2545         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2546
2547         return 0;
2548 }
2549
2550 static int
2551 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2552 {
2553         struct e1000_hw *hw =
2554                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2555         uint32_t rctl;
2556
2557         if (dev->data->promiscuous == 1)
2558                 return 0; /* must remain in all_multicast mode */
2559         rctl = E1000_READ_REG(hw, E1000_RCTL);
2560         rctl &= (~E1000_RCTL_MPE);
2561         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2562
2563         return 0;
2564 }
2565
2566 static int
2567 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2568 {
2569         struct e1000_hw *hw =
2570                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2571         struct e1000_vfta * shadow_vfta =
2572                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2573         uint32_t vfta;
2574         uint32_t vid_idx;
2575         uint32_t vid_bit;
2576
2577         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2578                               E1000_VFTA_ENTRY_MASK);
2579         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2580         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2581         if (on)
2582                 vfta |= vid_bit;
2583         else
2584                 vfta &= ~vid_bit;
2585         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2586
2587         /* update local VFTA copy */
2588         shadow_vfta->vfta[vid_idx] = vfta;
2589
2590         return 0;
2591 }
2592
2593 static int
2594 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2595                       enum rte_vlan_type vlan_type,
2596                       uint16_t tpid)
2597 {
2598         struct e1000_hw *hw =
2599                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2600         uint32_t reg, qinq;
2601
2602         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2603         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2604
2605         /* only outer TPID of double VLAN can be configured*/
2606         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2607                 reg = E1000_READ_REG(hw, E1000_VET);
2608                 reg = (reg & (~E1000_VET_VET_EXT)) |
2609                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2610                 E1000_WRITE_REG(hw, E1000_VET, reg);
2611
2612                 return 0;
2613         }
2614
2615         /* all other TPID values are read-only*/
2616         PMD_DRV_LOG(ERR, "Not supported");
2617
2618         return -ENOTSUP;
2619 }
2620
2621 static void
2622 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2623 {
2624         struct e1000_hw *hw =
2625                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2626         uint32_t reg;
2627
2628         /* Filter Table Disable */
2629         reg = E1000_READ_REG(hw, E1000_RCTL);
2630         reg &= ~E1000_RCTL_CFIEN;
2631         reg &= ~E1000_RCTL_VFE;
2632         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2633 }
2634
2635 static void
2636 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2637 {
2638         struct e1000_hw *hw =
2639                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640         struct e1000_vfta * shadow_vfta =
2641                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2642         uint32_t reg;
2643         int i;
2644
2645         /* Filter Table Enable, CFI not used for packet acceptance */
2646         reg = E1000_READ_REG(hw, E1000_RCTL);
2647         reg &= ~E1000_RCTL_CFIEN;
2648         reg |= E1000_RCTL_VFE;
2649         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2650
2651         /* restore VFTA table */
2652         for (i = 0; i < IGB_VFTA_SIZE; i++)
2653                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2654 }
2655
2656 static void
2657 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2658 {
2659         struct e1000_hw *hw =
2660                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2661         uint32_t reg;
2662
2663         /* VLAN Mode Disable */
2664         reg = E1000_READ_REG(hw, E1000_CTRL);
2665         reg &= ~E1000_CTRL_VME;
2666         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2667 }
2668
2669 static void
2670 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2671 {
2672         struct e1000_hw *hw =
2673                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2674         uint32_t reg;
2675
2676         /* VLAN Mode Enable */
2677         reg = E1000_READ_REG(hw, E1000_CTRL);
2678         reg |= E1000_CTRL_VME;
2679         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2680 }
2681
2682 static void
2683 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2684 {
2685         struct e1000_hw *hw =
2686                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2687         uint32_t reg;
2688
2689         /* CTRL_EXT: Extended VLAN */
2690         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2691         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2692         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2693
2694         /* Update maximum packet length */
2695         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2696                 E1000_WRITE_REG(hw, E1000_RLPML,
2697                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2698                                                 VLAN_TAG_SIZE);
2699 }
2700
2701 static void
2702 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2703 {
2704         struct e1000_hw *hw =
2705                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2706         uint32_t reg;
2707
2708         /* CTRL_EXT: Extended VLAN */
2709         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2710         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2711         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2712
2713         /* Update maximum packet length */
2714         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2715                 E1000_WRITE_REG(hw, E1000_RLPML,
2716                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2717                                                 2 * VLAN_TAG_SIZE);
2718 }
2719
2720 static int
2721 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2722 {
2723         struct rte_eth_rxmode *rxmode;
2724
2725         rxmode = &dev->data->dev_conf.rxmode;
2726         if(mask & ETH_VLAN_STRIP_MASK){
2727                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2728                         igb_vlan_hw_strip_enable(dev);
2729                 else
2730                         igb_vlan_hw_strip_disable(dev);
2731         }
2732
2733         if(mask & ETH_VLAN_FILTER_MASK){
2734                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2735                         igb_vlan_hw_filter_enable(dev);
2736                 else
2737                         igb_vlan_hw_filter_disable(dev);
2738         }
2739
2740         if(mask & ETH_VLAN_EXTEND_MASK){
2741                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2742                         igb_vlan_hw_extend_enable(dev);
2743                 else
2744                         igb_vlan_hw_extend_disable(dev);
2745         }
2746
2747         return 0;
2748 }
2749
2750
2751 /**
2752  * It enables the interrupt mask and then enable the interrupt.
2753  *
2754  * @param dev
2755  *  Pointer to struct rte_eth_dev.
2756  * @param on
2757  *  Enable or Disable
2758  *
2759  * @return
2760  *  - On success, zero.
2761  *  - On failure, a negative value.
2762  */
2763 static int
2764 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2765 {
2766         struct e1000_interrupt *intr =
2767                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2768
2769         if (on)
2770                 intr->mask |= E1000_ICR_LSC;
2771         else
2772                 intr->mask &= ~E1000_ICR_LSC;
2773
2774         return 0;
2775 }
2776
2777 /* It clears the interrupt causes and enables the interrupt.
2778  * It will be called once only during nic initialized.
2779  *
2780  * @param dev
2781  *  Pointer to struct rte_eth_dev.
2782  *
2783  * @return
2784  *  - On success, zero.
2785  *  - On failure, a negative value.
2786  */
2787 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2788 {
2789         uint32_t mask, regval;
2790         int ret;
2791         struct e1000_hw *hw =
2792                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2793         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2794         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2795         int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2796         struct rte_eth_dev_info dev_info;
2797
2798         memset(&dev_info, 0, sizeof(dev_info));
2799         ret = eth_igb_infos_get(dev, &dev_info);
2800         if (ret != 0)
2801                 return ret;
2802
2803         mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2804         regval = E1000_READ_REG(hw, E1000_EIMS);
2805         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2806
2807         return 0;
2808 }
2809
2810 /*
2811  * It reads ICR and gets interrupt causes, check it and set a bit flag
2812  * to update link status.
2813  *
2814  * @param dev
2815  *  Pointer to struct rte_eth_dev.
2816  *
2817  * @return
2818  *  - On success, zero.
2819  *  - On failure, a negative value.
2820  */
2821 static int
2822 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2823 {
2824         uint32_t icr;
2825         struct e1000_hw *hw =
2826                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2827         struct e1000_interrupt *intr =
2828                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2829
2830         igb_intr_disable(dev);
2831
2832         /* read-on-clear nic registers here */
2833         icr = E1000_READ_REG(hw, E1000_ICR);
2834
2835         intr->flags = 0;
2836         if (icr & E1000_ICR_LSC) {
2837                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2838         }
2839
2840         if (icr & E1000_ICR_VMMB)
2841                 intr->flags |= E1000_FLAG_MAILBOX;
2842
2843         return 0;
2844 }
2845
2846 /*
2847  * It executes link_update after knowing an interrupt is prsent.
2848  *
2849  * @param dev
2850  *  Pointer to struct rte_eth_dev.
2851  *
2852  * @return
2853  *  - On success, zero.
2854  *  - On failure, a negative value.
2855  */
2856 static int
2857 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2858                          struct rte_intr_handle *intr_handle)
2859 {
2860         struct e1000_hw *hw =
2861                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2862         struct e1000_interrupt *intr =
2863                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2864         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2865         struct rte_eth_link link;
2866         int ret;
2867
2868         if (intr->flags & E1000_FLAG_MAILBOX) {
2869                 igb_pf_mbx_process(dev);
2870                 intr->flags &= ~E1000_FLAG_MAILBOX;
2871         }
2872
2873         igb_intr_enable(dev);
2874         rte_intr_ack(intr_handle);
2875
2876         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2877                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2878
2879                 /* set get_link_status to check register later */
2880                 hw->mac.get_link_status = 1;
2881                 ret = eth_igb_link_update(dev, 0);
2882
2883                 /* check if link has changed */
2884                 if (ret < 0)
2885                         return 0;
2886
2887                 rte_eth_linkstatus_get(dev, &link);
2888                 if (link.link_status) {
2889                         PMD_INIT_LOG(INFO,
2890                                      " Port %d: Link Up - speed %u Mbps - %s",
2891                                      dev->data->port_id,
2892                                      (unsigned)link.link_speed,
2893                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2894                                      "full-duplex" : "half-duplex");
2895                 } else {
2896                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2897                                      dev->data->port_id);
2898                 }
2899
2900                 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2901                              pci_dev->addr.domain,
2902                              pci_dev->addr.bus,
2903                              pci_dev->addr.devid,
2904                              pci_dev->addr.function);
2905                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2906         }
2907
2908         return 0;
2909 }
2910
2911 /**
2912  * Interrupt handler which shall be registered at first.
2913  *
2914  * @param handle
2915  *  Pointer to interrupt handle.
2916  * @param param
2917  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2918  *
2919  * @return
2920  *  void
2921  */
2922 static void
2923 eth_igb_interrupt_handler(void *param)
2924 {
2925         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2926
2927         eth_igb_interrupt_get_status(dev);
2928         eth_igb_interrupt_action(dev, dev->intr_handle);
2929 }
2930
2931 static int
2932 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2933 {
2934         uint32_t eicr;
2935         struct e1000_hw *hw =
2936                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2937         struct e1000_interrupt *intr =
2938                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2939
2940         igbvf_intr_disable(hw);
2941
2942         /* read-on-clear nic registers here */
2943         eicr = E1000_READ_REG(hw, E1000_EICR);
2944         intr->flags = 0;
2945
2946         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2947                 intr->flags |= E1000_FLAG_MAILBOX;
2948
2949         return 0;
2950 }
2951
2952 void igbvf_mbx_process(struct rte_eth_dev *dev)
2953 {
2954         struct e1000_hw *hw =
2955                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2956         struct e1000_mbx_info *mbx = &hw->mbx;
2957         u32 in_msg = 0;
2958
2959         /* peek the message first */
2960         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2961
2962         /* PF reset VF event */
2963         if (in_msg == E1000_PF_CONTROL_MSG) {
2964                 /* dummy mbx read to ack pf */
2965                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2966                         return;
2967                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2968                                              NULL);
2969         }
2970 }
2971
2972 static int
2973 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2974 {
2975         struct e1000_interrupt *intr =
2976                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2977
2978         if (intr->flags & E1000_FLAG_MAILBOX) {
2979                 igbvf_mbx_process(dev);
2980                 intr->flags &= ~E1000_FLAG_MAILBOX;
2981         }
2982
2983         igbvf_intr_enable(dev);
2984         rte_intr_ack(intr_handle);
2985
2986         return 0;
2987 }
2988
2989 static void
2990 eth_igbvf_interrupt_handler(void *param)
2991 {
2992         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2993
2994         eth_igbvf_interrupt_get_status(dev);
2995         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2996 }
2997
2998 static int
2999 eth_igb_led_on(struct rte_eth_dev *dev)
3000 {
3001         struct e1000_hw *hw;
3002
3003         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3004         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3005 }
3006
3007 static int
3008 eth_igb_led_off(struct rte_eth_dev *dev)
3009 {
3010         struct e1000_hw *hw;
3011
3012         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3013         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3014 }
3015
3016 static int
3017 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3018 {
3019         struct e1000_hw *hw;
3020         uint32_t ctrl;
3021         int tx_pause;
3022         int rx_pause;
3023
3024         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3025         fc_conf->pause_time = hw->fc.pause_time;
3026         fc_conf->high_water = hw->fc.high_water;
3027         fc_conf->low_water = hw->fc.low_water;
3028         fc_conf->send_xon = hw->fc.send_xon;
3029         fc_conf->autoneg = hw->mac.autoneg;
3030
3031         /*
3032          * Return rx_pause and tx_pause status according to actual setting of
3033          * the TFCE and RFCE bits in the CTRL register.
3034          */
3035         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3036         if (ctrl & E1000_CTRL_TFCE)
3037                 tx_pause = 1;
3038         else
3039                 tx_pause = 0;
3040
3041         if (ctrl & E1000_CTRL_RFCE)
3042                 rx_pause = 1;
3043         else
3044                 rx_pause = 0;
3045
3046         if (rx_pause && tx_pause)
3047                 fc_conf->mode = RTE_FC_FULL;
3048         else if (rx_pause)
3049                 fc_conf->mode = RTE_FC_RX_PAUSE;
3050         else if (tx_pause)
3051                 fc_conf->mode = RTE_FC_TX_PAUSE;
3052         else
3053                 fc_conf->mode = RTE_FC_NONE;
3054
3055         return 0;
3056 }
3057
3058 static int
3059 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3060 {
3061         struct e1000_hw *hw;
3062         int err;
3063         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3064                 e1000_fc_none,
3065                 e1000_fc_rx_pause,
3066                 e1000_fc_tx_pause,
3067                 e1000_fc_full
3068         };
3069         uint32_t rx_buf_size;
3070         uint32_t max_high_water;
3071         uint32_t rctl;
3072
3073         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3074         if (fc_conf->autoneg != hw->mac.autoneg)
3075                 return -ENOTSUP;
3076         rx_buf_size = igb_get_rx_buffer_size(hw);
3077         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3078
3079         /* At least reserve one Ethernet frame for watermark */
3080         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3081         if ((fc_conf->high_water > max_high_water) ||
3082             (fc_conf->high_water < fc_conf->low_water)) {
3083                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3084                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3085                 return -EINVAL;
3086         }
3087
3088         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3089         hw->fc.pause_time     = fc_conf->pause_time;
3090         hw->fc.high_water     = fc_conf->high_water;
3091         hw->fc.low_water      = fc_conf->low_water;
3092         hw->fc.send_xon       = fc_conf->send_xon;
3093
3094         err = e1000_setup_link_generic(hw);
3095         if (err == E1000_SUCCESS) {
3096
3097                 /* check if we want to forward MAC frames - driver doesn't have native
3098                  * capability to do that, so we'll write the registers ourselves */
3099
3100                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3101
3102                 /* set or clear MFLCN.PMCF bit depending on configuration */
3103                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3104                         rctl |= E1000_RCTL_PMCF;
3105                 else
3106                         rctl &= ~E1000_RCTL_PMCF;
3107
3108                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3109                 E1000_WRITE_FLUSH(hw);
3110
3111                 return 0;
3112         }
3113
3114         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3115         return -EIO;
3116 }
3117
3118 #define E1000_RAH_POOLSEL_SHIFT      (18)
3119 static int
3120 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3121                 uint32_t index, uint32_t pool)
3122 {
3123         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3124         uint32_t rah;
3125
3126         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3127         rah = E1000_READ_REG(hw, E1000_RAH(index));
3128         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3129         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3130         return 0;
3131 }
3132
3133 static void
3134 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3135 {
3136         uint8_t addr[RTE_ETHER_ADDR_LEN];
3137         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3138
3139         memset(addr, 0, sizeof(addr));
3140
3141         e1000_rar_set(hw, addr, index);
3142 }
3143
3144 static int
3145 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3146                                 struct rte_ether_addr *addr)
3147 {
3148         eth_igb_rar_clear(dev, 0);
3149         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3150
3151         return 0;
3152 }
3153 /*
3154  * Virtual Function operations
3155  */
3156 static void
3157 igbvf_intr_disable(struct e1000_hw *hw)
3158 {
3159         PMD_INIT_FUNC_TRACE();
3160
3161         /* Clear interrupt mask to stop from interrupts being generated */
3162         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3163
3164         E1000_WRITE_FLUSH(hw);
3165 }
3166
3167 static void
3168 igbvf_stop_adapter(struct rte_eth_dev *dev)
3169 {
3170         u32 reg_val;
3171         u16 i;
3172         struct rte_eth_dev_info dev_info;
3173         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3174         int ret;
3175
3176         memset(&dev_info, 0, sizeof(dev_info));
3177         ret = eth_igbvf_infos_get(dev, &dev_info);
3178         if (ret != 0)
3179                 return;
3180
3181         /* Clear interrupt mask to stop from interrupts being generated */
3182         igbvf_intr_disable(hw);
3183
3184         /* Clear any pending interrupts, flush previous writes */
3185         E1000_READ_REG(hw, E1000_EICR);
3186
3187         /* Disable the transmit unit.  Each queue must be disabled. */
3188         for (i = 0; i < dev_info.max_tx_queues; i++)
3189                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3190
3191         /* Disable the receive unit by stopping each queue */
3192         for (i = 0; i < dev_info.max_rx_queues; i++) {
3193                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3194                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3195                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3196                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3197                         ;
3198         }
3199
3200         /* flush all queues disables */
3201         E1000_WRITE_FLUSH(hw);
3202         msec_delay(2);
3203 }
3204
3205 static int eth_igbvf_link_update(struct e1000_hw *hw)
3206 {
3207         struct e1000_mbx_info *mbx = &hw->mbx;
3208         struct e1000_mac_info *mac = &hw->mac;
3209         int ret_val = E1000_SUCCESS;
3210
3211         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3212
3213         /*
3214          * We only want to run this if there has been a rst asserted.
3215          * in this case that could mean a link change, device reset,
3216          * or a virtual function reset
3217          */
3218
3219         /* If we were hit with a reset or timeout drop the link */
3220         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3221                 mac->get_link_status = TRUE;
3222
3223         if (!mac->get_link_status)
3224                 goto out;
3225
3226         /* if link status is down no point in checking to see if pf is up */
3227         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3228                 goto out;
3229
3230         /* if we passed all the tests above then the link is up and we no
3231          * longer need to check for link */
3232         mac->get_link_status = FALSE;
3233
3234 out:
3235         return ret_val;
3236 }
3237
3238
3239 static int
3240 igbvf_dev_configure(struct rte_eth_dev *dev)
3241 {
3242         struct rte_eth_conf* conf = &dev->data->dev_conf;
3243
3244         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3245                      dev->data->port_id);
3246
3247         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3248                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3249
3250         /*
3251          * VF has no ability to enable/disable HW CRC
3252          * Keep the persistent behavior the same as Host PF
3253          */
3254 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3255         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3256                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3257                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3258         }
3259 #else
3260         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3261                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3262                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3263         }
3264 #endif
3265
3266         return 0;
3267 }
3268
3269 static int
3270 igbvf_dev_start(struct rte_eth_dev *dev)
3271 {
3272         struct e1000_hw *hw =
3273                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3274         struct e1000_adapter *adapter =
3275                 E1000_DEV_PRIVATE(dev->data->dev_private);
3276         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3277         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3278         int ret;
3279         uint32_t intr_vector = 0;
3280
3281         PMD_INIT_FUNC_TRACE();
3282
3283         hw->mac.ops.reset_hw(hw);
3284         adapter->stopped = 0;
3285
3286         /* Set all vfta */
3287         igbvf_set_vfta_all(dev,1);
3288
3289         eth_igbvf_tx_init(dev);
3290
3291         /* This can fail when allocating mbufs for descriptor rings */
3292         ret = eth_igbvf_rx_init(dev);
3293         if (ret) {
3294                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3295                 igb_dev_clear_queues(dev);
3296                 return ret;
3297         }
3298
3299         /* check and configure queue intr-vector mapping */
3300         if (rte_intr_cap_multiple(intr_handle) &&
3301             dev->data->dev_conf.intr_conf.rxq) {
3302                 intr_vector = dev->data->nb_rx_queues;
3303                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3304                 if (ret)
3305                         return ret;
3306         }
3307
3308         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3309                 intr_handle->intr_vec =
3310                         rte_zmalloc("intr_vec",
3311                                     dev->data->nb_rx_queues * sizeof(int), 0);
3312                 if (!intr_handle->intr_vec) {
3313                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3314                                      " intr_vec", dev->data->nb_rx_queues);
3315                         return -ENOMEM;
3316                 }
3317         }
3318
3319         eth_igbvf_configure_msix_intr(dev);
3320
3321         /* enable uio/vfio intr/eventfd mapping */
3322         rte_intr_enable(intr_handle);
3323
3324         /* resume enabled intr since hw reset */
3325         igbvf_intr_enable(dev);
3326
3327         return 0;
3328 }
3329
3330 static int
3331 igbvf_dev_stop(struct rte_eth_dev *dev)
3332 {
3333         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3334         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3335         struct e1000_adapter *adapter =
3336                 E1000_DEV_PRIVATE(dev->data->dev_private);
3337
3338         if (adapter->stopped)
3339                 return 0;
3340
3341         PMD_INIT_FUNC_TRACE();
3342
3343         igbvf_stop_adapter(dev);
3344
3345         /*
3346           * Clear what we set, but we still keep shadow_vfta to
3347           * restore after device starts
3348           */
3349         igbvf_set_vfta_all(dev,0);
3350
3351         igb_dev_clear_queues(dev);
3352
3353         /* disable intr eventfd mapping */
3354         rte_intr_disable(intr_handle);
3355
3356         /* Clean datapath event and queue/vec mapping */
3357         rte_intr_efd_disable(intr_handle);
3358         if (intr_handle->intr_vec) {
3359                 rte_free(intr_handle->intr_vec);
3360                 intr_handle->intr_vec = NULL;
3361         }
3362
3363         adapter->stopped = true;
3364         dev->data->dev_started = 0;
3365
3366         return 0;
3367 }
3368
3369 static int
3370 igbvf_dev_close(struct rte_eth_dev *dev)
3371 {
3372         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3373         struct rte_ether_addr addr;
3374         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3375         int ret;
3376
3377         PMD_INIT_FUNC_TRACE();
3378
3379         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3380                 return 0;
3381
3382         e1000_reset_hw(hw);
3383
3384         ret = igbvf_dev_stop(dev);
3385         if (ret != 0)
3386                 return ret;
3387
3388         igb_dev_free_queues(dev);
3389
3390         /**
3391          * reprogram the RAR with a zero mac address,
3392          * to ensure that the VF traffic goes to the PF
3393          * after stop, close and detach of the VF.
3394          **/
3395
3396         memset(&addr, 0, sizeof(addr));
3397         igbvf_default_mac_addr_set(dev, &addr);
3398
3399         rte_intr_callback_unregister(&pci_dev->intr_handle,
3400                                      eth_igbvf_interrupt_handler,
3401                                      (void *)dev);
3402
3403         return 0;
3404 }
3405
3406 static int
3407 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3408 {
3409         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3410
3411         /* Set both unicast and multicast promisc */
3412         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3413
3414         return 0;
3415 }
3416
3417 static int
3418 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3419 {
3420         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3421
3422         /* If in allmulticast mode leave multicast promisc */
3423         if (dev->data->all_multicast == 1)
3424                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3425         else
3426                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3427
3428         return 0;
3429 }
3430
3431 static int
3432 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3433 {
3434         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3435
3436         /* In promiscuous mode multicast promisc already set */
3437         if (dev->data->promiscuous == 0)
3438                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3439
3440         return 0;
3441 }
3442
3443 static int
3444 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3445 {
3446         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3447
3448         /* In promiscuous mode leave multicast promisc enabled */
3449         if (dev->data->promiscuous == 0)
3450                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3451
3452         return 0;
3453 }
3454
3455 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3456 {
3457         struct e1000_mbx_info *mbx = &hw->mbx;
3458         uint32_t msgbuf[2];
3459         s32 err;
3460
3461         /* After set vlan, vlan strip will also be enabled in igb driver*/
3462         msgbuf[0] = E1000_VF_SET_VLAN;
3463         msgbuf[1] = vid;
3464         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3465         if (on)
3466                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3467
3468         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3469         if (err)
3470                 goto mbx_err;
3471
3472         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3473         if (err)
3474                 goto mbx_err;
3475
3476         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3477         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3478                 err = -EINVAL;
3479
3480 mbx_err:
3481         return err;
3482 }
3483
3484 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3485 {
3486         struct e1000_hw *hw =
3487                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3488         struct e1000_vfta * shadow_vfta =
3489                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3490         int i = 0, j = 0, vfta = 0, mask = 1;
3491
3492         for (i = 0; i < IGB_VFTA_SIZE; i++){
3493                 vfta = shadow_vfta->vfta[i];
3494                 if(vfta){
3495                         mask = 1;
3496                         for (j = 0; j < 32; j++){
3497                                 if(vfta & mask)
3498                                         igbvf_set_vfta(hw,
3499                                                 (uint16_t)((i<<5)+j), on);
3500                                 mask<<=1;
3501                         }
3502                 }
3503         }
3504
3505 }
3506
3507 static int
3508 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3509 {
3510         struct e1000_hw *hw =
3511                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3512         struct e1000_vfta * shadow_vfta =
3513                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3514         uint32_t vid_idx = 0;
3515         uint32_t vid_bit = 0;
3516         int ret = 0;
3517
3518         PMD_INIT_FUNC_TRACE();
3519
3520         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3521         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3522         if(ret){
3523                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3524                 return ret;
3525         }
3526         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3527         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3528
3529         /*Save what we set and retore it after device reset*/
3530         if (on)
3531                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3532         else
3533                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3534
3535         return 0;
3536 }
3537
3538 static int
3539 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3540 {
3541         struct e1000_hw *hw =
3542                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3543
3544         /* index is not used by rar_set() */
3545         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3546         return 0;
3547 }
3548
3549
3550 static int
3551 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3552                         struct rte_eth_rss_reta_entry64 *reta_conf,
3553                         uint16_t reta_size)
3554 {
3555         uint8_t i, j, mask;
3556         uint32_t reta, r;
3557         uint16_t idx, shift;
3558         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3559
3560         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3561                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3562                         "(%d) doesn't match the number hardware can supported "
3563                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3564                 return -EINVAL;
3565         }
3566
3567         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3568                 idx = i / RTE_RETA_GROUP_SIZE;
3569                 shift = i % RTE_RETA_GROUP_SIZE;
3570                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3571                                                 IGB_4_BIT_MASK);
3572                 if (!mask)
3573                         continue;
3574                 if (mask == IGB_4_BIT_MASK)
3575                         r = 0;
3576                 else
3577                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3578                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3579                         if (mask & (0x1 << j))
3580                                 reta |= reta_conf[idx].reta[shift + j] <<
3581                                                         (CHAR_BIT * j);
3582                         else
3583                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3584                 }
3585                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3586         }
3587
3588         return 0;
3589 }
3590
3591 static int
3592 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3593                        struct rte_eth_rss_reta_entry64 *reta_conf,
3594                        uint16_t reta_size)
3595 {
3596         uint8_t i, j, mask;
3597         uint32_t reta;
3598         uint16_t idx, shift;
3599         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3600
3601         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3602                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3603                         "(%d) doesn't match the number hardware can supported "
3604                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3605                 return -EINVAL;
3606         }
3607
3608         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3609                 idx = i / RTE_RETA_GROUP_SIZE;
3610                 shift = i % RTE_RETA_GROUP_SIZE;
3611                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3612                                                 IGB_4_BIT_MASK);
3613                 if (!mask)
3614                         continue;
3615                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3616                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3617                         if (mask & (0x1 << j))
3618                                 reta_conf[idx].reta[shift + j] =
3619                                         ((reta >> (CHAR_BIT * j)) &
3620                                                 IGB_8_BIT_MASK);
3621                 }
3622         }
3623
3624         return 0;
3625 }
3626
3627 int
3628 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3629                         struct rte_eth_syn_filter *filter,
3630                         bool add)
3631 {
3632         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3633         struct e1000_filter_info *filter_info =
3634                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3635         uint32_t synqf, rfctl;
3636
3637         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3638                 return -EINVAL;
3639
3640         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3641
3642         if (add) {
3643                 if (synqf & E1000_SYN_FILTER_ENABLE)
3644                         return -EINVAL;
3645
3646                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3647                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3648
3649                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3650                 if (filter->hig_pri)
3651                         rfctl |= E1000_RFCTL_SYNQFP;
3652                 else
3653                         rfctl &= ~E1000_RFCTL_SYNQFP;
3654
3655                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3656         } else {
3657                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3658                         return -ENOENT;
3659                 synqf = 0;
3660         }
3661
3662         filter_info->syn_info = synqf;
3663         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3664         E1000_WRITE_FLUSH(hw);
3665         return 0;
3666 }
3667
3668 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3669 static inline int
3670 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3671                         struct e1000_2tuple_filter_info *filter_info)
3672 {
3673         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3674                 return -EINVAL;
3675         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3676                 return -EINVAL;  /* filter index is out of range. */
3677         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3678                 return -EINVAL;  /* flags is invalid. */
3679
3680         switch (filter->dst_port_mask) {
3681         case UINT16_MAX:
3682                 filter_info->dst_port_mask = 0;
3683                 filter_info->dst_port = filter->dst_port;
3684                 break;
3685         case 0:
3686                 filter_info->dst_port_mask = 1;
3687                 break;
3688         default:
3689                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3690                 return -EINVAL;
3691         }
3692
3693         switch (filter->proto_mask) {
3694         case UINT8_MAX:
3695                 filter_info->proto_mask = 0;
3696                 filter_info->proto = filter->proto;
3697                 break;
3698         case 0:
3699                 filter_info->proto_mask = 1;
3700                 break;
3701         default:
3702                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3703                 return -EINVAL;
3704         }
3705
3706         filter_info->priority = (uint8_t)filter->priority;
3707         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3708                 filter_info->tcp_flags = filter->tcp_flags;
3709         else
3710                 filter_info->tcp_flags = 0;
3711
3712         return 0;
3713 }
3714
3715 static inline struct e1000_2tuple_filter *
3716 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3717                         struct e1000_2tuple_filter_info *key)
3718 {
3719         struct e1000_2tuple_filter *it;
3720
3721         TAILQ_FOREACH(it, filter_list, entries) {
3722                 if (memcmp(key, &it->filter_info,
3723                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3724                         return it;
3725                 }
3726         }
3727         return NULL;
3728 }
3729
3730 /* inject a igb 2tuple filter to HW */
3731 static inline void
3732 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3733                            struct e1000_2tuple_filter *filter)
3734 {
3735         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3736         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3737         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3738         int i;
3739
3740         i = filter->index;
3741         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3742         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3743                 imir |= E1000_IMIR_PORT_BP;
3744         else
3745                 imir &= ~E1000_IMIR_PORT_BP;
3746
3747         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3748
3749         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3750         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3751         ttqf |= (uint32_t)(filter->filter_info.proto &
3752                                                 E1000_TTQF_PROTOCOL_MASK);
3753         if (filter->filter_info.proto_mask == 0)
3754                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3755
3756         /* tcp flags bits setting. */
3757         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3758                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3759                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3760                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3761                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3762                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3763                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3764                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3765                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3766                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3767                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3768                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3769                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3770         } else {
3771                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3772         }
3773         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3774         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3775         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3776 }
3777
3778 /*
3779  * igb_add_2tuple_filter - add a 2tuple filter
3780  *
3781  * @param
3782  * dev: Pointer to struct rte_eth_dev.
3783  * ntuple_filter: ponter to the filter that will be added.
3784  *
3785  * @return
3786  *    - On success, zero.
3787  *    - On failure, a negative value.
3788  */
3789 static int
3790 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3791                         struct rte_eth_ntuple_filter *ntuple_filter)
3792 {
3793         struct e1000_filter_info *filter_info =
3794                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3795         struct e1000_2tuple_filter *filter;
3796         int i, ret;
3797
3798         filter = rte_zmalloc("e1000_2tuple_filter",
3799                         sizeof(struct e1000_2tuple_filter), 0);
3800         if (filter == NULL)
3801                 return -ENOMEM;
3802
3803         ret = ntuple_filter_to_2tuple(ntuple_filter,
3804                                       &filter->filter_info);
3805         if (ret < 0) {
3806                 rte_free(filter);
3807                 return ret;
3808         }
3809         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3810                                          &filter->filter_info) != NULL) {
3811                 PMD_DRV_LOG(ERR, "filter exists.");
3812                 rte_free(filter);
3813                 return -EEXIST;
3814         }
3815         filter->queue = ntuple_filter->queue;
3816
3817         /*
3818          * look for an unused 2tuple filter index,
3819          * and insert the filter to list.
3820          */
3821         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3822                 if (!(filter_info->twotuple_mask & (1 << i))) {
3823                         filter_info->twotuple_mask |= 1 << i;
3824                         filter->index = i;
3825                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3826                                           filter,
3827                                           entries);
3828                         break;
3829                 }
3830         }
3831         if (i >= E1000_MAX_TTQF_FILTERS) {
3832                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3833                 rte_free(filter);
3834                 return -ENOSYS;
3835         }
3836
3837         igb_inject_2uple_filter(dev, filter);
3838         return 0;
3839 }
3840
3841 int
3842 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3843                         struct e1000_2tuple_filter *filter)
3844 {
3845         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3846         struct e1000_filter_info *filter_info =
3847                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3848
3849         filter_info->twotuple_mask &= ~(1 << filter->index);
3850         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3851         rte_free(filter);
3852
3853         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3854         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3855         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3856         return 0;
3857 }
3858
3859 /*
3860  * igb_remove_2tuple_filter - remove a 2tuple filter
3861  *
3862  * @param
3863  * dev: Pointer to struct rte_eth_dev.
3864  * ntuple_filter: ponter to the filter that will be removed.
3865  *
3866  * @return
3867  *    - On success, zero.
3868  *    - On failure, a negative value.
3869  */
3870 static int
3871 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3872                         struct rte_eth_ntuple_filter *ntuple_filter)
3873 {
3874         struct e1000_filter_info *filter_info =
3875                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3876         struct e1000_2tuple_filter_info filter_2tuple;
3877         struct e1000_2tuple_filter *filter;
3878         int ret;
3879
3880         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3881         ret = ntuple_filter_to_2tuple(ntuple_filter,
3882                                       &filter_2tuple);
3883         if (ret < 0)
3884                 return ret;
3885
3886         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3887                                          &filter_2tuple);
3888         if (filter == NULL) {
3889                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3890                 return -ENOENT;
3891         }
3892
3893         igb_delete_2tuple_filter(dev, filter);
3894
3895         return 0;
3896 }
3897
3898 /* inject a igb flex filter to HW */
3899 static inline void
3900 igb_inject_flex_filter(struct rte_eth_dev *dev,
3901                            struct e1000_flex_filter *filter)
3902 {
3903         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3904         uint32_t wufc, queueing;
3905         uint32_t reg_off;
3906         uint8_t i, j = 0;
3907
3908         wufc = E1000_READ_REG(hw, E1000_WUFC);
3909         if (filter->index < E1000_MAX_FHFT)
3910                 reg_off = E1000_FHFT(filter->index);
3911         else
3912                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3913
3914         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3915                         (E1000_WUFC_FLX0 << filter->index));
3916         queueing = filter->filter_info.len |
3917                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3918                 (filter->filter_info.priority <<
3919                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3920         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3921                         queueing);
3922
3923         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3924                 E1000_WRITE_REG(hw, reg_off,
3925                                 filter->filter_info.dwords[j]);
3926                 reg_off += sizeof(uint32_t);
3927                 E1000_WRITE_REG(hw, reg_off,
3928                                 filter->filter_info.dwords[++j]);
3929                 reg_off += sizeof(uint32_t);
3930                 E1000_WRITE_REG(hw, reg_off,
3931                         (uint32_t)filter->filter_info.mask[i]);
3932                 reg_off += sizeof(uint32_t) * 2;
3933                 ++j;
3934         }
3935 }
3936
3937 static inline struct e1000_flex_filter *
3938 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3939                         struct e1000_flex_filter_info *key)
3940 {
3941         struct e1000_flex_filter *it;
3942
3943         TAILQ_FOREACH(it, filter_list, entries) {
3944                 if (memcmp(key, &it->filter_info,
3945                         sizeof(struct e1000_flex_filter_info)) == 0)
3946                         return it;
3947         }
3948
3949         return NULL;
3950 }
3951
3952 /* remove a flex byte filter
3953  * @param
3954  * dev: Pointer to struct rte_eth_dev.
3955  * filter: the pointer of the filter will be removed.
3956  */
3957 void
3958 igb_remove_flex_filter(struct rte_eth_dev *dev,
3959                         struct e1000_flex_filter *filter)
3960 {
3961         struct e1000_filter_info *filter_info =
3962                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3963         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3964         uint32_t wufc, i;
3965         uint32_t reg_off;
3966
3967         wufc = E1000_READ_REG(hw, E1000_WUFC);
3968         if (filter->index < E1000_MAX_FHFT)
3969                 reg_off = E1000_FHFT(filter->index);
3970         else
3971                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3972
3973         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3974                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3975
3976         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3977                 (~(E1000_WUFC_FLX0 << filter->index)));
3978
3979         filter_info->flex_mask &= ~(1 << filter->index);
3980         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
3981         rte_free(filter);
3982 }
3983
3984 int
3985 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3986                         struct igb_flex_filter *filter,
3987                         bool add)
3988 {
3989         struct e1000_filter_info *filter_info =
3990                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3991         struct e1000_flex_filter *flex_filter, *it;
3992         uint32_t mask;
3993         uint8_t shift, i;
3994
3995         flex_filter = rte_zmalloc("e1000_flex_filter",
3996                         sizeof(struct e1000_flex_filter), 0);
3997         if (flex_filter == NULL)
3998                 return -ENOMEM;
3999
4000         flex_filter->filter_info.len = filter->len;
4001         flex_filter->filter_info.priority = filter->priority;
4002         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4003         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4004                 mask = 0;
4005                 /* reverse bits in flex filter's mask*/
4006                 for (shift = 0; shift < CHAR_BIT; shift++) {
4007                         if (filter->mask[i] & (0x01 << shift))
4008                                 mask |= (0x80 >> shift);
4009                 }
4010                 flex_filter->filter_info.mask[i] = mask;
4011         }
4012
4013         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4014                                 &flex_filter->filter_info);
4015         if (it == NULL && !add) {
4016                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4017                 rte_free(flex_filter);
4018                 return -ENOENT;
4019         }
4020         if (it != NULL && add) {
4021                 PMD_DRV_LOG(ERR, "filter exists.");
4022                 rte_free(flex_filter);
4023                 return -EEXIST;
4024         }
4025
4026         if (add) {
4027                 flex_filter->queue = filter->queue;
4028                 /*
4029                  * look for an unused flex filter index
4030                  * and insert the filter into the list.
4031                  */
4032                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4033                         if (!(filter_info->flex_mask & (1 << i))) {
4034                                 filter_info->flex_mask |= 1 << i;
4035                                 flex_filter->index = i;
4036                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4037                                         flex_filter,
4038                                         entries);
4039                                 break;
4040                         }
4041                 }
4042                 if (i >= E1000_MAX_FLEX_FILTERS) {
4043                         PMD_DRV_LOG(ERR, "flex filters are full.");
4044                         rte_free(flex_filter);
4045                         return -ENOSYS;
4046                 }
4047
4048                 igb_inject_flex_filter(dev, flex_filter);
4049
4050         } else {
4051                 igb_remove_flex_filter(dev, it);
4052                 rte_free(flex_filter);
4053         }
4054
4055         return 0;
4056 }
4057
4058 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4059 static inline int
4060 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4061                         struct e1000_5tuple_filter_info *filter_info)
4062 {
4063         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4064                 return -EINVAL;
4065         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4066                 return -EINVAL;  /* filter index is out of range. */
4067         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4068                 return -EINVAL;  /* flags is invalid. */
4069
4070         switch (filter->dst_ip_mask) {
4071         case UINT32_MAX:
4072                 filter_info->dst_ip_mask = 0;
4073                 filter_info->dst_ip = filter->dst_ip;
4074                 break;
4075         case 0:
4076                 filter_info->dst_ip_mask = 1;
4077                 break;
4078         default:
4079                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4080                 return -EINVAL;
4081         }
4082
4083         switch (filter->src_ip_mask) {
4084         case UINT32_MAX:
4085                 filter_info->src_ip_mask = 0;
4086                 filter_info->src_ip = filter->src_ip;
4087                 break;
4088         case 0:
4089                 filter_info->src_ip_mask = 1;
4090                 break;
4091         default:
4092                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4093                 return -EINVAL;
4094         }
4095
4096         switch (filter->dst_port_mask) {
4097         case UINT16_MAX:
4098                 filter_info->dst_port_mask = 0;
4099                 filter_info->dst_port = filter->dst_port;
4100                 break;
4101         case 0:
4102                 filter_info->dst_port_mask = 1;
4103                 break;
4104         default:
4105                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4106                 return -EINVAL;
4107         }
4108
4109         switch (filter->src_port_mask) {
4110         case UINT16_MAX:
4111                 filter_info->src_port_mask = 0;
4112                 filter_info->src_port = filter->src_port;
4113                 break;
4114         case 0:
4115                 filter_info->src_port_mask = 1;
4116                 break;
4117         default:
4118                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4119                 return -EINVAL;
4120         }
4121
4122         switch (filter->proto_mask) {
4123         case UINT8_MAX:
4124                 filter_info->proto_mask = 0;
4125                 filter_info->proto = filter->proto;
4126                 break;
4127         case 0:
4128                 filter_info->proto_mask = 1;
4129                 break;
4130         default:
4131                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4132                 return -EINVAL;
4133         }
4134
4135         filter_info->priority = (uint8_t)filter->priority;
4136         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4137                 filter_info->tcp_flags = filter->tcp_flags;
4138         else
4139                 filter_info->tcp_flags = 0;
4140
4141         return 0;
4142 }
4143
4144 static inline struct e1000_5tuple_filter *
4145 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4146                         struct e1000_5tuple_filter_info *key)
4147 {
4148         struct e1000_5tuple_filter *it;
4149
4150         TAILQ_FOREACH(it, filter_list, entries) {
4151                 if (memcmp(key, &it->filter_info,
4152                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4153                         return it;
4154                 }
4155         }
4156         return NULL;
4157 }
4158
4159 /* inject a igb 5-tuple filter to HW */
4160 static inline void
4161 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4162                            struct e1000_5tuple_filter *filter)
4163 {
4164         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4165         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4166         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4167         uint8_t i;
4168
4169         i = filter->index;
4170         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4171         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4172                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4173         if (filter->filter_info.dst_ip_mask == 0)
4174                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4175         if (filter->filter_info.src_port_mask == 0)
4176                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4177         if (filter->filter_info.proto_mask == 0)
4178                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4179         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4180                 E1000_FTQF_QUEUE_MASK;
4181         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4182         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4183         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4184         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4185
4186         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4187         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4188
4189         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4190         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4191                 imir |= E1000_IMIR_PORT_BP;
4192         else
4193                 imir &= ~E1000_IMIR_PORT_BP;
4194         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4195
4196         /* tcp flags bits setting. */
4197         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4198                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4199                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4200                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4201                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4202                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4203                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4204                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4205                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4206                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4207                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4208                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4209                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4210         } else {
4211                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4212         }
4213         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4214         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4215 }
4216
4217 /*
4218  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4219  *
4220  * @param
4221  * dev: Pointer to struct rte_eth_dev.
4222  * ntuple_filter: ponter to the filter that will be added.
4223  *
4224  * @return
4225  *    - On success, zero.
4226  *    - On failure, a negative value.
4227  */
4228 static int
4229 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4230                         struct rte_eth_ntuple_filter *ntuple_filter)
4231 {
4232         struct e1000_filter_info *filter_info =
4233                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4234         struct e1000_5tuple_filter *filter;
4235         uint8_t i;
4236         int ret;
4237
4238         filter = rte_zmalloc("e1000_5tuple_filter",
4239                         sizeof(struct e1000_5tuple_filter), 0);
4240         if (filter == NULL)
4241                 return -ENOMEM;
4242
4243         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4244                                             &filter->filter_info);
4245         if (ret < 0) {
4246                 rte_free(filter);
4247                 return ret;
4248         }
4249
4250         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4251                                          &filter->filter_info) != NULL) {
4252                 PMD_DRV_LOG(ERR, "filter exists.");
4253                 rte_free(filter);
4254                 return -EEXIST;
4255         }
4256         filter->queue = ntuple_filter->queue;
4257
4258         /*
4259          * look for an unused 5tuple filter index,
4260          * and insert the filter to list.
4261          */
4262         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4263                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4264                         filter_info->fivetuple_mask |= 1 << i;
4265                         filter->index = i;
4266                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4267                                           filter,
4268                                           entries);
4269                         break;
4270                 }
4271         }
4272         if (i >= E1000_MAX_FTQF_FILTERS) {
4273                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4274                 rte_free(filter);
4275                 return -ENOSYS;
4276         }
4277
4278         igb_inject_5tuple_filter_82576(dev, filter);
4279         return 0;
4280 }
4281
4282 int
4283 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4284                                 struct e1000_5tuple_filter *filter)
4285 {
4286         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4287         struct e1000_filter_info *filter_info =
4288                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4289
4290         filter_info->fivetuple_mask &= ~(1 << filter->index);
4291         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4292         rte_free(filter);
4293
4294         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4295                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4296         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4297         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4298         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4299         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4300         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4301         return 0;
4302 }
4303
4304 /*
4305  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4306  *
4307  * @param
4308  * dev: Pointer to struct rte_eth_dev.
4309  * ntuple_filter: ponter to the filter that will be removed.
4310  *
4311  * @return
4312  *    - On success, zero.
4313  *    - On failure, a negative value.
4314  */
4315 static int
4316 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4317                                 struct rte_eth_ntuple_filter *ntuple_filter)
4318 {
4319         struct e1000_filter_info *filter_info =
4320                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4321         struct e1000_5tuple_filter_info filter_5tuple;
4322         struct e1000_5tuple_filter *filter;
4323         int ret;
4324
4325         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4326         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4327                                             &filter_5tuple);
4328         if (ret < 0)
4329                 return ret;
4330
4331         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4332                                          &filter_5tuple);
4333         if (filter == NULL) {
4334                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4335                 return -ENOENT;
4336         }
4337
4338         igb_delete_5tuple_filter_82576(dev, filter);
4339
4340         return 0;
4341 }
4342
4343 static int
4344 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4345 {
4346         uint32_t rctl;
4347         struct e1000_hw *hw;
4348         struct rte_eth_dev_info dev_info;
4349         uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4350         int ret;
4351
4352         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4353
4354 #ifdef RTE_LIBRTE_82571_SUPPORT
4355         /* XXX: not bigger than max_rx_pktlen */
4356         if (hw->mac.type == e1000_82571)
4357                 return -ENOTSUP;
4358 #endif
4359         ret = eth_igb_infos_get(dev, &dev_info);
4360         if (ret != 0)
4361                 return ret;
4362
4363         /* check that mtu is within the allowed range */
4364         if (mtu < RTE_ETHER_MIN_MTU ||
4365                         frame_size > dev_info.max_rx_pktlen)
4366                 return -EINVAL;
4367
4368         /* refuse mtu that requires the support of scattered packets when this
4369          * feature has not been enabled before. */
4370         if (!dev->data->scattered_rx &&
4371             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4372                 return -EINVAL;
4373
4374         rctl = E1000_READ_REG(hw, E1000_RCTL);
4375
4376         /* switch to jumbo mode if needed */
4377         if (frame_size > RTE_ETHER_MAX_LEN) {
4378                 dev->data->dev_conf.rxmode.offloads |=
4379                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4380                 rctl |= E1000_RCTL_LPE;
4381         } else {
4382                 dev->data->dev_conf.rxmode.offloads &=
4383                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4384                 rctl &= ~E1000_RCTL_LPE;
4385         }
4386         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4387
4388         /* update max frame size */
4389         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4390
4391         E1000_WRITE_REG(hw, E1000_RLPML,
4392                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4393
4394         return 0;
4395 }
4396
4397 /*
4398  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4399  *
4400  * @param
4401  * dev: Pointer to struct rte_eth_dev.
4402  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4403  * add: if true, add filter, if false, remove filter
4404  *
4405  * @return
4406  *    - On success, zero.
4407  *    - On failure, a negative value.
4408  */
4409 int
4410 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4411                         struct rte_eth_ntuple_filter *ntuple_filter,
4412                         bool add)
4413 {
4414         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4415         int ret;
4416
4417         switch (ntuple_filter->flags) {
4418         case RTE_5TUPLE_FLAGS:
4419         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4420                 if (hw->mac.type != e1000_82576)
4421                         return -ENOTSUP;
4422                 if (add)
4423                         ret = igb_add_5tuple_filter_82576(dev,
4424                                                           ntuple_filter);
4425                 else
4426                         ret = igb_remove_5tuple_filter_82576(dev,
4427                                                              ntuple_filter);
4428                 break;
4429         case RTE_2TUPLE_FLAGS:
4430         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4431                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4432                         hw->mac.type != e1000_i210 &&
4433                         hw->mac.type != e1000_i211)
4434                         return -ENOTSUP;
4435                 if (add)
4436                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4437                 else
4438                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4439                 break;
4440         default:
4441                 ret = -EINVAL;
4442                 break;
4443         }
4444
4445         return ret;
4446 }
4447
4448 /*
4449  * igb_get_ntuple_filter - get a ntuple filter
4450  *
4451  * @param
4452  * dev: Pointer to struct rte_eth_dev.
4453  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4454  *
4455  * @return
4456  *    - On success, zero.
4457  *    - On failure, a negative value.
4458  */
4459 static int
4460 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4461                         struct rte_eth_ntuple_filter *ntuple_filter)
4462 {
4463         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4464         struct e1000_filter_info *filter_info =
4465                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4466         struct e1000_5tuple_filter_info filter_5tuple;
4467         struct e1000_2tuple_filter_info filter_2tuple;
4468         struct e1000_5tuple_filter *p_5tuple_filter;
4469         struct e1000_2tuple_filter *p_2tuple_filter;
4470         int ret;
4471
4472         switch (ntuple_filter->flags) {
4473         case RTE_5TUPLE_FLAGS:
4474         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4475                 if (hw->mac.type != e1000_82576)
4476                         return -ENOTSUP;
4477                 memset(&filter_5tuple,
4478                         0,
4479                         sizeof(struct e1000_5tuple_filter_info));
4480                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4481                                                     &filter_5tuple);
4482                 if (ret < 0)
4483                         return ret;
4484                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4485                                         &filter_info->fivetuple_list,
4486                                         &filter_5tuple);
4487                 if (p_5tuple_filter == NULL) {
4488                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4489                         return -ENOENT;
4490                 }
4491                 ntuple_filter->queue = p_5tuple_filter->queue;
4492                 break;
4493         case RTE_2TUPLE_FLAGS:
4494         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4495                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4496                         return -ENOTSUP;
4497                 memset(&filter_2tuple,
4498                         0,
4499                         sizeof(struct e1000_2tuple_filter_info));
4500                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4501                 if (ret < 0)
4502                         return ret;
4503                 p_2tuple_filter = igb_2tuple_filter_lookup(
4504                                         &filter_info->twotuple_list,
4505                                         &filter_2tuple);
4506                 if (p_2tuple_filter == NULL) {
4507                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4508                         return -ENOENT;
4509                 }
4510                 ntuple_filter->queue = p_2tuple_filter->queue;
4511                 break;
4512         default:
4513                 ret = -EINVAL;
4514                 break;
4515         }
4516
4517         return 0;
4518 }
4519
4520 /*
4521  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4522  * @dev: pointer to rte_eth_dev structure
4523  * @filter_op:operation will be taken.
4524  * @arg: a pointer to specific structure corresponding to the filter_op
4525  */
4526 static int
4527 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4528                                 enum rte_filter_op filter_op,
4529                                 void *arg)
4530 {
4531         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4532         int ret;
4533
4534         MAC_TYPE_FILTER_SUP(hw->mac.type);
4535
4536         if (filter_op == RTE_ETH_FILTER_NOP)
4537                 return 0;
4538
4539         if (arg == NULL) {
4540                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4541                             filter_op);
4542                 return -EINVAL;
4543         }
4544
4545         switch (filter_op) {
4546         case RTE_ETH_FILTER_ADD:
4547                 ret = igb_add_del_ntuple_filter(dev,
4548                         (struct rte_eth_ntuple_filter *)arg,
4549                         TRUE);
4550                 break;
4551         case RTE_ETH_FILTER_DELETE:
4552                 ret = igb_add_del_ntuple_filter(dev,
4553                         (struct rte_eth_ntuple_filter *)arg,
4554                         FALSE);
4555                 break;
4556         case RTE_ETH_FILTER_GET:
4557                 ret = igb_get_ntuple_filter(dev,
4558                         (struct rte_eth_ntuple_filter *)arg);
4559                 break;
4560         default:
4561                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4562                 ret = -EINVAL;
4563                 break;
4564         }
4565         return ret;
4566 }
4567
4568 static inline int
4569 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4570                         uint16_t ethertype)
4571 {
4572         int i;
4573
4574         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4575                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4576                     (filter_info->ethertype_mask & (1 << i)))
4577                         return i;
4578         }
4579         return -1;
4580 }
4581
4582 static inline int
4583 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4584                         uint16_t ethertype, uint32_t etqf)
4585 {
4586         int i;
4587
4588         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4589                 if (!(filter_info->ethertype_mask & (1 << i))) {
4590                         filter_info->ethertype_mask |= 1 << i;
4591                         filter_info->ethertype_filters[i].ethertype = ethertype;
4592                         filter_info->ethertype_filters[i].etqf = etqf;
4593                         return i;
4594                 }
4595         }
4596         return -1;
4597 }
4598
4599 int
4600 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4601                         uint8_t idx)
4602 {
4603         if (idx >= E1000_MAX_ETQF_FILTERS)
4604                 return -1;
4605         filter_info->ethertype_mask &= ~(1 << idx);
4606         filter_info->ethertype_filters[idx].ethertype = 0;
4607         filter_info->ethertype_filters[idx].etqf = 0;
4608         return idx;
4609 }
4610
4611
4612 int
4613 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4614                         struct rte_eth_ethertype_filter *filter,
4615                         bool add)
4616 {
4617         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4618         struct e1000_filter_info *filter_info =
4619                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4620         uint32_t etqf = 0;
4621         int ret;
4622
4623         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4624                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4625                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4626                         " ethertype filter.", filter->ether_type);
4627                 return -EINVAL;
4628         }
4629
4630         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4631                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4632                 return -EINVAL;
4633         }
4634         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4635                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4636                 return -EINVAL;
4637         }
4638
4639         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4640         if (ret >= 0 && add) {
4641                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4642                             filter->ether_type);
4643                 return -EEXIST;
4644         }
4645         if (ret < 0 && !add) {
4646                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4647                             filter->ether_type);
4648                 return -ENOENT;
4649         }
4650
4651         if (add) {
4652                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4653                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4654                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4655                 ret = igb_ethertype_filter_insert(filter_info,
4656                                 filter->ether_type, etqf);
4657                 if (ret < 0) {
4658                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4659                         return -ENOSYS;
4660                 }
4661         } else {
4662                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4663                 if (ret < 0)
4664                         return -ENOSYS;
4665         }
4666         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4667         E1000_WRITE_FLUSH(hw);
4668
4669         return 0;
4670 }
4671
4672 static int
4673 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4674                      enum rte_filter_type filter_type,
4675                      enum rte_filter_op filter_op,
4676                      void *arg)
4677 {
4678         int ret = 0;
4679
4680         switch (filter_type) {
4681         case RTE_ETH_FILTER_NTUPLE:
4682                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4683                 break;
4684         case RTE_ETH_FILTER_GENERIC:
4685                 if (filter_op != RTE_ETH_FILTER_GET)
4686                         return -EINVAL;
4687                 *(const void **)arg = &igb_flow_ops;
4688                 break;
4689         default:
4690                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4691                                                         filter_type);
4692                 break;
4693         }
4694
4695         return ret;
4696 }
4697
4698 static int
4699 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4700                          struct rte_ether_addr *mc_addr_set,
4701                          uint32_t nb_mc_addr)
4702 {
4703         struct e1000_hw *hw;
4704
4705         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4706         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4707         return 0;
4708 }
4709
4710 static uint64_t
4711 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4712 {
4713         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4714         uint64_t systime_cycles;
4715
4716         switch (hw->mac.type) {
4717         case e1000_i210:
4718         case e1000_i211:
4719                 /*
4720                  * Need to read System Time Residue Register to be able
4721                  * to read the other two registers.
4722                  */
4723                 E1000_READ_REG(hw, E1000_SYSTIMR);
4724                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4725                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4726                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4727                                 * NSEC_PER_SEC;
4728                 break;
4729         case e1000_82580:
4730         case e1000_i350:
4731         case e1000_i354:
4732                 /*
4733                  * Need to read System Time Residue Register to be able
4734                  * to read the other two registers.
4735                  */
4736                 E1000_READ_REG(hw, E1000_SYSTIMR);
4737                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4738                 /* Only the 8 LSB are valid. */
4739                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4740                                 & 0xff) << 32;
4741                 break;
4742         default:
4743                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4744                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4745                                 << 32;
4746                 break;
4747         }
4748
4749         return systime_cycles;
4750 }
4751
4752 static uint64_t
4753 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4754 {
4755         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4756         uint64_t rx_tstamp_cycles;
4757
4758         switch (hw->mac.type) {
4759         case e1000_i210:
4760         case e1000_i211:
4761                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4762                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4763                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4764                                 * NSEC_PER_SEC;
4765                 break;
4766         case e1000_82580:
4767         case e1000_i350:
4768         case e1000_i354:
4769                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4770                 /* Only the 8 LSB are valid. */
4771                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4772                                 & 0xff) << 32;
4773                 break;
4774         default:
4775                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4776                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4777                                 << 32;
4778                 break;
4779         }
4780
4781         return rx_tstamp_cycles;
4782 }
4783
4784 static uint64_t
4785 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4786 {
4787         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4788         uint64_t tx_tstamp_cycles;
4789
4790         switch (hw->mac.type) {
4791         case e1000_i210:
4792         case e1000_i211:
4793                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4794                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4795                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4796                                 * NSEC_PER_SEC;
4797                 break;
4798         case e1000_82580:
4799         case e1000_i350:
4800         case e1000_i354:
4801                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4802                 /* Only the 8 LSB are valid. */
4803                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4804                                 & 0xff) << 32;
4805                 break;
4806         default:
4807                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4808                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4809                                 << 32;
4810                 break;
4811         }
4812
4813         return tx_tstamp_cycles;
4814 }
4815
4816 static void
4817 igb_start_timecounters(struct rte_eth_dev *dev)
4818 {
4819         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4820         struct e1000_adapter *adapter = dev->data->dev_private;
4821         uint32_t incval = 1;
4822         uint32_t shift = 0;
4823         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4824
4825         switch (hw->mac.type) {
4826         case e1000_82580:
4827         case e1000_i350:
4828         case e1000_i354:
4829                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4830                 mask = (1ULL << 40) - 1;
4831                 /* fall-through */
4832         case e1000_i210:
4833         case e1000_i211:
4834                 /*
4835                  * Start incrementing the register
4836                  * used to timestamp PTP packets.
4837                  */
4838                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4839                 break;
4840         case e1000_82576:
4841                 incval = E1000_INCVALUE_82576;
4842                 shift = IGB_82576_TSYNC_SHIFT;
4843                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4844                                 E1000_INCPERIOD_82576 | incval);
4845                 break;
4846         default:
4847                 /* Not supported */
4848                 return;
4849         }
4850
4851         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4852         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4853         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4854
4855         adapter->systime_tc.cc_mask = mask;
4856         adapter->systime_tc.cc_shift = shift;
4857         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4858
4859         adapter->rx_tstamp_tc.cc_mask = mask;
4860         adapter->rx_tstamp_tc.cc_shift = shift;
4861         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4862
4863         adapter->tx_tstamp_tc.cc_mask = mask;
4864         adapter->tx_tstamp_tc.cc_shift = shift;
4865         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4866 }
4867
4868 static int
4869 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4870 {
4871         struct e1000_adapter *adapter = dev->data->dev_private;
4872
4873         adapter->systime_tc.nsec += delta;
4874         adapter->rx_tstamp_tc.nsec += delta;
4875         adapter->tx_tstamp_tc.nsec += delta;
4876
4877         return 0;
4878 }
4879
4880 static int
4881 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4882 {
4883         uint64_t ns;
4884         struct e1000_adapter *adapter = dev->data->dev_private;
4885
4886         ns = rte_timespec_to_ns(ts);
4887
4888         /* Set the timecounters to a new value. */
4889         adapter->systime_tc.nsec = ns;
4890         adapter->rx_tstamp_tc.nsec = ns;
4891         adapter->tx_tstamp_tc.nsec = ns;
4892
4893         return 0;
4894 }
4895
4896 static int
4897 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4898 {
4899         uint64_t ns, systime_cycles;
4900         struct e1000_adapter *adapter = dev->data->dev_private;
4901
4902         systime_cycles = igb_read_systime_cyclecounter(dev);
4903         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4904         *ts = rte_ns_to_timespec(ns);
4905
4906         return 0;
4907 }
4908
4909 static int
4910 igb_timesync_enable(struct rte_eth_dev *dev)
4911 {
4912         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4913         uint32_t tsync_ctl;
4914         uint32_t tsauxc;
4915
4916         /* Stop the timesync system time. */
4917         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4918         /* Reset the timesync system time value. */
4919         switch (hw->mac.type) {
4920         case e1000_82580:
4921         case e1000_i350:
4922         case e1000_i354:
4923         case e1000_i210:
4924         case e1000_i211:
4925                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4926                 /* fall-through */
4927         case e1000_82576:
4928                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4929                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4930                 break;
4931         default:
4932                 /* Not supported. */
4933                 return -ENOTSUP;
4934         }
4935
4936         /* Enable system time for it isn't on by default. */
4937         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4938         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4939         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4940
4941         igb_start_timecounters(dev);
4942
4943         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4944         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4945                         (RTE_ETHER_TYPE_1588 |
4946                          E1000_ETQF_FILTER_ENABLE |
4947                          E1000_ETQF_1588));
4948
4949         /* Enable timestamping of received PTP packets. */
4950         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4951         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4952         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4953
4954         /* Enable Timestamping of transmitted PTP packets. */
4955         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4956         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4957         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4958
4959         return 0;
4960 }
4961
4962 static int
4963 igb_timesync_disable(struct rte_eth_dev *dev)
4964 {
4965         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4966         uint32_t tsync_ctl;
4967
4968         /* Disable timestamping of transmitted PTP packets. */
4969         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4970         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4971         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4972
4973         /* Disable timestamping of received PTP packets. */
4974         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4975         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4976         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4977
4978         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4979         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4980
4981         /* Stop incrementating the System Time registers. */
4982         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4983
4984         return 0;
4985 }
4986
4987 static int
4988 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4989                                struct timespec *timestamp,
4990                                uint32_t flags __rte_unused)
4991 {
4992         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4993         struct e1000_adapter *adapter = dev->data->dev_private;
4994         uint32_t tsync_rxctl;
4995         uint64_t rx_tstamp_cycles;
4996         uint64_t ns;
4997
4998         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4999         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5000                 return -EINVAL;
5001
5002         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5003         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5004         *timestamp = rte_ns_to_timespec(ns);
5005
5006         return  0;
5007 }
5008
5009 static int
5010 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5011                                struct timespec *timestamp)
5012 {
5013         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5014         struct e1000_adapter *adapter = dev->data->dev_private;
5015         uint32_t tsync_txctl;
5016         uint64_t tx_tstamp_cycles;
5017         uint64_t ns;
5018
5019         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5020         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5021                 return -EINVAL;
5022
5023         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5024         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5025         *timestamp = rte_ns_to_timespec(ns);
5026
5027         return  0;
5028 }
5029
5030 static int
5031 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5032 {
5033         int count = 0;
5034         int g_ind = 0;
5035         const struct reg_info *reg_group;
5036
5037         while ((reg_group = igb_regs[g_ind++]))
5038                 count += igb_reg_group_count(reg_group);
5039
5040         return count;
5041 }
5042
5043 static int
5044 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5045 {
5046         int count = 0;
5047         int g_ind = 0;
5048         const struct reg_info *reg_group;
5049
5050         while ((reg_group = igbvf_regs[g_ind++]))
5051                 count += igb_reg_group_count(reg_group);
5052
5053         return count;
5054 }
5055
5056 static int
5057 eth_igb_get_regs(struct rte_eth_dev *dev,
5058         struct rte_dev_reg_info *regs)
5059 {
5060         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5061         uint32_t *data = regs->data;
5062         int g_ind = 0;
5063         int count = 0;
5064         const struct reg_info *reg_group;
5065
5066         if (data == NULL) {
5067                 regs->length = eth_igb_get_reg_length(dev);
5068                 regs->width = sizeof(uint32_t);
5069                 return 0;
5070         }
5071
5072         /* Support only full register dump */
5073         if ((regs->length == 0) ||
5074             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5075                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5076                         hw->device_id;
5077                 while ((reg_group = igb_regs[g_ind++]))
5078                         count += igb_read_regs_group(dev, &data[count],
5079                                                         reg_group);
5080                 return 0;
5081         }
5082
5083         return -ENOTSUP;
5084 }
5085
5086 static int
5087 igbvf_get_regs(struct rte_eth_dev *dev,
5088         struct rte_dev_reg_info *regs)
5089 {
5090         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5091         uint32_t *data = regs->data;
5092         int g_ind = 0;
5093         int count = 0;
5094         const struct reg_info *reg_group;
5095
5096         if (data == NULL) {
5097                 regs->length = igbvf_get_reg_length(dev);
5098                 regs->width = sizeof(uint32_t);
5099                 return 0;
5100         }
5101
5102         /* Support only full register dump */
5103         if ((regs->length == 0) ||
5104             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5105                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5106                         hw->device_id;
5107                 while ((reg_group = igbvf_regs[g_ind++]))
5108                         count += igb_read_regs_group(dev, &data[count],
5109                                                         reg_group);
5110                 return 0;
5111         }
5112
5113         return -ENOTSUP;
5114 }
5115
5116 static int
5117 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5118 {
5119         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5120
5121         /* Return unit is byte count */
5122         return hw->nvm.word_size * 2;
5123 }
5124
5125 static int
5126 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5127         struct rte_dev_eeprom_info *in_eeprom)
5128 {
5129         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5130         struct e1000_nvm_info *nvm = &hw->nvm;
5131         uint16_t *data = in_eeprom->data;
5132         int first, length;
5133
5134         first = in_eeprom->offset >> 1;
5135         length = in_eeprom->length >> 1;
5136         if ((first >= hw->nvm.word_size) ||
5137             ((first + length) >= hw->nvm.word_size))
5138                 return -EINVAL;
5139
5140         in_eeprom->magic = hw->vendor_id |
5141                 ((uint32_t)hw->device_id << 16);
5142
5143         if ((nvm->ops.read) == NULL)
5144                 return -ENOTSUP;
5145
5146         return nvm->ops.read(hw, first, length, data);
5147 }
5148
5149 static int
5150 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5151         struct rte_dev_eeprom_info *in_eeprom)
5152 {
5153         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5154         struct e1000_nvm_info *nvm = &hw->nvm;
5155         uint16_t *data = in_eeprom->data;
5156         int first, length;
5157
5158         first = in_eeprom->offset >> 1;
5159         length = in_eeprom->length >> 1;
5160         if ((first >= hw->nvm.word_size) ||
5161             ((first + length) >= hw->nvm.word_size))
5162                 return -EINVAL;
5163
5164         in_eeprom->magic = (uint32_t)hw->vendor_id |
5165                 ((uint32_t)hw->device_id << 16);
5166
5167         if ((nvm->ops.write) == NULL)
5168                 return -ENOTSUP;
5169         return nvm->ops.write(hw,  first, length, data);
5170 }
5171
5172 static int
5173 eth_igb_get_module_info(struct rte_eth_dev *dev,
5174                         struct rte_eth_dev_module_info *modinfo)
5175 {
5176         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5177
5178         uint32_t status = 0;
5179         uint16_t sff8472_rev, addr_mode;
5180         bool page_swap = false;
5181
5182         if (hw->phy.media_type == e1000_media_type_copper ||
5183             hw->phy.media_type == e1000_media_type_unknown)
5184                 return -EOPNOTSUPP;
5185
5186         /* Check whether we support SFF-8472 or not */
5187         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5188         if (status)
5189                 return -EIO;
5190
5191         /* addressing mode is not supported */
5192         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5193         if (status)
5194                 return -EIO;
5195
5196         /* addressing mode is not supported */
5197         if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5198                 PMD_DRV_LOG(ERR,
5199                             "Address change required to access page 0xA2, "
5200                             "but not supported. Please report the module "
5201                             "type to the driver maintainers.\n");
5202                 page_swap = true;
5203         }
5204
5205         if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5206                 /* We have an SFP, but it does not support SFF-8472 */
5207                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5208                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5209         } else {
5210                 /* We have an SFP which supports a revision of SFF-8472 */
5211                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5212                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5213         }
5214
5215         return 0;
5216 }
5217
5218 static int
5219 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5220                           struct rte_dev_eeprom_info *info)
5221 {
5222         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5223
5224         uint32_t status = 0;
5225         uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5226         u16 first_word, last_word;
5227         int i = 0;
5228
5229         if (info->length == 0)
5230                 return -EINVAL;
5231
5232         first_word = info->offset >> 1;
5233         last_word = (info->offset + info->length - 1) >> 1;
5234
5235         /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5236         for (i = 0; i < last_word - first_word + 1; i++) {
5237                 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5238                                                 &dataword[i]);
5239                 if (status) {
5240                         /* Error occurred while reading module */
5241                         return -EIO;
5242                 }
5243
5244                 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5245         }
5246
5247         memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5248
5249         return 0;
5250 }
5251
5252 static int
5253 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5254 {
5255         struct e1000_hw *hw =
5256                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5257         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5258         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5259         uint32_t vec = E1000_MISC_VEC_ID;
5260
5261         if (rte_intr_allow_others(intr_handle))
5262                 vec = E1000_RX_VEC_START;
5263
5264         uint32_t mask = 1 << (queue_id + vec);
5265
5266         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5267         E1000_WRITE_FLUSH(hw);
5268
5269         return 0;
5270 }
5271
5272 static int
5273 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5274 {
5275         struct e1000_hw *hw =
5276                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5277         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5278         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5279         uint32_t vec = E1000_MISC_VEC_ID;
5280
5281         if (rte_intr_allow_others(intr_handle))
5282                 vec = E1000_RX_VEC_START;
5283
5284         uint32_t mask = 1 << (queue_id + vec);
5285         uint32_t regval;
5286
5287         regval = E1000_READ_REG(hw, E1000_EIMS);
5288         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5289         E1000_WRITE_FLUSH(hw);
5290
5291         rte_intr_ack(intr_handle);
5292
5293         return 0;
5294 }
5295
5296 static void
5297 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5298                    uint8_t index, uint8_t offset)
5299 {
5300         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5301
5302         /* clear bits */
5303         val &= ~((uint32_t)0xFF << offset);
5304
5305         /* write vector and valid bit */
5306         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5307
5308         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5309 }
5310
5311 static void
5312 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5313                            uint8_t queue, uint8_t msix_vector)
5314 {
5315         uint32_t tmp = 0;
5316
5317         if (hw->mac.type == e1000_82575) {
5318                 if (direction == 0)
5319                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5320                 else if (direction == 1)
5321                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5322                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5323         } else if (hw->mac.type == e1000_82576) {
5324                 if ((direction == 0) || (direction == 1))
5325                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5326                                            ((queue & 0x8) << 1) +
5327                                            8 * direction);
5328         } else if ((hw->mac.type == e1000_82580) ||
5329                         (hw->mac.type == e1000_i350) ||
5330                         (hw->mac.type == e1000_i354) ||
5331                         (hw->mac.type == e1000_i210) ||
5332                         (hw->mac.type == e1000_i211)) {
5333                 if ((direction == 0) || (direction == 1))
5334                         eth_igb_write_ivar(hw, msix_vector,
5335                                            queue >> 1,
5336                                            ((queue & 0x1) << 4) +
5337                                            8 * direction);
5338         }
5339 }
5340
5341 /* Sets up the hardware to generate MSI-X interrupts properly
5342  * @hw
5343  *  board private structure
5344  */
5345 static void
5346 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5347 {
5348         int queue_id;
5349         uint32_t tmpval, regval, intr_mask;
5350         struct e1000_hw *hw =
5351                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5352         uint32_t vec = E1000_MISC_VEC_ID;
5353         uint32_t base = E1000_MISC_VEC_ID;
5354         uint32_t misc_shift = 0;
5355         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5356         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5357
5358         /* won't configure msix register if no mapping is done
5359          * between intr vector and event fd
5360          */
5361         if (!rte_intr_dp_is_en(intr_handle))
5362                 return;
5363
5364         if (rte_intr_allow_others(intr_handle)) {
5365                 vec = base = E1000_RX_VEC_START;
5366                 misc_shift = 1;
5367         }
5368
5369         /* set interrupt vector for other causes */
5370         if (hw->mac.type == e1000_82575) {
5371                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5372                 /* enable MSI-X PBA support */
5373                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5374
5375                 /* Auto-Mask interrupts upon ICR read */
5376                 tmpval |= E1000_CTRL_EXT_EIAME;
5377                 tmpval |= E1000_CTRL_EXT_IRCA;
5378
5379                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5380
5381                 /* enable msix_other interrupt */
5382                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5383                 regval = E1000_READ_REG(hw, E1000_EIAC);
5384                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5385                 regval = E1000_READ_REG(hw, E1000_EIAM);
5386                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5387         } else if ((hw->mac.type == e1000_82576) ||
5388                         (hw->mac.type == e1000_82580) ||
5389                         (hw->mac.type == e1000_i350) ||
5390                         (hw->mac.type == e1000_i354) ||
5391                         (hw->mac.type == e1000_i210) ||
5392                         (hw->mac.type == e1000_i211)) {
5393                 /* turn on MSI-X capability first */
5394                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5395                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5396                                         E1000_GPIE_NSICR);
5397                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5398                         misc_shift;
5399
5400                 if (dev->data->dev_conf.intr_conf.lsc != 0)
5401                         intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5402
5403                 regval = E1000_READ_REG(hw, E1000_EIAC);
5404                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5405
5406                 /* enable msix_other interrupt */
5407                 regval = E1000_READ_REG(hw, E1000_EIMS);
5408                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5409                 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5410                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5411         }
5412
5413         /* use EIAM to auto-mask when MSI-X interrupt
5414          * is asserted, this saves a register write for every interrupt
5415          */
5416         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5417                 misc_shift;
5418
5419         if (dev->data->dev_conf.intr_conf.lsc != 0)
5420                 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5421
5422         regval = E1000_READ_REG(hw, E1000_EIAM);
5423         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5424
5425         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5426                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5427                 intr_handle->intr_vec[queue_id] = vec;
5428                 if (vec < base + intr_handle->nb_efd - 1)
5429                         vec++;
5430         }
5431
5432         E1000_WRITE_FLUSH(hw);
5433 }
5434
5435 /* restore n-tuple filter */
5436 static inline void
5437 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5438 {
5439         struct e1000_filter_info *filter_info =
5440                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5441         struct e1000_5tuple_filter *p_5tuple;
5442         struct e1000_2tuple_filter *p_2tuple;
5443
5444         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5445                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5446         }
5447
5448         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5449                 igb_inject_2uple_filter(dev, p_2tuple);
5450         }
5451 }
5452
5453 /* restore SYN filter */
5454 static inline void
5455 igb_syn_filter_restore(struct rte_eth_dev *dev)
5456 {
5457         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5458         struct e1000_filter_info *filter_info =
5459                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5460         uint32_t synqf;
5461
5462         synqf = filter_info->syn_info;
5463
5464         if (synqf & E1000_SYN_FILTER_ENABLE) {
5465                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5466                 E1000_WRITE_FLUSH(hw);
5467         }
5468 }
5469
5470 /* restore ethernet type filter */
5471 static inline void
5472 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5473 {
5474         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5475         struct e1000_filter_info *filter_info =
5476                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5477         int i;
5478
5479         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5480                 if (filter_info->ethertype_mask & (1 << i)) {
5481                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5482                                 filter_info->ethertype_filters[i].etqf);
5483                         E1000_WRITE_FLUSH(hw);
5484                 }
5485         }
5486 }
5487
5488 /* restore flex byte filter */
5489 static inline void
5490 igb_flex_filter_restore(struct rte_eth_dev *dev)
5491 {
5492         struct e1000_filter_info *filter_info =
5493                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5494         struct e1000_flex_filter *flex_filter;
5495
5496         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5497                 igb_inject_flex_filter(dev, flex_filter);
5498         }
5499 }
5500
5501 /* restore rss filter */
5502 static inline void
5503 igb_rss_filter_restore(struct rte_eth_dev *dev)
5504 {
5505         struct e1000_filter_info *filter_info =
5506                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5507
5508         if (filter_info->rss_info.conf.queue_num)
5509                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5510 }
5511
5512 /* restore all types filter */
5513 static int
5514 igb_filter_restore(struct rte_eth_dev *dev)
5515 {
5516         igb_ntuple_filter_restore(dev);
5517         igb_ethertype_filter_restore(dev);
5518         igb_syn_filter_restore(dev);
5519         igb_flex_filter_restore(dev);
5520         igb_rss_filter_restore(dev);
5521
5522         return 0;
5523 }
5524
5525 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5526 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5527 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5528 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5529 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5530 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5531
5532 /* see e1000_logs.c */
5533 RTE_INIT(e1000_init_log)
5534 {
5535         e1000_igb_init_log();
5536 }