drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "base/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59 #include "igb_regs.h"
  60
  61 /*
  62  * Default values for port configuration
  63  */
  64 #define IGB_DEFAULT_RX_FREE_THRESH  32
  65
  66 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  67 #define IGB_DEFAULT_RX_HTHRESH      8
  68 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  69
  70 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  71 #define IGB_DEFAULT_TX_HTHRESH      1
  72 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  73
  74 #define IGB_HKEY_MAX_INDEX 10
  75
  76 /* Bit shift and mask */
  77 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  78 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  79 #define IGB_8_BIT_WIDTH  CHAR_BIT
  80 #define IGB_8_BIT_MASK   UINT8_MAX
  81
  82 /* Additional timesync values. */
  83 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  84 #define E1000_ETQF_FILTER_1588       3
  85 #define IGB_82576_TSYNC_SHIFT        16
  86 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  87 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  89
  90 #define E1000_VTIVAR_MISC                0x01740
  91 #define E1000_VTIVAR_MISC_MASK           0xFF
  92 #define E1000_VTIVAR_VALID               0x80
  93 #define E1000_VTIVAR_MISC_MAILBOX        0
  94 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  95
  96 /* External VLAN Enable bit mask */
  97 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  98
  99 /* External VLAN Ether Type bit mask and shift */
 100 #define E1000_VET_VET_EXT            0xFFFF0000
 101 #define E1000_VET_VET_EXT_SHIFT      16
 102
 103 static int  eth_igb_configure(struct rte_eth_dev *dev);
 104 static int  eth_igb_start(struct rte_eth_dev *dev);
 105 static void eth_igb_stop(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 107 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 108 static void eth_igb_close(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 113 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 114                                 int wait_to_complete);
 115 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 116                                 struct rte_eth_stats *rte_stats);
 117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 118                               struct rte_eth_xstat *xstats, unsigned n);
 119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
 120                 const uint64_t *ids,
 121                 uint64_t *values, unsigned int n);
 122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 123                                     struct rte_eth_xstat_name *xstats_names,
 124                                     unsigned int size);
 125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
 126                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 127                 unsigned int limit);
 128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 131                                    char *fw_version, size_t fw_size);
 132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 133                               struct rte_eth_dev_info *dev_info);
 134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 136                                 struct rte_eth_dev_info *dev_info);
 137 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 138                                 struct rte_eth_fc_conf *fc_conf);
 139 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 140                                 struct rte_eth_fc_conf *fc_conf);
 141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 145                                     struct rte_intr_handle *handle);
 146 static void eth_igb_interrupt_handler(void *param);
 147 static int  igb_hardware_init(struct e1000_hw *hw);
 148 static void igb_hw_control_acquire(struct e1000_hw *hw);
 149 static void igb_hw_control_release(struct e1000_hw *hw);
 150 static void igb_init_manageability(struct e1000_hw *hw);
 151 static void igb_release_manageability(struct e1000_hw *hw);
 152
 153 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154
 155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 156                 uint16_t vlan_id, int on);
 157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 158                                  enum rte_vlan_type vlan_type,
 159                                  uint16_t tpid_id);
 160 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 161
 162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 168
 169 static int eth_igb_led_on(struct rte_eth_dev *dev);
 170 static int eth_igb_led_off(struct rte_eth_dev *dev);
 171
 172 static void igb_intr_disable(struct e1000_hw *hw);
 173 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 174 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 175                            struct ether_addr *mac_addr,
 176                            uint32_t index, uint32_t pool);
 177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 179                 struct ether_addr *addr);
 180
 181 static void igbvf_intr_disable(struct e1000_hw *hw);
 182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 183 static int igbvf_dev_start(struct rte_eth_dev *dev);
 184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 185 static void igbvf_dev_close(struct rte_eth_dev *dev);
 186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 190 static int eth_igbvf_link_update(struct e1000_hw *hw);
 191 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 192                                 struct rte_eth_stats *rte_stats);
 193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 194                                 struct rte_eth_xstat *xstats, unsigned n);
 195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 196                                       struct rte_eth_xstat_name *xstats_names,
 197                                       unsigned limit);
 198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 200                 uint16_t vlan_id, int on);
 201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 204                 struct ether_addr *addr);
 205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 206 static int igbvf_get_regs(struct rte_eth_dev *dev,
 207                 struct rte_dev_reg_info *regs);
 208
 209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 210                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 211                                    uint16_t reta_size);
 212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 213                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 214                                   uint16_t reta_size);
 215
 216 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 217                         struct rte_eth_syn_filter *filter,
 218                         bool add);
 219 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 220                         struct rte_eth_syn_filter *filter);
 221 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 222                         enum rte_filter_op filter_op,
 223                         void *arg);
 224 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 225                         struct rte_eth_ntuple_filter *ntuple_filter);
 226 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 227                         struct rte_eth_ntuple_filter *ntuple_filter);
 228 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 229                         struct rte_eth_flex_filter *filter,
 230                         bool add);
 231 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 232                         struct rte_eth_flex_filter *filter);
 233 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 234                         enum rte_filter_op filter_op,
 235                         void *arg);
 236 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 237                         struct rte_eth_ntuple_filter *ntuple_filter);
 238 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 239                         struct rte_eth_ntuple_filter *ntuple_filter);
 240 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 241                         struct rte_eth_ntuple_filter *filter,
 242                         bool add);
 243 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 244                         struct rte_eth_ntuple_filter *filter);
 245 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 246                                 enum rte_filter_op filter_op,
 247                                 void *arg);
 248 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 249                         struct rte_eth_ethertype_filter *filter,
 250                         bool add);
 251 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 252                                 enum rte_filter_op filter_op,
 253                                 void *arg);
 254 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 255                         struct rte_eth_ethertype_filter *filter);
 256 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 257                      enum rte_filter_type filter_type,
 258                      enum rte_filter_op filter_op,
 259                      void *arg);
 260 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 261 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 262                 struct rte_dev_reg_info *regs);
 263 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 264 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 265                 struct rte_dev_eeprom_info *eeprom);
 266 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 267                 struct rte_dev_eeprom_info *eeprom);
 268 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 269                                     struct ether_addr *mc_addr_set,
 270                                     uint32_t nb_mc_addr);
 271 static int igb_timesync_enable(struct rte_eth_dev *dev);
 272 static int igb_timesync_disable(struct rte_eth_dev *dev);
 273 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 274                                           struct timespec *timestamp,
 275                                           uint32_t flags);
 276 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 277                                           struct timespec *timestamp);
 278 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 279 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 280                                   struct timespec *timestamp);
 281 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 282                                    const struct timespec *timestamp);
 283 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 284                                         uint16_t queue_id);
 285 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 286                                          uint16_t queue_id);
 287 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 288                                        uint8_t queue, uint8_t msix_vector);
 289 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 290                                uint8_t index, uint8_t offset);
 291 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 292 static void eth_igbvf_interrupt_handler(void *param);
 293 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 294 static int igb_filter_restore(struct rte_eth_dev *dev);
 295
 296 /*
 297  * Define VF Stats MACRO for Non "cleared on read" register
 298  */
 299 #define UPDATE_VF_STAT(reg, last, cur)            \
 300 {                                                 \
 301         u32 latest = E1000_READ_REG(hw, reg);     \
 302         cur += (latest - last) & UINT_MAX;        \
 303         last = latest;                            \
 304 }
 305
 306 #define IGB_FC_PAUSE_TIME 0x0680
 307 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 308 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 309
 310 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 311
 312 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 313
 314 /*
 315  * The set of PCI devices this driver supports
 316  */
 317 static const struct rte_pci_id pci_id_igb_map[] = {
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 326
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 330
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 337
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 348         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 349         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 350         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 351         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 352         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 353         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 354         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 357         { .vendor_id = 0, /* sentinel */ },
 358 };
 359
 360 /*
 361  * The set of PCI devices this driver supports (for 82576&I350 VF)
 362  */
 363 static const struct rte_pci_id pci_id_igbvf_map[] = {
 364         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 365         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 366         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 367         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 368         { .vendor_id = 0, /* sentinel */ },
 369 };
 370
 371 static const struct rte_eth_desc_lim rx_desc_lim = {
 372         .nb_max = E1000_MAX_RING_DESC,
 373         .nb_min = E1000_MIN_RING_DESC,
 374         .nb_align = IGB_RXD_ALIGN,
 375 };
 376
 377 static const struct rte_eth_desc_lim tx_desc_lim = {
 378         .nb_max = E1000_MAX_RING_DESC,
 379         .nb_min = E1000_MIN_RING_DESC,
 380         .nb_align = IGB_RXD_ALIGN,
 381         .nb_seg_max = IGB_TX_MAX_SEG,
 382         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 383 };
 384
 385 static const struct eth_dev_ops eth_igb_ops = {
 386         .dev_configure        = eth_igb_configure,
 387         .dev_start            = eth_igb_start,
 388         .dev_stop             = eth_igb_stop,
 389         .dev_set_link_up      = eth_igb_dev_set_link_up,
 390         .dev_set_link_down    = eth_igb_dev_set_link_down,
 391         .dev_close            = eth_igb_close,
 392         .promiscuous_enable   = eth_igb_promiscuous_enable,
 393         .promiscuous_disable  = eth_igb_promiscuous_disable,
 394         .allmulticast_enable  = eth_igb_allmulticast_enable,
 395         .allmulticast_disable = eth_igb_allmulticast_disable,
 396         .link_update          = eth_igb_link_update,
 397         .stats_get            = eth_igb_stats_get,
 398         .xstats_get           = eth_igb_xstats_get,
 399         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 400         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 401         .xstats_get_names     = eth_igb_xstats_get_names,
 402         .stats_reset          = eth_igb_stats_reset,
 403         .xstats_reset         = eth_igb_xstats_reset,
 404         .fw_version_get       = eth_igb_fw_version_get,
 405         .dev_infos_get        = eth_igb_infos_get,
 406         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 407         .mtu_set              = eth_igb_mtu_set,
 408         .vlan_filter_set      = eth_igb_vlan_filter_set,
 409         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 410         .vlan_offload_set     = eth_igb_vlan_offload_set,
 411         .rx_queue_setup       = eth_igb_rx_queue_setup,
 412         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 413         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 414         .rx_queue_release     = eth_igb_rx_queue_release,
 415         .rx_queue_count       = eth_igb_rx_queue_count,
 416         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 417         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 418         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 419         .tx_queue_setup       = eth_igb_tx_queue_setup,
 420         .tx_queue_release     = eth_igb_tx_queue_release,
 421         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 422         .dev_led_on           = eth_igb_led_on,
 423         .dev_led_off          = eth_igb_led_off,
 424         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 425         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 426         .mac_addr_add         = eth_igb_rar_set,
 427         .mac_addr_remove      = eth_igb_rar_clear,
 428         .mac_addr_set         = eth_igb_default_mac_addr_set,
 429         .reta_update          = eth_igb_rss_reta_update,
 430         .reta_query           = eth_igb_rss_reta_query,
 431         .rss_hash_update      = eth_igb_rss_hash_update,
 432         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 433         .filter_ctrl          = eth_igb_filter_ctrl,
 434         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 435         .rxq_info_get         = igb_rxq_info_get,
 436         .txq_info_get         = igb_txq_info_get,
 437         .timesync_enable      = igb_timesync_enable,
 438         .timesync_disable     = igb_timesync_disable,
 439         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 440         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 441         .get_reg              = eth_igb_get_regs,
 442         .get_eeprom_length    = eth_igb_get_eeprom_length,
 443         .get_eeprom           = eth_igb_get_eeprom,
 444         .set_eeprom           = eth_igb_set_eeprom,
 445         .timesync_adjust_time = igb_timesync_adjust_time,
 446         .timesync_read_time   = igb_timesync_read_time,
 447         .timesync_write_time  = igb_timesync_write_time,
 448 };
 449
 450 /*
 451  * dev_ops for virtual function, bare necessities for basic vf
 452  * operation have been implemented
 453  */
 454 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 455         .dev_configure        = igbvf_dev_configure,
 456         .dev_start            = igbvf_dev_start,
 457         .dev_stop             = igbvf_dev_stop,
 458         .dev_close            = igbvf_dev_close,
 459         .promiscuous_enable   = igbvf_promiscuous_enable,
 460         .promiscuous_disable  = igbvf_promiscuous_disable,
 461         .allmulticast_enable  = igbvf_allmulticast_enable,
 462         .allmulticast_disable = igbvf_allmulticast_disable,
 463         .link_update          = eth_igb_link_update,
 464         .stats_get            = eth_igbvf_stats_get,
 465         .xstats_get           = eth_igbvf_xstats_get,
 466         .xstats_get_names     = eth_igbvf_xstats_get_names,
 467         .stats_reset          = eth_igbvf_stats_reset,
 468         .xstats_reset         = eth_igbvf_stats_reset,
 469         .vlan_filter_set      = igbvf_vlan_filter_set,
 470         .dev_infos_get        = eth_igbvf_infos_get,
 471         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 472         .rx_queue_setup       = eth_igb_rx_queue_setup,
 473         .rx_queue_release     = eth_igb_rx_queue_release,
 474         .tx_queue_setup       = eth_igb_tx_queue_setup,
 475         .tx_queue_release     = eth_igb_tx_queue_release,
 476         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 477         .rxq_info_get         = igb_rxq_info_get,
 478         .txq_info_get         = igb_txq_info_get,
 479         .mac_addr_set         = igbvf_default_mac_addr_set,
 480         .get_reg              = igbvf_get_regs,
 481 };
 482
 483 /* store statistics names and its offset in stats structure */
 484 struct rte_igb_xstats_name_off {
 485         char name[RTE_ETH_XSTATS_NAME_SIZE];
 486         unsigned offset;
 487 };
 488
 489 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 490         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 491         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 492         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 493         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 494         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 495         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 496         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 497                 ecol)},
 498         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 499         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 500         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 501         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 502         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 503         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 504         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 505         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 506         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 507         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 508         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 509                 fcruc)},
 510         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 511         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 512         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 513         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 514         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 515                 prc1023)},
 516         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 517                 prc1522)},
 518         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 519         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 520         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 521         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 522         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 523         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 524         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 525         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 526         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 527         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 528         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 529         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 530         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 531         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 532         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 533         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 534         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 535         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 536                 ptc1023)},
 537         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 538                 ptc1522)},
 539         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 540         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 541         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 542         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 543         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 544         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 545         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 546
 547         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 548 };
 549
 550 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 551                 sizeof(rte_igb_stats_strings[0]))
 552
 553 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 554         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 555         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 556         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 557         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 558         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 559 };
 560
 561 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 562                 sizeof(rte_igbvf_stats_strings[0]))
 563
 564 /**
 565  * Atomically reads the link status information from global
 566  * structure rte_eth_dev.
 567  *
 568  * @param dev
 569  *   - Pointer to the structure rte_eth_dev to read from.
 570  *   - Pointer to the buffer to be saved with the link status.
 571  *
 572  * @return
 573  *   - On success, zero.
 574  *   - On failure, negative value.
 575  */
 576 static inline int
 577 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 578                                 struct rte_eth_link *link)
 579 {
 580         struct rte_eth_link *dst = link;
 581         struct rte_eth_link *src = &(dev->data->dev_link);
 582
 583         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 584                                         *(uint64_t *)src) == 0)
 585                 return -1;
 586
 587         return 0;
 588 }
 589
 590 /**
 591  * Atomically writes the link status information into global
 592  * structure rte_eth_dev.
 593  *
 594  * @param dev
 595  *   - Pointer to the structure rte_eth_dev to read from.
 596  *   - Pointer to the buffer to be saved with the link status.
 597  *
 598  * @return
 599  *   - On success, zero.
 600  *   - On failure, negative value.
 601  */
 602 static inline int
 603 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 604                                 struct rte_eth_link *link)
 605 {
 606         struct rte_eth_link *dst = &(dev->data->dev_link);
 607         struct rte_eth_link *src = link;
 608
 609         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 610                                         *(uint64_t *)src) == 0)
 611                 return -1;
 612
 613         return 0;
 614 }
 615
 616 static inline void
 617 igb_intr_enable(struct rte_eth_dev *dev)
 618 {
 619         struct e1000_interrupt *intr =
 620                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 621         struct e1000_hw *hw =
 622                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 623
 624         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 625         E1000_WRITE_FLUSH(hw);
 626 }
 627
 628 static void
 629 igb_intr_disable(struct e1000_hw *hw)
 630 {
 631         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 632         E1000_WRITE_FLUSH(hw);
 633 }
 634
 635 static inline void
 636 igbvf_intr_enable(struct rte_eth_dev *dev)
 637 {
 638         struct e1000_hw *hw =
 639                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 640
 641         /* only for mailbox */
 642         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 643         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 644         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 645         E1000_WRITE_FLUSH(hw);
 646 }
 647
 648 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 649 static void
 650 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 651 {
 652         uint32_t tmp = 0;
 653
 654         /* mailbox */
 655         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 656         tmp |= E1000_VTIVAR_VALID;
 657         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 658 }
 659
 660 static void
 661 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 662 {
 663         struct e1000_hw *hw =
 664                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 665
 666         /* Configure VF other cause ivar */
 667         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 668 }
 669
 670 static inline int32_t
 671 igb_pf_reset_hw(struct e1000_hw *hw)
 672 {
 673         uint32_t ctrl_ext;
 674         int32_t status;
 675
 676         status = e1000_reset_hw(hw);
 677
 678         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 679         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 680         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 681         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 682         E1000_WRITE_FLUSH(hw);
 683
 684         return status;
 685 }
 686
 687 static void
 688 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 689 {
 690         struct e1000_hw *hw =
 691                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 692
 693
 694         hw->vendor_id = pci_dev->id.vendor_id;
 695         hw->device_id = pci_dev->id.device_id;
 696         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 697         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 698
 699         e1000_set_mac_type(hw);
 700
 701         /* need to check if it is a vf device below */
 702 }
 703
 704 static int
 705 igb_reset_swfw_lock(struct e1000_hw *hw)
 706 {
 707         int ret_val;
 708
 709         /*
 710          * Do mac ops initialization manually here, since we will need
 711          * some function pointers set by this call.
 712          */
 713         ret_val = e1000_init_mac_params(hw);
 714         if (ret_val)
 715                 return ret_val;
 716
 717         /*
 718          * SMBI lock should not fail in this early stage. If this is the case,
 719          * it is due to an improper exit of the application.
 720          * So force the release of the faulty lock.
 721          */
 722         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 723                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 724         }
 725         e1000_put_hw_semaphore_generic(hw);
 726
 727         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 728                 uint16_t mask;
 729
 730                 /*
 731                  * Phy lock should not fail in this early stage. If this is the case,
 732                  * it is due to an improper exit of the application.
 733                  * So force the release of the faulty lock.
 734                  */
 735                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 736                 if (hw->bus.func > E1000_FUNC_1)
 737                         mask <<= 2;
 738                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 739                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 740                                     hw->bus.func);
 741                 }
 742                 hw->mac.ops.release_swfw_sync(hw, mask);
 743
 744                 /*
 745                  * This one is more tricky since it is common to all ports; but
 746                  * swfw_sync retries last long enough (1s) to be almost sure that if
 747                  * lock can not be taken it is due to an improper lock of the
 748                  * semaphore.
 749                  */
 750                 mask = E1000_SWFW_EEP_SM;
 751                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 752                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 753                 }
 754                 hw->mac.ops.release_swfw_sync(hw, mask);
 755         }
 756
 757         return E1000_SUCCESS;
 758 }
 759
 760 /* Remove all ntuple filters of the device */
 761 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 762 {
 763         struct e1000_filter_info *filter_info =
 764                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 765         struct e1000_5tuple_filter *p_5tuple;
 766         struct e1000_2tuple_filter *p_2tuple;
 767
 768         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 769                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 770                         p_5tuple, entries);
 771                         rte_free(p_5tuple);
 772         }
 773         filter_info->fivetuple_mask = 0;
 774         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 775                 TAILQ_REMOVE(&filter_info->twotuple_list,
 776                         p_2tuple, entries);
 777                         rte_free(p_2tuple);
 778         }
 779         filter_info->twotuple_mask = 0;
 780
 781         return 0;
 782 }
 783
 784 static int
 785 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 786 {
 787         int error = 0;
 788         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 789         struct e1000_hw *hw =
 790                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 791         struct e1000_vfta * shadow_vfta =
 792                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 793         struct e1000_filter_info *filter_info =
 794                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 795         struct e1000_adapter *adapter =
 796                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 797
 798         uint32_t ctrl_ext;
 799
 800         eth_dev->dev_ops = &eth_igb_ops;
 801         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 802         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 803         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 804
 805         /* for secondary processes, we don't initialise any further as primary
 806          * has already done this work. Only check we don't need a different
 807          * RX function */
 808         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 809                 if (eth_dev->data->scattered_rx)
 810                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 811                 return 0;
 812         }
 813
 814         rte_eth_copy_pci_info(eth_dev, pci_dev);
 815         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 816
 817         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 818
 819         igb_identify_hardware(eth_dev, pci_dev);
 820         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 821                 error = -EIO;
 822                 goto err_late;
 823         }
 824
 825         e1000_get_bus_info(hw);
 826
 827         /* Reset any pending lock */
 828         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 829                 error = -EIO;
 830                 goto err_late;
 831         }
 832
 833         /* Finish initialization */
 834         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 835                 error = -EIO;
 836                 goto err_late;
 837         }
 838
 839         hw->mac.autoneg = 1;
 840         hw->phy.autoneg_wait_to_complete = 0;
 841         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 842
 843         /* Copper options */
 844         if (hw->phy.media_type == e1000_media_type_copper) {
 845                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 846                 hw->phy.disable_polarity_correction = 0;
 847                 hw->phy.ms_type = e1000_ms_hw_default;
 848         }
 849
 850         /*
 851          * Start from a known state, this is important in reading the nvm
 852          * and mac from that.
 853          */
 854         igb_pf_reset_hw(hw);
 855
 856         /* Make sure we have a good EEPROM before we read from it */
 857         if (e1000_validate_nvm_checksum(hw) < 0) {
 858                 /*
 859                  * Some PCI-E parts fail the first check due to
 860                  * the link being in sleep state, call it again,
 861                  * if it fails a second time its a real issue.
 862                  */
 863                 if (e1000_validate_nvm_checksum(hw) < 0) {
 864                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 865                         error = -EIO;
 866                         goto err_late;
 867                 }
 868         }
 869
 870         /* Read the permanent MAC address out of the EEPROM */
 871         if (e1000_read_mac_addr(hw) != 0) {
 872                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 873                 error = -EIO;
 874                 goto err_late;
 875         }
 876
 877         /* Allocate memory for storing MAC addresses */
 878         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 879                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 880         if (eth_dev->data->mac_addrs == NULL) {
 881                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 882                                                 "store MAC addresses",
 883                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 884                 error = -ENOMEM;
 885                 goto err_late;
 886         }
 887
 888         /* Copy the permanent MAC address */
 889         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 890
 891         /* initialize the vfta */
 892         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 893
 894         /* Now initialize the hardware */
 895         if (igb_hardware_init(hw) != 0) {
 896                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 897                 rte_free(eth_dev->data->mac_addrs);
 898                 eth_dev->data->mac_addrs = NULL;
 899                 error = -ENODEV;
 900                 goto err_late;
 901         }
 902         hw->mac.get_link_status = 1;
 903         adapter->stopped = 0;
 904
 905         /* Indicate SOL/IDER usage */
 906         if (e1000_check_reset_block(hw) < 0) {
 907                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 908                                         "SOL/IDER session");
 909         }
 910
 911         /* initialize PF if max_vfs not zero */
 912         igb_pf_host_init(eth_dev);
 913
 914         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 915         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 916         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 917         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 918         E1000_WRITE_FLUSH(hw);
 919
 920         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 921                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 922                      pci_dev->id.device_id);
 923
 924         rte_intr_callback_register(&pci_dev->intr_handle,
 925                                    eth_igb_interrupt_handler,
 926                                    (void *)eth_dev);
 927
 928         /* enable uio/vfio intr/eventfd mapping */
 929         rte_intr_enable(&pci_dev->intr_handle);
 930
 931         /* enable support intr */
 932         igb_intr_enable(eth_dev);
 933
 934         /* initialize filter info */
 935         memset(filter_info, 0,
 936                sizeof(struct e1000_filter_info));
 937
 938         TAILQ_INIT(&filter_info->flex_list);
 939         TAILQ_INIT(&filter_info->twotuple_list);
 940         TAILQ_INIT(&filter_info->fivetuple_list);
 941
 942         return 0;
 943
 944 err_late:
 945         igb_hw_control_release(hw);
 946
 947         return error;
 948 }
 949
 950 static int
 951 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 952 {
 953         struct rte_pci_device *pci_dev;
 954         struct rte_intr_handle *intr_handle;
 955         struct e1000_hw *hw;
 956         struct e1000_adapter *adapter =
 957                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 958         struct e1000_filter_info *filter_info =
 959                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 960
 961         PMD_INIT_FUNC_TRACE();
 962
 963         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 964                 return -EPERM;
 965
 966         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 967         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 968         intr_handle = &pci_dev->intr_handle;
 969
 970         if (adapter->stopped == 0)
 971                 eth_igb_close(eth_dev);
 972
 973         eth_dev->dev_ops = NULL;
 974         eth_dev->rx_pkt_burst = NULL;
 975         eth_dev->tx_pkt_burst = NULL;
 976
 977         /* Reset any pending lock */
 978         igb_reset_swfw_lock(hw);
 979
 980         rte_free(eth_dev->data->mac_addrs);
 981         eth_dev->data->mac_addrs = NULL;
 982
 983         /* uninitialize PF if max_vfs not zero */
 984         igb_pf_host_uninit(eth_dev);
 985
 986         /* disable uio intr before callback unregister */
 987         rte_intr_disable(intr_handle);
 988         rte_intr_callback_unregister(intr_handle,
 989                                      eth_igb_interrupt_handler, eth_dev);
 990
 991         /* clear the SYN filter info */
 992         filter_info->syn_info = 0;
 993
 994         /* remove all ntuple filters of the device */
 995         igb_ntuple_filter_uninit(eth_dev);
 996
 997         return 0;
 998 }
 999
1000 /*
1001  * Virtual Function device init
1002  */
1003 static int
1004 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
1005 {
1006         struct rte_pci_device *pci_dev;
1007         struct rte_intr_handle *intr_handle;
1008         struct e1000_adapter *adapter =
1009                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1010         struct e1000_hw *hw =
1011                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1012         int diag;
1013         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
1014
1015         PMD_INIT_FUNC_TRACE();
1016
1017         eth_dev->dev_ops = &igbvf_eth_dev_ops;
1018         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
1019         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
1020         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
1021
1022         /* for secondary processes, we don't initialise any further as primary
1023          * has already done this work. Only check we don't need a different
1024          * RX function */
1025         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1026                 if (eth_dev->data->scattered_rx)
1027                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
1028                 return 0;
1029         }
1030
1031         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1032         rte_eth_copy_pci_info(eth_dev, pci_dev);
1033         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1034
1035         hw->device_id = pci_dev->id.device_id;
1036         hw->vendor_id = pci_dev->id.vendor_id;
1037         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1038         adapter->stopped = 0;
1039
1040         /* Initialize the shared code (base driver) */
1041         diag = e1000_setup_init_funcs(hw, TRUE);
1042         if (diag != 0) {
1043                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1044                         diag);
1045                 return -EIO;
1046         }
1047
1048         /* init_mailbox_params */
1049         hw->mbx.ops.init_params(hw);
1050
1051         /* Disable the interrupts for VF */
1052         igbvf_intr_disable(hw);
1053
1054         diag = hw->mac.ops.reset_hw(hw);
1055
1056         /* Allocate memory for storing MAC addresses */
1057         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1058                 hw->mac.rar_entry_count, 0);
1059         if (eth_dev->data->mac_addrs == NULL) {
1060                 PMD_INIT_LOG(ERR,
1061                         "Failed to allocate %d bytes needed to store MAC "
1062                         "addresses",
1063                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1064                 return -ENOMEM;
1065         }
1066
1067         /* Generate a random MAC address, if none was assigned by PF. */
1068         if (is_zero_ether_addr(perm_addr)) {
1069                 eth_random_addr(perm_addr->addr_bytes);
1070                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1071                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1072                              "%02x:%02x:%02x:%02x:%02x:%02x",
1073                              perm_addr->addr_bytes[0],
1074                              perm_addr->addr_bytes[1],
1075                              perm_addr->addr_bytes[2],
1076                              perm_addr->addr_bytes[3],
1077                              perm_addr->addr_bytes[4],
1078                              perm_addr->addr_bytes[5]);
1079         }
1080
1081         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1082         if (diag) {
1083                 rte_free(eth_dev->data->mac_addrs);
1084                 eth_dev->data->mac_addrs = NULL;
1085                 return diag;
1086         }
1087         /* Copy the permanent MAC address */
1088         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1089                         &eth_dev->data->mac_addrs[0]);
1090
1091         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1092                      "mac.type=%s",
1093                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1094                      pci_dev->id.device_id, "igb_mac_82576_vf");
1095
1096         intr_handle = &pci_dev->intr_handle;
1097         rte_intr_callback_register(intr_handle,
1098                                    eth_igbvf_interrupt_handler, eth_dev);
1099
1100         return 0;
1101 }
1102
1103 static int
1104 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1105 {
1106         struct e1000_adapter *adapter =
1107                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1108         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1109
1110         PMD_INIT_FUNC_TRACE();
1111
1112         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1113                 return -EPERM;
1114
1115         if (adapter->stopped == 0)
1116                 igbvf_dev_close(eth_dev);
1117
1118         eth_dev->dev_ops = NULL;
1119         eth_dev->rx_pkt_burst = NULL;
1120         eth_dev->tx_pkt_burst = NULL;
1121
1122         rte_free(eth_dev->data->mac_addrs);
1123         eth_dev->data->mac_addrs = NULL;
1124
1125         /* disable uio intr before callback unregister */
1126         rte_intr_disable(&pci_dev->intr_handle);
1127         rte_intr_callback_unregister(&pci_dev->intr_handle,
1128                                      eth_igbvf_interrupt_handler,
1129                                      (void *)eth_dev);
1130
1131         return 0;
1132 }
1133
1134 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1135         struct rte_pci_device *pci_dev)
1136 {
1137         return rte_eth_dev_pci_generic_probe(pci_dev,
1138                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1139 }
1140
1141 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1142 {
1143         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1144 }
1145
1146 static struct rte_pci_driver rte_igb_pmd = {
1147         .id_table = pci_id_igb_map,
1148         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1149         .probe = eth_igb_pci_probe,
1150         .remove = eth_igb_pci_remove,
1151 };
1152
1153
1154 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1155         struct rte_pci_device *pci_dev)
1156 {
1157         return rte_eth_dev_pci_generic_probe(pci_dev,
1158                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1159 }
1160
1161 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1162 {
1163         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1164 }
1165
1166 /*
1167  * virtual function driver struct
1168  */
1169 static struct rte_pci_driver rte_igbvf_pmd = {
1170         .id_table = pci_id_igbvf_map,
1171         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1172         .probe = eth_igbvf_pci_probe,
1173         .remove = eth_igbvf_pci_remove,
1174 };
1175
1176 static void
1177 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1178 {
1179         struct e1000_hw *hw =
1180                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1181         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1182         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1183         rctl |= E1000_RCTL_VFE;
1184         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1185 }
1186
1187 static int
1188 igb_check_mq_mode(struct rte_eth_dev *dev)
1189 {
1190         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1191         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1192         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1193         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1194
1195         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1196             tx_mq_mode == ETH_MQ_TX_DCB ||
1197             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1198                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1199                 return -EINVAL;
1200         }
1201         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1202                 /* Check multi-queue mode.
1203                  * To no break software we accept ETH_MQ_RX_NONE as this might
1204                  * be used to turn off VLAN filter.
1205                  */
1206
1207                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1208                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1209                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1210                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1211                 } else {
1212                         /* Only support one queue on VFs.
1213                          * RSS together with SRIOV is not supported.
1214                          */
1215                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1216                                         " wrong mq_mode rx %d.",
1217                                         rx_mq_mode);
1218                         return -EINVAL;
1219                 }
1220                 /* TX mode is not used here, so mode might be ignored.*/
1221                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1222                         /* SRIOV only works in VMDq enable mode */
1223                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1224                                         " TX mode %d is not supported. "
1225                                         " Driver will behave as %d mode.",
1226                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1227                 }
1228
1229                 /* check valid queue number */
1230                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1231                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1232                                         " only support one queue on VFs.");
1233                         return -EINVAL;
1234                 }
1235         } else {
1236                 /* To no break software that set invalid mode, only display
1237                  * warning if invalid mode is used.
1238                  */
1239                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1240                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1241                     rx_mq_mode != ETH_MQ_RX_RSS) {
1242                         /* RSS together with VMDq not supported*/
1243                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1244                                      rx_mq_mode);
1245                         return -EINVAL;
1246                 }
1247
1248                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1249                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1250                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1251                                         " Due to txmode is meaningless in this"
1252                                         " driver, just ignore.",
1253                                         tx_mq_mode);
1254                 }
1255         }
1256         return 0;
1257 }
1258
1259 static int
1260 eth_igb_configure(struct rte_eth_dev *dev)
1261 {
1262         struct e1000_interrupt *intr =
1263                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1264         int ret;
1265
1266         PMD_INIT_FUNC_TRACE();
1267
1268         /* multipe queue mode checking */
1269         ret  = igb_check_mq_mode(dev);
1270         if (ret != 0) {
1271                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1272                             ret);
1273                 return ret;
1274         }
1275
1276         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1277         PMD_INIT_FUNC_TRACE();
1278
1279         return 0;
1280 }
1281
1282 static int
1283 eth_igb_start(struct rte_eth_dev *dev)
1284 {
1285         struct e1000_hw *hw =
1286                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1287         struct e1000_adapter *adapter =
1288                 E1000_DEV_PRIVATE(dev->data->dev_private);
1289         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1290         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1291         int ret, mask;
1292         uint32_t intr_vector = 0;
1293         uint32_t ctrl_ext;
1294         uint32_t *speeds;
1295         int num_speeds;
1296         bool autoneg;
1297
1298         PMD_INIT_FUNC_TRACE();
1299
1300         /* disable uio/vfio intr/eventfd mapping */
1301         rte_intr_disable(intr_handle);
1302
1303         /* Power up the phy. Needed to make the link go Up */
1304         eth_igb_dev_set_link_up(dev);
1305
1306         /*
1307          * Packet Buffer Allocation (PBA)
1308          * Writing PBA sets the receive portion of the buffer
1309          * the remainder is used for the transmit buffer.
1310          */
1311         if (hw->mac.type == e1000_82575) {
1312                 uint32_t pba;
1313
1314                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1315                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1316         }
1317
1318         /* Put the address into the Receive Address Array */
1319         e1000_rar_set(hw, hw->mac.addr, 0);
1320
1321         /* Initialize the hardware */
1322         if (igb_hardware_init(hw)) {
1323                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1324                 return -EIO;
1325         }
1326         adapter->stopped = 0;
1327
1328         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1329
1330         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1331         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1332         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1333         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1334         E1000_WRITE_FLUSH(hw);
1335
1336         /* configure PF module if SRIOV enabled */
1337         igb_pf_host_configure(dev);
1338
1339         /* check and configure queue intr-vector mapping */
1340         if ((rte_intr_cap_multiple(intr_handle) ||
1341              !RTE_ETH_DEV_SRIOV(dev).active) &&
1342             dev->data->dev_conf.intr_conf.rxq != 0) {
1343                 intr_vector = dev->data->nb_rx_queues;
1344                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1345                         return -1;
1346         }
1347
1348         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1349                 intr_handle->intr_vec =
1350                         rte_zmalloc("intr_vec",
1351                                     dev->data->nb_rx_queues * sizeof(int), 0);
1352                 if (intr_handle->intr_vec == NULL) {
1353                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1354                                      " intr_vec", dev->data->nb_rx_queues);
1355                         return -ENOMEM;
1356                 }
1357         }
1358
1359         /* confiugre msix for rx interrupt */
1360         eth_igb_configure_msix_intr(dev);
1361
1362         /* Configure for OS presence */
1363         igb_init_manageability(hw);
1364
1365         eth_igb_tx_init(dev);
1366
1367         /* This can fail when allocating mbufs for descriptor rings */
1368         ret = eth_igb_rx_init(dev);
1369         if (ret) {
1370                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1371                 igb_dev_clear_queues(dev);
1372                 return ret;
1373         }
1374
1375         e1000_clear_hw_cntrs_base_generic(hw);
1376
1377         /*
1378          * VLAN Offload Settings
1379          */
1380         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1381                         ETH_VLAN_EXTEND_MASK;
1382         eth_igb_vlan_offload_set(dev, mask);
1383
1384         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1385                 /* Enable VLAN filter since VMDq always use VLAN filter */
1386                 igb_vmdq_vlan_hw_filter_enable(dev);
1387         }
1388
1389         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1390                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1391                 (hw->mac.type == e1000_i211)) {
1392                 /* Configure EITR with the maximum possible value (0xFFFF) */
1393                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1394         }
1395
1396         /* Setup link speed and duplex */
1397         speeds = &dev->data->dev_conf.link_speeds;
1398         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1399                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1400                 hw->mac.autoneg = 1;
1401         } else {
1402                 num_speeds = 0;
1403                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1404
1405                 /* Reset */
1406                 hw->phy.autoneg_advertised = 0;
1407
1408                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1409                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1410                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1411                         num_speeds = -1;
1412                         goto error_invalid_config;
1413                 }
1414                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1415                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1416                         num_speeds++;
1417                 }
1418                 if (*speeds & ETH_LINK_SPEED_10M) {
1419                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1420                         num_speeds++;
1421                 }
1422                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1423                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1424                         num_speeds++;
1425                 }
1426                 if (*speeds & ETH_LINK_SPEED_100M) {
1427                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1428                         num_speeds++;
1429                 }
1430                 if (*speeds & ETH_LINK_SPEED_1G) {
1431                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1432                         num_speeds++;
1433                 }
1434                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1435                         goto error_invalid_config;
1436
1437                 /* Set/reset the mac.autoneg based on the link speed,
1438                  * fixed or not
1439                  */
1440                 if (!autoneg) {
1441                         hw->mac.autoneg = 0;
1442                         hw->mac.forced_speed_duplex =
1443                                         hw->phy.autoneg_advertised;
1444                 } else {
1445                         hw->mac.autoneg = 1;
1446                 }
1447         }
1448
1449         e1000_setup_link(hw);
1450
1451         if (rte_intr_allow_others(intr_handle)) {
1452                 /* check if lsc interrupt is enabled */
1453                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1454                         eth_igb_lsc_interrupt_setup(dev);
1455         } else {
1456                 rte_intr_callback_unregister(intr_handle,
1457                                              eth_igb_interrupt_handler,
1458                                              (void *)dev);
1459                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1460                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1461                                      " no intr multiplex");
1462         }
1463
1464         /* check if rxq interrupt is enabled */
1465         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1466             rte_intr_dp_is_en(intr_handle))
1467                 eth_igb_rxq_interrupt_setup(dev);
1468
1469         /* enable uio/vfio intr/eventfd mapping */
1470         rte_intr_enable(intr_handle);
1471
1472         /* resume enabled intr since hw reset */
1473         igb_intr_enable(dev);
1474
1475         /* restore all types filter */
1476         igb_filter_restore(dev);
1477
1478         PMD_INIT_LOG(DEBUG, "<<");
1479
1480         return 0;
1481
1482 error_invalid_config:
1483         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1484                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1485         igb_dev_clear_queues(dev);
1486         return -EINVAL;
1487 }
1488
1489 /*********************************************************************
1490  *
1491  *  This routine disables all traffic on the adapter by issuing a
1492  *  global reset on the MAC.
1493  *
1494  **********************************************************************/
1495 static void
1496 eth_igb_stop(struct rte_eth_dev *dev)
1497 {
1498         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1499         struct e1000_filter_info *filter_info =
1500                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1501         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1502         struct rte_eth_link link;
1503         struct e1000_flex_filter *p_flex;
1504         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1505
1506         igb_intr_disable(hw);
1507
1508         /* disable intr eventfd mapping */
1509         rte_intr_disable(intr_handle);
1510
1511         igb_pf_reset_hw(hw);
1512         E1000_WRITE_REG(hw, E1000_WUC, 0);
1513
1514         /* Set bit for Go Link disconnect */
1515         if (hw->mac.type >= e1000_82580) {
1516                 uint32_t phpm_reg;
1517
1518                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1519                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1520                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1521         }
1522
1523         /* Power down the phy. Needed to make the link go Down */
1524         eth_igb_dev_set_link_down(dev);
1525
1526         igb_dev_clear_queues(dev);
1527
1528         /* clear the recorded link status */
1529         memset(&link, 0, sizeof(link));
1530         rte_igb_dev_atomic_write_link_status(dev, &link);
1531
1532         /* Remove all flex filters of the device */
1533         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1534                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1535                 rte_free(p_flex);
1536         }
1537         filter_info->flex_mask = 0;
1538
1539         if (!rte_intr_allow_others(intr_handle))
1540                 /* resume to the default handler */
1541                 rte_intr_callback_register(intr_handle,
1542                                            eth_igb_interrupt_handler,
1543                                            (void *)dev);
1544
1545         /* Clean datapath event and queue/vec mapping */
1546         rte_intr_efd_disable(intr_handle);
1547         if (intr_handle->intr_vec != NULL) {
1548                 rte_free(intr_handle->intr_vec);
1549                 intr_handle->intr_vec = NULL;
1550         }
1551 }
1552
1553 static int
1554 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1555 {
1556         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1557
1558         if (hw->phy.media_type == e1000_media_type_copper)
1559                 e1000_power_up_phy(hw);
1560         else
1561                 e1000_power_up_fiber_serdes_link(hw);
1562
1563         return 0;
1564 }
1565
1566 static int
1567 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1568 {
1569         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1570
1571         if (hw->phy.media_type == e1000_media_type_copper)
1572                 e1000_power_down_phy(hw);
1573         else
1574                 e1000_shutdown_fiber_serdes_link(hw);
1575
1576         return 0;
1577 }
1578
1579 static void
1580 eth_igb_close(struct rte_eth_dev *dev)
1581 {
1582         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1583         struct e1000_adapter *adapter =
1584                 E1000_DEV_PRIVATE(dev->data->dev_private);
1585         struct rte_eth_link link;
1586         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1587         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1588
1589         eth_igb_stop(dev);
1590         adapter->stopped = 1;
1591
1592         e1000_phy_hw_reset(hw);
1593         igb_release_manageability(hw);
1594         igb_hw_control_release(hw);
1595
1596         /* Clear bit for Go Link disconnect */
1597         if (hw->mac.type >= e1000_82580) {
1598                 uint32_t phpm_reg;
1599
1600                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1601                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1602                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1603         }
1604
1605         igb_dev_free_queues(dev);
1606
1607         if (intr_handle->intr_vec) {
1608                 rte_free(intr_handle->intr_vec);
1609                 intr_handle->intr_vec = NULL;
1610         }
1611
1612         memset(&link, 0, sizeof(link));
1613         rte_igb_dev_atomic_write_link_status(dev, &link);
1614 }
1615
1616 static int
1617 igb_get_rx_buffer_size(struct e1000_hw *hw)
1618 {
1619         uint32_t rx_buf_size;
1620         if (hw->mac.type == e1000_82576) {
1621                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1622         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1623                 /* PBS needs to be translated according to a lookup table */
1624                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1625                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1626                 rx_buf_size = (rx_buf_size << 10);
1627         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1628                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1629         } else {
1630                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1631         }
1632
1633         return rx_buf_size;
1634 }
1635
1636 /*********************************************************************
1637  *
1638  *  Initialize the hardware
1639  *
1640  **********************************************************************/
1641 static int
1642 igb_hardware_init(struct e1000_hw *hw)
1643 {
1644         uint32_t rx_buf_size;
1645         int diag;
1646
1647         /* Let the firmware know the OS is in control */
1648         igb_hw_control_acquire(hw);
1649
1650         /*
1651          * These parameters control the automatic generation (Tx) and
1652          * response (Rx) to Ethernet PAUSE frames.
1653          * - High water mark should allow for at least two standard size (1518)
1654          *   frames to be received after sending an XOFF.
1655          * - Low water mark works best when it is very near the high water mark.
1656          *   This allows the receiver to restart by sending XON when it has
1657          *   drained a bit. Here we use an arbitrary value of 1500 which will
1658          *   restart after one full frame is pulled from the buffer. There
1659          *   could be several smaller frames in the buffer and if so they will
1660          *   not trigger the XON until their total number reduces the buffer
1661          *   by 1500.
1662          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1663          */
1664         rx_buf_size = igb_get_rx_buffer_size(hw);
1665
1666         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1667         hw->fc.low_water = hw->fc.high_water - 1500;
1668         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1669         hw->fc.send_xon = 1;
1670
1671         /* Set Flow control, use the tunable location if sane */
1672         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1673                 hw->fc.requested_mode = igb_fc_setting;
1674         else
1675                 hw->fc.requested_mode = e1000_fc_none;
1676
1677         /* Issue a global reset */
1678         igb_pf_reset_hw(hw);
1679         E1000_WRITE_REG(hw, E1000_WUC, 0);
1680
1681         diag = e1000_init_hw(hw);
1682         if (diag < 0)
1683                 return diag;
1684
1685         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1686         e1000_get_phy_info(hw);
1687         e1000_check_for_link(hw);
1688
1689         return 0;
1690 }
1691
1692 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1693 static void
1694 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1695 {
1696         int pause_frames;
1697
1698         uint64_t old_gprc  = stats->gprc;
1699         uint64_t old_gptc  = stats->gptc;
1700         uint64_t old_tpr   = stats->tpr;
1701         uint64_t old_tpt   = stats->tpt;
1702         uint64_t old_rpthc = stats->rpthc;
1703         uint64_t old_hgptc = stats->hgptc;
1704
1705         if(hw->phy.media_type == e1000_media_type_copper ||
1706             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1707                 stats->symerrs +=
1708                     E1000_READ_REG(hw,E1000_SYMERRS);
1709                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1710         }
1711
1712         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1713         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1714         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1715         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1716
1717         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1718         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1719         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1720         stats->dc += E1000_READ_REG(hw, E1000_DC);
1721         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1722         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1723         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1724         /*
1725         ** For watchdog management we need to know if we have been
1726         ** paused during the last interval, so capture that here.
1727         */
1728         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1729         stats->xoffrxc += pause_frames;
1730         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1731         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1732         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1733         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1734         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1735         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1736         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1737         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1738         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1739         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1740         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1741         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1742
1743         /* For the 64-bit byte counters the low dword must be read first. */
1744         /* Both registers clear on the read of the high dword */
1745
1746         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1747         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1748         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1749         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1750         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1751         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1752         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1753
1754         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1755         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1756         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1757         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1758         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1759
1760         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1761         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1762
1763         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1764         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1765         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1766         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1767         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1768         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1769
1770         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1771         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1772         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1773         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1774         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1775         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1776         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1777         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1778
1779         /* Interrupt Counts */
1780
1781         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1782         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1783         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1784         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1785         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1786         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1787         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1788         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1789         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1790
1791         /* Host to Card Statistics */
1792
1793         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1794         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1795         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1796         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1797         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1798         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1799         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1800         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1801         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1802         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1803         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1804         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1805         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1806         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1807         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1808         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1809
1810         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1811         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1812         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1813         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1814         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1815         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1816 }
1817
1818 static void
1819 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1820 {
1821         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1822         struct e1000_hw_stats *stats =
1823                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1824
1825         igb_read_stats_registers(hw, stats);
1826
1827         if (rte_stats == NULL)
1828                 return;
1829
1830         /* Rx Errors */
1831         rte_stats->imissed = stats->mpc;
1832         rte_stats->ierrors = stats->crcerrs +
1833                              stats->rlec + stats->ruc + stats->roc +
1834                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1835
1836         /* Tx Errors */
1837         rte_stats->oerrors = stats->ecol + stats->latecol;
1838
1839         rte_stats->ipackets = stats->gprc;
1840         rte_stats->opackets = stats->gptc;
1841         rte_stats->ibytes   = stats->gorc;
1842         rte_stats->obytes   = stats->gotc;
1843 }
1844
1845 static void
1846 eth_igb_stats_reset(struct rte_eth_dev *dev)
1847 {
1848         struct e1000_hw_stats *hw_stats =
1849                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1850
1851         /* HW registers are cleared on read */
1852         eth_igb_stats_get(dev, NULL);
1853
1854         /* Reset software totals */
1855         memset(hw_stats, 0, sizeof(*hw_stats));
1856 }
1857
1858 static void
1859 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1860 {
1861         struct e1000_hw_stats *stats =
1862                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1863
1864         /* HW registers are cleared on read */
1865         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1866
1867         /* Reset software totals */
1868         memset(stats, 0, sizeof(*stats));
1869 }
1870
1871 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1872         struct rte_eth_xstat_name *xstats_names,
1873         __rte_unused unsigned int size)
1874 {
1875         unsigned i;
1876
1877         if (xstats_names == NULL)
1878                 return IGB_NB_XSTATS;
1879
1880         /* Note: limit checked in rte_eth_xstats_names() */
1881
1882         for (i = 0; i < IGB_NB_XSTATS; i++) {
1883                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1884                          "%s", rte_igb_stats_strings[i].name);
1885         }
1886
1887         return IGB_NB_XSTATS;
1888 }
1889
1890 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1891                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1892                 unsigned int limit)
1893 {
1894         unsigned int i;
1895
1896         if (!ids) {
1897                 if (xstats_names == NULL)
1898                         return IGB_NB_XSTATS;
1899
1900                 for (i = 0; i < IGB_NB_XSTATS; i++)
1901                         snprintf(xstats_names[i].name,
1902                                         sizeof(xstats_names[i].name),
1903                                         "%s", rte_igb_stats_strings[i].name);
1904
1905                 return IGB_NB_XSTATS;
1906
1907         } else {
1908                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1909
1910                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1911                                 IGB_NB_XSTATS);
1912
1913                 for (i = 0; i < limit; i++) {
1914                         if (ids[i] >= IGB_NB_XSTATS) {
1915                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1916                                 return -1;
1917                         }
1918                         strcpy(xstats_names[i].name,
1919                                         xstats_names_copy[ids[i]].name);
1920                 }
1921                 return limit;
1922         }
1923 }
1924
1925 static int
1926 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1927                    unsigned n)
1928 {
1929         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930         struct e1000_hw_stats *hw_stats =
1931                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1932         unsigned i;
1933
1934         if (n < IGB_NB_XSTATS)
1935                 return IGB_NB_XSTATS;
1936
1937         igb_read_stats_registers(hw, hw_stats);
1938
1939         /* If this is a reset xstats is NULL, and we have cleared the
1940          * registers by reading them.
1941          */
1942         if (!xstats)
1943                 return 0;
1944
1945         /* Extended stats */
1946         for (i = 0; i < IGB_NB_XSTATS; i++) {
1947                 xstats[i].id = i;
1948                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1949                         rte_igb_stats_strings[i].offset);
1950         }
1951
1952         return IGB_NB_XSTATS;
1953 }
1954
1955 static int
1956 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1957                 uint64_t *values, unsigned int n)
1958 {
1959         unsigned int i;
1960
1961         if (!ids) {
1962                 struct e1000_hw *hw =
1963                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1964                 struct e1000_hw_stats *hw_stats =
1965                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1966
1967                 if (n < IGB_NB_XSTATS)
1968                         return IGB_NB_XSTATS;
1969
1970                 igb_read_stats_registers(hw, hw_stats);
1971
1972                 /* If this is a reset xstats is NULL, and we have cleared the
1973                  * registers by reading them.
1974                  */
1975                 if (!values)
1976                         return 0;
1977
1978                 /* Extended stats */
1979                 for (i = 0; i < IGB_NB_XSTATS; i++)
1980                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1981                                         rte_igb_stats_strings[i].offset);
1982
1983                 return IGB_NB_XSTATS;
1984
1985         } else {
1986                 uint64_t values_copy[IGB_NB_XSTATS];
1987
1988                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1989                                 IGB_NB_XSTATS);
1990
1991                 for (i = 0; i < n; i++) {
1992                         if (ids[i] >= IGB_NB_XSTATS) {
1993                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1994                                 return -1;
1995                         }
1996                         values[i] = values_copy[ids[i]];
1997                 }
1998                 return n;
1999         }
2000 }
2001
2002 static void
2003 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2004 {
2005         /* Good Rx packets, include VF loopback */
2006         UPDATE_VF_STAT(E1000_VFGPRC,
2007             hw_stats->last_gprc, hw_stats->gprc);
2008
2009         /* Good Rx octets, include VF loopback */
2010         UPDATE_VF_STAT(E1000_VFGORC,
2011             hw_stats->last_gorc, hw_stats->gorc);
2012
2013         /* Good Tx packets, include VF loopback */
2014         UPDATE_VF_STAT(E1000_VFGPTC,
2015             hw_stats->last_gptc, hw_stats->gptc);
2016
2017         /* Good Tx octets, include VF loopback */
2018         UPDATE_VF_STAT(E1000_VFGOTC,
2019             hw_stats->last_gotc, hw_stats->gotc);
2020
2021         /* Rx Multicst packets */
2022         UPDATE_VF_STAT(E1000_VFMPRC,
2023             hw_stats->last_mprc, hw_stats->mprc);
2024
2025         /* Good Rx loopback packets */
2026         UPDATE_VF_STAT(E1000_VFGPRLBC,
2027             hw_stats->last_gprlbc, hw_stats->gprlbc);
2028
2029         /* Good Rx loopback octets */
2030         UPDATE_VF_STAT(E1000_VFGORLBC,
2031             hw_stats->last_gorlbc, hw_stats->gorlbc);
2032
2033         /* Good Tx loopback packets */
2034         UPDATE_VF_STAT(E1000_VFGPTLBC,
2035             hw_stats->last_gptlbc, hw_stats->gptlbc);
2036
2037         /* Good Tx loopback octets */
2038         UPDATE_VF_STAT(E1000_VFGOTLBC,
2039             hw_stats->last_gotlbc, hw_stats->gotlbc);
2040 }
2041
2042 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2043                                      struct rte_eth_xstat_name *xstats_names,
2044                                      __rte_unused unsigned limit)
2045 {
2046         unsigned i;
2047
2048         if (xstats_names != NULL)
2049                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2050                         snprintf(xstats_names[i].name,
2051                                 sizeof(xstats_names[i].name), "%s",
2052                                 rte_igbvf_stats_strings[i].name);
2053                 }
2054         return IGBVF_NB_XSTATS;
2055 }
2056
2057 static int
2058 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2059                      unsigned n)
2060 {
2061         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2062         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2063                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2064         unsigned i;
2065
2066         if (n < IGBVF_NB_XSTATS)
2067                 return IGBVF_NB_XSTATS;
2068
2069         igbvf_read_stats_registers(hw, hw_stats);
2070
2071         if (!xstats)
2072                 return 0;
2073
2074         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2075                 xstats[i].id = i;
2076                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2077                         rte_igbvf_stats_strings[i].offset);
2078         }
2079
2080         return IGBVF_NB_XSTATS;
2081 }
2082
2083 static void
2084 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2085 {
2086         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2088                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2089
2090         igbvf_read_stats_registers(hw, hw_stats);
2091
2092         if (rte_stats == NULL)
2093                 return;
2094
2095         rte_stats->ipackets = hw_stats->gprc;
2096         rte_stats->ibytes = hw_stats->gorc;
2097         rte_stats->opackets = hw_stats->gptc;
2098         rte_stats->obytes = hw_stats->gotc;
2099 }
2100
2101 static void
2102 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2103 {
2104         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2105                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2106
2107         /* Sync HW register to the last stats */
2108         eth_igbvf_stats_get(dev, NULL);
2109
2110         /* reset HW current stats*/
2111         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2112                offsetof(struct e1000_vf_stats, gprc));
2113 }
2114
2115 static int
2116 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2117                        size_t fw_size)
2118 {
2119         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120         struct e1000_fw_version fw;
2121         int ret;
2122
2123         e1000_get_fw_version(hw, &fw);
2124
2125         switch (hw->mac.type) {
2126         case e1000_i210:
2127         case e1000_i211:
2128                 if (!(e1000_get_flash_presence_i210(hw))) {
2129                         ret = snprintf(fw_version, fw_size,
2130                                  "%2d.%2d-%d",
2131                                  fw.invm_major, fw.invm_minor,
2132                                  fw.invm_img_type);
2133                         break;
2134                 }
2135                 /* fall through */
2136         default:
2137                 /* if option rom is valid, display its version too */
2138                 if (fw.or_valid) {
2139                         ret = snprintf(fw_version, fw_size,
2140                                  "%d.%d, 0x%08x, %d.%d.%d",
2141                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2142                                  fw.or_major, fw.or_build, fw.or_patch);
2143                 /* no option rom */
2144                 } else {
2145                         if (fw.etrack_id != 0X0000) {
2146                                 ret = snprintf(fw_version, fw_size,
2147                                          "%d.%d, 0x%08x",
2148                                          fw.eep_major, fw.eep_minor,
2149                                          fw.etrack_id);
2150                         } else {
2151                                 ret = snprintf(fw_version, fw_size,
2152                                          "%d.%d.%d",
2153                                          fw.eep_major, fw.eep_minor,
2154                                          fw.eep_build);
2155                         }
2156                 }
2157                 break;
2158         }
2159
2160         ret += 1; /* add the size of '\0' */
2161         if (fw_size < (u32)ret)
2162                 return ret;
2163         else
2164                 return 0;
2165 }
2166
2167 static void
2168 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2169 {
2170         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2171
2172         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2173         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2174         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2175         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2176         dev_info->rx_offload_capa =
2177                 DEV_RX_OFFLOAD_VLAN_STRIP |
2178                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2179                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2180                 DEV_RX_OFFLOAD_TCP_CKSUM;
2181         dev_info->tx_offload_capa =
2182                 DEV_TX_OFFLOAD_VLAN_INSERT |
2183                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2184                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2185                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2186                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2187                 DEV_TX_OFFLOAD_TCP_TSO;
2188
2189         switch (hw->mac.type) {
2190         case e1000_82575:
2191                 dev_info->max_rx_queues = 4;
2192                 dev_info->max_tx_queues = 4;
2193                 dev_info->max_vmdq_pools = 0;
2194                 break;
2195
2196         case e1000_82576:
2197                 dev_info->max_rx_queues = 16;
2198                 dev_info->max_tx_queues = 16;
2199                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2200                 dev_info->vmdq_queue_num = 16;
2201                 break;
2202
2203         case e1000_82580:
2204                 dev_info->max_rx_queues = 8;
2205                 dev_info->max_tx_queues = 8;
2206                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2207                 dev_info->vmdq_queue_num = 8;
2208                 break;
2209
2210         case e1000_i350:
2211                 dev_info->max_rx_queues = 8;
2212                 dev_info->max_tx_queues = 8;
2213                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2214                 dev_info->vmdq_queue_num = 8;
2215                 break;
2216
2217         case e1000_i354:
2218                 dev_info->max_rx_queues = 8;
2219                 dev_info->max_tx_queues = 8;
2220                 break;
2221
2222         case e1000_i210:
2223                 dev_info->max_rx_queues = 4;
2224                 dev_info->max_tx_queues = 4;
2225                 dev_info->max_vmdq_pools = 0;
2226                 break;
2227
2228         case e1000_i211:
2229                 dev_info->max_rx_queues = 2;
2230                 dev_info->max_tx_queues = 2;
2231                 dev_info->max_vmdq_pools = 0;
2232                 break;
2233
2234         default:
2235                 /* Should not happen */
2236                 break;
2237         }
2238         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2239         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2240         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2241
2242         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2243                 .rx_thresh = {
2244                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2245                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2246                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2247                 },
2248                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2249                 .rx_drop_en = 0,
2250         };
2251
2252         dev_info->default_txconf = (struct rte_eth_txconf) {
2253                 .tx_thresh = {
2254                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2255                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2256                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2257                 },
2258                 .txq_flags = 0,
2259         };
2260
2261         dev_info->rx_desc_lim = rx_desc_lim;
2262         dev_info->tx_desc_lim = tx_desc_lim;
2263
2264         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2265                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2266                         ETH_LINK_SPEED_1G;
2267 }
2268
2269 static const uint32_t *
2270 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2271 {
2272         static const uint32_t ptypes[] = {
2273                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2274                 RTE_PTYPE_L2_ETHER,
2275                 RTE_PTYPE_L3_IPV4,
2276                 RTE_PTYPE_L3_IPV4_EXT,
2277                 RTE_PTYPE_L3_IPV6,
2278                 RTE_PTYPE_L3_IPV6_EXT,
2279                 RTE_PTYPE_L4_TCP,
2280                 RTE_PTYPE_L4_UDP,
2281                 RTE_PTYPE_L4_SCTP,
2282                 RTE_PTYPE_TUNNEL_IP,
2283                 RTE_PTYPE_INNER_L3_IPV6,
2284                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2285                 RTE_PTYPE_INNER_L4_TCP,
2286                 RTE_PTYPE_INNER_L4_UDP,
2287                 RTE_PTYPE_UNKNOWN
2288         };
2289
2290         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2291             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2292                 return ptypes;
2293         return NULL;
2294 }
2295
2296 static void
2297 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2298 {
2299         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2300
2301         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2302         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2303         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2304         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2305         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2306                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2307                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2308                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2309         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2310                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2311                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2312                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2313                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2314                                 DEV_TX_OFFLOAD_TCP_TSO;
2315         switch (hw->mac.type) {
2316         case e1000_vfadapt:
2317                 dev_info->max_rx_queues = 2;
2318                 dev_info->max_tx_queues = 2;
2319                 break;
2320         case e1000_vfadapt_i350:
2321                 dev_info->max_rx_queues = 1;
2322                 dev_info->max_tx_queues = 1;
2323                 break;
2324         default:
2325                 /* Should not happen */
2326                 break;
2327         }
2328
2329         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2330                 .rx_thresh = {
2331                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2332                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2333                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2334                 },
2335                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2336                 .rx_drop_en = 0,
2337         };
2338
2339         dev_info->default_txconf = (struct rte_eth_txconf) {
2340                 .tx_thresh = {
2341                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2342                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2343                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2344                 },
2345                 .txq_flags = 0,
2346         };
2347
2348         dev_info->rx_desc_lim = rx_desc_lim;
2349         dev_info->tx_desc_lim = tx_desc_lim;
2350 }
2351
2352 /* return 0 means link status changed, -1 means not changed */
2353 static int
2354 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2355 {
2356         struct e1000_hw *hw =
2357                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2358         struct rte_eth_link link, old;
2359         int link_check, count;
2360
2361         link_check = 0;
2362         hw->mac.get_link_status = 1;
2363
2364         /* possible wait-to-complete in up to 9 seconds */
2365         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2366                 /* Read the real link status */
2367                 switch (hw->phy.media_type) {
2368                 case e1000_media_type_copper:
2369                         /* Do the work to read phy */
2370                         e1000_check_for_link(hw);
2371                         link_check = !hw->mac.get_link_status;
2372                         break;
2373
2374                 case e1000_media_type_fiber:
2375                         e1000_check_for_link(hw);
2376                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2377                                       E1000_STATUS_LU);
2378                         break;
2379
2380                 case e1000_media_type_internal_serdes:
2381                         e1000_check_for_link(hw);
2382                         link_check = hw->mac.serdes_has_link;
2383                         break;
2384
2385                 /* VF device is type_unknown */
2386                 case e1000_media_type_unknown:
2387                         eth_igbvf_link_update(hw);
2388                         link_check = !hw->mac.get_link_status;
2389                         break;
2390
2391                 default:
2392                         break;
2393                 }
2394                 if (link_check || wait_to_complete == 0)
2395                         break;
2396                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2397         }
2398         memset(&link, 0, sizeof(link));
2399         rte_igb_dev_atomic_read_link_status(dev, &link);
2400         old = link;
2401
2402         /* Now we check if a transition has happened */
2403         if (link_check) {
2404                 uint16_t duplex, speed;
2405                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2406                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2407                                 ETH_LINK_FULL_DUPLEX :
2408                                 ETH_LINK_HALF_DUPLEX;
2409                 link.link_speed = speed;
2410                 link.link_status = ETH_LINK_UP;
2411                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2412                                 ETH_LINK_SPEED_FIXED);
2413         } else if (!link_check) {
2414                 link.link_speed = 0;
2415                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2416                 link.link_status = ETH_LINK_DOWN;
2417                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2418         }
2419         rte_igb_dev_atomic_write_link_status(dev, &link);
2420
2421         /* not changed */
2422         if (old.link_status == link.link_status)
2423                 return -1;
2424
2425         /* changed */
2426         return 0;
2427 }
2428
2429 /*
2430  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2431  * For ASF and Pass Through versions of f/w this means
2432  * that the driver is loaded.
2433  */
2434 static void
2435 igb_hw_control_acquire(struct e1000_hw *hw)
2436 {
2437         uint32_t ctrl_ext;
2438
2439         /* Let firmware know the driver has taken over */
2440         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2441         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2442 }
2443
2444 /*
2445  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2446  * For ASF and Pass Through versions of f/w this means that the
2447  * driver is no longer loaded.
2448  */
2449 static void
2450 igb_hw_control_release(struct e1000_hw *hw)
2451 {
2452         uint32_t ctrl_ext;
2453
2454         /* Let firmware taken over control of h/w */
2455         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2456         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2457                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2458 }
2459
2460 /*
2461  * Bit of a misnomer, what this really means is
2462  * to enable OS management of the system... aka
2463  * to disable special hardware management features.
2464  */
2465 static void
2466 igb_init_manageability(struct e1000_hw *hw)
2467 {
2468         if (e1000_enable_mng_pass_thru(hw)) {
2469                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2470                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2471
2472                 /* disable hardware interception of ARP */
2473                 manc &= ~(E1000_MANC_ARP_EN);
2474
2475                 /* enable receiving management packets to the host */
2476                 manc |= E1000_MANC_EN_MNG2HOST;
2477                 manc2h |= 1 << 5;  /* Mng Port 623 */
2478                 manc2h |= 1 << 6;  /* Mng Port 664 */
2479                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2480                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2481         }
2482 }
2483
2484 static void
2485 igb_release_manageability(struct e1000_hw *hw)
2486 {
2487         if (e1000_enable_mng_pass_thru(hw)) {
2488                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2489
2490                 manc |= E1000_MANC_ARP_EN;
2491                 manc &= ~E1000_MANC_EN_MNG2HOST;
2492
2493                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2494         }
2495 }
2496
2497 static void
2498 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2499 {
2500         struct e1000_hw *hw =
2501                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2502         uint32_t rctl;
2503
2504         rctl = E1000_READ_REG(hw, E1000_RCTL);
2505         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2506         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2507 }
2508
2509 static void
2510 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2511 {
2512         struct e1000_hw *hw =
2513                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2514         uint32_t rctl;
2515
2516         rctl = E1000_READ_REG(hw, E1000_RCTL);
2517         rctl &= (~E1000_RCTL_UPE);
2518         if (dev->data->all_multicast == 1)
2519                 rctl |= E1000_RCTL_MPE;
2520         else
2521                 rctl &= (~E1000_RCTL_MPE);
2522         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2523 }
2524
2525 static void
2526 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2527 {
2528         struct e1000_hw *hw =
2529                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2530         uint32_t rctl;
2531
2532         rctl = E1000_READ_REG(hw, E1000_RCTL);
2533         rctl |= E1000_RCTL_MPE;
2534         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2535 }
2536
2537 static void
2538 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2539 {
2540         struct e1000_hw *hw =
2541                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2542         uint32_t rctl;
2543
2544         if (dev->data->promiscuous == 1)
2545                 return; /* must remain in all_multicast mode */
2546         rctl = E1000_READ_REG(hw, E1000_RCTL);
2547         rctl &= (~E1000_RCTL_MPE);
2548         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2549 }
2550
2551 static int
2552 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2553 {
2554         struct e1000_hw *hw =
2555                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2556         struct e1000_vfta * shadow_vfta =
2557                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2558         uint32_t vfta;
2559         uint32_t vid_idx;
2560         uint32_t vid_bit;
2561
2562         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2563                               E1000_VFTA_ENTRY_MASK);
2564         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2565         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2566         if (on)
2567                 vfta |= vid_bit;
2568         else
2569                 vfta &= ~vid_bit;
2570         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2571
2572         /* update local VFTA copy */
2573         shadow_vfta->vfta[vid_idx] = vfta;
2574
2575         return 0;
2576 }
2577
2578 static int
2579 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2580                       enum rte_vlan_type vlan_type,
2581                       uint16_t tpid)
2582 {
2583         struct e1000_hw *hw =
2584                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2585         uint32_t reg, qinq;
2586
2587         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2588         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2589
2590         /* only outer TPID of double VLAN can be configured*/
2591         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2592                 reg = E1000_READ_REG(hw, E1000_VET);
2593                 reg = (reg & (~E1000_VET_VET_EXT)) |
2594                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2595                 E1000_WRITE_REG(hw, E1000_VET, reg);
2596
2597                 return 0;
2598         }
2599
2600         /* all other TPID values are read-only*/
2601         PMD_DRV_LOG(ERR, "Not supported");
2602
2603         return -ENOTSUP;
2604 }
2605
2606 static void
2607 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2608 {
2609         struct e1000_hw *hw =
2610                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2611         uint32_t reg;
2612
2613         /* Filter Table Disable */
2614         reg = E1000_READ_REG(hw, E1000_RCTL);
2615         reg &= ~E1000_RCTL_CFIEN;
2616         reg &= ~E1000_RCTL_VFE;
2617         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2618 }
2619
2620 static void
2621 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2622 {
2623         struct e1000_hw *hw =
2624                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2625         struct e1000_vfta * shadow_vfta =
2626                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2627         uint32_t reg;
2628         int i;
2629
2630         /* Filter Table Enable, CFI not used for packet acceptance */
2631         reg = E1000_READ_REG(hw, E1000_RCTL);
2632         reg &= ~E1000_RCTL_CFIEN;
2633         reg |= E1000_RCTL_VFE;
2634         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2635
2636         /* restore VFTA table */
2637         for (i = 0; i < IGB_VFTA_SIZE; i++)
2638                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2639 }
2640
2641 static void
2642 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2643 {
2644         struct e1000_hw *hw =
2645                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2646         uint32_t reg;
2647
2648         /* VLAN Mode Disable */
2649         reg = E1000_READ_REG(hw, E1000_CTRL);
2650         reg &= ~E1000_CTRL_VME;
2651         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2652 }
2653
2654 static void
2655 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2656 {
2657         struct e1000_hw *hw =
2658                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2659         uint32_t reg;
2660
2661         /* VLAN Mode Enable */
2662         reg = E1000_READ_REG(hw, E1000_CTRL);
2663         reg |= E1000_CTRL_VME;
2664         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2665 }
2666
2667 static void
2668 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2669 {
2670         struct e1000_hw *hw =
2671                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2672         uint32_t reg;
2673
2674         /* CTRL_EXT: Extended VLAN */
2675         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2676         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2677         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2678
2679         /* Update maximum packet length */
2680         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2681                 E1000_WRITE_REG(hw, E1000_RLPML,
2682                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2683                                                 VLAN_TAG_SIZE);
2684 }
2685
2686 static void
2687 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2688 {
2689         struct e1000_hw *hw =
2690                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2691         uint32_t reg;
2692
2693         /* CTRL_EXT: Extended VLAN */
2694         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2695         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2696         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2697
2698         /* Update maximum packet length */
2699         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2700                 E1000_WRITE_REG(hw, E1000_RLPML,
2701                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2702                                                 2 * VLAN_TAG_SIZE);
2703 }
2704
2705 static void
2706 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2707 {
2708         if(mask & ETH_VLAN_STRIP_MASK){
2709                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2710                         igb_vlan_hw_strip_enable(dev);
2711                 else
2712                         igb_vlan_hw_strip_disable(dev);
2713         }
2714
2715         if(mask & ETH_VLAN_FILTER_MASK){
2716                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2717                         igb_vlan_hw_filter_enable(dev);
2718                 else
2719                         igb_vlan_hw_filter_disable(dev);
2720         }
2721
2722         if(mask & ETH_VLAN_EXTEND_MASK){
2723                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2724                         igb_vlan_hw_extend_enable(dev);
2725                 else
2726                         igb_vlan_hw_extend_disable(dev);
2727         }
2728 }
2729
2730
2731 /**
2732  * It enables the interrupt mask and then enable the interrupt.
2733  *
2734  * @param dev
2735  *  Pointer to struct rte_eth_dev.
2736  *
2737  * @return
2738  *  - On success, zero.
2739  *  - On failure, a negative value.
2740  */
2741 static int
2742 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2743 {
2744         struct e1000_interrupt *intr =
2745                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2746
2747         intr->mask |= E1000_ICR_LSC;
2748
2749         return 0;
2750 }
2751
2752 /* It clears the interrupt causes and enables the interrupt.
2753  * It will be called once only during nic initialized.
2754  *
2755  * @param dev
2756  *  Pointer to struct rte_eth_dev.
2757  *
2758  * @return
2759  *  - On success, zero.
2760  *  - On failure, a negative value.
2761  */
2762 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2763 {
2764         uint32_t mask, regval;
2765         struct e1000_hw *hw =
2766                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2767         struct rte_eth_dev_info dev_info;
2768
2769         memset(&dev_info, 0, sizeof(dev_info));
2770         eth_igb_infos_get(dev, &dev_info);
2771
2772         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2773         regval = E1000_READ_REG(hw, E1000_EIMS);
2774         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2775
2776         return 0;
2777 }
2778
2779 /*
2780  * It reads ICR and gets interrupt causes, check it and set a bit flag
2781  * to update link status.
2782  *
2783  * @param dev
2784  *  Pointer to struct rte_eth_dev.
2785  *
2786  * @return
2787  *  - On success, zero.
2788  *  - On failure, a negative value.
2789  */
2790 static int
2791 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2792 {
2793         uint32_t icr;
2794         struct e1000_hw *hw =
2795                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2796         struct e1000_interrupt *intr =
2797                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2798
2799         igb_intr_disable(hw);
2800
2801         /* read-on-clear nic registers here */
2802         icr = E1000_READ_REG(hw, E1000_ICR);
2803
2804         intr->flags = 0;
2805         if (icr & E1000_ICR_LSC) {
2806                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2807         }
2808
2809         if (icr & E1000_ICR_VMMB)
2810                 intr->flags |= E1000_FLAG_MAILBOX;
2811
2812         return 0;
2813 }
2814
2815 /*
2816  * It executes link_update after knowing an interrupt is prsent.
2817  *
2818  * @param dev
2819  *  Pointer to struct rte_eth_dev.
2820  *
2821  * @return
2822  *  - On success, zero.
2823  *  - On failure, a negative value.
2824  */
2825 static int
2826 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2827                          struct rte_intr_handle *intr_handle)
2828 {
2829         struct e1000_hw *hw =
2830                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2831         struct e1000_interrupt *intr =
2832                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2833         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2834         uint32_t tctl, rctl;
2835         struct rte_eth_link link;
2836         int ret;
2837
2838         if (intr->flags & E1000_FLAG_MAILBOX) {
2839                 igb_pf_mbx_process(dev);
2840                 intr->flags &= ~E1000_FLAG_MAILBOX;
2841         }
2842
2843         igb_intr_enable(dev);
2844         rte_intr_enable(intr_handle);
2845
2846         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2847                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2848
2849                 /* set get_link_status to check register later */
2850                 hw->mac.get_link_status = 1;
2851                 ret = eth_igb_link_update(dev, 0);
2852
2853                 /* check if link has changed */
2854                 if (ret < 0)
2855                         return 0;
2856
2857                 memset(&link, 0, sizeof(link));
2858                 rte_igb_dev_atomic_read_link_status(dev, &link);
2859                 if (link.link_status) {
2860                         PMD_INIT_LOG(INFO,
2861                                      " Port %d: Link Up - speed %u Mbps - %s",
2862                                      dev->data->port_id,
2863                                      (unsigned)link.link_speed,
2864                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2865                                      "full-duplex" : "half-duplex");
2866                 } else {
2867                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2868                                      dev->data->port_id);
2869                 }
2870
2871                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2872                              pci_dev->addr.domain,
2873                              pci_dev->addr.bus,
2874                              pci_dev->addr.devid,
2875                              pci_dev->addr.function);
2876                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2877                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2878                 if (link.link_status) {
2879                         /* enable Tx/Rx */
2880                         tctl |= E1000_TCTL_EN;
2881                         rctl |= E1000_RCTL_EN;
2882                 } else {
2883                         /* disable Tx/Rx */
2884                         tctl &= ~E1000_TCTL_EN;
2885                         rctl &= ~E1000_RCTL_EN;
2886                 }
2887                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2888                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2889                 E1000_WRITE_FLUSH(hw);
2890                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2891         }
2892
2893         return 0;
2894 }
2895
2896 /**
2897  * Interrupt handler which shall be registered at first.
2898  *
2899  * @param handle
2900  *  Pointer to interrupt handle.
2901  * @param param
2902  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2903  *
2904  * @return
2905  *  void
2906  */
2907 static void
2908 eth_igb_interrupt_handler(void *param)
2909 {
2910         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2911
2912         eth_igb_interrupt_get_status(dev);
2913         eth_igb_interrupt_action(dev, dev->intr_handle);
2914 }
2915
2916 static int
2917 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2918 {
2919         uint32_t eicr;
2920         struct e1000_hw *hw =
2921                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2922         struct e1000_interrupt *intr =
2923                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2924
2925         igbvf_intr_disable(hw);
2926
2927         /* read-on-clear nic registers here */
2928         eicr = E1000_READ_REG(hw, E1000_EICR);
2929         intr->flags = 0;
2930
2931         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2932                 intr->flags |= E1000_FLAG_MAILBOX;
2933
2934         return 0;
2935 }
2936
2937 void igbvf_mbx_process(struct rte_eth_dev *dev)
2938 {
2939         struct e1000_hw *hw =
2940                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2941         struct e1000_mbx_info *mbx = &hw->mbx;
2942         u32 in_msg = 0;
2943
2944         if (mbx->ops.read(hw, &in_msg, 1, 0))
2945                 return;
2946
2947         /* PF reset VF event */
2948         if (in_msg == E1000_PF_CONTROL_MSG)
2949                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2950 }
2951
2952 static int
2953 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2954 {
2955         struct e1000_interrupt *intr =
2956                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2957
2958         if (intr->flags & E1000_FLAG_MAILBOX) {
2959                 igbvf_mbx_process(dev);
2960                 intr->flags &= ~E1000_FLAG_MAILBOX;
2961         }
2962
2963         igbvf_intr_enable(dev);
2964         rte_intr_enable(intr_handle);
2965
2966         return 0;
2967 }
2968
2969 static void
2970 eth_igbvf_interrupt_handler(void *param)
2971 {
2972         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2973
2974         eth_igbvf_interrupt_get_status(dev);
2975         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2976 }
2977
2978 static int
2979 eth_igb_led_on(struct rte_eth_dev *dev)
2980 {
2981         struct e1000_hw *hw;
2982
2983         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2984         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2985 }
2986
2987 static int
2988 eth_igb_led_off(struct rte_eth_dev *dev)
2989 {
2990         struct e1000_hw *hw;
2991
2992         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2993         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2994 }
2995
2996 static int
2997 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2998 {
2999         struct e1000_hw *hw;
3000         uint32_t ctrl;
3001         int tx_pause;
3002         int rx_pause;
3003
3004         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3005         fc_conf->pause_time = hw->fc.pause_time;
3006         fc_conf->high_water = hw->fc.high_water;
3007         fc_conf->low_water = hw->fc.low_water;
3008         fc_conf->send_xon = hw->fc.send_xon;
3009         fc_conf->autoneg = hw->mac.autoneg;
3010
3011         /*
3012          * Return rx_pause and tx_pause status according to actual setting of
3013          * the TFCE and RFCE bits in the CTRL register.
3014          */
3015         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3016         if (ctrl & E1000_CTRL_TFCE)
3017                 tx_pause = 1;
3018         else
3019                 tx_pause = 0;
3020
3021         if (ctrl & E1000_CTRL_RFCE)
3022                 rx_pause = 1;
3023         else
3024                 rx_pause = 0;
3025
3026         if (rx_pause && tx_pause)
3027                 fc_conf->mode = RTE_FC_FULL;
3028         else if (rx_pause)
3029                 fc_conf->mode = RTE_FC_RX_PAUSE;
3030         else if (tx_pause)
3031                 fc_conf->mode = RTE_FC_TX_PAUSE;
3032         else
3033                 fc_conf->mode = RTE_FC_NONE;
3034
3035         return 0;
3036 }
3037
3038 static int
3039 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3040 {
3041         struct e1000_hw *hw;
3042         int err;
3043         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3044                 e1000_fc_none,
3045                 e1000_fc_rx_pause,
3046                 e1000_fc_tx_pause,
3047                 e1000_fc_full
3048         };
3049         uint32_t rx_buf_size;
3050         uint32_t max_high_water;
3051         uint32_t rctl;
3052
3053         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3054         if (fc_conf->autoneg != hw->mac.autoneg)
3055                 return -ENOTSUP;
3056         rx_buf_size = igb_get_rx_buffer_size(hw);
3057         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3058
3059         /* At least reserve one Ethernet frame for watermark */
3060         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3061         if ((fc_conf->high_water > max_high_water) ||
3062             (fc_conf->high_water < fc_conf->low_water)) {
3063                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3064                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3065                 return -EINVAL;
3066         }
3067
3068         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3069         hw->fc.pause_time     = fc_conf->pause_time;
3070         hw->fc.high_water     = fc_conf->high_water;
3071         hw->fc.low_water      = fc_conf->low_water;
3072         hw->fc.send_xon       = fc_conf->send_xon;
3073
3074         err = e1000_setup_link_generic(hw);
3075         if (err == E1000_SUCCESS) {
3076
3077                 /* check if we want to forward MAC frames - driver doesn't have native
3078                  * capability to do that, so we'll write the registers ourselves */
3079
3080                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3081
3082                 /* set or clear MFLCN.PMCF bit depending on configuration */
3083                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3084                         rctl |= E1000_RCTL_PMCF;
3085                 else
3086                         rctl &= ~E1000_RCTL_PMCF;
3087
3088                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3089                 E1000_WRITE_FLUSH(hw);
3090
3091                 return 0;
3092         }
3093
3094         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3095         return -EIO;
3096 }
3097
3098 #define E1000_RAH_POOLSEL_SHIFT      (18)
3099 static int
3100 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3101                 uint32_t index, uint32_t pool)
3102 {
3103         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3104         uint32_t rah;
3105
3106         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3107         rah = E1000_READ_REG(hw, E1000_RAH(index));
3108         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3109         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3110         return 0;
3111 }
3112
3113 static void
3114 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3115 {
3116         uint8_t addr[ETHER_ADDR_LEN];
3117         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3118
3119         memset(addr, 0, sizeof(addr));
3120
3121         e1000_rar_set(hw, addr, index);
3122 }
3123
3124 static void
3125 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3126                                 struct ether_addr *addr)
3127 {
3128         eth_igb_rar_clear(dev, 0);
3129
3130         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3131 }
3132 /*
3133  * Virtual Function operations
3134  */
3135 static void
3136 igbvf_intr_disable(struct e1000_hw *hw)
3137 {
3138         PMD_INIT_FUNC_TRACE();
3139
3140         /* Clear interrupt mask to stop from interrupts being generated */
3141         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3142
3143         E1000_WRITE_FLUSH(hw);
3144 }
3145
3146 static void
3147 igbvf_stop_adapter(struct rte_eth_dev *dev)
3148 {
3149         u32 reg_val;
3150         u16 i;
3151         struct rte_eth_dev_info dev_info;
3152         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3153
3154         memset(&dev_info, 0, sizeof(dev_info));
3155         eth_igbvf_infos_get(dev, &dev_info);
3156
3157         /* Clear interrupt mask to stop from interrupts being generated */
3158         igbvf_intr_disable(hw);
3159
3160         /* Clear any pending interrupts, flush previous writes */
3161         E1000_READ_REG(hw, E1000_EICR);
3162
3163         /* Disable the transmit unit.  Each queue must be disabled. */
3164         for (i = 0; i < dev_info.max_tx_queues; i++)
3165                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3166
3167         /* Disable the receive unit by stopping each queue */
3168         for (i = 0; i < dev_info.max_rx_queues; i++) {
3169                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3170                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3171                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3172                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3173                         ;
3174         }
3175
3176         /* flush all queues disables */
3177         E1000_WRITE_FLUSH(hw);
3178         msec_delay(2);
3179 }
3180
3181 static int eth_igbvf_link_update(struct e1000_hw *hw)
3182 {
3183         struct e1000_mbx_info *mbx = &hw->mbx;
3184         struct e1000_mac_info *mac = &hw->mac;
3185         int ret_val = E1000_SUCCESS;
3186
3187         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3188
3189         /*
3190          * We only want to run this if there has been a rst asserted.
3191          * in this case that could mean a link change, device reset,
3192          * or a virtual function reset
3193          */
3194
3195         /* If we were hit with a reset or timeout drop the link */
3196         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3197                 mac->get_link_status = TRUE;
3198
3199         if (!mac->get_link_status)
3200                 goto out;
3201
3202         /* if link status is down no point in checking to see if pf is up */
3203         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3204                 goto out;
3205
3206         /* if we passed all the tests above then the link is up and we no
3207          * longer need to check for link */
3208         mac->get_link_status = FALSE;
3209
3210 out:
3211         return ret_val;
3212 }
3213
3214
3215 static int
3216 igbvf_dev_configure(struct rte_eth_dev *dev)
3217 {
3218         struct rte_eth_conf* conf = &dev->data->dev_conf;
3219
3220         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3221                      dev->data->port_id);
3222
3223         /*
3224          * VF has no ability to enable/disable HW CRC
3225          * Keep the persistent behavior the same as Host PF
3226          */
3227 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3228         if (!conf->rxmode.hw_strip_crc) {
3229                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3230                 conf->rxmode.hw_strip_crc = 1;
3231         }
3232 #else
3233         if (conf->rxmode.hw_strip_crc) {
3234                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3235                 conf->rxmode.hw_strip_crc = 0;
3236         }
3237 #endif
3238
3239         return 0;
3240 }
3241
3242 static int
3243 igbvf_dev_start(struct rte_eth_dev *dev)
3244 {
3245         struct e1000_hw *hw =
3246                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3247         struct e1000_adapter *adapter =
3248                 E1000_DEV_PRIVATE(dev->data->dev_private);
3249         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3250         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3251         int ret;
3252         uint32_t intr_vector = 0;
3253
3254         PMD_INIT_FUNC_TRACE();
3255
3256         hw->mac.ops.reset_hw(hw);
3257         adapter->stopped = 0;
3258
3259         /* Set all vfta */
3260         igbvf_set_vfta_all(dev,1);
3261
3262         eth_igbvf_tx_init(dev);
3263
3264         /* This can fail when allocating mbufs for descriptor rings */
3265         ret = eth_igbvf_rx_init(dev);
3266         if (ret) {
3267                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3268                 igb_dev_clear_queues(dev);
3269                 return ret;
3270         }
3271
3272         /* check and configure queue intr-vector mapping */
3273         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3274                 intr_vector = dev->data->nb_rx_queues;
3275                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3276                 if (ret)
3277                         return ret;
3278         }
3279
3280         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3281                 intr_handle->intr_vec =
3282                         rte_zmalloc("intr_vec",
3283                                     dev->data->nb_rx_queues * sizeof(int), 0);
3284                 if (!intr_handle->intr_vec) {
3285                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3286                                      " intr_vec", dev->data->nb_rx_queues);
3287                         return -ENOMEM;
3288                 }
3289         }
3290
3291         eth_igbvf_configure_msix_intr(dev);
3292
3293         /* enable uio/vfio intr/eventfd mapping */
3294         rte_intr_enable(intr_handle);
3295
3296         /* resume enabled intr since hw reset */
3297         igbvf_intr_enable(dev);
3298
3299         return 0;
3300 }
3301
3302 static void
3303 igbvf_dev_stop(struct rte_eth_dev *dev)
3304 {
3305         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3306         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3307
3308         PMD_INIT_FUNC_TRACE();
3309
3310         igbvf_stop_adapter(dev);
3311
3312         /*
3313           * Clear what we set, but we still keep shadow_vfta to
3314           * restore after device starts
3315           */
3316         igbvf_set_vfta_all(dev,0);
3317
3318         igb_dev_clear_queues(dev);
3319
3320         /* disable intr eventfd mapping */
3321         rte_intr_disable(intr_handle);
3322
3323         /* Clean datapath event and queue/vec mapping */
3324         rte_intr_efd_disable(intr_handle);
3325         if (intr_handle->intr_vec) {
3326                 rte_free(intr_handle->intr_vec);
3327                 intr_handle->intr_vec = NULL;
3328         }
3329 }
3330
3331 static void
3332 igbvf_dev_close(struct rte_eth_dev *dev)
3333 {
3334         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3335         struct e1000_adapter *adapter =
3336                 E1000_DEV_PRIVATE(dev->data->dev_private);
3337         struct ether_addr addr;
3338
3339         PMD_INIT_FUNC_TRACE();
3340
3341         e1000_reset_hw(hw);
3342
3343         igbvf_dev_stop(dev);
3344         adapter->stopped = 1;
3345         igb_dev_free_queues(dev);
3346
3347         /**
3348          * reprogram the RAR with a zero mac address,
3349          * to ensure that the VF traffic goes to the PF
3350          * after stop, close and detach of the VF.
3351          **/
3352
3353         memset(&addr, 0, sizeof(addr));
3354         igbvf_default_mac_addr_set(dev, &addr);
3355 }
3356
3357 static void
3358 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3359 {
3360         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3361
3362         /* Set both unicast and multicast promisc */
3363         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3364 }
3365
3366 static void
3367 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3368 {
3369         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3370
3371         /* If in allmulticast mode leave multicast promisc */
3372         if (dev->data->all_multicast == 1)
3373                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3374         else
3375                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3376 }
3377
3378 static void
3379 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3380 {
3381         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3382
3383         /* In promiscuous mode multicast promisc already set */
3384         if (dev->data->promiscuous == 0)
3385                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3386 }
3387
3388 static void
3389 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3390 {
3391         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3392
3393         /* In promiscuous mode leave multicast promisc enabled */
3394         if (dev->data->promiscuous == 0)
3395                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3396 }
3397
3398 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3399 {
3400         struct e1000_mbx_info *mbx = &hw->mbx;
3401         uint32_t msgbuf[2];
3402         s32 err;
3403
3404         /* After set vlan, vlan strip will also be enabled in igb driver*/
3405         msgbuf[0] = E1000_VF_SET_VLAN;
3406         msgbuf[1] = vid;
3407         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3408         if (on)
3409                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3410
3411         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3412         if (err)
3413                 goto mbx_err;
3414
3415         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3416         if (err)
3417                 goto mbx_err;
3418
3419         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3420         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3421                 err = -EINVAL;
3422
3423 mbx_err:
3424         return err;
3425 }
3426
3427 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3428 {
3429         struct e1000_hw *hw =
3430                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3431         struct e1000_vfta * shadow_vfta =
3432                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3433         int i = 0, j = 0, vfta = 0, mask = 1;
3434
3435         for (i = 0; i < IGB_VFTA_SIZE; i++){
3436                 vfta = shadow_vfta->vfta[i];
3437                 if(vfta){
3438                         mask = 1;
3439                         for (j = 0; j < 32; j++){
3440                                 if(vfta & mask)
3441                                         igbvf_set_vfta(hw,
3442                                                 (uint16_t)((i<<5)+j), on);
3443                                 mask<<=1;
3444                         }
3445                 }
3446         }
3447
3448 }
3449
3450 static int
3451 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3452 {
3453         struct e1000_hw *hw =
3454                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3455         struct e1000_vfta * shadow_vfta =
3456                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3457         uint32_t vid_idx = 0;
3458         uint32_t vid_bit = 0;
3459         int ret = 0;
3460
3461         PMD_INIT_FUNC_TRACE();
3462
3463         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3464         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3465         if(ret){
3466                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3467                 return ret;
3468         }
3469         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3470         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3471
3472         /*Save what we set and retore it after device reset*/
3473         if (on)
3474                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3475         else
3476                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3477
3478         return 0;
3479 }
3480
3481 static void
3482 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3483 {
3484         struct e1000_hw *hw =
3485                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3486
3487         /* index is not used by rar_set() */
3488         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3489 }
3490
3491
3492 static int
3493 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3494                         struct rte_eth_rss_reta_entry64 *reta_conf,
3495                         uint16_t reta_size)
3496 {
3497         uint8_t i, j, mask;
3498         uint32_t reta, r;
3499         uint16_t idx, shift;
3500         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3501
3502         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3503                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3504                         "(%d) doesn't match the number hardware can supported "
3505                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3506                 return -EINVAL;
3507         }
3508
3509         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3510                 idx = i / RTE_RETA_GROUP_SIZE;
3511                 shift = i % RTE_RETA_GROUP_SIZE;
3512                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3513                                                 IGB_4_BIT_MASK);
3514                 if (!mask)
3515                         continue;
3516                 if (mask == IGB_4_BIT_MASK)
3517                         r = 0;
3518                 else
3519                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3520                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3521                         if (mask & (0x1 << j))
3522                                 reta |= reta_conf[idx].reta[shift + j] <<
3523                                                         (CHAR_BIT * j);
3524                         else
3525                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3526                 }
3527                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3528         }
3529
3530         return 0;
3531 }
3532
3533 static int
3534 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3535                        struct rte_eth_rss_reta_entry64 *reta_conf,
3536                        uint16_t reta_size)
3537 {
3538         uint8_t i, j, mask;
3539         uint32_t reta;
3540         uint16_t idx, shift;
3541         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3542
3543         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3544                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3545                         "(%d) doesn't match the number hardware can supported "
3546                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3547                 return -EINVAL;
3548         }
3549
3550         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3551                 idx = i / RTE_RETA_GROUP_SIZE;
3552                 shift = i % RTE_RETA_GROUP_SIZE;
3553                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3554                                                 IGB_4_BIT_MASK);
3555                 if (!mask)
3556                         continue;
3557                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3558                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3559                         if (mask & (0x1 << j))
3560                                 reta_conf[idx].reta[shift + j] =
3561                                         ((reta >> (CHAR_BIT * j)) &
3562                                                 IGB_8_BIT_MASK);
3563                 }
3564         }
3565
3566         return 0;
3567 }
3568
3569 #define MAC_TYPE_FILTER_SUP(type)    do {\
3570         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3571                 (type) != e1000_82576 && (type) != e1000_i210 &&\
3572                 (type) != e1000_i211)\
3573                 return -ENOTSUP;\
3574 } while (0)
3575
3576 static int
3577 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3578                         struct rte_eth_syn_filter *filter,
3579                         bool add)
3580 {
3581         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3582         struct e1000_filter_info *filter_info =
3583                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3584         uint32_t synqf, rfctl;
3585
3586         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3587                 return -EINVAL;
3588
3589         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3590
3591         if (add) {
3592                 if (synqf & E1000_SYN_FILTER_ENABLE)
3593                         return -EINVAL;
3594
3595                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3596                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3597
3598                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3599                 if (filter->hig_pri)
3600                         rfctl |= E1000_RFCTL_SYNQFP;
3601                 else
3602                         rfctl &= ~E1000_RFCTL_SYNQFP;
3603
3604                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3605         } else {
3606                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3607                         return -ENOENT;
3608                 synqf = 0;
3609         }
3610
3611         filter_info->syn_info = synqf;
3612         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3613         E1000_WRITE_FLUSH(hw);
3614         return 0;
3615 }
3616
3617 static int
3618 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3619                         struct rte_eth_syn_filter *filter)
3620 {
3621         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3622         uint32_t synqf, rfctl;
3623
3624         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3625         if (synqf & E1000_SYN_FILTER_ENABLE) {
3626                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3627                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3628                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3629                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3630                 return 0;
3631         }
3632
3633         return -ENOENT;
3634 }
3635
3636 static int
3637 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3638                         enum rte_filter_op filter_op,
3639                         void *arg)
3640 {
3641         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3642         int ret;
3643
3644         MAC_TYPE_FILTER_SUP(hw->mac.type);
3645
3646         if (filter_op == RTE_ETH_FILTER_NOP)
3647                 return 0;
3648
3649         if (arg == NULL) {
3650                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3651                             filter_op);
3652                 return -EINVAL;
3653         }
3654
3655         switch (filter_op) {
3656         case RTE_ETH_FILTER_ADD:
3657                 ret = eth_igb_syn_filter_set(dev,
3658                                 (struct rte_eth_syn_filter *)arg,
3659                                 TRUE);
3660                 break;
3661         case RTE_ETH_FILTER_DELETE:
3662                 ret = eth_igb_syn_filter_set(dev,
3663                                 (struct rte_eth_syn_filter *)arg,
3664                                 FALSE);
3665                 break;
3666         case RTE_ETH_FILTER_GET:
3667                 ret = eth_igb_syn_filter_get(dev,
3668                                 (struct rte_eth_syn_filter *)arg);
3669                 break;
3670         default:
3671                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3672                 ret = -EINVAL;
3673                 break;
3674         }
3675
3676         return ret;
3677 }
3678
3679 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3680         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3681                 (type) != e1000_i210 && (type) != e1000_i211)\
3682                 return -ENOSYS; \
3683 } while (0)
3684
3685 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3686 static inline int
3687 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3688                         struct e1000_2tuple_filter_info *filter_info)
3689 {
3690         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3691                 return -EINVAL;
3692         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3693                 return -EINVAL;  /* filter index is out of range. */
3694         if (filter->tcp_flags > TCP_FLAG_ALL)
3695                 return -EINVAL;  /* flags is invalid. */
3696
3697         switch (filter->dst_port_mask) {
3698         case UINT16_MAX:
3699                 filter_info->dst_port_mask = 0;
3700                 filter_info->dst_port = filter->dst_port;
3701                 break;
3702         case 0:
3703                 filter_info->dst_port_mask = 1;
3704                 break;
3705         default:
3706                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3707                 return -EINVAL;
3708         }
3709
3710         switch (filter->proto_mask) {
3711         case UINT8_MAX:
3712                 filter_info->proto_mask = 0;
3713                 filter_info->proto = filter->proto;
3714                 break;
3715         case 0:
3716                 filter_info->proto_mask = 1;
3717                 break;
3718         default:
3719                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3720                 return -EINVAL;
3721         }
3722
3723         filter_info->priority = (uint8_t)filter->priority;
3724         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3725                 filter_info->tcp_flags = filter->tcp_flags;
3726         else
3727                 filter_info->tcp_flags = 0;
3728
3729         return 0;
3730 }
3731
3732 static inline struct e1000_2tuple_filter *
3733 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3734                         struct e1000_2tuple_filter_info *key)
3735 {
3736         struct e1000_2tuple_filter *it;
3737
3738         TAILQ_FOREACH(it, filter_list, entries) {
3739                 if (memcmp(key, &it->filter_info,
3740                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3741                         return it;
3742                 }
3743         }
3744         return NULL;
3745 }
3746
3747 /* inject a igb 2tuple filter to HW */
3748 static inline void
3749 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3750                            struct e1000_2tuple_filter *filter)
3751 {
3752         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3753         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3754         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3755         int i;
3756
3757         i = filter->index;
3758         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3759         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3760                 imir |= E1000_IMIR_PORT_BP;
3761         else
3762                 imir &= ~E1000_IMIR_PORT_BP;
3763
3764         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3765
3766         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3767         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3768         ttqf |= (uint32_t)(filter->filter_info.proto &
3769                                                 E1000_TTQF_PROTOCOL_MASK);
3770         if (filter->filter_info.proto_mask == 0)
3771                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3772
3773         /* tcp flags bits setting. */
3774         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3775                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3776                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3777                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3778                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3779                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3780                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3781                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3782                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3783                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3784                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3785                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3786                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3787         } else {
3788                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3789         }
3790         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3791         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3792         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3793 }
3794
3795 /*
3796  * igb_add_2tuple_filter - add a 2tuple filter
3797  *
3798  * @param
3799  * dev: Pointer to struct rte_eth_dev.
3800  * ntuple_filter: ponter to the filter that will be added.
3801  *
3802  * @return
3803  *    - On success, zero.
3804  *    - On failure, a negative value.
3805  */
3806 static int
3807 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3808                         struct rte_eth_ntuple_filter *ntuple_filter)
3809 {
3810         struct e1000_filter_info *filter_info =
3811                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3812         struct e1000_2tuple_filter *filter;
3813         int i, ret;
3814
3815         filter = rte_zmalloc("e1000_2tuple_filter",
3816                         sizeof(struct e1000_2tuple_filter), 0);
3817         if (filter == NULL)
3818                 return -ENOMEM;
3819
3820         ret = ntuple_filter_to_2tuple(ntuple_filter,
3821                                       &filter->filter_info);
3822         if (ret < 0) {
3823                 rte_free(filter);
3824                 return ret;
3825         }
3826         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3827                                          &filter->filter_info) != NULL) {
3828                 PMD_DRV_LOG(ERR, "filter exists.");
3829                 rte_free(filter);
3830                 return -EEXIST;
3831         }
3832         filter->queue = ntuple_filter->queue;
3833
3834         /*
3835          * look for an unused 2tuple filter index,
3836          * and insert the filter to list.
3837          */
3838         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3839                 if (!(filter_info->twotuple_mask & (1 << i))) {
3840                         filter_info->twotuple_mask |= 1 << i;
3841                         filter->index = i;
3842                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3843                                           filter,
3844                                           entries);
3845                         break;
3846                 }
3847         }
3848         if (i >= E1000_MAX_TTQF_FILTERS) {
3849                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3850                 rte_free(filter);
3851                 return -ENOSYS;
3852         }
3853
3854         igb_inject_2uple_filter(dev, filter);
3855         return 0;
3856 }
3857
3858 /*
3859  * igb_remove_2tuple_filter - remove a 2tuple filter
3860  *
3861  * @param
3862  * dev: Pointer to struct rte_eth_dev.
3863  * ntuple_filter: ponter to the filter that will be removed.
3864  *
3865  * @return
3866  *    - On success, zero.
3867  *    - On failure, a negative value.
3868  */
3869 static int
3870 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3871                         struct rte_eth_ntuple_filter *ntuple_filter)
3872 {
3873         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3874         struct e1000_filter_info *filter_info =
3875                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3876         struct e1000_2tuple_filter_info filter_2tuple;
3877         struct e1000_2tuple_filter *filter;
3878         int ret;
3879
3880         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3881         ret = ntuple_filter_to_2tuple(ntuple_filter,
3882                                       &filter_2tuple);
3883         if (ret < 0)
3884                 return ret;
3885
3886         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3887                                          &filter_2tuple);
3888         if (filter == NULL) {
3889                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3890                 return -ENOENT;
3891         }
3892
3893         filter_info->twotuple_mask &= ~(1 << filter->index);
3894         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3895         rte_free(filter);
3896
3897         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3898         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3899         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3900         return 0;
3901 }
3902
3903 static inline struct e1000_flex_filter *
3904 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3905                         struct e1000_flex_filter_info *key)
3906 {
3907         struct e1000_flex_filter *it;
3908
3909         TAILQ_FOREACH(it, filter_list, entries) {
3910                 if (memcmp(key, &it->filter_info,
3911                         sizeof(struct e1000_flex_filter_info)) == 0)
3912                         return it;
3913         }
3914
3915         return NULL;
3916 }
3917
3918 static int
3919 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3920                         struct rte_eth_flex_filter *filter,
3921                         bool add)
3922 {
3923         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3924         struct e1000_filter_info *filter_info =
3925                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3926         struct e1000_flex_filter *flex_filter, *it;
3927         uint32_t wufc, queueing, mask;
3928         uint32_t reg_off;
3929         uint8_t shift, i, j = 0;
3930
3931         flex_filter = rte_zmalloc("e1000_flex_filter",
3932                         sizeof(struct e1000_flex_filter), 0);
3933         if (flex_filter == NULL)
3934                 return -ENOMEM;
3935
3936         flex_filter->filter_info.len = filter->len;
3937         flex_filter->filter_info.priority = filter->priority;
3938         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3939         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3940                 mask = 0;
3941                 /* reverse bits in flex filter's mask*/
3942                 for (shift = 0; shift < CHAR_BIT; shift++) {
3943                         if (filter->mask[i] & (0x01 << shift))
3944                                 mask |= (0x80 >> shift);
3945                 }
3946                 flex_filter->filter_info.mask[i] = mask;
3947         }
3948
3949         wufc = E1000_READ_REG(hw, E1000_WUFC);
3950
3951         if (add) {
3952                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3953                                 &flex_filter->filter_info) != NULL) {
3954                         PMD_DRV_LOG(ERR, "filter exists.");
3955                         rte_free(flex_filter);
3956                         return -EEXIST;
3957                 }
3958                 flex_filter->queue = filter->queue;
3959                 /*
3960                  * look for an unused flex filter index
3961                  * and insert the filter into the list.
3962                  */
3963                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3964                         if (!(filter_info->flex_mask & (1 << i))) {
3965                                 filter_info->flex_mask |= 1 << i;
3966                                 flex_filter->index = i;
3967                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3968                                         flex_filter,
3969                                         entries);
3970                                 break;
3971                         }
3972                 }
3973                 if (i >= E1000_MAX_FLEX_FILTERS) {
3974                         PMD_DRV_LOG(ERR, "flex filters are full.");
3975                         rte_free(flex_filter);
3976                         return -ENOSYS;
3977                 }
3978
3979                 if (flex_filter->index < E1000_MAX_FHFT)
3980                         reg_off = E1000_FHFT(flex_filter->index);
3981                 else
3982                         reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3983
3984                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3985                                 (E1000_WUFC_FLX0 << flex_filter->index));
3986                 queueing = filter->len |
3987                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3988                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3989                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3990                                 queueing);
3991                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3992                         E1000_WRITE_REG(hw, reg_off,
3993                                         flex_filter->filter_info.dwords[j]);
3994                         reg_off += sizeof(uint32_t);
3995                         E1000_WRITE_REG(hw, reg_off,
3996                                         flex_filter->filter_info.dwords[++j]);
3997                         reg_off += sizeof(uint32_t);
3998                         E1000_WRITE_REG(hw, reg_off,
3999                                 (uint32_t)flex_filter->filter_info.mask[i]);
4000                         reg_off += sizeof(uint32_t) * 2;
4001                         ++j;
4002                 }
4003         } else {
4004                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4005                                 &flex_filter->filter_info);
4006                 if (it == NULL) {
4007                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4008                         rte_free(flex_filter);
4009                         return -ENOENT;
4010                 }
4011
4012                 if (it->index < E1000_MAX_FHFT)
4013                         reg_off = E1000_FHFT(it->index);
4014                 else
4015                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4016
4017                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4018                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4019                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4020                         (~(E1000_WUFC_FLX0 << it->index)));
4021
4022                 filter_info->flex_mask &= ~(1 << it->index);
4023                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
4024                 rte_free(it);
4025                 rte_free(flex_filter);
4026         }
4027
4028         return 0;
4029 }
4030
4031 static int
4032 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4033                         struct rte_eth_flex_filter *filter)
4034 {
4035         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4036         struct e1000_filter_info *filter_info =
4037                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4038         struct e1000_flex_filter flex_filter, *it;
4039         uint32_t wufc, queueing, wufc_en = 0;
4040
4041         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4042         flex_filter.filter_info.len = filter->len;
4043         flex_filter.filter_info.priority = filter->priority;
4044         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4045         memcpy(flex_filter.filter_info.mask, filter->mask,
4046                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
4047
4048         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4049                                 &flex_filter.filter_info);
4050         if (it == NULL) {
4051                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4052                 return -ENOENT;
4053         }
4054
4055         wufc = E1000_READ_REG(hw, E1000_WUFC);
4056         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4057
4058         if ((wufc & wufc_en) == wufc_en) {
4059                 uint32_t reg_off = 0;
4060                 if (it->index < E1000_MAX_FHFT)
4061                         reg_off = E1000_FHFT(it->index);
4062                 else
4063                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4064
4065                 queueing = E1000_READ_REG(hw,
4066                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4067                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4068                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4069                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4070                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4071                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4072                 return 0;
4073         }
4074         return -ENOENT;
4075 }
4076
4077 static int
4078 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4079                         enum rte_filter_op filter_op,
4080                         void *arg)
4081 {
4082         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4083         struct rte_eth_flex_filter *filter;
4084         int ret = 0;
4085
4086         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4087
4088         if (filter_op == RTE_ETH_FILTER_NOP)
4089                 return ret;
4090
4091         if (arg == NULL) {
4092                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4093                             filter_op);
4094                 return -EINVAL;
4095         }
4096
4097         filter = (struct rte_eth_flex_filter *)arg;
4098         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4099             || filter->len % sizeof(uint64_t) != 0) {
4100                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4101                 return -EINVAL;
4102         }
4103         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4104                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4105                 return -EINVAL;
4106         }
4107
4108         switch (filter_op) {
4109         case RTE_ETH_FILTER_ADD:
4110                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4111                 break;
4112         case RTE_ETH_FILTER_DELETE:
4113                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4114                 break;
4115         case RTE_ETH_FILTER_GET:
4116                 ret = eth_igb_get_flex_filter(dev, filter);
4117                 break;
4118         default:
4119                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4120                 ret = -EINVAL;
4121                 break;
4122         }
4123
4124         return ret;
4125 }
4126
4127 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4128 static inline int
4129 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4130                         struct e1000_5tuple_filter_info *filter_info)
4131 {
4132         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4133                 return -EINVAL;
4134         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4135                 return -EINVAL;  /* filter index is out of range. */
4136         if (filter->tcp_flags > TCP_FLAG_ALL)
4137                 return -EINVAL;  /* flags is invalid. */
4138
4139         switch (filter->dst_ip_mask) {
4140         case UINT32_MAX:
4141                 filter_info->dst_ip_mask = 0;
4142                 filter_info->dst_ip = filter->dst_ip;
4143                 break;
4144         case 0:
4145                 filter_info->dst_ip_mask = 1;
4146                 break;
4147         default:
4148                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4149                 return -EINVAL;
4150         }
4151
4152         switch (filter->src_ip_mask) {
4153         case UINT32_MAX:
4154                 filter_info->src_ip_mask = 0;
4155                 filter_info->src_ip = filter->src_ip;
4156                 break;
4157         case 0:
4158                 filter_info->src_ip_mask = 1;
4159                 break;
4160         default:
4161                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4162                 return -EINVAL;
4163         }
4164
4165         switch (filter->dst_port_mask) {
4166         case UINT16_MAX:
4167                 filter_info->dst_port_mask = 0;
4168                 filter_info->dst_port = filter->dst_port;
4169                 break;
4170         case 0:
4171                 filter_info->dst_port_mask = 1;
4172                 break;
4173         default:
4174                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4175                 return -EINVAL;
4176         }
4177
4178         switch (filter->src_port_mask) {
4179         case UINT16_MAX:
4180                 filter_info->src_port_mask = 0;
4181                 filter_info->src_port = filter->src_port;
4182                 break;
4183         case 0:
4184                 filter_info->src_port_mask = 1;
4185                 break;
4186         default:
4187                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4188                 return -EINVAL;
4189         }
4190
4191         switch (filter->proto_mask) {
4192         case UINT8_MAX:
4193                 filter_info->proto_mask = 0;
4194                 filter_info->proto = filter->proto;
4195                 break;
4196         case 0:
4197                 filter_info->proto_mask = 1;
4198                 break;
4199         default:
4200                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4201                 return -EINVAL;
4202         }
4203
4204         filter_info->priority = (uint8_t)filter->priority;
4205         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4206                 filter_info->tcp_flags = filter->tcp_flags;
4207         else
4208                 filter_info->tcp_flags = 0;
4209
4210         return 0;
4211 }
4212
4213 static inline struct e1000_5tuple_filter *
4214 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4215                         struct e1000_5tuple_filter_info *key)
4216 {
4217         struct e1000_5tuple_filter *it;
4218
4219         TAILQ_FOREACH(it, filter_list, entries) {
4220                 if (memcmp(key, &it->filter_info,
4221                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4222                         return it;
4223                 }
4224         }
4225         return NULL;
4226 }
4227
4228 /* inject a igb 5-tuple filter to HW */
4229 static inline void
4230 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4231                            struct e1000_5tuple_filter *filter)
4232 {
4233         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4234         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4235         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4236         uint8_t i;
4237
4238         i = filter->index;
4239         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4240         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4241                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4242         if (filter->filter_info.dst_ip_mask == 0)
4243                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4244         if (filter->filter_info.src_port_mask == 0)
4245                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4246         if (filter->filter_info.proto_mask == 0)
4247                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4248         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4249                 E1000_FTQF_QUEUE_MASK;
4250         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4251         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4252         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4253         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4254
4255         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4256         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4257
4258         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4259         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4260                 imir |= E1000_IMIR_PORT_BP;
4261         else
4262                 imir &= ~E1000_IMIR_PORT_BP;
4263         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4264
4265         /* tcp flags bits setting. */
4266         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4267                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4268                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4269                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4270                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4271                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4272                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4273                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4274                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4275                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4276                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4277                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4278                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4279         } else {
4280                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4281         }
4282         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4283         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4284 }
4285
4286 /*
4287  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4288  *
4289  * @param
4290  * dev: Pointer to struct rte_eth_dev.
4291  * ntuple_filter: ponter to the filter that will be added.
4292  *
4293  * @return
4294  *    - On success, zero.
4295  *    - On failure, a negative value.
4296  */
4297 static int
4298 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4299                         struct rte_eth_ntuple_filter *ntuple_filter)
4300 {
4301         struct e1000_filter_info *filter_info =
4302                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4303         struct e1000_5tuple_filter *filter;
4304         uint8_t i;
4305         int ret;
4306
4307         filter = rte_zmalloc("e1000_5tuple_filter",
4308                         sizeof(struct e1000_5tuple_filter), 0);
4309         if (filter == NULL)
4310                 return -ENOMEM;
4311
4312         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4313                                             &filter->filter_info);
4314         if (ret < 0) {
4315                 rte_free(filter);
4316                 return ret;
4317         }
4318
4319         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4320                                          &filter->filter_info) != NULL) {
4321                 PMD_DRV_LOG(ERR, "filter exists.");
4322                 rte_free(filter);
4323                 return -EEXIST;
4324         }
4325         filter->queue = ntuple_filter->queue;
4326
4327         /*
4328          * look for an unused 5tuple filter index,
4329          * and insert the filter to list.
4330          */
4331         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4332                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4333                         filter_info->fivetuple_mask |= 1 << i;
4334                         filter->index = i;
4335                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4336                                           filter,
4337                                           entries);
4338                         break;
4339                 }
4340         }
4341         if (i >= E1000_MAX_FTQF_FILTERS) {
4342                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4343                 rte_free(filter);
4344                 return -ENOSYS;
4345         }
4346
4347         igb_inject_5tuple_filter_82576(dev, filter);
4348         return 0;
4349 }
4350
4351 /*
4352  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4353  *
4354  * @param
4355  * dev: Pointer to struct rte_eth_dev.
4356  * ntuple_filter: ponter to the filter that will be removed.
4357  *
4358  * @return
4359  *    - On success, zero.
4360  *    - On failure, a negative value.
4361  */
4362 static int
4363 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4364                                 struct rte_eth_ntuple_filter *ntuple_filter)
4365 {
4366         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4367         struct e1000_filter_info *filter_info =
4368                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4369         struct e1000_5tuple_filter_info filter_5tuple;
4370         struct e1000_5tuple_filter *filter;
4371         int ret;
4372
4373         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4374         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4375                                             &filter_5tuple);
4376         if (ret < 0)
4377                 return ret;
4378
4379         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4380                                          &filter_5tuple);
4381         if (filter == NULL) {
4382                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4383                 return -ENOENT;
4384         }
4385
4386         filter_info->fivetuple_mask &= ~(1 << filter->index);
4387         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4388         rte_free(filter);
4389
4390         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4391                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4392         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4393         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4394         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4395         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4396         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4397         return 0;
4398 }
4399
4400 static int
4401 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4402 {
4403         uint32_t rctl;
4404         struct e1000_hw *hw;
4405         struct rte_eth_dev_info dev_info;
4406         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4407                                      VLAN_TAG_SIZE);
4408
4409         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4410
4411 #ifdef RTE_LIBRTE_82571_SUPPORT
4412         /* XXX: not bigger than max_rx_pktlen */
4413         if (hw->mac.type == e1000_82571)
4414                 return -ENOTSUP;
4415 #endif
4416         eth_igb_infos_get(dev, &dev_info);
4417
4418         /* check that mtu is within the allowed range */
4419         if ((mtu < ETHER_MIN_MTU) ||
4420             (frame_size > dev_info.max_rx_pktlen))
4421                 return -EINVAL;
4422
4423         /* refuse mtu that requires the support of scattered packets when this
4424          * feature has not been enabled before. */
4425         if (!dev->data->scattered_rx &&
4426             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4427                 return -EINVAL;
4428
4429         rctl = E1000_READ_REG(hw, E1000_RCTL);
4430
4431         /* switch to jumbo mode if needed */
4432         if (frame_size > ETHER_MAX_LEN) {
4433                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4434                 rctl |= E1000_RCTL_LPE;
4435         } else {
4436                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4437                 rctl &= ~E1000_RCTL_LPE;
4438         }
4439         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4440
4441         /* update max frame size */
4442         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4443
4444         E1000_WRITE_REG(hw, E1000_RLPML,
4445                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4446
4447         return 0;
4448 }
4449
4450 /*
4451  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4452  *
4453  * @param
4454  * dev: Pointer to struct rte_eth_dev.
4455  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4456  * add: if true, add filter, if false, remove filter
4457  *
4458  * @return
4459  *    - On success, zero.
4460  *    - On failure, a negative value.
4461  */
4462 static int
4463 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4464                         struct rte_eth_ntuple_filter *ntuple_filter,
4465                         bool add)
4466 {
4467         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4468         int ret;
4469
4470         switch (ntuple_filter->flags) {
4471         case RTE_5TUPLE_FLAGS:
4472         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4473                 if (hw->mac.type != e1000_82576)
4474                         return -ENOTSUP;
4475                 if (add)
4476                         ret = igb_add_5tuple_filter_82576(dev,
4477                                                           ntuple_filter);
4478                 else
4479                         ret = igb_remove_5tuple_filter_82576(dev,
4480                                                              ntuple_filter);
4481                 break;
4482         case RTE_2TUPLE_FLAGS:
4483         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4484                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4485                         hw->mac.type != e1000_i210 &&
4486                         hw->mac.type != e1000_i211)
4487                         return -ENOTSUP;
4488                 if (add)
4489                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4490                 else
4491                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4492                 break;
4493         default:
4494                 ret = -EINVAL;
4495                 break;
4496         }
4497
4498         return ret;
4499 }
4500
4501 /*
4502  * igb_get_ntuple_filter - get a ntuple filter
4503  *
4504  * @param
4505  * dev: Pointer to struct rte_eth_dev.
4506  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4507  *
4508  * @return
4509  *    - On success, zero.
4510  *    - On failure, a negative value.
4511  */
4512 static int
4513 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4514                         struct rte_eth_ntuple_filter *ntuple_filter)
4515 {
4516         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4517         struct e1000_filter_info *filter_info =
4518                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4519         struct e1000_5tuple_filter_info filter_5tuple;
4520         struct e1000_2tuple_filter_info filter_2tuple;
4521         struct e1000_5tuple_filter *p_5tuple_filter;
4522         struct e1000_2tuple_filter *p_2tuple_filter;
4523         int ret;
4524
4525         switch (ntuple_filter->flags) {
4526         case RTE_5TUPLE_FLAGS:
4527         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4528                 if (hw->mac.type != e1000_82576)
4529                         return -ENOTSUP;
4530                 memset(&filter_5tuple,
4531                         0,
4532                         sizeof(struct e1000_5tuple_filter_info));
4533                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4534                                                     &filter_5tuple);
4535                 if (ret < 0)
4536                         return ret;
4537                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4538                                         &filter_info->fivetuple_list,
4539                                         &filter_5tuple);
4540                 if (p_5tuple_filter == NULL) {
4541                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4542                         return -ENOENT;
4543                 }
4544                 ntuple_filter->queue = p_5tuple_filter->queue;
4545                 break;
4546         case RTE_2TUPLE_FLAGS:
4547         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4548                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4549                         return -ENOTSUP;
4550                 memset(&filter_2tuple,
4551                         0,
4552                         sizeof(struct e1000_2tuple_filter_info));
4553                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4554                 if (ret < 0)
4555                         return ret;
4556                 p_2tuple_filter = igb_2tuple_filter_lookup(
4557                                         &filter_info->twotuple_list,
4558                                         &filter_2tuple);
4559                 if (p_2tuple_filter == NULL) {
4560                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4561                         return -ENOENT;
4562                 }
4563                 ntuple_filter->queue = p_2tuple_filter->queue;
4564                 break;
4565         default:
4566                 ret = -EINVAL;
4567                 break;
4568         }
4569
4570         return 0;
4571 }
4572
4573 /*
4574  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4575  * @dev: pointer to rte_eth_dev structure
4576  * @filter_op:operation will be taken.
4577  * @arg: a pointer to specific structure corresponding to the filter_op
4578  */
4579 static int
4580 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4581                                 enum rte_filter_op filter_op,
4582                                 void *arg)
4583 {
4584         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4585         int ret;
4586
4587         MAC_TYPE_FILTER_SUP(hw->mac.type);
4588
4589         if (filter_op == RTE_ETH_FILTER_NOP)
4590                 return 0;
4591
4592         if (arg == NULL) {
4593                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4594                             filter_op);
4595                 return -EINVAL;
4596         }
4597
4598         switch (filter_op) {
4599         case RTE_ETH_FILTER_ADD:
4600                 ret = igb_add_del_ntuple_filter(dev,
4601                         (struct rte_eth_ntuple_filter *)arg,
4602                         TRUE);
4603                 break;
4604         case RTE_ETH_FILTER_DELETE:
4605                 ret = igb_add_del_ntuple_filter(dev,
4606                         (struct rte_eth_ntuple_filter *)arg,
4607                         FALSE);
4608                 break;
4609         case RTE_ETH_FILTER_GET:
4610                 ret = igb_get_ntuple_filter(dev,
4611                         (struct rte_eth_ntuple_filter *)arg);
4612                 break;
4613         default:
4614                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4615                 ret = -EINVAL;
4616                 break;
4617         }
4618         return ret;
4619 }
4620
4621 static inline int
4622 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4623                         uint16_t ethertype)
4624 {
4625         int i;
4626
4627         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4628                 if (filter_info->ethertype_filters[i] == ethertype &&
4629                     (filter_info->ethertype_mask & (1 << i)))
4630                         return i;
4631         }
4632         return -1;
4633 }
4634
4635 static inline int
4636 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4637                         uint16_t ethertype)
4638 {
4639         int i;
4640
4641         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4642                 if (!(filter_info->ethertype_mask & (1 << i))) {
4643                         filter_info->ethertype_mask |= 1 << i;
4644                         filter_info->ethertype_filters[i] = ethertype;
4645                         return i;
4646                 }
4647         }
4648         return -1;
4649 }
4650
4651 static inline int
4652 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4653                         uint8_t idx)
4654 {
4655         if (idx >= E1000_MAX_ETQF_FILTERS)
4656                 return -1;
4657         filter_info->ethertype_mask &= ~(1 << idx);
4658         filter_info->ethertype_filters[idx] = 0;
4659         return idx;
4660 }
4661
4662
4663 static int
4664 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4665                         struct rte_eth_ethertype_filter *filter,
4666                         bool add)
4667 {
4668         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4669         struct e1000_filter_info *filter_info =
4670                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4671         uint32_t etqf = 0;
4672         int ret;
4673
4674         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4675                 filter->ether_type == ETHER_TYPE_IPv6) {
4676                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4677                         " ethertype filter.", filter->ether_type);
4678                 return -EINVAL;
4679         }
4680
4681         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4682                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4683                 return -EINVAL;
4684         }
4685         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4686                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4687                 return -EINVAL;
4688         }
4689
4690         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4691         if (ret >= 0 && add) {
4692                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4693                             filter->ether_type);
4694                 return -EEXIST;
4695         }
4696         if (ret < 0 && !add) {
4697                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4698                             filter->ether_type);
4699                 return -ENOENT;
4700         }
4701
4702         if (add) {
4703                 ret = igb_ethertype_filter_insert(filter_info,
4704                         filter->ether_type);
4705                 if (ret < 0) {
4706                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4707                         return -ENOSYS;
4708                 }
4709
4710                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4711                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4712                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4713         } else {
4714                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4715                 if (ret < 0)
4716                         return -ENOSYS;
4717         }
4718         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4719         E1000_WRITE_FLUSH(hw);
4720
4721         return 0;
4722 }
4723
4724 static int
4725 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4726                         struct rte_eth_ethertype_filter *filter)
4727 {
4728         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4729         struct e1000_filter_info *filter_info =
4730                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4731         uint32_t etqf;
4732         int ret;
4733
4734         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4735         if (ret < 0) {
4736                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4737                             filter->ether_type);
4738                 return -ENOENT;
4739         }
4740
4741         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4742         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4743                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4744                 filter->flags = 0;
4745                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4746                                 E1000_ETQF_QUEUE_SHIFT;
4747                 return 0;
4748         }
4749
4750         return -ENOENT;
4751 }
4752
4753 /*
4754  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4755  * @dev: pointer to rte_eth_dev structure
4756  * @filter_op:operation will be taken.
4757  * @arg: a pointer to specific structure corresponding to the filter_op
4758  */
4759 static int
4760 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4761                                 enum rte_filter_op filter_op,
4762                                 void *arg)
4763 {
4764         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4765         int ret;
4766
4767         MAC_TYPE_FILTER_SUP(hw->mac.type);
4768
4769         if (filter_op == RTE_ETH_FILTER_NOP)
4770                 return 0;
4771
4772         if (arg == NULL) {
4773                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4774                             filter_op);
4775                 return -EINVAL;
4776         }
4777
4778         switch (filter_op) {
4779         case RTE_ETH_FILTER_ADD:
4780                 ret = igb_add_del_ethertype_filter(dev,
4781                         (struct rte_eth_ethertype_filter *)arg,
4782                         TRUE);
4783                 break;
4784         case RTE_ETH_FILTER_DELETE:
4785                 ret = igb_add_del_ethertype_filter(dev,
4786                         (struct rte_eth_ethertype_filter *)arg,
4787                         FALSE);
4788                 break;
4789         case RTE_ETH_FILTER_GET:
4790                 ret = igb_get_ethertype_filter(dev,
4791                         (struct rte_eth_ethertype_filter *)arg);
4792                 break;
4793         default:
4794                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4795                 ret = -EINVAL;
4796                 break;
4797         }
4798         return ret;
4799 }
4800
4801 static int
4802 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4803                      enum rte_filter_type filter_type,
4804                      enum rte_filter_op filter_op,
4805                      void *arg)
4806 {
4807         int ret = -EINVAL;
4808
4809         switch (filter_type) {
4810         case RTE_ETH_FILTER_NTUPLE:
4811                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4812                 break;
4813         case RTE_ETH_FILTER_ETHERTYPE:
4814                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4815                 break;
4816         case RTE_ETH_FILTER_SYN:
4817                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4818                 break;
4819         case RTE_ETH_FILTER_FLEXIBLE:
4820                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4821                 break;
4822         default:
4823                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4824                                                         filter_type);
4825                 break;
4826         }
4827
4828         return ret;
4829 }
4830
4831 static int
4832 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4833                          struct ether_addr *mc_addr_set,
4834                          uint32_t nb_mc_addr)
4835 {
4836         struct e1000_hw *hw;
4837
4838         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4839         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4840         return 0;
4841 }
4842
4843 static uint64_t
4844 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4845 {
4846         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4847         uint64_t systime_cycles;
4848
4849         switch (hw->mac.type) {
4850         case e1000_i210:
4851         case e1000_i211:
4852                 /*
4853                  * Need to read System Time Residue Register to be able
4854                  * to read the other two registers.
4855                  */
4856                 E1000_READ_REG(hw, E1000_SYSTIMR);
4857                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4858                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4859                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4860                                 * NSEC_PER_SEC;
4861                 break;
4862         case e1000_82580:
4863         case e1000_i350:
4864         case e1000_i354:
4865                 /*
4866                  * Need to read System Time Residue Register to be able
4867                  * to read the other two registers.
4868                  */
4869                 E1000_READ_REG(hw, E1000_SYSTIMR);
4870                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4871                 /* Only the 8 LSB are valid. */
4872                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4873                                 & 0xff) << 32;
4874                 break;
4875         default:
4876                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4877                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4878                                 << 32;
4879                 break;
4880         }
4881
4882         return systime_cycles;
4883 }
4884
4885 static uint64_t
4886 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4887 {
4888         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4889         uint64_t rx_tstamp_cycles;
4890
4891         switch (hw->mac.type) {
4892         case e1000_i210:
4893         case e1000_i211:
4894                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4895                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4896                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4897                                 * NSEC_PER_SEC;
4898                 break;
4899         case e1000_82580:
4900         case e1000_i350:
4901         case e1000_i354:
4902                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4903                 /* Only the 8 LSB are valid. */
4904                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4905                                 & 0xff) << 32;
4906                 break;
4907         default:
4908                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4909                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4910                                 << 32;
4911                 break;
4912         }
4913
4914         return rx_tstamp_cycles;
4915 }
4916
4917 static uint64_t
4918 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4919 {
4920         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4921         uint64_t tx_tstamp_cycles;
4922
4923         switch (hw->mac.type) {
4924         case e1000_i210:
4925         case e1000_i211:
4926                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4927                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4928                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4929                                 * NSEC_PER_SEC;
4930                 break;
4931         case e1000_82580:
4932         case e1000_i350:
4933         case e1000_i354:
4934                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4935                 /* Only the 8 LSB are valid. */
4936                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4937                                 & 0xff) << 32;
4938                 break;
4939         default:
4940                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4941                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4942                                 << 32;
4943                 break;
4944         }
4945
4946         return tx_tstamp_cycles;
4947 }
4948
4949 static void
4950 igb_start_timecounters(struct rte_eth_dev *dev)
4951 {
4952         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4953         struct e1000_adapter *adapter =
4954                 (struct e1000_adapter *)dev->data->dev_private;
4955         uint32_t incval = 1;
4956         uint32_t shift = 0;
4957         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4958
4959         switch (hw->mac.type) {
4960         case e1000_82580:
4961         case e1000_i350:
4962         case e1000_i354:
4963                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4964                 mask = (1ULL << 40) - 1;
4965                 /* fall-through */
4966         case e1000_i210:
4967         case e1000_i211:
4968                 /*
4969                  * Start incrementing the register
4970                  * used to timestamp PTP packets.
4971                  */
4972                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4973                 break;
4974         case e1000_82576:
4975                 incval = E1000_INCVALUE_82576;
4976                 shift = IGB_82576_TSYNC_SHIFT;
4977                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4978                                 E1000_INCPERIOD_82576 | incval);
4979                 break;
4980         default:
4981                 /* Not supported */
4982                 return;
4983         }
4984
4985         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4986         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4987         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4988
4989         adapter->systime_tc.cc_mask = mask;
4990         adapter->systime_tc.cc_shift = shift;
4991         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4992
4993         adapter->rx_tstamp_tc.cc_mask = mask;
4994         adapter->rx_tstamp_tc.cc_shift = shift;
4995         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4996
4997         adapter->tx_tstamp_tc.cc_mask = mask;
4998         adapter->tx_tstamp_tc.cc_shift = shift;
4999         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5000 }
5001
5002 static int
5003 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5004 {
5005         struct e1000_adapter *adapter =
5006                         (struct e1000_adapter *)dev->data->dev_private;
5007
5008         adapter->systime_tc.nsec += delta;
5009         adapter->rx_tstamp_tc.nsec += delta;
5010         adapter->tx_tstamp_tc.nsec += delta;
5011
5012         return 0;
5013 }
5014
5015 static int
5016 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5017 {
5018         uint64_t ns;
5019         struct e1000_adapter *adapter =
5020                         (struct e1000_adapter *)dev->data->dev_private;
5021
5022         ns = rte_timespec_to_ns(ts);
5023
5024         /* Set the timecounters to a new value. */
5025         adapter->systime_tc.nsec = ns;
5026         adapter->rx_tstamp_tc.nsec = ns;
5027         adapter->tx_tstamp_tc.nsec = ns;
5028
5029         return 0;
5030 }
5031
5032 static int
5033 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5034 {
5035         uint64_t ns, systime_cycles;
5036         struct e1000_adapter *adapter =
5037                         (struct e1000_adapter *)dev->data->dev_private;
5038
5039         systime_cycles = igb_read_systime_cyclecounter(dev);
5040         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5041         *ts = rte_ns_to_timespec(ns);
5042
5043         return 0;
5044 }
5045
5046 static int
5047 igb_timesync_enable(struct rte_eth_dev *dev)
5048 {
5049         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5050         uint32_t tsync_ctl;
5051         uint32_t tsauxc;
5052
5053         /* Stop the timesync system time. */
5054         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5055         /* Reset the timesync system time value. */
5056         switch (hw->mac.type) {
5057         case e1000_82580:
5058         case e1000_i350:
5059         case e1000_i354:
5060         case e1000_i210:
5061         case e1000_i211:
5062                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5063                 /* fall-through */
5064         case e1000_82576:
5065                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5066                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5067                 break;
5068         default:
5069                 /* Not supported. */
5070                 return -ENOTSUP;
5071         }
5072
5073         /* Enable system time for it isn't on by default. */
5074         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5075         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5076         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5077
5078         igb_start_timecounters(dev);
5079
5080         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5081         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5082                         (ETHER_TYPE_1588 |
5083                          E1000_ETQF_FILTER_ENABLE |
5084                          E1000_ETQF_1588));
5085
5086         /* Enable timestamping of received PTP packets. */
5087         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5088         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5089         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5090
5091         /* Enable Timestamping of transmitted PTP packets. */
5092         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5093         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5094         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5095
5096         return 0;
5097 }
5098
5099 static int
5100 igb_timesync_disable(struct rte_eth_dev *dev)
5101 {
5102         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5103         uint32_t tsync_ctl;
5104
5105         /* Disable timestamping of transmitted PTP packets. */
5106         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5107         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5108         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5109
5110         /* Disable timestamping of received PTP packets. */
5111         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5112         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5113         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5114
5115         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5116         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5117
5118         /* Stop incrementating the System Time registers. */
5119         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5120
5121         return 0;
5122 }
5123
5124 static int
5125 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5126                                struct timespec *timestamp,
5127                                uint32_t flags __rte_unused)
5128 {
5129         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5130         struct e1000_adapter *adapter =
5131                         (struct e1000_adapter *)dev->data->dev_private;
5132         uint32_t tsync_rxctl;
5133         uint64_t rx_tstamp_cycles;
5134         uint64_t ns;
5135
5136         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5137         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5138                 return -EINVAL;
5139
5140         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5141         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5142         *timestamp = rte_ns_to_timespec(ns);
5143
5144         return  0;
5145 }
5146
5147 static int
5148 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5149                                struct timespec *timestamp)
5150 {
5151         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5152         struct e1000_adapter *adapter =
5153                         (struct e1000_adapter *)dev->data->dev_private;
5154         uint32_t tsync_txctl;
5155         uint64_t tx_tstamp_cycles;
5156         uint64_t ns;
5157
5158         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5159         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5160                 return -EINVAL;
5161
5162         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5163         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5164         *timestamp = rte_ns_to_timespec(ns);
5165
5166         return  0;
5167 }
5168
5169 static int
5170 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5171 {
5172         int count = 0;
5173         int g_ind = 0;
5174         const struct reg_info *reg_group;
5175
5176         while ((reg_group = igb_regs[g_ind++]))
5177                 count += igb_reg_group_count(reg_group);
5178
5179         return count;
5180 }
5181
5182 static int
5183 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5184 {
5185         int count = 0;
5186         int g_ind = 0;
5187         const struct reg_info *reg_group;
5188
5189         while ((reg_group = igbvf_regs[g_ind++]))
5190                 count += igb_reg_group_count(reg_group);
5191
5192         return count;
5193 }
5194
5195 static int
5196 eth_igb_get_regs(struct rte_eth_dev *dev,
5197         struct rte_dev_reg_info *regs)
5198 {
5199         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5200         uint32_t *data = regs->data;
5201         int g_ind = 0;
5202         int count = 0;
5203         const struct reg_info *reg_group;
5204
5205         if (data == NULL) {
5206                 regs->length = eth_igb_get_reg_length(dev);
5207                 regs->width = sizeof(uint32_t);
5208                 return 0;
5209         }
5210
5211         /* Support only full register dump */
5212         if ((regs->length == 0) ||
5213             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5214                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5215                         hw->device_id;
5216                 while ((reg_group = igb_regs[g_ind++]))
5217                         count += igb_read_regs_group(dev, &data[count],
5218                                                         reg_group);
5219                 return 0;
5220         }
5221
5222         return -ENOTSUP;
5223 }
5224
5225 static int
5226 igbvf_get_regs(struct rte_eth_dev *dev,
5227         struct rte_dev_reg_info *regs)
5228 {
5229         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5230         uint32_t *data = regs->data;
5231         int g_ind = 0;
5232         int count = 0;
5233         const struct reg_info *reg_group;
5234
5235         if (data == NULL) {
5236                 regs->length = igbvf_get_reg_length(dev);
5237                 regs->width = sizeof(uint32_t);
5238                 return 0;
5239         }
5240
5241         /* Support only full register dump */
5242         if ((regs->length == 0) ||
5243             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5244                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5245                         hw->device_id;
5246                 while ((reg_group = igbvf_regs[g_ind++]))
5247                         count += igb_read_regs_group(dev, &data[count],
5248                                                         reg_group);
5249                 return 0;
5250         }
5251
5252         return -ENOTSUP;
5253 }
5254
5255 static int
5256 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5257 {
5258         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5259
5260         /* Return unit is byte count */
5261         return hw->nvm.word_size * 2;
5262 }
5263
5264 static int
5265 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5266         struct rte_dev_eeprom_info *in_eeprom)
5267 {
5268         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5269         struct e1000_nvm_info *nvm = &hw->nvm;
5270         uint16_t *data = in_eeprom->data;
5271         int first, length;
5272
5273         first = in_eeprom->offset >> 1;
5274         length = in_eeprom->length >> 1;
5275         if ((first >= hw->nvm.word_size) ||
5276             ((first + length) >= hw->nvm.word_size))
5277                 return -EINVAL;
5278
5279         in_eeprom->magic = hw->vendor_id |
5280                 ((uint32_t)hw->device_id << 16);
5281
5282         if ((nvm->ops.read) == NULL)
5283                 return -ENOTSUP;
5284
5285         return nvm->ops.read(hw, first, length, data);
5286 }
5287
5288 static int
5289 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5290         struct rte_dev_eeprom_info *in_eeprom)
5291 {
5292         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5293         struct e1000_nvm_info *nvm = &hw->nvm;
5294         uint16_t *data = in_eeprom->data;
5295         int first, length;
5296
5297         first = in_eeprom->offset >> 1;
5298         length = in_eeprom->length >> 1;
5299         if ((first >= hw->nvm.word_size) ||
5300             ((first + length) >= hw->nvm.word_size))
5301                 return -EINVAL;
5302
5303         in_eeprom->magic = (uint32_t)hw->vendor_id |
5304                 ((uint32_t)hw->device_id << 16);
5305
5306         if ((nvm->ops.write) == NULL)
5307                 return -ENOTSUP;
5308         return nvm->ops.write(hw,  first, length, data);
5309 }
5310
5311 static int
5312 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5313 {
5314         struct e1000_hw *hw =
5315                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5316         uint32_t mask = 1 << queue_id;
5317
5318         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5319         E1000_WRITE_FLUSH(hw);
5320
5321         return 0;
5322 }
5323
5324 static int
5325 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5326 {
5327         struct e1000_hw *hw =
5328                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5329         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5330         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5331         uint32_t mask = 1 << queue_id;
5332         uint32_t regval;
5333
5334         regval = E1000_READ_REG(hw, E1000_EIMS);
5335         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5336         E1000_WRITE_FLUSH(hw);
5337
5338         rte_intr_enable(intr_handle);
5339
5340         return 0;
5341 }
5342
5343 static void
5344 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5345                    uint8_t index, uint8_t offset)
5346 {
5347         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5348
5349         /* clear bits */
5350         val &= ~((uint32_t)0xFF << offset);
5351
5352         /* write vector and valid bit */
5353         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5354
5355         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5356 }
5357
5358 static void
5359 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5360                            uint8_t queue, uint8_t msix_vector)
5361 {
5362         uint32_t tmp = 0;
5363
5364         if (hw->mac.type == e1000_82575) {
5365                 if (direction == 0)
5366                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5367                 else if (direction == 1)
5368                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5369                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5370         } else if (hw->mac.type == e1000_82576) {
5371                 if ((direction == 0) || (direction == 1))
5372                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5373                                            ((queue & 0x8) << 1) +
5374                                            8 * direction);
5375         } else if ((hw->mac.type == e1000_82580) ||
5376                         (hw->mac.type == e1000_i350) ||
5377                         (hw->mac.type == e1000_i354) ||
5378                         (hw->mac.type == e1000_i210) ||
5379                         (hw->mac.type == e1000_i211)) {
5380                 if ((direction == 0) || (direction == 1))
5381                         eth_igb_write_ivar(hw, msix_vector,
5382                                            queue >> 1,
5383                                            ((queue & 0x1) << 4) +
5384                                            8 * direction);
5385         }
5386 }
5387
5388 /* Sets up the hardware to generate MSI-X interrupts properly
5389  * @hw
5390  *  board private structure
5391  */
5392 static void
5393 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5394 {
5395         int queue_id;
5396         uint32_t tmpval, regval, intr_mask;
5397         struct e1000_hw *hw =
5398                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5399         uint32_t vec = E1000_MISC_VEC_ID;
5400         uint32_t base = E1000_MISC_VEC_ID;
5401         uint32_t misc_shift = 0;
5402         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5403         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5404
5405         /* won't configure msix register if no mapping is done
5406          * between intr vector and event fd
5407          */
5408         if (!rte_intr_dp_is_en(intr_handle))
5409                 return;
5410
5411         if (rte_intr_allow_others(intr_handle)) {
5412                 vec = base = E1000_RX_VEC_START;
5413                 misc_shift = 1;
5414         }
5415
5416         /* set interrupt vector for other causes */
5417         if (hw->mac.type == e1000_82575) {
5418                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5419                 /* enable MSI-X PBA support */
5420                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5421
5422                 /* Auto-Mask interrupts upon ICR read */
5423                 tmpval |= E1000_CTRL_EXT_EIAME;
5424                 tmpval |= E1000_CTRL_EXT_IRCA;
5425
5426                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5427
5428                 /* enable msix_other interrupt */
5429                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5430                 regval = E1000_READ_REG(hw, E1000_EIAC);
5431                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5432                 regval = E1000_READ_REG(hw, E1000_EIAM);
5433                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5434         } else if ((hw->mac.type == e1000_82576) ||
5435                         (hw->mac.type == e1000_82580) ||
5436                         (hw->mac.type == e1000_i350) ||
5437                         (hw->mac.type == e1000_i354) ||
5438                         (hw->mac.type == e1000_i210) ||
5439                         (hw->mac.type == e1000_i211)) {
5440                 /* turn on MSI-X capability first */
5441                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5442                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5443                                         E1000_GPIE_NSICR);
5444                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5445                         misc_shift;
5446                 regval = E1000_READ_REG(hw, E1000_EIAC);
5447                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5448
5449                 /* enable msix_other interrupt */
5450                 regval = E1000_READ_REG(hw, E1000_EIMS);
5451                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5452                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5453                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5454         }
5455
5456         /* use EIAM to auto-mask when MSI-X interrupt
5457          * is asserted, this saves a register write for every interrupt
5458          */
5459         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5460                 misc_shift;
5461         regval = E1000_READ_REG(hw, E1000_EIAM);
5462         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5463
5464         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5465                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5466                 intr_handle->intr_vec[queue_id] = vec;
5467                 if (vec < base + intr_handle->nb_efd - 1)
5468                         vec++;
5469         }
5470
5471         E1000_WRITE_FLUSH(hw);
5472 }
5473
5474 /* restore n-tuple filter */
5475 static inline void
5476 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5477 {
5478         struct e1000_filter_info *filter_info =
5479                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5480         struct e1000_5tuple_filter *p_5tuple;
5481         struct e1000_2tuple_filter *p_2tuple;
5482
5483         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5484                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5485         }
5486
5487         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5488                 igb_inject_2uple_filter(dev, p_2tuple);
5489         }
5490 }
5491
5492 /* restore SYN filter */
5493 static inline void
5494 igb_syn_filter_restore(struct rte_eth_dev *dev)
5495 {
5496         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5497         struct e1000_filter_info *filter_info =
5498                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5499         uint32_t synqf;
5500
5501         synqf = filter_info->syn_info;
5502
5503         if (synqf & E1000_SYN_FILTER_ENABLE) {
5504                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5505                 E1000_WRITE_FLUSH(hw);
5506         }
5507 }
5508
5509 /* restore all types filter */
5510 static int
5511 igb_filter_restore(struct rte_eth_dev *dev)
5512 {
5513         igb_ntuple_filter_restore(dev);
5514         igb_syn_filter_restore(dev);
5515
5516         return 0;
5517 }
5518
5519 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5520 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5521 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5522 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5523 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5524 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");