drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_string_fns.h>
  12 #include <rte_common.h>
  13 #include <rte_interrupts.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_log.h>
  16 #include <rte_debug.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memory.h>
  23 #include <rte_eal.h>
  24 #include <rte_malloc.h>
  25 #include <rte_dev.h>
  26
  27 #include "e1000_logs.h"
  28 #include "base/e1000_api.h"
  29 #include "e1000_ethdev.h"
  30 #include "igb_regs.h"
  31
  32 /*
  33  * Default values for port configuration
  34  */
  35 #define IGB_DEFAULT_RX_FREE_THRESH  32
  36
  37 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  38 #define IGB_DEFAULT_RX_HTHRESH      8
  39 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  40
  41 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  42 #define IGB_DEFAULT_TX_HTHRESH      1
  43 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  44
  45 /* Bit shift and mask */
  46 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  47 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  48 #define IGB_8_BIT_WIDTH  CHAR_BIT
  49 #define IGB_8_BIT_MASK   UINT8_MAX
  50
  51 /* Additional timesync values. */
  52 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  53 #define E1000_ETQF_FILTER_1588       3
  54 #define IGB_82576_TSYNC_SHIFT        16
  55 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  56 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  58
  59 #define E1000_VTIVAR_MISC                0x01740
  60 #define E1000_VTIVAR_MISC_MASK           0xFF
  61 #define E1000_VTIVAR_VALID               0x80
  62 #define E1000_VTIVAR_MISC_MAILBOX        0
  63 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  64
  65 /* External VLAN Enable bit mask */
  66 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  67
  68 /* External VLAN Ether Type bit mask and shift */
  69 #define E1000_VET_VET_EXT            0xFFFF0000
  70 #define E1000_VET_VET_EXT_SHIFT      16
  71
  72 /* MSI-X other interrupt vector */
  73 #define IGB_MSIX_OTHER_INTR_VEC      0
  74
  75 static int  eth_igb_configure(struct rte_eth_dev *dev);
  76 static int  eth_igb_start(struct rte_eth_dev *dev);
  77 static void eth_igb_stop(struct rte_eth_dev *dev);
  78 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  79 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  80 static void eth_igb_close(struct rte_eth_dev *dev);
  81 static int eth_igb_reset(struct rte_eth_dev *dev);
  82 static int  eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  83 static int  eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  84 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  85 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  87                                 int wait_to_complete);
  88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  89                                 struct rte_eth_stats *rte_stats);
  90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  91                               struct rte_eth_xstat *xstats, unsigned n);
  92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  93                 const uint64_t *ids,
  94                 uint64_t *values, unsigned int n);
  95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  96                                     struct rte_eth_xstat_name *xstats_names,
  97                                     unsigned int size);
  98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  99                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 100                 unsigned int limit);
 101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
 102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
 103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 104                                    char *fw_version, size_t fw_size);
 105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
 106                               struct rte_eth_dev_info *dev_info);
 107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_dev_info *dev_info);
 110 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 113                                 struct rte_eth_fc_conf *fc_conf);
 114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 118                                     struct rte_intr_handle *handle);
 119 static void eth_igb_interrupt_handler(void *param);
 120 static int  igb_hardware_init(struct e1000_hw *hw);
 121 static void igb_hw_control_acquire(struct e1000_hw *hw);
 122 static void igb_hw_control_release(struct e1000_hw *hw);
 123 static void igb_init_manageability(struct e1000_hw *hw);
 124 static void igb_release_manageability(struct e1000_hw *hw);
 125
 126 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 127
 128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 129                 uint16_t vlan_id, int on);
 130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 131                                  enum rte_vlan_type vlan_type,
 132                                  uint16_t tpid_id);
 133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134
 135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 141
 142 static int eth_igb_led_on(struct rte_eth_dev *dev);
 143 static int eth_igb_led_off(struct rte_eth_dev *dev);
 144
 145 static void igb_intr_disable(struct rte_eth_dev *dev);
 146 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 148                            struct rte_ether_addr *mac_addr,
 149                            uint32_t index, uint32_t pool);
 150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 152                 struct rte_ether_addr *addr);
 153
 154 static void igbvf_intr_disable(struct e1000_hw *hw);
 155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 156 static int igbvf_dev_start(struct rte_eth_dev *dev);
 157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 158 static void igbvf_dev_close(struct rte_eth_dev *dev);
 159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 161 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 162 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 163 static int eth_igbvf_link_update(struct e1000_hw *hw);
 164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_stats *rte_stats);
 166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 167                                 struct rte_eth_xstat *xstats, unsigned n);
 168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 169                                       struct rte_eth_xstat_name *xstats_names,
 170                                       unsigned limit);
 171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 173                 uint16_t vlan_id, int on);
 174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 177                 struct rte_ether_addr *addr);
 178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 179 static int igbvf_get_regs(struct rte_eth_dev *dev,
 180                 struct rte_dev_reg_info *regs);
 181
 182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 183                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                    uint16_t reta_size);
 185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 186                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 187                                   uint16_t reta_size);
 188
 189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 190                         struct rte_eth_syn_filter *filter);
 191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 192                         enum rte_filter_op filter_op,
 193                         void *arg);
 194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_ntuple_filter *ntuple_filter);
 198 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 199                         struct rte_eth_flex_filter *filter);
 200 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 201                         enum rte_filter_op filter_op,
 202                         void *arg);
 203 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 204                         struct rte_eth_ntuple_filter *ntuple_filter);
 205 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 206                         struct rte_eth_ntuple_filter *ntuple_filter);
 207 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 208                         struct rte_eth_ntuple_filter *filter);
 209 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 213                                 enum rte_filter_op filter_op,
 214                                 void *arg);
 215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ethertype_filter *filter);
 217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 218                      enum rte_filter_type filter_type,
 219                      enum rte_filter_op filter_op,
 220                      void *arg);
 221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 223                 struct rte_dev_reg_info *regs);
 224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 226                 struct rte_dev_eeprom_info *eeprom);
 227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 228                 struct rte_dev_eeprom_info *eeprom);
 229 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
 230                                    struct rte_eth_dev_module_info *modinfo);
 231 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
 232                                      struct rte_dev_eeprom_info *info);
 233 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 234                                     struct rte_ether_addr *mc_addr_set,
 235                                     uint32_t nb_mc_addr);
 236 static int igb_timesync_enable(struct rte_eth_dev *dev);
 237 static int igb_timesync_disable(struct rte_eth_dev *dev);
 238 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 239                                           struct timespec *timestamp,
 240                                           uint32_t flags);
 241 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 242                                           struct timespec *timestamp);
 243 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 244 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 245                                   struct timespec *timestamp);
 246 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 247                                    const struct timespec *timestamp);
 248 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 249                                         uint16_t queue_id);
 250 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 251                                          uint16_t queue_id);
 252 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 253                                        uint8_t queue, uint8_t msix_vector);
 254 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 255                                uint8_t index, uint8_t offset);
 256 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 257 static void eth_igbvf_interrupt_handler(void *param);
 258 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 259 static int igb_filter_restore(struct rte_eth_dev *dev);
 260
 261 /*
 262  * Define VF Stats MACRO for Non "cleared on read" register
 263  */
 264 #define UPDATE_VF_STAT(reg, last, cur)            \
 265 {                                                 \
 266         u32 latest = E1000_READ_REG(hw, reg);     \
 267         cur += (latest - last) & UINT_MAX;        \
 268         last = latest;                            \
 269 }
 270
 271 #define IGB_FC_PAUSE_TIME 0x0680
 272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 274
 275 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 276
 277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 278
 279 /*
 280  * The set of PCI devices this driver supports
 281  */
 282 static const struct rte_pci_id pci_id_igb_map[] = {
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 284         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 285         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 286         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 287         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 288         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 289         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 290         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 291
 292         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 295
 296         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 297         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 302
 303         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 304         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 305         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 324         { .vendor_id = 0, /* sentinel */ },
 325 };
 326
 327 /*
 328  * The set of PCI devices this driver supports (for 82576&I350 VF)
 329  */
 330 static const struct rte_pci_id pci_id_igbvf_map[] = {
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 335         { .vendor_id = 0, /* sentinel */ },
 336 };
 337
 338 static const struct rte_eth_desc_lim rx_desc_lim = {
 339         .nb_max = E1000_MAX_RING_DESC,
 340         .nb_min = E1000_MIN_RING_DESC,
 341         .nb_align = IGB_RXD_ALIGN,
 342 };
 343
 344 static const struct rte_eth_desc_lim tx_desc_lim = {
 345         .nb_max = E1000_MAX_RING_DESC,
 346         .nb_min = E1000_MIN_RING_DESC,
 347         .nb_align = IGB_RXD_ALIGN,
 348         .nb_seg_max = IGB_TX_MAX_SEG,
 349         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 350 };
 351
 352 static const struct eth_dev_ops eth_igb_ops = {
 353         .dev_configure        = eth_igb_configure,
 354         .dev_start            = eth_igb_start,
 355         .dev_stop             = eth_igb_stop,
 356         .dev_set_link_up      = eth_igb_dev_set_link_up,
 357         .dev_set_link_down    = eth_igb_dev_set_link_down,
 358         .dev_close            = eth_igb_close,
 359         .dev_reset            = eth_igb_reset,
 360         .promiscuous_enable   = eth_igb_promiscuous_enable,
 361         .promiscuous_disable  = eth_igb_promiscuous_disable,
 362         .allmulticast_enable  = eth_igb_allmulticast_enable,
 363         .allmulticast_disable = eth_igb_allmulticast_disable,
 364         .link_update          = eth_igb_link_update,
 365         .stats_get            = eth_igb_stats_get,
 366         .xstats_get           = eth_igb_xstats_get,
 367         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 368         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 369         .xstats_get_names     = eth_igb_xstats_get_names,
 370         .stats_reset          = eth_igb_stats_reset,
 371         .xstats_reset         = eth_igb_xstats_reset,
 372         .fw_version_get       = eth_igb_fw_version_get,
 373         .dev_infos_get        = eth_igb_infos_get,
 374         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 375         .mtu_set              = eth_igb_mtu_set,
 376         .vlan_filter_set      = eth_igb_vlan_filter_set,
 377         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 378         .vlan_offload_set     = eth_igb_vlan_offload_set,
 379         .rx_queue_setup       = eth_igb_rx_queue_setup,
 380         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 381         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 382         .rx_queue_release     = eth_igb_rx_queue_release,
 383         .rx_queue_count       = eth_igb_rx_queue_count,
 384         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 385         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 386         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 387         .tx_queue_setup       = eth_igb_tx_queue_setup,
 388         .tx_queue_release     = eth_igb_tx_queue_release,
 389         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 390         .dev_led_on           = eth_igb_led_on,
 391         .dev_led_off          = eth_igb_led_off,
 392         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 393         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 394         .mac_addr_add         = eth_igb_rar_set,
 395         .mac_addr_remove      = eth_igb_rar_clear,
 396         .mac_addr_set         = eth_igb_default_mac_addr_set,
 397         .reta_update          = eth_igb_rss_reta_update,
 398         .reta_query           = eth_igb_rss_reta_query,
 399         .rss_hash_update      = eth_igb_rss_hash_update,
 400         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 401         .filter_ctrl          = eth_igb_filter_ctrl,
 402         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 403         .rxq_info_get         = igb_rxq_info_get,
 404         .txq_info_get         = igb_txq_info_get,
 405         .timesync_enable      = igb_timesync_enable,
 406         .timesync_disable     = igb_timesync_disable,
 407         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 408         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 409         .get_reg              = eth_igb_get_regs,
 410         .get_eeprom_length    = eth_igb_get_eeprom_length,
 411         .get_eeprom           = eth_igb_get_eeprom,
 412         .set_eeprom           = eth_igb_set_eeprom,
 413         .get_module_info      = eth_igb_get_module_info,
 414         .get_module_eeprom    = eth_igb_get_module_eeprom,
 415         .timesync_adjust_time = igb_timesync_adjust_time,
 416         .timesync_read_time   = igb_timesync_read_time,
 417         .timesync_write_time  = igb_timesync_write_time,
 418 };
 419
 420 /*
 421  * dev_ops for virtual function, bare necessities for basic vf
 422  * operation have been implemented
 423  */
 424 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 425         .dev_configure        = igbvf_dev_configure,
 426         .dev_start            = igbvf_dev_start,
 427         .dev_stop             = igbvf_dev_stop,
 428         .dev_close            = igbvf_dev_close,
 429         .promiscuous_enable   = igbvf_promiscuous_enable,
 430         .promiscuous_disable  = igbvf_promiscuous_disable,
 431         .allmulticast_enable  = igbvf_allmulticast_enable,
 432         .allmulticast_disable = igbvf_allmulticast_disable,
 433         .link_update          = eth_igb_link_update,
 434         .stats_get            = eth_igbvf_stats_get,
 435         .xstats_get           = eth_igbvf_xstats_get,
 436         .xstats_get_names     = eth_igbvf_xstats_get_names,
 437         .stats_reset          = eth_igbvf_stats_reset,
 438         .xstats_reset         = eth_igbvf_stats_reset,
 439         .vlan_filter_set      = igbvf_vlan_filter_set,
 440         .dev_infos_get        = eth_igbvf_infos_get,
 441         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 442         .rx_queue_setup       = eth_igb_rx_queue_setup,
 443         .rx_queue_release     = eth_igb_rx_queue_release,
 444         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 445         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 446         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 447         .tx_queue_setup       = eth_igb_tx_queue_setup,
 448         .tx_queue_release     = eth_igb_tx_queue_release,
 449         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 450         .rxq_info_get         = igb_rxq_info_get,
 451         .txq_info_get         = igb_txq_info_get,
 452         .mac_addr_set         = igbvf_default_mac_addr_set,
 453         .get_reg              = igbvf_get_regs,
 454 };
 455
 456 /* store statistics names and its offset in stats structure */
 457 struct rte_igb_xstats_name_off {
 458         char name[RTE_ETH_XSTATS_NAME_SIZE];
 459         unsigned offset;
 460 };
 461
 462 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 463         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 464         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 465         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 466         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 467         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 468         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 469         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 470                 ecol)},
 471         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 472         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 473         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 474         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 475         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 476         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 477         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 478         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 479         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 480         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 481         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 482                 fcruc)},
 483         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 484         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 485         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 486         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 487         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 488                 prc1023)},
 489         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 490                 prc1522)},
 491         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 492         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 493         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 494         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 495         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 496         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 497         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 498         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 499         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 500         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 501         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 502         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 503         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 504         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 505         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 506         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 507         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 508         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 509                 ptc1023)},
 510         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 511                 ptc1522)},
 512         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 513         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 514         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 515         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 516         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 517         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 518         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 519
 520         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 521 };
 522
 523 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 524                 sizeof(rte_igb_stats_strings[0]))
 525
 526 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 527         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 528         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 529         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 530         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 531         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 532 };
 533
 534 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 535                 sizeof(rte_igbvf_stats_strings[0]))
 536
 537
 538 static inline void
 539 igb_intr_enable(struct rte_eth_dev *dev)
 540 {
 541         struct e1000_interrupt *intr =
 542                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 543         struct e1000_hw *hw =
 544                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 545         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 546         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 547
 548         if (rte_intr_allow_others(intr_handle) &&
 549                 dev->data->dev_conf.intr_conf.lsc != 0) {
 550                 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
 551         }
 552
 553         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 554         E1000_WRITE_FLUSH(hw);
 555 }
 556
 557 static void
 558 igb_intr_disable(struct rte_eth_dev *dev)
 559 {
 560         struct e1000_hw *hw =
 561                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 562         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 563         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 564
 565         if (rte_intr_allow_others(intr_handle) &&
 566                 dev->data->dev_conf.intr_conf.lsc != 0) {
 567                 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
 568         }
 569
 570         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 571         E1000_WRITE_FLUSH(hw);
 572 }
 573
 574 static inline void
 575 igbvf_intr_enable(struct rte_eth_dev *dev)
 576 {
 577         struct e1000_hw *hw =
 578                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 579
 580         /* only for mailbox */
 581         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 582         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 583         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 584         E1000_WRITE_FLUSH(hw);
 585 }
 586
 587 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 588 static void
 589 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 590 {
 591         uint32_t tmp = 0;
 592
 593         /* mailbox */
 594         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 595         tmp |= E1000_VTIVAR_VALID;
 596         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 597 }
 598
 599 static void
 600 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 601 {
 602         struct e1000_hw *hw =
 603                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 604
 605         /* Configure VF other cause ivar */
 606         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 607 }
 608
 609 static inline int32_t
 610 igb_pf_reset_hw(struct e1000_hw *hw)
 611 {
 612         uint32_t ctrl_ext;
 613         int32_t status;
 614
 615         status = e1000_reset_hw(hw);
 616
 617         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 618         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 619         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 620         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 621         E1000_WRITE_FLUSH(hw);
 622
 623         return status;
 624 }
 625
 626 static void
 627 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 628 {
 629         struct e1000_hw *hw =
 630                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 631
 632
 633         hw->vendor_id = pci_dev->id.vendor_id;
 634         hw->device_id = pci_dev->id.device_id;
 635         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 636         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 637
 638         e1000_set_mac_type(hw);
 639
 640         /* need to check if it is a vf device below */
 641 }
 642
 643 static int
 644 igb_reset_swfw_lock(struct e1000_hw *hw)
 645 {
 646         int ret_val;
 647
 648         /*
 649          * Do mac ops initialization manually here, since we will need
 650          * some function pointers set by this call.
 651          */
 652         ret_val = e1000_init_mac_params(hw);
 653         if (ret_val)
 654                 return ret_val;
 655
 656         /*
 657          * SMBI lock should not fail in this early stage. If this is the case,
 658          * it is due to an improper exit of the application.
 659          * So force the release of the faulty lock.
 660          */
 661         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 662                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 663         }
 664         e1000_put_hw_semaphore_generic(hw);
 665
 666         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 667                 uint16_t mask;
 668
 669                 /*
 670                  * Phy lock should not fail in this early stage. If this is the case,
 671                  * it is due to an improper exit of the application.
 672                  * So force the release of the faulty lock.
 673                  */
 674                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 675                 if (hw->bus.func > E1000_FUNC_1)
 676                         mask <<= 2;
 677                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 678                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 679                                     hw->bus.func);
 680                 }
 681                 hw->mac.ops.release_swfw_sync(hw, mask);
 682
 683                 /*
 684                  * This one is more tricky since it is common to all ports; but
 685                  * swfw_sync retries last long enough (1s) to be almost sure that if
 686                  * lock can not be taken it is due to an improper lock of the
 687                  * semaphore.
 688                  */
 689                 mask = E1000_SWFW_EEP_SM;
 690                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 691                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 692                 }
 693                 hw->mac.ops.release_swfw_sync(hw, mask);
 694         }
 695
 696         return E1000_SUCCESS;
 697 }
 698
 699 /* Remove all ntuple filters of the device */
 700 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 701 {
 702         struct e1000_filter_info *filter_info =
 703                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 704         struct e1000_5tuple_filter *p_5tuple;
 705         struct e1000_2tuple_filter *p_2tuple;
 706
 707         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 708                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 709                         p_5tuple, entries);
 710                         rte_free(p_5tuple);
 711         }
 712         filter_info->fivetuple_mask = 0;
 713         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 714                 TAILQ_REMOVE(&filter_info->twotuple_list,
 715                         p_2tuple, entries);
 716                         rte_free(p_2tuple);
 717         }
 718         filter_info->twotuple_mask = 0;
 719
 720         return 0;
 721 }
 722
 723 /* Remove all flex filters of the device */
 724 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 725 {
 726         struct e1000_filter_info *filter_info =
 727                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 728         struct e1000_flex_filter *p_flex;
 729
 730         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 731                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 732                 rte_free(p_flex);
 733         }
 734         filter_info->flex_mask = 0;
 735
 736         return 0;
 737 }
 738
 739 static int
 740 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 741 {
 742         int error = 0;
 743         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 744         struct e1000_hw *hw =
 745                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 746         struct e1000_vfta * shadow_vfta =
 747                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 748         struct e1000_filter_info *filter_info =
 749                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 750         struct e1000_adapter *adapter =
 751                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 752
 753         uint32_t ctrl_ext;
 754
 755         eth_dev->dev_ops = &eth_igb_ops;
 756         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 757         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 758         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 759
 760         /* for secondary processes, we don't initialise any further as primary
 761          * has already done this work. Only check we don't need a different
 762          * RX function */
 763         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 764                 if (eth_dev->data->scattered_rx)
 765                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 766                 return 0;
 767         }
 768
 769         rte_eth_copy_pci_info(eth_dev, pci_dev);
 770
 771         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 772
 773         igb_identify_hardware(eth_dev, pci_dev);
 774         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 775                 error = -EIO;
 776                 goto err_late;
 777         }
 778
 779         e1000_get_bus_info(hw);
 780
 781         /* Reset any pending lock */
 782         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 783                 error = -EIO;
 784                 goto err_late;
 785         }
 786
 787         /* Finish initialization */
 788         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 789                 error = -EIO;
 790                 goto err_late;
 791         }
 792
 793         hw->mac.autoneg = 1;
 794         hw->phy.autoneg_wait_to_complete = 0;
 795         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 796
 797         /* Copper options */
 798         if (hw->phy.media_type == e1000_media_type_copper) {
 799                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 800                 hw->phy.disable_polarity_correction = 0;
 801                 hw->phy.ms_type = e1000_ms_hw_default;
 802         }
 803
 804         /*
 805          * Start from a known state, this is important in reading the nvm
 806          * and mac from that.
 807          */
 808         igb_pf_reset_hw(hw);
 809
 810         /* Make sure we have a good EEPROM before we read from it */
 811         if (e1000_validate_nvm_checksum(hw) < 0) {
 812                 /*
 813                  * Some PCI-E parts fail the first check due to
 814                  * the link being in sleep state, call it again,
 815                  * if it fails a second time its a real issue.
 816                  */
 817                 if (e1000_validate_nvm_checksum(hw) < 0) {
 818                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 819                         error = -EIO;
 820                         goto err_late;
 821                 }
 822         }
 823
 824         /* Read the permanent MAC address out of the EEPROM */
 825         if (e1000_read_mac_addr(hw) != 0) {
 826                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 827                 error = -EIO;
 828                 goto err_late;
 829         }
 830
 831         /* Allocate memory for storing MAC addresses */
 832         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 833                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 834         if (eth_dev->data->mac_addrs == NULL) {
 835                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 836                                                 "store MAC addresses",
 837                                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 838                 error = -ENOMEM;
 839                 goto err_late;
 840         }
 841
 842         /* Copy the permanent MAC address */
 843         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 844                         &eth_dev->data->mac_addrs[0]);
 845
 846         /* initialize the vfta */
 847         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 848
 849         /* Now initialize the hardware */
 850         if (igb_hardware_init(hw) != 0) {
 851                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 852                 rte_free(eth_dev->data->mac_addrs);
 853                 eth_dev->data->mac_addrs = NULL;
 854                 error = -ENODEV;
 855                 goto err_late;
 856         }
 857         hw->mac.get_link_status = 1;
 858         adapter->stopped = 0;
 859
 860         /* Indicate SOL/IDER usage */
 861         if (e1000_check_reset_block(hw) < 0) {
 862                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 863                                         "SOL/IDER session");
 864         }
 865
 866         /* initialize PF if max_vfs not zero */
 867         igb_pf_host_init(eth_dev);
 868
 869         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 870         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 871         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 872         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 873         E1000_WRITE_FLUSH(hw);
 874
 875         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 876                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 877                      pci_dev->id.device_id);
 878
 879         rte_intr_callback_register(&pci_dev->intr_handle,
 880                                    eth_igb_interrupt_handler,
 881                                    (void *)eth_dev);
 882
 883         /* enable uio/vfio intr/eventfd mapping */
 884         rte_intr_enable(&pci_dev->intr_handle);
 885
 886         /* enable support intr */
 887         igb_intr_enable(eth_dev);
 888
 889         /* initialize filter info */
 890         memset(filter_info, 0,
 891                sizeof(struct e1000_filter_info));
 892
 893         TAILQ_INIT(&filter_info->flex_list);
 894         TAILQ_INIT(&filter_info->twotuple_list);
 895         TAILQ_INIT(&filter_info->fivetuple_list);
 896
 897         TAILQ_INIT(&igb_filter_ntuple_list);
 898         TAILQ_INIT(&igb_filter_ethertype_list);
 899         TAILQ_INIT(&igb_filter_syn_list);
 900         TAILQ_INIT(&igb_filter_flex_list);
 901         TAILQ_INIT(&igb_filter_rss_list);
 902         TAILQ_INIT(&igb_flow_list);
 903
 904         return 0;
 905
 906 err_late:
 907         igb_hw_control_release(hw);
 908
 909         return error;
 910 }
 911
 912 static int
 913 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 914 {
 915         struct rte_pci_device *pci_dev;
 916         struct rte_intr_handle *intr_handle;
 917         struct e1000_hw *hw;
 918         struct e1000_adapter *adapter =
 919                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 920         struct e1000_filter_info *filter_info =
 921                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 922
 923         PMD_INIT_FUNC_TRACE();
 924
 925         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 926                 return -EPERM;
 927
 928         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 929         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 930         intr_handle = &pci_dev->intr_handle;
 931
 932         if (adapter->stopped == 0)
 933                 eth_igb_close(eth_dev);
 934
 935         eth_dev->dev_ops = NULL;
 936         eth_dev->rx_pkt_burst = NULL;
 937         eth_dev->tx_pkt_burst = NULL;
 938
 939         /* Reset any pending lock */
 940         igb_reset_swfw_lock(hw);
 941
 942         /* uninitialize PF if max_vfs not zero */
 943         igb_pf_host_uninit(eth_dev);
 944
 945         /* disable uio intr before callback unregister */
 946         rte_intr_disable(intr_handle);
 947         rte_intr_callback_unregister(intr_handle,
 948                                      eth_igb_interrupt_handler, eth_dev);
 949
 950         /* clear the SYN filter info */
 951         filter_info->syn_info = 0;
 952
 953         /* clear the ethertype filters info */
 954         filter_info->ethertype_mask = 0;
 955         memset(filter_info->ethertype_filters, 0,
 956                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
 957
 958         /* clear the rss filter info */
 959         memset(&filter_info->rss_info, 0,
 960                 sizeof(struct igb_rte_flow_rss_conf));
 961
 962         /* remove all ntuple filters of the device */
 963         igb_ntuple_filter_uninit(eth_dev);
 964
 965         /* remove all flex filters of the device */
 966         igb_flex_filter_uninit(eth_dev);
 967
 968         /* clear all the filters list */
 969         igb_filterlist_flush(eth_dev);
 970
 971         return 0;
 972 }
 973
 974 /*
 975  * Virtual Function device init
 976  */
 977 static int
 978 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 979 {
 980         struct rte_pci_device *pci_dev;
 981         struct rte_intr_handle *intr_handle;
 982         struct e1000_adapter *adapter =
 983                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 984         struct e1000_hw *hw =
 985                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 986         int diag;
 987         struct rte_ether_addr *perm_addr =
 988                 (struct rte_ether_addr *)hw->mac.perm_addr;
 989
 990         PMD_INIT_FUNC_TRACE();
 991
 992         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 993         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 994         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 995         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 996
 997         /* for secondary processes, we don't initialise any further as primary
 998          * has already done this work. Only check we don't need a different
 999          * RX function */
1000         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1001                 if (eth_dev->data->scattered_rx)
1002                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
1003                 return 0;
1004         }
1005
1006         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1007         rte_eth_copy_pci_info(eth_dev, pci_dev);
1008
1009         hw->device_id = pci_dev->id.device_id;
1010         hw->vendor_id = pci_dev->id.vendor_id;
1011         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1012         adapter->stopped = 0;
1013
1014         /* Initialize the shared code (base driver) */
1015         diag = e1000_setup_init_funcs(hw, TRUE);
1016         if (diag != 0) {
1017                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1018                         diag);
1019                 return -EIO;
1020         }
1021
1022         /* init_mailbox_params */
1023         hw->mbx.ops.init_params(hw);
1024
1025         /* Disable the interrupts for VF */
1026         igbvf_intr_disable(hw);
1027
1028         diag = hw->mac.ops.reset_hw(hw);
1029
1030         /* Allocate memory for storing MAC addresses */
1031         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
1032                 hw->mac.rar_entry_count, 0);
1033         if (eth_dev->data->mac_addrs == NULL) {
1034                 PMD_INIT_LOG(ERR,
1035                         "Failed to allocate %d bytes needed to store MAC "
1036                         "addresses",
1037                         RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1038                 return -ENOMEM;
1039         }
1040
1041         /* Generate a random MAC address, if none was assigned by PF. */
1042         if (rte_is_zero_ether_addr(perm_addr)) {
1043                 rte_eth_random_addr(perm_addr->addr_bytes);
1044                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1045                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1046                              "%02x:%02x:%02x:%02x:%02x:%02x",
1047                              perm_addr->addr_bytes[0],
1048                              perm_addr->addr_bytes[1],
1049                              perm_addr->addr_bytes[2],
1050                              perm_addr->addr_bytes[3],
1051                              perm_addr->addr_bytes[4],
1052                              perm_addr->addr_bytes[5]);
1053         }
1054
1055         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1056         if (diag) {
1057                 rte_free(eth_dev->data->mac_addrs);
1058                 eth_dev->data->mac_addrs = NULL;
1059                 return diag;
1060         }
1061         /* Copy the permanent MAC address */
1062         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1063                         &eth_dev->data->mac_addrs[0]);
1064
1065         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1066                      "mac.type=%s",
1067                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1068                      pci_dev->id.device_id, "igb_mac_82576_vf");
1069
1070         intr_handle = &pci_dev->intr_handle;
1071         rte_intr_callback_register(intr_handle,
1072                                    eth_igbvf_interrupt_handler, eth_dev);
1073
1074         return 0;
1075 }
1076
1077 static int
1078 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1079 {
1080         struct e1000_adapter *adapter =
1081                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1082         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1083
1084         PMD_INIT_FUNC_TRACE();
1085
1086         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1087                 return -EPERM;
1088
1089         if (adapter->stopped == 0)
1090                 igbvf_dev_close(eth_dev);
1091
1092         eth_dev->dev_ops = NULL;
1093         eth_dev->rx_pkt_burst = NULL;
1094         eth_dev->tx_pkt_burst = NULL;
1095
1096         /* disable uio intr before callback unregister */
1097         rte_intr_disable(&pci_dev->intr_handle);
1098         rte_intr_callback_unregister(&pci_dev->intr_handle,
1099                                      eth_igbvf_interrupt_handler,
1100                                      (void *)eth_dev);
1101
1102         return 0;
1103 }
1104
1105 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1106         struct rte_pci_device *pci_dev)
1107 {
1108         return rte_eth_dev_pci_generic_probe(pci_dev,
1109                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1110 }
1111
1112 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1113 {
1114         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1115 }
1116
1117 static struct rte_pci_driver rte_igb_pmd = {
1118         .id_table = pci_id_igb_map,
1119         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1120         .probe = eth_igb_pci_probe,
1121         .remove = eth_igb_pci_remove,
1122 };
1123
1124
1125 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1126         struct rte_pci_device *pci_dev)
1127 {
1128         return rte_eth_dev_pci_generic_probe(pci_dev,
1129                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1130 }
1131
1132 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1133 {
1134         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1135 }
1136
1137 /*
1138  * virtual function driver struct
1139  */
1140 static struct rte_pci_driver rte_igbvf_pmd = {
1141         .id_table = pci_id_igbvf_map,
1142         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1143         .probe = eth_igbvf_pci_probe,
1144         .remove = eth_igbvf_pci_remove,
1145 };
1146
1147 static void
1148 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1149 {
1150         struct e1000_hw *hw =
1151                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1152         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1153         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1154         rctl |= E1000_RCTL_VFE;
1155         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1156 }
1157
1158 static int
1159 igb_check_mq_mode(struct rte_eth_dev *dev)
1160 {
1161         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1162         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1163         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1164         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1165
1166         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1167             tx_mq_mode == ETH_MQ_TX_DCB ||
1168             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1169                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1170                 return -EINVAL;
1171         }
1172         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1173                 /* Check multi-queue mode.
1174                  * To no break software we accept ETH_MQ_RX_NONE as this might
1175                  * be used to turn off VLAN filter.
1176                  */
1177
1178                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1179                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1180                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1181                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1182                 } else {
1183                         /* Only support one queue on VFs.
1184                          * RSS together with SRIOV is not supported.
1185                          */
1186                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1187                                         " wrong mq_mode rx %d.",
1188                                         rx_mq_mode);
1189                         return -EINVAL;
1190                 }
1191                 /* TX mode is not used here, so mode might be ignored.*/
1192                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1193                         /* SRIOV only works in VMDq enable mode */
1194                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1195                                         " TX mode %d is not supported. "
1196                                         " Driver will behave as %d mode.",
1197                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1198                 }
1199
1200                 /* check valid queue number */
1201                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1202                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1203                                         " only support one queue on VFs.");
1204                         return -EINVAL;
1205                 }
1206         } else {
1207                 /* To no break software that set invalid mode, only display
1208                  * warning if invalid mode is used.
1209                  */
1210                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1211                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1212                     rx_mq_mode != ETH_MQ_RX_RSS) {
1213                         /* RSS together with VMDq not supported*/
1214                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1215                                      rx_mq_mode);
1216                         return -EINVAL;
1217                 }
1218
1219                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1220                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1221                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1222                                         " Due to txmode is meaningless in this"
1223                                         " driver, just ignore.",
1224                                         tx_mq_mode);
1225                 }
1226         }
1227         return 0;
1228 }
1229
1230 static int
1231 eth_igb_configure(struct rte_eth_dev *dev)
1232 {
1233         struct e1000_interrupt *intr =
1234                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1235         int ret;
1236
1237         PMD_INIT_FUNC_TRACE();
1238
1239         /* multipe queue mode checking */
1240         ret  = igb_check_mq_mode(dev);
1241         if (ret != 0) {
1242                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1243                             ret);
1244                 return ret;
1245         }
1246
1247         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1248         PMD_INIT_FUNC_TRACE();
1249
1250         return 0;
1251 }
1252
1253 static void
1254 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1255                      bool enable)
1256 {
1257         struct e1000_hw *hw =
1258                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1259         uint32_t tctl, rctl;
1260
1261         tctl = E1000_READ_REG(hw, E1000_TCTL);
1262         rctl = E1000_READ_REG(hw, E1000_RCTL);
1263
1264         if (enable) {
1265                 /* enable Tx/Rx */
1266                 tctl |= E1000_TCTL_EN;
1267                 rctl |= E1000_RCTL_EN;
1268         } else {
1269                 /* disable Tx/Rx */
1270                 tctl &= ~E1000_TCTL_EN;
1271                 rctl &= ~E1000_RCTL_EN;
1272         }
1273         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1274         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1275         E1000_WRITE_FLUSH(hw);
1276 }
1277
1278 static int
1279 eth_igb_start(struct rte_eth_dev *dev)
1280 {
1281         struct e1000_hw *hw =
1282                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1283         struct e1000_adapter *adapter =
1284                 E1000_DEV_PRIVATE(dev->data->dev_private);
1285         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1286         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1287         int ret, mask;
1288         uint32_t intr_vector = 0;
1289         uint32_t ctrl_ext;
1290         uint32_t *speeds;
1291         int num_speeds;
1292         bool autoneg;
1293
1294         PMD_INIT_FUNC_TRACE();
1295
1296         /* disable uio/vfio intr/eventfd mapping */
1297         rte_intr_disable(intr_handle);
1298
1299         /* Power up the phy. Needed to make the link go Up */
1300         eth_igb_dev_set_link_up(dev);
1301
1302         /*
1303          * Packet Buffer Allocation (PBA)
1304          * Writing PBA sets the receive portion of the buffer
1305          * the remainder is used for the transmit buffer.
1306          */
1307         if (hw->mac.type == e1000_82575) {
1308                 uint32_t pba;
1309
1310                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1311                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1312         }
1313
1314         /* Put the address into the Receive Address Array */
1315         e1000_rar_set(hw, hw->mac.addr, 0);
1316
1317         /* Initialize the hardware */
1318         if (igb_hardware_init(hw)) {
1319                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1320                 return -EIO;
1321         }
1322         adapter->stopped = 0;
1323
1324         E1000_WRITE_REG(hw, E1000_VET,
1325                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1326
1327         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1328         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1329         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1330         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1331         E1000_WRITE_FLUSH(hw);
1332
1333         /* configure PF module if SRIOV enabled */
1334         igb_pf_host_configure(dev);
1335
1336         /* check and configure queue intr-vector mapping */
1337         if ((rte_intr_cap_multiple(intr_handle) ||
1338              !RTE_ETH_DEV_SRIOV(dev).active) &&
1339             dev->data->dev_conf.intr_conf.rxq != 0) {
1340                 intr_vector = dev->data->nb_rx_queues;
1341                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1342                         return -1;
1343         }
1344
1345         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1346                 intr_handle->intr_vec =
1347                         rte_zmalloc("intr_vec",
1348                                     dev->data->nb_rx_queues * sizeof(int), 0);
1349                 if (intr_handle->intr_vec == NULL) {
1350                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1351                                      " intr_vec", dev->data->nb_rx_queues);
1352                         return -ENOMEM;
1353                 }
1354         }
1355
1356         /* confiugre msix for rx interrupt */
1357         eth_igb_configure_msix_intr(dev);
1358
1359         /* Configure for OS presence */
1360         igb_init_manageability(hw);
1361
1362         eth_igb_tx_init(dev);
1363
1364         /* This can fail when allocating mbufs for descriptor rings */
1365         ret = eth_igb_rx_init(dev);
1366         if (ret) {
1367                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1368                 igb_dev_clear_queues(dev);
1369                 return ret;
1370         }
1371
1372         e1000_clear_hw_cntrs_base_generic(hw);
1373
1374         /*
1375          * VLAN Offload Settings
1376          */
1377         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1378                         ETH_VLAN_EXTEND_MASK;
1379         ret = eth_igb_vlan_offload_set(dev, mask);
1380         if (ret) {
1381                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1382                 igb_dev_clear_queues(dev);
1383                 return ret;
1384         }
1385
1386         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1387                 /* Enable VLAN filter since VMDq always use VLAN filter */
1388                 igb_vmdq_vlan_hw_filter_enable(dev);
1389         }
1390
1391         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1392                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1393                 (hw->mac.type == e1000_i211)) {
1394                 /* Configure EITR with the maximum possible value (0xFFFF) */
1395                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1396         }
1397
1398         /* Setup link speed and duplex */
1399         speeds = &dev->data->dev_conf.link_speeds;
1400         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1401                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1402                 hw->mac.autoneg = 1;
1403         } else {
1404                 num_speeds = 0;
1405                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1406
1407                 /* Reset */
1408                 hw->phy.autoneg_advertised = 0;
1409
1410                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1411                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1412                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1413                         num_speeds = -1;
1414                         goto error_invalid_config;
1415                 }
1416                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1417                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1418                         num_speeds++;
1419                 }
1420                 if (*speeds & ETH_LINK_SPEED_10M) {
1421                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1422                         num_speeds++;
1423                 }
1424                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1425                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1426                         num_speeds++;
1427                 }
1428                 if (*speeds & ETH_LINK_SPEED_100M) {
1429                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1430                         num_speeds++;
1431                 }
1432                 if (*speeds & ETH_LINK_SPEED_1G) {
1433                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1434                         num_speeds++;
1435                 }
1436                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1437                         goto error_invalid_config;
1438
1439                 /* Set/reset the mac.autoneg based on the link speed,
1440                  * fixed or not
1441                  */
1442                 if (!autoneg) {
1443                         hw->mac.autoneg = 0;
1444                         hw->mac.forced_speed_duplex =
1445                                         hw->phy.autoneg_advertised;
1446                 } else {
1447                         hw->mac.autoneg = 1;
1448                 }
1449         }
1450
1451         e1000_setup_link(hw);
1452
1453         if (rte_intr_allow_others(intr_handle)) {
1454                 /* check if lsc interrupt is enabled */
1455                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1456                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1457                 else
1458                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1459         } else {
1460                 rte_intr_callback_unregister(intr_handle,
1461                                              eth_igb_interrupt_handler,
1462                                              (void *)dev);
1463                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1464                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1465                                      " no intr multiplex");
1466         }
1467
1468         /* check if rxq interrupt is enabled */
1469         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1470             rte_intr_dp_is_en(intr_handle))
1471                 eth_igb_rxq_interrupt_setup(dev);
1472
1473         /* enable uio/vfio intr/eventfd mapping */
1474         rte_intr_enable(intr_handle);
1475
1476         /* resume enabled intr since hw reset */
1477         igb_intr_enable(dev);
1478
1479         /* restore all types filter */
1480         igb_filter_restore(dev);
1481
1482         eth_igb_rxtx_control(dev, true);
1483         eth_igb_link_update(dev, 0);
1484
1485         PMD_INIT_LOG(DEBUG, "<<");
1486
1487         return 0;
1488
1489 error_invalid_config:
1490         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1491                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1492         igb_dev_clear_queues(dev);
1493         return -EINVAL;
1494 }
1495
1496 /*********************************************************************
1497  *
1498  *  This routine disables all traffic on the adapter by issuing a
1499  *  global reset on the MAC.
1500  *
1501  **********************************************************************/
1502 static void
1503 eth_igb_stop(struct rte_eth_dev *dev)
1504 {
1505         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1506         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1507         struct rte_eth_link link;
1508         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1509
1510         eth_igb_rxtx_control(dev, false);
1511
1512         igb_intr_disable(dev);
1513
1514         /* disable intr eventfd mapping */
1515         rte_intr_disable(intr_handle);
1516
1517         igb_pf_reset_hw(hw);
1518         E1000_WRITE_REG(hw, E1000_WUC, 0);
1519
1520         /* Set bit for Go Link disconnect */
1521         if (hw->mac.type >= e1000_82580) {
1522                 uint32_t phpm_reg;
1523
1524                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1525                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1526                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1527         }
1528
1529         /* Power down the phy. Needed to make the link go Down */
1530         eth_igb_dev_set_link_down(dev);
1531
1532         igb_dev_clear_queues(dev);
1533
1534         /* clear the recorded link status */
1535         memset(&link, 0, sizeof(link));
1536         rte_eth_linkstatus_set(dev, &link);
1537
1538         if (!rte_intr_allow_others(intr_handle))
1539                 /* resume to the default handler */
1540                 rte_intr_callback_register(intr_handle,
1541                                            eth_igb_interrupt_handler,
1542                                            (void *)dev);
1543
1544         /* Clean datapath event and queue/vec mapping */
1545         rte_intr_efd_disable(intr_handle);
1546         if (intr_handle->intr_vec != NULL) {
1547                 rte_free(intr_handle->intr_vec);
1548                 intr_handle->intr_vec = NULL;
1549         }
1550 }
1551
1552 static int
1553 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1554 {
1555         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1556
1557         if (hw->phy.media_type == e1000_media_type_copper)
1558                 e1000_power_up_phy(hw);
1559         else
1560                 e1000_power_up_fiber_serdes_link(hw);
1561
1562         return 0;
1563 }
1564
1565 static int
1566 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1567 {
1568         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1569
1570         if (hw->phy.media_type == e1000_media_type_copper)
1571                 e1000_power_down_phy(hw);
1572         else
1573                 e1000_shutdown_fiber_serdes_link(hw);
1574
1575         return 0;
1576 }
1577
1578 static void
1579 eth_igb_close(struct rte_eth_dev *dev)
1580 {
1581         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1582         struct e1000_adapter *adapter =
1583                 E1000_DEV_PRIVATE(dev->data->dev_private);
1584         struct rte_eth_link link;
1585         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1586         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1587
1588         eth_igb_stop(dev);
1589         adapter->stopped = 1;
1590
1591         e1000_phy_hw_reset(hw);
1592         igb_release_manageability(hw);
1593         igb_hw_control_release(hw);
1594
1595         /* Clear bit for Go Link disconnect */
1596         if (hw->mac.type >= e1000_82580) {
1597                 uint32_t phpm_reg;
1598
1599                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1600                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1601                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1602         }
1603
1604         igb_dev_free_queues(dev);
1605
1606         if (intr_handle->intr_vec) {
1607                 rte_free(intr_handle->intr_vec);
1608                 intr_handle->intr_vec = NULL;
1609         }
1610
1611         memset(&link, 0, sizeof(link));
1612         rte_eth_linkstatus_set(dev, &link);
1613 }
1614
1615 /*
1616  * Reset PF device.
1617  */
1618 static int
1619 eth_igb_reset(struct rte_eth_dev *dev)
1620 {
1621         int ret;
1622
1623         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1624          * its VF to make them align with it. The detailed notification
1625          * mechanism is PMD specific and is currently not implemented.
1626          * To avoid unexpected behavior in VF, currently reset of PF with
1627          * SR-IOV activation is not supported. It might be supported later.
1628          */
1629         if (dev->data->sriov.active)
1630                 return -ENOTSUP;
1631
1632         ret = eth_igb_dev_uninit(dev);
1633         if (ret)
1634                 return ret;
1635
1636         ret = eth_igb_dev_init(dev);
1637
1638         return ret;
1639 }
1640
1641
1642 static int
1643 igb_get_rx_buffer_size(struct e1000_hw *hw)
1644 {
1645         uint32_t rx_buf_size;
1646         if (hw->mac.type == e1000_82576) {
1647                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1648         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1649                 /* PBS needs to be translated according to a lookup table */
1650                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1651                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1652                 rx_buf_size = (rx_buf_size << 10);
1653         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1654                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1655         } else {
1656                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1657         }
1658
1659         return rx_buf_size;
1660 }
1661
1662 /*********************************************************************
1663  *
1664  *  Initialize the hardware
1665  *
1666  **********************************************************************/
1667 static int
1668 igb_hardware_init(struct e1000_hw *hw)
1669 {
1670         uint32_t rx_buf_size;
1671         int diag;
1672
1673         /* Let the firmware know the OS is in control */
1674         igb_hw_control_acquire(hw);
1675
1676         /*
1677          * These parameters control the automatic generation (Tx) and
1678          * response (Rx) to Ethernet PAUSE frames.
1679          * - High water mark should allow for at least two standard size (1518)
1680          *   frames to be received after sending an XOFF.
1681          * - Low water mark works best when it is very near the high water mark.
1682          *   This allows the receiver to restart by sending XON when it has
1683          *   drained a bit. Here we use an arbitrary value of 1500 which will
1684          *   restart after one full frame is pulled from the buffer. There
1685          *   could be several smaller frames in the buffer and if so they will
1686          *   not trigger the XON until their total number reduces the buffer
1687          *   by 1500.
1688          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1689          */
1690         rx_buf_size = igb_get_rx_buffer_size(hw);
1691
1692         hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1693         hw->fc.low_water = hw->fc.high_water - 1500;
1694         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1695         hw->fc.send_xon = 1;
1696
1697         /* Set Flow control, use the tunable location if sane */
1698         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1699                 hw->fc.requested_mode = igb_fc_setting;
1700         else
1701                 hw->fc.requested_mode = e1000_fc_none;
1702
1703         /* Issue a global reset */
1704         igb_pf_reset_hw(hw);
1705         E1000_WRITE_REG(hw, E1000_WUC, 0);
1706
1707         diag = e1000_init_hw(hw);
1708         if (diag < 0)
1709                 return diag;
1710
1711         E1000_WRITE_REG(hw, E1000_VET,
1712                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1713         e1000_get_phy_info(hw);
1714         e1000_check_for_link(hw);
1715
1716         return 0;
1717 }
1718
1719 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1720 static void
1721 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1722 {
1723         int pause_frames;
1724
1725         uint64_t old_gprc  = stats->gprc;
1726         uint64_t old_gptc  = stats->gptc;
1727         uint64_t old_tpr   = stats->tpr;
1728         uint64_t old_tpt   = stats->tpt;
1729         uint64_t old_rpthc = stats->rpthc;
1730         uint64_t old_hgptc = stats->hgptc;
1731
1732         if(hw->phy.media_type == e1000_media_type_copper ||
1733             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1734                 stats->symerrs +=
1735                     E1000_READ_REG(hw,E1000_SYMERRS);
1736                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1737         }
1738
1739         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1740         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1741         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1742         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1743
1744         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1745         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1746         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1747         stats->dc += E1000_READ_REG(hw, E1000_DC);
1748         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1749         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1750         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1751         /*
1752         ** For watchdog management we need to know if we have been
1753         ** paused during the last interval, so capture that here.
1754         */
1755         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1756         stats->xoffrxc += pause_frames;
1757         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1758         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1759         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1760         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1761         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1762         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1763         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1764         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1765         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1766         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1767         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1768         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1769
1770         /* For the 64-bit byte counters the low dword must be read first. */
1771         /* Both registers clear on the read of the high dword */
1772
1773         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1774         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1775         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1776         stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1777         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1778         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1779         stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1780
1781         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1782         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1783         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1784         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1785         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1786
1787         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1788         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1789
1790         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1791         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1792         stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1793         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1794         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1795         stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1796
1797         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1798         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1799         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1800         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1801         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1802         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1803         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1804         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1805
1806         /* Interrupt Counts */
1807
1808         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1809         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1810         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1811         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1812         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1813         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1814         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1815         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1816         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1817
1818         /* Host to Card Statistics */
1819
1820         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1821         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1822         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1823         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1824         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1825         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1826         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1827         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1828         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1829         stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1830         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1831         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1832         stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1833         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1834         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1835         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1836
1837         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1838         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1839         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1840         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1841         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1842         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1843 }
1844
1845 static int
1846 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1847 {
1848         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1849         struct e1000_hw_stats *stats =
1850                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1851
1852         igb_read_stats_registers(hw, stats);
1853
1854         if (rte_stats == NULL)
1855                 return -EINVAL;
1856
1857         /* Rx Errors */
1858         rte_stats->imissed = stats->mpc;
1859         rte_stats->ierrors = stats->crcerrs +
1860                              stats->rlec + stats->ruc + stats->roc +
1861                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1862
1863         /* Tx Errors */
1864         rte_stats->oerrors = stats->ecol + stats->latecol;
1865
1866         rte_stats->ipackets = stats->gprc;
1867         rte_stats->opackets = stats->gptc;
1868         rte_stats->ibytes   = stats->gorc;
1869         rte_stats->obytes   = stats->gotc;
1870         return 0;
1871 }
1872
1873 static int
1874 eth_igb_stats_reset(struct rte_eth_dev *dev)
1875 {
1876         struct e1000_hw_stats *hw_stats =
1877                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1878
1879         /* HW registers are cleared on read */
1880         eth_igb_stats_get(dev, NULL);
1881
1882         /* Reset software totals */
1883         memset(hw_stats, 0, sizeof(*hw_stats));
1884
1885         return 0;
1886 }
1887
1888 static int
1889 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1890 {
1891         struct e1000_hw_stats *stats =
1892                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1893
1894         /* HW registers are cleared on read */
1895         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1896
1897         /* Reset software totals */
1898         memset(stats, 0, sizeof(*stats));
1899
1900         return 0;
1901 }
1902
1903 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1904         struct rte_eth_xstat_name *xstats_names,
1905         __rte_unused unsigned int size)
1906 {
1907         unsigned i;
1908
1909         if (xstats_names == NULL)
1910                 return IGB_NB_XSTATS;
1911
1912         /* Note: limit checked in rte_eth_xstats_names() */
1913
1914         for (i = 0; i < IGB_NB_XSTATS; i++) {
1915                 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1916                         sizeof(xstats_names[i].name));
1917         }
1918
1919         return IGB_NB_XSTATS;
1920 }
1921
1922 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1923                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1924                 unsigned int limit)
1925 {
1926         unsigned int i;
1927
1928         if (!ids) {
1929                 if (xstats_names == NULL)
1930                         return IGB_NB_XSTATS;
1931
1932                 for (i = 0; i < IGB_NB_XSTATS; i++)
1933                         strlcpy(xstats_names[i].name,
1934                                 rte_igb_stats_strings[i].name,
1935                                 sizeof(xstats_names[i].name));
1936
1937                 return IGB_NB_XSTATS;
1938
1939         } else {
1940                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1941
1942                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1943                                 IGB_NB_XSTATS);
1944
1945                 for (i = 0; i < limit; i++) {
1946                         if (ids[i] >= IGB_NB_XSTATS) {
1947                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1948                                 return -1;
1949                         }
1950                         strcpy(xstats_names[i].name,
1951                                         xstats_names_copy[ids[i]].name);
1952                 }
1953                 return limit;
1954         }
1955 }
1956
1957 static int
1958 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1959                    unsigned n)
1960 {
1961         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1962         struct e1000_hw_stats *hw_stats =
1963                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1964         unsigned i;
1965
1966         if (n < IGB_NB_XSTATS)
1967                 return IGB_NB_XSTATS;
1968
1969         igb_read_stats_registers(hw, hw_stats);
1970
1971         /* If this is a reset xstats is NULL, and we have cleared the
1972          * registers by reading them.
1973          */
1974         if (!xstats)
1975                 return 0;
1976
1977         /* Extended stats */
1978         for (i = 0; i < IGB_NB_XSTATS; i++) {
1979                 xstats[i].id = i;
1980                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1981                         rte_igb_stats_strings[i].offset);
1982         }
1983
1984         return IGB_NB_XSTATS;
1985 }
1986
1987 static int
1988 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1989                 uint64_t *values, unsigned int n)
1990 {
1991         unsigned int i;
1992
1993         if (!ids) {
1994                 struct e1000_hw *hw =
1995                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1996                 struct e1000_hw_stats *hw_stats =
1997                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1998
1999                 if (n < IGB_NB_XSTATS)
2000                         return IGB_NB_XSTATS;
2001
2002                 igb_read_stats_registers(hw, hw_stats);
2003
2004                 /* If this is a reset xstats is NULL, and we have cleared the
2005                  * registers by reading them.
2006                  */
2007                 if (!values)
2008                         return 0;
2009
2010                 /* Extended stats */
2011                 for (i = 0; i < IGB_NB_XSTATS; i++)
2012                         values[i] = *(uint64_t *)(((char *)hw_stats) +
2013                                         rte_igb_stats_strings[i].offset);
2014
2015                 return IGB_NB_XSTATS;
2016
2017         } else {
2018                 uint64_t values_copy[IGB_NB_XSTATS];
2019
2020                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2021                                 IGB_NB_XSTATS);
2022
2023                 for (i = 0; i < n; i++) {
2024                         if (ids[i] >= IGB_NB_XSTATS) {
2025                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2026                                 return -1;
2027                         }
2028                         values[i] = values_copy[ids[i]];
2029                 }
2030                 return n;
2031         }
2032 }
2033
2034 static void
2035 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2036 {
2037         /* Good Rx packets, include VF loopback */
2038         UPDATE_VF_STAT(E1000_VFGPRC,
2039             hw_stats->last_gprc, hw_stats->gprc);
2040
2041         /* Good Rx octets, include VF loopback */
2042         UPDATE_VF_STAT(E1000_VFGORC,
2043             hw_stats->last_gorc, hw_stats->gorc);
2044
2045         /* Good Tx packets, include VF loopback */
2046         UPDATE_VF_STAT(E1000_VFGPTC,
2047             hw_stats->last_gptc, hw_stats->gptc);
2048
2049         /* Good Tx octets, include VF loopback */
2050         UPDATE_VF_STAT(E1000_VFGOTC,
2051             hw_stats->last_gotc, hw_stats->gotc);
2052
2053         /* Rx Multicst packets */
2054         UPDATE_VF_STAT(E1000_VFMPRC,
2055             hw_stats->last_mprc, hw_stats->mprc);
2056
2057         /* Good Rx loopback packets */
2058         UPDATE_VF_STAT(E1000_VFGPRLBC,
2059             hw_stats->last_gprlbc, hw_stats->gprlbc);
2060
2061         /* Good Rx loopback octets */
2062         UPDATE_VF_STAT(E1000_VFGORLBC,
2063             hw_stats->last_gorlbc, hw_stats->gorlbc);
2064
2065         /* Good Tx loopback packets */
2066         UPDATE_VF_STAT(E1000_VFGPTLBC,
2067             hw_stats->last_gptlbc, hw_stats->gptlbc);
2068
2069         /* Good Tx loopback octets */
2070         UPDATE_VF_STAT(E1000_VFGOTLBC,
2071             hw_stats->last_gotlbc, hw_stats->gotlbc);
2072 }
2073
2074 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2075                                      struct rte_eth_xstat_name *xstats_names,
2076                                      __rte_unused unsigned limit)
2077 {
2078         unsigned i;
2079
2080         if (xstats_names != NULL)
2081                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2082                         strlcpy(xstats_names[i].name,
2083                                 rte_igbvf_stats_strings[i].name,
2084                                 sizeof(xstats_names[i].name));
2085                 }
2086         return IGBVF_NB_XSTATS;
2087 }
2088
2089 static int
2090 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2091                      unsigned n)
2092 {
2093         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2094         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2095                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2096         unsigned i;
2097
2098         if (n < IGBVF_NB_XSTATS)
2099                 return IGBVF_NB_XSTATS;
2100
2101         igbvf_read_stats_registers(hw, hw_stats);
2102
2103         if (!xstats)
2104                 return 0;
2105
2106         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2107                 xstats[i].id = i;
2108                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2109                         rte_igbvf_stats_strings[i].offset);
2110         }
2111
2112         return IGBVF_NB_XSTATS;
2113 }
2114
2115 static int
2116 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2117 {
2118         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2119         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2120                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2121
2122         igbvf_read_stats_registers(hw, hw_stats);
2123
2124         if (rte_stats == NULL)
2125                 return -EINVAL;
2126
2127         rte_stats->ipackets = hw_stats->gprc;
2128         rte_stats->ibytes = hw_stats->gorc;
2129         rte_stats->opackets = hw_stats->gptc;
2130         rte_stats->obytes = hw_stats->gotc;
2131         return 0;
2132 }
2133
2134 static int
2135 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2136 {
2137         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2138                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2139
2140         /* Sync HW register to the last stats */
2141         eth_igbvf_stats_get(dev, NULL);
2142
2143         /* reset HW current stats*/
2144         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2145                offsetof(struct e1000_vf_stats, gprc));
2146
2147         return 0;
2148 }
2149
2150 static int
2151 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2152                        size_t fw_size)
2153 {
2154         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2155         struct e1000_fw_version fw;
2156         int ret;
2157
2158         e1000_get_fw_version(hw, &fw);
2159
2160         switch (hw->mac.type) {
2161         case e1000_i210:
2162         case e1000_i211:
2163                 if (!(e1000_get_flash_presence_i210(hw))) {
2164                         ret = snprintf(fw_version, fw_size,
2165                                  "%2d.%2d-%d",
2166                                  fw.invm_major, fw.invm_minor,
2167                                  fw.invm_img_type);
2168                         break;
2169                 }
2170                 /* fall through */
2171         default:
2172                 /* if option rom is valid, display its version too */
2173                 if (fw.or_valid) {
2174                         ret = snprintf(fw_version, fw_size,
2175                                  "%d.%d, 0x%08x, %d.%d.%d",
2176                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2177                                  fw.or_major, fw.or_build, fw.or_patch);
2178                 /* no option rom */
2179                 } else {
2180                         if (fw.etrack_id != 0X0000) {
2181                                 ret = snprintf(fw_version, fw_size,
2182                                          "%d.%d, 0x%08x",
2183                                          fw.eep_major, fw.eep_minor,
2184                                          fw.etrack_id);
2185                         } else {
2186                                 ret = snprintf(fw_version, fw_size,
2187                                          "%d.%d.%d",
2188                                          fw.eep_major, fw.eep_minor,
2189                                          fw.eep_build);
2190                         }
2191                 }
2192                 break;
2193         }
2194
2195         ret += 1; /* add the size of '\0' */
2196         if (fw_size < (u32)ret)
2197                 return ret;
2198         else
2199                 return 0;
2200 }
2201
2202 static int
2203 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2204 {
2205         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2206
2207         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2208         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2209         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2210         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2211         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2212                                     dev_info->rx_queue_offload_capa;
2213         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2214         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2215                                     dev_info->tx_queue_offload_capa;
2216
2217         switch (hw->mac.type) {
2218         case e1000_82575:
2219                 dev_info->max_rx_queues = 4;
2220                 dev_info->max_tx_queues = 4;
2221                 dev_info->max_vmdq_pools = 0;
2222                 break;
2223
2224         case e1000_82576:
2225                 dev_info->max_rx_queues = 16;
2226                 dev_info->max_tx_queues = 16;
2227                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2228                 dev_info->vmdq_queue_num = 16;
2229                 break;
2230
2231         case e1000_82580:
2232                 dev_info->max_rx_queues = 8;
2233                 dev_info->max_tx_queues = 8;
2234                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2235                 dev_info->vmdq_queue_num = 8;
2236                 break;
2237
2238         case e1000_i350:
2239                 dev_info->max_rx_queues = 8;
2240                 dev_info->max_tx_queues = 8;
2241                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2242                 dev_info->vmdq_queue_num = 8;
2243                 break;
2244
2245         case e1000_i354:
2246                 dev_info->max_rx_queues = 8;
2247                 dev_info->max_tx_queues = 8;
2248                 break;
2249
2250         case e1000_i210:
2251                 dev_info->max_rx_queues = 4;
2252                 dev_info->max_tx_queues = 4;
2253                 dev_info->max_vmdq_pools = 0;
2254                 break;
2255
2256         case e1000_i211:
2257                 dev_info->max_rx_queues = 2;
2258                 dev_info->max_tx_queues = 2;
2259                 dev_info->max_vmdq_pools = 0;
2260                 break;
2261
2262         default:
2263                 /* Should not happen */
2264                 return -EINVAL;
2265         }
2266         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2267         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2268         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2269
2270         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2271                 .rx_thresh = {
2272                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2273                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2274                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2275                 },
2276                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2277                 .rx_drop_en = 0,
2278                 .offloads = 0,
2279         };
2280
2281         dev_info->default_txconf = (struct rte_eth_txconf) {
2282                 .tx_thresh = {
2283                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2284                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2285                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2286                 },
2287                 .offloads = 0,
2288         };
2289
2290         dev_info->rx_desc_lim = rx_desc_lim;
2291         dev_info->tx_desc_lim = tx_desc_lim;
2292
2293         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2294                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2295                         ETH_LINK_SPEED_1G;
2296
2297         dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2298         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2299
2300         return 0;
2301 }
2302
2303 static const uint32_t *
2304 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2305 {
2306         static const uint32_t ptypes[] = {
2307                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2308                 RTE_PTYPE_L2_ETHER,
2309                 RTE_PTYPE_L3_IPV4,
2310                 RTE_PTYPE_L3_IPV4_EXT,
2311                 RTE_PTYPE_L3_IPV6,
2312                 RTE_PTYPE_L3_IPV6_EXT,
2313                 RTE_PTYPE_L4_TCP,
2314                 RTE_PTYPE_L4_UDP,
2315                 RTE_PTYPE_L4_SCTP,
2316                 RTE_PTYPE_TUNNEL_IP,
2317                 RTE_PTYPE_INNER_L3_IPV6,
2318                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2319                 RTE_PTYPE_INNER_L4_TCP,
2320                 RTE_PTYPE_INNER_L4_UDP,
2321                 RTE_PTYPE_UNKNOWN
2322         };
2323
2324         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2325             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2326                 return ptypes;
2327         return NULL;
2328 }
2329
2330 static int
2331 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2332 {
2333         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2334
2335         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2336         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2337         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2338         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2339                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2340                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2341                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2342                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2343                                 DEV_TX_OFFLOAD_TCP_TSO;
2344         switch (hw->mac.type) {
2345         case e1000_vfadapt:
2346                 dev_info->max_rx_queues = 2;
2347                 dev_info->max_tx_queues = 2;
2348                 break;
2349         case e1000_vfadapt_i350:
2350                 dev_info->max_rx_queues = 1;
2351                 dev_info->max_tx_queues = 1;
2352                 break;
2353         default:
2354                 /* Should not happen */
2355                 return -EINVAL;
2356         }
2357
2358         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2359         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2360                                     dev_info->rx_queue_offload_capa;
2361         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2362         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2363                                     dev_info->tx_queue_offload_capa;
2364
2365         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2366                 .rx_thresh = {
2367                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2368                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2369                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2370                 },
2371                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2372                 .rx_drop_en = 0,
2373                 .offloads = 0,
2374         };
2375
2376         dev_info->default_txconf = (struct rte_eth_txconf) {
2377                 .tx_thresh = {
2378                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2379                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2380                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2381                 },
2382                 .offloads = 0,
2383         };
2384
2385         dev_info->rx_desc_lim = rx_desc_lim;
2386         dev_info->tx_desc_lim = tx_desc_lim;
2387
2388         return 0;
2389 }
2390
2391 /* return 0 means link status changed, -1 means not changed */
2392 static int
2393 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2394 {
2395         struct e1000_hw *hw =
2396                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2397         struct rte_eth_link link;
2398         int link_check, count;
2399
2400         link_check = 0;
2401         hw->mac.get_link_status = 1;
2402
2403         /* possible wait-to-complete in up to 9 seconds */
2404         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2405                 /* Read the real link status */
2406                 switch (hw->phy.media_type) {
2407                 case e1000_media_type_copper:
2408                         /* Do the work to read phy */
2409                         e1000_check_for_link(hw);
2410                         link_check = !hw->mac.get_link_status;
2411                         break;
2412
2413                 case e1000_media_type_fiber:
2414                         e1000_check_for_link(hw);
2415                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2416                                       E1000_STATUS_LU);
2417                         break;
2418
2419                 case e1000_media_type_internal_serdes:
2420                         e1000_check_for_link(hw);
2421                         link_check = hw->mac.serdes_has_link;
2422                         break;
2423
2424                 /* VF device is type_unknown */
2425                 case e1000_media_type_unknown:
2426                         eth_igbvf_link_update(hw);
2427                         link_check = !hw->mac.get_link_status;
2428                         break;
2429
2430                 default:
2431                         break;
2432                 }
2433                 if (link_check || wait_to_complete == 0)
2434                         break;
2435                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2436         }
2437         memset(&link, 0, sizeof(link));
2438
2439         /* Now we check if a transition has happened */
2440         if (link_check) {
2441                 uint16_t duplex, speed;
2442                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2443                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2444                                 ETH_LINK_FULL_DUPLEX :
2445                                 ETH_LINK_HALF_DUPLEX;
2446                 link.link_speed = speed;
2447                 link.link_status = ETH_LINK_UP;
2448                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2449                                 ETH_LINK_SPEED_FIXED);
2450         } else if (!link_check) {
2451                 link.link_speed = 0;
2452                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2453                 link.link_status = ETH_LINK_DOWN;
2454                 link.link_autoneg = ETH_LINK_FIXED;
2455         }
2456
2457         return rte_eth_linkstatus_set(dev, &link);
2458 }
2459
2460 /*
2461  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2462  * For ASF and Pass Through versions of f/w this means
2463  * that the driver is loaded.
2464  */
2465 static void
2466 igb_hw_control_acquire(struct e1000_hw *hw)
2467 {
2468         uint32_t ctrl_ext;
2469
2470         /* Let firmware know the driver has taken over */
2471         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2472         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2473 }
2474
2475 /*
2476  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2477  * For ASF and Pass Through versions of f/w this means that the
2478  * driver is no longer loaded.
2479  */
2480 static void
2481 igb_hw_control_release(struct e1000_hw *hw)
2482 {
2483         uint32_t ctrl_ext;
2484
2485         /* Let firmware taken over control of h/w */
2486         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2487         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2488                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2489 }
2490
2491 /*
2492  * Bit of a misnomer, what this really means is
2493  * to enable OS management of the system... aka
2494  * to disable special hardware management features.
2495  */
2496 static void
2497 igb_init_manageability(struct e1000_hw *hw)
2498 {
2499         if (e1000_enable_mng_pass_thru(hw)) {
2500                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2501                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2502
2503                 /* disable hardware interception of ARP */
2504                 manc &= ~(E1000_MANC_ARP_EN);
2505
2506                 /* enable receiving management packets to the host */
2507                 manc |= E1000_MANC_EN_MNG2HOST;
2508                 manc2h |= 1 << 5;  /* Mng Port 623 */
2509                 manc2h |= 1 << 6;  /* Mng Port 664 */
2510                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2511                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2512         }
2513 }
2514
2515 static void
2516 igb_release_manageability(struct e1000_hw *hw)
2517 {
2518         if (e1000_enable_mng_pass_thru(hw)) {
2519                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2520
2521                 manc |= E1000_MANC_ARP_EN;
2522                 manc &= ~E1000_MANC_EN_MNG2HOST;
2523
2524                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2525         }
2526 }
2527
2528 static int
2529 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2530 {
2531         struct e1000_hw *hw =
2532                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2533         uint32_t rctl;
2534
2535         rctl = E1000_READ_REG(hw, E1000_RCTL);
2536         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2537         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2538
2539         return 0;
2540 }
2541
2542 static int
2543 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2544 {
2545         struct e1000_hw *hw =
2546                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2547         uint32_t rctl;
2548
2549         rctl = E1000_READ_REG(hw, E1000_RCTL);
2550         rctl &= (~E1000_RCTL_UPE);
2551         if (dev->data->all_multicast == 1)
2552                 rctl |= E1000_RCTL_MPE;
2553         else
2554                 rctl &= (~E1000_RCTL_MPE);
2555         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2556
2557         return 0;
2558 }
2559
2560 static void
2561 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2562 {
2563         struct e1000_hw *hw =
2564                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2565         uint32_t rctl;
2566
2567         rctl = E1000_READ_REG(hw, E1000_RCTL);
2568         rctl |= E1000_RCTL_MPE;
2569         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2570 }
2571
2572 static void
2573 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2574 {
2575         struct e1000_hw *hw =
2576                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2577         uint32_t rctl;
2578
2579         if (dev->data->promiscuous == 1)
2580                 return; /* must remain in all_multicast mode */
2581         rctl = E1000_READ_REG(hw, E1000_RCTL);
2582         rctl &= (~E1000_RCTL_MPE);
2583         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2584 }
2585
2586 static int
2587 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2588 {
2589         struct e1000_hw *hw =
2590                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2591         struct e1000_vfta * shadow_vfta =
2592                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2593         uint32_t vfta;
2594         uint32_t vid_idx;
2595         uint32_t vid_bit;
2596
2597         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2598                               E1000_VFTA_ENTRY_MASK);
2599         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2600         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2601         if (on)
2602                 vfta |= vid_bit;
2603         else
2604                 vfta &= ~vid_bit;
2605         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2606
2607         /* update local VFTA copy */
2608         shadow_vfta->vfta[vid_idx] = vfta;
2609
2610         return 0;
2611 }
2612
2613 static int
2614 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2615                       enum rte_vlan_type vlan_type,
2616                       uint16_t tpid)
2617 {
2618         struct e1000_hw *hw =
2619                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2620         uint32_t reg, qinq;
2621
2622         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2623         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2624
2625         /* only outer TPID of double VLAN can be configured*/
2626         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2627                 reg = E1000_READ_REG(hw, E1000_VET);
2628                 reg = (reg & (~E1000_VET_VET_EXT)) |
2629                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2630                 E1000_WRITE_REG(hw, E1000_VET, reg);
2631
2632                 return 0;
2633         }
2634
2635         /* all other TPID values are read-only*/
2636         PMD_DRV_LOG(ERR, "Not supported");
2637
2638         return -ENOTSUP;
2639 }
2640
2641 static void
2642 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2643 {
2644         struct e1000_hw *hw =
2645                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2646         uint32_t reg;
2647
2648         /* Filter Table Disable */
2649         reg = E1000_READ_REG(hw, E1000_RCTL);
2650         reg &= ~E1000_RCTL_CFIEN;
2651         reg &= ~E1000_RCTL_VFE;
2652         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2653 }
2654
2655 static void
2656 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2657 {
2658         struct e1000_hw *hw =
2659                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2660         struct e1000_vfta * shadow_vfta =
2661                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2662         uint32_t reg;
2663         int i;
2664
2665         /* Filter Table Enable, CFI not used for packet acceptance */
2666         reg = E1000_READ_REG(hw, E1000_RCTL);
2667         reg &= ~E1000_RCTL_CFIEN;
2668         reg |= E1000_RCTL_VFE;
2669         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2670
2671         /* restore VFTA table */
2672         for (i = 0; i < IGB_VFTA_SIZE; i++)
2673                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2674 }
2675
2676 static void
2677 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2678 {
2679         struct e1000_hw *hw =
2680                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2681         uint32_t reg;
2682
2683         /* VLAN Mode Disable */
2684         reg = E1000_READ_REG(hw, E1000_CTRL);
2685         reg &= ~E1000_CTRL_VME;
2686         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2687 }
2688
2689 static void
2690 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2691 {
2692         struct e1000_hw *hw =
2693                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2694         uint32_t reg;
2695
2696         /* VLAN Mode Enable */
2697         reg = E1000_READ_REG(hw, E1000_CTRL);
2698         reg |= E1000_CTRL_VME;
2699         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2700 }
2701
2702 static void
2703 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2704 {
2705         struct e1000_hw *hw =
2706                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2707         uint32_t reg;
2708
2709         /* CTRL_EXT: Extended VLAN */
2710         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2711         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2712         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2713
2714         /* Update maximum packet length */
2715         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2716                 E1000_WRITE_REG(hw, E1000_RLPML,
2717                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2718                                                 VLAN_TAG_SIZE);
2719 }
2720
2721 static void
2722 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2723 {
2724         struct e1000_hw *hw =
2725                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2726         uint32_t reg;
2727
2728         /* CTRL_EXT: Extended VLAN */
2729         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2730         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2731         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2732
2733         /* Update maximum packet length */
2734         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2735                 E1000_WRITE_REG(hw, E1000_RLPML,
2736                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2737                                                 2 * VLAN_TAG_SIZE);
2738 }
2739
2740 static int
2741 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2742 {
2743         struct rte_eth_rxmode *rxmode;
2744
2745         rxmode = &dev->data->dev_conf.rxmode;
2746         if(mask & ETH_VLAN_STRIP_MASK){
2747                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2748                         igb_vlan_hw_strip_enable(dev);
2749                 else
2750                         igb_vlan_hw_strip_disable(dev);
2751         }
2752
2753         if(mask & ETH_VLAN_FILTER_MASK){
2754                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2755                         igb_vlan_hw_filter_enable(dev);
2756                 else
2757                         igb_vlan_hw_filter_disable(dev);
2758         }
2759
2760         if(mask & ETH_VLAN_EXTEND_MASK){
2761                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2762                         igb_vlan_hw_extend_enable(dev);
2763                 else
2764                         igb_vlan_hw_extend_disable(dev);
2765         }
2766
2767         return 0;
2768 }
2769
2770
2771 /**
2772  * It enables the interrupt mask and then enable the interrupt.
2773  *
2774  * @param dev
2775  *  Pointer to struct rte_eth_dev.
2776  * @param on
2777  *  Enable or Disable
2778  *
2779  * @return
2780  *  - On success, zero.
2781  *  - On failure, a negative value.
2782  */
2783 static int
2784 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2785 {
2786         struct e1000_interrupt *intr =
2787                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2788
2789         if (on)
2790                 intr->mask |= E1000_ICR_LSC;
2791         else
2792                 intr->mask &= ~E1000_ICR_LSC;
2793
2794         return 0;
2795 }
2796
2797 /* It clears the interrupt causes and enables the interrupt.
2798  * It will be called once only during nic initialized.
2799  *
2800  * @param dev
2801  *  Pointer to struct rte_eth_dev.
2802  *
2803  * @return
2804  *  - On success, zero.
2805  *  - On failure, a negative value.
2806  */
2807 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2808 {
2809         uint32_t mask, regval;
2810         int ret;
2811         struct e1000_hw *hw =
2812                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2813         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2814         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2815         int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2816         struct rte_eth_dev_info dev_info;
2817
2818         memset(&dev_info, 0, sizeof(dev_info));
2819         ret = eth_igb_infos_get(dev, &dev_info);
2820         if (ret != 0)
2821                 return ret;
2822
2823         mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2824         regval = E1000_READ_REG(hw, E1000_EIMS);
2825         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2826
2827         return 0;
2828 }
2829
2830 /*
2831  * It reads ICR and gets interrupt causes, check it and set a bit flag
2832  * to update link status.
2833  *
2834  * @param dev
2835  *  Pointer to struct rte_eth_dev.
2836  *
2837  * @return
2838  *  - On success, zero.
2839  *  - On failure, a negative value.
2840  */
2841 static int
2842 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2843 {
2844         uint32_t icr;
2845         struct e1000_hw *hw =
2846                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2847         struct e1000_interrupt *intr =
2848                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2849
2850         igb_intr_disable(dev);
2851
2852         /* read-on-clear nic registers here */
2853         icr = E1000_READ_REG(hw, E1000_ICR);
2854
2855         intr->flags = 0;
2856         if (icr & E1000_ICR_LSC) {
2857                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2858         }
2859
2860         if (icr & E1000_ICR_VMMB)
2861                 intr->flags |= E1000_FLAG_MAILBOX;
2862
2863         return 0;
2864 }
2865
2866 /*
2867  * It executes link_update after knowing an interrupt is prsent.
2868  *
2869  * @param dev
2870  *  Pointer to struct rte_eth_dev.
2871  *
2872  * @return
2873  *  - On success, zero.
2874  *  - On failure, a negative value.
2875  */
2876 static int
2877 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2878                          struct rte_intr_handle *intr_handle)
2879 {
2880         struct e1000_hw *hw =
2881                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2882         struct e1000_interrupt *intr =
2883                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2884         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2885         struct rte_eth_link link;
2886         int ret;
2887
2888         if (intr->flags & E1000_FLAG_MAILBOX) {
2889                 igb_pf_mbx_process(dev);
2890                 intr->flags &= ~E1000_FLAG_MAILBOX;
2891         }
2892
2893         igb_intr_enable(dev);
2894         rte_intr_ack(intr_handle);
2895
2896         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2897                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2898
2899                 /* set get_link_status to check register later */
2900                 hw->mac.get_link_status = 1;
2901                 ret = eth_igb_link_update(dev, 0);
2902
2903                 /* check if link has changed */
2904                 if (ret < 0)
2905                         return 0;
2906
2907                 rte_eth_linkstatus_get(dev, &link);
2908                 if (link.link_status) {
2909                         PMD_INIT_LOG(INFO,
2910                                      " Port %d: Link Up - speed %u Mbps - %s",
2911                                      dev->data->port_id,
2912                                      (unsigned)link.link_speed,
2913                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2914                                      "full-duplex" : "half-duplex");
2915                 } else {
2916                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2917                                      dev->data->port_id);
2918                 }
2919
2920                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2921                              pci_dev->addr.domain,
2922                              pci_dev->addr.bus,
2923                              pci_dev->addr.devid,
2924                              pci_dev->addr.function);
2925                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2926                                               NULL);
2927         }
2928
2929         return 0;
2930 }
2931
2932 /**
2933  * Interrupt handler which shall be registered at first.
2934  *
2935  * @param handle
2936  *  Pointer to interrupt handle.
2937  * @param param
2938  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2939  *
2940  * @return
2941  *  void
2942  */
2943 static void
2944 eth_igb_interrupt_handler(void *param)
2945 {
2946         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2947
2948         eth_igb_interrupt_get_status(dev);
2949         eth_igb_interrupt_action(dev, dev->intr_handle);
2950 }
2951
2952 static int
2953 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2954 {
2955         uint32_t eicr;
2956         struct e1000_hw *hw =
2957                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2958         struct e1000_interrupt *intr =
2959                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2960
2961         igbvf_intr_disable(hw);
2962
2963         /* read-on-clear nic registers here */
2964         eicr = E1000_READ_REG(hw, E1000_EICR);
2965         intr->flags = 0;
2966
2967         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2968                 intr->flags |= E1000_FLAG_MAILBOX;
2969
2970         return 0;
2971 }
2972
2973 void igbvf_mbx_process(struct rte_eth_dev *dev)
2974 {
2975         struct e1000_hw *hw =
2976                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2977         struct e1000_mbx_info *mbx = &hw->mbx;
2978         u32 in_msg = 0;
2979
2980         /* peek the message first */
2981         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2982
2983         /* PF reset VF event */
2984         if (in_msg == E1000_PF_CONTROL_MSG) {
2985                 /* dummy mbx read to ack pf */
2986                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2987                         return;
2988                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2989                                               NULL);
2990         }
2991 }
2992
2993 static int
2994 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2995 {
2996         struct e1000_interrupt *intr =
2997                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2998
2999         if (intr->flags & E1000_FLAG_MAILBOX) {
3000                 igbvf_mbx_process(dev);
3001                 intr->flags &= ~E1000_FLAG_MAILBOX;
3002         }
3003
3004         igbvf_intr_enable(dev);
3005         rte_intr_ack(intr_handle);
3006
3007         return 0;
3008 }
3009
3010 static void
3011 eth_igbvf_interrupt_handler(void *param)
3012 {
3013         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3014
3015         eth_igbvf_interrupt_get_status(dev);
3016         eth_igbvf_interrupt_action(dev, dev->intr_handle);
3017 }
3018
3019 static int
3020 eth_igb_led_on(struct rte_eth_dev *dev)
3021 {
3022         struct e1000_hw *hw;
3023
3024         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3025         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3026 }
3027
3028 static int
3029 eth_igb_led_off(struct rte_eth_dev *dev)
3030 {
3031         struct e1000_hw *hw;
3032
3033         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3034         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3035 }
3036
3037 static int
3038 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3039 {
3040         struct e1000_hw *hw;
3041         uint32_t ctrl;
3042         int tx_pause;
3043         int rx_pause;
3044
3045         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3046         fc_conf->pause_time = hw->fc.pause_time;
3047         fc_conf->high_water = hw->fc.high_water;
3048         fc_conf->low_water = hw->fc.low_water;
3049         fc_conf->send_xon = hw->fc.send_xon;
3050         fc_conf->autoneg = hw->mac.autoneg;
3051
3052         /*
3053          * Return rx_pause and tx_pause status according to actual setting of
3054          * the TFCE and RFCE bits in the CTRL register.
3055          */
3056         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3057         if (ctrl & E1000_CTRL_TFCE)
3058                 tx_pause = 1;
3059         else
3060                 tx_pause = 0;
3061
3062         if (ctrl & E1000_CTRL_RFCE)
3063                 rx_pause = 1;
3064         else
3065                 rx_pause = 0;
3066
3067         if (rx_pause && tx_pause)
3068                 fc_conf->mode = RTE_FC_FULL;
3069         else if (rx_pause)
3070                 fc_conf->mode = RTE_FC_RX_PAUSE;
3071         else if (tx_pause)
3072                 fc_conf->mode = RTE_FC_TX_PAUSE;
3073         else
3074                 fc_conf->mode = RTE_FC_NONE;
3075
3076         return 0;
3077 }
3078
3079 static int
3080 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3081 {
3082         struct e1000_hw *hw;
3083         int err;
3084         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3085                 e1000_fc_none,
3086                 e1000_fc_rx_pause,
3087                 e1000_fc_tx_pause,
3088                 e1000_fc_full
3089         };
3090         uint32_t rx_buf_size;
3091         uint32_t max_high_water;
3092         uint32_t rctl;
3093
3094         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3095         if (fc_conf->autoneg != hw->mac.autoneg)
3096                 return -ENOTSUP;
3097         rx_buf_size = igb_get_rx_buffer_size(hw);
3098         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3099
3100         /* At least reserve one Ethernet frame for watermark */
3101         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3102         if ((fc_conf->high_water > max_high_water) ||
3103             (fc_conf->high_water < fc_conf->low_water)) {
3104                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3105                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3106                 return -EINVAL;
3107         }
3108
3109         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3110         hw->fc.pause_time     = fc_conf->pause_time;
3111         hw->fc.high_water     = fc_conf->high_water;
3112         hw->fc.low_water      = fc_conf->low_water;
3113         hw->fc.send_xon       = fc_conf->send_xon;
3114
3115         err = e1000_setup_link_generic(hw);
3116         if (err == E1000_SUCCESS) {
3117
3118                 /* check if we want to forward MAC frames - driver doesn't have native
3119                  * capability to do that, so we'll write the registers ourselves */
3120
3121                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3122
3123                 /* set or clear MFLCN.PMCF bit depending on configuration */
3124                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3125                         rctl |= E1000_RCTL_PMCF;
3126                 else
3127                         rctl &= ~E1000_RCTL_PMCF;
3128
3129                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3130                 E1000_WRITE_FLUSH(hw);
3131
3132                 return 0;
3133         }
3134
3135         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3136         return -EIO;
3137 }
3138
3139 #define E1000_RAH_POOLSEL_SHIFT      (18)
3140 static int
3141 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3142                 uint32_t index, uint32_t pool)
3143 {
3144         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3145         uint32_t rah;
3146
3147         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3148         rah = E1000_READ_REG(hw, E1000_RAH(index));
3149         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3150         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3151         return 0;
3152 }
3153
3154 static void
3155 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3156 {
3157         uint8_t addr[RTE_ETHER_ADDR_LEN];
3158         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3159
3160         memset(addr, 0, sizeof(addr));
3161
3162         e1000_rar_set(hw, addr, index);
3163 }
3164
3165 static int
3166 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3167                                 struct rte_ether_addr *addr)
3168 {
3169         eth_igb_rar_clear(dev, 0);
3170         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3171
3172         return 0;
3173 }
3174 /*
3175  * Virtual Function operations
3176  */
3177 static void
3178 igbvf_intr_disable(struct e1000_hw *hw)
3179 {
3180         PMD_INIT_FUNC_TRACE();
3181
3182         /* Clear interrupt mask to stop from interrupts being generated */
3183         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3184
3185         E1000_WRITE_FLUSH(hw);
3186 }
3187
3188 static void
3189 igbvf_stop_adapter(struct rte_eth_dev *dev)
3190 {
3191         u32 reg_val;
3192         u16 i;
3193         struct rte_eth_dev_info dev_info;
3194         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3195         int ret;
3196
3197         memset(&dev_info, 0, sizeof(dev_info));
3198         ret = eth_igbvf_infos_get(dev, &dev_info);
3199         if (ret != 0)
3200                 return;
3201
3202         /* Clear interrupt mask to stop from interrupts being generated */
3203         igbvf_intr_disable(hw);
3204
3205         /* Clear any pending interrupts, flush previous writes */
3206         E1000_READ_REG(hw, E1000_EICR);
3207
3208         /* Disable the transmit unit.  Each queue must be disabled. */
3209         for (i = 0; i < dev_info.max_tx_queues; i++)
3210                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3211
3212         /* Disable the receive unit by stopping each queue */
3213         for (i = 0; i < dev_info.max_rx_queues; i++) {
3214                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3215                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3216                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3217                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3218                         ;
3219         }
3220
3221         /* flush all queues disables */
3222         E1000_WRITE_FLUSH(hw);
3223         msec_delay(2);
3224 }
3225
3226 static int eth_igbvf_link_update(struct e1000_hw *hw)
3227 {
3228         struct e1000_mbx_info *mbx = &hw->mbx;
3229         struct e1000_mac_info *mac = &hw->mac;
3230         int ret_val = E1000_SUCCESS;
3231
3232         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3233
3234         /*
3235          * We only want to run this if there has been a rst asserted.
3236          * in this case that could mean a link change, device reset,
3237          * or a virtual function reset
3238          */
3239
3240         /* If we were hit with a reset or timeout drop the link */
3241         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3242                 mac->get_link_status = TRUE;
3243
3244         if (!mac->get_link_status)
3245                 goto out;
3246
3247         /* if link status is down no point in checking to see if pf is up */
3248         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3249                 goto out;
3250
3251         /* if we passed all the tests above then the link is up and we no
3252          * longer need to check for link */
3253         mac->get_link_status = FALSE;
3254
3255 out:
3256         return ret_val;
3257 }
3258
3259
3260 static int
3261 igbvf_dev_configure(struct rte_eth_dev *dev)
3262 {
3263         struct rte_eth_conf* conf = &dev->data->dev_conf;
3264
3265         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3266                      dev->data->port_id);
3267
3268         /*
3269          * VF has no ability to enable/disable HW CRC
3270          * Keep the persistent behavior the same as Host PF
3271          */
3272 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3273         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3274                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3275                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3276         }
3277 #else
3278         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3279                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3280                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3281         }
3282 #endif
3283
3284         return 0;
3285 }
3286
3287 static int
3288 igbvf_dev_start(struct rte_eth_dev *dev)
3289 {
3290         struct e1000_hw *hw =
3291                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3292         struct e1000_adapter *adapter =
3293                 E1000_DEV_PRIVATE(dev->data->dev_private);
3294         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3295         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3296         int ret;
3297         uint32_t intr_vector = 0;
3298
3299         PMD_INIT_FUNC_TRACE();
3300
3301         hw->mac.ops.reset_hw(hw);
3302         adapter->stopped = 0;
3303
3304         /* Set all vfta */
3305         igbvf_set_vfta_all(dev,1);
3306
3307         eth_igbvf_tx_init(dev);
3308
3309         /* This can fail when allocating mbufs for descriptor rings */
3310         ret = eth_igbvf_rx_init(dev);
3311         if (ret) {
3312                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3313                 igb_dev_clear_queues(dev);
3314                 return ret;
3315         }
3316
3317         /* check and configure queue intr-vector mapping */
3318         if (rte_intr_cap_multiple(intr_handle) &&
3319             dev->data->dev_conf.intr_conf.rxq) {
3320                 intr_vector = dev->data->nb_rx_queues;
3321                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3322                 if (ret)
3323                         return ret;
3324         }
3325
3326         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3327                 intr_handle->intr_vec =
3328                         rte_zmalloc("intr_vec",
3329                                     dev->data->nb_rx_queues * sizeof(int), 0);
3330                 if (!intr_handle->intr_vec) {
3331                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3332                                      " intr_vec", dev->data->nb_rx_queues);
3333                         return -ENOMEM;
3334                 }
3335         }
3336
3337         eth_igbvf_configure_msix_intr(dev);
3338
3339         /* enable uio/vfio intr/eventfd mapping */
3340         rte_intr_enable(intr_handle);
3341
3342         /* resume enabled intr since hw reset */
3343         igbvf_intr_enable(dev);
3344
3345         return 0;
3346 }
3347
3348 static void
3349 igbvf_dev_stop(struct rte_eth_dev *dev)
3350 {
3351         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3352         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3353
3354         PMD_INIT_FUNC_TRACE();
3355
3356         igbvf_stop_adapter(dev);
3357
3358         /*
3359           * Clear what we set, but we still keep shadow_vfta to
3360           * restore after device starts
3361           */
3362         igbvf_set_vfta_all(dev,0);
3363
3364         igb_dev_clear_queues(dev);
3365
3366         /* disable intr eventfd mapping */
3367         rte_intr_disable(intr_handle);
3368
3369         /* Clean datapath event and queue/vec mapping */
3370         rte_intr_efd_disable(intr_handle);
3371         if (intr_handle->intr_vec) {
3372                 rte_free(intr_handle->intr_vec);
3373                 intr_handle->intr_vec = NULL;
3374         }
3375 }
3376
3377 static void
3378 igbvf_dev_close(struct rte_eth_dev *dev)
3379 {
3380         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3381         struct e1000_adapter *adapter =
3382                 E1000_DEV_PRIVATE(dev->data->dev_private);
3383         struct rte_ether_addr addr;
3384
3385         PMD_INIT_FUNC_TRACE();
3386
3387         e1000_reset_hw(hw);
3388
3389         igbvf_dev_stop(dev);
3390         adapter->stopped = 1;
3391         igb_dev_free_queues(dev);
3392
3393         /**
3394          * reprogram the RAR with a zero mac address,
3395          * to ensure that the VF traffic goes to the PF
3396          * after stop, close and detach of the VF.
3397          **/
3398
3399         memset(&addr, 0, sizeof(addr));
3400         igbvf_default_mac_addr_set(dev, &addr);
3401 }
3402
3403 static int
3404 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3405 {
3406         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3407
3408         /* Set both unicast and multicast promisc */
3409         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3410
3411         return 0;
3412 }
3413
3414 static int
3415 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3416 {
3417         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3418
3419         /* If in allmulticast mode leave multicast promisc */
3420         if (dev->data->all_multicast == 1)
3421                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3422         else
3423                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3424
3425         return 0;
3426 }
3427
3428 static void
3429 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3430 {
3431         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3432
3433         /* In promiscuous mode multicast promisc already set */
3434         if (dev->data->promiscuous == 0)
3435                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3436 }
3437
3438 static void
3439 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3440 {
3441         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3442
3443         /* In promiscuous mode leave multicast promisc enabled */
3444         if (dev->data->promiscuous == 0)
3445                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3446 }
3447
3448 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3449 {
3450         struct e1000_mbx_info *mbx = &hw->mbx;
3451         uint32_t msgbuf[2];
3452         s32 err;
3453
3454         /* After set vlan, vlan strip will also be enabled in igb driver*/
3455         msgbuf[0] = E1000_VF_SET_VLAN;
3456         msgbuf[1] = vid;
3457         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3458         if (on)
3459                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3460
3461         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3462         if (err)
3463                 goto mbx_err;
3464
3465         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3466         if (err)
3467                 goto mbx_err;
3468
3469         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3470         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3471                 err = -EINVAL;
3472
3473 mbx_err:
3474         return err;
3475 }
3476
3477 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3478 {
3479         struct e1000_hw *hw =
3480                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3481         struct e1000_vfta * shadow_vfta =
3482                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3483         int i = 0, j = 0, vfta = 0, mask = 1;
3484
3485         for (i = 0; i < IGB_VFTA_SIZE; i++){
3486                 vfta = shadow_vfta->vfta[i];
3487                 if(vfta){
3488                         mask = 1;
3489                         for (j = 0; j < 32; j++){
3490                                 if(vfta & mask)
3491                                         igbvf_set_vfta(hw,
3492                                                 (uint16_t)((i<<5)+j), on);
3493                                 mask<<=1;
3494                         }
3495                 }
3496         }
3497
3498 }
3499
3500 static int
3501 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3502 {
3503         struct e1000_hw *hw =
3504                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3505         struct e1000_vfta * shadow_vfta =
3506                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3507         uint32_t vid_idx = 0;
3508         uint32_t vid_bit = 0;
3509         int ret = 0;
3510
3511         PMD_INIT_FUNC_TRACE();
3512
3513         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3514         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3515         if(ret){
3516                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3517                 return ret;
3518         }
3519         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3520         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3521
3522         /*Save what we set and retore it after device reset*/
3523         if (on)
3524                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3525         else
3526                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3527
3528         return 0;
3529 }
3530
3531 static int
3532 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3533 {
3534         struct e1000_hw *hw =
3535                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3536
3537         /* index is not used by rar_set() */
3538         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3539         return 0;
3540 }
3541
3542
3543 static int
3544 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3545                         struct rte_eth_rss_reta_entry64 *reta_conf,
3546                         uint16_t reta_size)
3547 {
3548         uint8_t i, j, mask;
3549         uint32_t reta, r;
3550         uint16_t idx, shift;
3551         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3552
3553         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3554                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3555                         "(%d) doesn't match the number hardware can supported "
3556                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3557                 return -EINVAL;
3558         }
3559
3560         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3561                 idx = i / RTE_RETA_GROUP_SIZE;
3562                 shift = i % RTE_RETA_GROUP_SIZE;
3563                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3564                                                 IGB_4_BIT_MASK);
3565                 if (!mask)
3566                         continue;
3567                 if (mask == IGB_4_BIT_MASK)
3568                         r = 0;
3569                 else
3570                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3571                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3572                         if (mask & (0x1 << j))
3573                                 reta |= reta_conf[idx].reta[shift + j] <<
3574                                                         (CHAR_BIT * j);
3575                         else
3576                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3577                 }
3578                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3579         }
3580
3581         return 0;
3582 }
3583
3584 static int
3585 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3586                        struct rte_eth_rss_reta_entry64 *reta_conf,
3587                        uint16_t reta_size)
3588 {
3589         uint8_t i, j, mask;
3590         uint32_t reta;
3591         uint16_t idx, shift;
3592         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3593
3594         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3595                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3596                         "(%d) doesn't match the number hardware can supported "
3597                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3598                 return -EINVAL;
3599         }
3600
3601         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3602                 idx = i / RTE_RETA_GROUP_SIZE;
3603                 shift = i % RTE_RETA_GROUP_SIZE;
3604                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3605                                                 IGB_4_BIT_MASK);
3606                 if (!mask)
3607                         continue;
3608                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3609                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3610                         if (mask & (0x1 << j))
3611                                 reta_conf[idx].reta[shift + j] =
3612                                         ((reta >> (CHAR_BIT * j)) &
3613                                                 IGB_8_BIT_MASK);
3614                 }
3615         }
3616
3617         return 0;
3618 }
3619
3620 int
3621 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3622                         struct rte_eth_syn_filter *filter,
3623                         bool add)
3624 {
3625         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3626         struct e1000_filter_info *filter_info =
3627                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3628         uint32_t synqf, rfctl;
3629
3630         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3631                 return -EINVAL;
3632
3633         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3634
3635         if (add) {
3636                 if (synqf & E1000_SYN_FILTER_ENABLE)
3637                         return -EINVAL;
3638
3639                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3640                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3641
3642                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3643                 if (filter->hig_pri)
3644                         rfctl |= E1000_RFCTL_SYNQFP;
3645                 else
3646                         rfctl &= ~E1000_RFCTL_SYNQFP;
3647
3648                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3649         } else {
3650                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3651                         return -ENOENT;
3652                 synqf = 0;
3653         }
3654
3655         filter_info->syn_info = synqf;
3656         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3657         E1000_WRITE_FLUSH(hw);
3658         return 0;
3659 }
3660
3661 static int
3662 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3663                         struct rte_eth_syn_filter *filter)
3664 {
3665         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3666         uint32_t synqf, rfctl;
3667
3668         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3669         if (synqf & E1000_SYN_FILTER_ENABLE) {
3670                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3671                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3672                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3673                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3674                 return 0;
3675         }
3676
3677         return -ENOENT;
3678 }
3679
3680 static int
3681 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3682                         enum rte_filter_op filter_op,
3683                         void *arg)
3684 {
3685         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3686         int ret;
3687
3688         MAC_TYPE_FILTER_SUP(hw->mac.type);
3689
3690         if (filter_op == RTE_ETH_FILTER_NOP)
3691                 return 0;
3692
3693         if (arg == NULL) {
3694                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3695                             filter_op);
3696                 return -EINVAL;
3697         }
3698
3699         switch (filter_op) {
3700         case RTE_ETH_FILTER_ADD:
3701                 ret = eth_igb_syn_filter_set(dev,
3702                                 (struct rte_eth_syn_filter *)arg,
3703                                 TRUE);
3704                 break;
3705         case RTE_ETH_FILTER_DELETE:
3706                 ret = eth_igb_syn_filter_set(dev,
3707                                 (struct rte_eth_syn_filter *)arg,
3708                                 FALSE);
3709                 break;
3710         case RTE_ETH_FILTER_GET:
3711                 ret = eth_igb_syn_filter_get(dev,
3712                                 (struct rte_eth_syn_filter *)arg);
3713                 break;
3714         default:
3715                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3716                 ret = -EINVAL;
3717                 break;
3718         }
3719
3720         return ret;
3721 }
3722
3723 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3724 static inline int
3725 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3726                         struct e1000_2tuple_filter_info *filter_info)
3727 {
3728         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3729                 return -EINVAL;
3730         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3731                 return -EINVAL;  /* filter index is out of range. */
3732         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3733                 return -EINVAL;  /* flags is invalid. */
3734
3735         switch (filter->dst_port_mask) {
3736         case UINT16_MAX:
3737                 filter_info->dst_port_mask = 0;
3738                 filter_info->dst_port = filter->dst_port;
3739                 break;
3740         case 0:
3741                 filter_info->dst_port_mask = 1;
3742                 break;
3743         default:
3744                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3745                 return -EINVAL;
3746         }
3747
3748         switch (filter->proto_mask) {
3749         case UINT8_MAX:
3750                 filter_info->proto_mask = 0;
3751                 filter_info->proto = filter->proto;
3752                 break;
3753         case 0:
3754                 filter_info->proto_mask = 1;
3755                 break;
3756         default:
3757                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3758                 return -EINVAL;
3759         }
3760
3761         filter_info->priority = (uint8_t)filter->priority;
3762         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3763                 filter_info->tcp_flags = filter->tcp_flags;
3764         else
3765                 filter_info->tcp_flags = 0;
3766
3767         return 0;
3768 }
3769
3770 static inline struct e1000_2tuple_filter *
3771 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3772                         struct e1000_2tuple_filter_info *key)
3773 {
3774         struct e1000_2tuple_filter *it;
3775
3776         TAILQ_FOREACH(it, filter_list, entries) {
3777                 if (memcmp(key, &it->filter_info,
3778                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3779                         return it;
3780                 }
3781         }
3782         return NULL;
3783 }
3784
3785 /* inject a igb 2tuple filter to HW */
3786 static inline void
3787 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3788                            struct e1000_2tuple_filter *filter)
3789 {
3790         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3791         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3792         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3793         int i;
3794
3795         i = filter->index;
3796         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3797         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3798                 imir |= E1000_IMIR_PORT_BP;
3799         else
3800                 imir &= ~E1000_IMIR_PORT_BP;
3801
3802         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3803
3804         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3805         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3806         ttqf |= (uint32_t)(filter->filter_info.proto &
3807                                                 E1000_TTQF_PROTOCOL_MASK);
3808         if (filter->filter_info.proto_mask == 0)
3809                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3810
3811         /* tcp flags bits setting. */
3812         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3813                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3814                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3815                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3816                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3817                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3818                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3819                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3820                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3821                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3822                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3823                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3824                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3825         } else {
3826                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3827         }
3828         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3829         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3830         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3831 }
3832
3833 /*
3834  * igb_add_2tuple_filter - add a 2tuple filter
3835  *
3836  * @param
3837  * dev: Pointer to struct rte_eth_dev.
3838  * ntuple_filter: ponter to the filter that will be added.
3839  *
3840  * @return
3841  *    - On success, zero.
3842  *    - On failure, a negative value.
3843  */
3844 static int
3845 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3846                         struct rte_eth_ntuple_filter *ntuple_filter)
3847 {
3848         struct e1000_filter_info *filter_info =
3849                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3850         struct e1000_2tuple_filter *filter;
3851         int i, ret;
3852
3853         filter = rte_zmalloc("e1000_2tuple_filter",
3854                         sizeof(struct e1000_2tuple_filter), 0);
3855         if (filter == NULL)
3856                 return -ENOMEM;
3857
3858         ret = ntuple_filter_to_2tuple(ntuple_filter,
3859                                       &filter->filter_info);
3860         if (ret < 0) {
3861                 rte_free(filter);
3862                 return ret;
3863         }
3864         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3865                                          &filter->filter_info) != NULL) {
3866                 PMD_DRV_LOG(ERR, "filter exists.");
3867                 rte_free(filter);
3868                 return -EEXIST;
3869         }
3870         filter->queue = ntuple_filter->queue;
3871
3872         /*
3873          * look for an unused 2tuple filter index,
3874          * and insert the filter to list.
3875          */
3876         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3877                 if (!(filter_info->twotuple_mask & (1 << i))) {
3878                         filter_info->twotuple_mask |= 1 << i;
3879                         filter->index = i;
3880                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3881                                           filter,
3882                                           entries);
3883                         break;
3884                 }
3885         }
3886         if (i >= E1000_MAX_TTQF_FILTERS) {
3887                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3888                 rte_free(filter);
3889                 return -ENOSYS;
3890         }
3891
3892         igb_inject_2uple_filter(dev, filter);
3893         return 0;
3894 }
3895
3896 int
3897 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3898                         struct e1000_2tuple_filter *filter)
3899 {
3900         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3901         struct e1000_filter_info *filter_info =
3902                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3903
3904         filter_info->twotuple_mask &= ~(1 << filter->index);
3905         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3906         rte_free(filter);
3907
3908         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3909         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3910         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3911         return 0;
3912 }
3913
3914 /*
3915  * igb_remove_2tuple_filter - remove a 2tuple filter
3916  *
3917  * @param
3918  * dev: Pointer to struct rte_eth_dev.
3919  * ntuple_filter: ponter to the filter that will be removed.
3920  *
3921  * @return
3922  *    - On success, zero.
3923  *    - On failure, a negative value.
3924  */
3925 static int
3926 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3927                         struct rte_eth_ntuple_filter *ntuple_filter)
3928 {
3929         struct e1000_filter_info *filter_info =
3930                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3931         struct e1000_2tuple_filter_info filter_2tuple;
3932         struct e1000_2tuple_filter *filter;
3933         int ret;
3934
3935         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3936         ret = ntuple_filter_to_2tuple(ntuple_filter,
3937                                       &filter_2tuple);
3938         if (ret < 0)
3939                 return ret;
3940
3941         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3942                                          &filter_2tuple);
3943         if (filter == NULL) {
3944                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3945                 return -ENOENT;
3946         }
3947
3948         igb_delete_2tuple_filter(dev, filter);
3949
3950         return 0;
3951 }
3952
3953 /* inject a igb flex filter to HW */
3954 static inline void
3955 igb_inject_flex_filter(struct rte_eth_dev *dev,
3956                            struct e1000_flex_filter *filter)
3957 {
3958         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3959         uint32_t wufc, queueing;
3960         uint32_t reg_off;
3961         uint8_t i, j = 0;
3962
3963         wufc = E1000_READ_REG(hw, E1000_WUFC);
3964         if (filter->index < E1000_MAX_FHFT)
3965                 reg_off = E1000_FHFT(filter->index);
3966         else
3967                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3968
3969         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3970                         (E1000_WUFC_FLX0 << filter->index));
3971         queueing = filter->filter_info.len |
3972                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3973                 (filter->filter_info.priority <<
3974                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3975         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3976                         queueing);
3977
3978         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3979                 E1000_WRITE_REG(hw, reg_off,
3980                                 filter->filter_info.dwords[j]);
3981                 reg_off += sizeof(uint32_t);
3982                 E1000_WRITE_REG(hw, reg_off,
3983                                 filter->filter_info.dwords[++j]);
3984                 reg_off += sizeof(uint32_t);
3985                 E1000_WRITE_REG(hw, reg_off,
3986                         (uint32_t)filter->filter_info.mask[i]);
3987                 reg_off += sizeof(uint32_t) * 2;
3988                 ++j;
3989         }
3990 }
3991
3992 static inline struct e1000_flex_filter *
3993 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3994                         struct e1000_flex_filter_info *key)
3995 {
3996         struct e1000_flex_filter *it;
3997
3998         TAILQ_FOREACH(it, filter_list, entries) {
3999                 if (memcmp(key, &it->filter_info,
4000                         sizeof(struct e1000_flex_filter_info)) == 0)
4001                         return it;
4002         }
4003
4004         return NULL;
4005 }
4006
4007 /* remove a flex byte filter
4008  * @param
4009  * dev: Pointer to struct rte_eth_dev.
4010  * filter: the pointer of the filter will be removed.
4011  */
4012 void
4013 igb_remove_flex_filter(struct rte_eth_dev *dev,
4014                         struct e1000_flex_filter *filter)
4015 {
4016         struct e1000_filter_info *filter_info =
4017                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4018         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4019         uint32_t wufc, i;
4020         uint32_t reg_off;
4021
4022         wufc = E1000_READ_REG(hw, E1000_WUFC);
4023         if (filter->index < E1000_MAX_FHFT)
4024                 reg_off = E1000_FHFT(filter->index);
4025         else
4026                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4027
4028         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4029                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4030
4031         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4032                 (~(E1000_WUFC_FLX0 << filter->index)));
4033
4034         filter_info->flex_mask &= ~(1 << filter->index);
4035         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4036         rte_free(filter);
4037 }
4038
4039 int
4040 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4041                         struct rte_eth_flex_filter *filter,
4042                         bool add)
4043 {
4044         struct e1000_filter_info *filter_info =
4045                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4046         struct e1000_flex_filter *flex_filter, *it;
4047         uint32_t mask;
4048         uint8_t shift, i;
4049
4050         flex_filter = rte_zmalloc("e1000_flex_filter",
4051                         sizeof(struct e1000_flex_filter), 0);
4052         if (flex_filter == NULL)
4053                 return -ENOMEM;
4054
4055         flex_filter->filter_info.len = filter->len;
4056         flex_filter->filter_info.priority = filter->priority;
4057         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4058         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4059                 mask = 0;
4060                 /* reverse bits in flex filter's mask*/
4061                 for (shift = 0; shift < CHAR_BIT; shift++) {
4062                         if (filter->mask[i] & (0x01 << shift))
4063                                 mask |= (0x80 >> shift);
4064                 }
4065                 flex_filter->filter_info.mask[i] = mask;
4066         }
4067
4068         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4069                                 &flex_filter->filter_info);
4070         if (it == NULL && !add) {
4071                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4072                 rte_free(flex_filter);
4073                 return -ENOENT;
4074         }
4075         if (it != NULL && add) {
4076                 PMD_DRV_LOG(ERR, "filter exists.");
4077                 rte_free(flex_filter);
4078                 return -EEXIST;
4079         }
4080
4081         if (add) {
4082                 flex_filter->queue = filter->queue;
4083                 /*
4084                  * look for an unused flex filter index
4085                  * and insert the filter into the list.
4086                  */
4087                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4088                         if (!(filter_info->flex_mask & (1 << i))) {
4089                                 filter_info->flex_mask |= 1 << i;
4090                                 flex_filter->index = i;
4091                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4092                                         flex_filter,
4093                                         entries);
4094                                 break;
4095                         }
4096                 }
4097                 if (i >= E1000_MAX_FLEX_FILTERS) {
4098                         PMD_DRV_LOG(ERR, "flex filters are full.");
4099                         rte_free(flex_filter);
4100                         return -ENOSYS;
4101                 }
4102
4103                 igb_inject_flex_filter(dev, flex_filter);
4104
4105         } else {
4106                 igb_remove_flex_filter(dev, it);
4107                 rte_free(flex_filter);
4108         }
4109
4110         return 0;
4111 }
4112
4113 static int
4114 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4115                         struct rte_eth_flex_filter *filter)
4116 {
4117         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4118         struct e1000_filter_info *filter_info =
4119                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4120         struct e1000_flex_filter flex_filter, *it;
4121         uint32_t wufc, queueing, wufc_en = 0;
4122
4123         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4124         flex_filter.filter_info.len = filter->len;
4125         flex_filter.filter_info.priority = filter->priority;
4126         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4127         memcpy(flex_filter.filter_info.mask, filter->mask,
4128                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4129
4130         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4131                                 &flex_filter.filter_info);
4132         if (it == NULL) {
4133                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4134                 return -ENOENT;
4135         }
4136
4137         wufc = E1000_READ_REG(hw, E1000_WUFC);
4138         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4139
4140         if ((wufc & wufc_en) == wufc_en) {
4141                 uint32_t reg_off = 0;
4142                 if (it->index < E1000_MAX_FHFT)
4143                         reg_off = E1000_FHFT(it->index);
4144                 else
4145                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4146
4147                 queueing = E1000_READ_REG(hw,
4148                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4149                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4150                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4151                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4152                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4153                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4154                 return 0;
4155         }
4156         return -ENOENT;
4157 }
4158
4159 static int
4160 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4161                         enum rte_filter_op filter_op,
4162                         void *arg)
4163 {
4164         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4165         struct rte_eth_flex_filter *filter;
4166         int ret = 0;
4167
4168         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4169
4170         if (filter_op == RTE_ETH_FILTER_NOP)
4171                 return ret;
4172
4173         if (arg == NULL) {
4174                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4175                             filter_op);
4176                 return -EINVAL;
4177         }
4178
4179         filter = (struct rte_eth_flex_filter *)arg;
4180         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4181             || filter->len % sizeof(uint64_t) != 0) {
4182                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4183                 return -EINVAL;
4184         }
4185         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4186                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4187                 return -EINVAL;
4188         }
4189
4190         switch (filter_op) {
4191         case RTE_ETH_FILTER_ADD:
4192                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4193                 break;
4194         case RTE_ETH_FILTER_DELETE:
4195                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4196                 break;
4197         case RTE_ETH_FILTER_GET:
4198                 ret = eth_igb_get_flex_filter(dev, filter);
4199                 break;
4200         default:
4201                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4202                 ret = -EINVAL;
4203                 break;
4204         }
4205
4206         return ret;
4207 }
4208
4209 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4210 static inline int
4211 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4212                         struct e1000_5tuple_filter_info *filter_info)
4213 {
4214         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4215                 return -EINVAL;
4216         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4217                 return -EINVAL;  /* filter index is out of range. */
4218         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4219                 return -EINVAL;  /* flags is invalid. */
4220
4221         switch (filter->dst_ip_mask) {
4222         case UINT32_MAX:
4223                 filter_info->dst_ip_mask = 0;
4224                 filter_info->dst_ip = filter->dst_ip;
4225                 break;
4226         case 0:
4227                 filter_info->dst_ip_mask = 1;
4228                 break;
4229         default:
4230                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4231                 return -EINVAL;
4232         }
4233
4234         switch (filter->src_ip_mask) {
4235         case UINT32_MAX:
4236                 filter_info->src_ip_mask = 0;
4237                 filter_info->src_ip = filter->src_ip;
4238                 break;
4239         case 0:
4240                 filter_info->src_ip_mask = 1;
4241                 break;
4242         default:
4243                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4244                 return -EINVAL;
4245         }
4246
4247         switch (filter->dst_port_mask) {
4248         case UINT16_MAX:
4249                 filter_info->dst_port_mask = 0;
4250                 filter_info->dst_port = filter->dst_port;
4251                 break;
4252         case 0:
4253                 filter_info->dst_port_mask = 1;
4254                 break;
4255         default:
4256                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4257                 return -EINVAL;
4258         }
4259
4260         switch (filter->src_port_mask) {
4261         case UINT16_MAX:
4262                 filter_info->src_port_mask = 0;
4263                 filter_info->src_port = filter->src_port;
4264                 break;
4265         case 0:
4266                 filter_info->src_port_mask = 1;
4267                 break;
4268         default:
4269                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4270                 return -EINVAL;
4271         }
4272
4273         switch (filter->proto_mask) {
4274         case UINT8_MAX:
4275                 filter_info->proto_mask = 0;
4276                 filter_info->proto = filter->proto;
4277                 break;
4278         case 0:
4279                 filter_info->proto_mask = 1;
4280                 break;
4281         default:
4282                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4283                 return -EINVAL;
4284         }
4285
4286         filter_info->priority = (uint8_t)filter->priority;
4287         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4288                 filter_info->tcp_flags = filter->tcp_flags;
4289         else
4290                 filter_info->tcp_flags = 0;
4291
4292         return 0;
4293 }
4294
4295 static inline struct e1000_5tuple_filter *
4296 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4297                         struct e1000_5tuple_filter_info *key)
4298 {
4299         struct e1000_5tuple_filter *it;
4300
4301         TAILQ_FOREACH(it, filter_list, entries) {
4302                 if (memcmp(key, &it->filter_info,
4303                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4304                         return it;
4305                 }
4306         }
4307         return NULL;
4308 }
4309
4310 /* inject a igb 5-tuple filter to HW */
4311 static inline void
4312 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4313                            struct e1000_5tuple_filter *filter)
4314 {
4315         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4316         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4317         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4318         uint8_t i;
4319
4320         i = filter->index;
4321         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4322         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4323                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4324         if (filter->filter_info.dst_ip_mask == 0)
4325                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4326         if (filter->filter_info.src_port_mask == 0)
4327                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4328         if (filter->filter_info.proto_mask == 0)
4329                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4330         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4331                 E1000_FTQF_QUEUE_MASK;
4332         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4333         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4334         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4335         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4336
4337         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4338         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4339
4340         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4341         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4342                 imir |= E1000_IMIR_PORT_BP;
4343         else
4344                 imir &= ~E1000_IMIR_PORT_BP;
4345         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4346
4347         /* tcp flags bits setting. */
4348         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4349                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4350                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4351                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4352                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4353                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4354                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4355                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4356                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4357                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4358                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4359                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4360                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4361         } else {
4362                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4363         }
4364         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4365         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4366 }
4367
4368 /*
4369  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4370  *
4371  * @param
4372  * dev: Pointer to struct rte_eth_dev.
4373  * ntuple_filter: ponter to the filter that will be added.
4374  *
4375  * @return
4376  *    - On success, zero.
4377  *    - On failure, a negative value.
4378  */
4379 static int
4380 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4381                         struct rte_eth_ntuple_filter *ntuple_filter)
4382 {
4383         struct e1000_filter_info *filter_info =
4384                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4385         struct e1000_5tuple_filter *filter;
4386         uint8_t i;
4387         int ret;
4388
4389         filter = rte_zmalloc("e1000_5tuple_filter",
4390                         sizeof(struct e1000_5tuple_filter), 0);
4391         if (filter == NULL)
4392                 return -ENOMEM;
4393
4394         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4395                                             &filter->filter_info);
4396         if (ret < 0) {
4397                 rte_free(filter);
4398                 return ret;
4399         }
4400
4401         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4402                                          &filter->filter_info) != NULL) {
4403                 PMD_DRV_LOG(ERR, "filter exists.");
4404                 rte_free(filter);
4405                 return -EEXIST;
4406         }
4407         filter->queue = ntuple_filter->queue;
4408
4409         /*
4410          * look for an unused 5tuple filter index,
4411          * and insert the filter to list.
4412          */
4413         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4414                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4415                         filter_info->fivetuple_mask |= 1 << i;
4416                         filter->index = i;
4417                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4418                                           filter,
4419                                           entries);
4420                         break;
4421                 }
4422         }
4423         if (i >= E1000_MAX_FTQF_FILTERS) {
4424                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4425                 rte_free(filter);
4426                 return -ENOSYS;
4427         }
4428
4429         igb_inject_5tuple_filter_82576(dev, filter);
4430         return 0;
4431 }
4432
4433 int
4434 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4435                                 struct e1000_5tuple_filter *filter)
4436 {
4437         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4438         struct e1000_filter_info *filter_info =
4439                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4440
4441         filter_info->fivetuple_mask &= ~(1 << filter->index);
4442         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4443         rte_free(filter);
4444
4445         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4446                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4447         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4448         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4449         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4450         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4451         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4452         return 0;
4453 }
4454
4455 /*
4456  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4457  *
4458  * @param
4459  * dev: Pointer to struct rte_eth_dev.
4460  * ntuple_filter: ponter to the filter that will be removed.
4461  *
4462  * @return
4463  *    - On success, zero.
4464  *    - On failure, a negative value.
4465  */
4466 static int
4467 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4468                                 struct rte_eth_ntuple_filter *ntuple_filter)
4469 {
4470         struct e1000_filter_info *filter_info =
4471                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4472         struct e1000_5tuple_filter_info filter_5tuple;
4473         struct e1000_5tuple_filter *filter;
4474         int ret;
4475
4476         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4477         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4478                                             &filter_5tuple);
4479         if (ret < 0)
4480                 return ret;
4481
4482         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4483                                          &filter_5tuple);
4484         if (filter == NULL) {
4485                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4486                 return -ENOENT;
4487         }
4488
4489         igb_delete_5tuple_filter_82576(dev, filter);
4490
4491         return 0;
4492 }
4493
4494 static int
4495 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4496 {
4497         uint32_t rctl;
4498         struct e1000_hw *hw;
4499         struct rte_eth_dev_info dev_info;
4500         uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4501         int ret;
4502
4503         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4504
4505 #ifdef RTE_LIBRTE_82571_SUPPORT
4506         /* XXX: not bigger than max_rx_pktlen */
4507         if (hw->mac.type == e1000_82571)
4508                 return -ENOTSUP;
4509 #endif
4510         ret = eth_igb_infos_get(dev, &dev_info);
4511         if (ret != 0)
4512                 return ret;
4513
4514         /* check that mtu is within the allowed range */
4515         if (mtu < RTE_ETHER_MIN_MTU ||
4516                         frame_size > dev_info.max_rx_pktlen)
4517                 return -EINVAL;
4518
4519         /* refuse mtu that requires the support of scattered packets when this
4520          * feature has not been enabled before. */
4521         if (!dev->data->scattered_rx &&
4522             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4523                 return -EINVAL;
4524
4525         rctl = E1000_READ_REG(hw, E1000_RCTL);
4526
4527         /* switch to jumbo mode if needed */
4528         if (frame_size > RTE_ETHER_MAX_LEN) {
4529                 dev->data->dev_conf.rxmode.offloads |=
4530                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4531                 rctl |= E1000_RCTL_LPE;
4532         } else {
4533                 dev->data->dev_conf.rxmode.offloads &=
4534                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4535                 rctl &= ~E1000_RCTL_LPE;
4536         }
4537         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4538
4539         /* update max frame size */
4540         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4541
4542         E1000_WRITE_REG(hw, E1000_RLPML,
4543                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4544
4545         return 0;
4546 }
4547
4548 /*
4549  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4550  *
4551  * @param
4552  * dev: Pointer to struct rte_eth_dev.
4553  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4554  * add: if true, add filter, if false, remove filter
4555  *
4556  * @return
4557  *    - On success, zero.
4558  *    - On failure, a negative value.
4559  */
4560 int
4561 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4562                         struct rte_eth_ntuple_filter *ntuple_filter,
4563                         bool add)
4564 {
4565         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4566         int ret;
4567
4568         switch (ntuple_filter->flags) {
4569         case RTE_5TUPLE_FLAGS:
4570         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4571                 if (hw->mac.type != e1000_82576)
4572                         return -ENOTSUP;
4573                 if (add)
4574                         ret = igb_add_5tuple_filter_82576(dev,
4575                                                           ntuple_filter);
4576                 else
4577                         ret = igb_remove_5tuple_filter_82576(dev,
4578                                                              ntuple_filter);
4579                 break;
4580         case RTE_2TUPLE_FLAGS:
4581         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4582                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4583                         hw->mac.type != e1000_i210 &&
4584                         hw->mac.type != e1000_i211)
4585                         return -ENOTSUP;
4586                 if (add)
4587                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4588                 else
4589                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4590                 break;
4591         default:
4592                 ret = -EINVAL;
4593                 break;
4594         }
4595
4596         return ret;
4597 }
4598
4599 /*
4600  * igb_get_ntuple_filter - get a ntuple filter
4601  *
4602  * @param
4603  * dev: Pointer to struct rte_eth_dev.
4604  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4605  *
4606  * @return
4607  *    - On success, zero.
4608  *    - On failure, a negative value.
4609  */
4610 static int
4611 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4612                         struct rte_eth_ntuple_filter *ntuple_filter)
4613 {
4614         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4615         struct e1000_filter_info *filter_info =
4616                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4617         struct e1000_5tuple_filter_info filter_5tuple;
4618         struct e1000_2tuple_filter_info filter_2tuple;
4619         struct e1000_5tuple_filter *p_5tuple_filter;
4620         struct e1000_2tuple_filter *p_2tuple_filter;
4621         int ret;
4622
4623         switch (ntuple_filter->flags) {
4624         case RTE_5TUPLE_FLAGS:
4625         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4626                 if (hw->mac.type != e1000_82576)
4627                         return -ENOTSUP;
4628                 memset(&filter_5tuple,
4629                         0,
4630                         sizeof(struct e1000_5tuple_filter_info));
4631                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4632                                                     &filter_5tuple);
4633                 if (ret < 0)
4634                         return ret;
4635                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4636                                         &filter_info->fivetuple_list,
4637                                         &filter_5tuple);
4638                 if (p_5tuple_filter == NULL) {
4639                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4640                         return -ENOENT;
4641                 }
4642                 ntuple_filter->queue = p_5tuple_filter->queue;
4643                 break;
4644         case RTE_2TUPLE_FLAGS:
4645         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4646                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4647                         return -ENOTSUP;
4648                 memset(&filter_2tuple,
4649                         0,
4650                         sizeof(struct e1000_2tuple_filter_info));
4651                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4652                 if (ret < 0)
4653                         return ret;
4654                 p_2tuple_filter = igb_2tuple_filter_lookup(
4655                                         &filter_info->twotuple_list,
4656                                         &filter_2tuple);
4657                 if (p_2tuple_filter == NULL) {
4658                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4659                         return -ENOENT;
4660                 }
4661                 ntuple_filter->queue = p_2tuple_filter->queue;
4662                 break;
4663         default:
4664                 ret = -EINVAL;
4665                 break;
4666         }
4667
4668         return 0;
4669 }
4670
4671 /*
4672  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4673  * @dev: pointer to rte_eth_dev structure
4674  * @filter_op:operation will be taken.
4675  * @arg: a pointer to specific structure corresponding to the filter_op
4676  */
4677 static int
4678 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4679                                 enum rte_filter_op filter_op,
4680                                 void *arg)
4681 {
4682         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4683         int ret;
4684
4685         MAC_TYPE_FILTER_SUP(hw->mac.type);
4686
4687         if (filter_op == RTE_ETH_FILTER_NOP)
4688                 return 0;
4689
4690         if (arg == NULL) {
4691                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4692                             filter_op);
4693                 return -EINVAL;
4694         }
4695
4696         switch (filter_op) {
4697         case RTE_ETH_FILTER_ADD:
4698                 ret = igb_add_del_ntuple_filter(dev,
4699                         (struct rte_eth_ntuple_filter *)arg,
4700                         TRUE);
4701                 break;
4702         case RTE_ETH_FILTER_DELETE:
4703                 ret = igb_add_del_ntuple_filter(dev,
4704                         (struct rte_eth_ntuple_filter *)arg,
4705                         FALSE);
4706                 break;
4707         case RTE_ETH_FILTER_GET:
4708                 ret = igb_get_ntuple_filter(dev,
4709                         (struct rte_eth_ntuple_filter *)arg);
4710                 break;
4711         default:
4712                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4713                 ret = -EINVAL;
4714                 break;
4715         }
4716         return ret;
4717 }
4718
4719 static inline int
4720 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4721                         uint16_t ethertype)
4722 {
4723         int i;
4724
4725         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4726                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4727                     (filter_info->ethertype_mask & (1 << i)))
4728                         return i;
4729         }
4730         return -1;
4731 }
4732
4733 static inline int
4734 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4735                         uint16_t ethertype, uint32_t etqf)
4736 {
4737         int i;
4738
4739         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4740                 if (!(filter_info->ethertype_mask & (1 << i))) {
4741                         filter_info->ethertype_mask |= 1 << i;
4742                         filter_info->ethertype_filters[i].ethertype = ethertype;
4743                         filter_info->ethertype_filters[i].etqf = etqf;
4744                         return i;
4745                 }
4746         }
4747         return -1;
4748 }
4749
4750 int
4751 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4752                         uint8_t idx)
4753 {
4754         if (idx >= E1000_MAX_ETQF_FILTERS)
4755                 return -1;
4756         filter_info->ethertype_mask &= ~(1 << idx);
4757         filter_info->ethertype_filters[idx].ethertype = 0;
4758         filter_info->ethertype_filters[idx].etqf = 0;
4759         return idx;
4760 }
4761
4762
4763 int
4764 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4765                         struct rte_eth_ethertype_filter *filter,
4766                         bool add)
4767 {
4768         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4769         struct e1000_filter_info *filter_info =
4770                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4771         uint32_t etqf = 0;
4772         int ret;
4773
4774         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4775                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4776                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4777                         " ethertype filter.", filter->ether_type);
4778                 return -EINVAL;
4779         }
4780
4781         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4782                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4783                 return -EINVAL;
4784         }
4785         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4786                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4787                 return -EINVAL;
4788         }
4789
4790         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4791         if (ret >= 0 && add) {
4792                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4793                             filter->ether_type);
4794                 return -EEXIST;
4795         }
4796         if (ret < 0 && !add) {
4797                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4798                             filter->ether_type);
4799                 return -ENOENT;
4800         }
4801
4802         if (add) {
4803                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4804                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4805                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4806                 ret = igb_ethertype_filter_insert(filter_info,
4807                                 filter->ether_type, etqf);
4808                 if (ret < 0) {
4809                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4810                         return -ENOSYS;
4811                 }
4812         } else {
4813                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4814                 if (ret < 0)
4815                         return -ENOSYS;
4816         }
4817         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4818         E1000_WRITE_FLUSH(hw);
4819
4820         return 0;
4821 }
4822
4823 static int
4824 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4825                         struct rte_eth_ethertype_filter *filter)
4826 {
4827         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4828         struct e1000_filter_info *filter_info =
4829                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4830         uint32_t etqf;
4831         int ret;
4832
4833         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4834         if (ret < 0) {
4835                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4836                             filter->ether_type);
4837                 return -ENOENT;
4838         }
4839
4840         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4841         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4842                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4843                 filter->flags = 0;
4844                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4845                                 E1000_ETQF_QUEUE_SHIFT;
4846                 return 0;
4847         }
4848
4849         return -ENOENT;
4850 }
4851
4852 /*
4853  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4854  * @dev: pointer to rte_eth_dev structure
4855  * @filter_op:operation will be taken.
4856  * @arg: a pointer to specific structure corresponding to the filter_op
4857  */
4858 static int
4859 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4860                                 enum rte_filter_op filter_op,
4861                                 void *arg)
4862 {
4863         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4864         int ret;
4865
4866         MAC_TYPE_FILTER_SUP(hw->mac.type);
4867
4868         if (filter_op == RTE_ETH_FILTER_NOP)
4869                 return 0;
4870
4871         if (arg == NULL) {
4872                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4873                             filter_op);
4874                 return -EINVAL;
4875         }
4876
4877         switch (filter_op) {
4878         case RTE_ETH_FILTER_ADD:
4879                 ret = igb_add_del_ethertype_filter(dev,
4880                         (struct rte_eth_ethertype_filter *)arg,
4881                         TRUE);
4882                 break;
4883         case RTE_ETH_FILTER_DELETE:
4884                 ret = igb_add_del_ethertype_filter(dev,
4885                         (struct rte_eth_ethertype_filter *)arg,
4886                         FALSE);
4887                 break;
4888         case RTE_ETH_FILTER_GET:
4889                 ret = igb_get_ethertype_filter(dev,
4890                         (struct rte_eth_ethertype_filter *)arg);
4891                 break;
4892         default:
4893                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4894                 ret = -EINVAL;
4895                 break;
4896         }
4897         return ret;
4898 }
4899
4900 static int
4901 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4902                      enum rte_filter_type filter_type,
4903                      enum rte_filter_op filter_op,
4904                      void *arg)
4905 {
4906         int ret = 0;
4907
4908         switch (filter_type) {
4909         case RTE_ETH_FILTER_NTUPLE:
4910                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4911                 break;
4912         case RTE_ETH_FILTER_ETHERTYPE:
4913                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4914                 break;
4915         case RTE_ETH_FILTER_SYN:
4916                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4917                 break;
4918         case RTE_ETH_FILTER_FLEXIBLE:
4919                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4920                 break;
4921         case RTE_ETH_FILTER_GENERIC:
4922                 if (filter_op != RTE_ETH_FILTER_GET)
4923                         return -EINVAL;
4924                 *(const void **)arg = &igb_flow_ops;
4925                 break;
4926         default:
4927                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4928                                                         filter_type);
4929                 break;
4930         }
4931
4932         return ret;
4933 }
4934
4935 static int
4936 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4937                          struct rte_ether_addr *mc_addr_set,
4938                          uint32_t nb_mc_addr)
4939 {
4940         struct e1000_hw *hw;
4941
4942         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4943         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4944         return 0;
4945 }
4946
4947 static uint64_t
4948 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4949 {
4950         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4951         uint64_t systime_cycles;
4952
4953         switch (hw->mac.type) {
4954         case e1000_i210:
4955         case e1000_i211:
4956                 /*
4957                  * Need to read System Time Residue Register to be able
4958                  * to read the other two registers.
4959                  */
4960                 E1000_READ_REG(hw, E1000_SYSTIMR);
4961                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4962                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4963                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4964                                 * NSEC_PER_SEC;
4965                 break;
4966         case e1000_82580:
4967         case e1000_i350:
4968         case e1000_i354:
4969                 /*
4970                  * Need to read System Time Residue Register to be able
4971                  * to read the other two registers.
4972                  */
4973                 E1000_READ_REG(hw, E1000_SYSTIMR);
4974                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4975                 /* Only the 8 LSB are valid. */
4976                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4977                                 & 0xff) << 32;
4978                 break;
4979         default:
4980                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4981                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4982                                 << 32;
4983                 break;
4984         }
4985
4986         return systime_cycles;
4987 }
4988
4989 static uint64_t
4990 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4991 {
4992         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4993         uint64_t rx_tstamp_cycles;
4994
4995         switch (hw->mac.type) {
4996         case e1000_i210:
4997         case e1000_i211:
4998                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4999                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5000                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5001                                 * NSEC_PER_SEC;
5002                 break;
5003         case e1000_82580:
5004         case e1000_i350:
5005         case e1000_i354:
5006                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5007                 /* Only the 8 LSB are valid. */
5008                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
5009                                 & 0xff) << 32;
5010                 break;
5011         default:
5012                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5013                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5014                                 << 32;
5015                 break;
5016         }
5017
5018         return rx_tstamp_cycles;
5019 }
5020
5021 static uint64_t
5022 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5023 {
5024         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5025         uint64_t tx_tstamp_cycles;
5026
5027         switch (hw->mac.type) {
5028         case e1000_i210:
5029         case e1000_i211:
5030                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5031                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5032                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5033                                 * NSEC_PER_SEC;
5034                 break;
5035         case e1000_82580:
5036         case e1000_i350:
5037         case e1000_i354:
5038                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5039                 /* Only the 8 LSB are valid. */
5040                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5041                                 & 0xff) << 32;
5042                 break;
5043         default:
5044                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5045                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5046                                 << 32;
5047                 break;
5048         }
5049
5050         return tx_tstamp_cycles;
5051 }
5052
5053 static void
5054 igb_start_timecounters(struct rte_eth_dev *dev)
5055 {
5056         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5057         struct e1000_adapter *adapter = dev->data->dev_private;
5058         uint32_t incval = 1;
5059         uint32_t shift = 0;
5060         uint64_t mask = E1000_CYCLECOUNTER_MASK;
5061
5062         switch (hw->mac.type) {
5063         case e1000_82580:
5064         case e1000_i350:
5065         case e1000_i354:
5066                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5067                 mask = (1ULL << 40) - 1;
5068                 /* fall-through */
5069         case e1000_i210:
5070         case e1000_i211:
5071                 /*
5072                  * Start incrementing the register
5073                  * used to timestamp PTP packets.
5074                  */
5075                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5076                 break;
5077         case e1000_82576:
5078                 incval = E1000_INCVALUE_82576;
5079                 shift = IGB_82576_TSYNC_SHIFT;
5080                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5081                                 E1000_INCPERIOD_82576 | incval);
5082                 break;
5083         default:
5084                 /* Not supported */
5085                 return;
5086         }
5087
5088         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5089         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5090         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5091
5092         adapter->systime_tc.cc_mask = mask;
5093         adapter->systime_tc.cc_shift = shift;
5094         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5095
5096         adapter->rx_tstamp_tc.cc_mask = mask;
5097         adapter->rx_tstamp_tc.cc_shift = shift;
5098         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5099
5100         adapter->tx_tstamp_tc.cc_mask = mask;
5101         adapter->tx_tstamp_tc.cc_shift = shift;
5102         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5103 }
5104
5105 static int
5106 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5107 {
5108         struct e1000_adapter *adapter = dev->data->dev_private;
5109
5110         adapter->systime_tc.nsec += delta;
5111         adapter->rx_tstamp_tc.nsec += delta;
5112         adapter->tx_tstamp_tc.nsec += delta;
5113
5114         return 0;
5115 }
5116
5117 static int
5118 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5119 {
5120         uint64_t ns;
5121         struct e1000_adapter *adapter = dev->data->dev_private;
5122
5123         ns = rte_timespec_to_ns(ts);
5124
5125         /* Set the timecounters to a new value. */
5126         adapter->systime_tc.nsec = ns;
5127         adapter->rx_tstamp_tc.nsec = ns;
5128         adapter->tx_tstamp_tc.nsec = ns;
5129
5130         return 0;
5131 }
5132
5133 static int
5134 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5135 {
5136         uint64_t ns, systime_cycles;
5137         struct e1000_adapter *adapter = dev->data->dev_private;
5138
5139         systime_cycles = igb_read_systime_cyclecounter(dev);
5140         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5141         *ts = rte_ns_to_timespec(ns);
5142
5143         return 0;
5144 }
5145
5146 static int
5147 igb_timesync_enable(struct rte_eth_dev *dev)
5148 {
5149         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5150         uint32_t tsync_ctl;
5151         uint32_t tsauxc;
5152
5153         /* Stop the timesync system time. */
5154         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5155         /* Reset the timesync system time value. */
5156         switch (hw->mac.type) {
5157         case e1000_82580:
5158         case e1000_i350:
5159         case e1000_i354:
5160         case e1000_i210:
5161         case e1000_i211:
5162                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5163                 /* fall-through */
5164         case e1000_82576:
5165                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5166                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5167                 break;
5168         default:
5169                 /* Not supported. */
5170                 return -ENOTSUP;
5171         }
5172
5173         /* Enable system time for it isn't on by default. */
5174         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5175         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5176         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5177
5178         igb_start_timecounters(dev);
5179
5180         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5181         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5182                         (RTE_ETHER_TYPE_1588 |
5183                          E1000_ETQF_FILTER_ENABLE |
5184                          E1000_ETQF_1588));
5185
5186         /* Enable timestamping of received PTP packets. */
5187         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5188         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5189         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5190
5191         /* Enable Timestamping of transmitted PTP packets. */
5192         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5193         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5194         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5195
5196         return 0;
5197 }
5198
5199 static int
5200 igb_timesync_disable(struct rte_eth_dev *dev)
5201 {
5202         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5203         uint32_t tsync_ctl;
5204
5205         /* Disable timestamping of transmitted PTP packets. */
5206         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5207         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5208         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5209
5210         /* Disable timestamping of received PTP packets. */
5211         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5212         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5213         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5214
5215         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5216         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5217
5218         /* Stop incrementating the System Time registers. */
5219         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5220
5221         return 0;
5222 }
5223
5224 static int
5225 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5226                                struct timespec *timestamp,
5227                                uint32_t flags __rte_unused)
5228 {
5229         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5230         struct e1000_adapter *adapter = dev->data->dev_private;
5231         uint32_t tsync_rxctl;
5232         uint64_t rx_tstamp_cycles;
5233         uint64_t ns;
5234
5235         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5236         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5237                 return -EINVAL;
5238
5239         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5240         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5241         *timestamp = rte_ns_to_timespec(ns);
5242
5243         return  0;
5244 }
5245
5246 static int
5247 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5248                                struct timespec *timestamp)
5249 {
5250         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5251         struct e1000_adapter *adapter = dev->data->dev_private;
5252         uint32_t tsync_txctl;
5253         uint64_t tx_tstamp_cycles;
5254         uint64_t ns;
5255
5256         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5257         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5258                 return -EINVAL;
5259
5260         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5261         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5262         *timestamp = rte_ns_to_timespec(ns);
5263
5264         return  0;
5265 }
5266
5267 static int
5268 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5269 {
5270         int count = 0;
5271         int g_ind = 0;
5272         const struct reg_info *reg_group;
5273
5274         while ((reg_group = igb_regs[g_ind++]))
5275                 count += igb_reg_group_count(reg_group);
5276
5277         return count;
5278 }
5279
5280 static int
5281 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5282 {
5283         int count = 0;
5284         int g_ind = 0;
5285         const struct reg_info *reg_group;
5286
5287         while ((reg_group = igbvf_regs[g_ind++]))
5288                 count += igb_reg_group_count(reg_group);
5289
5290         return count;
5291 }
5292
5293 static int
5294 eth_igb_get_regs(struct rte_eth_dev *dev,
5295         struct rte_dev_reg_info *regs)
5296 {
5297         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5298         uint32_t *data = regs->data;
5299         int g_ind = 0;
5300         int count = 0;
5301         const struct reg_info *reg_group;
5302
5303         if (data == NULL) {
5304                 regs->length = eth_igb_get_reg_length(dev);
5305                 regs->width = sizeof(uint32_t);
5306                 return 0;
5307         }
5308
5309         /* Support only full register dump */
5310         if ((regs->length == 0) ||
5311             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5312                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5313                         hw->device_id;
5314                 while ((reg_group = igb_regs[g_ind++]))
5315                         count += igb_read_regs_group(dev, &data[count],
5316                                                         reg_group);
5317                 return 0;
5318         }
5319
5320         return -ENOTSUP;
5321 }
5322
5323 static int
5324 igbvf_get_regs(struct rte_eth_dev *dev,
5325         struct rte_dev_reg_info *regs)
5326 {
5327         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5328         uint32_t *data = regs->data;
5329         int g_ind = 0;
5330         int count = 0;
5331         const struct reg_info *reg_group;
5332
5333         if (data == NULL) {
5334                 regs->length = igbvf_get_reg_length(dev);
5335                 regs->width = sizeof(uint32_t);
5336                 return 0;
5337         }
5338
5339         /* Support only full register dump */
5340         if ((regs->length == 0) ||
5341             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5342                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5343                         hw->device_id;
5344                 while ((reg_group = igbvf_regs[g_ind++]))
5345                         count += igb_read_regs_group(dev, &data[count],
5346                                                         reg_group);
5347                 return 0;
5348         }
5349
5350         return -ENOTSUP;
5351 }
5352
5353 static int
5354 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5355 {
5356         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5357
5358         /* Return unit is byte count */
5359         return hw->nvm.word_size * 2;
5360 }
5361
5362 static int
5363 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5364         struct rte_dev_eeprom_info *in_eeprom)
5365 {
5366         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5367         struct e1000_nvm_info *nvm = &hw->nvm;
5368         uint16_t *data = in_eeprom->data;
5369         int first, length;
5370
5371         first = in_eeprom->offset >> 1;
5372         length = in_eeprom->length >> 1;
5373         if ((first >= hw->nvm.word_size) ||
5374             ((first + length) >= hw->nvm.word_size))
5375                 return -EINVAL;
5376
5377         in_eeprom->magic = hw->vendor_id |
5378                 ((uint32_t)hw->device_id << 16);
5379
5380         if ((nvm->ops.read) == NULL)
5381                 return -ENOTSUP;
5382
5383         return nvm->ops.read(hw, first, length, data);
5384 }
5385
5386 static int
5387 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5388         struct rte_dev_eeprom_info *in_eeprom)
5389 {
5390         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5391         struct e1000_nvm_info *nvm = &hw->nvm;
5392         uint16_t *data = in_eeprom->data;
5393         int first, length;
5394
5395         first = in_eeprom->offset >> 1;
5396         length = in_eeprom->length >> 1;
5397         if ((first >= hw->nvm.word_size) ||
5398             ((first + length) >= hw->nvm.word_size))
5399                 return -EINVAL;
5400
5401         in_eeprom->magic = (uint32_t)hw->vendor_id |
5402                 ((uint32_t)hw->device_id << 16);
5403
5404         if ((nvm->ops.write) == NULL)
5405                 return -ENOTSUP;
5406         return nvm->ops.write(hw,  first, length, data);
5407 }
5408
5409 static int
5410 eth_igb_get_module_info(struct rte_eth_dev *dev,
5411                         struct rte_eth_dev_module_info *modinfo)
5412 {
5413         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5414
5415         uint32_t status = 0;
5416         uint16_t sff8472_rev, addr_mode;
5417         bool page_swap = false;
5418
5419         if (hw->phy.media_type == e1000_media_type_copper ||
5420             hw->phy.media_type == e1000_media_type_unknown)
5421                 return -EOPNOTSUPP;
5422
5423         /* Check whether we support SFF-8472 or not */
5424         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5425         if (status)
5426                 return -EIO;
5427
5428         /* addressing mode is not supported */
5429         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5430         if (status)
5431                 return -EIO;
5432
5433         /* addressing mode is not supported */
5434         if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5435                 PMD_DRV_LOG(ERR,
5436                             "Address change required to access page 0xA2, "
5437                             "but not supported. Please report the module "
5438                             "type to the driver maintainers.\n");
5439                 page_swap = true;
5440         }
5441
5442         if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5443                 /* We have an SFP, but it does not support SFF-8472 */
5444                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5445                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5446         } else {
5447                 /* We have an SFP which supports a revision of SFF-8472 */
5448                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5449                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5450         }
5451
5452         return 0;
5453 }
5454
5455 static int
5456 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5457                           struct rte_dev_eeprom_info *info)
5458 {
5459         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5460
5461         uint32_t status = 0;
5462         uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5463         u16 first_word, last_word;
5464         int i = 0;
5465
5466         if (info->length == 0)
5467                 return -EINVAL;
5468
5469         first_word = info->offset >> 1;
5470         last_word = (info->offset + info->length - 1) >> 1;
5471
5472         /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5473         for (i = 0; i < last_word - first_word + 1; i++) {
5474                 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5475                                                 &dataword[i]);
5476                 if (status) {
5477                         /* Error occurred while reading module */
5478                         return -EIO;
5479                 }
5480
5481                 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5482         }
5483
5484         memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5485
5486         return 0;
5487 }
5488
5489 static int
5490 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5491 {
5492         struct e1000_hw *hw =
5493                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5494         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5495         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5496         uint32_t vec = E1000_MISC_VEC_ID;
5497
5498         if (rte_intr_allow_others(intr_handle))
5499                 vec = E1000_RX_VEC_START;
5500
5501         uint32_t mask = 1 << (queue_id + vec);
5502
5503         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5504         E1000_WRITE_FLUSH(hw);
5505
5506         return 0;
5507 }
5508
5509 static int
5510 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5511 {
5512         struct e1000_hw *hw =
5513                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5514         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5515         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5516         uint32_t vec = E1000_MISC_VEC_ID;
5517
5518         if (rte_intr_allow_others(intr_handle))
5519                 vec = E1000_RX_VEC_START;
5520
5521         uint32_t mask = 1 << (queue_id + vec);
5522         uint32_t regval;
5523
5524         regval = E1000_READ_REG(hw, E1000_EIMS);
5525         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5526         E1000_WRITE_FLUSH(hw);
5527
5528         rte_intr_ack(intr_handle);
5529
5530         return 0;
5531 }
5532
5533 static void
5534 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5535                    uint8_t index, uint8_t offset)
5536 {
5537         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5538
5539         /* clear bits */
5540         val &= ~((uint32_t)0xFF << offset);
5541
5542         /* write vector and valid bit */
5543         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5544
5545         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5546 }
5547
5548 static void
5549 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5550                            uint8_t queue, uint8_t msix_vector)
5551 {
5552         uint32_t tmp = 0;
5553
5554         if (hw->mac.type == e1000_82575) {
5555                 if (direction == 0)
5556                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5557                 else if (direction == 1)
5558                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5559                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5560         } else if (hw->mac.type == e1000_82576) {
5561                 if ((direction == 0) || (direction == 1))
5562                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5563                                            ((queue & 0x8) << 1) +
5564                                            8 * direction);
5565         } else if ((hw->mac.type == e1000_82580) ||
5566                         (hw->mac.type == e1000_i350) ||
5567                         (hw->mac.type == e1000_i354) ||
5568                         (hw->mac.type == e1000_i210) ||
5569                         (hw->mac.type == e1000_i211)) {
5570                 if ((direction == 0) || (direction == 1))
5571                         eth_igb_write_ivar(hw, msix_vector,
5572                                            queue >> 1,
5573                                            ((queue & 0x1) << 4) +
5574                                            8 * direction);
5575         }
5576 }
5577
5578 /* Sets up the hardware to generate MSI-X interrupts properly
5579  * @hw
5580  *  board private structure
5581  */
5582 static void
5583 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5584 {
5585         int queue_id;
5586         uint32_t tmpval, regval, intr_mask;
5587         struct e1000_hw *hw =
5588                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5589         uint32_t vec = E1000_MISC_VEC_ID;
5590         uint32_t base = E1000_MISC_VEC_ID;
5591         uint32_t misc_shift = 0;
5592         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5593         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5594
5595         /* won't configure msix register if no mapping is done
5596          * between intr vector and event fd
5597          */
5598         if (!rte_intr_dp_is_en(intr_handle))
5599                 return;
5600
5601         if (rte_intr_allow_others(intr_handle)) {
5602                 vec = base = E1000_RX_VEC_START;
5603                 misc_shift = 1;
5604         }
5605
5606         /* set interrupt vector for other causes */
5607         if (hw->mac.type == e1000_82575) {
5608                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5609                 /* enable MSI-X PBA support */
5610                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5611
5612                 /* Auto-Mask interrupts upon ICR read */
5613                 tmpval |= E1000_CTRL_EXT_EIAME;
5614                 tmpval |= E1000_CTRL_EXT_IRCA;
5615
5616                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5617
5618                 /* enable msix_other interrupt */
5619                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5620                 regval = E1000_READ_REG(hw, E1000_EIAC);
5621                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5622                 regval = E1000_READ_REG(hw, E1000_EIAM);
5623                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5624         } else if ((hw->mac.type == e1000_82576) ||
5625                         (hw->mac.type == e1000_82580) ||
5626                         (hw->mac.type == e1000_i350) ||
5627                         (hw->mac.type == e1000_i354) ||
5628                         (hw->mac.type == e1000_i210) ||
5629                         (hw->mac.type == e1000_i211)) {
5630                 /* turn on MSI-X capability first */
5631                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5632                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5633                                         E1000_GPIE_NSICR);
5634                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5635                         misc_shift;
5636
5637                 if (dev->data->dev_conf.intr_conf.lsc != 0)
5638                         intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5639
5640                 regval = E1000_READ_REG(hw, E1000_EIAC);
5641                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5642
5643                 /* enable msix_other interrupt */
5644                 regval = E1000_READ_REG(hw, E1000_EIMS);
5645                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5646                 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5647                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5648         }
5649
5650         /* use EIAM to auto-mask when MSI-X interrupt
5651          * is asserted, this saves a register write for every interrupt
5652          */
5653         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5654                 misc_shift;
5655
5656         if (dev->data->dev_conf.intr_conf.lsc != 0)
5657                 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5658
5659         regval = E1000_READ_REG(hw, E1000_EIAM);
5660         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5661
5662         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5663                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5664                 intr_handle->intr_vec[queue_id] = vec;
5665                 if (vec < base + intr_handle->nb_efd - 1)
5666                         vec++;
5667         }
5668
5669         E1000_WRITE_FLUSH(hw);
5670 }
5671
5672 /* restore n-tuple filter */
5673 static inline void
5674 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5675 {
5676         struct e1000_filter_info *filter_info =
5677                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5678         struct e1000_5tuple_filter *p_5tuple;
5679         struct e1000_2tuple_filter *p_2tuple;
5680
5681         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5682                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5683         }
5684
5685         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5686                 igb_inject_2uple_filter(dev, p_2tuple);
5687         }
5688 }
5689
5690 /* restore SYN filter */
5691 static inline void
5692 igb_syn_filter_restore(struct rte_eth_dev *dev)
5693 {
5694         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5695         struct e1000_filter_info *filter_info =
5696                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5697         uint32_t synqf;
5698
5699         synqf = filter_info->syn_info;
5700
5701         if (synqf & E1000_SYN_FILTER_ENABLE) {
5702                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5703                 E1000_WRITE_FLUSH(hw);
5704         }
5705 }
5706
5707 /* restore ethernet type filter */
5708 static inline void
5709 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5710 {
5711         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5712         struct e1000_filter_info *filter_info =
5713                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5714         int i;
5715
5716         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5717                 if (filter_info->ethertype_mask & (1 << i)) {
5718                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5719                                 filter_info->ethertype_filters[i].etqf);
5720                         E1000_WRITE_FLUSH(hw);
5721                 }
5722         }
5723 }
5724
5725 /* restore flex byte filter */
5726 static inline void
5727 igb_flex_filter_restore(struct rte_eth_dev *dev)
5728 {
5729         struct e1000_filter_info *filter_info =
5730                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5731         struct e1000_flex_filter *flex_filter;
5732
5733         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5734                 igb_inject_flex_filter(dev, flex_filter);
5735         }
5736 }
5737
5738 /* restore rss filter */
5739 static inline void
5740 igb_rss_filter_restore(struct rte_eth_dev *dev)
5741 {
5742         struct e1000_filter_info *filter_info =
5743                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5744
5745         if (filter_info->rss_info.conf.queue_num)
5746                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5747 }
5748
5749 /* restore all types filter */
5750 static int
5751 igb_filter_restore(struct rte_eth_dev *dev)
5752 {
5753         igb_ntuple_filter_restore(dev);
5754         igb_ethertype_filter_restore(dev);
5755         igb_syn_filter_restore(dev);
5756         igb_flex_filter_restore(dev);
5757         igb_rss_filter_restore(dev);
5758
5759         return 0;
5760 }
5761
5762 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5763 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5764 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5765 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5766 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5767 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5768
5769 /* see e1000_logs.c */
5770 RTE_INIT(e1000_init_log)
5771 {
5772         e1000_igb_init_log();
5773 }