drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 /*
  60  * Default values for port configuration
  61  */
  62 #define IGB_DEFAULT_RX_FREE_THRESH  32
  63 #define IGB_DEFAULT_RX_PTHRESH      8
  64 #define IGB_DEFAULT_RX_HTHRESH      8
  65 #define IGB_DEFAULT_RX_WTHRESH      0
  66
  67 #define IGB_DEFAULT_TX_PTHRESH      32
  68 #define IGB_DEFAULT_TX_HTHRESH      0
  69 #define IGB_DEFAULT_TX_WTHRESH      0
  70
  71 /* Bit shift and mask */
  72 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  73 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  74 #define IGB_8_BIT_WIDTH  CHAR_BIT
  75 #define IGB_8_BIT_MASK   UINT8_MAX
  76
  77 static int  eth_igb_configure(struct rte_eth_dev *dev);
  78 static int  eth_igb_start(struct rte_eth_dev *dev);
  79 static void eth_igb_stop(struct rte_eth_dev *dev);
  80 static void eth_igb_close(struct rte_eth_dev *dev);
  81 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  82 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  83 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  84 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  85 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  86                                 int wait_to_complete);
  87 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  88                                 struct rte_eth_stats *rte_stats);
  89 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  90 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  91                               struct rte_eth_dev_info *dev_info);
  92 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
  93                                 struct rte_eth_dev_info *dev_info);
  94 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
  95                                 struct rte_eth_fc_conf *fc_conf);
  96 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  97                                 struct rte_eth_fc_conf *fc_conf);
  98 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
  99 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 100 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 101 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 102                                                         void *param);
 103 static int  igb_hardware_init(struct e1000_hw *hw);
 104 static void igb_hw_control_acquire(struct e1000_hw *hw);
 105 static void igb_hw_control_release(struct e1000_hw *hw);
 106 static void igb_init_manageability(struct e1000_hw *hw);
 107 static void igb_release_manageability(struct e1000_hw *hw);
 108
 109 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 110
 111 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 112                 uint16_t vlan_id, int on);
 113 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 114 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 115
 116 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 117 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 118 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 119 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 120 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 121 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 122
 123 static int eth_igb_led_on(struct rte_eth_dev *dev);
 124 static int eth_igb_led_off(struct rte_eth_dev *dev);
 125
 126 static void igb_intr_disable(struct e1000_hw *hw);
 127 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 128 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 129                 struct ether_addr *mac_addr,
 130                 uint32_t index, uint32_t pool);
 131 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 132
 133 static void igbvf_intr_disable(struct e1000_hw *hw);
 134 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 135 static int igbvf_dev_start(struct rte_eth_dev *dev);
 136 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 137 static void igbvf_dev_close(struct rte_eth_dev *dev);
 138 static int eth_igbvf_link_update(struct e1000_hw *hw);
 139 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 140 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 141 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 142                 uint16_t vlan_id, int on);
 143 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 144 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 145 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 146                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 147                                    uint16_t reta_size);
 148 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 149                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 150                                   uint16_t reta_size);
 151
 152 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 153                         struct rte_eth_syn_filter *filter,
 154                         bool add);
 155 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 156                         struct rte_eth_syn_filter *filter);
 157 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 158                         enum rte_filter_op filter_op,
 159                         void *arg);
 160 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 161                         struct rte_eth_ntuple_filter *ntuple_filter);
 162 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 163                         struct rte_eth_ntuple_filter *ntuple_filter);
 164 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 165                         struct rte_eth_flex_filter *filter,
 166                         bool add);
 167 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 168                         struct rte_eth_flex_filter *filter);
 169 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 170                         enum rte_filter_op filter_op,
 171                         void *arg);
 172 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 173                         struct rte_eth_ntuple_filter *ntuple_filter);
 174 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 175                         struct rte_eth_ntuple_filter *ntuple_filter);
 176 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 177                         struct rte_eth_ntuple_filter *filter,
 178                         bool add);
 179 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 180                         struct rte_eth_ntuple_filter *filter);
 181 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 182                                 enum rte_filter_op filter_op,
 183                                 void *arg);
 184 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 185                         struct rte_eth_ethertype_filter *filter,
 186                         bool add);
 187 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 188                                 enum rte_filter_op filter_op,
 189                                 void *arg);
 190 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 191                         struct rte_eth_ethertype_filter *filter);
 192 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 193                      enum rte_filter_type filter_type,
 194                      enum rte_filter_op filter_op,
 195                      void *arg);
 196
 197 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 198                                     struct ether_addr *mc_addr_set,
 199                                     uint32_t nb_mc_addr);
 200
 201 /*
 202  * Define VF Stats MACRO for Non "cleared on read" register
 203  */
 204 #define UPDATE_VF_STAT(reg, last, cur)            \
 205 {                                                 \
 206         u32 latest = E1000_READ_REG(hw, reg);     \
 207         cur += latest - last;                     \
 208         last = latest;                            \
 209 }
 210
 211
 212 #define IGB_FC_PAUSE_TIME 0x0680
 213 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 214 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 215
 216 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 217
 218 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 219
 220 /*
 221  * The set of PCI devices this driver supports
 222  */
 223 static const struct rte_pci_id pci_id_igb_map[] = {
 224
 225 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 226 #include "rte_pci_dev_ids.h"
 227
 228 {0},
 229 };
 230
 231 /*
 232  * The set of PCI devices this driver supports (for 82576&I350 VF)
 233  */
 234 static const struct rte_pci_id pci_id_igbvf_map[] = {
 235
 236 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 237 #include "rte_pci_dev_ids.h"
 238
 239 {0},
 240 };
 241
 242 static const struct eth_dev_ops eth_igb_ops = {
 243         .dev_configure        = eth_igb_configure,
 244         .dev_start            = eth_igb_start,
 245         .dev_stop             = eth_igb_stop,
 246         .dev_close            = eth_igb_close,
 247         .promiscuous_enable   = eth_igb_promiscuous_enable,
 248         .promiscuous_disable  = eth_igb_promiscuous_disable,
 249         .allmulticast_enable  = eth_igb_allmulticast_enable,
 250         .allmulticast_disable = eth_igb_allmulticast_disable,
 251         .link_update          = eth_igb_link_update,
 252         .stats_get            = eth_igb_stats_get,
 253         .stats_reset          = eth_igb_stats_reset,
 254         .dev_infos_get        = eth_igb_infos_get,
 255         .mtu_set              = eth_igb_mtu_set,
 256         .vlan_filter_set      = eth_igb_vlan_filter_set,
 257         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 258         .vlan_offload_set     = eth_igb_vlan_offload_set,
 259         .rx_queue_setup       = eth_igb_rx_queue_setup,
 260         .rx_queue_release     = eth_igb_rx_queue_release,
 261         .rx_queue_count       = eth_igb_rx_queue_count,
 262         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 263         .tx_queue_setup       = eth_igb_tx_queue_setup,
 264         .tx_queue_release     = eth_igb_tx_queue_release,
 265         .dev_led_on           = eth_igb_led_on,
 266         .dev_led_off          = eth_igb_led_off,
 267         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 268         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 269         .mac_addr_add         = eth_igb_rar_set,
 270         .mac_addr_remove      = eth_igb_rar_clear,
 271         .reta_update          = eth_igb_rss_reta_update,
 272         .reta_query           = eth_igb_rss_reta_query,
 273         .rss_hash_update      = eth_igb_rss_hash_update,
 274         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 275         .filter_ctrl          = eth_igb_filter_ctrl,
 276         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 277 };
 278
 279 /*
 280  * dev_ops for virtual function, bare necessities for basic vf
 281  * operation have been implemented
 282  */
 283 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 284         .dev_configure        = igbvf_dev_configure,
 285         .dev_start            = igbvf_dev_start,
 286         .dev_stop             = igbvf_dev_stop,
 287         .dev_close            = igbvf_dev_close,
 288         .link_update          = eth_igb_link_update,
 289         .stats_get            = eth_igbvf_stats_get,
 290         .stats_reset          = eth_igbvf_stats_reset,
 291         .vlan_filter_set      = igbvf_vlan_filter_set,
 292         .dev_infos_get        = eth_igbvf_infos_get,
 293         .rx_queue_setup       = eth_igb_rx_queue_setup,
 294         .rx_queue_release     = eth_igb_rx_queue_release,
 295         .tx_queue_setup       = eth_igb_tx_queue_setup,
 296         .tx_queue_release     = eth_igb_tx_queue_release,
 297         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 298 };
 299
 300 /**
 301  * Atomically reads the link status information from global
 302  * structure rte_eth_dev.
 303  *
 304  * @param dev
 305  *   - Pointer to the structure rte_eth_dev to read from.
 306  *   - Pointer to the buffer to be saved with the link status.
 307  *
 308  * @return
 309  *   - On success, zero.
 310  *   - On failure, negative value.
 311  */
 312 static inline int
 313 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 314                                 struct rte_eth_link *link)
 315 {
 316         struct rte_eth_link *dst = link;
 317         struct rte_eth_link *src = &(dev->data->dev_link);
 318
 319         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 320                                         *(uint64_t *)src) == 0)
 321                 return -1;
 322
 323         return 0;
 324 }
 325
 326 /**
 327  * Atomically writes the link status information into global
 328  * structure rte_eth_dev.
 329  *
 330  * @param dev
 331  *   - Pointer to the structure rte_eth_dev to read from.
 332  *   - Pointer to the buffer to be saved with the link status.
 333  *
 334  * @return
 335  *   - On success, zero.
 336  *   - On failure, negative value.
 337  */
 338 static inline int
 339 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 340                                 struct rte_eth_link *link)
 341 {
 342         struct rte_eth_link *dst = &(dev->data->dev_link);
 343         struct rte_eth_link *src = link;
 344
 345         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 346                                         *(uint64_t *)src) == 0)
 347                 return -1;
 348
 349         return 0;
 350 }
 351
 352 static inline void
 353 igb_intr_enable(struct rte_eth_dev *dev)
 354 {
 355         struct e1000_interrupt *intr =
 356                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 357         struct e1000_hw *hw =
 358                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 359
 360         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 361         E1000_WRITE_FLUSH(hw);
 362 }
 363
 364 static void
 365 igb_intr_disable(struct e1000_hw *hw)
 366 {
 367         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 368         E1000_WRITE_FLUSH(hw);
 369 }
 370
 371 static inline int32_t
 372 igb_pf_reset_hw(struct e1000_hw *hw)
 373 {
 374         uint32_t ctrl_ext;
 375         int32_t status;
 376
 377         status = e1000_reset_hw(hw);
 378
 379         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 380         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 381         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 382         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 383         E1000_WRITE_FLUSH(hw);
 384
 385         return status;
 386 }
 387
 388 static void
 389 igb_identify_hardware(struct rte_eth_dev *dev)
 390 {
 391         struct e1000_hw *hw =
 392                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 393
 394         hw->vendor_id = dev->pci_dev->id.vendor_id;
 395         hw->device_id = dev->pci_dev->id.device_id;
 396         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 397         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 398
 399         e1000_set_mac_type(hw);
 400
 401         /* need to check if it is a vf device below */
 402 }
 403
 404 static int
 405 igb_reset_swfw_lock(struct e1000_hw *hw)
 406 {
 407         int ret_val;
 408
 409         /*
 410          * Do mac ops initialization manually here, since we will need
 411          * some function pointers set by this call.
 412          */
 413         ret_val = e1000_init_mac_params(hw);
 414         if (ret_val)
 415                 return ret_val;
 416
 417         /*
 418          * SMBI lock should not fail in this early stage. If this is the case,
 419          * it is due to an improper exit of the application.
 420          * So force the release of the faulty lock.
 421          */
 422         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 423                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 424         }
 425         e1000_put_hw_semaphore_generic(hw);
 426
 427         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 428                 uint16_t mask;
 429
 430                 /*
 431                  * Phy lock should not fail in this early stage. If this is the case,
 432                  * it is due to an improper exit of the application.
 433                  * So force the release of the faulty lock.
 434                  */
 435                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 436                 if (hw->bus.func > E1000_FUNC_1)
 437                         mask <<= 2;
 438                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 439                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 440                                     hw->bus.func);
 441                 }
 442                 hw->mac.ops.release_swfw_sync(hw, mask);
 443
 444                 /*
 445                  * This one is more tricky since it is common to all ports; but
 446                  * swfw_sync retries last long enough (1s) to be almost sure that if
 447                  * lock can not be taken it is due to an improper lock of the
 448                  * semaphore.
 449                  */
 450                 mask = E1000_SWFW_EEP_SM;
 451                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 452                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 453                 }
 454                 hw->mac.ops.release_swfw_sync(hw, mask);
 455         }
 456
 457         return E1000_SUCCESS;
 458 }
 459
 460 static int
 461 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 462 {
 463         int error = 0;
 464         struct rte_pci_device *pci_dev;
 465         struct e1000_hw *hw =
 466                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 467         struct e1000_vfta * shadow_vfta =
 468                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 469         struct e1000_filter_info *filter_info =
 470                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 471         uint32_t ctrl_ext;
 472
 473         pci_dev = eth_dev->pci_dev;
 474         eth_dev->dev_ops = &eth_igb_ops;
 475         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 476         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 477
 478         /* for secondary processes, we don't initialise any further as primary
 479          * has already done this work. Only check we don't need a different
 480          * RX function */
 481         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 482                 if (eth_dev->data->scattered_rx)
 483                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 484                 return 0;
 485         }
 486
 487         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 488
 489         igb_identify_hardware(eth_dev);
 490         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 491                 error = -EIO;
 492                 goto err_late;
 493         }
 494
 495         e1000_get_bus_info(hw);
 496
 497         /* Reset any pending lock */
 498         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 499                 error = -EIO;
 500                 goto err_late;
 501         }
 502
 503         /* Finish initialization */
 504         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 505                 error = -EIO;
 506                 goto err_late;
 507         }
 508
 509         hw->mac.autoneg = 1;
 510         hw->phy.autoneg_wait_to_complete = 0;
 511         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 512
 513         /* Copper options */
 514         if (hw->phy.media_type == e1000_media_type_copper) {
 515                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 516                 hw->phy.disable_polarity_correction = 0;
 517                 hw->phy.ms_type = e1000_ms_hw_default;
 518         }
 519
 520         /*
 521          * Start from a known state, this is important in reading the nvm
 522          * and mac from that.
 523          */
 524         igb_pf_reset_hw(hw);
 525
 526         /* Make sure we have a good EEPROM before we read from it */
 527         if (e1000_validate_nvm_checksum(hw) < 0) {
 528                 /*
 529                  * Some PCI-E parts fail the first check due to
 530                  * the link being in sleep state, call it again,
 531                  * if it fails a second time its a real issue.
 532                  */
 533                 if (e1000_validate_nvm_checksum(hw) < 0) {
 534                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 535                         error = -EIO;
 536                         goto err_late;
 537                 }
 538         }
 539
 540         /* Read the permanent MAC address out of the EEPROM */
 541         if (e1000_read_mac_addr(hw) != 0) {
 542                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 543                 error = -EIO;
 544                 goto err_late;
 545         }
 546
 547         /* Allocate memory for storing MAC addresses */
 548         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 549                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 550         if (eth_dev->data->mac_addrs == NULL) {
 551                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 552                                                 "store MAC addresses",
 553                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 554                 error = -ENOMEM;
 555                 goto err_late;
 556         }
 557
 558         /* Copy the permanent MAC address */
 559         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 560
 561         /* initialize the vfta */
 562         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 563
 564         /* Now initialize the hardware */
 565         if (igb_hardware_init(hw) != 0) {
 566                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 567                 rte_free(eth_dev->data->mac_addrs);
 568                 eth_dev->data->mac_addrs = NULL;
 569                 error = -ENODEV;
 570                 goto err_late;
 571         }
 572         hw->mac.get_link_status = 1;
 573
 574         /* Indicate SOL/IDER usage */
 575         if (e1000_check_reset_block(hw) < 0) {
 576                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 577                                         "SOL/IDER session");
 578         }
 579
 580         /* initialize PF if max_vfs not zero */
 581         igb_pf_host_init(eth_dev);
 582
 583         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 584         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 585         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 586         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 587         E1000_WRITE_FLUSH(hw);
 588
 589         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
 590                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 591                      pci_dev->id.device_id);
 592
 593         rte_intr_callback_register(&(pci_dev->intr_handle),
 594                 eth_igb_interrupt_handler, (void *)eth_dev);
 595
 596         /* enable uio intr after callback register */
 597         rte_intr_enable(&(pci_dev->intr_handle));
 598
 599         /* enable support intr */
 600         igb_intr_enable(eth_dev);
 601
 602         TAILQ_INIT(&filter_info->flex_list);
 603         filter_info->flex_mask = 0;
 604         TAILQ_INIT(&filter_info->twotuple_list);
 605         filter_info->twotuple_mask = 0;
 606         TAILQ_INIT(&filter_info->fivetuple_list);
 607         filter_info->fivetuple_mask = 0;
 608
 609         return 0;
 610
 611 err_late:
 612         igb_hw_control_release(hw);
 613
 614         return (error);
 615 }
 616
 617 /*
 618  * Virtual Function device init
 619  */
 620 static int
 621 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 622 {
 623         struct rte_pci_device *pci_dev;
 624         struct e1000_hw *hw =
 625                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 626         int diag;
 627
 628         PMD_INIT_FUNC_TRACE();
 629
 630         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 631         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 632         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 633
 634         /* for secondary processes, we don't initialise any further as primary
 635          * has already done this work. Only check we don't need a different
 636          * RX function */
 637         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 638                 if (eth_dev->data->scattered_rx)
 639                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 640                 return 0;
 641         }
 642
 643         pci_dev = eth_dev->pci_dev;
 644
 645         hw->device_id = pci_dev->id.device_id;
 646         hw->vendor_id = pci_dev->id.vendor_id;
 647         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 648
 649         /* Initialize the shared code (base driver) */
 650         diag = e1000_setup_init_funcs(hw, TRUE);
 651         if (diag != 0) {
 652                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 653                         diag);
 654                 return -EIO;
 655         }
 656
 657         /* init_mailbox_params */
 658         hw->mbx.ops.init_params(hw);
 659
 660         /* Disable the interrupts for VF */
 661         igbvf_intr_disable(hw);
 662
 663         diag = hw->mac.ops.reset_hw(hw);
 664
 665         /* Allocate memory for storing MAC addresses */
 666         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 667                 hw->mac.rar_entry_count, 0);
 668         if (eth_dev->data->mac_addrs == NULL) {
 669                 PMD_INIT_LOG(ERR,
 670                         "Failed to allocate %d bytes needed to store MAC "
 671                         "addresses",
 672                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 673                 return -ENOMEM;
 674         }
 675
 676         /* Copy the permanent MAC address */
 677         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 678                         &eth_dev->data->mac_addrs[0]);
 679
 680         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 681                      "mac.type=%s",
 682                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 683                      pci_dev->id.device_id, "igb_mac_82576_vf");
 684
 685         return 0;
 686 }
 687
 688 static struct eth_driver rte_igb_pmd = {
 689         .pci_drv = {
 690                 .name = "rte_igb_pmd",
 691                 .id_table = pci_id_igb_map,
 692                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 693         },
 694         .eth_dev_init = eth_igb_dev_init,
 695         .dev_private_size = sizeof(struct e1000_adapter),
 696 };
 697
 698 /*
 699  * virtual function driver struct
 700  */
 701 static struct eth_driver rte_igbvf_pmd = {
 702         .pci_drv = {
 703                 .name = "rte_igbvf_pmd",
 704                 .id_table = pci_id_igbvf_map,
 705                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 706         },
 707         .eth_dev_init = eth_igbvf_dev_init,
 708         .dev_private_size = sizeof(struct e1000_adapter),
 709 };
 710
 711 static int
 712 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 713 {
 714         rte_eth_driver_register(&rte_igb_pmd);
 715         return 0;
 716 }
 717
 718 static void
 719 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 720 {
 721         struct e1000_hw *hw =
 722                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 723         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 724         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 725         rctl |= E1000_RCTL_VFE;
 726         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 727 }
 728
 729 /*
 730  * VF Driver initialization routine.
 731  * Invoked one at EAL init time.
 732  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 733  */
 734 static int
 735 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 736 {
 737         PMD_INIT_FUNC_TRACE();
 738
 739         rte_eth_driver_register(&rte_igbvf_pmd);
 740         return (0);
 741 }
 742
 743 static int
 744 eth_igb_configure(struct rte_eth_dev *dev)
 745 {
 746         struct e1000_interrupt *intr =
 747                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 748
 749         PMD_INIT_FUNC_TRACE();
 750         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 751         PMD_INIT_FUNC_TRACE();
 752
 753         return (0);
 754 }
 755
 756 static int
 757 eth_igb_start(struct rte_eth_dev *dev)
 758 {
 759         struct e1000_hw *hw =
 760                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 761         int ret, i, mask;
 762         uint32_t ctrl_ext;
 763
 764         PMD_INIT_FUNC_TRACE();
 765
 766         /* Power up the phy. Needed to make the link go Up */
 767         e1000_power_up_phy(hw);
 768
 769         /*
 770          * Packet Buffer Allocation (PBA)
 771          * Writing PBA sets the receive portion of the buffer
 772          * the remainder is used for the transmit buffer.
 773          */
 774         if (hw->mac.type == e1000_82575) {
 775                 uint32_t pba;
 776
 777                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 778                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 779         }
 780
 781         /* Put the address into the Receive Address Array */
 782         e1000_rar_set(hw, hw->mac.addr, 0);
 783
 784         /* Initialize the hardware */
 785         if (igb_hardware_init(hw)) {
 786                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 787                 return (-EIO);
 788         }
 789
 790         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 791
 792         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 793         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 794         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 795         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 796         E1000_WRITE_FLUSH(hw);
 797
 798         /* configure PF module if SRIOV enabled */
 799         igb_pf_host_configure(dev);
 800
 801         /* Configure for OS presence */
 802         igb_init_manageability(hw);
 803
 804         eth_igb_tx_init(dev);
 805
 806         /* This can fail when allocating mbufs for descriptor rings */
 807         ret = eth_igb_rx_init(dev);
 808         if (ret) {
 809                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 810                 igb_dev_clear_queues(dev);
 811                 return ret;
 812         }
 813
 814         e1000_clear_hw_cntrs_base_generic(hw);
 815
 816         /*
 817          * VLAN Offload Settings
 818          */
 819         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 820                         ETH_VLAN_EXTEND_MASK;
 821         eth_igb_vlan_offload_set(dev, mask);
 822
 823         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 824                 /* Enable VLAN filter since VMDq always use VLAN filter */
 825                 igb_vmdq_vlan_hw_filter_enable(dev);
 826         }
 827
 828         /*
 829          * Configure the Interrupt Moderation register (EITR) with the maximum
 830          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 831          * spurious [DMA] memory updates of RX and TX ring descriptors.
 832          *
 833          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 834          * spurious memory updates per second should be expected.
 835          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 836          *
 837          * Because interrupts are not used at all, the MSI-X is not activated
 838          * and interrupt moderation is controlled by EITR[0].
 839          *
 840          * Note that having [almost] disabled memory updates of RX and TX ring
 841          * descriptors through the Interrupt Moderation mechanism, memory
 842          * updates of ring descriptors are now moderated by the configurable
 843          * value of Write-Back Threshold registers.
 844          */
 845         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 846                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
 847                 (hw->mac.type == e1000_i211)) {
 848                 uint32_t ivar;
 849
 850                 /* Enable all RX & TX queues in the IVAR registers */
 851                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 852                 for (i = 0; i < 8; i++)
 853                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 854
 855                 /* Configure EITR with the maximum possible value (0xFFFF) */
 856                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 857         }
 858
 859         /* Setup link speed and duplex */
 860         switch (dev->data->dev_conf.link_speed) {
 861         case ETH_LINK_SPEED_AUTONEG:
 862                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 863                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 864                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 865                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 866                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 867                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 868                 else
 869                         goto error_invalid_config;
 870                 break;
 871         case ETH_LINK_SPEED_10:
 872                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 873                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 874                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 875                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 876                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 877                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 878                 else
 879                         goto error_invalid_config;
 880                 break;
 881         case ETH_LINK_SPEED_100:
 882                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 883                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 884                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 885                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 886                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 887                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 888                 else
 889                         goto error_invalid_config;
 890                 break;
 891         case ETH_LINK_SPEED_1000:
 892                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 893                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 894                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 895                 else
 896                         goto error_invalid_config;
 897                 break;
 898         case ETH_LINK_SPEED_10000:
 899         default:
 900                 goto error_invalid_config;
 901         }
 902         e1000_setup_link(hw);
 903
 904         /* check if lsc interrupt feature is enabled */
 905         if (dev->data->dev_conf.intr_conf.lsc != 0)
 906                 ret = eth_igb_lsc_interrupt_setup(dev);
 907
 908         /* resume enabled intr since hw reset */
 909         igb_intr_enable(dev);
 910
 911         PMD_INIT_LOG(DEBUG, "<<");
 912
 913         return (0);
 914
 915 error_invalid_config:
 916         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
 917                      dev->data->dev_conf.link_speed,
 918                      dev->data->dev_conf.link_duplex, dev->data->port_id);
 919         igb_dev_clear_queues(dev);
 920         return (-EINVAL);
 921 }
 922
 923 /*********************************************************************
 924  *
 925  *  This routine disables all traffic on the adapter by issuing a
 926  *  global reset on the MAC.
 927  *
 928  **********************************************************************/
 929 static void
 930 eth_igb_stop(struct rte_eth_dev *dev)
 931 {
 932         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 933         struct e1000_filter_info *filter_info =
 934                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
 935         struct rte_eth_link link;
 936         struct e1000_flex_filter *p_flex;
 937         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
 938         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
 939
 940         igb_intr_disable(hw);
 941         igb_pf_reset_hw(hw);
 942         E1000_WRITE_REG(hw, E1000_WUC, 0);
 943
 944         /* Set bit for Go Link disconnect */
 945         if (hw->mac.type >= e1000_82580) {
 946                 uint32_t phpm_reg;
 947
 948                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 949                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 950                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 951         }
 952
 953         /* Power down the phy. Needed to make the link go Down */
 954         if (hw->phy.media_type == e1000_media_type_copper)
 955                 e1000_power_down_phy(hw);
 956         else
 957                 e1000_shutdown_fiber_serdes_link(hw);
 958
 959         igb_dev_clear_queues(dev);
 960
 961         /* clear the recorded link status */
 962         memset(&link, 0, sizeof(link));
 963         rte_igb_dev_atomic_write_link_status(dev, &link);
 964
 965         /* Remove all flex filters of the device */
 966         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 967                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 968                 rte_free(p_flex);
 969         }
 970         filter_info->flex_mask = 0;
 971
 972         /* Remove all ntuple filters of the device */
 973         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
 974              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
 975                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
 976                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 977                              p_5tuple, entries);
 978                 rte_free(p_5tuple);
 979         }
 980         filter_info->fivetuple_mask = 0;
 981         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
 982              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
 983                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
 984                 TAILQ_REMOVE(&filter_info->twotuple_list,
 985                              p_2tuple, entries);
 986                 rte_free(p_2tuple);
 987         }
 988         filter_info->twotuple_mask = 0;
 989 }
 990
 991 static void
 992 eth_igb_close(struct rte_eth_dev *dev)
 993 {
 994         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 995         struct rte_eth_link link;
 996
 997         eth_igb_stop(dev);
 998         e1000_phy_hw_reset(hw);
 999         igb_release_manageability(hw);
1000         igb_hw_control_release(hw);
1001
1002         /* Clear bit for Go Link disconnect */
1003         if (hw->mac.type >= e1000_82580) {
1004                 uint32_t phpm_reg;
1005
1006                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1007                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1008                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1009         }
1010
1011         igb_dev_clear_queues(dev);
1012
1013         memset(&link, 0, sizeof(link));
1014         rte_igb_dev_atomic_write_link_status(dev, &link);
1015 }
1016
1017 static int
1018 igb_get_rx_buffer_size(struct e1000_hw *hw)
1019 {
1020         uint32_t rx_buf_size;
1021         if (hw->mac.type == e1000_82576) {
1022                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1023         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1024                 /* PBS needs to be translated according to a lookup table */
1025                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1026                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1027                 rx_buf_size = (rx_buf_size << 10);
1028         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1029                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1030         } else {
1031                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1032         }
1033
1034         return rx_buf_size;
1035 }
1036
1037 /*********************************************************************
1038  *
1039  *  Initialize the hardware
1040  *
1041  **********************************************************************/
1042 static int
1043 igb_hardware_init(struct e1000_hw *hw)
1044 {
1045         uint32_t rx_buf_size;
1046         int diag;
1047
1048         /* Let the firmware know the OS is in control */
1049         igb_hw_control_acquire(hw);
1050
1051         /*
1052          * These parameters control the automatic generation (Tx) and
1053          * response (Rx) to Ethernet PAUSE frames.
1054          * - High water mark should allow for at least two standard size (1518)
1055          *   frames to be received after sending an XOFF.
1056          * - Low water mark works best when it is very near the high water mark.
1057          *   This allows the receiver to restart by sending XON when it has
1058          *   drained a bit. Here we use an arbitrary value of 1500 which will
1059          *   restart after one full frame is pulled from the buffer. There
1060          *   could be several smaller frames in the buffer and if so they will
1061          *   not trigger the XON until their total number reduces the buffer
1062          *   by 1500.
1063          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1064          */
1065         rx_buf_size = igb_get_rx_buffer_size(hw);
1066
1067         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1068         hw->fc.low_water = hw->fc.high_water - 1500;
1069         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1070         hw->fc.send_xon = 1;
1071
1072         /* Set Flow control, use the tunable location if sane */
1073         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1074                 hw->fc.requested_mode = igb_fc_setting;
1075         else
1076                 hw->fc.requested_mode = e1000_fc_none;
1077
1078         /* Issue a global reset */
1079         igb_pf_reset_hw(hw);
1080         E1000_WRITE_REG(hw, E1000_WUC, 0);
1081
1082         diag = e1000_init_hw(hw);
1083         if (diag < 0)
1084                 return (diag);
1085
1086         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1087         e1000_get_phy_info(hw);
1088         e1000_check_for_link(hw);
1089
1090         return (0);
1091 }
1092
1093 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1094 static void
1095 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1096 {
1097         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1098         struct e1000_hw_stats *stats =
1099                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1100         int pause_frames;
1101
1102         if(hw->phy.media_type == e1000_media_type_copper ||
1103             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1104                 stats->symerrs +=
1105                     E1000_READ_REG(hw,E1000_SYMERRS);
1106                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1107         }
1108
1109         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1110         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1111         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1112         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1113
1114         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1115         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1116         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1117         stats->dc += E1000_READ_REG(hw, E1000_DC);
1118         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1119         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1120         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1121         /*
1122         ** For watchdog management we need to know if we have been
1123         ** paused during the last interval, so capture that here.
1124         */
1125         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1126         stats->xoffrxc += pause_frames;
1127         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1128         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1129         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1130         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1131         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1132         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1133         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1134         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1135         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1136         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1137         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1138         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1139
1140         /* For the 64-bit byte counters the low dword must be read first. */
1141         /* Both registers clear on the read of the high dword */
1142
1143         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1144         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1145         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1146         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1147
1148         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1149         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1150         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1151         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1152         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1153
1154         stats->tor += E1000_READ_REG(hw, E1000_TORH);
1155         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1156
1157         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1158         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1159         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1160         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1161         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1162         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1163         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1164         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1165         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1166         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1167
1168         /* Interrupt Counts */
1169
1170         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1171         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1172         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1173         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1174         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1175         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1176         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1177         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1178         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1179
1180         /* Host to Card Statistics */
1181
1182         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1183         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1184         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1185         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1186         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1187         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1188         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1189         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1190         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1191         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1192         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1193         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1194         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1195         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1196
1197         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1198         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1199         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1200         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1201         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1202         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1203
1204         if (rte_stats == NULL)
1205                 return;
1206
1207         /* Rx Errors */
1208         rte_stats->ibadcrc = stats->crcerrs;
1209         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1210         rte_stats->imissed = stats->mpc;
1211         rte_stats->ierrors = rte_stats->ibadcrc +
1212                              rte_stats->ibadlen +
1213                              rte_stats->imissed +
1214                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1215
1216         /* Tx Errors */
1217         rte_stats->oerrors = stats->ecol + stats->latecol;
1218
1219         /* XON/XOFF pause frames */
1220         rte_stats->tx_pause_xon  = stats->xontxc;
1221         rte_stats->rx_pause_xon  = stats->xonrxc;
1222         rte_stats->tx_pause_xoff = stats->xofftxc;
1223         rte_stats->rx_pause_xoff = stats->xoffrxc;
1224
1225         rte_stats->ipackets = stats->gprc;
1226         rte_stats->opackets = stats->gptc;
1227         rte_stats->ibytes   = stats->gorc;
1228         rte_stats->obytes   = stats->gotc;
1229 }
1230
1231 static void
1232 eth_igb_stats_reset(struct rte_eth_dev *dev)
1233 {
1234         struct e1000_hw_stats *hw_stats =
1235                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1236
1237         /* HW registers are cleared on read */
1238         eth_igb_stats_get(dev, NULL);
1239
1240         /* Reset software totals */
1241         memset(hw_stats, 0, sizeof(*hw_stats));
1242 }
1243
1244 static void
1245 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1246 {
1247         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1248         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1249                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1250
1251         /* Good Rx packets, include VF loopback */
1252         UPDATE_VF_STAT(E1000_VFGPRC,
1253             hw_stats->last_gprc, hw_stats->gprc);
1254
1255         /* Good Rx octets, include VF loopback */
1256         UPDATE_VF_STAT(E1000_VFGORC,
1257             hw_stats->last_gorc, hw_stats->gorc);
1258
1259         /* Good Tx packets, include VF loopback */
1260         UPDATE_VF_STAT(E1000_VFGPTC,
1261             hw_stats->last_gptc, hw_stats->gptc);
1262
1263         /* Good Tx octets, include VF loopback */
1264         UPDATE_VF_STAT(E1000_VFGOTC,
1265             hw_stats->last_gotc, hw_stats->gotc);
1266
1267         /* Rx Multicst packets */
1268         UPDATE_VF_STAT(E1000_VFMPRC,
1269             hw_stats->last_mprc, hw_stats->mprc);
1270
1271         /* Good Rx loopback packets */
1272         UPDATE_VF_STAT(E1000_VFGPRLBC,
1273             hw_stats->last_gprlbc, hw_stats->gprlbc);
1274
1275         /* Good Rx loopback octets */
1276         UPDATE_VF_STAT(E1000_VFGORLBC,
1277             hw_stats->last_gorlbc, hw_stats->gorlbc);
1278
1279         /* Good Tx loopback packets */
1280         UPDATE_VF_STAT(E1000_VFGPTLBC,
1281             hw_stats->last_gptlbc, hw_stats->gptlbc);
1282
1283         /* Good Tx loopback octets */
1284         UPDATE_VF_STAT(E1000_VFGOTLBC,
1285             hw_stats->last_gotlbc, hw_stats->gotlbc);
1286
1287         if (rte_stats == NULL)
1288                 return;
1289
1290         rte_stats->ipackets = hw_stats->gprc;
1291         rte_stats->ibytes = hw_stats->gorc;
1292         rte_stats->opackets = hw_stats->gptc;
1293         rte_stats->obytes = hw_stats->gotc;
1294         rte_stats->imcasts = hw_stats->mprc;
1295         rte_stats->ilbpackets = hw_stats->gprlbc;
1296         rte_stats->ilbbytes = hw_stats->gorlbc;
1297         rte_stats->olbpackets = hw_stats->gptlbc;
1298         rte_stats->olbbytes = hw_stats->gotlbc;
1299
1300 }
1301
1302 static void
1303 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1304 {
1305         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1306                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1307
1308         /* Sync HW register to the last stats */
1309         eth_igbvf_stats_get(dev, NULL);
1310
1311         /* reset HW current stats*/
1312         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1313                offsetof(struct e1000_vf_stats, gprc));
1314
1315 }
1316
1317 static void
1318 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1319 {
1320         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1321
1322         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1323         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1324         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1325         dev_info->rx_offload_capa =
1326                 DEV_RX_OFFLOAD_VLAN_STRIP |
1327                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1328                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1329                 DEV_RX_OFFLOAD_TCP_CKSUM;
1330         dev_info->tx_offload_capa =
1331                 DEV_TX_OFFLOAD_VLAN_INSERT |
1332                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1333                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1334                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1335                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1336
1337         switch (hw->mac.type) {
1338         case e1000_82575:
1339                 dev_info->max_rx_queues = 4;
1340                 dev_info->max_tx_queues = 4;
1341                 dev_info->max_vmdq_pools = 0;
1342                 break;
1343
1344         case e1000_82576:
1345                 dev_info->max_rx_queues = 16;
1346                 dev_info->max_tx_queues = 16;
1347                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1348                 dev_info->vmdq_queue_num = 16;
1349                 break;
1350
1351         case e1000_82580:
1352                 dev_info->max_rx_queues = 8;
1353                 dev_info->max_tx_queues = 8;
1354                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1355                 dev_info->vmdq_queue_num = 8;
1356                 break;
1357
1358         case e1000_i350:
1359                 dev_info->max_rx_queues = 8;
1360                 dev_info->max_tx_queues = 8;
1361                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1362                 dev_info->vmdq_queue_num = 8;
1363                 break;
1364
1365         case e1000_i354:
1366                 dev_info->max_rx_queues = 8;
1367                 dev_info->max_tx_queues = 8;
1368                 break;
1369
1370         case e1000_i210:
1371                 dev_info->max_rx_queues = 4;
1372                 dev_info->max_tx_queues = 4;
1373                 dev_info->max_vmdq_pools = 0;
1374                 break;
1375
1376         case e1000_i211:
1377                 dev_info->max_rx_queues = 2;
1378                 dev_info->max_tx_queues = 2;
1379                 dev_info->max_vmdq_pools = 0;
1380                 break;
1381
1382         default:
1383                 /* Should not happen */
1384                 break;
1385         }
1386         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1387         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1388
1389         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1390                 .rx_thresh = {
1391                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1392                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1393                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1394                 },
1395                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1396                 .rx_drop_en = 0,
1397         };
1398
1399         dev_info->default_txconf = (struct rte_eth_txconf) {
1400                 .tx_thresh = {
1401                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1402                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1403                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1404                 },
1405                 .txq_flags = 0,
1406         };
1407 }
1408
1409 static void
1410 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1411 {
1412         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1413
1414         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1415         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1416         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1417         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1418                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1419                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1420                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1421         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1422                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1423                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1424                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1425                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1426         switch (hw->mac.type) {
1427         case e1000_vfadapt:
1428                 dev_info->max_rx_queues = 2;
1429                 dev_info->max_tx_queues = 2;
1430                 break;
1431         case e1000_vfadapt_i350:
1432                 dev_info->max_rx_queues = 1;
1433                 dev_info->max_tx_queues = 1;
1434                 break;
1435         default:
1436                 /* Should not happen */
1437                 break;
1438         }
1439
1440         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1441                 .rx_thresh = {
1442                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1443                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1444                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1445                 },
1446                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1447                 .rx_drop_en = 0,
1448         };
1449
1450         dev_info->default_txconf = (struct rte_eth_txconf) {
1451                 .tx_thresh = {
1452                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1453                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1454                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1455                 },
1456                 .txq_flags = 0,
1457         };
1458 }
1459
1460 /* return 0 means link status changed, -1 means not changed */
1461 static int
1462 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1463 {
1464         struct e1000_hw *hw =
1465                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1466         struct rte_eth_link link, old;
1467         int link_check, count;
1468
1469         link_check = 0;
1470         hw->mac.get_link_status = 1;
1471
1472         /* possible wait-to-complete in up to 9 seconds */
1473         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1474                 /* Read the real link status */
1475                 switch (hw->phy.media_type) {
1476                 case e1000_media_type_copper:
1477                         /* Do the work to read phy */
1478                         e1000_check_for_link(hw);
1479                         link_check = !hw->mac.get_link_status;
1480                         break;
1481
1482                 case e1000_media_type_fiber:
1483                         e1000_check_for_link(hw);
1484                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1485                                       E1000_STATUS_LU);
1486                         break;
1487
1488                 case e1000_media_type_internal_serdes:
1489                         e1000_check_for_link(hw);
1490                         link_check = hw->mac.serdes_has_link;
1491                         break;
1492
1493                 /* VF device is type_unknown */
1494                 case e1000_media_type_unknown:
1495                         eth_igbvf_link_update(hw);
1496                         link_check = !hw->mac.get_link_status;
1497                         break;
1498
1499                 default:
1500                         break;
1501                 }
1502                 if (link_check || wait_to_complete == 0)
1503                         break;
1504                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1505         }
1506         memset(&link, 0, sizeof(link));
1507         rte_igb_dev_atomic_read_link_status(dev, &link);
1508         old = link;
1509
1510         /* Now we check if a transition has happened */
1511         if (link_check) {
1512                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1513                                           &link.link_duplex);
1514                 link.link_status = 1;
1515         } else if (!link_check) {
1516                 link.link_speed = 0;
1517                 link.link_duplex = 0;
1518                 link.link_status = 0;
1519         }
1520         rte_igb_dev_atomic_write_link_status(dev, &link);
1521
1522         /* not changed */
1523         if (old.link_status == link.link_status)
1524                 return -1;
1525
1526         /* changed */
1527         return 0;
1528 }
1529
1530 /*
1531  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1532  * For ASF and Pass Through versions of f/w this means
1533  * that the driver is loaded.
1534  */
1535 static void
1536 igb_hw_control_acquire(struct e1000_hw *hw)
1537 {
1538         uint32_t ctrl_ext;
1539
1540         /* Let firmware know the driver has taken over */
1541         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1542         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1543 }
1544
1545 /*
1546  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1547  * For ASF and Pass Through versions of f/w this means that the
1548  * driver is no longer loaded.
1549  */
1550 static void
1551 igb_hw_control_release(struct e1000_hw *hw)
1552 {
1553         uint32_t ctrl_ext;
1554
1555         /* Let firmware taken over control of h/w */
1556         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1557         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1558                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1559 }
1560
1561 /*
1562  * Bit of a misnomer, what this really means is
1563  * to enable OS management of the system... aka
1564  * to disable special hardware management features.
1565  */
1566 static void
1567 igb_init_manageability(struct e1000_hw *hw)
1568 {
1569         if (e1000_enable_mng_pass_thru(hw)) {
1570                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1571                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1572
1573                 /* disable hardware interception of ARP */
1574                 manc &= ~(E1000_MANC_ARP_EN);
1575
1576                 /* enable receiving management packets to the host */
1577                 manc |= E1000_MANC_EN_MNG2HOST;
1578                 manc2h |= 1 << 5;  /* Mng Port 623 */
1579                 manc2h |= 1 << 6;  /* Mng Port 664 */
1580                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1581                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1582         }
1583 }
1584
1585 static void
1586 igb_release_manageability(struct e1000_hw *hw)
1587 {
1588         if (e1000_enable_mng_pass_thru(hw)) {
1589                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1590
1591                 manc |= E1000_MANC_ARP_EN;
1592                 manc &= ~E1000_MANC_EN_MNG2HOST;
1593
1594                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1595         }
1596 }
1597
1598 static void
1599 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1600 {
1601         struct e1000_hw *hw =
1602                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1603         uint32_t rctl;
1604
1605         rctl = E1000_READ_REG(hw, E1000_RCTL);
1606         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1607         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1608 }
1609
1610 static void
1611 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1612 {
1613         struct e1000_hw *hw =
1614                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1615         uint32_t rctl;
1616
1617         rctl = E1000_READ_REG(hw, E1000_RCTL);
1618         rctl &= (~E1000_RCTL_UPE);
1619         if (dev->data->all_multicast == 1)
1620                 rctl |= E1000_RCTL_MPE;
1621         else
1622                 rctl &= (~E1000_RCTL_MPE);
1623         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1624 }
1625
1626 static void
1627 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1628 {
1629         struct e1000_hw *hw =
1630                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631         uint32_t rctl;
1632
1633         rctl = E1000_READ_REG(hw, E1000_RCTL);
1634         rctl |= E1000_RCTL_MPE;
1635         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1636 }
1637
1638 static void
1639 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1640 {
1641         struct e1000_hw *hw =
1642                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1643         uint32_t rctl;
1644
1645         if (dev->data->promiscuous == 1)
1646                 return; /* must remain in all_multicast mode */
1647         rctl = E1000_READ_REG(hw, E1000_RCTL);
1648         rctl &= (~E1000_RCTL_MPE);
1649         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1650 }
1651
1652 static int
1653 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1654 {
1655         struct e1000_hw *hw =
1656                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1657         struct e1000_vfta * shadow_vfta =
1658                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1659         uint32_t vfta;
1660         uint32_t vid_idx;
1661         uint32_t vid_bit;
1662
1663         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1664                               E1000_VFTA_ENTRY_MASK);
1665         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1666         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1667         if (on)
1668                 vfta |= vid_bit;
1669         else
1670                 vfta &= ~vid_bit;
1671         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1672
1673         /* update local VFTA copy */
1674         shadow_vfta->vfta[vid_idx] = vfta;
1675
1676         return 0;
1677 }
1678
1679 static void
1680 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1681 {
1682         struct e1000_hw *hw =
1683                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1684         uint32_t reg = ETHER_TYPE_VLAN ;
1685
1686         reg |= (tpid << 16);
1687         E1000_WRITE_REG(hw, E1000_VET, reg);
1688 }
1689
1690 static void
1691 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1692 {
1693         struct e1000_hw *hw =
1694                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1695         uint32_t reg;
1696
1697         /* Filter Table Disable */
1698         reg = E1000_READ_REG(hw, E1000_RCTL);
1699         reg &= ~E1000_RCTL_CFIEN;
1700         reg &= ~E1000_RCTL_VFE;
1701         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1702 }
1703
1704 static void
1705 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1706 {
1707         struct e1000_hw *hw =
1708                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709         struct e1000_vfta * shadow_vfta =
1710                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1711         uint32_t reg;
1712         int i;
1713
1714         /* Filter Table Enable, CFI not used for packet acceptance */
1715         reg = E1000_READ_REG(hw, E1000_RCTL);
1716         reg &= ~E1000_RCTL_CFIEN;
1717         reg |= E1000_RCTL_VFE;
1718         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1719
1720         /* restore VFTA table */
1721         for (i = 0; i < IGB_VFTA_SIZE; i++)
1722                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1723 }
1724
1725 static void
1726 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1727 {
1728         struct e1000_hw *hw =
1729                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1730         uint32_t reg;
1731
1732         /* VLAN Mode Disable */
1733         reg = E1000_READ_REG(hw, E1000_CTRL);
1734         reg &= ~E1000_CTRL_VME;
1735         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1736 }
1737
1738 static void
1739 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1740 {
1741         struct e1000_hw *hw =
1742                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1743         uint32_t reg;
1744
1745         /* VLAN Mode Enable */
1746         reg = E1000_READ_REG(hw, E1000_CTRL);
1747         reg |= E1000_CTRL_VME;
1748         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1749 }
1750
1751 static void
1752 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1753 {
1754         struct e1000_hw *hw =
1755                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1756         uint32_t reg;
1757
1758         /* CTRL_EXT: Extended VLAN */
1759         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1760         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1761         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1762
1763         /* Update maximum packet length */
1764         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1765                 E1000_WRITE_REG(hw, E1000_RLPML,
1766                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1767                                                 VLAN_TAG_SIZE);
1768 }
1769
1770 static void
1771 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1772 {
1773         struct e1000_hw *hw =
1774                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1775         uint32_t reg;
1776
1777         /* CTRL_EXT: Extended VLAN */
1778         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1779         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1780         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1781
1782         /* Update maximum packet length */
1783         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1784                 E1000_WRITE_REG(hw, E1000_RLPML,
1785                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1786                                                 2 * VLAN_TAG_SIZE);
1787 }
1788
1789 static void
1790 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1791 {
1792         if(mask & ETH_VLAN_STRIP_MASK){
1793                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1794                         igb_vlan_hw_strip_enable(dev);
1795                 else
1796                         igb_vlan_hw_strip_disable(dev);
1797         }
1798
1799         if(mask & ETH_VLAN_FILTER_MASK){
1800                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1801                         igb_vlan_hw_filter_enable(dev);
1802                 else
1803                         igb_vlan_hw_filter_disable(dev);
1804         }
1805
1806         if(mask & ETH_VLAN_EXTEND_MASK){
1807                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1808                         igb_vlan_hw_extend_enable(dev);
1809                 else
1810                         igb_vlan_hw_extend_disable(dev);
1811         }
1812 }
1813
1814
1815 /**
1816  * It enables the interrupt mask and then enable the interrupt.
1817  *
1818  * @param dev
1819  *  Pointer to struct rte_eth_dev.
1820  *
1821  * @return
1822  *  - On success, zero.
1823  *  - On failure, a negative value.
1824  */
1825 static int
1826 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1827 {
1828         struct e1000_interrupt *intr =
1829                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1830
1831         intr->mask |= E1000_ICR_LSC;
1832
1833         return 0;
1834 }
1835
1836 /*
1837  * It reads ICR and gets interrupt causes, check it and set a bit flag
1838  * to update link status.
1839  *
1840  * @param dev
1841  *  Pointer to struct rte_eth_dev.
1842  *
1843  * @return
1844  *  - On success, zero.
1845  *  - On failure, a negative value.
1846  */
1847 static int
1848 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1849 {
1850         uint32_t icr;
1851         struct e1000_hw *hw =
1852                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853         struct e1000_interrupt *intr =
1854                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1855
1856         igb_intr_disable(hw);
1857
1858         /* read-on-clear nic registers here */
1859         icr = E1000_READ_REG(hw, E1000_ICR);
1860
1861         intr->flags = 0;
1862         if (icr & E1000_ICR_LSC) {
1863                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1864         }
1865
1866         if (icr & E1000_ICR_VMMB)
1867                 intr->flags |= E1000_FLAG_MAILBOX;
1868
1869         return 0;
1870 }
1871
1872 /*
1873  * It executes link_update after knowing an interrupt is prsent.
1874  *
1875  * @param dev
1876  *  Pointer to struct rte_eth_dev.
1877  *
1878  * @return
1879  *  - On success, zero.
1880  *  - On failure, a negative value.
1881  */
1882 static int
1883 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1884 {
1885         struct e1000_hw *hw =
1886                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1887         struct e1000_interrupt *intr =
1888                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1889         uint32_t tctl, rctl;
1890         struct rte_eth_link link;
1891         int ret;
1892
1893         if (intr->flags & E1000_FLAG_MAILBOX) {
1894                 igb_pf_mbx_process(dev);
1895                 intr->flags &= ~E1000_FLAG_MAILBOX;
1896         }
1897
1898         igb_intr_enable(dev);
1899         rte_intr_enable(&(dev->pci_dev->intr_handle));
1900
1901         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1902                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1903
1904                 /* set get_link_status to check register later */
1905                 hw->mac.get_link_status = 1;
1906                 ret = eth_igb_link_update(dev, 0);
1907
1908                 /* check if link has changed */
1909                 if (ret < 0)
1910                         return 0;
1911
1912                 memset(&link, 0, sizeof(link));
1913                 rte_igb_dev_atomic_read_link_status(dev, &link);
1914                 if (link.link_status) {
1915                         PMD_INIT_LOG(INFO,
1916                                      " Port %d: Link Up - speed %u Mbps - %s",
1917                                      dev->data->port_id,
1918                                      (unsigned)link.link_speed,
1919                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1920                                      "full-duplex" : "half-duplex");
1921                 } else {
1922                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
1923                                      dev->data->port_id);
1924                 }
1925                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1926                              dev->pci_dev->addr.domain,
1927                              dev->pci_dev->addr.bus,
1928                              dev->pci_dev->addr.devid,
1929                              dev->pci_dev->addr.function);
1930                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1931                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1932                 if (link.link_status) {
1933                         /* enable Tx/Rx */
1934                         tctl |= E1000_TCTL_EN;
1935                         rctl |= E1000_RCTL_EN;
1936                 } else {
1937                         /* disable Tx/Rx */
1938                         tctl &= ~E1000_TCTL_EN;
1939                         rctl &= ~E1000_RCTL_EN;
1940                 }
1941                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1942                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1943                 E1000_WRITE_FLUSH(hw);
1944                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1945         }
1946
1947         return 0;
1948 }
1949
1950 /**
1951  * Interrupt handler which shall be registered at first.
1952  *
1953  * @param handle
1954  *  Pointer to interrupt handle.
1955  * @param param
1956  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1957  *
1958  * @return
1959  *  void
1960  */
1961 static void
1962 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1963                                                         void *param)
1964 {
1965         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1966
1967         eth_igb_interrupt_get_status(dev);
1968         eth_igb_interrupt_action(dev);
1969 }
1970
1971 static int
1972 eth_igb_led_on(struct rte_eth_dev *dev)
1973 {
1974         struct e1000_hw *hw;
1975
1976         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1977         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1978 }
1979
1980 static int
1981 eth_igb_led_off(struct rte_eth_dev *dev)
1982 {
1983         struct e1000_hw *hw;
1984
1985         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1986         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1987 }
1988
1989 static int
1990 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1991 {
1992         struct e1000_hw *hw;
1993         uint32_t ctrl;
1994         int tx_pause;
1995         int rx_pause;
1996
1997         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1998         fc_conf->pause_time = hw->fc.pause_time;
1999         fc_conf->high_water = hw->fc.high_water;
2000         fc_conf->low_water = hw->fc.low_water;
2001         fc_conf->send_xon = hw->fc.send_xon;
2002         fc_conf->autoneg = hw->mac.autoneg;
2003
2004         /*
2005          * Return rx_pause and tx_pause status according to actual setting of
2006          * the TFCE and RFCE bits in the CTRL register.
2007          */
2008         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2009         if (ctrl & E1000_CTRL_TFCE)
2010                 tx_pause = 1;
2011         else
2012                 tx_pause = 0;
2013
2014         if (ctrl & E1000_CTRL_RFCE)
2015                 rx_pause = 1;
2016         else
2017                 rx_pause = 0;
2018
2019         if (rx_pause && tx_pause)
2020                 fc_conf->mode = RTE_FC_FULL;
2021         else if (rx_pause)
2022                 fc_conf->mode = RTE_FC_RX_PAUSE;
2023         else if (tx_pause)
2024                 fc_conf->mode = RTE_FC_TX_PAUSE;
2025         else
2026                 fc_conf->mode = RTE_FC_NONE;
2027
2028         return 0;
2029 }
2030
2031 static int
2032 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2033 {
2034         struct e1000_hw *hw;
2035         int err;
2036         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2037                 e1000_fc_none,
2038                 e1000_fc_rx_pause,
2039                 e1000_fc_tx_pause,
2040                 e1000_fc_full
2041         };
2042         uint32_t rx_buf_size;
2043         uint32_t max_high_water;
2044         uint32_t rctl;
2045
2046         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2047         if (fc_conf->autoneg != hw->mac.autoneg)
2048                 return -ENOTSUP;
2049         rx_buf_size = igb_get_rx_buffer_size(hw);
2050         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2051
2052         /* At least reserve one Ethernet frame for watermark */
2053         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2054         if ((fc_conf->high_water > max_high_water) ||
2055             (fc_conf->high_water < fc_conf->low_water)) {
2056                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2057                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2058                 return (-EINVAL);
2059         }
2060
2061         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2062         hw->fc.pause_time     = fc_conf->pause_time;
2063         hw->fc.high_water     = fc_conf->high_water;
2064         hw->fc.low_water      = fc_conf->low_water;
2065         hw->fc.send_xon       = fc_conf->send_xon;
2066
2067         err = e1000_setup_link_generic(hw);
2068         if (err == E1000_SUCCESS) {
2069
2070                 /* check if we want to forward MAC frames - driver doesn't have native
2071                  * capability to do that, so we'll write the registers ourselves */
2072
2073                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2074
2075                 /* set or clear MFLCN.PMCF bit depending on configuration */
2076                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2077                         rctl |= E1000_RCTL_PMCF;
2078                 else
2079                         rctl &= ~E1000_RCTL_PMCF;
2080
2081                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2082                 E1000_WRITE_FLUSH(hw);
2083
2084                 return 0;
2085         }
2086
2087         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2088         return (-EIO);
2089 }
2090
2091 #define E1000_RAH_POOLSEL_SHIFT      (18)
2092 static void
2093 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2094                 uint32_t index, __rte_unused uint32_t pool)
2095 {
2096         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2097         uint32_t rah;
2098
2099         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2100         rah = E1000_READ_REG(hw, E1000_RAH(index));
2101         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2102         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2103 }
2104
2105 static void
2106 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2107 {
2108         uint8_t addr[ETHER_ADDR_LEN];
2109         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2110
2111         memset(addr, 0, sizeof(addr));
2112
2113         e1000_rar_set(hw, addr, index);
2114 }
2115
2116 /*
2117  * Virtual Function operations
2118  */
2119 static void
2120 igbvf_intr_disable(struct e1000_hw *hw)
2121 {
2122         PMD_INIT_FUNC_TRACE();
2123
2124         /* Clear interrupt mask to stop from interrupts being generated */
2125         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2126
2127         E1000_WRITE_FLUSH(hw);
2128 }
2129
2130 static void
2131 igbvf_stop_adapter(struct rte_eth_dev *dev)
2132 {
2133         u32 reg_val;
2134         u16 i;
2135         struct rte_eth_dev_info dev_info;
2136         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2137
2138         memset(&dev_info, 0, sizeof(dev_info));
2139         eth_igbvf_infos_get(dev, &dev_info);
2140
2141         /* Clear interrupt mask to stop from interrupts being generated */
2142         igbvf_intr_disable(hw);
2143
2144         /* Clear any pending interrupts, flush previous writes */
2145         E1000_READ_REG(hw, E1000_EICR);
2146
2147         /* Disable the transmit unit.  Each queue must be disabled. */
2148         for (i = 0; i < dev_info.max_tx_queues; i++)
2149                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2150
2151         /* Disable the receive unit by stopping each queue */
2152         for (i = 0; i < dev_info.max_rx_queues; i++) {
2153                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2154                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2155                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2156                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2157                         ;
2158         }
2159
2160         /* flush all queues disables */
2161         E1000_WRITE_FLUSH(hw);
2162         msec_delay(2);
2163 }
2164
2165 static int eth_igbvf_link_update(struct e1000_hw *hw)
2166 {
2167         struct e1000_mbx_info *mbx = &hw->mbx;
2168         struct e1000_mac_info *mac = &hw->mac;
2169         int ret_val = E1000_SUCCESS;
2170
2171         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2172
2173         /*
2174          * We only want to run this if there has been a rst asserted.
2175          * in this case that could mean a link change, device reset,
2176          * or a virtual function reset
2177          */
2178
2179         /* If we were hit with a reset or timeout drop the link */
2180         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2181                 mac->get_link_status = TRUE;
2182
2183         if (!mac->get_link_status)
2184                 goto out;
2185
2186         /* if link status is down no point in checking to see if pf is up */
2187         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2188                 goto out;
2189
2190         /* if we passed all the tests above then the link is up and we no
2191          * longer need to check for link */
2192         mac->get_link_status = FALSE;
2193
2194 out:
2195         return ret_val;
2196 }
2197
2198
2199 static int
2200 igbvf_dev_configure(struct rte_eth_dev *dev)
2201 {
2202         struct rte_eth_conf* conf = &dev->data->dev_conf;
2203
2204         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2205                      dev->data->port_id);
2206
2207         /*
2208          * VF has no ability to enable/disable HW CRC
2209          * Keep the persistent behavior the same as Host PF
2210          */
2211 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2212         if (!conf->rxmode.hw_strip_crc) {
2213                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2214                 conf->rxmode.hw_strip_crc = 1;
2215         }
2216 #else
2217         if (conf->rxmode.hw_strip_crc) {
2218                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2219                 conf->rxmode.hw_strip_crc = 0;
2220         }
2221 #endif
2222
2223         return 0;
2224 }
2225
2226 static int
2227 igbvf_dev_start(struct rte_eth_dev *dev)
2228 {
2229         struct e1000_hw *hw =
2230                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2231         int ret;
2232
2233         PMD_INIT_FUNC_TRACE();
2234
2235         hw->mac.ops.reset_hw(hw);
2236
2237         /* Set all vfta */
2238         igbvf_set_vfta_all(dev,1);
2239
2240         eth_igbvf_tx_init(dev);
2241
2242         /* This can fail when allocating mbufs for descriptor rings */
2243         ret = eth_igbvf_rx_init(dev);
2244         if (ret) {
2245                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2246                 igb_dev_clear_queues(dev);
2247                 return ret;
2248         }
2249
2250         return 0;
2251 }
2252
2253 static void
2254 igbvf_dev_stop(struct rte_eth_dev *dev)
2255 {
2256         PMD_INIT_FUNC_TRACE();
2257
2258         igbvf_stop_adapter(dev);
2259
2260         /*
2261           * Clear what we set, but we still keep shadow_vfta to
2262           * restore after device starts
2263           */
2264         igbvf_set_vfta_all(dev,0);
2265
2266         igb_dev_clear_queues(dev);
2267 }
2268
2269 static void
2270 igbvf_dev_close(struct rte_eth_dev *dev)
2271 {
2272         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2273
2274         PMD_INIT_FUNC_TRACE();
2275
2276         e1000_reset_hw(hw);
2277
2278         igbvf_dev_stop(dev);
2279 }
2280
2281 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2282 {
2283         struct e1000_mbx_info *mbx = &hw->mbx;
2284         uint32_t msgbuf[2];
2285
2286         /* After set vlan, vlan strip will also be enabled in igb driver*/
2287         msgbuf[0] = E1000_VF_SET_VLAN;
2288         msgbuf[1] = vid;
2289         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2290         if (on)
2291                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2292
2293         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2294 }
2295
2296 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2297 {
2298         struct e1000_hw *hw =
2299                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2300         struct e1000_vfta * shadow_vfta =
2301                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2302         int i = 0, j = 0, vfta = 0, mask = 1;
2303
2304         for (i = 0; i < IGB_VFTA_SIZE; i++){
2305                 vfta = shadow_vfta->vfta[i];
2306                 if(vfta){
2307                         mask = 1;
2308                         for (j = 0; j < 32; j++){
2309                                 if(vfta & mask)
2310                                         igbvf_set_vfta(hw,
2311                                                 (uint16_t)((i<<5)+j), on);
2312                                 mask<<=1;
2313                         }
2314                 }
2315         }
2316
2317 }
2318
2319 static int
2320 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2321 {
2322         struct e1000_hw *hw =
2323                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2324         struct e1000_vfta * shadow_vfta =
2325                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2326         uint32_t vid_idx = 0;
2327         uint32_t vid_bit = 0;
2328         int ret = 0;
2329
2330         PMD_INIT_FUNC_TRACE();
2331
2332         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2333         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2334         if(ret){
2335                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2336                 return ret;
2337         }
2338         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2339         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2340
2341         /*Save what we set and retore it after device reset*/
2342         if (on)
2343                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2344         else
2345                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2346
2347         return 0;
2348 }
2349
2350 static int
2351 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2352                         struct rte_eth_rss_reta_entry64 *reta_conf,
2353                         uint16_t reta_size)
2354 {
2355         uint8_t i, j, mask;
2356         uint32_t reta, r;
2357         uint16_t idx, shift;
2358         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2359
2360         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2361                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2362                         "(%d) doesn't match the number hardware can supported "
2363                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2364                 return -EINVAL;
2365         }
2366
2367         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2368                 idx = i / RTE_RETA_GROUP_SIZE;
2369                 shift = i % RTE_RETA_GROUP_SIZE;
2370                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2371                                                 IGB_4_BIT_MASK);
2372                 if (!mask)
2373                         continue;
2374                 if (mask == IGB_4_BIT_MASK)
2375                         r = 0;
2376                 else
2377                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2378                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2379                         if (mask & (0x1 << j))
2380                                 reta |= reta_conf[idx].reta[shift + j] <<
2381                                                         (CHAR_BIT * j);
2382                         else
2383                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2384                 }
2385                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2386         }
2387
2388         return 0;
2389 }
2390
2391 static int
2392 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2393                        struct rte_eth_rss_reta_entry64 *reta_conf,
2394                        uint16_t reta_size)
2395 {
2396         uint8_t i, j, mask;
2397         uint32_t reta;
2398         uint16_t idx, shift;
2399         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2400
2401         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2402                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2403                         "(%d) doesn't match the number hardware can supported "
2404                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2405                 return -EINVAL;
2406         }
2407
2408         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2409                 idx = i / RTE_RETA_GROUP_SIZE;
2410                 shift = i % RTE_RETA_GROUP_SIZE;
2411                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2412                                                 IGB_4_BIT_MASK);
2413                 if (!mask)
2414                         continue;
2415                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2416                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2417                         if (mask & (0x1 << j))
2418                                 reta_conf[idx].reta[shift + j] =
2419                                         ((reta >> (CHAR_BIT * j)) &
2420                                                 IGB_8_BIT_MASK);
2421                 }
2422         }
2423
2424         return 0;
2425 }
2426
2427 #define MAC_TYPE_FILTER_SUP(type)    do {\
2428         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2429                 (type) != e1000_82576)\
2430                 return -ENOTSUP;\
2431 } while (0)
2432
2433 static int
2434 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2435                         struct rte_eth_syn_filter *filter,
2436                         bool add)
2437 {
2438         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439         uint32_t synqf, rfctl;
2440
2441         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2442                 return -EINVAL;
2443
2444         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2445
2446         if (add) {
2447                 if (synqf & E1000_SYN_FILTER_ENABLE)
2448                         return -EINVAL;
2449
2450                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2451                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2452
2453                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2454                 if (filter->hig_pri)
2455                         rfctl |= E1000_RFCTL_SYNQFP;
2456                 else
2457                         rfctl &= ~E1000_RFCTL_SYNQFP;
2458
2459                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2460         } else {
2461                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
2462                         return -ENOENT;
2463                 synqf = 0;
2464         }
2465
2466         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2467         E1000_WRITE_FLUSH(hw);
2468         return 0;
2469 }
2470
2471 static int
2472 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
2473                         struct rte_eth_syn_filter *filter)
2474 {
2475         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2476         uint32_t synqf, rfctl;
2477
2478         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2479         if (synqf & E1000_SYN_FILTER_ENABLE) {
2480                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2481                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2482                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2483                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2484                 return 0;
2485         }
2486
2487         return -ENOENT;
2488 }
2489
2490 static int
2491 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
2492                         enum rte_filter_op filter_op,
2493                         void *arg)
2494 {
2495         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2496         int ret;
2497
2498         MAC_TYPE_FILTER_SUP(hw->mac.type);
2499
2500         if (filter_op == RTE_ETH_FILTER_NOP)
2501                 return 0;
2502
2503         if (arg == NULL) {
2504                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2505                             filter_op);
2506                 return -EINVAL;
2507         }
2508
2509         switch (filter_op) {
2510         case RTE_ETH_FILTER_ADD:
2511                 ret = eth_igb_syn_filter_set(dev,
2512                                 (struct rte_eth_syn_filter *)arg,
2513                                 TRUE);
2514                 break;
2515         case RTE_ETH_FILTER_DELETE:
2516                 ret = eth_igb_syn_filter_set(dev,
2517                                 (struct rte_eth_syn_filter *)arg,
2518                                 FALSE);
2519                 break;
2520         case RTE_ETH_FILTER_GET:
2521                 ret = eth_igb_syn_filter_get(dev,
2522                                 (struct rte_eth_syn_filter *)arg);
2523                 break;
2524         default:
2525                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
2526                 ret = -EINVAL;
2527                 break;
2528         }
2529
2530         return ret;
2531 }
2532
2533 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
2534         if ((type) != e1000_82580 && (type) != e1000_i350)\
2535                 return -ENOSYS; \
2536 } while (0)
2537
2538 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
2539 static inline int
2540 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
2541                         struct e1000_2tuple_filter_info *filter_info)
2542 {
2543         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2544                 return -EINVAL;
2545         if (filter->priority > E1000_2TUPLE_MAX_PRI)
2546                 return -EINVAL;  /* filter index is out of range. */
2547         if (filter->tcp_flags > TCP_FLAG_ALL)
2548                 return -EINVAL;  /* flags is invalid. */
2549
2550         switch (filter->dst_port_mask) {
2551         case UINT16_MAX:
2552                 filter_info->dst_port_mask = 0;
2553                 filter_info->dst_port = filter->dst_port;
2554                 break;
2555         case 0:
2556                 filter_info->dst_port_mask = 1;
2557                 break;
2558         default:
2559                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2560                 return -EINVAL;
2561         }
2562
2563         switch (filter->proto_mask) {
2564         case UINT8_MAX:
2565                 filter_info->proto_mask = 0;
2566                 filter_info->proto = filter->proto;
2567                 break;
2568         case 0:
2569                 filter_info->proto_mask = 1;
2570                 break;
2571         default:
2572                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2573                 return -EINVAL;
2574         }
2575
2576         filter_info->priority = (uint8_t)filter->priority;
2577         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
2578                 filter_info->tcp_flags = filter->tcp_flags;
2579         else
2580                 filter_info->tcp_flags = 0;
2581
2582         return 0;
2583 }
2584
2585 static inline struct e1000_2tuple_filter *
2586 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
2587                         struct e1000_2tuple_filter_info *key)
2588 {
2589         struct e1000_2tuple_filter *it;
2590
2591         TAILQ_FOREACH(it, filter_list, entries) {
2592                 if (memcmp(key, &it->filter_info,
2593                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
2594                         return it;
2595                 }
2596         }
2597         return NULL;
2598 }
2599
2600 /*
2601  * igb_add_2tuple_filter - add a 2tuple filter
2602  *
2603  * @param
2604  * dev: Pointer to struct rte_eth_dev.
2605  * ntuple_filter: ponter to the filter that will be added.
2606  *
2607  * @return
2608  *    - On success, zero.
2609  *    - On failure, a negative value.
2610  */
2611 static int
2612 igb_add_2tuple_filter(struct rte_eth_dev *dev,
2613                         struct rte_eth_ntuple_filter *ntuple_filter)
2614 {
2615         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616         struct e1000_filter_info *filter_info =
2617                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2618         struct e1000_2tuple_filter *filter;
2619         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
2620         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
2621         int i, ret;
2622
2623         filter = rte_zmalloc("e1000_2tuple_filter",
2624                         sizeof(struct e1000_2tuple_filter), 0);
2625         if (filter == NULL)
2626                 return -ENOMEM;
2627
2628         ret = ntuple_filter_to_2tuple(ntuple_filter,
2629                                       &filter->filter_info);
2630         if (ret < 0) {
2631                 rte_free(filter);
2632                 return ret;
2633         }
2634         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2635                                          &filter->filter_info) != NULL) {
2636                 PMD_DRV_LOG(ERR, "filter exists.");
2637                 rte_free(filter);
2638                 return -EEXIST;
2639         }
2640         filter->queue = ntuple_filter->queue;
2641
2642         /*
2643          * look for an unused 2tuple filter index,
2644          * and insert the filter to list.
2645          */
2646         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
2647                 if (!(filter_info->twotuple_mask & (1 << i))) {
2648                         filter_info->twotuple_mask |= 1 << i;
2649                         filter->index = i;
2650                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
2651                                           filter,
2652                                           entries);
2653                         break;
2654                 }
2655         }
2656         if (i >= E1000_MAX_TTQF_FILTERS) {
2657                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
2658                 rte_free(filter);
2659                 return -ENOSYS;
2660         }
2661
2662         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
2663         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
2664                 imir |= E1000_IMIR_PORT_BP;
2665         else
2666                 imir &= ~E1000_IMIR_PORT_BP;
2667
2668         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
2669
2670         ttqf |= E1000_TTQF_QUEUE_ENABLE;
2671         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
2672         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
2673         if (filter->filter_info.proto_mask == 0)
2674                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2675
2676         /* tcp flags bits setting. */
2677         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
2678                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
2679                         imir_ext |= E1000_IMIREXT_CTRL_URG;
2680                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
2681                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
2682                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
2683                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
2684                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
2685                         imir_ext |= E1000_IMIREXT_CTRL_RST;
2686                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
2687                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
2688                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
2689                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
2690         } else
2691                 imir_ext |= E1000_IMIREXT_CTRL_BP;
2692         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
2693         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
2694         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
2695         return 0;
2696 }
2697
2698 /*
2699  * igb_remove_2tuple_filter - remove a 2tuple filter
2700  *
2701  * @param
2702  * dev: Pointer to struct rte_eth_dev.
2703  * ntuple_filter: ponter to the filter that will be removed.
2704  *
2705  * @return
2706  *    - On success, zero.
2707  *    - On failure, a negative value.
2708  */
2709 static int
2710 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2711                         struct rte_eth_ntuple_filter *ntuple_filter)
2712 {
2713         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2714         struct e1000_filter_info *filter_info =
2715                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2716         struct e1000_2tuple_filter_info filter_2tuple;
2717         struct e1000_2tuple_filter *filter;
2718         int ret;
2719
2720         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
2721         ret = ntuple_filter_to_2tuple(ntuple_filter,
2722                                       &filter_2tuple);
2723         if (ret < 0)
2724                 return ret;
2725
2726         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2727                                          &filter_2tuple);
2728         if (filter == NULL) {
2729                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2730                 return -ENOENT;
2731         }
2732
2733         filter_info->twotuple_mask &= ~(1 << filter->index);
2734         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
2735         rte_free(filter);
2736
2737         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
2738         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
2739         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
2740         return 0;
2741 }
2742
2743 static inline struct e1000_flex_filter *
2744 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
2745                         struct e1000_flex_filter_info *key)
2746 {
2747         struct e1000_flex_filter *it;
2748
2749         TAILQ_FOREACH(it, filter_list, entries) {
2750                 if (memcmp(key, &it->filter_info,
2751                         sizeof(struct e1000_flex_filter_info)) == 0)
2752                         return it;
2753         }
2754
2755         return NULL;
2756 }
2757
2758 static int
2759 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
2760                         struct rte_eth_flex_filter *filter,
2761                         bool add)
2762 {
2763         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2764         struct e1000_filter_info *filter_info =
2765                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2766         struct e1000_flex_filter *flex_filter, *it;
2767         uint32_t wufc, queueing, mask;
2768         uint32_t reg_off;
2769         uint8_t shift, i, j = 0;
2770
2771         flex_filter = rte_zmalloc("e1000_flex_filter",
2772                         sizeof(struct e1000_flex_filter), 0);
2773         if (flex_filter == NULL)
2774                 return -ENOMEM;
2775
2776         flex_filter->filter_info.len = filter->len;
2777         flex_filter->filter_info.priority = filter->priority;
2778         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
2779         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
2780                 mask = 0;
2781                 /* reverse bits in flex filter's mask*/
2782                 for (shift = 0; shift < CHAR_BIT; shift++) {
2783                         if (filter->mask[i] & (0x01 << shift))
2784                                 mask |= (0x80 >> shift);
2785                 }
2786                 flex_filter->filter_info.mask[i] = mask;
2787         }
2788
2789         wufc = E1000_READ_REG(hw, E1000_WUFC);
2790         if (flex_filter->index < E1000_MAX_FHFT)
2791                 reg_off = E1000_FHFT(flex_filter->index);
2792         else
2793                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
2794
2795         if (add) {
2796                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
2797                                 &flex_filter->filter_info) != NULL) {
2798                         PMD_DRV_LOG(ERR, "filter exists.");
2799                         rte_free(flex_filter);
2800                         return -EEXIST;
2801                 }
2802                 flex_filter->queue = filter->queue;
2803                 /*
2804                  * look for an unused flex filter index
2805                  * and insert the filter into the list.
2806                  */
2807                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
2808                         if (!(filter_info->flex_mask & (1 << i))) {
2809                                 filter_info->flex_mask |= 1 << i;
2810                                 flex_filter->index = i;
2811                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
2812                                         flex_filter,
2813                                         entries);
2814                                 break;
2815                         }
2816                 }
2817                 if (i >= E1000_MAX_FLEX_FILTERS) {
2818                         PMD_DRV_LOG(ERR, "flex filters are full.");
2819                         rte_free(flex_filter);
2820                         return -ENOSYS;
2821                 }
2822
2823                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
2824                                 (E1000_WUFC_FLX0 << flex_filter->index));
2825                 queueing = filter->len |
2826                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2827                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2828                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
2829                                 queueing);
2830                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
2831                         E1000_WRITE_REG(hw, reg_off,
2832                                         flex_filter->filter_info.dwords[j]);
2833                         reg_off += sizeof(uint32_t);
2834                         E1000_WRITE_REG(hw, reg_off,
2835                                         flex_filter->filter_info.dwords[++j]);
2836                         reg_off += sizeof(uint32_t);
2837                         E1000_WRITE_REG(hw, reg_off,
2838                                 (uint32_t)flex_filter->filter_info.mask[i]);
2839                         reg_off += sizeof(uint32_t) * 2;
2840                         ++j;
2841                 }
2842         } else {
2843                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
2844                                 &flex_filter->filter_info);
2845                 if (it == NULL) {
2846                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
2847                         rte_free(flex_filter);
2848                         return -ENOENT;
2849                 }
2850
2851                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
2852                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
2853                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
2854                         (~(E1000_WUFC_FLX0 << it->index)));
2855
2856                 filter_info->flex_mask &= ~(1 << it->index);
2857                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
2858                 rte_free(it);
2859                 rte_free(flex_filter);
2860         }
2861
2862         return 0;
2863 }
2864
2865 static int
2866 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
2867                         struct rte_eth_flex_filter *filter)
2868 {
2869         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2870         struct e1000_filter_info *filter_info =
2871                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2872         struct e1000_flex_filter flex_filter, *it;
2873         uint32_t wufc, queueing, wufc_en = 0;
2874
2875         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
2876         flex_filter.filter_info.len = filter->len;
2877         flex_filter.filter_info.priority = filter->priority;
2878         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
2879         memcpy(flex_filter.filter_info.mask, filter->mask,
2880                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
2881
2882         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
2883                                 &flex_filter.filter_info);
2884         if (it == NULL) {
2885                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2886                 return -ENOENT;
2887         }
2888
2889         wufc = E1000_READ_REG(hw, E1000_WUFC);
2890         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
2891
2892         if ((wufc & wufc_en) == wufc_en) {
2893                 uint32_t reg_off = 0;
2894                 if (it->index < E1000_MAX_FHFT)
2895                         reg_off = E1000_FHFT(it->index);
2896                 else
2897                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
2898
2899                 queueing = E1000_READ_REG(hw,
2900                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2901                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2902                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2903                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
2904                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2905                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2906                 return 0;
2907         }
2908         return -ENOENT;
2909 }
2910
2911 static int
2912 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
2913                         enum rte_filter_op filter_op,
2914                         void *arg)
2915 {
2916         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2917         struct rte_eth_flex_filter *filter;
2918         int ret = 0;
2919
2920         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2921
2922         if (filter_op == RTE_ETH_FILTER_NOP)
2923                 return ret;
2924
2925         if (arg == NULL) {
2926                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2927                             filter_op);
2928                 return -EINVAL;
2929         }
2930
2931         filter = (struct rte_eth_flex_filter *)arg;
2932         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
2933             || filter->len % sizeof(uint64_t) != 0) {
2934                 PMD_DRV_LOG(ERR, "filter's length is out of range");
2935                 return -EINVAL;
2936         }
2937         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
2938                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
2939                 return -EINVAL;
2940         }
2941
2942         switch (filter_op) {
2943         case RTE_ETH_FILTER_ADD:
2944                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
2945                 break;
2946         case RTE_ETH_FILTER_DELETE:
2947                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
2948                 break;
2949         case RTE_ETH_FILTER_GET:
2950                 ret = eth_igb_get_flex_filter(dev, filter);
2951                 break;
2952         default:
2953                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
2954                 ret = -EINVAL;
2955                 break;
2956         }
2957
2958         return ret;
2959 }
2960
2961 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
2962 static inline int
2963 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
2964                         struct e1000_5tuple_filter_info *filter_info)
2965 {
2966         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2967                 return -EINVAL;
2968         if (filter->priority > E1000_2TUPLE_MAX_PRI)
2969                 return -EINVAL;  /* filter index is out of range. */
2970         if (filter->tcp_flags > TCP_FLAG_ALL)
2971                 return -EINVAL;  /* flags is invalid. */
2972
2973         switch (filter->dst_ip_mask) {
2974         case UINT32_MAX:
2975                 filter_info->dst_ip_mask = 0;
2976                 filter_info->dst_ip = filter->dst_ip;
2977                 break;
2978         case 0:
2979                 filter_info->dst_ip_mask = 1;
2980                 break;
2981         default:
2982                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2983                 return -EINVAL;
2984         }
2985
2986         switch (filter->src_ip_mask) {
2987         case UINT32_MAX:
2988                 filter_info->src_ip_mask = 0;
2989                 filter_info->src_ip = filter->src_ip;
2990                 break;
2991         case 0:
2992                 filter_info->src_ip_mask = 1;
2993                 break;
2994         default:
2995                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2996                 return -EINVAL;
2997         }
2998
2999         switch (filter->dst_port_mask) {
3000         case UINT16_MAX:
3001                 filter_info->dst_port_mask = 0;
3002                 filter_info->dst_port = filter->dst_port;
3003                 break;
3004         case 0:
3005                 filter_info->dst_port_mask = 1;
3006                 break;
3007         default:
3008                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3009                 return -EINVAL;
3010         }
3011
3012         switch (filter->src_port_mask) {
3013         case UINT16_MAX:
3014                 filter_info->src_port_mask = 0;
3015                 filter_info->src_port = filter->src_port;
3016                 break;
3017         case 0:
3018                 filter_info->src_port_mask = 1;
3019                 break;
3020         default:
3021                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3022                 return -EINVAL;
3023         }
3024
3025         switch (filter->proto_mask) {
3026         case UINT8_MAX:
3027                 filter_info->proto_mask = 0;
3028                 filter_info->proto = filter->proto;
3029                 break;
3030         case 0:
3031                 filter_info->proto_mask = 1;
3032                 break;
3033         default:
3034                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3035                 return -EINVAL;
3036         }
3037
3038         filter_info->priority = (uint8_t)filter->priority;
3039         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3040                 filter_info->tcp_flags = filter->tcp_flags;
3041         else
3042                 filter_info->tcp_flags = 0;
3043
3044         return 0;
3045 }
3046
3047 static inline struct e1000_5tuple_filter *
3048 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3049                         struct e1000_5tuple_filter_info *key)
3050 {
3051         struct e1000_5tuple_filter *it;
3052
3053         TAILQ_FOREACH(it, filter_list, entries) {
3054                 if (memcmp(key, &it->filter_info,
3055                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3056                         return it;
3057                 }
3058         }
3059         return NULL;
3060 }
3061
3062 /*
3063  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3064  *
3065  * @param
3066  * dev: Pointer to struct rte_eth_dev.
3067  * ntuple_filter: ponter to the filter that will be added.
3068  *
3069  * @return
3070  *    - On success, zero.
3071  *    - On failure, a negative value.
3072  */
3073 static int
3074 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3075                         struct rte_eth_ntuple_filter *ntuple_filter)
3076 {
3077         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3078         struct e1000_filter_info *filter_info =
3079                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3080         struct e1000_5tuple_filter *filter;
3081         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3082         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3083         uint8_t i;
3084         int ret;
3085
3086         filter = rte_zmalloc("e1000_5tuple_filter",
3087                         sizeof(struct e1000_5tuple_filter), 0);
3088         if (filter == NULL)
3089                 return -ENOMEM;
3090
3091         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3092                                             &filter->filter_info);
3093         if (ret < 0) {
3094                 rte_free(filter);
3095                 return ret;
3096         }
3097
3098         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3099                                          &filter->filter_info) != NULL) {
3100                 PMD_DRV_LOG(ERR, "filter exists.");
3101                 rte_free(filter);
3102                 return -EEXIST;
3103         }
3104         filter->queue = ntuple_filter->queue;
3105
3106         /*
3107          * look for an unused 5tuple filter index,
3108          * and insert the filter to list.
3109          */
3110         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3111                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3112                         filter_info->fivetuple_mask |= 1 << i;
3113                         filter->index = i;
3114                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3115                                           filter,
3116                                           entries);
3117                         break;
3118                 }
3119         }
3120         if (i >= E1000_MAX_FTQF_FILTERS) {
3121                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3122                 rte_free(filter);
3123                 return -ENOSYS;
3124         }
3125
3126         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3127         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3128                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3129         if (filter->filter_info.dst_ip_mask == 0)
3130                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3131         if (filter->filter_info.src_port_mask == 0)
3132                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3133         if (filter->filter_info.proto_mask == 0)
3134                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3135         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3136                 E1000_FTQF_QUEUE_MASK;
3137         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3138         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3139         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3140         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3141
3142         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3143         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3144
3145         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3146         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3147                 imir |= E1000_IMIR_PORT_BP;
3148         else
3149                 imir &= ~E1000_IMIR_PORT_BP;
3150         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3151
3152         /* tcp flags bits setting. */
3153         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3154                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3155                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3156                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3157                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3158                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3159                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3160                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3161                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3162                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3163                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3164                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3165                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3166         } else
3167                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3168         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3169         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3170         return 0;
3171 }
3172
3173 /*
3174  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3175  *
3176  * @param
3177  * dev: Pointer to struct rte_eth_dev.
3178  * ntuple_filter: ponter to the filter that will be removed.
3179  *
3180  * @return
3181  *    - On success, zero.
3182  *    - On failure, a negative value.
3183  */
3184 static int
3185 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3186                                 struct rte_eth_ntuple_filter *ntuple_filter)
3187 {
3188         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3189         struct e1000_filter_info *filter_info =
3190                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3191         struct e1000_5tuple_filter_info filter_5tuple;
3192         struct e1000_5tuple_filter *filter;
3193         int ret;
3194
3195         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3196         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3197                                             &filter_5tuple);
3198         if (ret < 0)
3199                 return ret;
3200
3201         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3202                                          &filter_5tuple);
3203         if (filter == NULL) {
3204                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3205                 return -ENOENT;
3206         }
3207
3208         filter_info->fivetuple_mask &= ~(1 << filter->index);
3209         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3210         rte_free(filter);
3211
3212         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3213                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3214         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3215         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3216         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3217         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3218         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3219         return 0;
3220 }
3221
3222 static int
3223 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3224 {
3225         uint32_t rctl;
3226         struct e1000_hw *hw;
3227         struct rte_eth_dev_info dev_info;
3228         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3229                                      VLAN_TAG_SIZE);
3230
3231         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3232
3233 #ifdef RTE_LIBRTE_82571_SUPPORT
3234         /* XXX: not bigger than max_rx_pktlen */
3235         if (hw->mac.type == e1000_82571)
3236                 return -ENOTSUP;
3237 #endif
3238         eth_igb_infos_get(dev, &dev_info);
3239
3240         /* check that mtu is within the allowed range */
3241         if ((mtu < ETHER_MIN_MTU) ||
3242             (frame_size > dev_info.max_rx_pktlen))
3243                 return -EINVAL;
3244
3245         /* refuse mtu that requires the support of scattered packets when this
3246          * feature has not been enabled before. */
3247         if (!dev->data->scattered_rx &&
3248             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3249                 return -EINVAL;
3250
3251         rctl = E1000_READ_REG(hw, E1000_RCTL);
3252
3253         /* switch to jumbo mode if needed */
3254         if (frame_size > ETHER_MAX_LEN) {
3255                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3256                 rctl |= E1000_RCTL_LPE;
3257         } else {
3258                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3259                 rctl &= ~E1000_RCTL_LPE;
3260         }
3261         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3262
3263         /* update max frame size */
3264         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3265
3266         E1000_WRITE_REG(hw, E1000_RLPML,
3267                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3268
3269         return 0;
3270 }
3271
3272 /*
3273  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3274  *
3275  * @param
3276  * dev: Pointer to struct rte_eth_dev.
3277  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3278  * add: if true, add filter, if false, remove filter
3279  *
3280  * @return
3281  *    - On success, zero.
3282  *    - On failure, a negative value.
3283  */
3284 static int
3285 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3286                         struct rte_eth_ntuple_filter *ntuple_filter,
3287                         bool add)
3288 {
3289         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3290         int ret;
3291
3292         switch (ntuple_filter->flags) {
3293         case RTE_5TUPLE_FLAGS:
3294         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3295                 if (hw->mac.type != e1000_82576)
3296                         return -ENOTSUP;
3297                 if (add)
3298                         ret = igb_add_5tuple_filter_82576(dev,
3299                                                           ntuple_filter);
3300                 else
3301                         ret = igb_remove_5tuple_filter_82576(dev,
3302                                                              ntuple_filter);
3303                 break;
3304         case RTE_2TUPLE_FLAGS:
3305         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3306                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3307                         return -ENOTSUP;
3308                 if (add)
3309                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3310                 else
3311                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3312                 break;
3313         default:
3314                 ret = -EINVAL;
3315                 break;
3316         }
3317
3318         return ret;
3319 }
3320
3321 /*
3322  * igb_get_ntuple_filter - get a ntuple filter
3323  *
3324  * @param
3325  * dev: Pointer to struct rte_eth_dev.
3326  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3327  *
3328  * @return
3329  *    - On success, zero.
3330  *    - On failure, a negative value.
3331  */
3332 static int
3333 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3334                         struct rte_eth_ntuple_filter *ntuple_filter)
3335 {
3336         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3337         struct e1000_filter_info *filter_info =
3338                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3339         struct e1000_5tuple_filter_info filter_5tuple;
3340         struct e1000_2tuple_filter_info filter_2tuple;
3341         struct e1000_5tuple_filter *p_5tuple_filter;
3342         struct e1000_2tuple_filter *p_2tuple_filter;
3343         int ret;
3344
3345         switch (ntuple_filter->flags) {
3346         case RTE_5TUPLE_FLAGS:
3347         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3348                 if (hw->mac.type != e1000_82576)
3349                         return -ENOTSUP;
3350                 memset(&filter_5tuple,
3351                         0,
3352                         sizeof(struct e1000_5tuple_filter_info));
3353                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3354                                                     &filter_5tuple);
3355                 if (ret < 0)
3356                         return ret;
3357                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3358                                         &filter_info->fivetuple_list,
3359                                         &filter_5tuple);
3360                 if (p_5tuple_filter == NULL) {
3361                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3362                         return -ENOENT;
3363                 }
3364                 ntuple_filter->queue = p_5tuple_filter->queue;
3365                 break;
3366         case RTE_2TUPLE_FLAGS:
3367         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3368                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3369                         return -ENOTSUP;
3370                 memset(&filter_2tuple,
3371                         0,
3372                         sizeof(struct e1000_2tuple_filter_info));
3373                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3374                 if (ret < 0)
3375                         return ret;
3376                 p_2tuple_filter = igb_2tuple_filter_lookup(
3377                                         &filter_info->twotuple_list,
3378                                         &filter_2tuple);
3379                 if (p_2tuple_filter == NULL) {
3380                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3381                         return -ENOENT;
3382                 }
3383                 ntuple_filter->queue = p_2tuple_filter->queue;
3384                 break;
3385         default:
3386                 ret = -EINVAL;
3387                 break;
3388         }
3389
3390         return 0;
3391 }
3392
3393 /*
3394  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3395  * @dev: pointer to rte_eth_dev structure
3396  * @filter_op:operation will be taken.
3397  * @arg: a pointer to specific structure corresponding to the filter_op
3398  */
3399 static int
3400 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3401                                 enum rte_filter_op filter_op,
3402                                 void *arg)
3403 {
3404         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3405         int ret;
3406
3407         MAC_TYPE_FILTER_SUP(hw->mac.type);
3408
3409         if (filter_op == RTE_ETH_FILTER_NOP)
3410                 return 0;
3411
3412         if (arg == NULL) {
3413                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3414                             filter_op);
3415                 return -EINVAL;
3416         }
3417
3418         switch (filter_op) {
3419         case RTE_ETH_FILTER_ADD:
3420                 ret = igb_add_del_ntuple_filter(dev,
3421                         (struct rte_eth_ntuple_filter *)arg,
3422                         TRUE);
3423                 break;
3424         case RTE_ETH_FILTER_DELETE:
3425                 ret = igb_add_del_ntuple_filter(dev,
3426                         (struct rte_eth_ntuple_filter *)arg,
3427                         FALSE);
3428                 break;
3429         case RTE_ETH_FILTER_GET:
3430                 ret = igb_get_ntuple_filter(dev,
3431                         (struct rte_eth_ntuple_filter *)arg);
3432                 break;
3433         default:
3434                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3435                 ret = -EINVAL;
3436                 break;
3437         }
3438         return ret;
3439 }
3440
3441 static inline int
3442 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3443                         uint16_t ethertype)
3444 {
3445         int i;
3446
3447         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3448                 if (filter_info->ethertype_filters[i] == ethertype &&
3449                     (filter_info->ethertype_mask & (1 << i)))
3450                         return i;
3451         }
3452         return -1;
3453 }
3454
3455 static inline int
3456 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3457                         uint16_t ethertype)
3458 {
3459         int i;
3460
3461         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3462                 if (!(filter_info->ethertype_mask & (1 << i))) {
3463                         filter_info->ethertype_mask |= 1 << i;
3464                         filter_info->ethertype_filters[i] = ethertype;
3465                         return i;
3466                 }
3467         }
3468         return -1;
3469 }
3470
3471 static inline int
3472 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3473                         uint8_t idx)
3474 {
3475         if (idx >= E1000_MAX_ETQF_FILTERS)
3476                 return -1;
3477         filter_info->ethertype_mask &= ~(1 << idx);
3478         filter_info->ethertype_filters[idx] = 0;
3479         return idx;
3480 }
3481
3482
3483 static int
3484 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
3485                         struct rte_eth_ethertype_filter *filter,
3486                         bool add)
3487 {
3488         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3489         struct e1000_filter_info *filter_info =
3490                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3491         uint32_t etqf = 0;
3492         int ret;
3493
3494         if (filter->ether_type == ETHER_TYPE_IPv4 ||
3495                 filter->ether_type == ETHER_TYPE_IPv6) {
3496                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3497                         " ethertype filter.", filter->ether_type);
3498                 return -EINVAL;
3499         }
3500
3501         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3502                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3503                 return -EINVAL;
3504         }
3505         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3506                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3507                 return -EINVAL;
3508         }
3509
3510         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3511         if (ret >= 0 && add) {
3512                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3513                             filter->ether_type);
3514                 return -EEXIST;
3515         }
3516         if (ret < 0 && !add) {
3517                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3518                             filter->ether_type);
3519                 return -ENOENT;
3520         }
3521
3522         if (add) {
3523                 ret = igb_ethertype_filter_insert(filter_info,
3524                         filter->ether_type);
3525                 if (ret < 0) {
3526                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
3527                         return -ENOSYS;
3528                 }
3529
3530                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
3531                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
3532                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
3533         } else {
3534                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
3535                 if (ret < 0)
3536                         return -ENOSYS;
3537         }
3538         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
3539         E1000_WRITE_FLUSH(hw);
3540
3541         return 0;
3542 }
3543
3544 static int
3545 igb_get_ethertype_filter(struct rte_eth_dev *dev,
3546                         struct rte_eth_ethertype_filter *filter)
3547 {
3548         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3549         struct e1000_filter_info *filter_info =
3550                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3551         uint32_t etqf;
3552         int ret;
3553
3554         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3555         if (ret < 0) {
3556                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3557                             filter->ether_type);
3558                 return -ENOENT;
3559         }
3560
3561         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
3562         if (etqf & E1000_ETQF_FILTER_ENABLE) {
3563                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
3564                 filter->flags = 0;
3565                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
3566                                 E1000_ETQF_QUEUE_SHIFT;
3567                 return 0;
3568         }
3569
3570         return -ENOENT;
3571 }
3572
3573 /*
3574  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
3575  * @dev: pointer to rte_eth_dev structure
3576  * @filter_op:operation will be taken.
3577  * @arg: a pointer to specific structure corresponding to the filter_op
3578  */
3579 static int
3580 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
3581                                 enum rte_filter_op filter_op,
3582                                 void *arg)
3583 {
3584         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3585         int ret;
3586
3587         MAC_TYPE_FILTER_SUP(hw->mac.type);
3588
3589         if (filter_op == RTE_ETH_FILTER_NOP)
3590                 return 0;
3591
3592         if (arg == NULL) {
3593                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3594                             filter_op);
3595                 return -EINVAL;
3596         }
3597
3598         switch (filter_op) {
3599         case RTE_ETH_FILTER_ADD:
3600                 ret = igb_add_del_ethertype_filter(dev,
3601                         (struct rte_eth_ethertype_filter *)arg,
3602                         TRUE);
3603                 break;
3604         case RTE_ETH_FILTER_DELETE:
3605                 ret = igb_add_del_ethertype_filter(dev,
3606                         (struct rte_eth_ethertype_filter *)arg,
3607                         FALSE);
3608                 break;
3609         case RTE_ETH_FILTER_GET:
3610                 ret = igb_get_ethertype_filter(dev,
3611                         (struct rte_eth_ethertype_filter *)arg);
3612                 break;
3613         default:
3614                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3615                 ret = -EINVAL;
3616                 break;
3617         }
3618         return ret;
3619 }
3620
3621 static int
3622 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
3623                      enum rte_filter_type filter_type,
3624                      enum rte_filter_op filter_op,
3625                      void *arg)
3626 {
3627         int ret = -EINVAL;
3628
3629         switch (filter_type) {
3630         case RTE_ETH_FILTER_NTUPLE:
3631                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
3632                 break;
3633         case RTE_ETH_FILTER_ETHERTYPE:
3634                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
3635                 break;
3636         case RTE_ETH_FILTER_SYN:
3637                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
3638                 break;
3639         case RTE_ETH_FILTER_FLEXIBLE:
3640                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
3641                 break;
3642         default:
3643                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3644                                                         filter_type);
3645                 break;
3646         }
3647
3648         return ret;
3649 }
3650
3651 static int
3652 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
3653                          struct ether_addr *mc_addr_set,
3654                          uint32_t nb_mc_addr)
3655 {
3656         struct e1000_hw *hw;
3657
3658         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3659         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
3660         return 0;
3661 }
3662
3663 static struct rte_driver pmd_igb_drv = {
3664         .type = PMD_PDEV,
3665         .init = rte_igb_pmd_init,
3666 };
3667
3668 static struct rte_driver pmd_igbvf_drv = {
3669         .type = PMD_PDEV,
3670         .init = rte_igbvf_pmd_init,
3671 };
3672
3673 PMD_REGISTER_DRIVER(pmd_igb_drv);
3674 PMD_REGISTER_DRIVER(pmd_igbvf_drv);