drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_string_fns.h>
  12 #include <rte_common.h>
  13 #include <rte_interrupts.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_log.h>
  16 #include <rte_debug.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memory.h>
  23 #include <rte_eal.h>
  24 #include <rte_malloc.h>
  25 #include <rte_dev.h>
  26
  27 #include "e1000_logs.h"
  28 #include "base/e1000_api.h"
  29 #include "e1000_ethdev.h"
  30 #include "igb_regs.h"
  31
  32 /*
  33  * Default values for port configuration
  34  */
  35 #define IGB_DEFAULT_RX_FREE_THRESH  32
  36
  37 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  38 #define IGB_DEFAULT_RX_HTHRESH      8
  39 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  40
  41 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  42 #define IGB_DEFAULT_TX_HTHRESH      1
  43 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  44
  45 /* Bit shift and mask */
  46 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  47 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  48 #define IGB_8_BIT_WIDTH  CHAR_BIT
  49 #define IGB_8_BIT_MASK   UINT8_MAX
  50
  51 /* Additional timesync values. */
  52 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  53 #define E1000_ETQF_FILTER_1588       3
  54 #define IGB_82576_TSYNC_SHIFT        16
  55 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  56 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  58
  59 #define E1000_VTIVAR_MISC                0x01740
  60 #define E1000_VTIVAR_MISC_MASK           0xFF
  61 #define E1000_VTIVAR_VALID               0x80
  62 #define E1000_VTIVAR_MISC_MAILBOX        0
  63 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  64
  65 /* External VLAN Enable bit mask */
  66 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  67
  68 /* External VLAN Ether Type bit mask and shift */
  69 #define E1000_VET_VET_EXT            0xFFFF0000
  70 #define E1000_VET_VET_EXT_SHIFT      16
  71
  72 /* MSI-X other interrupt vector */
  73 #define IGB_MSIX_OTHER_INTR_VEC      0
  74
  75 static int  eth_igb_configure(struct rte_eth_dev *dev);
  76 static int  eth_igb_start(struct rte_eth_dev *dev);
  77 static int  eth_igb_stop(struct rte_eth_dev *dev);
  78 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  79 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  80 static int eth_igb_close(struct rte_eth_dev *dev);
  81 static int eth_igb_reset(struct rte_eth_dev *dev);
  82 static int  eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  83 static int  eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  84 static int  eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  85 static int  eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  87                                 int wait_to_complete);
  88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  89                                 struct rte_eth_stats *rte_stats);
  90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  91                               struct rte_eth_xstat *xstats, unsigned n);
  92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  93                 const uint64_t *ids,
  94                 uint64_t *values, unsigned int n);
  95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  96                                     struct rte_eth_xstat_name *xstats_names,
  97                                     unsigned int size);
  98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  99                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 100                 unsigned int limit);
 101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
 102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
 103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 104                                    char *fw_version, size_t fw_size);
 105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
 106                               struct rte_eth_dev_info *dev_info);
 107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_dev_info *dev_info);
 110 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 113                                 struct rte_eth_fc_conf *fc_conf);
 114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 118                                     struct rte_intr_handle *handle);
 119 static void eth_igb_interrupt_handler(void *param);
 120 static int  igb_hardware_init(struct e1000_hw *hw);
 121 static void igb_hw_control_acquire(struct e1000_hw *hw);
 122 static void igb_hw_control_release(struct e1000_hw *hw);
 123 static void igb_init_manageability(struct e1000_hw *hw);
 124 static void igb_release_manageability(struct e1000_hw *hw);
 125
 126 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 127
 128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 129                 uint16_t vlan_id, int on);
 130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 131                                  enum rte_vlan_type vlan_type,
 132                                  uint16_t tpid_id);
 133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134
 135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 141
 142 static int eth_igb_led_on(struct rte_eth_dev *dev);
 143 static int eth_igb_led_off(struct rte_eth_dev *dev);
 144
 145 static void igb_intr_disable(struct rte_eth_dev *dev);
 146 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 148                            struct rte_ether_addr *mac_addr,
 149                            uint32_t index, uint32_t pool);
 150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 152                 struct rte_ether_addr *addr);
 153
 154 static void igbvf_intr_disable(struct e1000_hw *hw);
 155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 156 static int igbvf_dev_start(struct rte_eth_dev *dev);
 157 static int igbvf_dev_stop(struct rte_eth_dev *dev);
 158 static int igbvf_dev_close(struct rte_eth_dev *dev);
 159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 163 static int eth_igbvf_link_update(struct e1000_hw *hw);
 164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_stats *rte_stats);
 166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 167                                 struct rte_eth_xstat *xstats, unsigned n);
 168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 169                                       struct rte_eth_xstat_name *xstats_names,
 170                                       unsigned limit);
 171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 173                 uint16_t vlan_id, int on);
 174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 177                 struct rte_ether_addr *addr);
 178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 179 static int igbvf_get_regs(struct rte_eth_dev *dev,
 180                 struct rte_dev_reg_info *regs);
 181
 182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 183                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                    uint16_t reta_size);
 185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 186                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 187                                   uint16_t reta_size);
 188
 189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 190                         struct rte_eth_syn_filter *filter);
 191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 192                         enum rte_filter_op filter_op,
 193                         void *arg);
 194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_ntuple_filter *ntuple_filter);
 198 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 199                         struct rte_eth_ntuple_filter *ntuple_filter);
 200 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 201                         struct rte_eth_ntuple_filter *ntuple_filter);
 202 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 203                         struct rte_eth_ntuple_filter *filter);
 204 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 205                                 enum rte_filter_op filter_op,
 206                                 void *arg);
 207 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 208                      enum rte_filter_type filter_type,
 209                      enum rte_filter_op filter_op,
 210                      void *arg);
 211 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 212 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 213                 struct rte_dev_reg_info *regs);
 214 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 215 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 216                 struct rte_dev_eeprom_info *eeprom);
 217 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 218                 struct rte_dev_eeprom_info *eeprom);
 219 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
 220                                    struct rte_eth_dev_module_info *modinfo);
 221 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
 222                                      struct rte_dev_eeprom_info *info);
 223 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 224                                     struct rte_ether_addr *mc_addr_set,
 225                                     uint32_t nb_mc_addr);
 226 static int igb_timesync_enable(struct rte_eth_dev *dev);
 227 static int igb_timesync_disable(struct rte_eth_dev *dev);
 228 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 229                                           struct timespec *timestamp,
 230                                           uint32_t flags);
 231 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 232                                           struct timespec *timestamp);
 233 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 234 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 235                                   struct timespec *timestamp);
 236 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 237                                    const struct timespec *timestamp);
 238 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 239                                         uint16_t queue_id);
 240 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 241                                          uint16_t queue_id);
 242 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 243                                        uint8_t queue, uint8_t msix_vector);
 244 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 245                                uint8_t index, uint8_t offset);
 246 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 247 static void eth_igbvf_interrupt_handler(void *param);
 248 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 249 static int igb_filter_restore(struct rte_eth_dev *dev);
 250
 251 /*
 252  * Define VF Stats MACRO for Non "cleared on read" register
 253  */
 254 #define UPDATE_VF_STAT(reg, last, cur)            \
 255 {                                                 \
 256         u32 latest = E1000_READ_REG(hw, reg);     \
 257         cur += (latest - last) & UINT_MAX;        \
 258         last = latest;                            \
 259 }
 260
 261 #define IGB_FC_PAUSE_TIME 0x0680
 262 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 263 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 264
 265 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 266
 267 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 268
 269 /*
 270  * The set of PCI devices this driver supports
 271  */
 272 static const struct rte_pci_id pci_id_igb_map[] = {
 273         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 274         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 275         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 276         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 277         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 278         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 279         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 280         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 281
 282         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 284         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 285
 286         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 287         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 288         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 289         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 290         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 291         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 292
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 295         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 296         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 297         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 302         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 303         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 304         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 305         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 314         { .vendor_id = 0, /* sentinel */ },
 315 };
 316
 317 /*
 318  * The set of PCI devices this driver supports (for 82576&I350 VF)
 319  */
 320 static const struct rte_pci_id pci_id_igbvf_map[] = {
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 325         { .vendor_id = 0, /* sentinel */ },
 326 };
 327
 328 static const struct rte_eth_desc_lim rx_desc_lim = {
 329         .nb_max = E1000_MAX_RING_DESC,
 330         .nb_min = E1000_MIN_RING_DESC,
 331         .nb_align = IGB_RXD_ALIGN,
 332 };
 333
 334 static const struct rte_eth_desc_lim tx_desc_lim = {
 335         .nb_max = E1000_MAX_RING_DESC,
 336         .nb_min = E1000_MIN_RING_DESC,
 337         .nb_align = IGB_RXD_ALIGN,
 338         .nb_seg_max = IGB_TX_MAX_SEG,
 339         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 340 };
 341
 342 static const struct eth_dev_ops eth_igb_ops = {
 343         .dev_configure        = eth_igb_configure,
 344         .dev_start            = eth_igb_start,
 345         .dev_stop             = eth_igb_stop,
 346         .dev_set_link_up      = eth_igb_dev_set_link_up,
 347         .dev_set_link_down    = eth_igb_dev_set_link_down,
 348         .dev_close            = eth_igb_close,
 349         .dev_reset            = eth_igb_reset,
 350         .promiscuous_enable   = eth_igb_promiscuous_enable,
 351         .promiscuous_disable  = eth_igb_promiscuous_disable,
 352         .allmulticast_enable  = eth_igb_allmulticast_enable,
 353         .allmulticast_disable = eth_igb_allmulticast_disable,
 354         .link_update          = eth_igb_link_update,
 355         .stats_get            = eth_igb_stats_get,
 356         .xstats_get           = eth_igb_xstats_get,
 357         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 358         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 359         .xstats_get_names     = eth_igb_xstats_get_names,
 360         .stats_reset          = eth_igb_stats_reset,
 361         .xstats_reset         = eth_igb_xstats_reset,
 362         .fw_version_get       = eth_igb_fw_version_get,
 363         .dev_infos_get        = eth_igb_infos_get,
 364         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 365         .mtu_set              = eth_igb_mtu_set,
 366         .vlan_filter_set      = eth_igb_vlan_filter_set,
 367         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 368         .vlan_offload_set     = eth_igb_vlan_offload_set,
 369         .rx_queue_setup       = eth_igb_rx_queue_setup,
 370         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 371         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 372         .rx_queue_release     = eth_igb_rx_queue_release,
 373         .tx_queue_setup       = eth_igb_tx_queue_setup,
 374         .tx_queue_release     = eth_igb_tx_queue_release,
 375         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 376         .dev_led_on           = eth_igb_led_on,
 377         .dev_led_off          = eth_igb_led_off,
 378         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 379         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 380         .mac_addr_add         = eth_igb_rar_set,
 381         .mac_addr_remove      = eth_igb_rar_clear,
 382         .mac_addr_set         = eth_igb_default_mac_addr_set,
 383         .reta_update          = eth_igb_rss_reta_update,
 384         .reta_query           = eth_igb_rss_reta_query,
 385         .rss_hash_update      = eth_igb_rss_hash_update,
 386         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 387         .filter_ctrl          = eth_igb_filter_ctrl,
 388         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 389         .rxq_info_get         = igb_rxq_info_get,
 390         .txq_info_get         = igb_txq_info_get,
 391         .timesync_enable      = igb_timesync_enable,
 392         .timesync_disable     = igb_timesync_disable,
 393         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 394         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 395         .get_reg              = eth_igb_get_regs,
 396         .get_eeprom_length    = eth_igb_get_eeprom_length,
 397         .get_eeprom           = eth_igb_get_eeprom,
 398         .set_eeprom           = eth_igb_set_eeprom,
 399         .get_module_info      = eth_igb_get_module_info,
 400         .get_module_eeprom    = eth_igb_get_module_eeprom,
 401         .timesync_adjust_time = igb_timesync_adjust_time,
 402         .timesync_read_time   = igb_timesync_read_time,
 403         .timesync_write_time  = igb_timesync_write_time,
 404 };
 405
 406 /*
 407  * dev_ops for virtual function, bare necessities for basic vf
 408  * operation have been implemented
 409  */
 410 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 411         .dev_configure        = igbvf_dev_configure,
 412         .dev_start            = igbvf_dev_start,
 413         .dev_stop             = igbvf_dev_stop,
 414         .dev_close            = igbvf_dev_close,
 415         .promiscuous_enable   = igbvf_promiscuous_enable,
 416         .promiscuous_disable  = igbvf_promiscuous_disable,
 417         .allmulticast_enable  = igbvf_allmulticast_enable,
 418         .allmulticast_disable = igbvf_allmulticast_disable,
 419         .link_update          = eth_igb_link_update,
 420         .stats_get            = eth_igbvf_stats_get,
 421         .xstats_get           = eth_igbvf_xstats_get,
 422         .xstats_get_names     = eth_igbvf_xstats_get_names,
 423         .stats_reset          = eth_igbvf_stats_reset,
 424         .xstats_reset         = eth_igbvf_stats_reset,
 425         .vlan_filter_set      = igbvf_vlan_filter_set,
 426         .dev_infos_get        = eth_igbvf_infos_get,
 427         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 428         .rx_queue_setup       = eth_igb_rx_queue_setup,
 429         .rx_queue_release     = eth_igb_rx_queue_release,
 430         .tx_queue_setup       = eth_igb_tx_queue_setup,
 431         .tx_queue_release     = eth_igb_tx_queue_release,
 432         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 433         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 434         .rxq_info_get         = igb_rxq_info_get,
 435         .txq_info_get         = igb_txq_info_get,
 436         .mac_addr_set         = igbvf_default_mac_addr_set,
 437         .get_reg              = igbvf_get_regs,
 438 };
 439
 440 /* store statistics names and its offset in stats structure */
 441 struct rte_igb_xstats_name_off {
 442         char name[RTE_ETH_XSTATS_NAME_SIZE];
 443         unsigned offset;
 444 };
 445
 446 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 447         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 448         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 449         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 450         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 451         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 452         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 453         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 454                 ecol)},
 455         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 456         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 457         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 458         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 459         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 460         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 461         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 462         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 463         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 464         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 465         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 466                 fcruc)},
 467         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 468         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 469         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 470         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 471         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 472                 prc1023)},
 473         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 474                 prc1522)},
 475         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 476         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 477         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 478         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 479         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 480         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 481         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 482         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 483         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 484         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 485         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 486         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 487         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 488         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 489         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 490         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 491         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 492         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 493                 ptc1023)},
 494         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 495                 ptc1522)},
 496         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 497         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 498         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 499         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 500         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 501         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 502         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 503
 504         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 505 };
 506
 507 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 508                 sizeof(rte_igb_stats_strings[0]))
 509
 510 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 511         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 512         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 513         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 514         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 515         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 516 };
 517
 518 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 519                 sizeof(rte_igbvf_stats_strings[0]))
 520
 521
 522 static inline void
 523 igb_intr_enable(struct rte_eth_dev *dev)
 524 {
 525         struct e1000_interrupt *intr =
 526                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 527         struct e1000_hw *hw =
 528                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 529         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 530         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 531
 532         if (rte_intr_allow_others(intr_handle) &&
 533                 dev->data->dev_conf.intr_conf.lsc != 0) {
 534                 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
 535         }
 536
 537         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 538         E1000_WRITE_FLUSH(hw);
 539 }
 540
 541 static void
 542 igb_intr_disable(struct rte_eth_dev *dev)
 543 {
 544         struct e1000_hw *hw =
 545                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 546         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 547         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 548
 549         if (rte_intr_allow_others(intr_handle) &&
 550                 dev->data->dev_conf.intr_conf.lsc != 0) {
 551                 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
 552         }
 553
 554         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 555         E1000_WRITE_FLUSH(hw);
 556 }
 557
 558 static inline void
 559 igbvf_intr_enable(struct rte_eth_dev *dev)
 560 {
 561         struct e1000_hw *hw =
 562                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 563
 564         /* only for mailbox */
 565         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 566         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 567         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 568         E1000_WRITE_FLUSH(hw);
 569 }
 570
 571 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 572 static void
 573 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 574 {
 575         uint32_t tmp = 0;
 576
 577         /* mailbox */
 578         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 579         tmp |= E1000_VTIVAR_VALID;
 580         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 581 }
 582
 583 static void
 584 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 585 {
 586         struct e1000_hw *hw =
 587                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 588
 589         /* Configure VF other cause ivar */
 590         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 591 }
 592
 593 static inline int32_t
 594 igb_pf_reset_hw(struct e1000_hw *hw)
 595 {
 596         uint32_t ctrl_ext;
 597         int32_t status;
 598
 599         status = e1000_reset_hw(hw);
 600
 601         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 602         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 603         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 604         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 605         E1000_WRITE_FLUSH(hw);
 606
 607         return status;
 608 }
 609
 610 static void
 611 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 612 {
 613         struct e1000_hw *hw =
 614                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 615
 616
 617         hw->vendor_id = pci_dev->id.vendor_id;
 618         hw->device_id = pci_dev->id.device_id;
 619         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 620         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 621
 622         e1000_set_mac_type(hw);
 623
 624         /* need to check if it is a vf device below */
 625 }
 626
 627 static int
 628 igb_reset_swfw_lock(struct e1000_hw *hw)
 629 {
 630         int ret_val;
 631
 632         /*
 633          * Do mac ops initialization manually here, since we will need
 634          * some function pointers set by this call.
 635          */
 636         ret_val = e1000_init_mac_params(hw);
 637         if (ret_val)
 638                 return ret_val;
 639
 640         /*
 641          * SMBI lock should not fail in this early stage. If this is the case,
 642          * it is due to an improper exit of the application.
 643          * So force the release of the faulty lock.
 644          */
 645         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 646                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 647         }
 648         e1000_put_hw_semaphore_generic(hw);
 649
 650         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 651                 uint16_t mask;
 652
 653                 /*
 654                  * Phy lock should not fail in this early stage. If this is the case,
 655                  * it is due to an improper exit of the application.
 656                  * So force the release of the faulty lock.
 657                  */
 658                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 659                 if (hw->bus.func > E1000_FUNC_1)
 660                         mask <<= 2;
 661                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 662                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 663                                     hw->bus.func);
 664                 }
 665                 hw->mac.ops.release_swfw_sync(hw, mask);
 666
 667                 /*
 668                  * This one is more tricky since it is common to all ports; but
 669                  * swfw_sync retries last long enough (1s) to be almost sure that if
 670                  * lock can not be taken it is due to an improper lock of the
 671                  * semaphore.
 672                  */
 673                 mask = E1000_SWFW_EEP_SM;
 674                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 675                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 676                 }
 677                 hw->mac.ops.release_swfw_sync(hw, mask);
 678         }
 679
 680         return E1000_SUCCESS;
 681 }
 682
 683 /* Remove all ntuple filters of the device */
 684 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 685 {
 686         struct e1000_filter_info *filter_info =
 687                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 688         struct e1000_5tuple_filter *p_5tuple;
 689         struct e1000_2tuple_filter *p_2tuple;
 690
 691         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 692                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 693                         p_5tuple, entries);
 694                         rte_free(p_5tuple);
 695         }
 696         filter_info->fivetuple_mask = 0;
 697         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 698                 TAILQ_REMOVE(&filter_info->twotuple_list,
 699                         p_2tuple, entries);
 700                         rte_free(p_2tuple);
 701         }
 702         filter_info->twotuple_mask = 0;
 703
 704         return 0;
 705 }
 706
 707 /* Remove all flex filters of the device */
 708 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 709 {
 710         struct e1000_filter_info *filter_info =
 711                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 712         struct e1000_flex_filter *p_flex;
 713
 714         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 715                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 716                 rte_free(p_flex);
 717         }
 718         filter_info->flex_mask = 0;
 719
 720         return 0;
 721 }
 722
 723 static int
 724 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 725 {
 726         int error = 0;
 727         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 728         struct e1000_hw *hw =
 729                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 730         struct e1000_vfta * shadow_vfta =
 731                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 732         struct e1000_filter_info *filter_info =
 733                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 734         struct e1000_adapter *adapter =
 735                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 736
 737         uint32_t ctrl_ext;
 738
 739         eth_dev->dev_ops = &eth_igb_ops;
 740         eth_dev->rx_queue_count = eth_igb_rx_queue_count;
 741         eth_dev->rx_descriptor_done   = eth_igb_rx_descriptor_done;
 742         eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
 743         eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
 744         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 745         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 746         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 747
 748         /* for secondary processes, we don't initialise any further as primary
 749          * has already done this work. Only check we don't need a different
 750          * RX function */
 751         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 752                 if (eth_dev->data->scattered_rx)
 753                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 754                 return 0;
 755         }
 756
 757         rte_eth_copy_pci_info(eth_dev, pci_dev);
 758         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 759
 760         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 761
 762         igb_identify_hardware(eth_dev, pci_dev);
 763         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 764                 error = -EIO;
 765                 goto err_late;
 766         }
 767
 768         e1000_get_bus_info(hw);
 769
 770         /* Reset any pending lock */
 771         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 772                 error = -EIO;
 773                 goto err_late;
 774         }
 775
 776         /* Finish initialization */
 777         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 778                 error = -EIO;
 779                 goto err_late;
 780         }
 781
 782         hw->mac.autoneg = 1;
 783         hw->phy.autoneg_wait_to_complete = 0;
 784         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 785
 786         /* Copper options */
 787         if (hw->phy.media_type == e1000_media_type_copper) {
 788                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 789                 hw->phy.disable_polarity_correction = 0;
 790                 hw->phy.ms_type = e1000_ms_hw_default;
 791         }
 792
 793         /*
 794          * Start from a known state, this is important in reading the nvm
 795          * and mac from that.
 796          */
 797         igb_pf_reset_hw(hw);
 798
 799         /* Make sure we have a good EEPROM before we read from it */
 800         if (e1000_validate_nvm_checksum(hw) < 0) {
 801                 /*
 802                  * Some PCI-E parts fail the first check due to
 803                  * the link being in sleep state, call it again,
 804                  * if it fails a second time its a real issue.
 805                  */
 806                 if (e1000_validate_nvm_checksum(hw) < 0) {
 807                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 808                         error = -EIO;
 809                         goto err_late;
 810                 }
 811         }
 812
 813         /* Read the permanent MAC address out of the EEPROM */
 814         if (e1000_read_mac_addr(hw) != 0) {
 815                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 816                 error = -EIO;
 817                 goto err_late;
 818         }
 819
 820         /* Allocate memory for storing MAC addresses */
 821         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 822                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 823         if (eth_dev->data->mac_addrs == NULL) {
 824                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 825                                                 "store MAC addresses",
 826                                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 827                 error = -ENOMEM;
 828                 goto err_late;
 829         }
 830
 831         /* Copy the permanent MAC address */
 832         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 833                         &eth_dev->data->mac_addrs[0]);
 834
 835         /* initialize the vfta */
 836         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 837
 838         /* Now initialize the hardware */
 839         if (igb_hardware_init(hw) != 0) {
 840                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 841                 rte_free(eth_dev->data->mac_addrs);
 842                 eth_dev->data->mac_addrs = NULL;
 843                 error = -ENODEV;
 844                 goto err_late;
 845         }
 846         hw->mac.get_link_status = 1;
 847         adapter->stopped = 0;
 848
 849         /* Indicate SOL/IDER usage */
 850         if (e1000_check_reset_block(hw) < 0) {
 851                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 852                                         "SOL/IDER session");
 853         }
 854
 855         /* initialize PF if max_vfs not zero */
 856         igb_pf_host_init(eth_dev);
 857
 858         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 859         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 860         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 861         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 862         E1000_WRITE_FLUSH(hw);
 863
 864         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 865                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 866                      pci_dev->id.device_id);
 867
 868         rte_intr_callback_register(&pci_dev->intr_handle,
 869                                    eth_igb_interrupt_handler,
 870                                    (void *)eth_dev);
 871
 872         /* enable uio/vfio intr/eventfd mapping */
 873         rte_intr_enable(&pci_dev->intr_handle);
 874
 875         /* enable support intr */
 876         igb_intr_enable(eth_dev);
 877
 878         eth_igb_dev_set_link_down(eth_dev);
 879
 880         /* initialize filter info */
 881         memset(filter_info, 0,
 882                sizeof(struct e1000_filter_info));
 883
 884         TAILQ_INIT(&filter_info->flex_list);
 885         TAILQ_INIT(&filter_info->twotuple_list);
 886         TAILQ_INIT(&filter_info->fivetuple_list);
 887
 888         TAILQ_INIT(&igb_filter_ntuple_list);
 889         TAILQ_INIT(&igb_filter_ethertype_list);
 890         TAILQ_INIT(&igb_filter_syn_list);
 891         TAILQ_INIT(&igb_filter_flex_list);
 892         TAILQ_INIT(&igb_filter_rss_list);
 893         TAILQ_INIT(&igb_flow_list);
 894
 895         return 0;
 896
 897 err_late:
 898         igb_hw_control_release(hw);
 899
 900         return error;
 901 }
 902
 903 static int
 904 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 905 {
 906         PMD_INIT_FUNC_TRACE();
 907
 908         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 909                 return 0;
 910
 911         eth_igb_close(eth_dev);
 912
 913         return 0;
 914 }
 915
 916 /*
 917  * Virtual Function device init
 918  */
 919 static int
 920 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 921 {
 922         struct rte_pci_device *pci_dev;
 923         struct rte_intr_handle *intr_handle;
 924         struct e1000_adapter *adapter =
 925                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 926         struct e1000_hw *hw =
 927                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 928         int diag;
 929         struct rte_ether_addr *perm_addr =
 930                 (struct rte_ether_addr *)hw->mac.perm_addr;
 931
 932         PMD_INIT_FUNC_TRACE();
 933
 934         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 935         eth_dev->rx_descriptor_done   = eth_igb_rx_descriptor_done;
 936         eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
 937         eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
 938         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 939         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 940         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 941
 942         /* for secondary processes, we don't initialise any further as primary
 943          * has already done this work. Only check we don't need a different
 944          * RX function */
 945         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 946                 if (eth_dev->data->scattered_rx)
 947                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 948                 return 0;
 949         }
 950
 951         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 952         rte_eth_copy_pci_info(eth_dev, pci_dev);
 953         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 954
 955         hw->device_id = pci_dev->id.device_id;
 956         hw->vendor_id = pci_dev->id.vendor_id;
 957         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 958         adapter->stopped = 0;
 959
 960         /* Initialize the shared code (base driver) */
 961         diag = e1000_setup_init_funcs(hw, TRUE);
 962         if (diag != 0) {
 963                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 964                         diag);
 965                 return -EIO;
 966         }
 967
 968         /* init_mailbox_params */
 969         hw->mbx.ops.init_params(hw);
 970
 971         /* Disable the interrupts for VF */
 972         igbvf_intr_disable(hw);
 973
 974         diag = hw->mac.ops.reset_hw(hw);
 975
 976         /* Allocate memory for storing MAC addresses */
 977         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
 978                 hw->mac.rar_entry_count, 0);
 979         if (eth_dev->data->mac_addrs == NULL) {
 980                 PMD_INIT_LOG(ERR,
 981                         "Failed to allocate %d bytes needed to store MAC "
 982                         "addresses",
 983                         RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 984                 return -ENOMEM;
 985         }
 986
 987         /* Generate a random MAC address, if none was assigned by PF. */
 988         if (rte_is_zero_ether_addr(perm_addr)) {
 989                 rte_eth_random_addr(perm_addr->addr_bytes);
 990                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
 991                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
 992                              "%02x:%02x:%02x:%02x:%02x:%02x",
 993                              perm_addr->addr_bytes[0],
 994                              perm_addr->addr_bytes[1],
 995                              perm_addr->addr_bytes[2],
 996                              perm_addr->addr_bytes[3],
 997                              perm_addr->addr_bytes[4],
 998                              perm_addr->addr_bytes[5]);
 999         }
1000
1001         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1002         if (diag) {
1003                 rte_free(eth_dev->data->mac_addrs);
1004                 eth_dev->data->mac_addrs = NULL;
1005                 return diag;
1006         }
1007         /* Copy the permanent MAC address */
1008         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1009                         &eth_dev->data->mac_addrs[0]);
1010
1011         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1012                      "mac.type=%s",
1013                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1014                      pci_dev->id.device_id, "igb_mac_82576_vf");
1015
1016         intr_handle = &pci_dev->intr_handle;
1017         rte_intr_callback_register(intr_handle,
1018                                    eth_igbvf_interrupt_handler, eth_dev);
1019
1020         return 0;
1021 }
1022
1023 static int
1024 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1025 {
1026         PMD_INIT_FUNC_TRACE();
1027
1028         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1029                 return 0;
1030
1031         igbvf_dev_close(eth_dev);
1032
1033         return 0;
1034 }
1035
1036 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1037         struct rte_pci_device *pci_dev)
1038 {
1039         return rte_eth_dev_pci_generic_probe(pci_dev,
1040                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1041 }
1042
1043 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1044 {
1045         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1046 }
1047
1048 static struct rte_pci_driver rte_igb_pmd = {
1049         .id_table = pci_id_igb_map,
1050         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1051         .probe = eth_igb_pci_probe,
1052         .remove = eth_igb_pci_remove,
1053 };
1054
1055
1056 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1057         struct rte_pci_device *pci_dev)
1058 {
1059         return rte_eth_dev_pci_generic_probe(pci_dev,
1060                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1061 }
1062
1063 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1064 {
1065         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1066 }
1067
1068 /*
1069  * virtual function driver struct
1070  */
1071 static struct rte_pci_driver rte_igbvf_pmd = {
1072         .id_table = pci_id_igbvf_map,
1073         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1074         .probe = eth_igbvf_pci_probe,
1075         .remove = eth_igbvf_pci_remove,
1076 };
1077
1078 static void
1079 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1080 {
1081         struct e1000_hw *hw =
1082                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1083         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1084         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1085         rctl |= E1000_RCTL_VFE;
1086         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1087 }
1088
1089 static int
1090 igb_check_mq_mode(struct rte_eth_dev *dev)
1091 {
1092         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1093         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1094         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1095         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1096
1097         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1098             tx_mq_mode == ETH_MQ_TX_DCB ||
1099             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1100                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1101                 return -EINVAL;
1102         }
1103         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1104                 /* Check multi-queue mode.
1105                  * To no break software we accept ETH_MQ_RX_NONE as this might
1106                  * be used to turn off VLAN filter.
1107                  */
1108
1109                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1110                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1111                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1112                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1113                 } else {
1114                         /* Only support one queue on VFs.
1115                          * RSS together with SRIOV is not supported.
1116                          */
1117                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1118                                         " wrong mq_mode rx %d.",
1119                                         rx_mq_mode);
1120                         return -EINVAL;
1121                 }
1122                 /* TX mode is not used here, so mode might be ignored.*/
1123                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1124                         /* SRIOV only works in VMDq enable mode */
1125                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1126                                         " TX mode %d is not supported. "
1127                                         " Driver will behave as %d mode.",
1128                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1129                 }
1130
1131                 /* check valid queue number */
1132                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1133                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1134                                         " only support one queue on VFs.");
1135                         return -EINVAL;
1136                 }
1137         } else {
1138                 /* To no break software that set invalid mode, only display
1139                  * warning if invalid mode is used.
1140                  */
1141                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1142                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1143                     rx_mq_mode != ETH_MQ_RX_RSS) {
1144                         /* RSS together with VMDq not supported*/
1145                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1146                                      rx_mq_mode);
1147                         return -EINVAL;
1148                 }
1149
1150                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1151                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1152                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1153                                         " Due to txmode is meaningless in this"
1154                                         " driver, just ignore.",
1155                                         tx_mq_mode);
1156                 }
1157         }
1158         return 0;
1159 }
1160
1161 static int
1162 eth_igb_configure(struct rte_eth_dev *dev)
1163 {
1164         struct e1000_interrupt *intr =
1165                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1166         int ret;
1167
1168         PMD_INIT_FUNC_TRACE();
1169
1170         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1171                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1172
1173         /* multipe queue mode checking */
1174         ret  = igb_check_mq_mode(dev);
1175         if (ret != 0) {
1176                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1177                             ret);
1178                 return ret;
1179         }
1180
1181         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1182         PMD_INIT_FUNC_TRACE();
1183
1184         return 0;
1185 }
1186
1187 static void
1188 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1189                      bool enable)
1190 {
1191         struct e1000_hw *hw =
1192                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1193         uint32_t tctl, rctl;
1194
1195         tctl = E1000_READ_REG(hw, E1000_TCTL);
1196         rctl = E1000_READ_REG(hw, E1000_RCTL);
1197
1198         if (enable) {
1199                 /* enable Tx/Rx */
1200                 tctl |= E1000_TCTL_EN;
1201                 rctl |= E1000_RCTL_EN;
1202         } else {
1203                 /* disable Tx/Rx */
1204                 tctl &= ~E1000_TCTL_EN;
1205                 rctl &= ~E1000_RCTL_EN;
1206         }
1207         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1208         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1209         E1000_WRITE_FLUSH(hw);
1210 }
1211
1212 static int
1213 eth_igb_start(struct rte_eth_dev *dev)
1214 {
1215         struct e1000_hw *hw =
1216                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1217         struct e1000_adapter *adapter =
1218                 E1000_DEV_PRIVATE(dev->data->dev_private);
1219         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1220         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1221         int ret, mask;
1222         uint32_t intr_vector = 0;
1223         uint32_t ctrl_ext;
1224         uint32_t *speeds;
1225         int num_speeds;
1226         bool autoneg;
1227
1228         PMD_INIT_FUNC_TRACE();
1229
1230         /* disable uio/vfio intr/eventfd mapping */
1231         rte_intr_disable(intr_handle);
1232
1233         /* Power up the phy. Needed to make the link go Up */
1234         eth_igb_dev_set_link_up(dev);
1235
1236         /*
1237          * Packet Buffer Allocation (PBA)
1238          * Writing PBA sets the receive portion of the buffer
1239          * the remainder is used for the transmit buffer.
1240          */
1241         if (hw->mac.type == e1000_82575) {
1242                 uint32_t pba;
1243
1244                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1245                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1246         }
1247
1248         /* Put the address into the Receive Address Array */
1249         e1000_rar_set(hw, hw->mac.addr, 0);
1250
1251         /* Initialize the hardware */
1252         if (igb_hardware_init(hw)) {
1253                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1254                 return -EIO;
1255         }
1256         adapter->stopped = 0;
1257
1258         E1000_WRITE_REG(hw, E1000_VET,
1259                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1260
1261         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1262         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1263         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1264         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1265         E1000_WRITE_FLUSH(hw);
1266
1267         /* configure PF module if SRIOV enabled */
1268         igb_pf_host_configure(dev);
1269
1270         /* check and configure queue intr-vector mapping */
1271         if ((rte_intr_cap_multiple(intr_handle) ||
1272              !RTE_ETH_DEV_SRIOV(dev).active) &&
1273             dev->data->dev_conf.intr_conf.rxq != 0) {
1274                 intr_vector = dev->data->nb_rx_queues;
1275                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1276                         return -1;
1277         }
1278
1279         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1280                 intr_handle->intr_vec =
1281                         rte_zmalloc("intr_vec",
1282                                     dev->data->nb_rx_queues * sizeof(int), 0);
1283                 if (intr_handle->intr_vec == NULL) {
1284                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1285                                      " intr_vec", dev->data->nb_rx_queues);
1286                         return -ENOMEM;
1287                 }
1288         }
1289
1290         /* confiugre msix for rx interrupt */
1291         eth_igb_configure_msix_intr(dev);
1292
1293         /* Configure for OS presence */
1294         igb_init_manageability(hw);
1295
1296         eth_igb_tx_init(dev);
1297
1298         /* This can fail when allocating mbufs for descriptor rings */
1299         ret = eth_igb_rx_init(dev);
1300         if (ret) {
1301                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1302                 igb_dev_clear_queues(dev);
1303                 return ret;
1304         }
1305
1306         e1000_clear_hw_cntrs_base_generic(hw);
1307
1308         /*
1309          * VLAN Offload Settings
1310          */
1311         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1312                         ETH_VLAN_EXTEND_MASK;
1313         ret = eth_igb_vlan_offload_set(dev, mask);
1314         if (ret) {
1315                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1316                 igb_dev_clear_queues(dev);
1317                 return ret;
1318         }
1319
1320         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1321                 /* Enable VLAN filter since VMDq always use VLAN filter */
1322                 igb_vmdq_vlan_hw_filter_enable(dev);
1323         }
1324
1325         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1326                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1327                 (hw->mac.type == e1000_i211)) {
1328                 /* Configure EITR with the maximum possible value (0xFFFF) */
1329                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1330         }
1331
1332         /* Setup link speed and duplex */
1333         speeds = &dev->data->dev_conf.link_speeds;
1334         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1335                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1336                 hw->mac.autoneg = 1;
1337         } else {
1338                 num_speeds = 0;
1339                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1340
1341                 /* Reset */
1342                 hw->phy.autoneg_advertised = 0;
1343
1344                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1345                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1346                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1347                         num_speeds = -1;
1348                         goto error_invalid_config;
1349                 }
1350                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1351                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1352                         num_speeds++;
1353                 }
1354                 if (*speeds & ETH_LINK_SPEED_10M) {
1355                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1356                         num_speeds++;
1357                 }
1358                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1359                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1360                         num_speeds++;
1361                 }
1362                 if (*speeds & ETH_LINK_SPEED_100M) {
1363                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1364                         num_speeds++;
1365                 }
1366                 if (*speeds & ETH_LINK_SPEED_1G) {
1367                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1368                         num_speeds++;
1369                 }
1370                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1371                         goto error_invalid_config;
1372
1373                 /* Set/reset the mac.autoneg based on the link speed,
1374                  * fixed or not
1375                  */
1376                 if (!autoneg) {
1377                         hw->mac.autoneg = 0;
1378                         hw->mac.forced_speed_duplex =
1379                                         hw->phy.autoneg_advertised;
1380                 } else {
1381                         hw->mac.autoneg = 1;
1382                 }
1383         }
1384
1385         e1000_setup_link(hw);
1386
1387         if (rte_intr_allow_others(intr_handle)) {
1388                 /* check if lsc interrupt is enabled */
1389                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1390                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1391                 else
1392                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1393         } else {
1394                 rte_intr_callback_unregister(intr_handle,
1395                                              eth_igb_interrupt_handler,
1396                                              (void *)dev);
1397                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1398                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1399                                      " no intr multiplex");
1400         }
1401
1402         /* check if rxq interrupt is enabled */
1403         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1404             rte_intr_dp_is_en(intr_handle))
1405                 eth_igb_rxq_interrupt_setup(dev);
1406
1407         /* enable uio/vfio intr/eventfd mapping */
1408         rte_intr_enable(intr_handle);
1409
1410         /* resume enabled intr since hw reset */
1411         igb_intr_enable(dev);
1412
1413         /* restore all types filter */
1414         igb_filter_restore(dev);
1415
1416         eth_igb_rxtx_control(dev, true);
1417         eth_igb_link_update(dev, 0);
1418
1419         PMD_INIT_LOG(DEBUG, "<<");
1420
1421         return 0;
1422
1423 error_invalid_config:
1424         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1425                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1426         igb_dev_clear_queues(dev);
1427         return -EINVAL;
1428 }
1429
1430 /*********************************************************************
1431  *
1432  *  This routine disables all traffic on the adapter by issuing a
1433  *  global reset on the MAC.
1434  *
1435  **********************************************************************/
1436 static int
1437 eth_igb_stop(struct rte_eth_dev *dev)
1438 {
1439         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1440         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1441         struct rte_eth_link link;
1442         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1443         struct e1000_adapter *adapter =
1444                 E1000_DEV_PRIVATE(dev->data->dev_private);
1445
1446         if (adapter->stopped)
1447                 return 0;
1448
1449         eth_igb_rxtx_control(dev, false);
1450
1451         igb_intr_disable(dev);
1452
1453         /* disable intr eventfd mapping */
1454         rte_intr_disable(intr_handle);
1455
1456         igb_pf_reset_hw(hw);
1457         E1000_WRITE_REG(hw, E1000_WUC, 0);
1458
1459         /* Set bit for Go Link disconnect if PHY reset is not blocked */
1460         if (hw->mac.type >= e1000_82580 &&
1461             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1462                 uint32_t phpm_reg;
1463
1464                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1465                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1466                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1467         }
1468
1469         /* Power down the phy. Needed to make the link go Down */
1470         eth_igb_dev_set_link_down(dev);
1471
1472         igb_dev_clear_queues(dev);
1473
1474         /* clear the recorded link status */
1475         memset(&link, 0, sizeof(link));
1476         rte_eth_linkstatus_set(dev, &link);
1477
1478         if (!rte_intr_allow_others(intr_handle))
1479                 /* resume to the default handler */
1480                 rte_intr_callback_register(intr_handle,
1481                                            eth_igb_interrupt_handler,
1482                                            (void *)dev);
1483
1484         /* Clean datapath event and queue/vec mapping */
1485         rte_intr_efd_disable(intr_handle);
1486         if (intr_handle->intr_vec != NULL) {
1487                 rte_free(intr_handle->intr_vec);
1488                 intr_handle->intr_vec = NULL;
1489         }
1490
1491         adapter->stopped = true;
1492         dev->data->dev_started = 0;
1493
1494         return 0;
1495 }
1496
1497 static int
1498 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1499 {
1500         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1501
1502         if (hw->phy.media_type == e1000_media_type_copper)
1503                 e1000_power_up_phy(hw);
1504         else
1505                 e1000_power_up_fiber_serdes_link(hw);
1506
1507         return 0;
1508 }
1509
1510 static int
1511 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1512 {
1513         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1514
1515         if (hw->phy.media_type == e1000_media_type_copper)
1516                 e1000_power_down_phy(hw);
1517         else
1518                 e1000_shutdown_fiber_serdes_link(hw);
1519
1520         return 0;
1521 }
1522
1523 static int
1524 eth_igb_close(struct rte_eth_dev *dev)
1525 {
1526         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1527         struct rte_eth_link link;
1528         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1529         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1530         struct e1000_filter_info *filter_info =
1531                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1532         int ret;
1533
1534         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1535                 return 0;
1536
1537         ret = eth_igb_stop(dev);
1538
1539         e1000_phy_hw_reset(hw);
1540         igb_release_manageability(hw);
1541         igb_hw_control_release(hw);
1542
1543         /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1544         if (hw->mac.type >= e1000_82580 &&
1545             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1546                 uint32_t phpm_reg;
1547
1548                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1549                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1550                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1551         }
1552
1553         igb_dev_free_queues(dev);
1554
1555         if (intr_handle->intr_vec) {
1556                 rte_free(intr_handle->intr_vec);
1557                 intr_handle->intr_vec = NULL;
1558         }
1559
1560         memset(&link, 0, sizeof(link));
1561         rte_eth_linkstatus_set(dev, &link);
1562
1563         /* Reset any pending lock */
1564         igb_reset_swfw_lock(hw);
1565
1566         /* uninitialize PF if max_vfs not zero */
1567         igb_pf_host_uninit(dev);
1568
1569         rte_intr_callback_unregister(intr_handle,
1570                                      eth_igb_interrupt_handler, dev);
1571
1572         /* clear the SYN filter info */
1573         filter_info->syn_info = 0;
1574
1575         /* clear the ethertype filters info */
1576         filter_info->ethertype_mask = 0;
1577         memset(filter_info->ethertype_filters, 0,
1578                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1579
1580         /* clear the rss filter info */
1581         memset(&filter_info->rss_info, 0,
1582                 sizeof(struct igb_rte_flow_rss_conf));
1583
1584         /* remove all ntuple filters of the device */
1585         igb_ntuple_filter_uninit(dev);
1586
1587         /* remove all flex filters of the device */
1588         igb_flex_filter_uninit(dev);
1589
1590         /* clear all the filters list */
1591         igb_filterlist_flush(dev);
1592
1593         return ret;
1594 }
1595
1596 /*
1597  * Reset PF device.
1598  */
1599 static int
1600 eth_igb_reset(struct rte_eth_dev *dev)
1601 {
1602         int ret;
1603
1604         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1605          * its VF to make them align with it. The detailed notification
1606          * mechanism is PMD specific and is currently not implemented.
1607          * To avoid unexpected behavior in VF, currently reset of PF with
1608          * SR-IOV activation is not supported. It might be supported later.
1609          */
1610         if (dev->data->sriov.active)
1611                 return -ENOTSUP;
1612
1613         ret = eth_igb_dev_uninit(dev);
1614         if (ret)
1615                 return ret;
1616
1617         ret = eth_igb_dev_init(dev);
1618
1619         return ret;
1620 }
1621
1622
1623 static int
1624 igb_get_rx_buffer_size(struct e1000_hw *hw)
1625 {
1626         uint32_t rx_buf_size;
1627         if (hw->mac.type == e1000_82576) {
1628                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1629         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1630                 /* PBS needs to be translated according to a lookup table */
1631                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1632                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1633                 rx_buf_size = (rx_buf_size << 10);
1634         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1635                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1636         } else {
1637                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1638         }
1639
1640         return rx_buf_size;
1641 }
1642
1643 /*********************************************************************
1644  *
1645  *  Initialize the hardware
1646  *
1647  **********************************************************************/
1648 static int
1649 igb_hardware_init(struct e1000_hw *hw)
1650 {
1651         uint32_t rx_buf_size;
1652         int diag;
1653
1654         /* Let the firmware know the OS is in control */
1655         igb_hw_control_acquire(hw);
1656
1657         /*
1658          * These parameters control the automatic generation (Tx) and
1659          * response (Rx) to Ethernet PAUSE frames.
1660          * - High water mark should allow for at least two standard size (1518)
1661          *   frames to be received after sending an XOFF.
1662          * - Low water mark works best when it is very near the high water mark.
1663          *   This allows the receiver to restart by sending XON when it has
1664          *   drained a bit. Here we use an arbitrary value of 1500 which will
1665          *   restart after one full frame is pulled from the buffer. There
1666          *   could be several smaller frames in the buffer and if so they will
1667          *   not trigger the XON until their total number reduces the buffer
1668          *   by 1500.
1669          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1670          */
1671         rx_buf_size = igb_get_rx_buffer_size(hw);
1672
1673         hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1674         hw->fc.low_water = hw->fc.high_water - 1500;
1675         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1676         hw->fc.send_xon = 1;
1677
1678         /* Set Flow control, use the tunable location if sane */
1679         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1680                 hw->fc.requested_mode = igb_fc_setting;
1681         else
1682                 hw->fc.requested_mode = e1000_fc_none;
1683
1684         /* Issue a global reset */
1685         igb_pf_reset_hw(hw);
1686         E1000_WRITE_REG(hw, E1000_WUC, 0);
1687
1688         diag = e1000_init_hw(hw);
1689         if (diag < 0)
1690                 return diag;
1691
1692         E1000_WRITE_REG(hw, E1000_VET,
1693                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1694         e1000_get_phy_info(hw);
1695         e1000_check_for_link(hw);
1696
1697         return 0;
1698 }
1699
1700 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1701 static void
1702 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1703 {
1704         int pause_frames;
1705
1706         uint64_t old_gprc  = stats->gprc;
1707         uint64_t old_gptc  = stats->gptc;
1708         uint64_t old_tpr   = stats->tpr;
1709         uint64_t old_tpt   = stats->tpt;
1710         uint64_t old_rpthc = stats->rpthc;
1711         uint64_t old_hgptc = stats->hgptc;
1712
1713         if(hw->phy.media_type == e1000_media_type_copper ||
1714             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1715                 stats->symerrs +=
1716                     E1000_READ_REG(hw,E1000_SYMERRS);
1717                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1718         }
1719
1720         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1721         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1722         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1723         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1724
1725         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1726         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1727         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1728         stats->dc += E1000_READ_REG(hw, E1000_DC);
1729         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1730         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1731         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1732         /*
1733         ** For watchdog management we need to know if we have been
1734         ** paused during the last interval, so capture that here.
1735         */
1736         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1737         stats->xoffrxc += pause_frames;
1738         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1739         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1740         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1741         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1742         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1743         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1744         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1745         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1746         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1747         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1748         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1749         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1750
1751         /* For the 64-bit byte counters the low dword must be read first. */
1752         /* Both registers clear on the read of the high dword */
1753
1754         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1755         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1756         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1757         stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1758         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1759         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1760         stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1761
1762         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1763         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1764         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1765         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1766         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1767
1768         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1769         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1770
1771         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1772         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1773         stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1774         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1775         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1776         stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1777
1778         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1779         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1780         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1781         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1782         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1783         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1784         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1785         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1786
1787         /* Interrupt Counts */
1788
1789         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1790         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1791         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1792         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1793         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1794         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1795         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1796         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1797         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1798
1799         /* Host to Card Statistics */
1800
1801         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1802         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1803         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1804         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1805         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1806         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1807         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1808         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1809         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1810         stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1811         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1812         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1813         stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1814         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1815         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1816         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1817
1818         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1819         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1820         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1821         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1822         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1823         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1824 }
1825
1826 static int
1827 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1828 {
1829         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1830         struct e1000_hw_stats *stats =
1831                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1832
1833         igb_read_stats_registers(hw, stats);
1834
1835         if (rte_stats == NULL)
1836                 return -EINVAL;
1837
1838         /* Rx Errors */
1839         rte_stats->imissed = stats->mpc;
1840         rte_stats->ierrors = stats->crcerrs +
1841                              stats->rlec + stats->ruc + stats->roc +
1842                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1843
1844         /* Tx Errors */
1845         rte_stats->oerrors = stats->ecol + stats->latecol;
1846
1847         rte_stats->ipackets = stats->gprc;
1848         rte_stats->opackets = stats->gptc;
1849         rte_stats->ibytes   = stats->gorc;
1850         rte_stats->obytes   = stats->gotc;
1851         return 0;
1852 }
1853
1854 static int
1855 eth_igb_stats_reset(struct rte_eth_dev *dev)
1856 {
1857         struct e1000_hw_stats *hw_stats =
1858                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1859
1860         /* HW registers are cleared on read */
1861         eth_igb_stats_get(dev, NULL);
1862
1863         /* Reset software totals */
1864         memset(hw_stats, 0, sizeof(*hw_stats));
1865
1866         return 0;
1867 }
1868
1869 static int
1870 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1871 {
1872         struct e1000_hw_stats *stats =
1873                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1874
1875         /* HW registers are cleared on read */
1876         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1877
1878         /* Reset software totals */
1879         memset(stats, 0, sizeof(*stats));
1880
1881         return 0;
1882 }
1883
1884 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1885         struct rte_eth_xstat_name *xstats_names,
1886         __rte_unused unsigned int size)
1887 {
1888         unsigned i;
1889
1890         if (xstats_names == NULL)
1891                 return IGB_NB_XSTATS;
1892
1893         /* Note: limit checked in rte_eth_xstats_names() */
1894
1895         for (i = 0; i < IGB_NB_XSTATS; i++) {
1896                 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1897                         sizeof(xstats_names[i].name));
1898         }
1899
1900         return IGB_NB_XSTATS;
1901 }
1902
1903 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1904                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1905                 unsigned int limit)
1906 {
1907         unsigned int i;
1908
1909         if (!ids) {
1910                 if (xstats_names == NULL)
1911                         return IGB_NB_XSTATS;
1912
1913                 for (i = 0; i < IGB_NB_XSTATS; i++)
1914                         strlcpy(xstats_names[i].name,
1915                                 rte_igb_stats_strings[i].name,
1916                                 sizeof(xstats_names[i].name));
1917
1918                 return IGB_NB_XSTATS;
1919
1920         } else {
1921                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1922
1923                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1924                                 IGB_NB_XSTATS);
1925
1926                 for (i = 0; i < limit; i++) {
1927                         if (ids[i] >= IGB_NB_XSTATS) {
1928                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1929                                 return -1;
1930                         }
1931                         strcpy(xstats_names[i].name,
1932                                         xstats_names_copy[ids[i]].name);
1933                 }
1934                 return limit;
1935         }
1936 }
1937
1938 static int
1939 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1940                    unsigned n)
1941 {
1942         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943         struct e1000_hw_stats *hw_stats =
1944                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1945         unsigned i;
1946
1947         if (n < IGB_NB_XSTATS)
1948                 return IGB_NB_XSTATS;
1949
1950         igb_read_stats_registers(hw, hw_stats);
1951
1952         /* If this is a reset xstats is NULL, and we have cleared the
1953          * registers by reading them.
1954          */
1955         if (!xstats)
1956                 return 0;
1957
1958         /* Extended stats */
1959         for (i = 0; i < IGB_NB_XSTATS; i++) {
1960                 xstats[i].id = i;
1961                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1962                         rte_igb_stats_strings[i].offset);
1963         }
1964
1965         return IGB_NB_XSTATS;
1966 }
1967
1968 static int
1969 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1970                 uint64_t *values, unsigned int n)
1971 {
1972         unsigned int i;
1973
1974         if (!ids) {
1975                 struct e1000_hw *hw =
1976                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1977                 struct e1000_hw_stats *hw_stats =
1978                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1979
1980                 if (n < IGB_NB_XSTATS)
1981                         return IGB_NB_XSTATS;
1982
1983                 igb_read_stats_registers(hw, hw_stats);
1984
1985                 /* If this is a reset xstats is NULL, and we have cleared the
1986                  * registers by reading them.
1987                  */
1988                 if (!values)
1989                         return 0;
1990
1991                 /* Extended stats */
1992                 for (i = 0; i < IGB_NB_XSTATS; i++)
1993                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1994                                         rte_igb_stats_strings[i].offset);
1995
1996                 return IGB_NB_XSTATS;
1997
1998         } else {
1999                 uint64_t values_copy[IGB_NB_XSTATS];
2000
2001                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2002                                 IGB_NB_XSTATS);
2003
2004                 for (i = 0; i < n; i++) {
2005                         if (ids[i] >= IGB_NB_XSTATS) {
2006                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2007                                 return -1;
2008                         }
2009                         values[i] = values_copy[ids[i]];
2010                 }
2011                 return n;
2012         }
2013 }
2014
2015 static void
2016 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2017 {
2018         /* Good Rx packets, include VF loopback */
2019         UPDATE_VF_STAT(E1000_VFGPRC,
2020             hw_stats->last_gprc, hw_stats->gprc);
2021
2022         /* Good Rx octets, include VF loopback */
2023         UPDATE_VF_STAT(E1000_VFGORC,
2024             hw_stats->last_gorc, hw_stats->gorc);
2025
2026         /* Good Tx packets, include VF loopback */
2027         UPDATE_VF_STAT(E1000_VFGPTC,
2028             hw_stats->last_gptc, hw_stats->gptc);
2029
2030         /* Good Tx octets, include VF loopback */
2031         UPDATE_VF_STAT(E1000_VFGOTC,
2032             hw_stats->last_gotc, hw_stats->gotc);
2033
2034         /* Rx Multicst packets */
2035         UPDATE_VF_STAT(E1000_VFMPRC,
2036             hw_stats->last_mprc, hw_stats->mprc);
2037
2038         /* Good Rx loopback packets */
2039         UPDATE_VF_STAT(E1000_VFGPRLBC,
2040             hw_stats->last_gprlbc, hw_stats->gprlbc);
2041
2042         /* Good Rx loopback octets */
2043         UPDATE_VF_STAT(E1000_VFGORLBC,
2044             hw_stats->last_gorlbc, hw_stats->gorlbc);
2045
2046         /* Good Tx loopback packets */
2047         UPDATE_VF_STAT(E1000_VFGPTLBC,
2048             hw_stats->last_gptlbc, hw_stats->gptlbc);
2049
2050         /* Good Tx loopback octets */
2051         UPDATE_VF_STAT(E1000_VFGOTLBC,
2052             hw_stats->last_gotlbc, hw_stats->gotlbc);
2053 }
2054
2055 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2056                                      struct rte_eth_xstat_name *xstats_names,
2057                                      __rte_unused unsigned limit)
2058 {
2059         unsigned i;
2060
2061         if (xstats_names != NULL)
2062                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2063                         strlcpy(xstats_names[i].name,
2064                                 rte_igbvf_stats_strings[i].name,
2065                                 sizeof(xstats_names[i].name));
2066                 }
2067         return IGBVF_NB_XSTATS;
2068 }
2069
2070 static int
2071 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2072                      unsigned n)
2073 {
2074         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2075         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2076                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2077         unsigned i;
2078
2079         if (n < IGBVF_NB_XSTATS)
2080                 return IGBVF_NB_XSTATS;
2081
2082         igbvf_read_stats_registers(hw, hw_stats);
2083
2084         if (!xstats)
2085                 return 0;
2086
2087         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2088                 xstats[i].id = i;
2089                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2090                         rte_igbvf_stats_strings[i].offset);
2091         }
2092
2093         return IGBVF_NB_XSTATS;
2094 }
2095
2096 static int
2097 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2098 {
2099         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2101                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2102
2103         igbvf_read_stats_registers(hw, hw_stats);
2104
2105         if (rte_stats == NULL)
2106                 return -EINVAL;
2107
2108         rte_stats->ipackets = hw_stats->gprc;
2109         rte_stats->ibytes = hw_stats->gorc;
2110         rte_stats->opackets = hw_stats->gptc;
2111         rte_stats->obytes = hw_stats->gotc;
2112         return 0;
2113 }
2114
2115 static int
2116 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2117 {
2118         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2119                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2120
2121         /* Sync HW register to the last stats */
2122         eth_igbvf_stats_get(dev, NULL);
2123
2124         /* reset HW current stats*/
2125         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2126                offsetof(struct e1000_vf_stats, gprc));
2127
2128         return 0;
2129 }
2130
2131 static int
2132 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2133                        size_t fw_size)
2134 {
2135         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2136         struct e1000_fw_version fw;
2137         int ret;
2138
2139         e1000_get_fw_version(hw, &fw);
2140
2141         switch (hw->mac.type) {
2142         case e1000_i210:
2143         case e1000_i211:
2144                 if (!(e1000_get_flash_presence_i210(hw))) {
2145                         ret = snprintf(fw_version, fw_size,
2146                                  "%2d.%2d-%d",
2147                                  fw.invm_major, fw.invm_minor,
2148                                  fw.invm_img_type);
2149                         break;
2150                 }
2151                 /* fall through */
2152         default:
2153                 /* if option rom is valid, display its version too */
2154                 if (fw.or_valid) {
2155                         ret = snprintf(fw_version, fw_size,
2156                                  "%d.%d, 0x%08x, %d.%d.%d",
2157                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2158                                  fw.or_major, fw.or_build, fw.or_patch);
2159                 /* no option rom */
2160                 } else {
2161                         if (fw.etrack_id != 0X0000) {
2162                                 ret = snprintf(fw_version, fw_size,
2163                                          "%d.%d, 0x%08x",
2164                                          fw.eep_major, fw.eep_minor,
2165                                          fw.etrack_id);
2166                         } else {
2167                                 ret = snprintf(fw_version, fw_size,
2168                                          "%d.%d.%d",
2169                                          fw.eep_major, fw.eep_minor,
2170                                          fw.eep_build);
2171                         }
2172                 }
2173                 break;
2174         }
2175
2176         ret += 1; /* add the size of '\0' */
2177         if (fw_size < (u32)ret)
2178                 return ret;
2179         else
2180                 return 0;
2181 }
2182
2183 static int
2184 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2185 {
2186         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2187
2188         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2189         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2190         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2191         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2192         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2193                                     dev_info->rx_queue_offload_capa;
2194         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2195         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2196                                     dev_info->tx_queue_offload_capa;
2197
2198         switch (hw->mac.type) {
2199         case e1000_82575:
2200                 dev_info->max_rx_queues = 4;
2201                 dev_info->max_tx_queues = 4;
2202                 dev_info->max_vmdq_pools = 0;
2203                 break;
2204
2205         case e1000_82576:
2206                 dev_info->max_rx_queues = 16;
2207                 dev_info->max_tx_queues = 16;
2208                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2209                 dev_info->vmdq_queue_num = 16;
2210                 break;
2211
2212         case e1000_82580:
2213                 dev_info->max_rx_queues = 8;
2214                 dev_info->max_tx_queues = 8;
2215                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2216                 dev_info->vmdq_queue_num = 8;
2217                 break;
2218
2219         case e1000_i350:
2220                 dev_info->max_rx_queues = 8;
2221                 dev_info->max_tx_queues = 8;
2222                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2223                 dev_info->vmdq_queue_num = 8;
2224                 break;
2225
2226         case e1000_i354:
2227                 dev_info->max_rx_queues = 8;
2228                 dev_info->max_tx_queues = 8;
2229                 break;
2230
2231         case e1000_i210:
2232                 dev_info->max_rx_queues = 4;
2233                 dev_info->max_tx_queues = 4;
2234                 dev_info->max_vmdq_pools = 0;
2235                 break;
2236
2237         case e1000_i211:
2238                 dev_info->max_rx_queues = 2;
2239                 dev_info->max_tx_queues = 2;
2240                 dev_info->max_vmdq_pools = 0;
2241                 break;
2242
2243         default:
2244                 /* Should not happen */
2245                 return -EINVAL;
2246         }
2247         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2248         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2249         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2250
2251         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2252                 .rx_thresh = {
2253                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2254                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2255                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2256                 },
2257                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2258                 .rx_drop_en = 0,
2259                 .offloads = 0,
2260         };
2261
2262         dev_info->default_txconf = (struct rte_eth_txconf) {
2263                 .tx_thresh = {
2264                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2265                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2266                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2267                 },
2268                 .offloads = 0,
2269         };
2270
2271         dev_info->rx_desc_lim = rx_desc_lim;
2272         dev_info->tx_desc_lim = tx_desc_lim;
2273
2274         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2275                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2276                         ETH_LINK_SPEED_1G;
2277
2278         dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2279         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2280
2281         return 0;
2282 }
2283
2284 static const uint32_t *
2285 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2286 {
2287         static const uint32_t ptypes[] = {
2288                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2289                 RTE_PTYPE_L2_ETHER,
2290                 RTE_PTYPE_L3_IPV4,
2291                 RTE_PTYPE_L3_IPV4_EXT,
2292                 RTE_PTYPE_L3_IPV6,
2293                 RTE_PTYPE_L3_IPV6_EXT,
2294                 RTE_PTYPE_L4_TCP,
2295                 RTE_PTYPE_L4_UDP,
2296                 RTE_PTYPE_L4_SCTP,
2297                 RTE_PTYPE_TUNNEL_IP,
2298                 RTE_PTYPE_INNER_L3_IPV6,
2299                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2300                 RTE_PTYPE_INNER_L4_TCP,
2301                 RTE_PTYPE_INNER_L4_UDP,
2302                 RTE_PTYPE_UNKNOWN
2303         };
2304
2305         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2306             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2307                 return ptypes;
2308         return NULL;
2309 }
2310
2311 static int
2312 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2313 {
2314         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2315
2316         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2317         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2318         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2319         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2320                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2321                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2322                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2323                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2324                                 DEV_TX_OFFLOAD_TCP_TSO;
2325         switch (hw->mac.type) {
2326         case e1000_vfadapt:
2327                 dev_info->max_rx_queues = 2;
2328                 dev_info->max_tx_queues = 2;
2329                 break;
2330         case e1000_vfadapt_i350:
2331                 dev_info->max_rx_queues = 1;
2332                 dev_info->max_tx_queues = 1;
2333                 break;
2334         default:
2335                 /* Should not happen */
2336                 return -EINVAL;
2337         }
2338
2339         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2340         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2341                                     dev_info->rx_queue_offload_capa;
2342         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2343         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2344                                     dev_info->tx_queue_offload_capa;
2345
2346         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2347                 .rx_thresh = {
2348                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2349                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2350                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2351                 },
2352                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2353                 .rx_drop_en = 0,
2354                 .offloads = 0,
2355         };
2356
2357         dev_info->default_txconf = (struct rte_eth_txconf) {
2358                 .tx_thresh = {
2359                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2360                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2361                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2362                 },
2363                 .offloads = 0,
2364         };
2365
2366         dev_info->rx_desc_lim = rx_desc_lim;
2367         dev_info->tx_desc_lim = tx_desc_lim;
2368
2369         return 0;
2370 }
2371
2372 /* return 0 means link status changed, -1 means not changed */
2373 static int
2374 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2375 {
2376         struct e1000_hw *hw =
2377                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2378         struct rte_eth_link link;
2379         int link_check, count;
2380
2381         link_check = 0;
2382         hw->mac.get_link_status = 1;
2383
2384         /* possible wait-to-complete in up to 9 seconds */
2385         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2386                 /* Read the real link status */
2387                 switch (hw->phy.media_type) {
2388                 case e1000_media_type_copper:
2389                         /* Do the work to read phy */
2390                         e1000_check_for_link(hw);
2391                         link_check = !hw->mac.get_link_status;
2392                         break;
2393
2394                 case e1000_media_type_fiber:
2395                         e1000_check_for_link(hw);
2396                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2397                                       E1000_STATUS_LU);
2398                         break;
2399
2400                 case e1000_media_type_internal_serdes:
2401                         e1000_check_for_link(hw);
2402                         link_check = hw->mac.serdes_has_link;
2403                         break;
2404
2405                 /* VF device is type_unknown */
2406                 case e1000_media_type_unknown:
2407                         eth_igbvf_link_update(hw);
2408                         link_check = !hw->mac.get_link_status;
2409                         break;
2410
2411                 default:
2412                         break;
2413                 }
2414                 if (link_check || wait_to_complete == 0)
2415                         break;
2416                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2417         }
2418         memset(&link, 0, sizeof(link));
2419
2420         /* Now we check if a transition has happened */
2421         if (link_check) {
2422                 uint16_t duplex, speed;
2423                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2424                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2425                                 ETH_LINK_FULL_DUPLEX :
2426                                 ETH_LINK_HALF_DUPLEX;
2427                 link.link_speed = speed;
2428                 link.link_status = ETH_LINK_UP;
2429                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2430                                 ETH_LINK_SPEED_FIXED);
2431         } else if (!link_check) {
2432                 link.link_speed = 0;
2433                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2434                 link.link_status = ETH_LINK_DOWN;
2435                 link.link_autoneg = ETH_LINK_FIXED;
2436         }
2437
2438         return rte_eth_linkstatus_set(dev, &link);
2439 }
2440
2441 /*
2442  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2443  * For ASF and Pass Through versions of f/w this means
2444  * that the driver is loaded.
2445  */
2446 static void
2447 igb_hw_control_acquire(struct e1000_hw *hw)
2448 {
2449         uint32_t ctrl_ext;
2450
2451         /* Let firmware know the driver has taken over */
2452         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2453         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2454 }
2455
2456 /*
2457  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2458  * For ASF and Pass Through versions of f/w this means that the
2459  * driver is no longer loaded.
2460  */
2461 static void
2462 igb_hw_control_release(struct e1000_hw *hw)
2463 {
2464         uint32_t ctrl_ext;
2465
2466         /* Let firmware taken over control of h/w */
2467         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2468         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2469                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2470 }
2471
2472 /*
2473  * Bit of a misnomer, what this really means is
2474  * to enable OS management of the system... aka
2475  * to disable special hardware management features.
2476  */
2477 static void
2478 igb_init_manageability(struct e1000_hw *hw)
2479 {
2480         if (e1000_enable_mng_pass_thru(hw)) {
2481                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2482                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2483
2484                 /* disable hardware interception of ARP */
2485                 manc &= ~(E1000_MANC_ARP_EN);
2486
2487                 /* enable receiving management packets to the host */
2488                 manc |= E1000_MANC_EN_MNG2HOST;
2489                 manc2h |= 1 << 5;  /* Mng Port 623 */
2490                 manc2h |= 1 << 6;  /* Mng Port 664 */
2491                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2492                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2493         }
2494 }
2495
2496 static void
2497 igb_release_manageability(struct e1000_hw *hw)
2498 {
2499         if (e1000_enable_mng_pass_thru(hw)) {
2500                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2501
2502                 manc |= E1000_MANC_ARP_EN;
2503                 manc &= ~E1000_MANC_EN_MNG2HOST;
2504
2505                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2506         }
2507 }
2508
2509 static int
2510 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2511 {
2512         struct e1000_hw *hw =
2513                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2514         uint32_t rctl;
2515
2516         rctl = E1000_READ_REG(hw, E1000_RCTL);
2517         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2518         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2519
2520         return 0;
2521 }
2522
2523 static int
2524 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2525 {
2526         struct e1000_hw *hw =
2527                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2528         uint32_t rctl;
2529
2530         rctl = E1000_READ_REG(hw, E1000_RCTL);
2531         rctl &= (~E1000_RCTL_UPE);
2532         if (dev->data->all_multicast == 1)
2533                 rctl |= E1000_RCTL_MPE;
2534         else
2535                 rctl &= (~E1000_RCTL_MPE);
2536         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2537
2538         return 0;
2539 }
2540
2541 static int
2542 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2543 {
2544         struct e1000_hw *hw =
2545                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2546         uint32_t rctl;
2547
2548         rctl = E1000_READ_REG(hw, E1000_RCTL);
2549         rctl |= E1000_RCTL_MPE;
2550         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2551
2552         return 0;
2553 }
2554
2555 static int
2556 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2557 {
2558         struct e1000_hw *hw =
2559                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2560         uint32_t rctl;
2561
2562         if (dev->data->promiscuous == 1)
2563                 return 0; /* must remain in all_multicast mode */
2564         rctl = E1000_READ_REG(hw, E1000_RCTL);
2565         rctl &= (~E1000_RCTL_MPE);
2566         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2567
2568         return 0;
2569 }
2570
2571 static int
2572 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2573 {
2574         struct e1000_hw *hw =
2575                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2576         struct e1000_vfta * shadow_vfta =
2577                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2578         uint32_t vfta;
2579         uint32_t vid_idx;
2580         uint32_t vid_bit;
2581
2582         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2583                               E1000_VFTA_ENTRY_MASK);
2584         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2585         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2586         if (on)
2587                 vfta |= vid_bit;
2588         else
2589                 vfta &= ~vid_bit;
2590         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2591
2592         /* update local VFTA copy */
2593         shadow_vfta->vfta[vid_idx] = vfta;
2594
2595         return 0;
2596 }
2597
2598 static int
2599 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2600                       enum rte_vlan_type vlan_type,
2601                       uint16_t tpid)
2602 {
2603         struct e1000_hw *hw =
2604                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2605         uint32_t reg, qinq;
2606
2607         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2608         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2609
2610         /* only outer TPID of double VLAN can be configured*/
2611         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2612                 reg = E1000_READ_REG(hw, E1000_VET);
2613                 reg = (reg & (~E1000_VET_VET_EXT)) |
2614                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2615                 E1000_WRITE_REG(hw, E1000_VET, reg);
2616
2617                 return 0;
2618         }
2619
2620         /* all other TPID values are read-only*/
2621         PMD_DRV_LOG(ERR, "Not supported");
2622
2623         return -ENOTSUP;
2624 }
2625
2626 static void
2627 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2628 {
2629         struct e1000_hw *hw =
2630                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2631         uint32_t reg;
2632
2633         /* Filter Table Disable */
2634         reg = E1000_READ_REG(hw, E1000_RCTL);
2635         reg &= ~E1000_RCTL_CFIEN;
2636         reg &= ~E1000_RCTL_VFE;
2637         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2638 }
2639
2640 static void
2641 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2642 {
2643         struct e1000_hw *hw =
2644                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2645         struct e1000_vfta * shadow_vfta =
2646                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2647         uint32_t reg;
2648         int i;
2649
2650         /* Filter Table Enable, CFI not used for packet acceptance */
2651         reg = E1000_READ_REG(hw, E1000_RCTL);
2652         reg &= ~E1000_RCTL_CFIEN;
2653         reg |= E1000_RCTL_VFE;
2654         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2655
2656         /* restore VFTA table */
2657         for (i = 0; i < IGB_VFTA_SIZE; i++)
2658                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2659 }
2660
2661 static void
2662 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2663 {
2664         struct e1000_hw *hw =
2665                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2666         uint32_t reg;
2667
2668         /* VLAN Mode Disable */
2669         reg = E1000_READ_REG(hw, E1000_CTRL);
2670         reg &= ~E1000_CTRL_VME;
2671         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2672 }
2673
2674 static void
2675 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2676 {
2677         struct e1000_hw *hw =
2678                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2679         uint32_t reg;
2680
2681         /* VLAN Mode Enable */
2682         reg = E1000_READ_REG(hw, E1000_CTRL);
2683         reg |= E1000_CTRL_VME;
2684         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2685 }
2686
2687 static void
2688 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2689 {
2690         struct e1000_hw *hw =
2691                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2692         uint32_t reg;
2693
2694         /* CTRL_EXT: Extended VLAN */
2695         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2696         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2697         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2698
2699         /* Update maximum packet length */
2700         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2701                 E1000_WRITE_REG(hw, E1000_RLPML,
2702                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2703                                                 VLAN_TAG_SIZE);
2704 }
2705
2706 static void
2707 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2708 {
2709         struct e1000_hw *hw =
2710                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2711         uint32_t reg;
2712
2713         /* CTRL_EXT: Extended VLAN */
2714         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2715         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2716         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2717
2718         /* Update maximum packet length */
2719         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2720                 E1000_WRITE_REG(hw, E1000_RLPML,
2721                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2722                                                 2 * VLAN_TAG_SIZE);
2723 }
2724
2725 static int
2726 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2727 {
2728         struct rte_eth_rxmode *rxmode;
2729
2730         rxmode = &dev->data->dev_conf.rxmode;
2731         if(mask & ETH_VLAN_STRIP_MASK){
2732                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2733                         igb_vlan_hw_strip_enable(dev);
2734                 else
2735                         igb_vlan_hw_strip_disable(dev);
2736         }
2737
2738         if(mask & ETH_VLAN_FILTER_MASK){
2739                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2740                         igb_vlan_hw_filter_enable(dev);
2741                 else
2742                         igb_vlan_hw_filter_disable(dev);
2743         }
2744
2745         if(mask & ETH_VLAN_EXTEND_MASK){
2746                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2747                         igb_vlan_hw_extend_enable(dev);
2748                 else
2749                         igb_vlan_hw_extend_disable(dev);
2750         }
2751
2752         return 0;
2753 }
2754
2755
2756 /**
2757  * It enables the interrupt mask and then enable the interrupt.
2758  *
2759  * @param dev
2760  *  Pointer to struct rte_eth_dev.
2761  * @param on
2762  *  Enable or Disable
2763  *
2764  * @return
2765  *  - On success, zero.
2766  *  - On failure, a negative value.
2767  */
2768 static int
2769 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2770 {
2771         struct e1000_interrupt *intr =
2772                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2773
2774         if (on)
2775                 intr->mask |= E1000_ICR_LSC;
2776         else
2777                 intr->mask &= ~E1000_ICR_LSC;
2778
2779         return 0;
2780 }
2781
2782 /* It clears the interrupt causes and enables the interrupt.
2783  * It will be called once only during nic initialized.
2784  *
2785  * @param dev
2786  *  Pointer to struct rte_eth_dev.
2787  *
2788  * @return
2789  *  - On success, zero.
2790  *  - On failure, a negative value.
2791  */
2792 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2793 {
2794         uint32_t mask, regval;
2795         int ret;
2796         struct e1000_hw *hw =
2797                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2798         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2799         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2800         int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2801         struct rte_eth_dev_info dev_info;
2802
2803         memset(&dev_info, 0, sizeof(dev_info));
2804         ret = eth_igb_infos_get(dev, &dev_info);
2805         if (ret != 0)
2806                 return ret;
2807
2808         mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2809         regval = E1000_READ_REG(hw, E1000_EIMS);
2810         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2811
2812         return 0;
2813 }
2814
2815 /*
2816  * It reads ICR and gets interrupt causes, check it and set a bit flag
2817  * to update link status.
2818  *
2819  * @param dev
2820  *  Pointer to struct rte_eth_dev.
2821  *
2822  * @return
2823  *  - On success, zero.
2824  *  - On failure, a negative value.
2825  */
2826 static int
2827 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2828 {
2829         uint32_t icr;
2830         struct e1000_hw *hw =
2831                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2832         struct e1000_interrupt *intr =
2833                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2834
2835         igb_intr_disable(dev);
2836
2837         /* read-on-clear nic registers here */
2838         icr = E1000_READ_REG(hw, E1000_ICR);
2839
2840         intr->flags = 0;
2841         if (icr & E1000_ICR_LSC) {
2842                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2843         }
2844
2845         if (icr & E1000_ICR_VMMB)
2846                 intr->flags |= E1000_FLAG_MAILBOX;
2847
2848         return 0;
2849 }
2850
2851 /*
2852  * It executes link_update after knowing an interrupt is prsent.
2853  *
2854  * @param dev
2855  *  Pointer to struct rte_eth_dev.
2856  *
2857  * @return
2858  *  - On success, zero.
2859  *  - On failure, a negative value.
2860  */
2861 static int
2862 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2863                          struct rte_intr_handle *intr_handle)
2864 {
2865         struct e1000_hw *hw =
2866                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2867         struct e1000_interrupt *intr =
2868                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2869         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2870         struct rte_eth_link link;
2871         int ret;
2872
2873         if (intr->flags & E1000_FLAG_MAILBOX) {
2874                 igb_pf_mbx_process(dev);
2875                 intr->flags &= ~E1000_FLAG_MAILBOX;
2876         }
2877
2878         igb_intr_enable(dev);
2879         rte_intr_ack(intr_handle);
2880
2881         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2882                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2883
2884                 /* set get_link_status to check register later */
2885                 hw->mac.get_link_status = 1;
2886                 ret = eth_igb_link_update(dev, 0);
2887
2888                 /* check if link has changed */
2889                 if (ret < 0)
2890                         return 0;
2891
2892                 rte_eth_linkstatus_get(dev, &link);
2893                 if (link.link_status) {
2894                         PMD_INIT_LOG(INFO,
2895                                      " Port %d: Link Up - speed %u Mbps - %s",
2896                                      dev->data->port_id,
2897                                      (unsigned)link.link_speed,
2898                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2899                                      "full-duplex" : "half-duplex");
2900                 } else {
2901                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2902                                      dev->data->port_id);
2903                 }
2904
2905                 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2906                              pci_dev->addr.domain,
2907                              pci_dev->addr.bus,
2908                              pci_dev->addr.devid,
2909                              pci_dev->addr.function);
2910                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2911         }
2912
2913         return 0;
2914 }
2915
2916 /**
2917  * Interrupt handler which shall be registered at first.
2918  *
2919  * @param handle
2920  *  Pointer to interrupt handle.
2921  * @param param
2922  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2923  *
2924  * @return
2925  *  void
2926  */
2927 static void
2928 eth_igb_interrupt_handler(void *param)
2929 {
2930         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2931
2932         eth_igb_interrupt_get_status(dev);
2933         eth_igb_interrupt_action(dev, dev->intr_handle);
2934 }
2935
2936 static int
2937 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2938 {
2939         uint32_t eicr;
2940         struct e1000_hw *hw =
2941                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2942         struct e1000_interrupt *intr =
2943                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2944
2945         igbvf_intr_disable(hw);
2946
2947         /* read-on-clear nic registers here */
2948         eicr = E1000_READ_REG(hw, E1000_EICR);
2949         intr->flags = 0;
2950
2951         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2952                 intr->flags |= E1000_FLAG_MAILBOX;
2953
2954         return 0;
2955 }
2956
2957 void igbvf_mbx_process(struct rte_eth_dev *dev)
2958 {
2959         struct e1000_hw *hw =
2960                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2961         struct e1000_mbx_info *mbx = &hw->mbx;
2962         u32 in_msg = 0;
2963
2964         /* peek the message first */
2965         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2966
2967         /* PF reset VF event */
2968         if (in_msg == E1000_PF_CONTROL_MSG) {
2969                 /* dummy mbx read to ack pf */
2970                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2971                         return;
2972                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2973                                              NULL);
2974         }
2975 }
2976
2977 static int
2978 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2979 {
2980         struct e1000_interrupt *intr =
2981                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2982
2983         if (intr->flags & E1000_FLAG_MAILBOX) {
2984                 igbvf_mbx_process(dev);
2985                 intr->flags &= ~E1000_FLAG_MAILBOX;
2986         }
2987
2988         igbvf_intr_enable(dev);
2989         rte_intr_ack(intr_handle);
2990
2991         return 0;
2992 }
2993
2994 static void
2995 eth_igbvf_interrupt_handler(void *param)
2996 {
2997         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2998
2999         eth_igbvf_interrupt_get_status(dev);
3000         eth_igbvf_interrupt_action(dev, dev->intr_handle);
3001 }
3002
3003 static int
3004 eth_igb_led_on(struct rte_eth_dev *dev)
3005 {
3006         struct e1000_hw *hw;
3007
3008         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3009         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3010 }
3011
3012 static int
3013 eth_igb_led_off(struct rte_eth_dev *dev)
3014 {
3015         struct e1000_hw *hw;
3016
3017         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3018         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3019 }
3020
3021 static int
3022 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3023 {
3024         struct e1000_hw *hw;
3025         uint32_t ctrl;
3026         int tx_pause;
3027         int rx_pause;
3028
3029         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3030         fc_conf->pause_time = hw->fc.pause_time;
3031         fc_conf->high_water = hw->fc.high_water;
3032         fc_conf->low_water = hw->fc.low_water;
3033         fc_conf->send_xon = hw->fc.send_xon;
3034         fc_conf->autoneg = hw->mac.autoneg;
3035
3036         /*
3037          * Return rx_pause and tx_pause status according to actual setting of
3038          * the TFCE and RFCE bits in the CTRL register.
3039          */
3040         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3041         if (ctrl & E1000_CTRL_TFCE)
3042                 tx_pause = 1;
3043         else
3044                 tx_pause = 0;
3045
3046         if (ctrl & E1000_CTRL_RFCE)
3047                 rx_pause = 1;
3048         else
3049                 rx_pause = 0;
3050
3051         if (rx_pause && tx_pause)
3052                 fc_conf->mode = RTE_FC_FULL;
3053         else if (rx_pause)
3054                 fc_conf->mode = RTE_FC_RX_PAUSE;
3055         else if (tx_pause)
3056                 fc_conf->mode = RTE_FC_TX_PAUSE;
3057         else
3058                 fc_conf->mode = RTE_FC_NONE;
3059
3060         return 0;
3061 }
3062
3063 static int
3064 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3065 {
3066         struct e1000_hw *hw;
3067         int err;
3068         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3069                 e1000_fc_none,
3070                 e1000_fc_rx_pause,
3071                 e1000_fc_tx_pause,
3072                 e1000_fc_full
3073         };
3074         uint32_t rx_buf_size;
3075         uint32_t max_high_water;
3076         uint32_t rctl;
3077
3078         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3079         if (fc_conf->autoneg != hw->mac.autoneg)
3080                 return -ENOTSUP;
3081         rx_buf_size = igb_get_rx_buffer_size(hw);
3082         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3083
3084         /* At least reserve one Ethernet frame for watermark */
3085         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3086         if ((fc_conf->high_water > max_high_water) ||
3087             (fc_conf->high_water < fc_conf->low_water)) {
3088                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3089                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3090                 return -EINVAL;
3091         }
3092
3093         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3094         hw->fc.pause_time     = fc_conf->pause_time;
3095         hw->fc.high_water     = fc_conf->high_water;
3096         hw->fc.low_water      = fc_conf->low_water;
3097         hw->fc.send_xon       = fc_conf->send_xon;
3098
3099         err = e1000_setup_link_generic(hw);
3100         if (err == E1000_SUCCESS) {
3101
3102                 /* check if we want to forward MAC frames - driver doesn't have native
3103                  * capability to do that, so we'll write the registers ourselves */
3104
3105                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3106
3107                 /* set or clear MFLCN.PMCF bit depending on configuration */
3108                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3109                         rctl |= E1000_RCTL_PMCF;
3110                 else
3111                         rctl &= ~E1000_RCTL_PMCF;
3112
3113                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3114                 E1000_WRITE_FLUSH(hw);
3115
3116                 return 0;
3117         }
3118
3119         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3120         return -EIO;
3121 }
3122
3123 #define E1000_RAH_POOLSEL_SHIFT      (18)
3124 static int
3125 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3126                 uint32_t index, uint32_t pool)
3127 {
3128         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3129         uint32_t rah;
3130
3131         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3132         rah = E1000_READ_REG(hw, E1000_RAH(index));
3133         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3134         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3135         return 0;
3136 }
3137
3138 static void
3139 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3140 {
3141         uint8_t addr[RTE_ETHER_ADDR_LEN];
3142         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3143
3144         memset(addr, 0, sizeof(addr));
3145
3146         e1000_rar_set(hw, addr, index);
3147 }
3148
3149 static int
3150 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3151                                 struct rte_ether_addr *addr)
3152 {
3153         eth_igb_rar_clear(dev, 0);
3154         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3155
3156         return 0;
3157 }
3158 /*
3159  * Virtual Function operations
3160  */
3161 static void
3162 igbvf_intr_disable(struct e1000_hw *hw)
3163 {
3164         PMD_INIT_FUNC_TRACE();
3165
3166         /* Clear interrupt mask to stop from interrupts being generated */
3167         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3168
3169         E1000_WRITE_FLUSH(hw);
3170 }
3171
3172 static void
3173 igbvf_stop_adapter(struct rte_eth_dev *dev)
3174 {
3175         u32 reg_val;
3176         u16 i;
3177         struct rte_eth_dev_info dev_info;
3178         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3179         int ret;
3180
3181         memset(&dev_info, 0, sizeof(dev_info));
3182         ret = eth_igbvf_infos_get(dev, &dev_info);
3183         if (ret != 0)
3184                 return;
3185
3186         /* Clear interrupt mask to stop from interrupts being generated */
3187         igbvf_intr_disable(hw);
3188
3189         /* Clear any pending interrupts, flush previous writes */
3190         E1000_READ_REG(hw, E1000_EICR);
3191
3192         /* Disable the transmit unit.  Each queue must be disabled. */
3193         for (i = 0; i < dev_info.max_tx_queues; i++)
3194                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3195
3196         /* Disable the receive unit by stopping each queue */
3197         for (i = 0; i < dev_info.max_rx_queues; i++) {
3198                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3199                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3200                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3201                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3202                         ;
3203         }
3204
3205         /* flush all queues disables */
3206         E1000_WRITE_FLUSH(hw);
3207         msec_delay(2);
3208 }
3209
3210 static int eth_igbvf_link_update(struct e1000_hw *hw)
3211 {
3212         struct e1000_mbx_info *mbx = &hw->mbx;
3213         struct e1000_mac_info *mac = &hw->mac;
3214         int ret_val = E1000_SUCCESS;
3215
3216         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3217
3218         /*
3219          * We only want to run this if there has been a rst asserted.
3220          * in this case that could mean a link change, device reset,
3221          * or a virtual function reset
3222          */
3223
3224         /* If we were hit with a reset or timeout drop the link */
3225         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3226                 mac->get_link_status = TRUE;
3227
3228         if (!mac->get_link_status)
3229                 goto out;
3230
3231         /* if link status is down no point in checking to see if pf is up */
3232         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3233                 goto out;
3234
3235         /* if we passed all the tests above then the link is up and we no
3236          * longer need to check for link */
3237         mac->get_link_status = FALSE;
3238
3239 out:
3240         return ret_val;
3241 }
3242
3243
3244 static int
3245 igbvf_dev_configure(struct rte_eth_dev *dev)
3246 {
3247         struct rte_eth_conf* conf = &dev->data->dev_conf;
3248
3249         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3250                      dev->data->port_id);
3251
3252         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3253                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3254
3255         /*
3256          * VF has no ability to enable/disable HW CRC
3257          * Keep the persistent behavior the same as Host PF
3258          */
3259 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3260         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3261                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3262                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3263         }
3264 #else
3265         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3266                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3267                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3268         }
3269 #endif
3270
3271         return 0;
3272 }
3273
3274 static int
3275 igbvf_dev_start(struct rte_eth_dev *dev)
3276 {
3277         struct e1000_hw *hw =
3278                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3279         struct e1000_adapter *adapter =
3280                 E1000_DEV_PRIVATE(dev->data->dev_private);
3281         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3282         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3283         int ret;
3284         uint32_t intr_vector = 0;
3285
3286         PMD_INIT_FUNC_TRACE();
3287
3288         hw->mac.ops.reset_hw(hw);
3289         adapter->stopped = 0;
3290
3291         /* Set all vfta */
3292         igbvf_set_vfta_all(dev,1);
3293
3294         eth_igbvf_tx_init(dev);
3295
3296         /* This can fail when allocating mbufs for descriptor rings */
3297         ret = eth_igbvf_rx_init(dev);
3298         if (ret) {
3299                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3300                 igb_dev_clear_queues(dev);
3301                 return ret;
3302         }
3303
3304         /* check and configure queue intr-vector mapping */
3305         if (rte_intr_cap_multiple(intr_handle) &&
3306             dev->data->dev_conf.intr_conf.rxq) {
3307                 intr_vector = dev->data->nb_rx_queues;
3308                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3309                 if (ret)
3310                         return ret;
3311         }
3312
3313         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3314                 intr_handle->intr_vec =
3315                         rte_zmalloc("intr_vec",
3316                                     dev->data->nb_rx_queues * sizeof(int), 0);
3317                 if (!intr_handle->intr_vec) {
3318                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3319                                      " intr_vec", dev->data->nb_rx_queues);
3320                         return -ENOMEM;
3321                 }
3322         }
3323
3324         eth_igbvf_configure_msix_intr(dev);
3325
3326         /* enable uio/vfio intr/eventfd mapping */
3327         rte_intr_enable(intr_handle);
3328
3329         /* resume enabled intr since hw reset */
3330         igbvf_intr_enable(dev);
3331
3332         return 0;
3333 }
3334
3335 static int
3336 igbvf_dev_stop(struct rte_eth_dev *dev)
3337 {
3338         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3339         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3340         struct e1000_adapter *adapter =
3341                 E1000_DEV_PRIVATE(dev->data->dev_private);
3342
3343         if (adapter->stopped)
3344                 return 0;
3345
3346         PMD_INIT_FUNC_TRACE();
3347
3348         igbvf_stop_adapter(dev);
3349
3350         /*
3351           * Clear what we set, but we still keep shadow_vfta to
3352           * restore after device starts
3353           */
3354         igbvf_set_vfta_all(dev,0);
3355
3356         igb_dev_clear_queues(dev);
3357
3358         /* disable intr eventfd mapping */
3359         rte_intr_disable(intr_handle);
3360
3361         /* Clean datapath event and queue/vec mapping */
3362         rte_intr_efd_disable(intr_handle);
3363         if (intr_handle->intr_vec) {
3364                 rte_free(intr_handle->intr_vec);
3365                 intr_handle->intr_vec = NULL;
3366         }
3367
3368         adapter->stopped = true;
3369         dev->data->dev_started = 0;
3370
3371         return 0;
3372 }
3373
3374 static int
3375 igbvf_dev_close(struct rte_eth_dev *dev)
3376 {
3377         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3378         struct rte_ether_addr addr;
3379         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3380         int ret;
3381
3382         PMD_INIT_FUNC_TRACE();
3383
3384         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3385                 return 0;
3386
3387         e1000_reset_hw(hw);
3388
3389         ret = igbvf_dev_stop(dev);
3390         if (ret != 0)
3391                 return ret;
3392
3393         igb_dev_free_queues(dev);
3394
3395         /**
3396          * reprogram the RAR with a zero mac address,
3397          * to ensure that the VF traffic goes to the PF
3398          * after stop, close and detach of the VF.
3399          **/
3400
3401         memset(&addr, 0, sizeof(addr));
3402         igbvf_default_mac_addr_set(dev, &addr);
3403
3404         rte_intr_callback_unregister(&pci_dev->intr_handle,
3405                                      eth_igbvf_interrupt_handler,
3406                                      (void *)dev);
3407
3408         return 0;
3409 }
3410
3411 static int
3412 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3413 {
3414         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3415
3416         /* Set both unicast and multicast promisc */
3417         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3418
3419         return 0;
3420 }
3421
3422 static int
3423 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3424 {
3425         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3426
3427         /* If in allmulticast mode leave multicast promisc */
3428         if (dev->data->all_multicast == 1)
3429                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3430         else
3431                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3432
3433         return 0;
3434 }
3435
3436 static int
3437 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3438 {
3439         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3440
3441         /* In promiscuous mode multicast promisc already set */
3442         if (dev->data->promiscuous == 0)
3443                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3444
3445         return 0;
3446 }
3447
3448 static int
3449 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3450 {
3451         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3452
3453         /* In promiscuous mode leave multicast promisc enabled */
3454         if (dev->data->promiscuous == 0)
3455                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3456
3457         return 0;
3458 }
3459
3460 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3461 {
3462         struct e1000_mbx_info *mbx = &hw->mbx;
3463         uint32_t msgbuf[2];
3464         s32 err;
3465
3466         /* After set vlan, vlan strip will also be enabled in igb driver*/
3467         msgbuf[0] = E1000_VF_SET_VLAN;
3468         msgbuf[1] = vid;
3469         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3470         if (on)
3471                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3472
3473         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3474         if (err)
3475                 goto mbx_err;
3476
3477         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3478         if (err)
3479                 goto mbx_err;
3480
3481         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3482         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3483                 err = -EINVAL;
3484
3485 mbx_err:
3486         return err;
3487 }
3488
3489 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3490 {
3491         struct e1000_hw *hw =
3492                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3493         struct e1000_vfta * shadow_vfta =
3494                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3495         int i = 0, j = 0, vfta = 0, mask = 1;
3496
3497         for (i = 0; i < IGB_VFTA_SIZE; i++){
3498                 vfta = shadow_vfta->vfta[i];
3499                 if(vfta){
3500                         mask = 1;
3501                         for (j = 0; j < 32; j++){
3502                                 if(vfta & mask)
3503                                         igbvf_set_vfta(hw,
3504                                                 (uint16_t)((i<<5)+j), on);
3505                                 mask<<=1;
3506                         }
3507                 }
3508         }
3509
3510 }
3511
3512 static int
3513 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3514 {
3515         struct e1000_hw *hw =
3516                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3517         struct e1000_vfta * shadow_vfta =
3518                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3519         uint32_t vid_idx = 0;
3520         uint32_t vid_bit = 0;
3521         int ret = 0;
3522
3523         PMD_INIT_FUNC_TRACE();
3524
3525         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3526         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3527         if(ret){
3528                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3529                 return ret;
3530         }
3531         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3532         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3533
3534         /*Save what we set and retore it after device reset*/
3535         if (on)
3536                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3537         else
3538                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3539
3540         return 0;
3541 }
3542
3543 static int
3544 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3545 {
3546         struct e1000_hw *hw =
3547                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3548
3549         /* index is not used by rar_set() */
3550         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3551         return 0;
3552 }
3553
3554
3555 static int
3556 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3557                         struct rte_eth_rss_reta_entry64 *reta_conf,
3558                         uint16_t reta_size)
3559 {
3560         uint8_t i, j, mask;
3561         uint32_t reta, r;
3562         uint16_t idx, shift;
3563         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3564
3565         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3566                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3567                         "(%d) doesn't match the number hardware can supported "
3568                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3569                 return -EINVAL;
3570         }
3571
3572         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3573                 idx = i / RTE_RETA_GROUP_SIZE;
3574                 shift = i % RTE_RETA_GROUP_SIZE;
3575                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3576                                                 IGB_4_BIT_MASK);
3577                 if (!mask)
3578                         continue;
3579                 if (mask == IGB_4_BIT_MASK)
3580                         r = 0;
3581                 else
3582                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3583                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3584                         if (mask & (0x1 << j))
3585                                 reta |= reta_conf[idx].reta[shift + j] <<
3586                                                         (CHAR_BIT * j);
3587                         else
3588                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3589                 }
3590                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3591         }
3592
3593         return 0;
3594 }
3595
3596 static int
3597 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3598                        struct rte_eth_rss_reta_entry64 *reta_conf,
3599                        uint16_t reta_size)
3600 {
3601         uint8_t i, j, mask;
3602         uint32_t reta;
3603         uint16_t idx, shift;
3604         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3605
3606         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3607                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3608                         "(%d) doesn't match the number hardware can supported "
3609                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3610                 return -EINVAL;
3611         }
3612
3613         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3614                 idx = i / RTE_RETA_GROUP_SIZE;
3615                 shift = i % RTE_RETA_GROUP_SIZE;
3616                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3617                                                 IGB_4_BIT_MASK);
3618                 if (!mask)
3619                         continue;
3620                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3621                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3622                         if (mask & (0x1 << j))
3623                                 reta_conf[idx].reta[shift + j] =
3624                                         ((reta >> (CHAR_BIT * j)) &
3625                                                 IGB_8_BIT_MASK);
3626                 }
3627         }
3628
3629         return 0;
3630 }
3631
3632 int
3633 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3634                         struct rte_eth_syn_filter *filter,
3635                         bool add)
3636 {
3637         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3638         struct e1000_filter_info *filter_info =
3639                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3640         uint32_t synqf, rfctl;
3641
3642         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3643                 return -EINVAL;
3644
3645         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3646
3647         if (add) {
3648                 if (synqf & E1000_SYN_FILTER_ENABLE)
3649                         return -EINVAL;
3650
3651                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3652                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3653
3654                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3655                 if (filter->hig_pri)
3656                         rfctl |= E1000_RFCTL_SYNQFP;
3657                 else
3658                         rfctl &= ~E1000_RFCTL_SYNQFP;
3659
3660                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3661         } else {
3662                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3663                         return -ENOENT;
3664                 synqf = 0;
3665         }
3666
3667         filter_info->syn_info = synqf;
3668         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3669         E1000_WRITE_FLUSH(hw);
3670         return 0;
3671 }
3672
3673 static int
3674 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3675                         struct rte_eth_syn_filter *filter)
3676 {
3677         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3678         uint32_t synqf, rfctl;
3679
3680         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3681         if (synqf & E1000_SYN_FILTER_ENABLE) {
3682                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3683                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3684                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3685                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3686                 return 0;
3687         }
3688
3689         return -ENOENT;
3690 }
3691
3692 static int
3693 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3694                         enum rte_filter_op filter_op,
3695                         void *arg)
3696 {
3697         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3698         int ret;
3699
3700         MAC_TYPE_FILTER_SUP(hw->mac.type);
3701
3702         if (filter_op == RTE_ETH_FILTER_NOP)
3703                 return 0;
3704
3705         if (arg == NULL) {
3706                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3707                             filter_op);
3708                 return -EINVAL;
3709         }
3710
3711         switch (filter_op) {
3712         case RTE_ETH_FILTER_ADD:
3713                 ret = eth_igb_syn_filter_set(dev,
3714                                 (struct rte_eth_syn_filter *)arg,
3715                                 TRUE);
3716                 break;
3717         case RTE_ETH_FILTER_DELETE:
3718                 ret = eth_igb_syn_filter_set(dev,
3719                                 (struct rte_eth_syn_filter *)arg,
3720                                 FALSE);
3721                 break;
3722         case RTE_ETH_FILTER_GET:
3723                 ret = eth_igb_syn_filter_get(dev,
3724                                 (struct rte_eth_syn_filter *)arg);
3725                 break;
3726         default:
3727                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3728                 ret = -EINVAL;
3729                 break;
3730         }
3731
3732         return ret;
3733 }
3734
3735 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3736 static inline int
3737 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3738                         struct e1000_2tuple_filter_info *filter_info)
3739 {
3740         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3741                 return -EINVAL;
3742         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3743                 return -EINVAL;  /* filter index is out of range. */
3744         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3745                 return -EINVAL;  /* flags is invalid. */
3746
3747         switch (filter->dst_port_mask) {
3748         case UINT16_MAX:
3749                 filter_info->dst_port_mask = 0;
3750                 filter_info->dst_port = filter->dst_port;
3751                 break;
3752         case 0:
3753                 filter_info->dst_port_mask = 1;
3754                 break;
3755         default:
3756                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3757                 return -EINVAL;
3758         }
3759
3760         switch (filter->proto_mask) {
3761         case UINT8_MAX:
3762                 filter_info->proto_mask = 0;
3763                 filter_info->proto = filter->proto;
3764                 break;
3765         case 0:
3766                 filter_info->proto_mask = 1;
3767                 break;
3768         default:
3769                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3770                 return -EINVAL;
3771         }
3772
3773         filter_info->priority = (uint8_t)filter->priority;
3774         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3775                 filter_info->tcp_flags = filter->tcp_flags;
3776         else
3777                 filter_info->tcp_flags = 0;
3778
3779         return 0;
3780 }
3781
3782 static inline struct e1000_2tuple_filter *
3783 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3784                         struct e1000_2tuple_filter_info *key)
3785 {
3786         struct e1000_2tuple_filter *it;
3787
3788         TAILQ_FOREACH(it, filter_list, entries) {
3789                 if (memcmp(key, &it->filter_info,
3790                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3791                         return it;
3792                 }
3793         }
3794         return NULL;
3795 }
3796
3797 /* inject a igb 2tuple filter to HW */
3798 static inline void
3799 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3800                            struct e1000_2tuple_filter *filter)
3801 {
3802         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3803         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3804         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3805         int i;
3806
3807         i = filter->index;
3808         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3809         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3810                 imir |= E1000_IMIR_PORT_BP;
3811         else
3812                 imir &= ~E1000_IMIR_PORT_BP;
3813
3814         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3815
3816         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3817         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3818         ttqf |= (uint32_t)(filter->filter_info.proto &
3819                                                 E1000_TTQF_PROTOCOL_MASK);
3820         if (filter->filter_info.proto_mask == 0)
3821                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3822
3823         /* tcp flags bits setting. */
3824         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3825                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3826                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3827                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3828                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3829                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3830                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3831                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3832                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3833                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3834                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3835                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3836                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3837         } else {
3838                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3839         }
3840         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3841         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3842         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3843 }
3844
3845 /*
3846  * igb_add_2tuple_filter - add a 2tuple filter
3847  *
3848  * @param
3849  * dev: Pointer to struct rte_eth_dev.
3850  * ntuple_filter: ponter to the filter that will be added.
3851  *
3852  * @return
3853  *    - On success, zero.
3854  *    - On failure, a negative value.
3855  */
3856 static int
3857 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3858                         struct rte_eth_ntuple_filter *ntuple_filter)
3859 {
3860         struct e1000_filter_info *filter_info =
3861                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3862         struct e1000_2tuple_filter *filter;
3863         int i, ret;
3864
3865         filter = rte_zmalloc("e1000_2tuple_filter",
3866                         sizeof(struct e1000_2tuple_filter), 0);
3867         if (filter == NULL)
3868                 return -ENOMEM;
3869
3870         ret = ntuple_filter_to_2tuple(ntuple_filter,
3871                                       &filter->filter_info);
3872         if (ret < 0) {
3873                 rte_free(filter);
3874                 return ret;
3875         }
3876         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3877                                          &filter->filter_info) != NULL) {
3878                 PMD_DRV_LOG(ERR, "filter exists.");
3879                 rte_free(filter);
3880                 return -EEXIST;
3881         }
3882         filter->queue = ntuple_filter->queue;
3883
3884         /*
3885          * look for an unused 2tuple filter index,
3886          * and insert the filter to list.
3887          */
3888         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3889                 if (!(filter_info->twotuple_mask & (1 << i))) {
3890                         filter_info->twotuple_mask |= 1 << i;
3891                         filter->index = i;
3892                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3893                                           filter,
3894                                           entries);
3895                         break;
3896                 }
3897         }
3898         if (i >= E1000_MAX_TTQF_FILTERS) {
3899                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3900                 rte_free(filter);
3901                 return -ENOSYS;
3902         }
3903
3904         igb_inject_2uple_filter(dev, filter);
3905         return 0;
3906 }
3907
3908 int
3909 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3910                         struct e1000_2tuple_filter *filter)
3911 {
3912         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3913         struct e1000_filter_info *filter_info =
3914                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3915
3916         filter_info->twotuple_mask &= ~(1 << filter->index);
3917         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3918         rte_free(filter);
3919
3920         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3921         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3922         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3923         return 0;
3924 }
3925
3926 /*
3927  * igb_remove_2tuple_filter - remove a 2tuple filter
3928  *
3929  * @param
3930  * dev: Pointer to struct rte_eth_dev.
3931  * ntuple_filter: ponter to the filter that will be removed.
3932  *
3933  * @return
3934  *    - On success, zero.
3935  *    - On failure, a negative value.
3936  */
3937 static int
3938 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3939                         struct rte_eth_ntuple_filter *ntuple_filter)
3940 {
3941         struct e1000_filter_info *filter_info =
3942                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3943         struct e1000_2tuple_filter_info filter_2tuple;
3944         struct e1000_2tuple_filter *filter;
3945         int ret;
3946
3947         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3948         ret = ntuple_filter_to_2tuple(ntuple_filter,
3949                                       &filter_2tuple);
3950         if (ret < 0)
3951                 return ret;
3952
3953         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3954                                          &filter_2tuple);
3955         if (filter == NULL) {
3956                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3957                 return -ENOENT;
3958         }
3959
3960         igb_delete_2tuple_filter(dev, filter);
3961
3962         return 0;
3963 }
3964
3965 /* inject a igb flex filter to HW */
3966 static inline void
3967 igb_inject_flex_filter(struct rte_eth_dev *dev,
3968                            struct e1000_flex_filter *filter)
3969 {
3970         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3971         uint32_t wufc, queueing;
3972         uint32_t reg_off;
3973         uint8_t i, j = 0;
3974
3975         wufc = E1000_READ_REG(hw, E1000_WUFC);
3976         if (filter->index < E1000_MAX_FHFT)
3977                 reg_off = E1000_FHFT(filter->index);
3978         else
3979                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3980
3981         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3982                         (E1000_WUFC_FLX0 << filter->index));
3983         queueing = filter->filter_info.len |
3984                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3985                 (filter->filter_info.priority <<
3986                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3987         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3988                         queueing);
3989
3990         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3991                 E1000_WRITE_REG(hw, reg_off,
3992                                 filter->filter_info.dwords[j]);
3993                 reg_off += sizeof(uint32_t);
3994                 E1000_WRITE_REG(hw, reg_off,
3995                                 filter->filter_info.dwords[++j]);
3996                 reg_off += sizeof(uint32_t);
3997                 E1000_WRITE_REG(hw, reg_off,
3998                         (uint32_t)filter->filter_info.mask[i]);
3999                 reg_off += sizeof(uint32_t) * 2;
4000                 ++j;
4001         }
4002 }
4003
4004 static inline struct e1000_flex_filter *
4005 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
4006                         struct e1000_flex_filter_info *key)
4007 {
4008         struct e1000_flex_filter *it;
4009
4010         TAILQ_FOREACH(it, filter_list, entries) {
4011                 if (memcmp(key, &it->filter_info,
4012                         sizeof(struct e1000_flex_filter_info)) == 0)
4013                         return it;
4014         }
4015
4016         return NULL;
4017 }
4018
4019 /* remove a flex byte filter
4020  * @param
4021  * dev: Pointer to struct rte_eth_dev.
4022  * filter: the pointer of the filter will be removed.
4023  */
4024 void
4025 igb_remove_flex_filter(struct rte_eth_dev *dev,
4026                         struct e1000_flex_filter *filter)
4027 {
4028         struct e1000_filter_info *filter_info =
4029                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4030         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4031         uint32_t wufc, i;
4032         uint32_t reg_off;
4033
4034         wufc = E1000_READ_REG(hw, E1000_WUFC);
4035         if (filter->index < E1000_MAX_FHFT)
4036                 reg_off = E1000_FHFT(filter->index);
4037         else
4038                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4039
4040         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4041                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4042
4043         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4044                 (~(E1000_WUFC_FLX0 << filter->index)));
4045
4046         filter_info->flex_mask &= ~(1 << filter->index);
4047         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4048         rte_free(filter);
4049 }
4050
4051 int
4052 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4053                         struct rte_eth_flex_filter *filter,
4054                         bool add)
4055 {
4056         struct e1000_filter_info *filter_info =
4057                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4058         struct e1000_flex_filter *flex_filter, *it;
4059         uint32_t mask;
4060         uint8_t shift, i;
4061
4062         flex_filter = rte_zmalloc("e1000_flex_filter",
4063                         sizeof(struct e1000_flex_filter), 0);
4064         if (flex_filter == NULL)
4065                 return -ENOMEM;
4066
4067         flex_filter->filter_info.len = filter->len;
4068         flex_filter->filter_info.priority = filter->priority;
4069         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4070         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4071                 mask = 0;
4072                 /* reverse bits in flex filter's mask*/
4073                 for (shift = 0; shift < CHAR_BIT; shift++) {
4074                         if (filter->mask[i] & (0x01 << shift))
4075                                 mask |= (0x80 >> shift);
4076                 }
4077                 flex_filter->filter_info.mask[i] = mask;
4078         }
4079
4080         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4081                                 &flex_filter->filter_info);
4082         if (it == NULL && !add) {
4083                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4084                 rte_free(flex_filter);
4085                 return -ENOENT;
4086         }
4087         if (it != NULL && add) {
4088                 PMD_DRV_LOG(ERR, "filter exists.");
4089                 rte_free(flex_filter);
4090                 return -EEXIST;
4091         }
4092
4093         if (add) {
4094                 flex_filter->queue = filter->queue;
4095                 /*
4096                  * look for an unused flex filter index
4097                  * and insert the filter into the list.
4098                  */
4099                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4100                         if (!(filter_info->flex_mask & (1 << i))) {
4101                                 filter_info->flex_mask |= 1 << i;
4102                                 flex_filter->index = i;
4103                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4104                                         flex_filter,
4105                                         entries);
4106                                 break;
4107                         }
4108                 }
4109                 if (i >= E1000_MAX_FLEX_FILTERS) {
4110                         PMD_DRV_LOG(ERR, "flex filters are full.");
4111                         rte_free(flex_filter);
4112                         return -ENOSYS;
4113                 }
4114
4115                 igb_inject_flex_filter(dev, flex_filter);
4116
4117         } else {
4118                 igb_remove_flex_filter(dev, it);
4119                 rte_free(flex_filter);
4120         }
4121
4122         return 0;
4123 }
4124
4125 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4126 static inline int
4127 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4128                         struct e1000_5tuple_filter_info *filter_info)
4129 {
4130         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4131                 return -EINVAL;
4132         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4133                 return -EINVAL;  /* filter index is out of range. */
4134         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4135                 return -EINVAL;  /* flags is invalid. */
4136
4137         switch (filter->dst_ip_mask) {
4138         case UINT32_MAX:
4139                 filter_info->dst_ip_mask = 0;
4140                 filter_info->dst_ip = filter->dst_ip;
4141                 break;
4142         case 0:
4143                 filter_info->dst_ip_mask = 1;
4144                 break;
4145         default:
4146                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4147                 return -EINVAL;
4148         }
4149
4150         switch (filter->src_ip_mask) {
4151         case UINT32_MAX:
4152                 filter_info->src_ip_mask = 0;
4153                 filter_info->src_ip = filter->src_ip;
4154                 break;
4155         case 0:
4156                 filter_info->src_ip_mask = 1;
4157                 break;
4158         default:
4159                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4160                 return -EINVAL;
4161         }
4162
4163         switch (filter->dst_port_mask) {
4164         case UINT16_MAX:
4165                 filter_info->dst_port_mask = 0;
4166                 filter_info->dst_port = filter->dst_port;
4167                 break;
4168         case 0:
4169                 filter_info->dst_port_mask = 1;
4170                 break;
4171         default:
4172                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4173                 return -EINVAL;
4174         }
4175
4176         switch (filter->src_port_mask) {
4177         case UINT16_MAX:
4178                 filter_info->src_port_mask = 0;
4179                 filter_info->src_port = filter->src_port;
4180                 break;
4181         case 0:
4182                 filter_info->src_port_mask = 1;
4183                 break;
4184         default:
4185                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4186                 return -EINVAL;
4187         }
4188
4189         switch (filter->proto_mask) {
4190         case UINT8_MAX:
4191                 filter_info->proto_mask = 0;
4192                 filter_info->proto = filter->proto;
4193                 break;
4194         case 0:
4195                 filter_info->proto_mask = 1;
4196                 break;
4197         default:
4198                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4199                 return -EINVAL;
4200         }
4201
4202         filter_info->priority = (uint8_t)filter->priority;
4203         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4204                 filter_info->tcp_flags = filter->tcp_flags;
4205         else
4206                 filter_info->tcp_flags = 0;
4207
4208         return 0;
4209 }
4210
4211 static inline struct e1000_5tuple_filter *
4212 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4213                         struct e1000_5tuple_filter_info *key)
4214 {
4215         struct e1000_5tuple_filter *it;
4216
4217         TAILQ_FOREACH(it, filter_list, entries) {
4218                 if (memcmp(key, &it->filter_info,
4219                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4220                         return it;
4221                 }
4222         }
4223         return NULL;
4224 }
4225
4226 /* inject a igb 5-tuple filter to HW */
4227 static inline void
4228 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4229                            struct e1000_5tuple_filter *filter)
4230 {
4231         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4232         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4233         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4234         uint8_t i;
4235
4236         i = filter->index;
4237         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4238         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4239                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4240         if (filter->filter_info.dst_ip_mask == 0)
4241                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4242         if (filter->filter_info.src_port_mask == 0)
4243                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4244         if (filter->filter_info.proto_mask == 0)
4245                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4246         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4247                 E1000_FTQF_QUEUE_MASK;
4248         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4249         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4250         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4251         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4252
4253         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4254         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4255
4256         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4257         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4258                 imir |= E1000_IMIR_PORT_BP;
4259         else
4260                 imir &= ~E1000_IMIR_PORT_BP;
4261         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4262
4263         /* tcp flags bits setting. */
4264         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4265                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4266                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4267                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4268                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4269                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4270                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4271                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4272                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4273                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4274                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4275                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4276                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4277         } else {
4278                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4279         }
4280         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4281         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4282 }
4283
4284 /*
4285  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4286  *
4287  * @param
4288  * dev: Pointer to struct rte_eth_dev.
4289  * ntuple_filter: ponter to the filter that will be added.
4290  *
4291  * @return
4292  *    - On success, zero.
4293  *    - On failure, a negative value.
4294  */
4295 static int
4296 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4297                         struct rte_eth_ntuple_filter *ntuple_filter)
4298 {
4299         struct e1000_filter_info *filter_info =
4300                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4301         struct e1000_5tuple_filter *filter;
4302         uint8_t i;
4303         int ret;
4304
4305         filter = rte_zmalloc("e1000_5tuple_filter",
4306                         sizeof(struct e1000_5tuple_filter), 0);
4307         if (filter == NULL)
4308                 return -ENOMEM;
4309
4310         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4311                                             &filter->filter_info);
4312         if (ret < 0) {
4313                 rte_free(filter);
4314                 return ret;
4315         }
4316
4317         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4318                                          &filter->filter_info) != NULL) {
4319                 PMD_DRV_LOG(ERR, "filter exists.");
4320                 rte_free(filter);
4321                 return -EEXIST;
4322         }
4323         filter->queue = ntuple_filter->queue;
4324
4325         /*
4326          * look for an unused 5tuple filter index,
4327          * and insert the filter to list.
4328          */
4329         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4330                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4331                         filter_info->fivetuple_mask |= 1 << i;
4332                         filter->index = i;
4333                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4334                                           filter,
4335                                           entries);
4336                         break;
4337                 }
4338         }
4339         if (i >= E1000_MAX_FTQF_FILTERS) {
4340                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4341                 rte_free(filter);
4342                 return -ENOSYS;
4343         }
4344
4345         igb_inject_5tuple_filter_82576(dev, filter);
4346         return 0;
4347 }
4348
4349 int
4350 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4351                                 struct e1000_5tuple_filter *filter)
4352 {
4353         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4354         struct e1000_filter_info *filter_info =
4355                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4356
4357         filter_info->fivetuple_mask &= ~(1 << filter->index);
4358         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4359         rte_free(filter);
4360
4361         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4362                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4363         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4364         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4365         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4366         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4367         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4368         return 0;
4369 }
4370
4371 /*
4372  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4373  *
4374  * @param
4375  * dev: Pointer to struct rte_eth_dev.
4376  * ntuple_filter: ponter to the filter that will be removed.
4377  *
4378  * @return
4379  *    - On success, zero.
4380  *    - On failure, a negative value.
4381  */
4382 static int
4383 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4384                                 struct rte_eth_ntuple_filter *ntuple_filter)
4385 {
4386         struct e1000_filter_info *filter_info =
4387                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4388         struct e1000_5tuple_filter_info filter_5tuple;
4389         struct e1000_5tuple_filter *filter;
4390         int ret;
4391
4392         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4393         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4394                                             &filter_5tuple);
4395         if (ret < 0)
4396                 return ret;
4397
4398         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4399                                          &filter_5tuple);
4400         if (filter == NULL) {
4401                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4402                 return -ENOENT;
4403         }
4404
4405         igb_delete_5tuple_filter_82576(dev, filter);
4406
4407         return 0;
4408 }
4409
4410 static int
4411 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4412 {
4413         uint32_t rctl;
4414         struct e1000_hw *hw;
4415         struct rte_eth_dev_info dev_info;
4416         uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4417         int ret;
4418
4419         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4420
4421 #ifdef RTE_LIBRTE_82571_SUPPORT
4422         /* XXX: not bigger than max_rx_pktlen */
4423         if (hw->mac.type == e1000_82571)
4424                 return -ENOTSUP;
4425 #endif
4426         ret = eth_igb_infos_get(dev, &dev_info);
4427         if (ret != 0)
4428                 return ret;
4429
4430         /* check that mtu is within the allowed range */
4431         if (mtu < RTE_ETHER_MIN_MTU ||
4432                         frame_size > dev_info.max_rx_pktlen)
4433                 return -EINVAL;
4434
4435         /* refuse mtu that requires the support of scattered packets when this
4436          * feature has not been enabled before. */
4437         if (!dev->data->scattered_rx &&
4438             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4439                 return -EINVAL;
4440
4441         rctl = E1000_READ_REG(hw, E1000_RCTL);
4442
4443         /* switch to jumbo mode if needed */
4444         if (frame_size > RTE_ETHER_MAX_LEN) {
4445                 dev->data->dev_conf.rxmode.offloads |=
4446                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4447                 rctl |= E1000_RCTL_LPE;
4448         } else {
4449                 dev->data->dev_conf.rxmode.offloads &=
4450                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4451                 rctl &= ~E1000_RCTL_LPE;
4452         }
4453         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4454
4455         /* update max frame size */
4456         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4457
4458         E1000_WRITE_REG(hw, E1000_RLPML,
4459                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4460
4461         return 0;
4462 }
4463
4464 /*
4465  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4466  *
4467  * @param
4468  * dev: Pointer to struct rte_eth_dev.
4469  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4470  * add: if true, add filter, if false, remove filter
4471  *
4472  * @return
4473  *    - On success, zero.
4474  *    - On failure, a negative value.
4475  */
4476 int
4477 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4478                         struct rte_eth_ntuple_filter *ntuple_filter,
4479                         bool add)
4480 {
4481         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4482         int ret;
4483
4484         switch (ntuple_filter->flags) {
4485         case RTE_5TUPLE_FLAGS:
4486         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4487                 if (hw->mac.type != e1000_82576)
4488                         return -ENOTSUP;
4489                 if (add)
4490                         ret = igb_add_5tuple_filter_82576(dev,
4491                                                           ntuple_filter);
4492                 else
4493                         ret = igb_remove_5tuple_filter_82576(dev,
4494                                                              ntuple_filter);
4495                 break;
4496         case RTE_2TUPLE_FLAGS:
4497         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4498                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4499                         hw->mac.type != e1000_i210 &&
4500                         hw->mac.type != e1000_i211)
4501                         return -ENOTSUP;
4502                 if (add)
4503                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4504                 else
4505                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4506                 break;
4507         default:
4508                 ret = -EINVAL;
4509                 break;
4510         }
4511
4512         return ret;
4513 }
4514
4515 /*
4516  * igb_get_ntuple_filter - get a ntuple filter
4517  *
4518  * @param
4519  * dev: Pointer to struct rte_eth_dev.
4520  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4521  *
4522  * @return
4523  *    - On success, zero.
4524  *    - On failure, a negative value.
4525  */
4526 static int
4527 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4528                         struct rte_eth_ntuple_filter *ntuple_filter)
4529 {
4530         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4531         struct e1000_filter_info *filter_info =
4532                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4533         struct e1000_5tuple_filter_info filter_5tuple;
4534         struct e1000_2tuple_filter_info filter_2tuple;
4535         struct e1000_5tuple_filter *p_5tuple_filter;
4536         struct e1000_2tuple_filter *p_2tuple_filter;
4537         int ret;
4538
4539         switch (ntuple_filter->flags) {
4540         case RTE_5TUPLE_FLAGS:
4541         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4542                 if (hw->mac.type != e1000_82576)
4543                         return -ENOTSUP;
4544                 memset(&filter_5tuple,
4545                         0,
4546                         sizeof(struct e1000_5tuple_filter_info));
4547                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4548                                                     &filter_5tuple);
4549                 if (ret < 0)
4550                         return ret;
4551                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4552                                         &filter_info->fivetuple_list,
4553                                         &filter_5tuple);
4554                 if (p_5tuple_filter == NULL) {
4555                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4556                         return -ENOENT;
4557                 }
4558                 ntuple_filter->queue = p_5tuple_filter->queue;
4559                 break;
4560         case RTE_2TUPLE_FLAGS:
4561         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4562                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4563                         return -ENOTSUP;
4564                 memset(&filter_2tuple,
4565                         0,
4566                         sizeof(struct e1000_2tuple_filter_info));
4567                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4568                 if (ret < 0)
4569                         return ret;
4570                 p_2tuple_filter = igb_2tuple_filter_lookup(
4571                                         &filter_info->twotuple_list,
4572                                         &filter_2tuple);
4573                 if (p_2tuple_filter == NULL) {
4574                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4575                         return -ENOENT;
4576                 }
4577                 ntuple_filter->queue = p_2tuple_filter->queue;
4578                 break;
4579         default:
4580                 ret = -EINVAL;
4581                 break;
4582         }
4583
4584         return 0;
4585 }
4586
4587 /*
4588  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4589  * @dev: pointer to rte_eth_dev structure
4590  * @filter_op:operation will be taken.
4591  * @arg: a pointer to specific structure corresponding to the filter_op
4592  */
4593 static int
4594 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4595                                 enum rte_filter_op filter_op,
4596                                 void *arg)
4597 {
4598         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4599         int ret;
4600
4601         MAC_TYPE_FILTER_SUP(hw->mac.type);
4602
4603         if (filter_op == RTE_ETH_FILTER_NOP)
4604                 return 0;
4605
4606         if (arg == NULL) {
4607                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4608                             filter_op);
4609                 return -EINVAL;
4610         }
4611
4612         switch (filter_op) {
4613         case RTE_ETH_FILTER_ADD:
4614                 ret = igb_add_del_ntuple_filter(dev,
4615                         (struct rte_eth_ntuple_filter *)arg,
4616                         TRUE);
4617                 break;
4618         case RTE_ETH_FILTER_DELETE:
4619                 ret = igb_add_del_ntuple_filter(dev,
4620                         (struct rte_eth_ntuple_filter *)arg,
4621                         FALSE);
4622                 break;
4623         case RTE_ETH_FILTER_GET:
4624                 ret = igb_get_ntuple_filter(dev,
4625                         (struct rte_eth_ntuple_filter *)arg);
4626                 break;
4627         default:
4628                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4629                 ret = -EINVAL;
4630                 break;
4631         }
4632         return ret;
4633 }
4634
4635 static inline int
4636 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4637                         uint16_t ethertype)
4638 {
4639         int i;
4640
4641         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4642                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4643                     (filter_info->ethertype_mask & (1 << i)))
4644                         return i;
4645         }
4646         return -1;
4647 }
4648
4649 static inline int
4650 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4651                         uint16_t ethertype, uint32_t etqf)
4652 {
4653         int i;
4654
4655         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4656                 if (!(filter_info->ethertype_mask & (1 << i))) {
4657                         filter_info->ethertype_mask |= 1 << i;
4658                         filter_info->ethertype_filters[i].ethertype = ethertype;
4659                         filter_info->ethertype_filters[i].etqf = etqf;
4660                         return i;
4661                 }
4662         }
4663         return -1;
4664 }
4665
4666 int
4667 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4668                         uint8_t idx)
4669 {
4670         if (idx >= E1000_MAX_ETQF_FILTERS)
4671                 return -1;
4672         filter_info->ethertype_mask &= ~(1 << idx);
4673         filter_info->ethertype_filters[idx].ethertype = 0;
4674         filter_info->ethertype_filters[idx].etqf = 0;
4675         return idx;
4676 }
4677
4678
4679 int
4680 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4681                         struct rte_eth_ethertype_filter *filter,
4682                         bool add)
4683 {
4684         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4685         struct e1000_filter_info *filter_info =
4686                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4687         uint32_t etqf = 0;
4688         int ret;
4689
4690         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4691                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4692                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4693                         " ethertype filter.", filter->ether_type);
4694                 return -EINVAL;
4695         }
4696
4697         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4698                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4699                 return -EINVAL;
4700         }
4701         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4702                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4703                 return -EINVAL;
4704         }
4705
4706         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4707         if (ret >= 0 && add) {
4708                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4709                             filter->ether_type);
4710                 return -EEXIST;
4711         }
4712         if (ret < 0 && !add) {
4713                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4714                             filter->ether_type);
4715                 return -ENOENT;
4716         }
4717
4718         if (add) {
4719                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4720                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4721                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4722                 ret = igb_ethertype_filter_insert(filter_info,
4723                                 filter->ether_type, etqf);
4724                 if (ret < 0) {
4725                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4726                         return -ENOSYS;
4727                 }
4728         } else {
4729                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4730                 if (ret < 0)
4731                         return -ENOSYS;
4732         }
4733         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4734         E1000_WRITE_FLUSH(hw);
4735
4736         return 0;
4737 }
4738
4739 static int
4740 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4741                      enum rte_filter_type filter_type,
4742                      enum rte_filter_op filter_op,
4743                      void *arg)
4744 {
4745         int ret = 0;
4746
4747         switch (filter_type) {
4748         case RTE_ETH_FILTER_NTUPLE:
4749                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4750                 break;
4751         case RTE_ETH_FILTER_SYN:
4752                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4753                 break;
4754         case RTE_ETH_FILTER_GENERIC:
4755                 if (filter_op != RTE_ETH_FILTER_GET)
4756                         return -EINVAL;
4757                 *(const void **)arg = &igb_flow_ops;
4758                 break;
4759         default:
4760                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4761                                                         filter_type);
4762                 break;
4763         }
4764
4765         return ret;
4766 }
4767
4768 static int
4769 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4770                          struct rte_ether_addr *mc_addr_set,
4771                          uint32_t nb_mc_addr)
4772 {
4773         struct e1000_hw *hw;
4774
4775         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4776         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4777         return 0;
4778 }
4779
4780 static uint64_t
4781 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4782 {
4783         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4784         uint64_t systime_cycles;
4785
4786         switch (hw->mac.type) {
4787         case e1000_i210:
4788         case e1000_i211:
4789                 /*
4790                  * Need to read System Time Residue Register to be able
4791                  * to read the other two registers.
4792                  */
4793                 E1000_READ_REG(hw, E1000_SYSTIMR);
4794                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4795                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4796                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4797                                 * NSEC_PER_SEC;
4798                 break;
4799         case e1000_82580:
4800         case e1000_i350:
4801         case e1000_i354:
4802                 /*
4803                  * Need to read System Time Residue Register to be able
4804                  * to read the other two registers.
4805                  */
4806                 E1000_READ_REG(hw, E1000_SYSTIMR);
4807                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4808                 /* Only the 8 LSB are valid. */
4809                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4810                                 & 0xff) << 32;
4811                 break;
4812         default:
4813                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4814                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4815                                 << 32;
4816                 break;
4817         }
4818
4819         return systime_cycles;
4820 }
4821
4822 static uint64_t
4823 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4824 {
4825         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4826         uint64_t rx_tstamp_cycles;
4827
4828         switch (hw->mac.type) {
4829         case e1000_i210:
4830         case e1000_i211:
4831                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4832                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4833                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4834                                 * NSEC_PER_SEC;
4835                 break;
4836         case e1000_82580:
4837         case e1000_i350:
4838         case e1000_i354:
4839                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4840                 /* Only the 8 LSB are valid. */
4841                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4842                                 & 0xff) << 32;
4843                 break;
4844         default:
4845                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4846                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4847                                 << 32;
4848                 break;
4849         }
4850
4851         return rx_tstamp_cycles;
4852 }
4853
4854 static uint64_t
4855 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4856 {
4857         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4858         uint64_t tx_tstamp_cycles;
4859
4860         switch (hw->mac.type) {
4861         case e1000_i210:
4862         case e1000_i211:
4863                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4864                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4865                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4866                                 * NSEC_PER_SEC;
4867                 break;
4868         case e1000_82580:
4869         case e1000_i350:
4870         case e1000_i354:
4871                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4872                 /* Only the 8 LSB are valid. */
4873                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4874                                 & 0xff) << 32;
4875                 break;
4876         default:
4877                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4878                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4879                                 << 32;
4880                 break;
4881         }
4882
4883         return tx_tstamp_cycles;
4884 }
4885
4886 static void
4887 igb_start_timecounters(struct rte_eth_dev *dev)
4888 {
4889         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4890         struct e1000_adapter *adapter = dev->data->dev_private;
4891         uint32_t incval = 1;
4892         uint32_t shift = 0;
4893         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4894
4895         switch (hw->mac.type) {
4896         case e1000_82580:
4897         case e1000_i350:
4898         case e1000_i354:
4899                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4900                 mask = (1ULL << 40) - 1;
4901                 /* fall-through */
4902         case e1000_i210:
4903         case e1000_i211:
4904                 /*
4905                  * Start incrementing the register
4906                  * used to timestamp PTP packets.
4907                  */
4908                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4909                 break;
4910         case e1000_82576:
4911                 incval = E1000_INCVALUE_82576;
4912                 shift = IGB_82576_TSYNC_SHIFT;
4913                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4914                                 E1000_INCPERIOD_82576 | incval);
4915                 break;
4916         default:
4917                 /* Not supported */
4918                 return;
4919         }
4920
4921         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4922         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4923         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4924
4925         adapter->systime_tc.cc_mask = mask;
4926         adapter->systime_tc.cc_shift = shift;
4927         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4928
4929         adapter->rx_tstamp_tc.cc_mask = mask;
4930         adapter->rx_tstamp_tc.cc_shift = shift;
4931         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4932
4933         adapter->tx_tstamp_tc.cc_mask = mask;
4934         adapter->tx_tstamp_tc.cc_shift = shift;
4935         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4936 }
4937
4938 static int
4939 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4940 {
4941         struct e1000_adapter *adapter = dev->data->dev_private;
4942
4943         adapter->systime_tc.nsec += delta;
4944         adapter->rx_tstamp_tc.nsec += delta;
4945         adapter->tx_tstamp_tc.nsec += delta;
4946
4947         return 0;
4948 }
4949
4950 static int
4951 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4952 {
4953         uint64_t ns;
4954         struct e1000_adapter *adapter = dev->data->dev_private;
4955
4956         ns = rte_timespec_to_ns(ts);
4957
4958         /* Set the timecounters to a new value. */
4959         adapter->systime_tc.nsec = ns;
4960         adapter->rx_tstamp_tc.nsec = ns;
4961         adapter->tx_tstamp_tc.nsec = ns;
4962
4963         return 0;
4964 }
4965
4966 static int
4967 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4968 {
4969         uint64_t ns, systime_cycles;
4970         struct e1000_adapter *adapter = dev->data->dev_private;
4971
4972         systime_cycles = igb_read_systime_cyclecounter(dev);
4973         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4974         *ts = rte_ns_to_timespec(ns);
4975
4976         return 0;
4977 }
4978
4979 static int
4980 igb_timesync_enable(struct rte_eth_dev *dev)
4981 {
4982         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4983         uint32_t tsync_ctl;
4984         uint32_t tsauxc;
4985
4986         /* Stop the timesync system time. */
4987         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4988         /* Reset the timesync system time value. */
4989         switch (hw->mac.type) {
4990         case e1000_82580:
4991         case e1000_i350:
4992         case e1000_i354:
4993         case e1000_i210:
4994         case e1000_i211:
4995                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4996                 /* fall-through */
4997         case e1000_82576:
4998                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4999                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5000                 break;
5001         default:
5002                 /* Not supported. */
5003                 return -ENOTSUP;
5004         }
5005
5006         /* Enable system time for it isn't on by default. */
5007         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5008         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5009         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5010
5011         igb_start_timecounters(dev);
5012
5013         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5014         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5015                         (RTE_ETHER_TYPE_1588 |
5016                          E1000_ETQF_FILTER_ENABLE |
5017                          E1000_ETQF_1588));
5018
5019         /* Enable timestamping of received PTP packets. */
5020         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5021         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5022         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5023
5024         /* Enable Timestamping of transmitted PTP packets. */
5025         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5026         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5027         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5028
5029         return 0;
5030 }
5031
5032 static int
5033 igb_timesync_disable(struct rte_eth_dev *dev)
5034 {
5035         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5036         uint32_t tsync_ctl;
5037
5038         /* Disable timestamping of transmitted PTP packets. */
5039         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5040         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5041         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5042
5043         /* Disable timestamping of received PTP packets. */
5044         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5045         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5046         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5047
5048         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5049         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5050
5051         /* Stop incrementating the System Time registers. */
5052         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5053
5054         return 0;
5055 }
5056
5057 static int
5058 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5059                                struct timespec *timestamp,
5060                                uint32_t flags __rte_unused)
5061 {
5062         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5063         struct e1000_adapter *adapter = dev->data->dev_private;
5064         uint32_t tsync_rxctl;
5065         uint64_t rx_tstamp_cycles;
5066         uint64_t ns;
5067
5068         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5069         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5070                 return -EINVAL;
5071
5072         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5073         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5074         *timestamp = rte_ns_to_timespec(ns);
5075
5076         return  0;
5077 }
5078
5079 static int
5080 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5081                                struct timespec *timestamp)
5082 {
5083         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5084         struct e1000_adapter *adapter = dev->data->dev_private;
5085         uint32_t tsync_txctl;
5086         uint64_t tx_tstamp_cycles;
5087         uint64_t ns;
5088
5089         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5090         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5091                 return -EINVAL;
5092
5093         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5094         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5095         *timestamp = rte_ns_to_timespec(ns);
5096
5097         return  0;
5098 }
5099
5100 static int
5101 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5102 {
5103         int count = 0;
5104         int g_ind = 0;
5105         const struct reg_info *reg_group;
5106
5107         while ((reg_group = igb_regs[g_ind++]))
5108                 count += igb_reg_group_count(reg_group);
5109
5110         return count;
5111 }
5112
5113 static int
5114 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5115 {
5116         int count = 0;
5117         int g_ind = 0;
5118         const struct reg_info *reg_group;
5119
5120         while ((reg_group = igbvf_regs[g_ind++]))
5121                 count += igb_reg_group_count(reg_group);
5122
5123         return count;
5124 }
5125
5126 static int
5127 eth_igb_get_regs(struct rte_eth_dev *dev,
5128         struct rte_dev_reg_info *regs)
5129 {
5130         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131         uint32_t *data = regs->data;
5132         int g_ind = 0;
5133         int count = 0;
5134         const struct reg_info *reg_group;
5135
5136         if (data == NULL) {
5137                 regs->length = eth_igb_get_reg_length(dev);
5138                 regs->width = sizeof(uint32_t);
5139                 return 0;
5140         }
5141
5142         /* Support only full register dump */
5143         if ((regs->length == 0) ||
5144             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5145                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5146                         hw->device_id;
5147                 while ((reg_group = igb_regs[g_ind++]))
5148                         count += igb_read_regs_group(dev, &data[count],
5149                                                         reg_group);
5150                 return 0;
5151         }
5152
5153         return -ENOTSUP;
5154 }
5155
5156 static int
5157 igbvf_get_regs(struct rte_eth_dev *dev,
5158         struct rte_dev_reg_info *regs)
5159 {
5160         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5161         uint32_t *data = regs->data;
5162         int g_ind = 0;
5163         int count = 0;
5164         const struct reg_info *reg_group;
5165
5166         if (data == NULL) {
5167                 regs->length = igbvf_get_reg_length(dev);
5168                 regs->width = sizeof(uint32_t);
5169                 return 0;
5170         }
5171
5172         /* Support only full register dump */
5173         if ((regs->length == 0) ||
5174             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5175                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5176                         hw->device_id;
5177                 while ((reg_group = igbvf_regs[g_ind++]))
5178                         count += igb_read_regs_group(dev, &data[count],
5179                                                         reg_group);
5180                 return 0;
5181         }
5182
5183         return -ENOTSUP;
5184 }
5185
5186 static int
5187 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5188 {
5189         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5190
5191         /* Return unit is byte count */
5192         return hw->nvm.word_size * 2;
5193 }
5194
5195 static int
5196 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5197         struct rte_dev_eeprom_info *in_eeprom)
5198 {
5199         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5200         struct e1000_nvm_info *nvm = &hw->nvm;
5201         uint16_t *data = in_eeprom->data;
5202         int first, length;
5203
5204         first = in_eeprom->offset >> 1;
5205         length = in_eeprom->length >> 1;
5206         if ((first >= hw->nvm.word_size) ||
5207             ((first + length) >= hw->nvm.word_size))
5208                 return -EINVAL;
5209
5210         in_eeprom->magic = hw->vendor_id |
5211                 ((uint32_t)hw->device_id << 16);
5212
5213         if ((nvm->ops.read) == NULL)
5214                 return -ENOTSUP;
5215
5216         return nvm->ops.read(hw, first, length, data);
5217 }
5218
5219 static int
5220 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5221         struct rte_dev_eeprom_info *in_eeprom)
5222 {
5223         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5224         struct e1000_nvm_info *nvm = &hw->nvm;
5225         uint16_t *data = in_eeprom->data;
5226         int first, length;
5227
5228         first = in_eeprom->offset >> 1;
5229         length = in_eeprom->length >> 1;
5230         if ((first >= hw->nvm.word_size) ||
5231             ((first + length) >= hw->nvm.word_size))
5232                 return -EINVAL;
5233
5234         in_eeprom->magic = (uint32_t)hw->vendor_id |
5235                 ((uint32_t)hw->device_id << 16);
5236
5237         if ((nvm->ops.write) == NULL)
5238                 return -ENOTSUP;
5239         return nvm->ops.write(hw,  first, length, data);
5240 }
5241
5242 static int
5243 eth_igb_get_module_info(struct rte_eth_dev *dev,
5244                         struct rte_eth_dev_module_info *modinfo)
5245 {
5246         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5247
5248         uint32_t status = 0;
5249         uint16_t sff8472_rev, addr_mode;
5250         bool page_swap = false;
5251
5252         if (hw->phy.media_type == e1000_media_type_copper ||
5253             hw->phy.media_type == e1000_media_type_unknown)
5254                 return -EOPNOTSUPP;
5255
5256         /* Check whether we support SFF-8472 or not */
5257         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5258         if (status)
5259                 return -EIO;
5260
5261         /* addressing mode is not supported */
5262         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5263         if (status)
5264                 return -EIO;
5265
5266         /* addressing mode is not supported */
5267         if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5268                 PMD_DRV_LOG(ERR,
5269                             "Address change required to access page 0xA2, "
5270                             "but not supported. Please report the module "
5271                             "type to the driver maintainers.\n");
5272                 page_swap = true;
5273         }
5274
5275         if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5276                 /* We have an SFP, but it does not support SFF-8472 */
5277                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5278                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5279         } else {
5280                 /* We have an SFP which supports a revision of SFF-8472 */
5281                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5282                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5283         }
5284
5285         return 0;
5286 }
5287
5288 static int
5289 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5290                           struct rte_dev_eeprom_info *info)
5291 {
5292         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5293
5294         uint32_t status = 0;
5295         uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5296         u16 first_word, last_word;
5297         int i = 0;
5298
5299         if (info->length == 0)
5300                 return -EINVAL;
5301
5302         first_word = info->offset >> 1;
5303         last_word = (info->offset + info->length - 1) >> 1;
5304
5305         /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5306         for (i = 0; i < last_word - first_word + 1; i++) {
5307                 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5308                                                 &dataword[i]);
5309                 if (status) {
5310                         /* Error occurred while reading module */
5311                         return -EIO;
5312                 }
5313
5314                 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5315         }
5316
5317         memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5318
5319         return 0;
5320 }
5321
5322 static int
5323 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5324 {
5325         struct e1000_hw *hw =
5326                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5327         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5328         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5329         uint32_t vec = E1000_MISC_VEC_ID;
5330
5331         if (rte_intr_allow_others(intr_handle))
5332                 vec = E1000_RX_VEC_START;
5333
5334         uint32_t mask = 1 << (queue_id + vec);
5335
5336         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5337         E1000_WRITE_FLUSH(hw);
5338
5339         return 0;
5340 }
5341
5342 static int
5343 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5344 {
5345         struct e1000_hw *hw =
5346                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5347         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5348         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5349         uint32_t vec = E1000_MISC_VEC_ID;
5350
5351         if (rte_intr_allow_others(intr_handle))
5352                 vec = E1000_RX_VEC_START;
5353
5354         uint32_t mask = 1 << (queue_id + vec);
5355         uint32_t regval;
5356
5357         regval = E1000_READ_REG(hw, E1000_EIMS);
5358         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5359         E1000_WRITE_FLUSH(hw);
5360
5361         rte_intr_ack(intr_handle);
5362
5363         return 0;
5364 }
5365
5366 static void
5367 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5368                    uint8_t index, uint8_t offset)
5369 {
5370         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5371
5372         /* clear bits */
5373         val &= ~((uint32_t)0xFF << offset);
5374
5375         /* write vector and valid bit */
5376         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5377
5378         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5379 }
5380
5381 static void
5382 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5383                            uint8_t queue, uint8_t msix_vector)
5384 {
5385         uint32_t tmp = 0;
5386
5387         if (hw->mac.type == e1000_82575) {
5388                 if (direction == 0)
5389                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5390                 else if (direction == 1)
5391                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5392                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5393         } else if (hw->mac.type == e1000_82576) {
5394                 if ((direction == 0) || (direction == 1))
5395                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5396                                            ((queue & 0x8) << 1) +
5397                                            8 * direction);
5398         } else if ((hw->mac.type == e1000_82580) ||
5399                         (hw->mac.type == e1000_i350) ||
5400                         (hw->mac.type == e1000_i354) ||
5401                         (hw->mac.type == e1000_i210) ||
5402                         (hw->mac.type == e1000_i211)) {
5403                 if ((direction == 0) || (direction == 1))
5404                         eth_igb_write_ivar(hw, msix_vector,
5405                                            queue >> 1,
5406                                            ((queue & 0x1) << 4) +
5407                                            8 * direction);
5408         }
5409 }
5410
5411 /* Sets up the hardware to generate MSI-X interrupts properly
5412  * @hw
5413  *  board private structure
5414  */
5415 static void
5416 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5417 {
5418         int queue_id;
5419         uint32_t tmpval, regval, intr_mask;
5420         struct e1000_hw *hw =
5421                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5422         uint32_t vec = E1000_MISC_VEC_ID;
5423         uint32_t base = E1000_MISC_VEC_ID;
5424         uint32_t misc_shift = 0;
5425         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5426         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5427
5428         /* won't configure msix register if no mapping is done
5429          * between intr vector and event fd
5430          */
5431         if (!rte_intr_dp_is_en(intr_handle))
5432                 return;
5433
5434         if (rte_intr_allow_others(intr_handle)) {
5435                 vec = base = E1000_RX_VEC_START;
5436                 misc_shift = 1;
5437         }
5438
5439         /* set interrupt vector for other causes */
5440         if (hw->mac.type == e1000_82575) {
5441                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5442                 /* enable MSI-X PBA support */
5443                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5444
5445                 /* Auto-Mask interrupts upon ICR read */
5446                 tmpval |= E1000_CTRL_EXT_EIAME;
5447                 tmpval |= E1000_CTRL_EXT_IRCA;
5448
5449                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5450
5451                 /* enable msix_other interrupt */
5452                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5453                 regval = E1000_READ_REG(hw, E1000_EIAC);
5454                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5455                 regval = E1000_READ_REG(hw, E1000_EIAM);
5456                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5457         } else if ((hw->mac.type == e1000_82576) ||
5458                         (hw->mac.type == e1000_82580) ||
5459                         (hw->mac.type == e1000_i350) ||
5460                         (hw->mac.type == e1000_i354) ||
5461                         (hw->mac.type == e1000_i210) ||
5462                         (hw->mac.type == e1000_i211)) {
5463                 /* turn on MSI-X capability first */
5464                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5465                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5466                                         E1000_GPIE_NSICR);
5467                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5468                         misc_shift;
5469
5470                 if (dev->data->dev_conf.intr_conf.lsc != 0)
5471                         intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5472
5473                 regval = E1000_READ_REG(hw, E1000_EIAC);
5474                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5475
5476                 /* enable msix_other interrupt */
5477                 regval = E1000_READ_REG(hw, E1000_EIMS);
5478                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5479                 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5480                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5481         }
5482
5483         /* use EIAM to auto-mask when MSI-X interrupt
5484          * is asserted, this saves a register write for every interrupt
5485          */
5486         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5487                 misc_shift;
5488
5489         if (dev->data->dev_conf.intr_conf.lsc != 0)
5490                 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5491
5492         regval = E1000_READ_REG(hw, E1000_EIAM);
5493         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5494
5495         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5496                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5497                 intr_handle->intr_vec[queue_id] = vec;
5498                 if (vec < base + intr_handle->nb_efd - 1)
5499                         vec++;
5500         }
5501
5502         E1000_WRITE_FLUSH(hw);
5503 }
5504
5505 /* restore n-tuple filter */
5506 static inline void
5507 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5508 {
5509         struct e1000_filter_info *filter_info =
5510                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5511         struct e1000_5tuple_filter *p_5tuple;
5512         struct e1000_2tuple_filter *p_2tuple;
5513
5514         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5515                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5516         }
5517
5518         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5519                 igb_inject_2uple_filter(dev, p_2tuple);
5520         }
5521 }
5522
5523 /* restore SYN filter */
5524 static inline void
5525 igb_syn_filter_restore(struct rte_eth_dev *dev)
5526 {
5527         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5528         struct e1000_filter_info *filter_info =
5529                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5530         uint32_t synqf;
5531
5532         synqf = filter_info->syn_info;
5533
5534         if (synqf & E1000_SYN_FILTER_ENABLE) {
5535                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5536                 E1000_WRITE_FLUSH(hw);
5537         }
5538 }
5539
5540 /* restore ethernet type filter */
5541 static inline void
5542 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5543 {
5544         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5545         struct e1000_filter_info *filter_info =
5546                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5547         int i;
5548
5549         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5550                 if (filter_info->ethertype_mask & (1 << i)) {
5551                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5552                                 filter_info->ethertype_filters[i].etqf);
5553                         E1000_WRITE_FLUSH(hw);
5554                 }
5555         }
5556 }
5557
5558 /* restore flex byte filter */
5559 static inline void
5560 igb_flex_filter_restore(struct rte_eth_dev *dev)
5561 {
5562         struct e1000_filter_info *filter_info =
5563                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5564         struct e1000_flex_filter *flex_filter;
5565
5566         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5567                 igb_inject_flex_filter(dev, flex_filter);
5568         }
5569 }
5570
5571 /* restore rss filter */
5572 static inline void
5573 igb_rss_filter_restore(struct rte_eth_dev *dev)
5574 {
5575         struct e1000_filter_info *filter_info =
5576                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5577
5578         if (filter_info->rss_info.conf.queue_num)
5579                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5580 }
5581
5582 /* restore all types filter */
5583 static int
5584 igb_filter_restore(struct rte_eth_dev *dev)
5585 {
5586         igb_ntuple_filter_restore(dev);
5587         igb_ethertype_filter_restore(dev);
5588         igb_syn_filter_restore(dev);
5589         igb_flex_filter_restore(dev);
5590         igb_rss_filter_restore(dev);
5591
5592         return 0;
5593 }
5594
5595 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5596 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5597 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5598 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5599 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5600 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5601
5602 /* see e1000_logs.c */
5603 RTE_INIT(e1000_init_log)
5604 {
5605         e1000_igb_init_log();
5606 }