drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "base/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59 #include "igb_regs.h"
  60
  61 /*
  62  * Default values for port configuration
  63  */
  64 #define IGB_DEFAULT_RX_FREE_THRESH  32
  65
  66 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  67 #define IGB_DEFAULT_RX_HTHRESH      8
  68 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  69
  70 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  71 #define IGB_DEFAULT_TX_HTHRESH      1
  72 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  73
  74 #define IGB_HKEY_MAX_INDEX 10
  75
  76 /* Bit shift and mask */
  77 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  78 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  79 #define IGB_8_BIT_WIDTH  CHAR_BIT
  80 #define IGB_8_BIT_MASK   UINT8_MAX
  81
  82 /* Additional timesync values. */
  83 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  84 #define E1000_ETQF_FILTER_1588       3
  85 #define IGB_82576_TSYNC_SHIFT        16
  86 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  87 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  89
  90 #define E1000_VTIVAR_MISC                0x01740
  91 #define E1000_VTIVAR_MISC_MASK           0xFF
  92 #define E1000_VTIVAR_VALID               0x80
  93 #define E1000_VTIVAR_MISC_MAILBOX        0
  94 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  95
  96 /* External VLAN Enable bit mask */
  97 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  98
  99 /* External VLAN Ether Type bit mask and shift */
 100 #define E1000_VET_VET_EXT            0xFFFF0000
 101 #define E1000_VET_VET_EXT_SHIFT      16
 102
 103 static int  eth_igb_configure(struct rte_eth_dev *dev);
 104 static int  eth_igb_start(struct rte_eth_dev *dev);
 105 static void eth_igb_stop(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 107 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 108 static void eth_igb_close(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 113 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 114                                 int wait_to_complete);
 115 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 116                                 struct rte_eth_stats *rte_stats);
 117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 118                               struct rte_eth_xstat *xstats, unsigned n);
 119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
 120                 const uint64_t *ids,
 121                 uint64_t *values, unsigned int n);
 122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 123                                     struct rte_eth_xstat_name *xstats_names,
 124                                     unsigned int size);
 125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
 126                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 127                 unsigned int limit);
 128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 131                                    char *fw_version, size_t fw_size);
 132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 133                               struct rte_eth_dev_info *dev_info);
 134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 136                                 struct rte_eth_dev_info *dev_info);
 137 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 138                                 struct rte_eth_fc_conf *fc_conf);
 139 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 140                                 struct rte_eth_fc_conf *fc_conf);
 141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 145                                     struct rte_intr_handle *handle);
 146 static void eth_igb_interrupt_handler(void *param);
 147 static int  igb_hardware_init(struct e1000_hw *hw);
 148 static void igb_hw_control_acquire(struct e1000_hw *hw);
 149 static void igb_hw_control_release(struct e1000_hw *hw);
 150 static void igb_init_manageability(struct e1000_hw *hw);
 151 static void igb_release_manageability(struct e1000_hw *hw);
 152
 153 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154
 155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 156                 uint16_t vlan_id, int on);
 157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 158                                  enum rte_vlan_type vlan_type,
 159                                  uint16_t tpid_id);
 160 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 161
 162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 168
 169 static int eth_igb_led_on(struct rte_eth_dev *dev);
 170 static int eth_igb_led_off(struct rte_eth_dev *dev);
 171
 172 static void igb_intr_disable(struct e1000_hw *hw);
 173 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 174 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 175                            struct ether_addr *mac_addr,
 176                            uint32_t index, uint32_t pool);
 177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 179                 struct ether_addr *addr);
 180
 181 static void igbvf_intr_disable(struct e1000_hw *hw);
 182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 183 static int igbvf_dev_start(struct rte_eth_dev *dev);
 184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 185 static void igbvf_dev_close(struct rte_eth_dev *dev);
 186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 190 static int eth_igbvf_link_update(struct e1000_hw *hw);
 191 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 192                                 struct rte_eth_stats *rte_stats);
 193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 194                                 struct rte_eth_xstat *xstats, unsigned n);
 195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 196                                       struct rte_eth_xstat_name *xstats_names,
 197                                       unsigned limit);
 198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 200                 uint16_t vlan_id, int on);
 201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 204                 struct ether_addr *addr);
 205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 206 static int igbvf_get_regs(struct rte_eth_dev *dev,
 207                 struct rte_dev_reg_info *regs);
 208
 209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 210                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 211                                    uint16_t reta_size);
 212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 213                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 214                                   uint16_t reta_size);
 215
 216 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 217                         struct rte_eth_syn_filter *filter,
 218                         bool add);
 219 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 220                         struct rte_eth_syn_filter *filter);
 221 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 222                         enum rte_filter_op filter_op,
 223                         void *arg);
 224 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 225                         struct rte_eth_ntuple_filter *ntuple_filter);
 226 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 227                         struct rte_eth_ntuple_filter *ntuple_filter);
 228 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 229                         struct rte_eth_flex_filter *filter,
 230                         bool add);
 231 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 232                         struct rte_eth_flex_filter *filter);
 233 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 234                         enum rte_filter_op filter_op,
 235                         void *arg);
 236 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 237                         struct rte_eth_ntuple_filter *ntuple_filter);
 238 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 239                         struct rte_eth_ntuple_filter *ntuple_filter);
 240 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 241                         struct rte_eth_ntuple_filter *filter,
 242                         bool add);
 243 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 244                         struct rte_eth_ntuple_filter *filter);
 245 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 246                                 enum rte_filter_op filter_op,
 247                                 void *arg);
 248 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 249                         struct rte_eth_ethertype_filter *filter,
 250                         bool add);
 251 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 252                                 enum rte_filter_op filter_op,
 253                                 void *arg);
 254 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 255                         struct rte_eth_ethertype_filter *filter);
 256 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 257                      enum rte_filter_type filter_type,
 258                      enum rte_filter_op filter_op,
 259                      void *arg);
 260 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 261 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 262                 struct rte_dev_reg_info *regs);
 263 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 264 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 265                 struct rte_dev_eeprom_info *eeprom);
 266 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 267                 struct rte_dev_eeprom_info *eeprom);
 268 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 269                                     struct ether_addr *mc_addr_set,
 270                                     uint32_t nb_mc_addr);
 271 static int igb_timesync_enable(struct rte_eth_dev *dev);
 272 static int igb_timesync_disable(struct rte_eth_dev *dev);
 273 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 274                                           struct timespec *timestamp,
 275                                           uint32_t flags);
 276 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 277                                           struct timespec *timestamp);
 278 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 279 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 280                                   struct timespec *timestamp);
 281 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 282                                    const struct timespec *timestamp);
 283 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 284                                         uint16_t queue_id);
 285 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 286                                          uint16_t queue_id);
 287 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 288                                        uint8_t queue, uint8_t msix_vector);
 289 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 290                                uint8_t index, uint8_t offset);
 291 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 292 static void eth_igbvf_interrupt_handler(void *param);
 293 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 294 static int igb_filter_restore(struct rte_eth_dev *dev);
 295
 296 /*
 297  * Define VF Stats MACRO for Non "cleared on read" register
 298  */
 299 #define UPDATE_VF_STAT(reg, last, cur)            \
 300 {                                                 \
 301         u32 latest = E1000_READ_REG(hw, reg);     \
 302         cur += (latest - last) & UINT_MAX;        \
 303         last = latest;                            \
 304 }
 305
 306 #define IGB_FC_PAUSE_TIME 0x0680
 307 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 308 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 309
 310 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 311
 312 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 313
 314 /*
 315  * The set of PCI devices this driver supports
 316  */
 317 static const struct rte_pci_id pci_id_igb_map[] = {
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 326
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 330
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 337
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 348         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 349         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 350         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 351         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 352         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 353         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 354         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 357         { .vendor_id = 0, /* sentinel */ },
 358 };
 359
 360 /*
 361  * The set of PCI devices this driver supports (for 82576&I350 VF)
 362  */
 363 static const struct rte_pci_id pci_id_igbvf_map[] = {
 364         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 365         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 366         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 367         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 368         { .vendor_id = 0, /* sentinel */ },
 369 };
 370
 371 static const struct rte_eth_desc_lim rx_desc_lim = {
 372         .nb_max = E1000_MAX_RING_DESC,
 373         .nb_min = E1000_MIN_RING_DESC,
 374         .nb_align = IGB_RXD_ALIGN,
 375 };
 376
 377 static const struct rte_eth_desc_lim tx_desc_lim = {
 378         .nb_max = E1000_MAX_RING_DESC,
 379         .nb_min = E1000_MIN_RING_DESC,
 380         .nb_align = IGB_RXD_ALIGN,
 381         .nb_seg_max = IGB_TX_MAX_SEG,
 382         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 383 };
 384
 385 static const struct eth_dev_ops eth_igb_ops = {
 386         .dev_configure        = eth_igb_configure,
 387         .dev_start            = eth_igb_start,
 388         .dev_stop             = eth_igb_stop,
 389         .dev_set_link_up      = eth_igb_dev_set_link_up,
 390         .dev_set_link_down    = eth_igb_dev_set_link_down,
 391         .dev_close            = eth_igb_close,
 392         .promiscuous_enable   = eth_igb_promiscuous_enable,
 393         .promiscuous_disable  = eth_igb_promiscuous_disable,
 394         .allmulticast_enable  = eth_igb_allmulticast_enable,
 395         .allmulticast_disable = eth_igb_allmulticast_disable,
 396         .link_update          = eth_igb_link_update,
 397         .stats_get            = eth_igb_stats_get,
 398         .xstats_get           = eth_igb_xstats_get,
 399         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 400         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 401         .xstats_get_names     = eth_igb_xstats_get_names,
 402         .stats_reset          = eth_igb_stats_reset,
 403         .xstats_reset         = eth_igb_xstats_reset,
 404         .fw_version_get       = eth_igb_fw_version_get,
 405         .dev_infos_get        = eth_igb_infos_get,
 406         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 407         .mtu_set              = eth_igb_mtu_set,
 408         .vlan_filter_set      = eth_igb_vlan_filter_set,
 409         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 410         .vlan_offload_set     = eth_igb_vlan_offload_set,
 411         .rx_queue_setup       = eth_igb_rx_queue_setup,
 412         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 413         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 414         .rx_queue_release     = eth_igb_rx_queue_release,
 415         .rx_queue_count       = eth_igb_rx_queue_count,
 416         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 417         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 418         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 419         .tx_queue_setup       = eth_igb_tx_queue_setup,
 420         .tx_queue_release     = eth_igb_tx_queue_release,
 421         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 422         .dev_led_on           = eth_igb_led_on,
 423         .dev_led_off          = eth_igb_led_off,
 424         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 425         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 426         .mac_addr_add         = eth_igb_rar_set,
 427         .mac_addr_remove      = eth_igb_rar_clear,
 428         .mac_addr_set         = eth_igb_default_mac_addr_set,
 429         .reta_update          = eth_igb_rss_reta_update,
 430         .reta_query           = eth_igb_rss_reta_query,
 431         .rss_hash_update      = eth_igb_rss_hash_update,
 432         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 433         .filter_ctrl          = eth_igb_filter_ctrl,
 434         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 435         .rxq_info_get         = igb_rxq_info_get,
 436         .txq_info_get         = igb_txq_info_get,
 437         .timesync_enable      = igb_timesync_enable,
 438         .timesync_disable     = igb_timesync_disable,
 439         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 440         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 441         .get_reg              = eth_igb_get_regs,
 442         .get_eeprom_length    = eth_igb_get_eeprom_length,
 443         .get_eeprom           = eth_igb_get_eeprom,
 444         .set_eeprom           = eth_igb_set_eeprom,
 445         .timesync_adjust_time = igb_timesync_adjust_time,
 446         .timesync_read_time   = igb_timesync_read_time,
 447         .timesync_write_time  = igb_timesync_write_time,
 448 };
 449
 450 /*
 451  * dev_ops for virtual function, bare necessities for basic vf
 452  * operation have been implemented
 453  */
 454 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 455         .dev_configure        = igbvf_dev_configure,
 456         .dev_start            = igbvf_dev_start,
 457         .dev_stop             = igbvf_dev_stop,
 458         .dev_close            = igbvf_dev_close,
 459         .promiscuous_enable   = igbvf_promiscuous_enable,
 460         .promiscuous_disable  = igbvf_promiscuous_disable,
 461         .allmulticast_enable  = igbvf_allmulticast_enable,
 462         .allmulticast_disable = igbvf_allmulticast_disable,
 463         .link_update          = eth_igb_link_update,
 464         .stats_get            = eth_igbvf_stats_get,
 465         .xstats_get           = eth_igbvf_xstats_get,
 466         .xstats_get_names     = eth_igbvf_xstats_get_names,
 467         .stats_reset          = eth_igbvf_stats_reset,
 468         .xstats_reset         = eth_igbvf_stats_reset,
 469         .vlan_filter_set      = igbvf_vlan_filter_set,
 470         .dev_infos_get        = eth_igbvf_infos_get,
 471         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 472         .rx_queue_setup       = eth_igb_rx_queue_setup,
 473         .rx_queue_release     = eth_igb_rx_queue_release,
 474         .tx_queue_setup       = eth_igb_tx_queue_setup,
 475         .tx_queue_release     = eth_igb_tx_queue_release,
 476         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 477         .rxq_info_get         = igb_rxq_info_get,
 478         .txq_info_get         = igb_txq_info_get,
 479         .mac_addr_set         = igbvf_default_mac_addr_set,
 480         .get_reg              = igbvf_get_regs,
 481 };
 482
 483 /* store statistics names and its offset in stats structure */
 484 struct rte_igb_xstats_name_off {
 485         char name[RTE_ETH_XSTATS_NAME_SIZE];
 486         unsigned offset;
 487 };
 488
 489 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 490         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 491         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 492         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 493         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 494         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 495         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 496         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 497                 ecol)},
 498         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 499         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 500         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 501         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 502         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 503         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 504         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 505         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 506         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 507         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 508         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 509                 fcruc)},
 510         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 511         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 512         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 513         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 514         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 515                 prc1023)},
 516         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 517                 prc1522)},
 518         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 519         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 520         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 521         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 522         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 523         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 524         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 525         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 526         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 527         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 528         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 529         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 530         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 531         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 532         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 533         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 534         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 535         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 536                 ptc1023)},
 537         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 538                 ptc1522)},
 539         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 540         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 541         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 542         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 543         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 544         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 545         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 546
 547         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 548 };
 549
 550 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 551                 sizeof(rte_igb_stats_strings[0]))
 552
 553 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 554         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 555         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 556         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 557         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 558         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 559 };
 560
 561 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 562                 sizeof(rte_igbvf_stats_strings[0]))
 563
 564 /**
 565  * Atomically reads the link status information from global
 566  * structure rte_eth_dev.
 567  *
 568  * @param dev
 569  *   - Pointer to the structure rte_eth_dev to read from.
 570  *   - Pointer to the buffer to be saved with the link status.
 571  *
 572  * @return
 573  *   - On success, zero.
 574  *   - On failure, negative value.
 575  */
 576 static inline int
 577 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 578                                 struct rte_eth_link *link)
 579 {
 580         struct rte_eth_link *dst = link;
 581         struct rte_eth_link *src = &(dev->data->dev_link);
 582
 583         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 584                                         *(uint64_t *)src) == 0)
 585                 return -1;
 586
 587         return 0;
 588 }
 589
 590 /**
 591  * Atomically writes the link status information into global
 592  * structure rte_eth_dev.
 593  *
 594  * @param dev
 595  *   - Pointer to the structure rte_eth_dev to read from.
 596  *   - Pointer to the buffer to be saved with the link status.
 597  *
 598  * @return
 599  *   - On success, zero.
 600  *   - On failure, negative value.
 601  */
 602 static inline int
 603 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 604                                 struct rte_eth_link *link)
 605 {
 606         struct rte_eth_link *dst = &(dev->data->dev_link);
 607         struct rte_eth_link *src = link;
 608
 609         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 610                                         *(uint64_t *)src) == 0)
 611                 return -1;
 612
 613         return 0;
 614 }
 615
 616 static inline void
 617 igb_intr_enable(struct rte_eth_dev *dev)
 618 {
 619         struct e1000_interrupt *intr =
 620                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 621         struct e1000_hw *hw =
 622                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 623
 624         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 625         E1000_WRITE_FLUSH(hw);
 626 }
 627
 628 static void
 629 igb_intr_disable(struct e1000_hw *hw)
 630 {
 631         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 632         E1000_WRITE_FLUSH(hw);
 633 }
 634
 635 static inline void
 636 igbvf_intr_enable(struct rte_eth_dev *dev)
 637 {
 638         struct e1000_hw *hw =
 639                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 640
 641         /* only for mailbox */
 642         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 643         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 644         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 645         E1000_WRITE_FLUSH(hw);
 646 }
 647
 648 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 649 static void
 650 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 651 {
 652         uint32_t tmp = 0;
 653
 654         /* mailbox */
 655         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 656         tmp |= E1000_VTIVAR_VALID;
 657         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 658 }
 659
 660 static void
 661 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 662 {
 663         struct e1000_hw *hw =
 664                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 665
 666         /* Configure VF other cause ivar */
 667         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 668 }
 669
 670 static inline int32_t
 671 igb_pf_reset_hw(struct e1000_hw *hw)
 672 {
 673         uint32_t ctrl_ext;
 674         int32_t status;
 675
 676         status = e1000_reset_hw(hw);
 677
 678         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 679         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 680         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 681         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 682         E1000_WRITE_FLUSH(hw);
 683
 684         return status;
 685 }
 686
 687 static void
 688 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 689 {
 690         struct e1000_hw *hw =
 691                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 692
 693
 694         hw->vendor_id = pci_dev->id.vendor_id;
 695         hw->device_id = pci_dev->id.device_id;
 696         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 697         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 698
 699         e1000_set_mac_type(hw);
 700
 701         /* need to check if it is a vf device below */
 702 }
 703
 704 static int
 705 igb_reset_swfw_lock(struct e1000_hw *hw)
 706 {
 707         int ret_val;
 708
 709         /*
 710          * Do mac ops initialization manually here, since we will need
 711          * some function pointers set by this call.
 712          */
 713         ret_val = e1000_init_mac_params(hw);
 714         if (ret_val)
 715                 return ret_val;
 716
 717         /*
 718          * SMBI lock should not fail in this early stage. If this is the case,
 719          * it is due to an improper exit of the application.
 720          * So force the release of the faulty lock.
 721          */
 722         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 723                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 724         }
 725         e1000_put_hw_semaphore_generic(hw);
 726
 727         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 728                 uint16_t mask;
 729
 730                 /*
 731                  * Phy lock should not fail in this early stage. If this is the case,
 732                  * it is due to an improper exit of the application.
 733                  * So force the release of the faulty lock.
 734                  */
 735                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 736                 if (hw->bus.func > E1000_FUNC_1)
 737                         mask <<= 2;
 738                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 739                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 740                                     hw->bus.func);
 741                 }
 742                 hw->mac.ops.release_swfw_sync(hw, mask);
 743
 744                 /*
 745                  * This one is more tricky since it is common to all ports; but
 746                  * swfw_sync retries last long enough (1s) to be almost sure that if
 747                  * lock can not be taken it is due to an improper lock of the
 748                  * semaphore.
 749                  */
 750                 mask = E1000_SWFW_EEP_SM;
 751                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 752                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 753                 }
 754                 hw->mac.ops.release_swfw_sync(hw, mask);
 755         }
 756
 757         return E1000_SUCCESS;
 758 }
 759
 760 static int
 761 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 762 {
 763         int error = 0;
 764         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 765         struct e1000_hw *hw =
 766                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 767         struct e1000_vfta * shadow_vfta =
 768                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 769         struct e1000_filter_info *filter_info =
 770                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 771         struct e1000_adapter *adapter =
 772                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 773
 774         uint32_t ctrl_ext;
 775
 776         eth_dev->dev_ops = &eth_igb_ops;
 777         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 778         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 779         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 780
 781         /* for secondary processes, we don't initialise any further as primary
 782          * has already done this work. Only check we don't need a different
 783          * RX function */
 784         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 785                 if (eth_dev->data->scattered_rx)
 786                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 787                 return 0;
 788         }
 789
 790         rte_eth_copy_pci_info(eth_dev, pci_dev);
 791         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 792
 793         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 794
 795         igb_identify_hardware(eth_dev, pci_dev);
 796         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 797                 error = -EIO;
 798                 goto err_late;
 799         }
 800
 801         e1000_get_bus_info(hw);
 802
 803         /* Reset any pending lock */
 804         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 805                 error = -EIO;
 806                 goto err_late;
 807         }
 808
 809         /* Finish initialization */
 810         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 811                 error = -EIO;
 812                 goto err_late;
 813         }
 814
 815         hw->mac.autoneg = 1;
 816         hw->phy.autoneg_wait_to_complete = 0;
 817         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 818
 819         /* Copper options */
 820         if (hw->phy.media_type == e1000_media_type_copper) {
 821                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 822                 hw->phy.disable_polarity_correction = 0;
 823                 hw->phy.ms_type = e1000_ms_hw_default;
 824         }
 825
 826         /*
 827          * Start from a known state, this is important in reading the nvm
 828          * and mac from that.
 829          */
 830         igb_pf_reset_hw(hw);
 831
 832         /* Make sure we have a good EEPROM before we read from it */
 833         if (e1000_validate_nvm_checksum(hw) < 0) {
 834                 /*
 835                  * Some PCI-E parts fail the first check due to
 836                  * the link being in sleep state, call it again,
 837                  * if it fails a second time its a real issue.
 838                  */
 839                 if (e1000_validate_nvm_checksum(hw) < 0) {
 840                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 841                         error = -EIO;
 842                         goto err_late;
 843                 }
 844         }
 845
 846         /* Read the permanent MAC address out of the EEPROM */
 847         if (e1000_read_mac_addr(hw) != 0) {
 848                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 849                 error = -EIO;
 850                 goto err_late;
 851         }
 852
 853         /* Allocate memory for storing MAC addresses */
 854         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 855                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 856         if (eth_dev->data->mac_addrs == NULL) {
 857                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 858                                                 "store MAC addresses",
 859                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 860                 error = -ENOMEM;
 861                 goto err_late;
 862         }
 863
 864         /* Copy the permanent MAC address */
 865         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 866
 867         /* initialize the vfta */
 868         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 869
 870         /* Now initialize the hardware */
 871         if (igb_hardware_init(hw) != 0) {
 872                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 873                 rte_free(eth_dev->data->mac_addrs);
 874                 eth_dev->data->mac_addrs = NULL;
 875                 error = -ENODEV;
 876                 goto err_late;
 877         }
 878         hw->mac.get_link_status = 1;
 879         adapter->stopped = 0;
 880
 881         /* Indicate SOL/IDER usage */
 882         if (e1000_check_reset_block(hw) < 0) {
 883                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 884                                         "SOL/IDER session");
 885         }
 886
 887         /* initialize PF if max_vfs not zero */
 888         igb_pf_host_init(eth_dev);
 889
 890         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 891         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 892         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 893         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 894         E1000_WRITE_FLUSH(hw);
 895
 896         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 897                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 898                      pci_dev->id.device_id);
 899
 900         rte_intr_callback_register(&pci_dev->intr_handle,
 901                                    eth_igb_interrupt_handler,
 902                                    (void *)eth_dev);
 903
 904         /* enable uio/vfio intr/eventfd mapping */
 905         rte_intr_enable(&pci_dev->intr_handle);
 906
 907         /* enable support intr */
 908         igb_intr_enable(eth_dev);
 909
 910         /* initialize filter info */
 911         memset(filter_info, 0,
 912                sizeof(struct e1000_filter_info));
 913
 914         TAILQ_INIT(&filter_info->flex_list);
 915         TAILQ_INIT(&filter_info->twotuple_list);
 916         TAILQ_INIT(&filter_info->fivetuple_list);
 917
 918         return 0;
 919
 920 err_late:
 921         igb_hw_control_release(hw);
 922
 923         return error;
 924 }
 925
 926 static int
 927 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 928 {
 929         struct rte_pci_device *pci_dev;
 930         struct rte_intr_handle *intr_handle;
 931         struct e1000_hw *hw;
 932         struct e1000_adapter *adapter =
 933                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 934         struct e1000_filter_info *filter_info =
 935                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 936
 937         PMD_INIT_FUNC_TRACE();
 938
 939         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 940                 return -EPERM;
 941
 942         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 943         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 944         intr_handle = &pci_dev->intr_handle;
 945
 946         if (adapter->stopped == 0)
 947                 eth_igb_close(eth_dev);
 948
 949         eth_dev->dev_ops = NULL;
 950         eth_dev->rx_pkt_burst = NULL;
 951         eth_dev->tx_pkt_burst = NULL;
 952
 953         /* Reset any pending lock */
 954         igb_reset_swfw_lock(hw);
 955
 956         rte_free(eth_dev->data->mac_addrs);
 957         eth_dev->data->mac_addrs = NULL;
 958
 959         /* uninitialize PF if max_vfs not zero */
 960         igb_pf_host_uninit(eth_dev);
 961
 962         /* disable uio intr before callback unregister */
 963         rte_intr_disable(intr_handle);
 964         rte_intr_callback_unregister(intr_handle,
 965                                      eth_igb_interrupt_handler, eth_dev);
 966
 967         /* clear the SYN filter info */
 968         filter_info->syn_info = 0;
 969
 970         return 0;
 971 }
 972
 973 /*
 974  * Virtual Function device init
 975  */
 976 static int
 977 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 978 {
 979         struct rte_pci_device *pci_dev;
 980         struct rte_intr_handle *intr_handle;
 981         struct e1000_adapter *adapter =
 982                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 983         struct e1000_hw *hw =
 984                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 985         int diag;
 986         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 987
 988         PMD_INIT_FUNC_TRACE();
 989
 990         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 991         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 992         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 993         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 994
 995         /* for secondary processes, we don't initialise any further as primary
 996          * has already done this work. Only check we don't need a different
 997          * RX function */
 998         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 999                 if (eth_dev->data->scattered_rx)
1000                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
1001                 return 0;
1002         }
1003
1004         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1005         rte_eth_copy_pci_info(eth_dev, pci_dev);
1006         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1007
1008         hw->device_id = pci_dev->id.device_id;
1009         hw->vendor_id = pci_dev->id.vendor_id;
1010         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1011         adapter->stopped = 0;
1012
1013         /* Initialize the shared code (base driver) */
1014         diag = e1000_setup_init_funcs(hw, TRUE);
1015         if (diag != 0) {
1016                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1017                         diag);
1018                 return -EIO;
1019         }
1020
1021         /* init_mailbox_params */
1022         hw->mbx.ops.init_params(hw);
1023
1024         /* Disable the interrupts for VF */
1025         igbvf_intr_disable(hw);
1026
1027         diag = hw->mac.ops.reset_hw(hw);
1028
1029         /* Allocate memory for storing MAC addresses */
1030         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1031                 hw->mac.rar_entry_count, 0);
1032         if (eth_dev->data->mac_addrs == NULL) {
1033                 PMD_INIT_LOG(ERR,
1034                         "Failed to allocate %d bytes needed to store MAC "
1035                         "addresses",
1036                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1037                 return -ENOMEM;
1038         }
1039
1040         /* Generate a random MAC address, if none was assigned by PF. */
1041         if (is_zero_ether_addr(perm_addr)) {
1042                 eth_random_addr(perm_addr->addr_bytes);
1043                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1044                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1045                              "%02x:%02x:%02x:%02x:%02x:%02x",
1046                              perm_addr->addr_bytes[0],
1047                              perm_addr->addr_bytes[1],
1048                              perm_addr->addr_bytes[2],
1049                              perm_addr->addr_bytes[3],
1050                              perm_addr->addr_bytes[4],
1051                              perm_addr->addr_bytes[5]);
1052         }
1053
1054         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1055         if (diag) {
1056                 rte_free(eth_dev->data->mac_addrs);
1057                 eth_dev->data->mac_addrs = NULL;
1058                 return diag;
1059         }
1060         /* Copy the permanent MAC address */
1061         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1062                         &eth_dev->data->mac_addrs[0]);
1063
1064         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1065                      "mac.type=%s",
1066                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1067                      pci_dev->id.device_id, "igb_mac_82576_vf");
1068
1069         intr_handle = &pci_dev->intr_handle;
1070         rte_intr_callback_register(intr_handle,
1071                                    eth_igbvf_interrupt_handler, eth_dev);
1072
1073         return 0;
1074 }
1075
1076 static int
1077 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1078 {
1079         struct e1000_adapter *adapter =
1080                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1081         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1082
1083         PMD_INIT_FUNC_TRACE();
1084
1085         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1086                 return -EPERM;
1087
1088         if (adapter->stopped == 0)
1089                 igbvf_dev_close(eth_dev);
1090
1091         eth_dev->dev_ops = NULL;
1092         eth_dev->rx_pkt_burst = NULL;
1093         eth_dev->tx_pkt_burst = NULL;
1094
1095         rte_free(eth_dev->data->mac_addrs);
1096         eth_dev->data->mac_addrs = NULL;
1097
1098         /* disable uio intr before callback unregister */
1099         rte_intr_disable(&pci_dev->intr_handle);
1100         rte_intr_callback_unregister(&pci_dev->intr_handle,
1101                                      eth_igbvf_interrupt_handler,
1102                                      (void *)eth_dev);
1103
1104         return 0;
1105 }
1106
1107 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1108         struct rte_pci_device *pci_dev)
1109 {
1110         return rte_eth_dev_pci_generic_probe(pci_dev,
1111                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1112 }
1113
1114 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1115 {
1116         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1117 }
1118
1119 static struct rte_pci_driver rte_igb_pmd = {
1120         .id_table = pci_id_igb_map,
1121         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1122         .probe = eth_igb_pci_probe,
1123         .remove = eth_igb_pci_remove,
1124 };
1125
1126
1127 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1128         struct rte_pci_device *pci_dev)
1129 {
1130         return rte_eth_dev_pci_generic_probe(pci_dev,
1131                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1132 }
1133
1134 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1135 {
1136         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1137 }
1138
1139 /*
1140  * virtual function driver struct
1141  */
1142 static struct rte_pci_driver rte_igbvf_pmd = {
1143         .id_table = pci_id_igbvf_map,
1144         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1145         .probe = eth_igbvf_pci_probe,
1146         .remove = eth_igbvf_pci_remove,
1147 };
1148
1149 static void
1150 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1151 {
1152         struct e1000_hw *hw =
1153                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1154         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1155         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1156         rctl |= E1000_RCTL_VFE;
1157         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1158 }
1159
1160 static int
1161 igb_check_mq_mode(struct rte_eth_dev *dev)
1162 {
1163         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1164         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1165         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1166         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1167
1168         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1169             tx_mq_mode == ETH_MQ_TX_DCB ||
1170             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1171                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1172                 return -EINVAL;
1173         }
1174         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1175                 /* Check multi-queue mode.
1176                  * To no break software we accept ETH_MQ_RX_NONE as this might
1177                  * be used to turn off VLAN filter.
1178                  */
1179
1180                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1181                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1182                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1183                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1184                 } else {
1185                         /* Only support one queue on VFs.
1186                          * RSS together with SRIOV is not supported.
1187                          */
1188                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1189                                         " wrong mq_mode rx %d.",
1190                                         rx_mq_mode);
1191                         return -EINVAL;
1192                 }
1193                 /* TX mode is not used here, so mode might be ignored.*/
1194                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1195                         /* SRIOV only works in VMDq enable mode */
1196                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1197                                         " TX mode %d is not supported. "
1198                                         " Driver will behave as %d mode.",
1199                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1200                 }
1201
1202                 /* check valid queue number */
1203                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1204                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1205                                         " only support one queue on VFs.");
1206                         return -EINVAL;
1207                 }
1208         } else {
1209                 /* To no break software that set invalid mode, only display
1210                  * warning if invalid mode is used.
1211                  */
1212                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1213                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1214                     rx_mq_mode != ETH_MQ_RX_RSS) {
1215                         /* RSS together with VMDq not supported*/
1216                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1217                                      rx_mq_mode);
1218                         return -EINVAL;
1219                 }
1220
1221                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1222                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1223                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1224                                         " Due to txmode is meaningless in this"
1225                                         " driver, just ignore.",
1226                                         tx_mq_mode);
1227                 }
1228         }
1229         return 0;
1230 }
1231
1232 static int
1233 eth_igb_configure(struct rte_eth_dev *dev)
1234 {
1235         struct e1000_interrupt *intr =
1236                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1237         int ret;
1238
1239         PMD_INIT_FUNC_TRACE();
1240
1241         /* multipe queue mode checking */
1242         ret  = igb_check_mq_mode(dev);
1243         if (ret != 0) {
1244                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1245                             ret);
1246                 return ret;
1247         }
1248
1249         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1250         PMD_INIT_FUNC_TRACE();
1251
1252         return 0;
1253 }
1254
1255 static int
1256 eth_igb_start(struct rte_eth_dev *dev)
1257 {
1258         struct e1000_hw *hw =
1259                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1260         struct e1000_adapter *adapter =
1261                 E1000_DEV_PRIVATE(dev->data->dev_private);
1262         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1263         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1264         int ret, mask;
1265         uint32_t intr_vector = 0;
1266         uint32_t ctrl_ext;
1267         uint32_t *speeds;
1268         int num_speeds;
1269         bool autoneg;
1270
1271         PMD_INIT_FUNC_TRACE();
1272
1273         /* disable uio/vfio intr/eventfd mapping */
1274         rte_intr_disable(intr_handle);
1275
1276         /* Power up the phy. Needed to make the link go Up */
1277         eth_igb_dev_set_link_up(dev);
1278
1279         /*
1280          * Packet Buffer Allocation (PBA)
1281          * Writing PBA sets the receive portion of the buffer
1282          * the remainder is used for the transmit buffer.
1283          */
1284         if (hw->mac.type == e1000_82575) {
1285                 uint32_t pba;
1286
1287                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1288                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1289         }
1290
1291         /* Put the address into the Receive Address Array */
1292         e1000_rar_set(hw, hw->mac.addr, 0);
1293
1294         /* Initialize the hardware */
1295         if (igb_hardware_init(hw)) {
1296                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1297                 return -EIO;
1298         }
1299         adapter->stopped = 0;
1300
1301         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1302
1303         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1304         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1305         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1306         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1307         E1000_WRITE_FLUSH(hw);
1308
1309         /* configure PF module if SRIOV enabled */
1310         igb_pf_host_configure(dev);
1311
1312         /* check and configure queue intr-vector mapping */
1313         if ((rte_intr_cap_multiple(intr_handle) ||
1314              !RTE_ETH_DEV_SRIOV(dev).active) &&
1315             dev->data->dev_conf.intr_conf.rxq != 0) {
1316                 intr_vector = dev->data->nb_rx_queues;
1317                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1318                         return -1;
1319         }
1320
1321         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1322                 intr_handle->intr_vec =
1323                         rte_zmalloc("intr_vec",
1324                                     dev->data->nb_rx_queues * sizeof(int), 0);
1325                 if (intr_handle->intr_vec == NULL) {
1326                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1327                                      " intr_vec", dev->data->nb_rx_queues);
1328                         return -ENOMEM;
1329                 }
1330         }
1331
1332         /* confiugre msix for rx interrupt */
1333         eth_igb_configure_msix_intr(dev);
1334
1335         /* Configure for OS presence */
1336         igb_init_manageability(hw);
1337
1338         eth_igb_tx_init(dev);
1339
1340         /* This can fail when allocating mbufs for descriptor rings */
1341         ret = eth_igb_rx_init(dev);
1342         if (ret) {
1343                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1344                 igb_dev_clear_queues(dev);
1345                 return ret;
1346         }
1347
1348         e1000_clear_hw_cntrs_base_generic(hw);
1349
1350         /*
1351          * VLAN Offload Settings
1352          */
1353         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1354                         ETH_VLAN_EXTEND_MASK;
1355         eth_igb_vlan_offload_set(dev, mask);
1356
1357         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1358                 /* Enable VLAN filter since VMDq always use VLAN filter */
1359                 igb_vmdq_vlan_hw_filter_enable(dev);
1360         }
1361
1362         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1363                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1364                 (hw->mac.type == e1000_i211)) {
1365                 /* Configure EITR with the maximum possible value (0xFFFF) */
1366                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1367         }
1368
1369         /* Setup link speed and duplex */
1370         speeds = &dev->data->dev_conf.link_speeds;
1371         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1372                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1373                 hw->mac.autoneg = 1;
1374         } else {
1375                 num_speeds = 0;
1376                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1377
1378                 /* Reset */
1379                 hw->phy.autoneg_advertised = 0;
1380
1381                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1382                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1383                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1384                         num_speeds = -1;
1385                         goto error_invalid_config;
1386                 }
1387                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1388                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1389                         num_speeds++;
1390                 }
1391                 if (*speeds & ETH_LINK_SPEED_10M) {
1392                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1393                         num_speeds++;
1394                 }
1395                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1396                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1397                         num_speeds++;
1398                 }
1399                 if (*speeds & ETH_LINK_SPEED_100M) {
1400                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1401                         num_speeds++;
1402                 }
1403                 if (*speeds & ETH_LINK_SPEED_1G) {
1404                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1405                         num_speeds++;
1406                 }
1407                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1408                         goto error_invalid_config;
1409
1410                 /* Set/reset the mac.autoneg based on the link speed,
1411                  * fixed or not
1412                  */
1413                 if (!autoneg) {
1414                         hw->mac.autoneg = 0;
1415                         hw->mac.forced_speed_duplex =
1416                                         hw->phy.autoneg_advertised;
1417                 } else {
1418                         hw->mac.autoneg = 1;
1419                 }
1420         }
1421
1422         e1000_setup_link(hw);
1423
1424         if (rte_intr_allow_others(intr_handle)) {
1425                 /* check if lsc interrupt is enabled */
1426                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1427                         eth_igb_lsc_interrupt_setup(dev);
1428         } else {
1429                 rte_intr_callback_unregister(intr_handle,
1430                                              eth_igb_interrupt_handler,
1431                                              (void *)dev);
1432                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1433                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1434                                      " no intr multiplex");
1435         }
1436
1437         /* check if rxq interrupt is enabled */
1438         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1439             rte_intr_dp_is_en(intr_handle))
1440                 eth_igb_rxq_interrupt_setup(dev);
1441
1442         /* enable uio/vfio intr/eventfd mapping */
1443         rte_intr_enable(intr_handle);
1444
1445         /* resume enabled intr since hw reset */
1446         igb_intr_enable(dev);
1447
1448         /* restore all types filter */
1449         igb_filter_restore(dev);
1450
1451         PMD_INIT_LOG(DEBUG, "<<");
1452
1453         return 0;
1454
1455 error_invalid_config:
1456         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1457                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1458         igb_dev_clear_queues(dev);
1459         return -EINVAL;
1460 }
1461
1462 /*********************************************************************
1463  *
1464  *  This routine disables all traffic on the adapter by issuing a
1465  *  global reset on the MAC.
1466  *
1467  **********************************************************************/
1468 static void
1469 eth_igb_stop(struct rte_eth_dev *dev)
1470 {
1471         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1472         struct e1000_filter_info *filter_info =
1473                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1474         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1475         struct rte_eth_link link;
1476         struct e1000_flex_filter *p_flex;
1477         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1478         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1479         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1480
1481         igb_intr_disable(hw);
1482
1483         /* disable intr eventfd mapping */
1484         rte_intr_disable(intr_handle);
1485
1486         igb_pf_reset_hw(hw);
1487         E1000_WRITE_REG(hw, E1000_WUC, 0);
1488
1489         /* Set bit for Go Link disconnect */
1490         if (hw->mac.type >= e1000_82580) {
1491                 uint32_t phpm_reg;
1492
1493                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1494                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1495                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1496         }
1497
1498         /* Power down the phy. Needed to make the link go Down */
1499         eth_igb_dev_set_link_down(dev);
1500
1501         igb_dev_clear_queues(dev);
1502
1503         /* clear the recorded link status */
1504         memset(&link, 0, sizeof(link));
1505         rte_igb_dev_atomic_write_link_status(dev, &link);
1506
1507         /* Remove all flex filters of the device */
1508         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1509                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1510                 rte_free(p_flex);
1511         }
1512         filter_info->flex_mask = 0;
1513
1514         /* Remove all ntuple filters of the device */
1515         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1516              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1517                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1518                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1519                              p_5tuple, entries);
1520                 rte_free(p_5tuple);
1521         }
1522         filter_info->fivetuple_mask = 0;
1523         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1524              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1525                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1526                 TAILQ_REMOVE(&filter_info->twotuple_list,
1527                              p_2tuple, entries);
1528                 rte_free(p_2tuple);
1529         }
1530         filter_info->twotuple_mask = 0;
1531
1532         if (!rte_intr_allow_others(intr_handle))
1533                 /* resume to the default handler */
1534                 rte_intr_callback_register(intr_handle,
1535                                            eth_igb_interrupt_handler,
1536                                            (void *)dev);
1537
1538         /* Clean datapath event and queue/vec mapping */
1539         rte_intr_efd_disable(intr_handle);
1540         if (intr_handle->intr_vec != NULL) {
1541                 rte_free(intr_handle->intr_vec);
1542                 intr_handle->intr_vec = NULL;
1543         }
1544 }
1545
1546 static int
1547 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1548 {
1549         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1550
1551         if (hw->phy.media_type == e1000_media_type_copper)
1552                 e1000_power_up_phy(hw);
1553         else
1554                 e1000_power_up_fiber_serdes_link(hw);
1555
1556         return 0;
1557 }
1558
1559 static int
1560 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1561 {
1562         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1563
1564         if (hw->phy.media_type == e1000_media_type_copper)
1565                 e1000_power_down_phy(hw);
1566         else
1567                 e1000_shutdown_fiber_serdes_link(hw);
1568
1569         return 0;
1570 }
1571
1572 static void
1573 eth_igb_close(struct rte_eth_dev *dev)
1574 {
1575         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1576         struct e1000_adapter *adapter =
1577                 E1000_DEV_PRIVATE(dev->data->dev_private);
1578         struct rte_eth_link link;
1579         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1580         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1581
1582         eth_igb_stop(dev);
1583         adapter->stopped = 1;
1584
1585         e1000_phy_hw_reset(hw);
1586         igb_release_manageability(hw);
1587         igb_hw_control_release(hw);
1588
1589         /* Clear bit for Go Link disconnect */
1590         if (hw->mac.type >= e1000_82580) {
1591                 uint32_t phpm_reg;
1592
1593                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1594                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1595                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1596         }
1597
1598         igb_dev_free_queues(dev);
1599
1600         if (intr_handle->intr_vec) {
1601                 rte_free(intr_handle->intr_vec);
1602                 intr_handle->intr_vec = NULL;
1603         }
1604
1605         memset(&link, 0, sizeof(link));
1606         rte_igb_dev_atomic_write_link_status(dev, &link);
1607 }
1608
1609 static int
1610 igb_get_rx_buffer_size(struct e1000_hw *hw)
1611 {
1612         uint32_t rx_buf_size;
1613         if (hw->mac.type == e1000_82576) {
1614                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1615         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1616                 /* PBS needs to be translated according to a lookup table */
1617                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1618                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1619                 rx_buf_size = (rx_buf_size << 10);
1620         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1621                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1622         } else {
1623                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1624         }
1625
1626         return rx_buf_size;
1627 }
1628
1629 /*********************************************************************
1630  *
1631  *  Initialize the hardware
1632  *
1633  **********************************************************************/
1634 static int
1635 igb_hardware_init(struct e1000_hw *hw)
1636 {
1637         uint32_t rx_buf_size;
1638         int diag;
1639
1640         /* Let the firmware know the OS is in control */
1641         igb_hw_control_acquire(hw);
1642
1643         /*
1644          * These parameters control the automatic generation (Tx) and
1645          * response (Rx) to Ethernet PAUSE frames.
1646          * - High water mark should allow for at least two standard size (1518)
1647          *   frames to be received after sending an XOFF.
1648          * - Low water mark works best when it is very near the high water mark.
1649          *   This allows the receiver to restart by sending XON when it has
1650          *   drained a bit. Here we use an arbitrary value of 1500 which will
1651          *   restart after one full frame is pulled from the buffer. There
1652          *   could be several smaller frames in the buffer and if so they will
1653          *   not trigger the XON until their total number reduces the buffer
1654          *   by 1500.
1655          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1656          */
1657         rx_buf_size = igb_get_rx_buffer_size(hw);
1658
1659         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1660         hw->fc.low_water = hw->fc.high_water - 1500;
1661         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1662         hw->fc.send_xon = 1;
1663
1664         /* Set Flow control, use the tunable location if sane */
1665         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1666                 hw->fc.requested_mode = igb_fc_setting;
1667         else
1668                 hw->fc.requested_mode = e1000_fc_none;
1669
1670         /* Issue a global reset */
1671         igb_pf_reset_hw(hw);
1672         E1000_WRITE_REG(hw, E1000_WUC, 0);
1673
1674         diag = e1000_init_hw(hw);
1675         if (diag < 0)
1676                 return diag;
1677
1678         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1679         e1000_get_phy_info(hw);
1680         e1000_check_for_link(hw);
1681
1682         return 0;
1683 }
1684
1685 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1686 static void
1687 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1688 {
1689         int pause_frames;
1690
1691         uint64_t old_gprc  = stats->gprc;
1692         uint64_t old_gptc  = stats->gptc;
1693         uint64_t old_tpr   = stats->tpr;
1694         uint64_t old_tpt   = stats->tpt;
1695         uint64_t old_rpthc = stats->rpthc;
1696         uint64_t old_hgptc = stats->hgptc;
1697
1698         if(hw->phy.media_type == e1000_media_type_copper ||
1699             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1700                 stats->symerrs +=
1701                     E1000_READ_REG(hw,E1000_SYMERRS);
1702                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1703         }
1704
1705         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1706         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1707         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1708         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1709
1710         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1711         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1712         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1713         stats->dc += E1000_READ_REG(hw, E1000_DC);
1714         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1715         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1716         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1717         /*
1718         ** For watchdog management we need to know if we have been
1719         ** paused during the last interval, so capture that here.
1720         */
1721         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1722         stats->xoffrxc += pause_frames;
1723         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1724         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1725         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1726         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1727         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1728         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1729         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1730         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1731         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1732         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1733         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1734         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1735
1736         /* For the 64-bit byte counters the low dword must be read first. */
1737         /* Both registers clear on the read of the high dword */
1738
1739         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1740         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1741         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1742         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1743         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1744         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1745         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1746
1747         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1748         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1749         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1750         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1751         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1752
1753         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1754         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1755
1756         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1757         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1758         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1759         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1760         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1761         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1762
1763         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1764         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1765         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1766         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1767         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1768         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1769         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1770         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1771
1772         /* Interrupt Counts */
1773
1774         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1775         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1776         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1777         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1778         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1779         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1780         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1781         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1782         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1783
1784         /* Host to Card Statistics */
1785
1786         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1787         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1788         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1789         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1790         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1791         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1792         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1793         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1794         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1795         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1796         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1797         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1798         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1799         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1800         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1801         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1802
1803         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1804         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1805         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1806         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1807         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1808         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1809 }
1810
1811 static void
1812 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1813 {
1814         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1815         struct e1000_hw_stats *stats =
1816                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1817
1818         igb_read_stats_registers(hw, stats);
1819
1820         if (rte_stats == NULL)
1821                 return;
1822
1823         /* Rx Errors */
1824         rte_stats->imissed = stats->mpc;
1825         rte_stats->ierrors = stats->crcerrs +
1826                              stats->rlec + stats->ruc + stats->roc +
1827                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1828
1829         /* Tx Errors */
1830         rte_stats->oerrors = stats->ecol + stats->latecol;
1831
1832         rte_stats->ipackets = stats->gprc;
1833         rte_stats->opackets = stats->gptc;
1834         rte_stats->ibytes   = stats->gorc;
1835         rte_stats->obytes   = stats->gotc;
1836 }
1837
1838 static void
1839 eth_igb_stats_reset(struct rte_eth_dev *dev)
1840 {
1841         struct e1000_hw_stats *hw_stats =
1842                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1843
1844         /* HW registers are cleared on read */
1845         eth_igb_stats_get(dev, NULL);
1846
1847         /* Reset software totals */
1848         memset(hw_stats, 0, sizeof(*hw_stats));
1849 }
1850
1851 static void
1852 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1853 {
1854         struct e1000_hw_stats *stats =
1855                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1856
1857         /* HW registers are cleared on read */
1858         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1859
1860         /* Reset software totals */
1861         memset(stats, 0, sizeof(*stats));
1862 }
1863
1864 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1865         struct rte_eth_xstat_name *xstats_names,
1866         __rte_unused unsigned int size)
1867 {
1868         unsigned i;
1869
1870         if (xstats_names == NULL)
1871                 return IGB_NB_XSTATS;
1872
1873         /* Note: limit checked in rte_eth_xstats_names() */
1874
1875         for (i = 0; i < IGB_NB_XSTATS; i++) {
1876                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1877                          "%s", rte_igb_stats_strings[i].name);
1878         }
1879
1880         return IGB_NB_XSTATS;
1881 }
1882
1883 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1884                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1885                 unsigned int limit)
1886 {
1887         unsigned int i;
1888
1889         if (!ids) {
1890                 if (xstats_names == NULL)
1891                         return IGB_NB_XSTATS;
1892
1893                 for (i = 0; i < IGB_NB_XSTATS; i++)
1894                         snprintf(xstats_names[i].name,
1895                                         sizeof(xstats_names[i].name),
1896                                         "%s", rte_igb_stats_strings[i].name);
1897
1898                 return IGB_NB_XSTATS;
1899
1900         } else {
1901                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1902
1903                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1904                                 IGB_NB_XSTATS);
1905
1906                 for (i = 0; i < limit; i++) {
1907                         if (ids[i] >= IGB_NB_XSTATS) {
1908                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1909                                 return -1;
1910                         }
1911                         strcpy(xstats_names[i].name,
1912                                         xstats_names_copy[ids[i]].name);
1913                 }
1914                 return limit;
1915         }
1916 }
1917
1918 static int
1919 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1920                    unsigned n)
1921 {
1922         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1923         struct e1000_hw_stats *hw_stats =
1924                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1925         unsigned i;
1926
1927         if (n < IGB_NB_XSTATS)
1928                 return IGB_NB_XSTATS;
1929
1930         igb_read_stats_registers(hw, hw_stats);
1931
1932         /* If this is a reset xstats is NULL, and we have cleared the
1933          * registers by reading them.
1934          */
1935         if (!xstats)
1936                 return 0;
1937
1938         /* Extended stats */
1939         for (i = 0; i < IGB_NB_XSTATS; i++) {
1940                 xstats[i].id = i;
1941                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1942                         rte_igb_stats_strings[i].offset);
1943         }
1944
1945         return IGB_NB_XSTATS;
1946 }
1947
1948 static int
1949 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1950                 uint64_t *values, unsigned int n)
1951 {
1952         unsigned int i;
1953
1954         if (!ids) {
1955                 struct e1000_hw *hw =
1956                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1957                 struct e1000_hw_stats *hw_stats =
1958                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1959
1960                 if (n < IGB_NB_XSTATS)
1961                         return IGB_NB_XSTATS;
1962
1963                 igb_read_stats_registers(hw, hw_stats);
1964
1965                 /* If this is a reset xstats is NULL, and we have cleared the
1966                  * registers by reading them.
1967                  */
1968                 if (!values)
1969                         return 0;
1970
1971                 /* Extended stats */
1972                 for (i = 0; i < IGB_NB_XSTATS; i++)
1973                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1974                                         rte_igb_stats_strings[i].offset);
1975
1976                 return IGB_NB_XSTATS;
1977
1978         } else {
1979                 uint64_t values_copy[IGB_NB_XSTATS];
1980
1981                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1982                                 IGB_NB_XSTATS);
1983
1984                 for (i = 0; i < n; i++) {
1985                         if (ids[i] >= IGB_NB_XSTATS) {
1986                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1987                                 return -1;
1988                         }
1989                         values[i] = values_copy[ids[i]];
1990                 }
1991                 return n;
1992         }
1993 }
1994
1995 static void
1996 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1997 {
1998         /* Good Rx packets, include VF loopback */
1999         UPDATE_VF_STAT(E1000_VFGPRC,
2000             hw_stats->last_gprc, hw_stats->gprc);
2001
2002         /* Good Rx octets, include VF loopback */
2003         UPDATE_VF_STAT(E1000_VFGORC,
2004             hw_stats->last_gorc, hw_stats->gorc);
2005
2006         /* Good Tx packets, include VF loopback */
2007         UPDATE_VF_STAT(E1000_VFGPTC,
2008             hw_stats->last_gptc, hw_stats->gptc);
2009
2010         /* Good Tx octets, include VF loopback */
2011         UPDATE_VF_STAT(E1000_VFGOTC,
2012             hw_stats->last_gotc, hw_stats->gotc);
2013
2014         /* Rx Multicst packets */
2015         UPDATE_VF_STAT(E1000_VFMPRC,
2016             hw_stats->last_mprc, hw_stats->mprc);
2017
2018         /* Good Rx loopback packets */
2019         UPDATE_VF_STAT(E1000_VFGPRLBC,
2020             hw_stats->last_gprlbc, hw_stats->gprlbc);
2021
2022         /* Good Rx loopback octets */
2023         UPDATE_VF_STAT(E1000_VFGORLBC,
2024             hw_stats->last_gorlbc, hw_stats->gorlbc);
2025
2026         /* Good Tx loopback packets */
2027         UPDATE_VF_STAT(E1000_VFGPTLBC,
2028             hw_stats->last_gptlbc, hw_stats->gptlbc);
2029
2030         /* Good Tx loopback octets */
2031         UPDATE_VF_STAT(E1000_VFGOTLBC,
2032             hw_stats->last_gotlbc, hw_stats->gotlbc);
2033 }
2034
2035 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2036                                      struct rte_eth_xstat_name *xstats_names,
2037                                      __rte_unused unsigned limit)
2038 {
2039         unsigned i;
2040
2041         if (xstats_names != NULL)
2042                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2043                         snprintf(xstats_names[i].name,
2044                                 sizeof(xstats_names[i].name), "%s",
2045                                 rte_igbvf_stats_strings[i].name);
2046                 }
2047         return IGBVF_NB_XSTATS;
2048 }
2049
2050 static int
2051 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2052                      unsigned n)
2053 {
2054         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2056                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2057         unsigned i;
2058
2059         if (n < IGBVF_NB_XSTATS)
2060                 return IGBVF_NB_XSTATS;
2061
2062         igbvf_read_stats_registers(hw, hw_stats);
2063
2064         if (!xstats)
2065                 return 0;
2066
2067         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2068                 xstats[i].id = i;
2069                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2070                         rte_igbvf_stats_strings[i].offset);
2071         }
2072
2073         return IGBVF_NB_XSTATS;
2074 }
2075
2076 static void
2077 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2078 {
2079         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2081                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2082
2083         igbvf_read_stats_registers(hw, hw_stats);
2084
2085         if (rte_stats == NULL)
2086                 return;
2087
2088         rte_stats->ipackets = hw_stats->gprc;
2089         rte_stats->ibytes = hw_stats->gorc;
2090         rte_stats->opackets = hw_stats->gptc;
2091         rte_stats->obytes = hw_stats->gotc;
2092 }
2093
2094 static void
2095 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2096 {
2097         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2098                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2099
2100         /* Sync HW register to the last stats */
2101         eth_igbvf_stats_get(dev, NULL);
2102
2103         /* reset HW current stats*/
2104         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2105                offsetof(struct e1000_vf_stats, gprc));
2106 }
2107
2108 static int
2109 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2110                        size_t fw_size)
2111 {
2112         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2113         struct e1000_fw_version fw;
2114         int ret;
2115
2116         e1000_get_fw_version(hw, &fw);
2117
2118         switch (hw->mac.type) {
2119         case e1000_i210:
2120         case e1000_i211:
2121                 if (!(e1000_get_flash_presence_i210(hw))) {
2122                         ret = snprintf(fw_version, fw_size,
2123                                  "%2d.%2d-%d",
2124                                  fw.invm_major, fw.invm_minor,
2125                                  fw.invm_img_type);
2126                         break;
2127                 }
2128                 /* fall through */
2129         default:
2130                 /* if option rom is valid, display its version too */
2131                 if (fw.or_valid) {
2132                         ret = snprintf(fw_version, fw_size,
2133                                  "%d.%d, 0x%08x, %d.%d.%d",
2134                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2135                                  fw.or_major, fw.or_build, fw.or_patch);
2136                 /* no option rom */
2137                 } else {
2138                         if (fw.etrack_id != 0X0000) {
2139                                 ret = snprintf(fw_version, fw_size,
2140                                          "%d.%d, 0x%08x",
2141                                          fw.eep_major, fw.eep_minor,
2142                                          fw.etrack_id);
2143                         } else {
2144                                 ret = snprintf(fw_version, fw_size,
2145                                          "%d.%d.%d",
2146                                          fw.eep_major, fw.eep_minor,
2147                                          fw.eep_build);
2148                         }
2149                 }
2150                 break;
2151         }
2152
2153         ret += 1; /* add the size of '\0' */
2154         if (fw_size < (u32)ret)
2155                 return ret;
2156         else
2157                 return 0;
2158 }
2159
2160 static void
2161 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2162 {
2163         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164
2165         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2166         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2167         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2168         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2169         dev_info->rx_offload_capa =
2170                 DEV_RX_OFFLOAD_VLAN_STRIP |
2171                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2172                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2173                 DEV_RX_OFFLOAD_TCP_CKSUM;
2174         dev_info->tx_offload_capa =
2175                 DEV_TX_OFFLOAD_VLAN_INSERT |
2176                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2177                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2178                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2179                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2180                 DEV_TX_OFFLOAD_TCP_TSO;
2181
2182         switch (hw->mac.type) {
2183         case e1000_82575:
2184                 dev_info->max_rx_queues = 4;
2185                 dev_info->max_tx_queues = 4;
2186                 dev_info->max_vmdq_pools = 0;
2187                 break;
2188
2189         case e1000_82576:
2190                 dev_info->max_rx_queues = 16;
2191                 dev_info->max_tx_queues = 16;
2192                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2193                 dev_info->vmdq_queue_num = 16;
2194                 break;
2195
2196         case e1000_82580:
2197                 dev_info->max_rx_queues = 8;
2198                 dev_info->max_tx_queues = 8;
2199                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2200                 dev_info->vmdq_queue_num = 8;
2201                 break;
2202
2203         case e1000_i350:
2204                 dev_info->max_rx_queues = 8;
2205                 dev_info->max_tx_queues = 8;
2206                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2207                 dev_info->vmdq_queue_num = 8;
2208                 break;
2209
2210         case e1000_i354:
2211                 dev_info->max_rx_queues = 8;
2212                 dev_info->max_tx_queues = 8;
2213                 break;
2214
2215         case e1000_i210:
2216                 dev_info->max_rx_queues = 4;
2217                 dev_info->max_tx_queues = 4;
2218                 dev_info->max_vmdq_pools = 0;
2219                 break;
2220
2221         case e1000_i211:
2222                 dev_info->max_rx_queues = 2;
2223                 dev_info->max_tx_queues = 2;
2224                 dev_info->max_vmdq_pools = 0;
2225                 break;
2226
2227         default:
2228                 /* Should not happen */
2229                 break;
2230         }
2231         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2232         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2233         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2234
2235         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2236                 .rx_thresh = {
2237                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2238                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2239                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2240                 },
2241                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2242                 .rx_drop_en = 0,
2243         };
2244
2245         dev_info->default_txconf = (struct rte_eth_txconf) {
2246                 .tx_thresh = {
2247                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2248                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2249                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2250                 },
2251                 .txq_flags = 0,
2252         };
2253
2254         dev_info->rx_desc_lim = rx_desc_lim;
2255         dev_info->tx_desc_lim = tx_desc_lim;
2256
2257         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2258                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2259                         ETH_LINK_SPEED_1G;
2260 }
2261
2262 static const uint32_t *
2263 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2264 {
2265         static const uint32_t ptypes[] = {
2266                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2267                 RTE_PTYPE_L2_ETHER,
2268                 RTE_PTYPE_L3_IPV4,
2269                 RTE_PTYPE_L3_IPV4_EXT,
2270                 RTE_PTYPE_L3_IPV6,
2271                 RTE_PTYPE_L3_IPV6_EXT,
2272                 RTE_PTYPE_L4_TCP,
2273                 RTE_PTYPE_L4_UDP,
2274                 RTE_PTYPE_L4_SCTP,
2275                 RTE_PTYPE_TUNNEL_IP,
2276                 RTE_PTYPE_INNER_L3_IPV6,
2277                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2278                 RTE_PTYPE_INNER_L4_TCP,
2279                 RTE_PTYPE_INNER_L4_UDP,
2280                 RTE_PTYPE_UNKNOWN
2281         };
2282
2283         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2284             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2285                 return ptypes;
2286         return NULL;
2287 }
2288
2289 static void
2290 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2291 {
2292         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2293
2294         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2295         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2296         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2297         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2298         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2299                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2300                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2301                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2302         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2303                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2304                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2305                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2306                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2307                                 DEV_TX_OFFLOAD_TCP_TSO;
2308         switch (hw->mac.type) {
2309         case e1000_vfadapt:
2310                 dev_info->max_rx_queues = 2;
2311                 dev_info->max_tx_queues = 2;
2312                 break;
2313         case e1000_vfadapt_i350:
2314                 dev_info->max_rx_queues = 1;
2315                 dev_info->max_tx_queues = 1;
2316                 break;
2317         default:
2318                 /* Should not happen */
2319                 break;
2320         }
2321
2322         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2323                 .rx_thresh = {
2324                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2325                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2326                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2327                 },
2328                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2329                 .rx_drop_en = 0,
2330         };
2331
2332         dev_info->default_txconf = (struct rte_eth_txconf) {
2333                 .tx_thresh = {
2334                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2335                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2336                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2337                 },
2338                 .txq_flags = 0,
2339         };
2340
2341         dev_info->rx_desc_lim = rx_desc_lim;
2342         dev_info->tx_desc_lim = tx_desc_lim;
2343 }
2344
2345 /* return 0 means link status changed, -1 means not changed */
2346 static int
2347 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2348 {
2349         struct e1000_hw *hw =
2350                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2351         struct rte_eth_link link, old;
2352         int link_check, count;
2353
2354         link_check = 0;
2355         hw->mac.get_link_status = 1;
2356
2357         /* possible wait-to-complete in up to 9 seconds */
2358         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2359                 /* Read the real link status */
2360                 switch (hw->phy.media_type) {
2361                 case e1000_media_type_copper:
2362                         /* Do the work to read phy */
2363                         e1000_check_for_link(hw);
2364                         link_check = !hw->mac.get_link_status;
2365                         break;
2366
2367                 case e1000_media_type_fiber:
2368                         e1000_check_for_link(hw);
2369                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2370                                       E1000_STATUS_LU);
2371                         break;
2372
2373                 case e1000_media_type_internal_serdes:
2374                         e1000_check_for_link(hw);
2375                         link_check = hw->mac.serdes_has_link;
2376                         break;
2377
2378                 /* VF device is type_unknown */
2379                 case e1000_media_type_unknown:
2380                         eth_igbvf_link_update(hw);
2381                         link_check = !hw->mac.get_link_status;
2382                         break;
2383
2384                 default:
2385                         break;
2386                 }
2387                 if (link_check || wait_to_complete == 0)
2388                         break;
2389                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2390         }
2391         memset(&link, 0, sizeof(link));
2392         rte_igb_dev_atomic_read_link_status(dev, &link);
2393         old = link;
2394
2395         /* Now we check if a transition has happened */
2396         if (link_check) {
2397                 uint16_t duplex, speed;
2398                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2399                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2400                                 ETH_LINK_FULL_DUPLEX :
2401                                 ETH_LINK_HALF_DUPLEX;
2402                 link.link_speed = speed;
2403                 link.link_status = ETH_LINK_UP;
2404                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2405                                 ETH_LINK_SPEED_FIXED);
2406         } else if (!link_check) {
2407                 link.link_speed = 0;
2408                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2409                 link.link_status = ETH_LINK_DOWN;
2410                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2411         }
2412         rte_igb_dev_atomic_write_link_status(dev, &link);
2413
2414         /* not changed */
2415         if (old.link_status == link.link_status)
2416                 return -1;
2417
2418         /* changed */
2419         return 0;
2420 }
2421
2422 /*
2423  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2424  * For ASF and Pass Through versions of f/w this means
2425  * that the driver is loaded.
2426  */
2427 static void
2428 igb_hw_control_acquire(struct e1000_hw *hw)
2429 {
2430         uint32_t ctrl_ext;
2431
2432         /* Let firmware know the driver has taken over */
2433         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2434         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2435 }
2436
2437 /*
2438  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2439  * For ASF and Pass Through versions of f/w this means that the
2440  * driver is no longer loaded.
2441  */
2442 static void
2443 igb_hw_control_release(struct e1000_hw *hw)
2444 {
2445         uint32_t ctrl_ext;
2446
2447         /* Let firmware taken over control of h/w */
2448         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2449         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2450                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2451 }
2452
2453 /*
2454  * Bit of a misnomer, what this really means is
2455  * to enable OS management of the system... aka
2456  * to disable special hardware management features.
2457  */
2458 static void
2459 igb_init_manageability(struct e1000_hw *hw)
2460 {
2461         if (e1000_enable_mng_pass_thru(hw)) {
2462                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2463                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2464
2465                 /* disable hardware interception of ARP */
2466                 manc &= ~(E1000_MANC_ARP_EN);
2467
2468                 /* enable receiving management packets to the host */
2469                 manc |= E1000_MANC_EN_MNG2HOST;
2470                 manc2h |= 1 << 5;  /* Mng Port 623 */
2471                 manc2h |= 1 << 6;  /* Mng Port 664 */
2472                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2473                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2474         }
2475 }
2476
2477 static void
2478 igb_release_manageability(struct e1000_hw *hw)
2479 {
2480         if (e1000_enable_mng_pass_thru(hw)) {
2481                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2482
2483                 manc |= E1000_MANC_ARP_EN;
2484                 manc &= ~E1000_MANC_EN_MNG2HOST;
2485
2486                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2487         }
2488 }
2489
2490 static void
2491 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2492 {
2493         struct e1000_hw *hw =
2494                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2495         uint32_t rctl;
2496
2497         rctl = E1000_READ_REG(hw, E1000_RCTL);
2498         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2499         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2500 }
2501
2502 static void
2503 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2504 {
2505         struct e1000_hw *hw =
2506                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2507         uint32_t rctl;
2508
2509         rctl = E1000_READ_REG(hw, E1000_RCTL);
2510         rctl &= (~E1000_RCTL_UPE);
2511         if (dev->data->all_multicast == 1)
2512                 rctl |= E1000_RCTL_MPE;
2513         else
2514                 rctl &= (~E1000_RCTL_MPE);
2515         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2516 }
2517
2518 static void
2519 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2520 {
2521         struct e1000_hw *hw =
2522                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523         uint32_t rctl;
2524
2525         rctl = E1000_READ_REG(hw, E1000_RCTL);
2526         rctl |= E1000_RCTL_MPE;
2527         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2528 }
2529
2530 static void
2531 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2532 {
2533         struct e1000_hw *hw =
2534                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2535         uint32_t rctl;
2536
2537         if (dev->data->promiscuous == 1)
2538                 return; /* must remain in all_multicast mode */
2539         rctl = E1000_READ_REG(hw, E1000_RCTL);
2540         rctl &= (~E1000_RCTL_MPE);
2541         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2542 }
2543
2544 static int
2545 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2546 {
2547         struct e1000_hw *hw =
2548                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2549         struct e1000_vfta * shadow_vfta =
2550                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2551         uint32_t vfta;
2552         uint32_t vid_idx;
2553         uint32_t vid_bit;
2554
2555         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2556                               E1000_VFTA_ENTRY_MASK);
2557         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2558         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2559         if (on)
2560                 vfta |= vid_bit;
2561         else
2562                 vfta &= ~vid_bit;
2563         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2564
2565         /* update local VFTA copy */
2566         shadow_vfta->vfta[vid_idx] = vfta;
2567
2568         return 0;
2569 }
2570
2571 static int
2572 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2573                       enum rte_vlan_type vlan_type,
2574                       uint16_t tpid)
2575 {
2576         struct e1000_hw *hw =
2577                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2578         uint32_t reg, qinq;
2579
2580         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2581         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2582
2583         /* only outer TPID of double VLAN can be configured*/
2584         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2585                 reg = E1000_READ_REG(hw, E1000_VET);
2586                 reg = (reg & (~E1000_VET_VET_EXT)) |
2587                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2588                 E1000_WRITE_REG(hw, E1000_VET, reg);
2589
2590                 return 0;
2591         }
2592
2593         /* all other TPID values are read-only*/
2594         PMD_DRV_LOG(ERR, "Not supported");
2595
2596         return -ENOTSUP;
2597 }
2598
2599 static void
2600 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2601 {
2602         struct e1000_hw *hw =
2603                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2604         uint32_t reg;
2605
2606         /* Filter Table Disable */
2607         reg = E1000_READ_REG(hw, E1000_RCTL);
2608         reg &= ~E1000_RCTL_CFIEN;
2609         reg &= ~E1000_RCTL_VFE;
2610         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2611 }
2612
2613 static void
2614 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2615 {
2616         struct e1000_hw *hw =
2617                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2618         struct e1000_vfta * shadow_vfta =
2619                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2620         uint32_t reg;
2621         int i;
2622
2623         /* Filter Table Enable, CFI not used for packet acceptance */
2624         reg = E1000_READ_REG(hw, E1000_RCTL);
2625         reg &= ~E1000_RCTL_CFIEN;
2626         reg |= E1000_RCTL_VFE;
2627         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2628
2629         /* restore VFTA table */
2630         for (i = 0; i < IGB_VFTA_SIZE; i++)
2631                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2632 }
2633
2634 static void
2635 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2636 {
2637         struct e1000_hw *hw =
2638                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2639         uint32_t reg;
2640
2641         /* VLAN Mode Disable */
2642         reg = E1000_READ_REG(hw, E1000_CTRL);
2643         reg &= ~E1000_CTRL_VME;
2644         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2645 }
2646
2647 static void
2648 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2649 {
2650         struct e1000_hw *hw =
2651                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2652         uint32_t reg;
2653
2654         /* VLAN Mode Enable */
2655         reg = E1000_READ_REG(hw, E1000_CTRL);
2656         reg |= E1000_CTRL_VME;
2657         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2658 }
2659
2660 static void
2661 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2662 {
2663         struct e1000_hw *hw =
2664                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2665         uint32_t reg;
2666
2667         /* CTRL_EXT: Extended VLAN */
2668         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2669         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2670         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2671
2672         /* Update maximum packet length */
2673         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2674                 E1000_WRITE_REG(hw, E1000_RLPML,
2675                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2676                                                 VLAN_TAG_SIZE);
2677 }
2678
2679 static void
2680 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2681 {
2682         struct e1000_hw *hw =
2683                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2684         uint32_t reg;
2685
2686         /* CTRL_EXT: Extended VLAN */
2687         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2688         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2689         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2690
2691         /* Update maximum packet length */
2692         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2693                 E1000_WRITE_REG(hw, E1000_RLPML,
2694                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2695                                                 2 * VLAN_TAG_SIZE);
2696 }
2697
2698 static void
2699 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2700 {
2701         if(mask & ETH_VLAN_STRIP_MASK){
2702                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2703                         igb_vlan_hw_strip_enable(dev);
2704                 else
2705                         igb_vlan_hw_strip_disable(dev);
2706         }
2707
2708         if(mask & ETH_VLAN_FILTER_MASK){
2709                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2710                         igb_vlan_hw_filter_enable(dev);
2711                 else
2712                         igb_vlan_hw_filter_disable(dev);
2713         }
2714
2715         if(mask & ETH_VLAN_EXTEND_MASK){
2716                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2717                         igb_vlan_hw_extend_enable(dev);
2718                 else
2719                         igb_vlan_hw_extend_disable(dev);
2720         }
2721 }
2722
2723
2724 /**
2725  * It enables the interrupt mask and then enable the interrupt.
2726  *
2727  * @param dev
2728  *  Pointer to struct rte_eth_dev.
2729  *
2730  * @return
2731  *  - On success, zero.
2732  *  - On failure, a negative value.
2733  */
2734 static int
2735 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2736 {
2737         struct e1000_interrupt *intr =
2738                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2739
2740         intr->mask |= E1000_ICR_LSC;
2741
2742         return 0;
2743 }
2744
2745 /* It clears the interrupt causes and enables the interrupt.
2746  * It will be called once only during nic initialized.
2747  *
2748  * @param dev
2749  *  Pointer to struct rte_eth_dev.
2750  *
2751  * @return
2752  *  - On success, zero.
2753  *  - On failure, a negative value.
2754  */
2755 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2756 {
2757         uint32_t mask, regval;
2758         struct e1000_hw *hw =
2759                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2760         struct rte_eth_dev_info dev_info;
2761
2762         memset(&dev_info, 0, sizeof(dev_info));
2763         eth_igb_infos_get(dev, &dev_info);
2764
2765         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2766         regval = E1000_READ_REG(hw, E1000_EIMS);
2767         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2768
2769         return 0;
2770 }
2771
2772 /*
2773  * It reads ICR and gets interrupt causes, check it and set a bit flag
2774  * to update link status.
2775  *
2776  * @param dev
2777  *  Pointer to struct rte_eth_dev.
2778  *
2779  * @return
2780  *  - On success, zero.
2781  *  - On failure, a negative value.
2782  */
2783 static int
2784 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2785 {
2786         uint32_t icr;
2787         struct e1000_hw *hw =
2788                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2789         struct e1000_interrupt *intr =
2790                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2791
2792         igb_intr_disable(hw);
2793
2794         /* read-on-clear nic registers here */
2795         icr = E1000_READ_REG(hw, E1000_ICR);
2796
2797         intr->flags = 0;
2798         if (icr & E1000_ICR_LSC) {
2799                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2800         }
2801
2802         if (icr & E1000_ICR_VMMB)
2803                 intr->flags |= E1000_FLAG_MAILBOX;
2804
2805         return 0;
2806 }
2807
2808 /*
2809  * It executes link_update after knowing an interrupt is prsent.
2810  *
2811  * @param dev
2812  *  Pointer to struct rte_eth_dev.
2813  *
2814  * @return
2815  *  - On success, zero.
2816  *  - On failure, a negative value.
2817  */
2818 static int
2819 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2820                          struct rte_intr_handle *intr_handle)
2821 {
2822         struct e1000_hw *hw =
2823                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2824         struct e1000_interrupt *intr =
2825                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2826         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2827         uint32_t tctl, rctl;
2828         struct rte_eth_link link;
2829         int ret;
2830
2831         if (intr->flags & E1000_FLAG_MAILBOX) {
2832                 igb_pf_mbx_process(dev);
2833                 intr->flags &= ~E1000_FLAG_MAILBOX;
2834         }
2835
2836         igb_intr_enable(dev);
2837         rte_intr_enable(intr_handle);
2838
2839         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2840                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2841
2842                 /* set get_link_status to check register later */
2843                 hw->mac.get_link_status = 1;
2844                 ret = eth_igb_link_update(dev, 0);
2845
2846                 /* check if link has changed */
2847                 if (ret < 0)
2848                         return 0;
2849
2850                 memset(&link, 0, sizeof(link));
2851                 rte_igb_dev_atomic_read_link_status(dev, &link);
2852                 if (link.link_status) {
2853                         PMD_INIT_LOG(INFO,
2854                                      " Port %d: Link Up - speed %u Mbps - %s",
2855                                      dev->data->port_id,
2856                                      (unsigned)link.link_speed,
2857                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2858                                      "full-duplex" : "half-duplex");
2859                 } else {
2860                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2861                                      dev->data->port_id);
2862                 }
2863
2864                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2865                              pci_dev->addr.domain,
2866                              pci_dev->addr.bus,
2867                              pci_dev->addr.devid,
2868                              pci_dev->addr.function);
2869                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2870                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2871                 if (link.link_status) {
2872                         /* enable Tx/Rx */
2873                         tctl |= E1000_TCTL_EN;
2874                         rctl |= E1000_RCTL_EN;
2875                 } else {
2876                         /* disable Tx/Rx */
2877                         tctl &= ~E1000_TCTL_EN;
2878                         rctl &= ~E1000_RCTL_EN;
2879                 }
2880                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2881                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2882                 E1000_WRITE_FLUSH(hw);
2883                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2884         }
2885
2886         return 0;
2887 }
2888
2889 /**
2890  * Interrupt handler which shall be registered at first.
2891  *
2892  * @param handle
2893  *  Pointer to interrupt handle.
2894  * @param param
2895  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2896  *
2897  * @return
2898  *  void
2899  */
2900 static void
2901 eth_igb_interrupt_handler(void *param)
2902 {
2903         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2904
2905         eth_igb_interrupt_get_status(dev);
2906         eth_igb_interrupt_action(dev, dev->intr_handle);
2907 }
2908
2909 static int
2910 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2911 {
2912         uint32_t eicr;
2913         struct e1000_hw *hw =
2914                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2915         struct e1000_interrupt *intr =
2916                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2917
2918         igbvf_intr_disable(hw);
2919
2920         /* read-on-clear nic registers here */
2921         eicr = E1000_READ_REG(hw, E1000_EICR);
2922         intr->flags = 0;
2923
2924         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2925                 intr->flags |= E1000_FLAG_MAILBOX;
2926
2927         return 0;
2928 }
2929
2930 void igbvf_mbx_process(struct rte_eth_dev *dev)
2931 {
2932         struct e1000_hw *hw =
2933                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2934         struct e1000_mbx_info *mbx = &hw->mbx;
2935         u32 in_msg = 0;
2936
2937         if (mbx->ops.read(hw, &in_msg, 1, 0))
2938                 return;
2939
2940         /* PF reset VF event */
2941         if (in_msg == E1000_PF_CONTROL_MSG)
2942                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2943 }
2944
2945 static int
2946 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2947 {
2948         struct e1000_interrupt *intr =
2949                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2950
2951         if (intr->flags & E1000_FLAG_MAILBOX) {
2952                 igbvf_mbx_process(dev);
2953                 intr->flags &= ~E1000_FLAG_MAILBOX;
2954         }
2955
2956         igbvf_intr_enable(dev);
2957         rte_intr_enable(intr_handle);
2958
2959         return 0;
2960 }
2961
2962 static void
2963 eth_igbvf_interrupt_handler(void *param)
2964 {
2965         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2966
2967         eth_igbvf_interrupt_get_status(dev);
2968         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2969 }
2970
2971 static int
2972 eth_igb_led_on(struct rte_eth_dev *dev)
2973 {
2974         struct e1000_hw *hw;
2975
2976         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2977         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2978 }
2979
2980 static int
2981 eth_igb_led_off(struct rte_eth_dev *dev)
2982 {
2983         struct e1000_hw *hw;
2984
2985         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2986         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2987 }
2988
2989 static int
2990 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2991 {
2992         struct e1000_hw *hw;
2993         uint32_t ctrl;
2994         int tx_pause;
2995         int rx_pause;
2996
2997         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2998         fc_conf->pause_time = hw->fc.pause_time;
2999         fc_conf->high_water = hw->fc.high_water;
3000         fc_conf->low_water = hw->fc.low_water;
3001         fc_conf->send_xon = hw->fc.send_xon;
3002         fc_conf->autoneg = hw->mac.autoneg;
3003
3004         /*
3005          * Return rx_pause and tx_pause status according to actual setting of
3006          * the TFCE and RFCE bits in the CTRL register.
3007          */
3008         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3009         if (ctrl & E1000_CTRL_TFCE)
3010                 tx_pause = 1;
3011         else
3012                 tx_pause = 0;
3013
3014         if (ctrl & E1000_CTRL_RFCE)
3015                 rx_pause = 1;
3016         else
3017                 rx_pause = 0;
3018
3019         if (rx_pause && tx_pause)
3020                 fc_conf->mode = RTE_FC_FULL;
3021         else if (rx_pause)
3022                 fc_conf->mode = RTE_FC_RX_PAUSE;
3023         else if (tx_pause)
3024                 fc_conf->mode = RTE_FC_TX_PAUSE;
3025         else
3026                 fc_conf->mode = RTE_FC_NONE;
3027
3028         return 0;
3029 }
3030
3031 static int
3032 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3033 {
3034         struct e1000_hw *hw;
3035         int err;
3036         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3037                 e1000_fc_none,
3038                 e1000_fc_rx_pause,
3039                 e1000_fc_tx_pause,
3040                 e1000_fc_full
3041         };
3042         uint32_t rx_buf_size;
3043         uint32_t max_high_water;
3044         uint32_t rctl;
3045
3046         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3047         if (fc_conf->autoneg != hw->mac.autoneg)
3048                 return -ENOTSUP;
3049         rx_buf_size = igb_get_rx_buffer_size(hw);
3050         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3051
3052         /* At least reserve one Ethernet frame for watermark */
3053         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3054         if ((fc_conf->high_water > max_high_water) ||
3055             (fc_conf->high_water < fc_conf->low_water)) {
3056                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3057                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3058                 return -EINVAL;
3059         }
3060
3061         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3062         hw->fc.pause_time     = fc_conf->pause_time;
3063         hw->fc.high_water     = fc_conf->high_water;
3064         hw->fc.low_water      = fc_conf->low_water;
3065         hw->fc.send_xon       = fc_conf->send_xon;
3066
3067         err = e1000_setup_link_generic(hw);
3068         if (err == E1000_SUCCESS) {
3069
3070                 /* check if we want to forward MAC frames - driver doesn't have native
3071                  * capability to do that, so we'll write the registers ourselves */
3072
3073                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3074
3075                 /* set or clear MFLCN.PMCF bit depending on configuration */
3076                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3077                         rctl |= E1000_RCTL_PMCF;
3078                 else
3079                         rctl &= ~E1000_RCTL_PMCF;
3080
3081                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3082                 E1000_WRITE_FLUSH(hw);
3083
3084                 return 0;
3085         }
3086
3087         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3088         return -EIO;
3089 }
3090
3091 #define E1000_RAH_POOLSEL_SHIFT      (18)
3092 static int
3093 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3094                 uint32_t index, uint32_t pool)
3095 {
3096         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3097         uint32_t rah;
3098
3099         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3100         rah = E1000_READ_REG(hw, E1000_RAH(index));
3101         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3102         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3103         return 0;
3104 }
3105
3106 static void
3107 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3108 {
3109         uint8_t addr[ETHER_ADDR_LEN];
3110         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3111
3112         memset(addr, 0, sizeof(addr));
3113
3114         e1000_rar_set(hw, addr, index);
3115 }
3116
3117 static void
3118 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3119                                 struct ether_addr *addr)
3120 {
3121         eth_igb_rar_clear(dev, 0);
3122
3123         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3124 }
3125 /*
3126  * Virtual Function operations
3127  */
3128 static void
3129 igbvf_intr_disable(struct e1000_hw *hw)
3130 {
3131         PMD_INIT_FUNC_TRACE();
3132
3133         /* Clear interrupt mask to stop from interrupts being generated */
3134         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3135
3136         E1000_WRITE_FLUSH(hw);
3137 }
3138
3139 static void
3140 igbvf_stop_adapter(struct rte_eth_dev *dev)
3141 {
3142         u32 reg_val;
3143         u16 i;
3144         struct rte_eth_dev_info dev_info;
3145         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3146
3147         memset(&dev_info, 0, sizeof(dev_info));
3148         eth_igbvf_infos_get(dev, &dev_info);
3149
3150         /* Clear interrupt mask to stop from interrupts being generated */
3151         igbvf_intr_disable(hw);
3152
3153         /* Clear any pending interrupts, flush previous writes */
3154         E1000_READ_REG(hw, E1000_EICR);
3155
3156         /* Disable the transmit unit.  Each queue must be disabled. */
3157         for (i = 0; i < dev_info.max_tx_queues; i++)
3158                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3159
3160         /* Disable the receive unit by stopping each queue */
3161         for (i = 0; i < dev_info.max_rx_queues; i++) {
3162                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3163                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3164                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3165                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3166                         ;
3167         }
3168
3169         /* flush all queues disables */
3170         E1000_WRITE_FLUSH(hw);
3171         msec_delay(2);
3172 }
3173
3174 static int eth_igbvf_link_update(struct e1000_hw *hw)
3175 {
3176         struct e1000_mbx_info *mbx = &hw->mbx;
3177         struct e1000_mac_info *mac = &hw->mac;
3178         int ret_val = E1000_SUCCESS;
3179
3180         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3181
3182         /*
3183          * We only want to run this if there has been a rst asserted.
3184          * in this case that could mean a link change, device reset,
3185          * or a virtual function reset
3186          */
3187
3188         /* If we were hit with a reset or timeout drop the link */
3189         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3190                 mac->get_link_status = TRUE;
3191
3192         if (!mac->get_link_status)
3193                 goto out;
3194
3195         /* if link status is down no point in checking to see if pf is up */
3196         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3197                 goto out;
3198
3199         /* if we passed all the tests above then the link is up and we no
3200          * longer need to check for link */
3201         mac->get_link_status = FALSE;
3202
3203 out:
3204         return ret_val;
3205 }
3206
3207
3208 static int
3209 igbvf_dev_configure(struct rte_eth_dev *dev)
3210 {
3211         struct rte_eth_conf* conf = &dev->data->dev_conf;
3212
3213         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3214                      dev->data->port_id);
3215
3216         /*
3217          * VF has no ability to enable/disable HW CRC
3218          * Keep the persistent behavior the same as Host PF
3219          */
3220 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3221         if (!conf->rxmode.hw_strip_crc) {
3222                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3223                 conf->rxmode.hw_strip_crc = 1;
3224         }
3225 #else
3226         if (conf->rxmode.hw_strip_crc) {
3227                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3228                 conf->rxmode.hw_strip_crc = 0;
3229         }
3230 #endif
3231
3232         return 0;
3233 }
3234
3235 static int
3236 igbvf_dev_start(struct rte_eth_dev *dev)
3237 {
3238         struct e1000_hw *hw =
3239                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3240         struct e1000_adapter *adapter =
3241                 E1000_DEV_PRIVATE(dev->data->dev_private);
3242         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3243         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3244         int ret;
3245         uint32_t intr_vector = 0;
3246
3247         PMD_INIT_FUNC_TRACE();
3248
3249         hw->mac.ops.reset_hw(hw);
3250         adapter->stopped = 0;
3251
3252         /* Set all vfta */
3253         igbvf_set_vfta_all(dev,1);
3254
3255         eth_igbvf_tx_init(dev);
3256
3257         /* This can fail when allocating mbufs for descriptor rings */
3258         ret = eth_igbvf_rx_init(dev);
3259         if (ret) {
3260                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3261                 igb_dev_clear_queues(dev);
3262                 return ret;
3263         }
3264
3265         /* check and configure queue intr-vector mapping */
3266         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3267                 intr_vector = dev->data->nb_rx_queues;
3268                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3269                 if (ret)
3270                         return ret;
3271         }
3272
3273         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3274                 intr_handle->intr_vec =
3275                         rte_zmalloc("intr_vec",
3276                                     dev->data->nb_rx_queues * sizeof(int), 0);
3277                 if (!intr_handle->intr_vec) {
3278                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3279                                      " intr_vec", dev->data->nb_rx_queues);
3280                         return -ENOMEM;
3281                 }
3282         }
3283
3284         eth_igbvf_configure_msix_intr(dev);
3285
3286         /* enable uio/vfio intr/eventfd mapping */
3287         rte_intr_enable(intr_handle);
3288
3289         /* resume enabled intr since hw reset */
3290         igbvf_intr_enable(dev);
3291
3292         return 0;
3293 }
3294
3295 static void
3296 igbvf_dev_stop(struct rte_eth_dev *dev)
3297 {
3298         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3299         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3300
3301         PMD_INIT_FUNC_TRACE();
3302
3303         igbvf_stop_adapter(dev);
3304
3305         /*
3306           * Clear what we set, but we still keep shadow_vfta to
3307           * restore after device starts
3308           */
3309         igbvf_set_vfta_all(dev,0);
3310
3311         igb_dev_clear_queues(dev);
3312
3313         /* disable intr eventfd mapping */
3314         rte_intr_disable(intr_handle);
3315
3316         /* Clean datapath event and queue/vec mapping */
3317         rte_intr_efd_disable(intr_handle);
3318         if (intr_handle->intr_vec) {
3319                 rte_free(intr_handle->intr_vec);
3320                 intr_handle->intr_vec = NULL;
3321         }
3322 }
3323
3324 static void
3325 igbvf_dev_close(struct rte_eth_dev *dev)
3326 {
3327         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3328         struct e1000_adapter *adapter =
3329                 E1000_DEV_PRIVATE(dev->data->dev_private);
3330         struct ether_addr addr;
3331
3332         PMD_INIT_FUNC_TRACE();
3333
3334         e1000_reset_hw(hw);
3335
3336         igbvf_dev_stop(dev);
3337         adapter->stopped = 1;
3338         igb_dev_free_queues(dev);
3339
3340         /**
3341          * reprogram the RAR with a zero mac address,
3342          * to ensure that the VF traffic goes to the PF
3343          * after stop, close and detach of the VF.
3344          **/
3345
3346         memset(&addr, 0, sizeof(addr));
3347         igbvf_default_mac_addr_set(dev, &addr);
3348 }
3349
3350 static void
3351 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3352 {
3353         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3354
3355         /* Set both unicast and multicast promisc */
3356         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3357 }
3358
3359 static void
3360 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3361 {
3362         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3363
3364         /* If in allmulticast mode leave multicast promisc */
3365         if (dev->data->all_multicast == 1)
3366                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3367         else
3368                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3369 }
3370
3371 static void
3372 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3373 {
3374         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3375
3376         /* In promiscuous mode multicast promisc already set */
3377         if (dev->data->promiscuous == 0)
3378                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3379 }
3380
3381 static void
3382 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3383 {
3384         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3385
3386         /* In promiscuous mode leave multicast promisc enabled */
3387         if (dev->data->promiscuous == 0)
3388                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3389 }
3390
3391 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3392 {
3393         struct e1000_mbx_info *mbx = &hw->mbx;
3394         uint32_t msgbuf[2];
3395         s32 err;
3396
3397         /* After set vlan, vlan strip will also be enabled in igb driver*/
3398         msgbuf[0] = E1000_VF_SET_VLAN;
3399         msgbuf[1] = vid;
3400         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3401         if (on)
3402                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3403
3404         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3405         if (err)
3406                 goto mbx_err;
3407
3408         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3409         if (err)
3410                 goto mbx_err;
3411
3412         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3413         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3414                 err = -EINVAL;
3415
3416 mbx_err:
3417         return err;
3418 }
3419
3420 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3421 {
3422         struct e1000_hw *hw =
3423                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3424         struct e1000_vfta * shadow_vfta =
3425                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3426         int i = 0, j = 0, vfta = 0, mask = 1;
3427
3428         for (i = 0; i < IGB_VFTA_SIZE; i++){
3429                 vfta = shadow_vfta->vfta[i];
3430                 if(vfta){
3431                         mask = 1;
3432                         for (j = 0; j < 32; j++){
3433                                 if(vfta & mask)
3434                                         igbvf_set_vfta(hw,
3435                                                 (uint16_t)((i<<5)+j), on);
3436                                 mask<<=1;
3437                         }
3438                 }
3439         }
3440
3441 }
3442
3443 static int
3444 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3445 {
3446         struct e1000_hw *hw =
3447                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3448         struct e1000_vfta * shadow_vfta =
3449                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3450         uint32_t vid_idx = 0;
3451         uint32_t vid_bit = 0;
3452         int ret = 0;
3453
3454         PMD_INIT_FUNC_TRACE();
3455
3456         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3457         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3458         if(ret){
3459                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3460                 return ret;
3461         }
3462         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3463         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3464
3465         /*Save what we set and retore it after device reset*/
3466         if (on)
3467                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3468         else
3469                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3470
3471         return 0;
3472 }
3473
3474 static void
3475 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3476 {
3477         struct e1000_hw *hw =
3478                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3479
3480         /* index is not used by rar_set() */
3481         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3482 }
3483
3484
3485 static int
3486 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3487                         struct rte_eth_rss_reta_entry64 *reta_conf,
3488                         uint16_t reta_size)
3489 {
3490         uint8_t i, j, mask;
3491         uint32_t reta, r;
3492         uint16_t idx, shift;
3493         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3494
3495         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3496                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3497                         "(%d) doesn't match the number hardware can supported "
3498                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3499                 return -EINVAL;
3500         }
3501
3502         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3503                 idx = i / RTE_RETA_GROUP_SIZE;
3504                 shift = i % RTE_RETA_GROUP_SIZE;
3505                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3506                                                 IGB_4_BIT_MASK);
3507                 if (!mask)
3508                         continue;
3509                 if (mask == IGB_4_BIT_MASK)
3510                         r = 0;
3511                 else
3512                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3513                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3514                         if (mask & (0x1 << j))
3515                                 reta |= reta_conf[idx].reta[shift + j] <<
3516                                                         (CHAR_BIT * j);
3517                         else
3518                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3519                 }
3520                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3521         }
3522
3523         return 0;
3524 }
3525
3526 static int
3527 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3528                        struct rte_eth_rss_reta_entry64 *reta_conf,
3529                        uint16_t reta_size)
3530 {
3531         uint8_t i, j, mask;
3532         uint32_t reta;
3533         uint16_t idx, shift;
3534         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3535
3536         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3537                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3538                         "(%d) doesn't match the number hardware can supported "
3539                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3540                 return -EINVAL;
3541         }
3542
3543         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3544                 idx = i / RTE_RETA_GROUP_SIZE;
3545                 shift = i % RTE_RETA_GROUP_SIZE;
3546                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3547                                                 IGB_4_BIT_MASK);
3548                 if (!mask)
3549                         continue;
3550                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3551                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3552                         if (mask & (0x1 << j))
3553                                 reta_conf[idx].reta[shift + j] =
3554                                         ((reta >> (CHAR_BIT * j)) &
3555                                                 IGB_8_BIT_MASK);
3556                 }
3557         }
3558
3559         return 0;
3560 }
3561
3562 #define MAC_TYPE_FILTER_SUP(type)    do {\
3563         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3564                 (type) != e1000_82576 && (type) != e1000_i210 &&\
3565                 (type) != e1000_i211)\
3566                 return -ENOTSUP;\
3567 } while (0)
3568
3569 static int
3570 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3571                         struct rte_eth_syn_filter *filter,
3572                         bool add)
3573 {
3574         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3575         struct e1000_filter_info *filter_info =
3576                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3577         uint32_t synqf, rfctl;
3578
3579         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3580                 return -EINVAL;
3581
3582         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3583
3584         if (add) {
3585                 if (synqf & E1000_SYN_FILTER_ENABLE)
3586                         return -EINVAL;
3587
3588                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3589                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3590
3591                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3592                 if (filter->hig_pri)
3593                         rfctl |= E1000_RFCTL_SYNQFP;
3594                 else
3595                         rfctl &= ~E1000_RFCTL_SYNQFP;
3596
3597                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3598         } else {
3599                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3600                         return -ENOENT;
3601                 synqf = 0;
3602         }
3603
3604         filter_info->syn_info = synqf;
3605         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3606         E1000_WRITE_FLUSH(hw);
3607         return 0;
3608 }
3609
3610 static int
3611 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3612                         struct rte_eth_syn_filter *filter)
3613 {
3614         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3615         uint32_t synqf, rfctl;
3616
3617         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3618         if (synqf & E1000_SYN_FILTER_ENABLE) {
3619                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3620                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3621                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3622                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3623                 return 0;
3624         }
3625
3626         return -ENOENT;
3627 }
3628
3629 static int
3630 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3631                         enum rte_filter_op filter_op,
3632                         void *arg)
3633 {
3634         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3635         int ret;
3636
3637         MAC_TYPE_FILTER_SUP(hw->mac.type);
3638
3639         if (filter_op == RTE_ETH_FILTER_NOP)
3640                 return 0;
3641
3642         if (arg == NULL) {
3643                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3644                             filter_op);
3645                 return -EINVAL;
3646         }
3647
3648         switch (filter_op) {
3649         case RTE_ETH_FILTER_ADD:
3650                 ret = eth_igb_syn_filter_set(dev,
3651                                 (struct rte_eth_syn_filter *)arg,
3652                                 TRUE);
3653                 break;
3654         case RTE_ETH_FILTER_DELETE:
3655                 ret = eth_igb_syn_filter_set(dev,
3656                                 (struct rte_eth_syn_filter *)arg,
3657                                 FALSE);
3658                 break;
3659         case RTE_ETH_FILTER_GET:
3660                 ret = eth_igb_syn_filter_get(dev,
3661                                 (struct rte_eth_syn_filter *)arg);
3662                 break;
3663         default:
3664                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3665                 ret = -EINVAL;
3666                 break;
3667         }
3668
3669         return ret;
3670 }
3671
3672 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3673         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3674                 (type) != e1000_i210 && (type) != e1000_i211)\
3675                 return -ENOSYS; \
3676 } while (0)
3677
3678 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3679 static inline int
3680 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3681                         struct e1000_2tuple_filter_info *filter_info)
3682 {
3683         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3684                 return -EINVAL;
3685         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3686                 return -EINVAL;  /* filter index is out of range. */
3687         if (filter->tcp_flags > TCP_FLAG_ALL)
3688                 return -EINVAL;  /* flags is invalid. */
3689
3690         switch (filter->dst_port_mask) {
3691         case UINT16_MAX:
3692                 filter_info->dst_port_mask = 0;
3693                 filter_info->dst_port = filter->dst_port;
3694                 break;
3695         case 0:
3696                 filter_info->dst_port_mask = 1;
3697                 break;
3698         default:
3699                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3700                 return -EINVAL;
3701         }
3702
3703         switch (filter->proto_mask) {
3704         case UINT8_MAX:
3705                 filter_info->proto_mask = 0;
3706                 filter_info->proto = filter->proto;
3707                 break;
3708         case 0:
3709                 filter_info->proto_mask = 1;
3710                 break;
3711         default:
3712                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3713                 return -EINVAL;
3714         }
3715
3716         filter_info->priority = (uint8_t)filter->priority;
3717         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3718                 filter_info->tcp_flags = filter->tcp_flags;
3719         else
3720                 filter_info->tcp_flags = 0;
3721
3722         return 0;
3723 }
3724
3725 static inline struct e1000_2tuple_filter *
3726 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3727                         struct e1000_2tuple_filter_info *key)
3728 {
3729         struct e1000_2tuple_filter *it;
3730
3731         TAILQ_FOREACH(it, filter_list, entries) {
3732                 if (memcmp(key, &it->filter_info,
3733                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3734                         return it;
3735                 }
3736         }
3737         return NULL;
3738 }
3739
3740 /*
3741  * igb_add_2tuple_filter - add a 2tuple filter
3742  *
3743  * @param
3744  * dev: Pointer to struct rte_eth_dev.
3745  * ntuple_filter: ponter to the filter that will be added.
3746  *
3747  * @return
3748  *    - On success, zero.
3749  *    - On failure, a negative value.
3750  */
3751 static int
3752 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3753                         struct rte_eth_ntuple_filter *ntuple_filter)
3754 {
3755         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3756         struct e1000_filter_info *filter_info =
3757                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3758         struct e1000_2tuple_filter *filter;
3759         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3760         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3761         int i, ret;
3762
3763         filter = rte_zmalloc("e1000_2tuple_filter",
3764                         sizeof(struct e1000_2tuple_filter), 0);
3765         if (filter == NULL)
3766                 return -ENOMEM;
3767
3768         ret = ntuple_filter_to_2tuple(ntuple_filter,
3769                                       &filter->filter_info);
3770         if (ret < 0) {
3771                 rte_free(filter);
3772                 return ret;
3773         }
3774         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3775                                          &filter->filter_info) != NULL) {
3776                 PMD_DRV_LOG(ERR, "filter exists.");
3777                 rte_free(filter);
3778                 return -EEXIST;
3779         }
3780         filter->queue = ntuple_filter->queue;
3781
3782         /*
3783          * look for an unused 2tuple filter index,
3784          * and insert the filter to list.
3785          */
3786         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3787                 if (!(filter_info->twotuple_mask & (1 << i))) {
3788                         filter_info->twotuple_mask |= 1 << i;
3789                         filter->index = i;
3790                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3791                                           filter,
3792                                           entries);
3793                         break;
3794                 }
3795         }
3796         if (i >= E1000_MAX_TTQF_FILTERS) {
3797                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3798                 rte_free(filter);
3799                 return -ENOSYS;
3800         }
3801
3802         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3803         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3804                 imir |= E1000_IMIR_PORT_BP;
3805         else
3806                 imir &= ~E1000_IMIR_PORT_BP;
3807
3808         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3809
3810         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3811         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3812         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3813         if (filter->filter_info.proto_mask == 0)
3814                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3815
3816         /* tcp flags bits setting. */
3817         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3818                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3819                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3820                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3821                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3822                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3823                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3824                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3825                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3826                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3827                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3828                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3829                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3830         } else
3831                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3832         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3833         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3834         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3835         return 0;
3836 }
3837
3838 /*
3839  * igb_remove_2tuple_filter - remove a 2tuple filter
3840  *
3841  * @param
3842  * dev: Pointer to struct rte_eth_dev.
3843  * ntuple_filter: ponter to the filter that will be removed.
3844  *
3845  * @return
3846  *    - On success, zero.
3847  *    - On failure, a negative value.
3848  */
3849 static int
3850 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3851                         struct rte_eth_ntuple_filter *ntuple_filter)
3852 {
3853         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3854         struct e1000_filter_info *filter_info =
3855                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3856         struct e1000_2tuple_filter_info filter_2tuple;
3857         struct e1000_2tuple_filter *filter;
3858         int ret;
3859
3860         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3861         ret = ntuple_filter_to_2tuple(ntuple_filter,
3862                                       &filter_2tuple);
3863         if (ret < 0)
3864                 return ret;
3865
3866         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3867                                          &filter_2tuple);
3868         if (filter == NULL) {
3869                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3870                 return -ENOENT;
3871         }
3872
3873         filter_info->twotuple_mask &= ~(1 << filter->index);
3874         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3875         rte_free(filter);
3876
3877         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3878         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3879         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3880         return 0;
3881 }
3882
3883 static inline struct e1000_flex_filter *
3884 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3885                         struct e1000_flex_filter_info *key)
3886 {
3887         struct e1000_flex_filter *it;
3888
3889         TAILQ_FOREACH(it, filter_list, entries) {
3890                 if (memcmp(key, &it->filter_info,
3891                         sizeof(struct e1000_flex_filter_info)) == 0)
3892                         return it;
3893         }
3894
3895         return NULL;
3896 }
3897
3898 static int
3899 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3900                         struct rte_eth_flex_filter *filter,
3901                         bool add)
3902 {
3903         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3904         struct e1000_filter_info *filter_info =
3905                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3906         struct e1000_flex_filter *flex_filter, *it;
3907         uint32_t wufc, queueing, mask;
3908         uint32_t reg_off;
3909         uint8_t shift, i, j = 0;
3910
3911         flex_filter = rte_zmalloc("e1000_flex_filter",
3912                         sizeof(struct e1000_flex_filter), 0);
3913         if (flex_filter == NULL)
3914                 return -ENOMEM;
3915
3916         flex_filter->filter_info.len = filter->len;
3917         flex_filter->filter_info.priority = filter->priority;
3918         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3919         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3920                 mask = 0;
3921                 /* reverse bits in flex filter's mask*/
3922                 for (shift = 0; shift < CHAR_BIT; shift++) {
3923                         if (filter->mask[i] & (0x01 << shift))
3924                                 mask |= (0x80 >> shift);
3925                 }
3926                 flex_filter->filter_info.mask[i] = mask;
3927         }
3928
3929         wufc = E1000_READ_REG(hw, E1000_WUFC);
3930
3931         if (add) {
3932                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3933                                 &flex_filter->filter_info) != NULL) {
3934                         PMD_DRV_LOG(ERR, "filter exists.");
3935                         rte_free(flex_filter);
3936                         return -EEXIST;
3937                 }
3938                 flex_filter->queue = filter->queue;
3939                 /*
3940                  * look for an unused flex filter index
3941                  * and insert the filter into the list.
3942                  */
3943                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3944                         if (!(filter_info->flex_mask & (1 << i))) {
3945                                 filter_info->flex_mask |= 1 << i;
3946                                 flex_filter->index = i;
3947                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3948                                         flex_filter,
3949                                         entries);
3950                                 break;
3951                         }
3952                 }
3953                 if (i >= E1000_MAX_FLEX_FILTERS) {
3954                         PMD_DRV_LOG(ERR, "flex filters are full.");
3955                         rte_free(flex_filter);
3956                         return -ENOSYS;
3957                 }
3958
3959                 if (flex_filter->index < E1000_MAX_FHFT)
3960                         reg_off = E1000_FHFT(flex_filter->index);
3961                 else
3962                         reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3963
3964                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3965                                 (E1000_WUFC_FLX0 << flex_filter->index));
3966                 queueing = filter->len |
3967                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3968                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3969                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3970                                 queueing);
3971                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3972                         E1000_WRITE_REG(hw, reg_off,
3973                                         flex_filter->filter_info.dwords[j]);
3974                         reg_off += sizeof(uint32_t);
3975                         E1000_WRITE_REG(hw, reg_off,
3976                                         flex_filter->filter_info.dwords[++j]);
3977                         reg_off += sizeof(uint32_t);
3978                         E1000_WRITE_REG(hw, reg_off,
3979                                 (uint32_t)flex_filter->filter_info.mask[i]);
3980                         reg_off += sizeof(uint32_t) * 2;
3981                         ++j;
3982                 }
3983         } else {
3984                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3985                                 &flex_filter->filter_info);
3986                 if (it == NULL) {
3987                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3988                         rte_free(flex_filter);
3989                         return -ENOENT;
3990                 }
3991
3992                 if (it->index < E1000_MAX_FHFT)
3993                         reg_off = E1000_FHFT(it->index);
3994                 else
3995                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3996
3997                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3998                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3999                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4000                         (~(E1000_WUFC_FLX0 << it->index)));
4001
4002                 filter_info->flex_mask &= ~(1 << it->index);
4003                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
4004                 rte_free(it);
4005                 rte_free(flex_filter);
4006         }
4007
4008         return 0;
4009 }
4010
4011 static int
4012 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4013                         struct rte_eth_flex_filter *filter)
4014 {
4015         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4016         struct e1000_filter_info *filter_info =
4017                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4018         struct e1000_flex_filter flex_filter, *it;
4019         uint32_t wufc, queueing, wufc_en = 0;
4020
4021         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4022         flex_filter.filter_info.len = filter->len;
4023         flex_filter.filter_info.priority = filter->priority;
4024         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4025         memcpy(flex_filter.filter_info.mask, filter->mask,
4026                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
4027
4028         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4029                                 &flex_filter.filter_info);
4030         if (it == NULL) {
4031                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4032                 return -ENOENT;
4033         }
4034
4035         wufc = E1000_READ_REG(hw, E1000_WUFC);
4036         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4037
4038         if ((wufc & wufc_en) == wufc_en) {
4039                 uint32_t reg_off = 0;
4040                 if (it->index < E1000_MAX_FHFT)
4041                         reg_off = E1000_FHFT(it->index);
4042                 else
4043                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4044
4045                 queueing = E1000_READ_REG(hw,
4046                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4047                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4048                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4049                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4050                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4051                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4052                 return 0;
4053         }
4054         return -ENOENT;
4055 }
4056
4057 static int
4058 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4059                         enum rte_filter_op filter_op,
4060                         void *arg)
4061 {
4062         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4063         struct rte_eth_flex_filter *filter;
4064         int ret = 0;
4065
4066         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4067
4068         if (filter_op == RTE_ETH_FILTER_NOP)
4069                 return ret;
4070
4071         if (arg == NULL) {
4072                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4073                             filter_op);
4074                 return -EINVAL;
4075         }
4076
4077         filter = (struct rte_eth_flex_filter *)arg;
4078         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4079             || filter->len % sizeof(uint64_t) != 0) {
4080                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4081                 return -EINVAL;
4082         }
4083         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4084                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4085                 return -EINVAL;
4086         }
4087
4088         switch (filter_op) {
4089         case RTE_ETH_FILTER_ADD:
4090                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4091                 break;
4092         case RTE_ETH_FILTER_DELETE:
4093                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4094                 break;
4095         case RTE_ETH_FILTER_GET:
4096                 ret = eth_igb_get_flex_filter(dev, filter);
4097                 break;
4098         default:
4099                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4100                 ret = -EINVAL;
4101                 break;
4102         }
4103
4104         return ret;
4105 }
4106
4107 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4108 static inline int
4109 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4110                         struct e1000_5tuple_filter_info *filter_info)
4111 {
4112         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4113                 return -EINVAL;
4114         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4115                 return -EINVAL;  /* filter index is out of range. */
4116         if (filter->tcp_flags > TCP_FLAG_ALL)
4117                 return -EINVAL;  /* flags is invalid. */
4118
4119         switch (filter->dst_ip_mask) {
4120         case UINT32_MAX:
4121                 filter_info->dst_ip_mask = 0;
4122                 filter_info->dst_ip = filter->dst_ip;
4123                 break;
4124         case 0:
4125                 filter_info->dst_ip_mask = 1;
4126                 break;
4127         default:
4128                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4129                 return -EINVAL;
4130         }
4131
4132         switch (filter->src_ip_mask) {
4133         case UINT32_MAX:
4134                 filter_info->src_ip_mask = 0;
4135                 filter_info->src_ip = filter->src_ip;
4136                 break;
4137         case 0:
4138                 filter_info->src_ip_mask = 1;
4139                 break;
4140         default:
4141                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4142                 return -EINVAL;
4143         }
4144
4145         switch (filter->dst_port_mask) {
4146         case UINT16_MAX:
4147                 filter_info->dst_port_mask = 0;
4148                 filter_info->dst_port = filter->dst_port;
4149                 break;
4150         case 0:
4151                 filter_info->dst_port_mask = 1;
4152                 break;
4153         default:
4154                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4155                 return -EINVAL;
4156         }
4157
4158         switch (filter->src_port_mask) {
4159         case UINT16_MAX:
4160                 filter_info->src_port_mask = 0;
4161                 filter_info->src_port = filter->src_port;
4162                 break;
4163         case 0:
4164                 filter_info->src_port_mask = 1;
4165                 break;
4166         default:
4167                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4168                 return -EINVAL;
4169         }
4170
4171         switch (filter->proto_mask) {
4172         case UINT8_MAX:
4173                 filter_info->proto_mask = 0;
4174                 filter_info->proto = filter->proto;
4175                 break;
4176         case 0:
4177                 filter_info->proto_mask = 1;
4178                 break;
4179         default:
4180                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4181                 return -EINVAL;
4182         }
4183
4184         filter_info->priority = (uint8_t)filter->priority;
4185         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4186                 filter_info->tcp_flags = filter->tcp_flags;
4187         else
4188                 filter_info->tcp_flags = 0;
4189
4190         return 0;
4191 }
4192
4193 static inline struct e1000_5tuple_filter *
4194 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4195                         struct e1000_5tuple_filter_info *key)
4196 {
4197         struct e1000_5tuple_filter *it;
4198
4199         TAILQ_FOREACH(it, filter_list, entries) {
4200                 if (memcmp(key, &it->filter_info,
4201                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4202                         return it;
4203                 }
4204         }
4205         return NULL;
4206 }
4207
4208 /*
4209  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4210  *
4211  * @param
4212  * dev: Pointer to struct rte_eth_dev.
4213  * ntuple_filter: ponter to the filter that will be added.
4214  *
4215  * @return
4216  *    - On success, zero.
4217  *    - On failure, a negative value.
4218  */
4219 static int
4220 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4221                         struct rte_eth_ntuple_filter *ntuple_filter)
4222 {
4223         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4224         struct e1000_filter_info *filter_info =
4225                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4226         struct e1000_5tuple_filter *filter;
4227         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4228         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4229         uint8_t i;
4230         int ret;
4231
4232         filter = rte_zmalloc("e1000_5tuple_filter",
4233                         sizeof(struct e1000_5tuple_filter), 0);
4234         if (filter == NULL)
4235                 return -ENOMEM;
4236
4237         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4238                                             &filter->filter_info);
4239         if (ret < 0) {
4240                 rte_free(filter);
4241                 return ret;
4242         }
4243
4244         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4245                                          &filter->filter_info) != NULL) {
4246                 PMD_DRV_LOG(ERR, "filter exists.");
4247                 rte_free(filter);
4248                 return -EEXIST;
4249         }
4250         filter->queue = ntuple_filter->queue;
4251
4252         /*
4253          * look for an unused 5tuple filter index,
4254          * and insert the filter to list.
4255          */
4256         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4257                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4258                         filter_info->fivetuple_mask |= 1 << i;
4259                         filter->index = i;
4260                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4261                                           filter,
4262                                           entries);
4263                         break;
4264                 }
4265         }
4266         if (i >= E1000_MAX_FTQF_FILTERS) {
4267                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4268                 rte_free(filter);
4269                 return -ENOSYS;
4270         }
4271
4272         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4273         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4274                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4275         if (filter->filter_info.dst_ip_mask == 0)
4276                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4277         if (filter->filter_info.src_port_mask == 0)
4278                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4279         if (filter->filter_info.proto_mask == 0)
4280                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4281         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4282                 E1000_FTQF_QUEUE_MASK;
4283         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4284         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4285         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4286         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4287
4288         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4289         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4290
4291         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4292         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4293                 imir |= E1000_IMIR_PORT_BP;
4294         else
4295                 imir &= ~E1000_IMIR_PORT_BP;
4296         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4297
4298         /* tcp flags bits setting. */
4299         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4300                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4301                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4302                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4303                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4304                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4305                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4306                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4307                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4308                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4309                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4310                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4311                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4312         } else
4313                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4314         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4315         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4316         return 0;
4317 }
4318
4319 /*
4320  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4321  *
4322  * @param
4323  * dev: Pointer to struct rte_eth_dev.
4324  * ntuple_filter: ponter to the filter that will be removed.
4325  *
4326  * @return
4327  *    - On success, zero.
4328  *    - On failure, a negative value.
4329  */
4330 static int
4331 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4332                                 struct rte_eth_ntuple_filter *ntuple_filter)
4333 {
4334         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4335         struct e1000_filter_info *filter_info =
4336                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4337         struct e1000_5tuple_filter_info filter_5tuple;
4338         struct e1000_5tuple_filter *filter;
4339         int ret;
4340
4341         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4342         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4343                                             &filter_5tuple);
4344         if (ret < 0)
4345                 return ret;
4346
4347         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4348                                          &filter_5tuple);
4349         if (filter == NULL) {
4350                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4351                 return -ENOENT;
4352         }
4353
4354         filter_info->fivetuple_mask &= ~(1 << filter->index);
4355         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4356         rte_free(filter);
4357
4358         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4359                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4360         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4361         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4362         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4363         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4364         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4365         return 0;
4366 }
4367
4368 static int
4369 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4370 {
4371         uint32_t rctl;
4372         struct e1000_hw *hw;
4373         struct rte_eth_dev_info dev_info;
4374         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4375                                      VLAN_TAG_SIZE);
4376
4377         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4378
4379 #ifdef RTE_LIBRTE_82571_SUPPORT
4380         /* XXX: not bigger than max_rx_pktlen */
4381         if (hw->mac.type == e1000_82571)
4382                 return -ENOTSUP;
4383 #endif
4384         eth_igb_infos_get(dev, &dev_info);
4385
4386         /* check that mtu is within the allowed range */
4387         if ((mtu < ETHER_MIN_MTU) ||
4388             (frame_size > dev_info.max_rx_pktlen))
4389                 return -EINVAL;
4390
4391         /* refuse mtu that requires the support of scattered packets when this
4392          * feature has not been enabled before. */
4393         if (!dev->data->scattered_rx &&
4394             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4395                 return -EINVAL;
4396
4397         rctl = E1000_READ_REG(hw, E1000_RCTL);
4398
4399         /* switch to jumbo mode if needed */
4400         if (frame_size > ETHER_MAX_LEN) {
4401                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4402                 rctl |= E1000_RCTL_LPE;
4403         } else {
4404                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4405                 rctl &= ~E1000_RCTL_LPE;
4406         }
4407         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4408
4409         /* update max frame size */
4410         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4411
4412         E1000_WRITE_REG(hw, E1000_RLPML,
4413                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4414
4415         return 0;
4416 }
4417
4418 /*
4419  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4420  *
4421  * @param
4422  * dev: Pointer to struct rte_eth_dev.
4423  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4424  * add: if true, add filter, if false, remove filter
4425  *
4426  * @return
4427  *    - On success, zero.
4428  *    - On failure, a negative value.
4429  */
4430 static int
4431 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4432                         struct rte_eth_ntuple_filter *ntuple_filter,
4433                         bool add)
4434 {
4435         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4436         int ret;
4437
4438         switch (ntuple_filter->flags) {
4439         case RTE_5TUPLE_FLAGS:
4440         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4441                 if (hw->mac.type != e1000_82576)
4442                         return -ENOTSUP;
4443                 if (add)
4444                         ret = igb_add_5tuple_filter_82576(dev,
4445                                                           ntuple_filter);
4446                 else
4447                         ret = igb_remove_5tuple_filter_82576(dev,
4448                                                              ntuple_filter);
4449                 break;
4450         case RTE_2TUPLE_FLAGS:
4451         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4452                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4453                         hw->mac.type != e1000_i210 &&
4454                         hw->mac.type != e1000_i211)
4455                         return -ENOTSUP;
4456                 if (add)
4457                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4458                 else
4459                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4460                 break;
4461         default:
4462                 ret = -EINVAL;
4463                 break;
4464         }
4465
4466         return ret;
4467 }
4468
4469 /*
4470  * igb_get_ntuple_filter - get a ntuple filter
4471  *
4472  * @param
4473  * dev: Pointer to struct rte_eth_dev.
4474  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4475  *
4476  * @return
4477  *    - On success, zero.
4478  *    - On failure, a negative value.
4479  */
4480 static int
4481 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4482                         struct rte_eth_ntuple_filter *ntuple_filter)
4483 {
4484         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4485         struct e1000_filter_info *filter_info =
4486                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4487         struct e1000_5tuple_filter_info filter_5tuple;
4488         struct e1000_2tuple_filter_info filter_2tuple;
4489         struct e1000_5tuple_filter *p_5tuple_filter;
4490         struct e1000_2tuple_filter *p_2tuple_filter;
4491         int ret;
4492
4493         switch (ntuple_filter->flags) {
4494         case RTE_5TUPLE_FLAGS:
4495         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4496                 if (hw->mac.type != e1000_82576)
4497                         return -ENOTSUP;
4498                 memset(&filter_5tuple,
4499                         0,
4500                         sizeof(struct e1000_5tuple_filter_info));
4501                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4502                                                     &filter_5tuple);
4503                 if (ret < 0)
4504                         return ret;
4505                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4506                                         &filter_info->fivetuple_list,
4507                                         &filter_5tuple);
4508                 if (p_5tuple_filter == NULL) {
4509                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4510                         return -ENOENT;
4511                 }
4512                 ntuple_filter->queue = p_5tuple_filter->queue;
4513                 break;
4514         case RTE_2TUPLE_FLAGS:
4515         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4516                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4517                         return -ENOTSUP;
4518                 memset(&filter_2tuple,
4519                         0,
4520                         sizeof(struct e1000_2tuple_filter_info));
4521                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4522                 if (ret < 0)
4523                         return ret;
4524                 p_2tuple_filter = igb_2tuple_filter_lookup(
4525                                         &filter_info->twotuple_list,
4526                                         &filter_2tuple);
4527                 if (p_2tuple_filter == NULL) {
4528                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4529                         return -ENOENT;
4530                 }
4531                 ntuple_filter->queue = p_2tuple_filter->queue;
4532                 break;
4533         default:
4534                 ret = -EINVAL;
4535                 break;
4536         }
4537
4538         return 0;
4539 }
4540
4541 /*
4542  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4543  * @dev: pointer to rte_eth_dev structure
4544  * @filter_op:operation will be taken.
4545  * @arg: a pointer to specific structure corresponding to the filter_op
4546  */
4547 static int
4548 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4549                                 enum rte_filter_op filter_op,
4550                                 void *arg)
4551 {
4552         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4553         int ret;
4554
4555         MAC_TYPE_FILTER_SUP(hw->mac.type);
4556
4557         if (filter_op == RTE_ETH_FILTER_NOP)
4558                 return 0;
4559
4560         if (arg == NULL) {
4561                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4562                             filter_op);
4563                 return -EINVAL;
4564         }
4565
4566         switch (filter_op) {
4567         case RTE_ETH_FILTER_ADD:
4568                 ret = igb_add_del_ntuple_filter(dev,
4569                         (struct rte_eth_ntuple_filter *)arg,
4570                         TRUE);
4571                 break;
4572         case RTE_ETH_FILTER_DELETE:
4573                 ret = igb_add_del_ntuple_filter(dev,
4574                         (struct rte_eth_ntuple_filter *)arg,
4575                         FALSE);
4576                 break;
4577         case RTE_ETH_FILTER_GET:
4578                 ret = igb_get_ntuple_filter(dev,
4579                         (struct rte_eth_ntuple_filter *)arg);
4580                 break;
4581         default:
4582                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4583                 ret = -EINVAL;
4584                 break;
4585         }
4586         return ret;
4587 }
4588
4589 static inline int
4590 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4591                         uint16_t ethertype)
4592 {
4593         int i;
4594
4595         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4596                 if (filter_info->ethertype_filters[i] == ethertype &&
4597                     (filter_info->ethertype_mask & (1 << i)))
4598                         return i;
4599         }
4600         return -1;
4601 }
4602
4603 static inline int
4604 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4605                         uint16_t ethertype)
4606 {
4607         int i;
4608
4609         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4610                 if (!(filter_info->ethertype_mask & (1 << i))) {
4611                         filter_info->ethertype_mask |= 1 << i;
4612                         filter_info->ethertype_filters[i] = ethertype;
4613                         return i;
4614                 }
4615         }
4616         return -1;
4617 }
4618
4619 static inline int
4620 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4621                         uint8_t idx)
4622 {
4623         if (idx >= E1000_MAX_ETQF_FILTERS)
4624                 return -1;
4625         filter_info->ethertype_mask &= ~(1 << idx);
4626         filter_info->ethertype_filters[idx] = 0;
4627         return idx;
4628 }
4629
4630
4631 static int
4632 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4633                         struct rte_eth_ethertype_filter *filter,
4634                         bool add)
4635 {
4636         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4637         struct e1000_filter_info *filter_info =
4638                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4639         uint32_t etqf = 0;
4640         int ret;
4641
4642         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4643                 filter->ether_type == ETHER_TYPE_IPv6) {
4644                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4645                         " ethertype filter.", filter->ether_type);
4646                 return -EINVAL;
4647         }
4648
4649         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4650                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4651                 return -EINVAL;
4652         }
4653         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4654                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4655                 return -EINVAL;
4656         }
4657
4658         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4659         if (ret >= 0 && add) {
4660                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4661                             filter->ether_type);
4662                 return -EEXIST;
4663         }
4664         if (ret < 0 && !add) {
4665                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4666                             filter->ether_type);
4667                 return -ENOENT;
4668         }
4669
4670         if (add) {
4671                 ret = igb_ethertype_filter_insert(filter_info,
4672                         filter->ether_type);
4673                 if (ret < 0) {
4674                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4675                         return -ENOSYS;
4676                 }
4677
4678                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4679                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4680                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4681         } else {
4682                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4683                 if (ret < 0)
4684                         return -ENOSYS;
4685         }
4686         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4687         E1000_WRITE_FLUSH(hw);
4688
4689         return 0;
4690 }
4691
4692 static int
4693 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4694                         struct rte_eth_ethertype_filter *filter)
4695 {
4696         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4697         struct e1000_filter_info *filter_info =
4698                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4699         uint32_t etqf;
4700         int ret;
4701
4702         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4703         if (ret < 0) {
4704                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4705                             filter->ether_type);
4706                 return -ENOENT;
4707         }
4708
4709         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4710         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4711                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4712                 filter->flags = 0;
4713                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4714                                 E1000_ETQF_QUEUE_SHIFT;
4715                 return 0;
4716         }
4717
4718         return -ENOENT;
4719 }
4720
4721 /*
4722  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4723  * @dev: pointer to rte_eth_dev structure
4724  * @filter_op:operation will be taken.
4725  * @arg: a pointer to specific structure corresponding to the filter_op
4726  */
4727 static int
4728 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4729                                 enum rte_filter_op filter_op,
4730                                 void *arg)
4731 {
4732         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4733         int ret;
4734
4735         MAC_TYPE_FILTER_SUP(hw->mac.type);
4736
4737         if (filter_op == RTE_ETH_FILTER_NOP)
4738                 return 0;
4739
4740         if (arg == NULL) {
4741                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4742                             filter_op);
4743                 return -EINVAL;
4744         }
4745
4746         switch (filter_op) {
4747         case RTE_ETH_FILTER_ADD:
4748                 ret = igb_add_del_ethertype_filter(dev,
4749                         (struct rte_eth_ethertype_filter *)arg,
4750                         TRUE);
4751                 break;
4752         case RTE_ETH_FILTER_DELETE:
4753                 ret = igb_add_del_ethertype_filter(dev,
4754                         (struct rte_eth_ethertype_filter *)arg,
4755                         FALSE);
4756                 break;
4757         case RTE_ETH_FILTER_GET:
4758                 ret = igb_get_ethertype_filter(dev,
4759                         (struct rte_eth_ethertype_filter *)arg);
4760                 break;
4761         default:
4762                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4763                 ret = -EINVAL;
4764                 break;
4765         }
4766         return ret;
4767 }
4768
4769 static int
4770 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4771                      enum rte_filter_type filter_type,
4772                      enum rte_filter_op filter_op,
4773                      void *arg)
4774 {
4775         int ret = -EINVAL;
4776
4777         switch (filter_type) {
4778         case RTE_ETH_FILTER_NTUPLE:
4779                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4780                 break;
4781         case RTE_ETH_FILTER_ETHERTYPE:
4782                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4783                 break;
4784         case RTE_ETH_FILTER_SYN:
4785                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4786                 break;
4787         case RTE_ETH_FILTER_FLEXIBLE:
4788                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4789                 break;
4790         default:
4791                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4792                                                         filter_type);
4793                 break;
4794         }
4795
4796         return ret;
4797 }
4798
4799 static int
4800 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4801                          struct ether_addr *mc_addr_set,
4802                          uint32_t nb_mc_addr)
4803 {
4804         struct e1000_hw *hw;
4805
4806         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4807         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4808         return 0;
4809 }
4810
4811 static uint64_t
4812 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4813 {
4814         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4815         uint64_t systime_cycles;
4816
4817         switch (hw->mac.type) {
4818         case e1000_i210:
4819         case e1000_i211:
4820                 /*
4821                  * Need to read System Time Residue Register to be able
4822                  * to read the other two registers.
4823                  */
4824                 E1000_READ_REG(hw, E1000_SYSTIMR);
4825                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4826                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4827                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4828                                 * NSEC_PER_SEC;
4829                 break;
4830         case e1000_82580:
4831         case e1000_i350:
4832         case e1000_i354:
4833                 /*
4834                  * Need to read System Time Residue Register to be able
4835                  * to read the other two registers.
4836                  */
4837                 E1000_READ_REG(hw, E1000_SYSTIMR);
4838                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4839                 /* Only the 8 LSB are valid. */
4840                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4841                                 & 0xff) << 32;
4842                 break;
4843         default:
4844                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4845                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4846                                 << 32;
4847                 break;
4848         }
4849
4850         return systime_cycles;
4851 }
4852
4853 static uint64_t
4854 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4855 {
4856         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4857         uint64_t rx_tstamp_cycles;
4858
4859         switch (hw->mac.type) {
4860         case e1000_i210:
4861         case e1000_i211:
4862                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4863                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4864                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4865                                 * NSEC_PER_SEC;
4866                 break;
4867         case e1000_82580:
4868         case e1000_i350:
4869         case e1000_i354:
4870                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4871                 /* Only the 8 LSB are valid. */
4872                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4873                                 & 0xff) << 32;
4874                 break;
4875         default:
4876                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4877                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4878                                 << 32;
4879                 break;
4880         }
4881
4882         return rx_tstamp_cycles;
4883 }
4884
4885 static uint64_t
4886 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4887 {
4888         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4889         uint64_t tx_tstamp_cycles;
4890
4891         switch (hw->mac.type) {
4892         case e1000_i210:
4893         case e1000_i211:
4894                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4895                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4896                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4897                                 * NSEC_PER_SEC;
4898                 break;
4899         case e1000_82580:
4900         case e1000_i350:
4901         case e1000_i354:
4902                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4903                 /* Only the 8 LSB are valid. */
4904                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4905                                 & 0xff) << 32;
4906                 break;
4907         default:
4908                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4909                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4910                                 << 32;
4911                 break;
4912         }
4913
4914         return tx_tstamp_cycles;
4915 }
4916
4917 static void
4918 igb_start_timecounters(struct rte_eth_dev *dev)
4919 {
4920         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4921         struct e1000_adapter *adapter =
4922                 (struct e1000_adapter *)dev->data->dev_private;
4923         uint32_t incval = 1;
4924         uint32_t shift = 0;
4925         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4926
4927         switch (hw->mac.type) {
4928         case e1000_82580:
4929         case e1000_i350:
4930         case e1000_i354:
4931                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4932                 mask = (1ULL << 40) - 1;
4933                 /* fall-through */
4934         case e1000_i210:
4935         case e1000_i211:
4936                 /*
4937                  * Start incrementing the register
4938                  * used to timestamp PTP packets.
4939                  */
4940                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4941                 break;
4942         case e1000_82576:
4943                 incval = E1000_INCVALUE_82576;
4944                 shift = IGB_82576_TSYNC_SHIFT;
4945                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4946                                 E1000_INCPERIOD_82576 | incval);
4947                 break;
4948         default:
4949                 /* Not supported */
4950                 return;
4951         }
4952
4953         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4954         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4955         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4956
4957         adapter->systime_tc.cc_mask = mask;
4958         adapter->systime_tc.cc_shift = shift;
4959         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4960
4961         adapter->rx_tstamp_tc.cc_mask = mask;
4962         adapter->rx_tstamp_tc.cc_shift = shift;
4963         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4964
4965         adapter->tx_tstamp_tc.cc_mask = mask;
4966         adapter->tx_tstamp_tc.cc_shift = shift;
4967         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4968 }
4969
4970 static int
4971 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4972 {
4973         struct e1000_adapter *adapter =
4974                         (struct e1000_adapter *)dev->data->dev_private;
4975
4976         adapter->systime_tc.nsec += delta;
4977         adapter->rx_tstamp_tc.nsec += delta;
4978         adapter->tx_tstamp_tc.nsec += delta;
4979
4980         return 0;
4981 }
4982
4983 static int
4984 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4985 {
4986         uint64_t ns;
4987         struct e1000_adapter *adapter =
4988                         (struct e1000_adapter *)dev->data->dev_private;
4989
4990         ns = rte_timespec_to_ns(ts);
4991
4992         /* Set the timecounters to a new value. */
4993         adapter->systime_tc.nsec = ns;
4994         adapter->rx_tstamp_tc.nsec = ns;
4995         adapter->tx_tstamp_tc.nsec = ns;
4996
4997         return 0;
4998 }
4999
5000 static int
5001 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5002 {
5003         uint64_t ns, systime_cycles;
5004         struct e1000_adapter *adapter =
5005                         (struct e1000_adapter *)dev->data->dev_private;
5006
5007         systime_cycles = igb_read_systime_cyclecounter(dev);
5008         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5009         *ts = rte_ns_to_timespec(ns);
5010
5011         return 0;
5012 }
5013
5014 static int
5015 igb_timesync_enable(struct rte_eth_dev *dev)
5016 {
5017         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5018         uint32_t tsync_ctl;
5019         uint32_t tsauxc;
5020
5021         /* Stop the timesync system time. */
5022         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5023         /* Reset the timesync system time value. */
5024         switch (hw->mac.type) {
5025         case e1000_82580:
5026         case e1000_i350:
5027         case e1000_i354:
5028         case e1000_i210:
5029         case e1000_i211:
5030                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5031                 /* fall-through */
5032         case e1000_82576:
5033                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5034                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5035                 break;
5036         default:
5037                 /* Not supported. */
5038                 return -ENOTSUP;
5039         }
5040
5041         /* Enable system time for it isn't on by default. */
5042         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5043         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5044         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5045
5046         igb_start_timecounters(dev);
5047
5048         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5049         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5050                         (ETHER_TYPE_1588 |
5051                          E1000_ETQF_FILTER_ENABLE |
5052                          E1000_ETQF_1588));
5053
5054         /* Enable timestamping of received PTP packets. */
5055         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5056         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5057         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5058
5059         /* Enable Timestamping of transmitted PTP packets. */
5060         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5061         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5062         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5063
5064         return 0;
5065 }
5066
5067 static int
5068 igb_timesync_disable(struct rte_eth_dev *dev)
5069 {
5070         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5071         uint32_t tsync_ctl;
5072
5073         /* Disable timestamping of transmitted PTP packets. */
5074         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5075         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5076         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5077
5078         /* Disable timestamping of received PTP packets. */
5079         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5080         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5081         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5082
5083         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5084         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5085
5086         /* Stop incrementating the System Time registers. */
5087         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5088
5089         return 0;
5090 }
5091
5092 static int
5093 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5094                                struct timespec *timestamp,
5095                                uint32_t flags __rte_unused)
5096 {
5097         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5098         struct e1000_adapter *adapter =
5099                         (struct e1000_adapter *)dev->data->dev_private;
5100         uint32_t tsync_rxctl;
5101         uint64_t rx_tstamp_cycles;
5102         uint64_t ns;
5103
5104         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5105         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5106                 return -EINVAL;
5107
5108         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5109         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5110         *timestamp = rte_ns_to_timespec(ns);
5111
5112         return  0;
5113 }
5114
5115 static int
5116 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5117                                struct timespec *timestamp)
5118 {
5119         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5120         struct e1000_adapter *adapter =
5121                         (struct e1000_adapter *)dev->data->dev_private;
5122         uint32_t tsync_txctl;
5123         uint64_t tx_tstamp_cycles;
5124         uint64_t ns;
5125
5126         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5127         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5128                 return -EINVAL;
5129
5130         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5131         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5132         *timestamp = rte_ns_to_timespec(ns);
5133
5134         return  0;
5135 }
5136
5137 static int
5138 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5139 {
5140         int count = 0;
5141         int g_ind = 0;
5142         const struct reg_info *reg_group;
5143
5144         while ((reg_group = igb_regs[g_ind++]))
5145                 count += igb_reg_group_count(reg_group);
5146
5147         return count;
5148 }
5149
5150 static int
5151 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5152 {
5153         int count = 0;
5154         int g_ind = 0;
5155         const struct reg_info *reg_group;
5156
5157         while ((reg_group = igbvf_regs[g_ind++]))
5158                 count += igb_reg_group_count(reg_group);
5159
5160         return count;
5161 }
5162
5163 static int
5164 eth_igb_get_regs(struct rte_eth_dev *dev,
5165         struct rte_dev_reg_info *regs)
5166 {
5167         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5168         uint32_t *data = regs->data;
5169         int g_ind = 0;
5170         int count = 0;
5171         const struct reg_info *reg_group;
5172
5173         if (data == NULL) {
5174                 regs->length = eth_igb_get_reg_length(dev);
5175                 regs->width = sizeof(uint32_t);
5176                 return 0;
5177         }
5178
5179         /* Support only full register dump */
5180         if ((regs->length == 0) ||
5181             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5182                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5183                         hw->device_id;
5184                 while ((reg_group = igb_regs[g_ind++]))
5185                         count += igb_read_regs_group(dev, &data[count],
5186                                                         reg_group);
5187                 return 0;
5188         }
5189
5190         return -ENOTSUP;
5191 }
5192
5193 static int
5194 igbvf_get_regs(struct rte_eth_dev *dev,
5195         struct rte_dev_reg_info *regs)
5196 {
5197         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5198         uint32_t *data = regs->data;
5199         int g_ind = 0;
5200         int count = 0;
5201         const struct reg_info *reg_group;
5202
5203         if (data == NULL) {
5204                 regs->length = igbvf_get_reg_length(dev);
5205                 regs->width = sizeof(uint32_t);
5206                 return 0;
5207         }
5208
5209         /* Support only full register dump */
5210         if ((regs->length == 0) ||
5211             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5212                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5213                         hw->device_id;
5214                 while ((reg_group = igbvf_regs[g_ind++]))
5215                         count += igb_read_regs_group(dev, &data[count],
5216                                                         reg_group);
5217                 return 0;
5218         }
5219
5220         return -ENOTSUP;
5221 }
5222
5223 static int
5224 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5225 {
5226         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5227
5228         /* Return unit is byte count */
5229         return hw->nvm.word_size * 2;
5230 }
5231
5232 static int
5233 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5234         struct rte_dev_eeprom_info *in_eeprom)
5235 {
5236         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5237         struct e1000_nvm_info *nvm = &hw->nvm;
5238         uint16_t *data = in_eeprom->data;
5239         int first, length;
5240
5241         first = in_eeprom->offset >> 1;
5242         length = in_eeprom->length >> 1;
5243         if ((first >= hw->nvm.word_size) ||
5244             ((first + length) >= hw->nvm.word_size))
5245                 return -EINVAL;
5246
5247         in_eeprom->magic = hw->vendor_id |
5248                 ((uint32_t)hw->device_id << 16);
5249
5250         if ((nvm->ops.read) == NULL)
5251                 return -ENOTSUP;
5252
5253         return nvm->ops.read(hw, first, length, data);
5254 }
5255
5256 static int
5257 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5258         struct rte_dev_eeprom_info *in_eeprom)
5259 {
5260         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5261         struct e1000_nvm_info *nvm = &hw->nvm;
5262         uint16_t *data = in_eeprom->data;
5263         int first, length;
5264
5265         first = in_eeprom->offset >> 1;
5266         length = in_eeprom->length >> 1;
5267         if ((first >= hw->nvm.word_size) ||
5268             ((first + length) >= hw->nvm.word_size))
5269                 return -EINVAL;
5270
5271         in_eeprom->magic = (uint32_t)hw->vendor_id |
5272                 ((uint32_t)hw->device_id << 16);
5273
5274         if ((nvm->ops.write) == NULL)
5275                 return -ENOTSUP;
5276         return nvm->ops.write(hw,  first, length, data);
5277 }
5278
5279 static int
5280 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5281 {
5282         struct e1000_hw *hw =
5283                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5284         uint32_t mask = 1 << queue_id;
5285
5286         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5287         E1000_WRITE_FLUSH(hw);
5288
5289         return 0;
5290 }
5291
5292 static int
5293 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5294 {
5295         struct e1000_hw *hw =
5296                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5297         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5298         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5299         uint32_t mask = 1 << queue_id;
5300         uint32_t regval;
5301
5302         regval = E1000_READ_REG(hw, E1000_EIMS);
5303         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5304         E1000_WRITE_FLUSH(hw);
5305
5306         rte_intr_enable(intr_handle);
5307
5308         return 0;
5309 }
5310
5311 static void
5312 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5313                    uint8_t index, uint8_t offset)
5314 {
5315         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5316
5317         /* clear bits */
5318         val &= ~((uint32_t)0xFF << offset);
5319
5320         /* write vector and valid bit */
5321         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5322
5323         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5324 }
5325
5326 static void
5327 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5328                            uint8_t queue, uint8_t msix_vector)
5329 {
5330         uint32_t tmp = 0;
5331
5332         if (hw->mac.type == e1000_82575) {
5333                 if (direction == 0)
5334                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5335                 else if (direction == 1)
5336                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5337                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5338         } else if (hw->mac.type == e1000_82576) {
5339                 if ((direction == 0) || (direction == 1))
5340                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5341                                            ((queue & 0x8) << 1) +
5342                                            8 * direction);
5343         } else if ((hw->mac.type == e1000_82580) ||
5344                         (hw->mac.type == e1000_i350) ||
5345                         (hw->mac.type == e1000_i354) ||
5346                         (hw->mac.type == e1000_i210) ||
5347                         (hw->mac.type == e1000_i211)) {
5348                 if ((direction == 0) || (direction == 1))
5349                         eth_igb_write_ivar(hw, msix_vector,
5350                                            queue >> 1,
5351                                            ((queue & 0x1) << 4) +
5352                                            8 * direction);
5353         }
5354 }
5355
5356 /* Sets up the hardware to generate MSI-X interrupts properly
5357  * @hw
5358  *  board private structure
5359  */
5360 static void
5361 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5362 {
5363         int queue_id;
5364         uint32_t tmpval, regval, intr_mask;
5365         struct e1000_hw *hw =
5366                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5367         uint32_t vec = E1000_MISC_VEC_ID;
5368         uint32_t base = E1000_MISC_VEC_ID;
5369         uint32_t misc_shift = 0;
5370         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5371         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5372
5373         /* won't configure msix register if no mapping is done
5374          * between intr vector and event fd
5375          */
5376         if (!rte_intr_dp_is_en(intr_handle))
5377                 return;
5378
5379         if (rte_intr_allow_others(intr_handle)) {
5380                 vec = base = E1000_RX_VEC_START;
5381                 misc_shift = 1;
5382         }
5383
5384         /* set interrupt vector for other causes */
5385         if (hw->mac.type == e1000_82575) {
5386                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5387                 /* enable MSI-X PBA support */
5388                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5389
5390                 /* Auto-Mask interrupts upon ICR read */
5391                 tmpval |= E1000_CTRL_EXT_EIAME;
5392                 tmpval |= E1000_CTRL_EXT_IRCA;
5393
5394                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5395
5396                 /* enable msix_other interrupt */
5397                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5398                 regval = E1000_READ_REG(hw, E1000_EIAC);
5399                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5400                 regval = E1000_READ_REG(hw, E1000_EIAM);
5401                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5402         } else if ((hw->mac.type == e1000_82576) ||
5403                         (hw->mac.type == e1000_82580) ||
5404                         (hw->mac.type == e1000_i350) ||
5405                         (hw->mac.type == e1000_i354) ||
5406                         (hw->mac.type == e1000_i210) ||
5407                         (hw->mac.type == e1000_i211)) {
5408                 /* turn on MSI-X capability first */
5409                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5410                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5411                                         E1000_GPIE_NSICR);
5412                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5413                         misc_shift;
5414                 regval = E1000_READ_REG(hw, E1000_EIAC);
5415                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5416
5417                 /* enable msix_other interrupt */
5418                 regval = E1000_READ_REG(hw, E1000_EIMS);
5419                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5420                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5421                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5422         }
5423
5424         /* use EIAM to auto-mask when MSI-X interrupt
5425          * is asserted, this saves a register write for every interrupt
5426          */
5427         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5428                 misc_shift;
5429         regval = E1000_READ_REG(hw, E1000_EIAM);
5430         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5431
5432         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5433                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5434                 intr_handle->intr_vec[queue_id] = vec;
5435                 if (vec < base + intr_handle->nb_efd - 1)
5436                         vec++;
5437         }
5438
5439         E1000_WRITE_FLUSH(hw);
5440 }
5441
5442 /* restore SYN filter */
5443 static inline void
5444 igb_syn_filter_restore(struct rte_eth_dev *dev)
5445 {
5446         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5447         struct e1000_filter_info *filter_info =
5448                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5449         uint32_t synqf;
5450
5451         synqf = filter_info->syn_info;
5452
5453         if (synqf & E1000_SYN_FILTER_ENABLE) {
5454                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5455                 E1000_WRITE_FLUSH(hw);
5456         }
5457 }
5458
5459 /* restore all types filter */
5460 static int
5461 igb_filter_restore(struct rte_eth_dev *dev)
5462 {
5463         igb_syn_filter_restore(dev);
5464
5465         return 0;
5466 }
5467
5468 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5469 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5470 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5471 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5472 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5473 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");