drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 #define IGB_HKEY_MAX_INDEX 10
  73
  74 /* Bit shift and mask */
  75 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  76 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  77 #define IGB_8_BIT_WIDTH  CHAR_BIT
  78 #define IGB_8_BIT_MASK   UINT8_MAX
  79
  80 /* Additional timesync values. */
  81 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  82 #define E1000_ETQF_FILTER_1588       3
  83 #define IGB_82576_TSYNC_SHIFT        16
  84 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  85 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  86 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  87
  88 static int  eth_igb_configure(struct rte_eth_dev *dev);
  89 static int  eth_igb_start(struct rte_eth_dev *dev);
  90 static void eth_igb_stop(struct rte_eth_dev *dev);
  91 static void eth_igb_close(struct rte_eth_dev *dev);
  92 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  93 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  94 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  95 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  96 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  97                                 int wait_to_complete);
  98 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  99                                 struct rte_eth_stats *rte_stats);
 100 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 101                               struct rte_eth_xstats *xstats, unsigned n);
 102 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 103 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 104 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 105                               struct rte_eth_dev_info *dev_info);
 106 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 107                                 struct rte_eth_dev_info *dev_info);
 108 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_fc_conf *fc_conf);
 110 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 113 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 114 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 115 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 116 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 117                                                         void *param);
 118 static int  igb_hardware_init(struct e1000_hw *hw);
 119 static void igb_hw_control_acquire(struct e1000_hw *hw);
 120 static void igb_hw_control_release(struct e1000_hw *hw);
 121 static void igb_init_manageability(struct e1000_hw *hw);
 122 static void igb_release_manageability(struct e1000_hw *hw);
 123
 124 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 125
 126 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 127                 uint16_t vlan_id, int on);
 128 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 129                                  enum rte_vlan_type vlan_type,
 130                                  uint16_t tpid_id);
 131 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 132
 133 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 134 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 135 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 139
 140 static int eth_igb_led_on(struct rte_eth_dev *dev);
 141 static int eth_igb_led_off(struct rte_eth_dev *dev);
 142
 143 static void igb_intr_disable(struct e1000_hw *hw);
 144 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 145 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 146                 struct ether_addr *mac_addr,
 147                 uint32_t index, uint32_t pool);
 148 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 149 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 150                 struct ether_addr *addr);
 151
 152 static void igbvf_intr_disable(struct e1000_hw *hw);
 153 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 154 static int igbvf_dev_start(struct rte_eth_dev *dev);
 155 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 156 static void igbvf_dev_close(struct rte_eth_dev *dev);
 157 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 158 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 159 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 160 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 161 static int eth_igbvf_link_update(struct e1000_hw *hw);
 162 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 163                                 struct rte_eth_stats *rte_stats);
 164 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_xstats *xstats, unsigned n);
 166 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 167 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 168                 uint16_t vlan_id, int on);
 169 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 170 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 171 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 172                 struct ether_addr *addr);
 173 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 174 static int igbvf_get_regs(struct rte_eth_dev *dev,
 175                 struct rte_dev_reg_info *regs);
 176
 177 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 178                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 179                                    uint16_t reta_size);
 180 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 181                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 182                                   uint16_t reta_size);
 183
 184 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 185                         struct rte_eth_syn_filter *filter,
 186                         bool add);
 187 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 188                         struct rte_eth_syn_filter *filter);
 189 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 190                         enum rte_filter_op filter_op,
 191                         void *arg);
 192 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 193                         struct rte_eth_ntuple_filter *ntuple_filter);
 194 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_flex_filter *filter,
 198                         bool add);
 199 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 200                         struct rte_eth_flex_filter *filter);
 201 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 202                         enum rte_filter_op filter_op,
 203                         void *arg);
 204 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 205                         struct rte_eth_ntuple_filter *ntuple_filter);
 206 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 207                         struct rte_eth_ntuple_filter *ntuple_filter);
 208 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 209                         struct rte_eth_ntuple_filter *filter,
 210                         bool add);
 211 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 212                         struct rte_eth_ntuple_filter *filter);
 213 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 214                                 enum rte_filter_op filter_op,
 215                                 void *arg);
 216 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 217                         struct rte_eth_ethertype_filter *filter,
 218                         bool add);
 219 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 220                                 enum rte_filter_op filter_op,
 221                                 void *arg);
 222 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 223                         struct rte_eth_ethertype_filter *filter);
 224 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 225                      enum rte_filter_type filter_type,
 226                      enum rte_filter_op filter_op,
 227                      void *arg);
 228 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 229 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 230                 struct rte_dev_reg_info *regs);
 231 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 232 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 233                 struct rte_dev_eeprom_info *eeprom);
 234 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 235                 struct rte_dev_eeprom_info *eeprom);
 236 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 237                                     struct ether_addr *mc_addr_set,
 238                                     uint32_t nb_mc_addr);
 239 static int igb_timesync_enable(struct rte_eth_dev *dev);
 240 static int igb_timesync_disable(struct rte_eth_dev *dev);
 241 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 242                                           struct timespec *timestamp,
 243                                           uint32_t flags);
 244 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 245                                           struct timespec *timestamp);
 246 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 247 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 248                                   struct timespec *timestamp);
 249 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 250                                    const struct timespec *timestamp);
 251 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 252                                         uint16_t queue_id);
 253 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 254                                          uint16_t queue_id);
 255 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 256                                        uint8_t queue, uint8_t msix_vector);
 257 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 258                                uint8_t index, uint8_t offset);
 259 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 260
 261 /*
 262  * Define VF Stats MACRO for Non "cleared on read" register
 263  */
 264 #define UPDATE_VF_STAT(reg, last, cur)            \
 265 {                                                 \
 266         u32 latest = E1000_READ_REG(hw, reg);     \
 267         cur += (latest - last) & UINT_MAX;        \
 268         last = latest;                            \
 269 }
 270
 271 #define IGB_FC_PAUSE_TIME 0x0680
 272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 274
 275 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 276
 277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 278
 279 /*
 280  * The set of PCI devices this driver supports
 281  */
 282 static const struct rte_pci_id pci_id_igb_map[] = {
 283
 284 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 285 #include "rte_pci_dev_ids.h"
 286
 287 {0},
 288 };
 289
 290 /*
 291  * The set of PCI devices this driver supports (for 82576&I350 VF)
 292  */
 293 static const struct rte_pci_id pci_id_igbvf_map[] = {
 294
 295 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 296 #include "rte_pci_dev_ids.h"
 297
 298 {0},
 299 };
 300
 301 static const struct rte_eth_desc_lim rx_desc_lim = {
 302         .nb_max = E1000_MAX_RING_DESC,
 303         .nb_min = E1000_MIN_RING_DESC,
 304         .nb_align = IGB_RXD_ALIGN,
 305 };
 306
 307 static const struct rte_eth_desc_lim tx_desc_lim = {
 308         .nb_max = E1000_MAX_RING_DESC,
 309         .nb_min = E1000_MIN_RING_DESC,
 310         .nb_align = IGB_RXD_ALIGN,
 311 };
 312
 313 static const struct eth_dev_ops eth_igb_ops = {
 314         .dev_configure        = eth_igb_configure,
 315         .dev_start            = eth_igb_start,
 316         .dev_stop             = eth_igb_stop,
 317         .dev_close            = eth_igb_close,
 318         .promiscuous_enable   = eth_igb_promiscuous_enable,
 319         .promiscuous_disable  = eth_igb_promiscuous_disable,
 320         .allmulticast_enable  = eth_igb_allmulticast_enable,
 321         .allmulticast_disable = eth_igb_allmulticast_disable,
 322         .link_update          = eth_igb_link_update,
 323         .stats_get            = eth_igb_stats_get,
 324         .xstats_get           = eth_igb_xstats_get,
 325         .stats_reset          = eth_igb_stats_reset,
 326         .xstats_reset         = eth_igb_xstats_reset,
 327         .dev_infos_get        = eth_igb_infos_get,
 328         .mtu_set              = eth_igb_mtu_set,
 329         .vlan_filter_set      = eth_igb_vlan_filter_set,
 330         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 331         .vlan_offload_set     = eth_igb_vlan_offload_set,
 332         .rx_queue_setup       = eth_igb_rx_queue_setup,
 333         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 334         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 335         .rx_queue_release     = eth_igb_rx_queue_release,
 336         .rx_queue_count       = eth_igb_rx_queue_count,
 337         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 338         .tx_queue_setup       = eth_igb_tx_queue_setup,
 339         .tx_queue_release     = eth_igb_tx_queue_release,
 340         .dev_led_on           = eth_igb_led_on,
 341         .dev_led_off          = eth_igb_led_off,
 342         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 343         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 344         .mac_addr_add         = eth_igb_rar_set,
 345         .mac_addr_remove      = eth_igb_rar_clear,
 346         .mac_addr_set         = eth_igb_default_mac_addr_set,
 347         .reta_update          = eth_igb_rss_reta_update,
 348         .reta_query           = eth_igb_rss_reta_query,
 349         .rss_hash_update      = eth_igb_rss_hash_update,
 350         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 351         .filter_ctrl          = eth_igb_filter_ctrl,
 352         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 353         .rxq_info_get         = igb_rxq_info_get,
 354         .txq_info_get         = igb_txq_info_get,
 355         .timesync_enable      = igb_timesync_enable,
 356         .timesync_disable     = igb_timesync_disable,
 357         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 358         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 359         .get_reg_length       = eth_igb_get_reg_length,
 360         .get_reg              = eth_igb_get_regs,
 361         .get_eeprom_length    = eth_igb_get_eeprom_length,
 362         .get_eeprom           = eth_igb_get_eeprom,
 363         .set_eeprom           = eth_igb_set_eeprom,
 364         .timesync_adjust_time = igb_timesync_adjust_time,
 365         .timesync_read_time   = igb_timesync_read_time,
 366         .timesync_write_time  = igb_timesync_write_time,
 367 };
 368
 369 /*
 370  * dev_ops for virtual function, bare necessities for basic vf
 371  * operation have been implemented
 372  */
 373 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 374         .dev_configure        = igbvf_dev_configure,
 375         .dev_start            = igbvf_dev_start,
 376         .dev_stop             = igbvf_dev_stop,
 377         .dev_close            = igbvf_dev_close,
 378         .promiscuous_enable   = igbvf_promiscuous_enable,
 379         .promiscuous_disable  = igbvf_promiscuous_disable,
 380         .allmulticast_enable  = igbvf_allmulticast_enable,
 381         .allmulticast_disable = igbvf_allmulticast_disable,
 382         .link_update          = eth_igb_link_update,
 383         .stats_get            = eth_igbvf_stats_get,
 384         .xstats_get           = eth_igbvf_xstats_get,
 385         .stats_reset          = eth_igbvf_stats_reset,
 386         .xstats_reset         = eth_igbvf_stats_reset,
 387         .vlan_filter_set      = igbvf_vlan_filter_set,
 388         .dev_infos_get        = eth_igbvf_infos_get,
 389         .rx_queue_setup       = eth_igb_rx_queue_setup,
 390         .rx_queue_release     = eth_igb_rx_queue_release,
 391         .tx_queue_setup       = eth_igb_tx_queue_setup,
 392         .tx_queue_release     = eth_igb_tx_queue_release,
 393         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 394         .rxq_info_get         = igb_rxq_info_get,
 395         .txq_info_get         = igb_txq_info_get,
 396         .mac_addr_set         = igbvf_default_mac_addr_set,
 397         .get_reg_length       = igbvf_get_reg_length,
 398         .get_reg              = igbvf_get_regs,
 399 };
 400
 401 /* store statistics names and its offset in stats structure */
 402 struct rte_igb_xstats_name_off {
 403         char name[RTE_ETH_XSTATS_NAME_SIZE];
 404         unsigned offset;
 405 };
 406
 407 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 408         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 409         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 410         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 411         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 412         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 413         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 414         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 415                 ecol)},
 416         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 417         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 418         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 419         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 420         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 421         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 422         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 423         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 424         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 425         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 426         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 427                 fcruc)},
 428         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 429         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 430         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 431         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 432         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 433                 prc1023)},
 434         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 435                 prc1522)},
 436         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 437         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 438         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 439         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 440         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 441         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 442         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 443         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 444         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 445         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 446         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 447         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 448         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 449         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 450         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 451         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 452         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 453         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 454                 ptc1023)},
 455         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 456                 ptc1522)},
 457         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 458         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 459         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 460         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 461         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 462         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 463         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 464
 465         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 466 };
 467
 468 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 469                 sizeof(rte_igb_stats_strings[0]))
 470
 471 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 472         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 473         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 474         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 475         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 476         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 477 };
 478
 479 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 480                 sizeof(rte_igbvf_stats_strings[0]))
 481
 482 /**
 483  * Atomically reads the link status information from global
 484  * structure rte_eth_dev.
 485  *
 486  * @param dev
 487  *   - Pointer to the structure rte_eth_dev to read from.
 488  *   - Pointer to the buffer to be saved with the link status.
 489  *
 490  * @return
 491  *   - On success, zero.
 492  *   - On failure, negative value.
 493  */
 494 static inline int
 495 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 496                                 struct rte_eth_link *link)
 497 {
 498         struct rte_eth_link *dst = link;
 499         struct rte_eth_link *src = &(dev->data->dev_link);
 500
 501         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 502                                         *(uint64_t *)src) == 0)
 503                 return -1;
 504
 505         return 0;
 506 }
 507
 508 /**
 509  * Atomically writes the link status information into global
 510  * structure rte_eth_dev.
 511  *
 512  * @param dev
 513  *   - Pointer to the structure rte_eth_dev to read from.
 514  *   - Pointer to the buffer to be saved with the link status.
 515  *
 516  * @return
 517  *   - On success, zero.
 518  *   - On failure, negative value.
 519  */
 520 static inline int
 521 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 522                                 struct rte_eth_link *link)
 523 {
 524         struct rte_eth_link *dst = &(dev->data->dev_link);
 525         struct rte_eth_link *src = link;
 526
 527         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 528                                         *(uint64_t *)src) == 0)
 529                 return -1;
 530
 531         return 0;
 532 }
 533
 534 static inline void
 535 igb_intr_enable(struct rte_eth_dev *dev)
 536 {
 537         struct e1000_interrupt *intr =
 538                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 539         struct e1000_hw *hw =
 540                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 541
 542         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 543         E1000_WRITE_FLUSH(hw);
 544 }
 545
 546 static void
 547 igb_intr_disable(struct e1000_hw *hw)
 548 {
 549         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 550         E1000_WRITE_FLUSH(hw);
 551 }
 552
 553 static inline int32_t
 554 igb_pf_reset_hw(struct e1000_hw *hw)
 555 {
 556         uint32_t ctrl_ext;
 557         int32_t status;
 558
 559         status = e1000_reset_hw(hw);
 560
 561         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 562         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 563         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 564         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 565         E1000_WRITE_FLUSH(hw);
 566
 567         return status;
 568 }
 569
 570 static void
 571 igb_identify_hardware(struct rte_eth_dev *dev)
 572 {
 573         struct e1000_hw *hw =
 574                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 575
 576         hw->vendor_id = dev->pci_dev->id.vendor_id;
 577         hw->device_id = dev->pci_dev->id.device_id;
 578         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 579         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 580
 581         e1000_set_mac_type(hw);
 582
 583         /* need to check if it is a vf device below */
 584 }
 585
 586 static int
 587 igb_reset_swfw_lock(struct e1000_hw *hw)
 588 {
 589         int ret_val;
 590
 591         /*
 592          * Do mac ops initialization manually here, since we will need
 593          * some function pointers set by this call.
 594          */
 595         ret_val = e1000_init_mac_params(hw);
 596         if (ret_val)
 597                 return ret_val;
 598
 599         /*
 600          * SMBI lock should not fail in this early stage. If this is the case,
 601          * it is due to an improper exit of the application.
 602          * So force the release of the faulty lock.
 603          */
 604         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 605                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 606         }
 607         e1000_put_hw_semaphore_generic(hw);
 608
 609         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 610                 uint16_t mask;
 611
 612                 /*
 613                  * Phy lock should not fail in this early stage. If this is the case,
 614                  * it is due to an improper exit of the application.
 615                  * So force the release of the faulty lock.
 616                  */
 617                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 618                 if (hw->bus.func > E1000_FUNC_1)
 619                         mask <<= 2;
 620                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 621                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 622                                     hw->bus.func);
 623                 }
 624                 hw->mac.ops.release_swfw_sync(hw, mask);
 625
 626                 /*
 627                  * This one is more tricky since it is common to all ports; but
 628                  * swfw_sync retries last long enough (1s) to be almost sure that if
 629                  * lock can not be taken it is due to an improper lock of the
 630                  * semaphore.
 631                  */
 632                 mask = E1000_SWFW_EEP_SM;
 633                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 634                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 635                 }
 636                 hw->mac.ops.release_swfw_sync(hw, mask);
 637         }
 638
 639         return E1000_SUCCESS;
 640 }
 641
 642 static int
 643 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 644 {
 645         int error = 0;
 646         struct rte_pci_device *pci_dev;
 647         struct e1000_hw *hw =
 648                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 649         struct e1000_vfta * shadow_vfta =
 650                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 651         struct e1000_filter_info *filter_info =
 652                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 653         struct e1000_adapter *adapter =
 654                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 655
 656         uint32_t ctrl_ext;
 657
 658         pci_dev = eth_dev->pci_dev;
 659
 660         eth_dev->dev_ops = &eth_igb_ops;
 661         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 662         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 663
 664         /* for secondary processes, we don't initialise any further as primary
 665          * has already done this work. Only check we don't need a different
 666          * RX function */
 667         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 668                 if (eth_dev->data->scattered_rx)
 669                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 670                 return 0;
 671         }
 672
 673         rte_eth_copy_pci_info(eth_dev, pci_dev);
 674
 675         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 676
 677         igb_identify_hardware(eth_dev);
 678         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 679                 error = -EIO;
 680                 goto err_late;
 681         }
 682
 683         e1000_get_bus_info(hw);
 684
 685         /* Reset any pending lock */
 686         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 687                 error = -EIO;
 688                 goto err_late;
 689         }
 690
 691         /* Finish initialization */
 692         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 693                 error = -EIO;
 694                 goto err_late;
 695         }
 696
 697         hw->mac.autoneg = 1;
 698         hw->phy.autoneg_wait_to_complete = 0;
 699         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 700
 701         /* Copper options */
 702         if (hw->phy.media_type == e1000_media_type_copper) {
 703                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 704                 hw->phy.disable_polarity_correction = 0;
 705                 hw->phy.ms_type = e1000_ms_hw_default;
 706         }
 707
 708         /*
 709          * Start from a known state, this is important in reading the nvm
 710          * and mac from that.
 711          */
 712         igb_pf_reset_hw(hw);
 713
 714         /* Make sure we have a good EEPROM before we read from it */
 715         if (e1000_validate_nvm_checksum(hw) < 0) {
 716                 /*
 717                  * Some PCI-E parts fail the first check due to
 718                  * the link being in sleep state, call it again,
 719                  * if it fails a second time its a real issue.
 720                  */
 721                 if (e1000_validate_nvm_checksum(hw) < 0) {
 722                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 723                         error = -EIO;
 724                         goto err_late;
 725                 }
 726         }
 727
 728         /* Read the permanent MAC address out of the EEPROM */
 729         if (e1000_read_mac_addr(hw) != 0) {
 730                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 731                 error = -EIO;
 732                 goto err_late;
 733         }
 734
 735         /* Allocate memory for storing MAC addresses */
 736         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 737                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 738         if (eth_dev->data->mac_addrs == NULL) {
 739                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 740                                                 "store MAC addresses",
 741                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 742                 error = -ENOMEM;
 743                 goto err_late;
 744         }
 745
 746         /* Copy the permanent MAC address */
 747         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 748
 749         /* initialize the vfta */
 750         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 751
 752         /* Now initialize the hardware */
 753         if (igb_hardware_init(hw) != 0) {
 754                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 755                 rte_free(eth_dev->data->mac_addrs);
 756                 eth_dev->data->mac_addrs = NULL;
 757                 error = -ENODEV;
 758                 goto err_late;
 759         }
 760         hw->mac.get_link_status = 1;
 761         adapter->stopped = 0;
 762
 763         /* Indicate SOL/IDER usage */
 764         if (e1000_check_reset_block(hw) < 0) {
 765                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 766                                         "SOL/IDER session");
 767         }
 768
 769         /* initialize PF if max_vfs not zero */
 770         igb_pf_host_init(eth_dev);
 771
 772         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 773         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 774         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 775         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 776         E1000_WRITE_FLUSH(hw);
 777
 778         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 779                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 780                      pci_dev->id.device_id);
 781
 782         rte_intr_callback_register(&pci_dev->intr_handle,
 783                                    eth_igb_interrupt_handler,
 784                                    (void *)eth_dev);
 785
 786         /* enable uio/vfio intr/eventfd mapping */
 787         rte_intr_enable(&pci_dev->intr_handle);
 788
 789         /* enable support intr */
 790         igb_intr_enable(eth_dev);
 791
 792         TAILQ_INIT(&filter_info->flex_list);
 793         filter_info->flex_mask = 0;
 794         TAILQ_INIT(&filter_info->twotuple_list);
 795         filter_info->twotuple_mask = 0;
 796         TAILQ_INIT(&filter_info->fivetuple_list);
 797         filter_info->fivetuple_mask = 0;
 798
 799         return 0;
 800
 801 err_late:
 802         igb_hw_control_release(hw);
 803
 804         return error;
 805 }
 806
 807 static int
 808 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 809 {
 810         struct rte_pci_device *pci_dev;
 811         struct e1000_hw *hw;
 812         struct e1000_adapter *adapter =
 813                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 814
 815         PMD_INIT_FUNC_TRACE();
 816
 817         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 818                 return -EPERM;
 819
 820         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 821         pci_dev = eth_dev->pci_dev;
 822
 823         if (adapter->stopped == 0)
 824                 eth_igb_close(eth_dev);
 825
 826         eth_dev->dev_ops = NULL;
 827         eth_dev->rx_pkt_burst = NULL;
 828         eth_dev->tx_pkt_burst = NULL;
 829
 830         /* Reset any pending lock */
 831         igb_reset_swfw_lock(hw);
 832
 833         rte_free(eth_dev->data->mac_addrs);
 834         eth_dev->data->mac_addrs = NULL;
 835
 836         /* uninitialize PF if max_vfs not zero */
 837         igb_pf_host_uninit(eth_dev);
 838
 839         /* disable uio intr before callback unregister */
 840         rte_intr_disable(&(pci_dev->intr_handle));
 841         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 842                 eth_igb_interrupt_handler, (void *)eth_dev);
 843
 844         return 0;
 845 }
 846
 847 /*
 848  * Virtual Function device init
 849  */
 850 static int
 851 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 852 {
 853         struct rte_pci_device *pci_dev;
 854         struct e1000_adapter *adapter =
 855                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 856         struct e1000_hw *hw =
 857                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 858         int diag;
 859         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 860
 861         PMD_INIT_FUNC_TRACE();
 862
 863         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 864         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 865         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 866
 867         /* for secondary processes, we don't initialise any further as primary
 868          * has already done this work. Only check we don't need a different
 869          * RX function */
 870         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 871                 if (eth_dev->data->scattered_rx)
 872                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 873                 return 0;
 874         }
 875
 876         pci_dev = eth_dev->pci_dev;
 877
 878         rte_eth_copy_pci_info(eth_dev, pci_dev);
 879
 880         hw->device_id = pci_dev->id.device_id;
 881         hw->vendor_id = pci_dev->id.vendor_id;
 882         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 883         adapter->stopped = 0;
 884
 885         /* Initialize the shared code (base driver) */
 886         diag = e1000_setup_init_funcs(hw, TRUE);
 887         if (diag != 0) {
 888                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 889                         diag);
 890                 return -EIO;
 891         }
 892
 893         /* init_mailbox_params */
 894         hw->mbx.ops.init_params(hw);
 895
 896         /* Disable the interrupts for VF */
 897         igbvf_intr_disable(hw);
 898
 899         diag = hw->mac.ops.reset_hw(hw);
 900
 901         /* Allocate memory for storing MAC addresses */
 902         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 903                 hw->mac.rar_entry_count, 0);
 904         if (eth_dev->data->mac_addrs == NULL) {
 905                 PMD_INIT_LOG(ERR,
 906                         "Failed to allocate %d bytes needed to store MAC "
 907                         "addresses",
 908                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 909                 return -ENOMEM;
 910         }
 911
 912         /* Generate a random MAC address, if none was assigned by PF. */
 913         if (is_zero_ether_addr(perm_addr)) {
 914                 eth_random_addr(perm_addr->addr_bytes);
 915                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
 916                 if (diag) {
 917                         rte_free(eth_dev->data->mac_addrs);
 918                         eth_dev->data->mac_addrs = NULL;
 919                         return diag;
 920                 }
 921                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
 922                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
 923                              "%02x:%02x:%02x:%02x:%02x:%02x",
 924                              perm_addr->addr_bytes[0],
 925                              perm_addr->addr_bytes[1],
 926                              perm_addr->addr_bytes[2],
 927                              perm_addr->addr_bytes[3],
 928                              perm_addr->addr_bytes[4],
 929                              perm_addr->addr_bytes[5]);
 930         }
 931
 932         /* Copy the permanent MAC address */
 933         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 934                         &eth_dev->data->mac_addrs[0]);
 935
 936         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 937                      "mac.type=%s",
 938                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 939                      pci_dev->id.device_id, "igb_mac_82576_vf");
 940
 941         return 0;
 942 }
 943
 944 static int
 945 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
 946 {
 947         struct e1000_adapter *adapter =
 948                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 949
 950         PMD_INIT_FUNC_TRACE();
 951
 952         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 953                 return -EPERM;
 954
 955         if (adapter->stopped == 0)
 956                 igbvf_dev_close(eth_dev);
 957
 958         eth_dev->dev_ops = NULL;
 959         eth_dev->rx_pkt_burst = NULL;
 960         eth_dev->tx_pkt_burst = NULL;
 961
 962         rte_free(eth_dev->data->mac_addrs);
 963         eth_dev->data->mac_addrs = NULL;
 964
 965         return 0;
 966 }
 967
 968 static struct eth_driver rte_igb_pmd = {
 969         .pci_drv = {
 970                 .name = "rte_igb_pmd",
 971                 .id_table = pci_id_igb_map,
 972                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 973                         RTE_PCI_DRV_DETACHABLE,
 974         },
 975         .eth_dev_init = eth_igb_dev_init,
 976         .eth_dev_uninit = eth_igb_dev_uninit,
 977         .dev_private_size = sizeof(struct e1000_adapter),
 978 };
 979
 980 /*
 981  * virtual function driver struct
 982  */
 983 static struct eth_driver rte_igbvf_pmd = {
 984         .pci_drv = {
 985                 .name = "rte_igbvf_pmd",
 986                 .id_table = pci_id_igbvf_map,
 987                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
 988         },
 989         .eth_dev_init = eth_igbvf_dev_init,
 990         .eth_dev_uninit = eth_igbvf_dev_uninit,
 991         .dev_private_size = sizeof(struct e1000_adapter),
 992 };
 993
 994 static int
 995 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 996 {
 997         rte_eth_driver_register(&rte_igb_pmd);
 998         return 0;
 999 }
1000
1001 static void
1002 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1003 {
1004         struct e1000_hw *hw =
1005                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1006         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1007         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1008         rctl |= E1000_RCTL_VFE;
1009         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1010 }
1011
1012 /*
1013  * VF Driver initialization routine.
1014  * Invoked one at EAL init time.
1015  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
1016  */
1017 static int
1018 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1019 {
1020         PMD_INIT_FUNC_TRACE();
1021
1022         rte_eth_driver_register(&rte_igbvf_pmd);
1023         return 0;
1024 }
1025
1026 static int
1027 igb_check_mq_mode(struct rte_eth_dev *dev)
1028 {
1029         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1030         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1031         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1032         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1033
1034         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1035             tx_mq_mode == ETH_MQ_TX_DCB ||
1036             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1037                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1038                 return -EINVAL;
1039         }
1040         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1041                 /* Check multi-queue mode.
1042                  * To no break software we accept ETH_MQ_RX_NONE as this might
1043                  * be used to turn off VLAN filter.
1044                  */
1045
1046                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1047                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1048                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1049                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1050                 } else {
1051                         /* Only support one queue on VFs.
1052                          * RSS together with SRIOV is not supported.
1053                          */
1054                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1055                                         " wrong mq_mode rx %d.",
1056                                         rx_mq_mode);
1057                         return -EINVAL;
1058                 }
1059                 /* TX mode is not used here, so mode might be ignored.*/
1060                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1061                         /* SRIOV only works in VMDq enable mode */
1062                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1063                                         " TX mode %d is not supported. "
1064                                         " Driver will behave as %d mode.",
1065                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1066                 }
1067
1068                 /* check valid queue number */
1069                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1070                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1071                                         " only support one queue on VFs.");
1072                         return -EINVAL;
1073                 }
1074         } else {
1075                 /* To no break software that set invalid mode, only display
1076                  * warning if invalid mode is used.
1077                  */
1078                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1079                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1080                     rx_mq_mode != ETH_MQ_RX_RSS) {
1081                         /* RSS together with VMDq not supported*/
1082                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1083                                      rx_mq_mode);
1084                         return -EINVAL;
1085                 }
1086
1087                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1088                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1089                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1090                                         " Due to txmode is meaningless in this"
1091                                         " driver, just ignore.",
1092                                         tx_mq_mode);
1093                 }
1094         }
1095         return 0;
1096 }
1097
1098 static int
1099 eth_igb_configure(struct rte_eth_dev *dev)
1100 {
1101         struct e1000_interrupt *intr =
1102                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1103         int ret;
1104
1105         PMD_INIT_FUNC_TRACE();
1106
1107         /* multipe queue mode checking */
1108         ret  = igb_check_mq_mode(dev);
1109         if (ret != 0) {
1110                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1111                             ret);
1112                 return ret;
1113         }
1114
1115         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1116         PMD_INIT_FUNC_TRACE();
1117
1118         return 0;
1119 }
1120
1121 static int
1122 eth_igb_start(struct rte_eth_dev *dev)
1123 {
1124         struct e1000_hw *hw =
1125                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1126         struct e1000_adapter *adapter =
1127                 E1000_DEV_PRIVATE(dev->data->dev_private);
1128         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1129         int ret, mask;
1130         uint32_t intr_vector = 0;
1131         uint32_t ctrl_ext;
1132
1133         PMD_INIT_FUNC_TRACE();
1134
1135         /* disable uio/vfio intr/eventfd mapping */
1136         rte_intr_disable(intr_handle);
1137
1138         /* Power up the phy. Needed to make the link go Up */
1139         e1000_power_up_phy(hw);
1140
1141         /*
1142          * Packet Buffer Allocation (PBA)
1143          * Writing PBA sets the receive portion of the buffer
1144          * the remainder is used for the transmit buffer.
1145          */
1146         if (hw->mac.type == e1000_82575) {
1147                 uint32_t pba;
1148
1149                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1150                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1151         }
1152
1153         /* Put the address into the Receive Address Array */
1154         e1000_rar_set(hw, hw->mac.addr, 0);
1155
1156         /* Initialize the hardware */
1157         if (igb_hardware_init(hw)) {
1158                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1159                 return -EIO;
1160         }
1161         adapter->stopped = 0;
1162
1163         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1164
1165         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1166         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1167         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1168         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1169         E1000_WRITE_FLUSH(hw);
1170
1171         /* configure PF module if SRIOV enabled */
1172         igb_pf_host_configure(dev);
1173
1174         /* check and configure queue intr-vector mapping */
1175         if ((rte_intr_cap_multiple(intr_handle) ||
1176              !RTE_ETH_DEV_SRIOV(dev).active) &&
1177             dev->data->dev_conf.intr_conf.rxq != 0) {
1178                 intr_vector = dev->data->nb_rx_queues;
1179                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1180                         return -1;
1181         }
1182
1183         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1184                 intr_handle->intr_vec =
1185                         rte_zmalloc("intr_vec",
1186                                     dev->data->nb_rx_queues * sizeof(int), 0);
1187                 if (intr_handle->intr_vec == NULL) {
1188                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1189                                      " intr_vec\n", dev->data->nb_rx_queues);
1190                         return -ENOMEM;
1191                 }
1192         }
1193
1194         /* confiugre msix for rx interrupt */
1195         eth_igb_configure_msix_intr(dev);
1196
1197         /* Configure for OS presence */
1198         igb_init_manageability(hw);
1199
1200         eth_igb_tx_init(dev);
1201
1202         /* This can fail when allocating mbufs for descriptor rings */
1203         ret = eth_igb_rx_init(dev);
1204         if (ret) {
1205                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1206                 igb_dev_clear_queues(dev);
1207                 return ret;
1208         }
1209
1210         e1000_clear_hw_cntrs_base_generic(hw);
1211
1212         /*
1213          * VLAN Offload Settings
1214          */
1215         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1216                         ETH_VLAN_EXTEND_MASK;
1217         eth_igb_vlan_offload_set(dev, mask);
1218
1219         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1220                 /* Enable VLAN filter since VMDq always use VLAN filter */
1221                 igb_vmdq_vlan_hw_filter_enable(dev);
1222         }
1223
1224         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1225                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1226                 (hw->mac.type == e1000_i211)) {
1227                 /* Configure EITR with the maximum possible value (0xFFFF) */
1228                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1229         }
1230
1231         /* Setup link speed and duplex */
1232         switch (dev->data->dev_conf.link_speed) {
1233         case ETH_LINK_SPEED_AUTONEG:
1234                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1235                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1236                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1237                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
1238                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1239                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
1240                 else
1241                         goto error_invalid_config;
1242                 break;
1243         case ETH_LINK_SPEED_10:
1244                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1245                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
1246                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1247                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
1248                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1249                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1250                 else
1251                         goto error_invalid_config;
1252                 break;
1253         case ETH_LINK_SPEED_100:
1254                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1255                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1256                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1257                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1258                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1259                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1260                 else
1261                         goto error_invalid_config;
1262                 break;
1263         case ETH_LINK_SPEED_1000:
1264                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1265                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1266                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1267                 else
1268                         goto error_invalid_config;
1269                 break;
1270         case ETH_LINK_SPEED_10000:
1271         default:
1272                 goto error_invalid_config;
1273         }
1274         e1000_setup_link(hw);
1275
1276         if (rte_intr_allow_others(intr_handle)) {
1277                 /* check if lsc interrupt is enabled */
1278                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1279                         eth_igb_lsc_interrupt_setup(dev);
1280         } else {
1281                 rte_intr_callback_unregister(intr_handle,
1282                                              eth_igb_interrupt_handler,
1283                                              (void *)dev);
1284                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1285                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1286                                      " no intr multiplex\n");
1287         }
1288
1289         /* check if rxq interrupt is enabled */
1290         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1291             rte_intr_dp_is_en(intr_handle))
1292                 eth_igb_rxq_interrupt_setup(dev);
1293
1294         /* enable uio/vfio intr/eventfd mapping */
1295         rte_intr_enable(intr_handle);
1296
1297         /* resume enabled intr since hw reset */
1298         igb_intr_enable(dev);
1299
1300         PMD_INIT_LOG(DEBUG, "<<");
1301
1302         return 0;
1303
1304 error_invalid_config:
1305         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1306                      dev->data->dev_conf.link_speed,
1307                      dev->data->dev_conf.link_duplex, dev->data->port_id);
1308         igb_dev_clear_queues(dev);
1309         return -EINVAL;
1310 }
1311
1312 /*********************************************************************
1313  *
1314  *  This routine disables all traffic on the adapter by issuing a
1315  *  global reset on the MAC.
1316  *
1317  **********************************************************************/
1318 static void
1319 eth_igb_stop(struct rte_eth_dev *dev)
1320 {
1321         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1322         struct e1000_filter_info *filter_info =
1323                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1324         struct rte_eth_link link;
1325         struct e1000_flex_filter *p_flex;
1326         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1327         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1328         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1329
1330         igb_intr_disable(hw);
1331
1332         /* disable intr eventfd mapping */
1333         rte_intr_disable(intr_handle);
1334
1335         igb_pf_reset_hw(hw);
1336         E1000_WRITE_REG(hw, E1000_WUC, 0);
1337
1338         /* Set bit for Go Link disconnect */
1339         if (hw->mac.type >= e1000_82580) {
1340                 uint32_t phpm_reg;
1341
1342                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1343                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1344                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1345         }
1346
1347         /* Power down the phy. Needed to make the link go Down */
1348         if (hw->phy.media_type == e1000_media_type_copper)
1349                 e1000_power_down_phy(hw);
1350         else
1351                 e1000_shutdown_fiber_serdes_link(hw);
1352
1353         igb_dev_clear_queues(dev);
1354
1355         /* clear the recorded link status */
1356         memset(&link, 0, sizeof(link));
1357         rte_igb_dev_atomic_write_link_status(dev, &link);
1358
1359         /* Remove all flex filters of the device */
1360         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1361                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1362                 rte_free(p_flex);
1363         }
1364         filter_info->flex_mask = 0;
1365
1366         /* Remove all ntuple filters of the device */
1367         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1368              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1369                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1370                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1371                              p_5tuple, entries);
1372                 rte_free(p_5tuple);
1373         }
1374         filter_info->fivetuple_mask = 0;
1375         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1376              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1377                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1378                 TAILQ_REMOVE(&filter_info->twotuple_list,
1379                              p_2tuple, entries);
1380                 rte_free(p_2tuple);
1381         }
1382         filter_info->twotuple_mask = 0;
1383
1384         if (!rte_intr_allow_others(intr_handle))
1385                 /* resume to the default handler */
1386                 rte_intr_callback_register(intr_handle,
1387                                            eth_igb_interrupt_handler,
1388                                            (void *)dev);
1389
1390         /* Clean datapath event and queue/vec mapping */
1391         rte_intr_efd_disable(intr_handle);
1392         if (intr_handle->intr_vec != NULL) {
1393                 rte_free(intr_handle->intr_vec);
1394                 intr_handle->intr_vec = NULL;
1395         }
1396 }
1397
1398 static void
1399 eth_igb_close(struct rte_eth_dev *dev)
1400 {
1401         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1402         struct e1000_adapter *adapter =
1403                 E1000_DEV_PRIVATE(dev->data->dev_private);
1404         struct rte_eth_link link;
1405         struct rte_pci_device *pci_dev;
1406
1407         eth_igb_stop(dev);
1408         adapter->stopped = 1;
1409
1410         e1000_phy_hw_reset(hw);
1411         igb_release_manageability(hw);
1412         igb_hw_control_release(hw);
1413
1414         /* Clear bit for Go Link disconnect */
1415         if (hw->mac.type >= e1000_82580) {
1416                 uint32_t phpm_reg;
1417
1418                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1419                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1420                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1421         }
1422
1423         igb_dev_free_queues(dev);
1424
1425         pci_dev = dev->pci_dev;
1426         if (pci_dev->intr_handle.intr_vec) {
1427                 rte_free(pci_dev->intr_handle.intr_vec);
1428                 pci_dev->intr_handle.intr_vec = NULL;
1429         }
1430
1431         memset(&link, 0, sizeof(link));
1432         rte_igb_dev_atomic_write_link_status(dev, &link);
1433 }
1434
1435 static int
1436 igb_get_rx_buffer_size(struct e1000_hw *hw)
1437 {
1438         uint32_t rx_buf_size;
1439         if (hw->mac.type == e1000_82576) {
1440                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1441         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1442                 /* PBS needs to be translated according to a lookup table */
1443                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1444                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1445                 rx_buf_size = (rx_buf_size << 10);
1446         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1447                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1448         } else {
1449                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1450         }
1451
1452         return rx_buf_size;
1453 }
1454
1455 /*********************************************************************
1456  *
1457  *  Initialize the hardware
1458  *
1459  **********************************************************************/
1460 static int
1461 igb_hardware_init(struct e1000_hw *hw)
1462 {
1463         uint32_t rx_buf_size;
1464         int diag;
1465
1466         /* Let the firmware know the OS is in control */
1467         igb_hw_control_acquire(hw);
1468
1469         /*
1470          * These parameters control the automatic generation (Tx) and
1471          * response (Rx) to Ethernet PAUSE frames.
1472          * - High water mark should allow for at least two standard size (1518)
1473          *   frames to be received after sending an XOFF.
1474          * - Low water mark works best when it is very near the high water mark.
1475          *   This allows the receiver to restart by sending XON when it has
1476          *   drained a bit. Here we use an arbitrary value of 1500 which will
1477          *   restart after one full frame is pulled from the buffer. There
1478          *   could be several smaller frames in the buffer and if so they will
1479          *   not trigger the XON until their total number reduces the buffer
1480          *   by 1500.
1481          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1482          */
1483         rx_buf_size = igb_get_rx_buffer_size(hw);
1484
1485         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1486         hw->fc.low_water = hw->fc.high_water - 1500;
1487         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1488         hw->fc.send_xon = 1;
1489
1490         /* Set Flow control, use the tunable location if sane */
1491         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1492                 hw->fc.requested_mode = igb_fc_setting;
1493         else
1494                 hw->fc.requested_mode = e1000_fc_none;
1495
1496         /* Issue a global reset */
1497         igb_pf_reset_hw(hw);
1498         E1000_WRITE_REG(hw, E1000_WUC, 0);
1499
1500         diag = e1000_init_hw(hw);
1501         if (diag < 0)
1502                 return diag;
1503
1504         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1505         e1000_get_phy_info(hw);
1506         e1000_check_for_link(hw);
1507
1508         return 0;
1509 }
1510
1511 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1512 static void
1513 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1514 {
1515         int pause_frames;
1516
1517         uint64_t old_gprc  = stats->gprc;
1518         uint64_t old_gptc  = stats->gptc;
1519         uint64_t old_tpr   = stats->tpr;
1520         uint64_t old_tpt   = stats->tpt;
1521         uint64_t old_rpthc = stats->rpthc;
1522         uint64_t old_hgptc = stats->hgptc;
1523
1524         if(hw->phy.media_type == e1000_media_type_copper ||
1525             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1526                 stats->symerrs +=
1527                     E1000_READ_REG(hw,E1000_SYMERRS);
1528                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1529         }
1530
1531         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1532         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1533         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1534         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1535
1536         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1537         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1538         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1539         stats->dc += E1000_READ_REG(hw, E1000_DC);
1540         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1541         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1542         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1543         /*
1544         ** For watchdog management we need to know if we have been
1545         ** paused during the last interval, so capture that here.
1546         */
1547         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1548         stats->xoffrxc += pause_frames;
1549         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1550         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1551         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1552         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1553         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1554         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1555         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1556         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1557         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1558         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1559         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1560         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1561
1562         /* For the 64-bit byte counters the low dword must be read first. */
1563         /* Both registers clear on the read of the high dword */
1564
1565         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1566         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1567         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1568         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1569         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1570         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1571         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1572
1573         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1574         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1575         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1576         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1577         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1578
1579         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1580         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1581
1582         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1583         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1584         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1585         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1586         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1587         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1588
1589         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1590         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1591         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1592         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1593         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1594         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1595         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1596         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1597
1598         /* Interrupt Counts */
1599
1600         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1601         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1602         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1603         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1604         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1605         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1606         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1607         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1608         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1609
1610         /* Host to Card Statistics */
1611
1612         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1613         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1614         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1615         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1616         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1617         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1618         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1619         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1620         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1621         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1622         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1623         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1624         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1625         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1626         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1627         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1628
1629         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1630         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1631         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1632         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1633         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1634         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1635 }
1636
1637 static void
1638 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1639 {
1640         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1641         struct e1000_hw_stats *stats =
1642                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1643
1644         igb_read_stats_registers(hw, stats);
1645
1646         if (rte_stats == NULL)
1647                 return;
1648
1649         /* Rx Errors */
1650         rte_stats->imissed = stats->mpc;
1651         rte_stats->ierrors = stats->crcerrs +
1652                              stats->rlec + stats->ruc + stats->roc +
1653                              rte_stats->imissed +
1654                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1655
1656         /* Tx Errors */
1657         rte_stats->oerrors = stats->ecol + stats->latecol;
1658
1659         rte_stats->ipackets = stats->gprc;
1660         rte_stats->opackets = stats->gptc;
1661         rte_stats->ibytes   = stats->gorc;
1662         rte_stats->obytes   = stats->gotc;
1663 }
1664
1665 static void
1666 eth_igb_stats_reset(struct rte_eth_dev *dev)
1667 {
1668         struct e1000_hw_stats *hw_stats =
1669                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1670
1671         /* HW registers are cleared on read */
1672         eth_igb_stats_get(dev, NULL);
1673
1674         /* Reset software totals */
1675         memset(hw_stats, 0, sizeof(*hw_stats));
1676 }
1677
1678 static void
1679 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1680 {
1681         struct e1000_hw_stats *stats =
1682                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1683
1684         /* HW registers are cleared on read */
1685         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1686
1687         /* Reset software totals */
1688         memset(stats, 0, sizeof(*stats));
1689 }
1690
1691 static int
1692 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1693                    unsigned n)
1694 {
1695         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1696         struct e1000_hw_stats *hw_stats =
1697                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1698         unsigned i;
1699
1700         if (n < IGB_NB_XSTATS)
1701                 return IGB_NB_XSTATS;
1702
1703         igb_read_stats_registers(hw, hw_stats);
1704
1705         /* If this is a reset xstats is NULL, and we have cleared the
1706          * registers by reading them.
1707          */
1708         if (!xstats)
1709                 return 0;
1710
1711         /* Extended stats */
1712         for (i = 0; i < IGB_NB_XSTATS; i++) {
1713                 snprintf(xstats[i].name, sizeof(xstats[i].name),
1714                          "%s", rte_igb_stats_strings[i].name);
1715                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1716                         rte_igb_stats_strings[i].offset);
1717         }
1718
1719         return IGB_NB_XSTATS;
1720 }
1721
1722 static void
1723 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1724 {
1725         /* Good Rx packets, include VF loopback */
1726         UPDATE_VF_STAT(E1000_VFGPRC,
1727             hw_stats->last_gprc, hw_stats->gprc);
1728
1729         /* Good Rx octets, include VF loopback */
1730         UPDATE_VF_STAT(E1000_VFGORC,
1731             hw_stats->last_gorc, hw_stats->gorc);
1732
1733         /* Good Tx packets, include VF loopback */
1734         UPDATE_VF_STAT(E1000_VFGPTC,
1735             hw_stats->last_gptc, hw_stats->gptc);
1736
1737         /* Good Tx octets, include VF loopback */
1738         UPDATE_VF_STAT(E1000_VFGOTC,
1739             hw_stats->last_gotc, hw_stats->gotc);
1740
1741         /* Rx Multicst packets */
1742         UPDATE_VF_STAT(E1000_VFMPRC,
1743             hw_stats->last_mprc, hw_stats->mprc);
1744
1745         /* Good Rx loopback packets */
1746         UPDATE_VF_STAT(E1000_VFGPRLBC,
1747             hw_stats->last_gprlbc, hw_stats->gprlbc);
1748
1749         /* Good Rx loopback octets */
1750         UPDATE_VF_STAT(E1000_VFGORLBC,
1751             hw_stats->last_gorlbc, hw_stats->gorlbc);
1752
1753         /* Good Tx loopback packets */
1754         UPDATE_VF_STAT(E1000_VFGPTLBC,
1755             hw_stats->last_gptlbc, hw_stats->gptlbc);
1756
1757         /* Good Tx loopback octets */
1758         UPDATE_VF_STAT(E1000_VFGOTLBC,
1759             hw_stats->last_gotlbc, hw_stats->gotlbc);
1760 }
1761
1762 static int
1763 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1764                      unsigned n)
1765 {
1766         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1767         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1768                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1769         unsigned i;
1770
1771         if (n < IGBVF_NB_XSTATS)
1772                 return IGBVF_NB_XSTATS;
1773
1774         igbvf_read_stats_registers(hw, hw_stats);
1775
1776         if (!xstats)
1777                 return 0;
1778
1779         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1780                 snprintf(xstats[i].name, sizeof(xstats[i].name), "%s",
1781                          rte_igbvf_stats_strings[i].name);
1782                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1783                         rte_igbvf_stats_strings[i].offset);
1784         }
1785
1786         return IGBVF_NB_XSTATS;
1787 }
1788
1789 static void
1790 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1791 {
1792         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1793         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1794                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1795
1796         igbvf_read_stats_registers(hw, hw_stats);
1797
1798         if (rte_stats == NULL)
1799                 return;
1800
1801         rte_stats->ipackets = hw_stats->gprc;
1802         rte_stats->ibytes = hw_stats->gorc;
1803         rte_stats->opackets = hw_stats->gptc;
1804         rte_stats->obytes = hw_stats->gotc;
1805         rte_stats->imcasts = hw_stats->mprc;
1806         rte_stats->ilbpackets = hw_stats->gprlbc;
1807         rte_stats->ilbbytes = hw_stats->gorlbc;
1808         rte_stats->olbpackets = hw_stats->gptlbc;
1809         rte_stats->olbbytes = hw_stats->gotlbc;
1810 }
1811
1812 static void
1813 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1814 {
1815         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1816                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1817
1818         /* Sync HW register to the last stats */
1819         eth_igbvf_stats_get(dev, NULL);
1820
1821         /* reset HW current stats*/
1822         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1823                offsetof(struct e1000_vf_stats, gprc));
1824 }
1825
1826 static void
1827 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1828 {
1829         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1830
1831         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1832         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1833         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1834         dev_info->rx_offload_capa =
1835                 DEV_RX_OFFLOAD_VLAN_STRIP |
1836                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1837                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1838                 DEV_RX_OFFLOAD_TCP_CKSUM;
1839         dev_info->tx_offload_capa =
1840                 DEV_TX_OFFLOAD_VLAN_INSERT |
1841                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1842                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1843                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1844                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1845                 DEV_TX_OFFLOAD_TCP_TSO;
1846
1847         switch (hw->mac.type) {
1848         case e1000_82575:
1849                 dev_info->max_rx_queues = 4;
1850                 dev_info->max_tx_queues = 4;
1851                 dev_info->max_vmdq_pools = 0;
1852                 break;
1853
1854         case e1000_82576:
1855                 dev_info->max_rx_queues = 16;
1856                 dev_info->max_tx_queues = 16;
1857                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1858                 dev_info->vmdq_queue_num = 16;
1859                 break;
1860
1861         case e1000_82580:
1862                 dev_info->max_rx_queues = 8;
1863                 dev_info->max_tx_queues = 8;
1864                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1865                 dev_info->vmdq_queue_num = 8;
1866                 break;
1867
1868         case e1000_i350:
1869                 dev_info->max_rx_queues = 8;
1870                 dev_info->max_tx_queues = 8;
1871                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1872                 dev_info->vmdq_queue_num = 8;
1873                 break;
1874
1875         case e1000_i354:
1876                 dev_info->max_rx_queues = 8;
1877                 dev_info->max_tx_queues = 8;
1878                 break;
1879
1880         case e1000_i210:
1881                 dev_info->max_rx_queues = 4;
1882                 dev_info->max_tx_queues = 4;
1883                 dev_info->max_vmdq_pools = 0;
1884                 break;
1885
1886         case e1000_i211:
1887                 dev_info->max_rx_queues = 2;
1888                 dev_info->max_tx_queues = 2;
1889                 dev_info->max_vmdq_pools = 0;
1890                 break;
1891
1892         default:
1893                 /* Should not happen */
1894                 break;
1895         }
1896         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1897         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1898         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1899
1900         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1901                 .rx_thresh = {
1902                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1903                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1904                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1905                 },
1906                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1907                 .rx_drop_en = 0,
1908         };
1909
1910         dev_info->default_txconf = (struct rte_eth_txconf) {
1911                 .tx_thresh = {
1912                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1913                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1914                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1915                 },
1916                 .txq_flags = 0,
1917         };
1918
1919         dev_info->rx_desc_lim = rx_desc_lim;
1920         dev_info->tx_desc_lim = tx_desc_lim;
1921 }
1922
1923 static void
1924 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1925 {
1926         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927
1928         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1929         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1930         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1931         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1932                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1933                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1934                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1935         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1936                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1937                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1938                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1939                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1940                                 DEV_TX_OFFLOAD_TCP_TSO;
1941         switch (hw->mac.type) {
1942         case e1000_vfadapt:
1943                 dev_info->max_rx_queues = 2;
1944                 dev_info->max_tx_queues = 2;
1945                 break;
1946         case e1000_vfadapt_i350:
1947                 dev_info->max_rx_queues = 1;
1948                 dev_info->max_tx_queues = 1;
1949                 break;
1950         default:
1951                 /* Should not happen */
1952                 break;
1953         }
1954
1955         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1956                 .rx_thresh = {
1957                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1958                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1959                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1960                 },
1961                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1962                 .rx_drop_en = 0,
1963         };
1964
1965         dev_info->default_txconf = (struct rte_eth_txconf) {
1966                 .tx_thresh = {
1967                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1968                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1969                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1970                 },
1971                 .txq_flags = 0,
1972         };
1973
1974         dev_info->rx_desc_lim = rx_desc_lim;
1975         dev_info->tx_desc_lim = tx_desc_lim;
1976 }
1977
1978 /* return 0 means link status changed, -1 means not changed */
1979 static int
1980 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1981 {
1982         struct e1000_hw *hw =
1983                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1984         struct rte_eth_link link, old;
1985         int link_check, count;
1986
1987         link_check = 0;
1988         hw->mac.get_link_status = 1;
1989
1990         /* possible wait-to-complete in up to 9 seconds */
1991         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1992                 /* Read the real link status */
1993                 switch (hw->phy.media_type) {
1994                 case e1000_media_type_copper:
1995                         /* Do the work to read phy */
1996                         e1000_check_for_link(hw);
1997                         link_check = !hw->mac.get_link_status;
1998                         break;
1999
2000                 case e1000_media_type_fiber:
2001                         e1000_check_for_link(hw);
2002                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2003                                       E1000_STATUS_LU);
2004                         break;
2005
2006                 case e1000_media_type_internal_serdes:
2007                         e1000_check_for_link(hw);
2008                         link_check = hw->mac.serdes_has_link;
2009                         break;
2010
2011                 /* VF device is type_unknown */
2012                 case e1000_media_type_unknown:
2013                         eth_igbvf_link_update(hw);
2014                         link_check = !hw->mac.get_link_status;
2015                         break;
2016
2017                 default:
2018                         break;
2019                 }
2020                 if (link_check || wait_to_complete == 0)
2021                         break;
2022                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2023         }
2024         memset(&link, 0, sizeof(link));
2025         rte_igb_dev_atomic_read_link_status(dev, &link);
2026         old = link;
2027
2028         /* Now we check if a transition has happened */
2029         if (link_check) {
2030                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
2031                                           &link.link_duplex);
2032                 link.link_status = 1;
2033         } else if (!link_check) {
2034                 link.link_speed = 0;
2035                 link.link_duplex = 0;
2036                 link.link_status = 0;
2037         }
2038         rte_igb_dev_atomic_write_link_status(dev, &link);
2039
2040         /* not changed */
2041         if (old.link_status == link.link_status)
2042                 return -1;
2043
2044         /* changed */
2045         return 0;
2046 }
2047
2048 /*
2049  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2050  * For ASF and Pass Through versions of f/w this means
2051  * that the driver is loaded.
2052  */
2053 static void
2054 igb_hw_control_acquire(struct e1000_hw *hw)
2055 {
2056         uint32_t ctrl_ext;
2057
2058         /* Let firmware know the driver has taken over */
2059         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2060         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2061 }
2062
2063 /*
2064  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2065  * For ASF and Pass Through versions of f/w this means that the
2066  * driver is no longer loaded.
2067  */
2068 static void
2069 igb_hw_control_release(struct e1000_hw *hw)
2070 {
2071         uint32_t ctrl_ext;
2072
2073         /* Let firmware taken over control of h/w */
2074         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2075         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2076                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2077 }
2078
2079 /*
2080  * Bit of a misnomer, what this really means is
2081  * to enable OS management of the system... aka
2082  * to disable special hardware management features.
2083  */
2084 static void
2085 igb_init_manageability(struct e1000_hw *hw)
2086 {
2087         if (e1000_enable_mng_pass_thru(hw)) {
2088                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2089                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2090
2091                 /* disable hardware interception of ARP */
2092                 manc &= ~(E1000_MANC_ARP_EN);
2093
2094                 /* enable receiving management packets to the host */
2095                 manc |= E1000_MANC_EN_MNG2HOST;
2096                 manc2h |= 1 << 5;  /* Mng Port 623 */
2097                 manc2h |= 1 << 6;  /* Mng Port 664 */
2098                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2099                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2100         }
2101 }
2102
2103 static void
2104 igb_release_manageability(struct e1000_hw *hw)
2105 {
2106         if (e1000_enable_mng_pass_thru(hw)) {
2107                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2108
2109                 manc |= E1000_MANC_ARP_EN;
2110                 manc &= ~E1000_MANC_EN_MNG2HOST;
2111
2112                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2113         }
2114 }
2115
2116 static void
2117 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2118 {
2119         struct e1000_hw *hw =
2120                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2121         uint32_t rctl;
2122
2123         rctl = E1000_READ_REG(hw, E1000_RCTL);
2124         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2125         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2126 }
2127
2128 static void
2129 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2130 {
2131         struct e1000_hw *hw =
2132                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2133         uint32_t rctl;
2134
2135         rctl = E1000_READ_REG(hw, E1000_RCTL);
2136         rctl &= (~E1000_RCTL_UPE);
2137         if (dev->data->all_multicast == 1)
2138                 rctl |= E1000_RCTL_MPE;
2139         else
2140                 rctl &= (~E1000_RCTL_MPE);
2141         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2142 }
2143
2144 static void
2145 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2146 {
2147         struct e1000_hw *hw =
2148                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2149         uint32_t rctl;
2150
2151         rctl = E1000_READ_REG(hw, E1000_RCTL);
2152         rctl |= E1000_RCTL_MPE;
2153         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2154 }
2155
2156 static void
2157 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2158 {
2159         struct e1000_hw *hw =
2160                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2161         uint32_t rctl;
2162
2163         if (dev->data->promiscuous == 1)
2164                 return; /* must remain in all_multicast mode */
2165         rctl = E1000_READ_REG(hw, E1000_RCTL);
2166         rctl &= (~E1000_RCTL_MPE);
2167         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2168 }
2169
2170 static int
2171 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2172 {
2173         struct e1000_hw *hw =
2174                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2175         struct e1000_vfta * shadow_vfta =
2176                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2177         uint32_t vfta;
2178         uint32_t vid_idx;
2179         uint32_t vid_bit;
2180
2181         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2182                               E1000_VFTA_ENTRY_MASK);
2183         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2184         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2185         if (on)
2186                 vfta |= vid_bit;
2187         else
2188                 vfta &= ~vid_bit;
2189         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2190
2191         /* update local VFTA copy */
2192         shadow_vfta->vfta[vid_idx] = vfta;
2193
2194         return 0;
2195 }
2196
2197 static int
2198 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2199                       enum rte_vlan_type vlan_type,
2200                       uint16_t tpid)
2201 {
2202         struct e1000_hw *hw =
2203                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2204         uint32_t reg = ETHER_TYPE_VLAN;
2205         int ret = 0;
2206
2207         switch (vlan_type) {
2208         case ETH_VLAN_TYPE_INNER:
2209                 reg |= (tpid << 16);
2210                 E1000_WRITE_REG(hw, E1000_VET, reg);
2211                 break;
2212         default:
2213                 ret = -EINVAL;
2214                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
2215                 break;
2216         }
2217
2218         return ret;
2219 }
2220
2221 static void
2222 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2223 {
2224         struct e1000_hw *hw =
2225                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2226         uint32_t reg;
2227
2228         /* Filter Table Disable */
2229         reg = E1000_READ_REG(hw, E1000_RCTL);
2230         reg &= ~E1000_RCTL_CFIEN;
2231         reg &= ~E1000_RCTL_VFE;
2232         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2233 }
2234
2235 static void
2236 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2237 {
2238         struct e1000_hw *hw =
2239                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240         struct e1000_vfta * shadow_vfta =
2241                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2242         uint32_t reg;
2243         int i;
2244
2245         /* Filter Table Enable, CFI not used for packet acceptance */
2246         reg = E1000_READ_REG(hw, E1000_RCTL);
2247         reg &= ~E1000_RCTL_CFIEN;
2248         reg |= E1000_RCTL_VFE;
2249         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2250
2251         /* restore VFTA table */
2252         for (i = 0; i < IGB_VFTA_SIZE; i++)
2253                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2254 }
2255
2256 static void
2257 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2258 {
2259         struct e1000_hw *hw =
2260                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2261         uint32_t reg;
2262
2263         /* VLAN Mode Disable */
2264         reg = E1000_READ_REG(hw, E1000_CTRL);
2265         reg &= ~E1000_CTRL_VME;
2266         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2267 }
2268
2269 static void
2270 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2271 {
2272         struct e1000_hw *hw =
2273                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2274         uint32_t reg;
2275
2276         /* VLAN Mode Enable */
2277         reg = E1000_READ_REG(hw, E1000_CTRL);
2278         reg |= E1000_CTRL_VME;
2279         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2280 }
2281
2282 static void
2283 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2284 {
2285         struct e1000_hw *hw =
2286                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2287         uint32_t reg;
2288
2289         /* CTRL_EXT: Extended VLAN */
2290         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2291         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2292         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2293
2294         /* Update maximum packet length */
2295         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2296                 E1000_WRITE_REG(hw, E1000_RLPML,
2297                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2298                                                 VLAN_TAG_SIZE);
2299 }
2300
2301 static void
2302 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2303 {
2304         struct e1000_hw *hw =
2305                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2306         uint32_t reg;
2307
2308         /* CTRL_EXT: Extended VLAN */
2309         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2310         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2311         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2312
2313         /* Update maximum packet length */
2314         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2315                 E1000_WRITE_REG(hw, E1000_RLPML,
2316                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2317                                                 2 * VLAN_TAG_SIZE);
2318 }
2319
2320 static void
2321 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2322 {
2323         if(mask & ETH_VLAN_STRIP_MASK){
2324                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2325                         igb_vlan_hw_strip_enable(dev);
2326                 else
2327                         igb_vlan_hw_strip_disable(dev);
2328         }
2329
2330         if(mask & ETH_VLAN_FILTER_MASK){
2331                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2332                         igb_vlan_hw_filter_enable(dev);
2333                 else
2334                         igb_vlan_hw_filter_disable(dev);
2335         }
2336
2337         if(mask & ETH_VLAN_EXTEND_MASK){
2338                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2339                         igb_vlan_hw_extend_enable(dev);
2340                 else
2341                         igb_vlan_hw_extend_disable(dev);
2342         }
2343 }
2344
2345
2346 /**
2347  * It enables the interrupt mask and then enable the interrupt.
2348  *
2349  * @param dev
2350  *  Pointer to struct rte_eth_dev.
2351  *
2352  * @return
2353  *  - On success, zero.
2354  *  - On failure, a negative value.
2355  */
2356 static int
2357 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2358 {
2359         struct e1000_interrupt *intr =
2360                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2361
2362         intr->mask |= E1000_ICR_LSC;
2363
2364         return 0;
2365 }
2366
2367 /* It clears the interrupt causes and enables the interrupt.
2368  * It will be called once only during nic initialized.
2369  *
2370  * @param dev
2371  *  Pointer to struct rte_eth_dev.
2372  *
2373  * @return
2374  *  - On success, zero.
2375  *  - On failure, a negative value.
2376  */
2377 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2378 {
2379         uint32_t mask, regval;
2380         struct e1000_hw *hw =
2381                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2382         struct rte_eth_dev_info dev_info;
2383
2384         memset(&dev_info, 0, sizeof(dev_info));
2385         eth_igb_infos_get(dev, &dev_info);
2386
2387         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2388         regval = E1000_READ_REG(hw, E1000_EIMS);
2389         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2390
2391         return 0;
2392 }
2393
2394 /*
2395  * It reads ICR and gets interrupt causes, check it and set a bit flag
2396  * to update link status.
2397  *
2398  * @param dev
2399  *  Pointer to struct rte_eth_dev.
2400  *
2401  * @return
2402  *  - On success, zero.
2403  *  - On failure, a negative value.
2404  */
2405 static int
2406 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2407 {
2408         uint32_t icr;
2409         struct e1000_hw *hw =
2410                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2411         struct e1000_interrupt *intr =
2412                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2413
2414         igb_intr_disable(hw);
2415
2416         /* read-on-clear nic registers here */
2417         icr = E1000_READ_REG(hw, E1000_ICR);
2418
2419         intr->flags = 0;
2420         if (icr & E1000_ICR_LSC) {
2421                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2422         }
2423
2424         if (icr & E1000_ICR_VMMB)
2425                 intr->flags |= E1000_FLAG_MAILBOX;
2426
2427         return 0;
2428 }
2429
2430 /*
2431  * It executes link_update after knowing an interrupt is prsent.
2432  *
2433  * @param dev
2434  *  Pointer to struct rte_eth_dev.
2435  *
2436  * @return
2437  *  - On success, zero.
2438  *  - On failure, a negative value.
2439  */
2440 static int
2441 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2442 {
2443         struct e1000_hw *hw =
2444                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2445         struct e1000_interrupt *intr =
2446                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2447         uint32_t tctl, rctl;
2448         struct rte_eth_link link;
2449         int ret;
2450
2451         if (intr->flags & E1000_FLAG_MAILBOX) {
2452                 igb_pf_mbx_process(dev);
2453                 intr->flags &= ~E1000_FLAG_MAILBOX;
2454         }
2455
2456         igb_intr_enable(dev);
2457         rte_intr_enable(&(dev->pci_dev->intr_handle));
2458
2459         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2460                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2461
2462                 /* set get_link_status to check register later */
2463                 hw->mac.get_link_status = 1;
2464                 ret = eth_igb_link_update(dev, 0);
2465
2466                 /* check if link has changed */
2467                 if (ret < 0)
2468                         return 0;
2469
2470                 memset(&link, 0, sizeof(link));
2471                 rte_igb_dev_atomic_read_link_status(dev, &link);
2472                 if (link.link_status) {
2473                         PMD_INIT_LOG(INFO,
2474                                      " Port %d: Link Up - speed %u Mbps - %s",
2475                                      dev->data->port_id,
2476                                      (unsigned)link.link_speed,
2477                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2478                                      "full-duplex" : "half-duplex");
2479                 } else {
2480                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2481                                      dev->data->port_id);
2482                 }
2483
2484                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2485                              dev->pci_dev->addr.domain,
2486                              dev->pci_dev->addr.bus,
2487                              dev->pci_dev->addr.devid,
2488                              dev->pci_dev->addr.function);
2489                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2490                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2491                 if (link.link_status) {
2492                         /* enable Tx/Rx */
2493                         tctl |= E1000_TCTL_EN;
2494                         rctl |= E1000_RCTL_EN;
2495                 } else {
2496                         /* disable Tx/Rx */
2497                         tctl &= ~E1000_TCTL_EN;
2498                         rctl &= ~E1000_RCTL_EN;
2499                 }
2500                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2501                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2502                 E1000_WRITE_FLUSH(hw);
2503                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2504         }
2505
2506         return 0;
2507 }
2508
2509 /**
2510  * Interrupt handler which shall be registered at first.
2511  *
2512  * @param handle
2513  *  Pointer to interrupt handle.
2514  * @param param
2515  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2516  *
2517  * @return
2518  *  void
2519  */
2520 static void
2521 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2522                                                         void *param)
2523 {
2524         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2525
2526         eth_igb_interrupt_get_status(dev);
2527         eth_igb_interrupt_action(dev);
2528 }
2529
2530 static int
2531 eth_igb_led_on(struct rte_eth_dev *dev)
2532 {
2533         struct e1000_hw *hw;
2534
2535         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2537 }
2538
2539 static int
2540 eth_igb_led_off(struct rte_eth_dev *dev)
2541 {
2542         struct e1000_hw *hw;
2543
2544         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2545         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2546 }
2547
2548 static int
2549 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2550 {
2551         struct e1000_hw *hw;
2552         uint32_t ctrl;
2553         int tx_pause;
2554         int rx_pause;
2555
2556         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2557         fc_conf->pause_time = hw->fc.pause_time;
2558         fc_conf->high_water = hw->fc.high_water;
2559         fc_conf->low_water = hw->fc.low_water;
2560         fc_conf->send_xon = hw->fc.send_xon;
2561         fc_conf->autoneg = hw->mac.autoneg;
2562
2563         /*
2564          * Return rx_pause and tx_pause status according to actual setting of
2565          * the TFCE and RFCE bits in the CTRL register.
2566          */
2567         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2568         if (ctrl & E1000_CTRL_TFCE)
2569                 tx_pause = 1;
2570         else
2571                 tx_pause = 0;
2572
2573         if (ctrl & E1000_CTRL_RFCE)
2574                 rx_pause = 1;
2575         else
2576                 rx_pause = 0;
2577
2578         if (rx_pause && tx_pause)
2579                 fc_conf->mode = RTE_FC_FULL;
2580         else if (rx_pause)
2581                 fc_conf->mode = RTE_FC_RX_PAUSE;
2582         else if (tx_pause)
2583                 fc_conf->mode = RTE_FC_TX_PAUSE;
2584         else
2585                 fc_conf->mode = RTE_FC_NONE;
2586
2587         return 0;
2588 }
2589
2590 static int
2591 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2592 {
2593         struct e1000_hw *hw;
2594         int err;
2595         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2596                 e1000_fc_none,
2597                 e1000_fc_rx_pause,
2598                 e1000_fc_tx_pause,
2599                 e1000_fc_full
2600         };
2601         uint32_t rx_buf_size;
2602         uint32_t max_high_water;
2603         uint32_t rctl;
2604
2605         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2606         if (fc_conf->autoneg != hw->mac.autoneg)
2607                 return -ENOTSUP;
2608         rx_buf_size = igb_get_rx_buffer_size(hw);
2609         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2610
2611         /* At least reserve one Ethernet frame for watermark */
2612         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2613         if ((fc_conf->high_water > max_high_water) ||
2614             (fc_conf->high_water < fc_conf->low_water)) {
2615                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2616                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2617                 return -EINVAL;
2618         }
2619
2620         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2621         hw->fc.pause_time     = fc_conf->pause_time;
2622         hw->fc.high_water     = fc_conf->high_water;
2623         hw->fc.low_water      = fc_conf->low_water;
2624         hw->fc.send_xon       = fc_conf->send_xon;
2625
2626         err = e1000_setup_link_generic(hw);
2627         if (err == E1000_SUCCESS) {
2628
2629                 /* check if we want to forward MAC frames - driver doesn't have native
2630                  * capability to do that, so we'll write the registers ourselves */
2631
2632                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2633
2634                 /* set or clear MFLCN.PMCF bit depending on configuration */
2635                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2636                         rctl |= E1000_RCTL_PMCF;
2637                 else
2638                         rctl &= ~E1000_RCTL_PMCF;
2639
2640                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2641                 E1000_WRITE_FLUSH(hw);
2642
2643                 return 0;
2644         }
2645
2646         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2647         return -EIO;
2648 }
2649
2650 #define E1000_RAH_POOLSEL_SHIFT      (18)
2651 static void
2652 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2653                 uint32_t index, __rte_unused uint32_t pool)
2654 {
2655         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2656         uint32_t rah;
2657
2658         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2659         rah = E1000_READ_REG(hw, E1000_RAH(index));
2660         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2661         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2662 }
2663
2664 static void
2665 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2666 {
2667         uint8_t addr[ETHER_ADDR_LEN];
2668         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2669
2670         memset(addr, 0, sizeof(addr));
2671
2672         e1000_rar_set(hw, addr, index);
2673 }
2674
2675 static void
2676 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2677                                 struct ether_addr *addr)
2678 {
2679         eth_igb_rar_clear(dev, 0);
2680
2681         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2682 }
2683 /*
2684  * Virtual Function operations
2685  */
2686 static void
2687 igbvf_intr_disable(struct e1000_hw *hw)
2688 {
2689         PMD_INIT_FUNC_TRACE();
2690
2691         /* Clear interrupt mask to stop from interrupts being generated */
2692         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2693
2694         E1000_WRITE_FLUSH(hw);
2695 }
2696
2697 static void
2698 igbvf_stop_adapter(struct rte_eth_dev *dev)
2699 {
2700         u32 reg_val;
2701         u16 i;
2702         struct rte_eth_dev_info dev_info;
2703         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2704
2705         memset(&dev_info, 0, sizeof(dev_info));
2706         eth_igbvf_infos_get(dev, &dev_info);
2707
2708         /* Clear interrupt mask to stop from interrupts being generated */
2709         igbvf_intr_disable(hw);
2710
2711         /* Clear any pending interrupts, flush previous writes */
2712         E1000_READ_REG(hw, E1000_EICR);
2713
2714         /* Disable the transmit unit.  Each queue must be disabled. */
2715         for (i = 0; i < dev_info.max_tx_queues; i++)
2716                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2717
2718         /* Disable the receive unit by stopping each queue */
2719         for (i = 0; i < dev_info.max_rx_queues; i++) {
2720                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2721                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2722                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2723                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2724                         ;
2725         }
2726
2727         /* flush all queues disables */
2728         E1000_WRITE_FLUSH(hw);
2729         msec_delay(2);
2730 }
2731
2732 static int eth_igbvf_link_update(struct e1000_hw *hw)
2733 {
2734         struct e1000_mbx_info *mbx = &hw->mbx;
2735         struct e1000_mac_info *mac = &hw->mac;
2736         int ret_val = E1000_SUCCESS;
2737
2738         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2739
2740         /*
2741          * We only want to run this if there has been a rst asserted.
2742          * in this case that could mean a link change, device reset,
2743          * or a virtual function reset
2744          */
2745
2746         /* If we were hit with a reset or timeout drop the link */
2747         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2748                 mac->get_link_status = TRUE;
2749
2750         if (!mac->get_link_status)
2751                 goto out;
2752
2753         /* if link status is down no point in checking to see if pf is up */
2754         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2755                 goto out;
2756
2757         /* if we passed all the tests above then the link is up and we no
2758          * longer need to check for link */
2759         mac->get_link_status = FALSE;
2760
2761 out:
2762         return ret_val;
2763 }
2764
2765
2766 static int
2767 igbvf_dev_configure(struct rte_eth_dev *dev)
2768 {
2769         struct rte_eth_conf* conf = &dev->data->dev_conf;
2770
2771         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2772                      dev->data->port_id);
2773
2774         /*
2775          * VF has no ability to enable/disable HW CRC
2776          * Keep the persistent behavior the same as Host PF
2777          */
2778 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2779         if (!conf->rxmode.hw_strip_crc) {
2780                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2781                 conf->rxmode.hw_strip_crc = 1;
2782         }
2783 #else
2784         if (conf->rxmode.hw_strip_crc) {
2785                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2786                 conf->rxmode.hw_strip_crc = 0;
2787         }
2788 #endif
2789
2790         return 0;
2791 }
2792
2793 static int
2794 igbvf_dev_start(struct rte_eth_dev *dev)
2795 {
2796         struct e1000_hw *hw =
2797                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2798         struct e1000_adapter *adapter =
2799                 E1000_DEV_PRIVATE(dev->data->dev_private);
2800         int ret;
2801
2802         PMD_INIT_FUNC_TRACE();
2803
2804         hw->mac.ops.reset_hw(hw);
2805         adapter->stopped = 0;
2806
2807         /* Set all vfta */
2808         igbvf_set_vfta_all(dev,1);
2809
2810         eth_igbvf_tx_init(dev);
2811
2812         /* This can fail when allocating mbufs for descriptor rings */
2813         ret = eth_igbvf_rx_init(dev);
2814         if (ret) {
2815                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2816                 igb_dev_clear_queues(dev);
2817                 return ret;
2818         }
2819
2820         return 0;
2821 }
2822
2823 static void
2824 igbvf_dev_stop(struct rte_eth_dev *dev)
2825 {
2826         PMD_INIT_FUNC_TRACE();
2827
2828         igbvf_stop_adapter(dev);
2829
2830         /*
2831           * Clear what we set, but we still keep shadow_vfta to
2832           * restore after device starts
2833           */
2834         igbvf_set_vfta_all(dev,0);
2835
2836         igb_dev_clear_queues(dev);
2837 }
2838
2839 static void
2840 igbvf_dev_close(struct rte_eth_dev *dev)
2841 {
2842         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843         struct e1000_adapter *adapter =
2844                 E1000_DEV_PRIVATE(dev->data->dev_private);
2845
2846         PMD_INIT_FUNC_TRACE();
2847
2848         e1000_reset_hw(hw);
2849
2850         igbvf_dev_stop(dev);
2851         adapter->stopped = 1;
2852         igb_dev_free_queues(dev);
2853 }
2854
2855 static void
2856 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
2857 {
2858         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2859
2860         /* Set both unicast and multicast promisc */
2861         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
2862 }
2863
2864 static void
2865 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
2866 {
2867         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2868
2869         /* If in allmulticast mode leave multicast promisc */
2870         if (dev->data->all_multicast == 1)
2871                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
2872         else
2873                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
2874 }
2875
2876 static void
2877 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
2878 {
2879         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2880
2881         /* In promiscuous mode multicast promisc already set */
2882         if (dev->data->promiscuous == 0)
2883                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
2884 }
2885
2886 static void
2887 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
2888 {
2889         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2890
2891         /* In promiscuous mode leave multicast promisc enabled */
2892         if (dev->data->promiscuous == 0)
2893                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
2894 }
2895
2896 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2897 {
2898         struct e1000_mbx_info *mbx = &hw->mbx;
2899         uint32_t msgbuf[2];
2900         s32 err;
2901
2902         /* After set vlan, vlan strip will also be enabled in igb driver*/
2903         msgbuf[0] = E1000_VF_SET_VLAN;
2904         msgbuf[1] = vid;
2905         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2906         if (on)
2907                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2908
2909         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
2910         if (err)
2911                 goto mbx_err;
2912
2913         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
2914         if (err)
2915                 goto mbx_err;
2916
2917         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
2918         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
2919                 err = -EINVAL;
2920
2921 mbx_err:
2922         return err;
2923 }
2924
2925 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2926 {
2927         struct e1000_hw *hw =
2928                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2929         struct e1000_vfta * shadow_vfta =
2930                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2931         int i = 0, j = 0, vfta = 0, mask = 1;
2932
2933         for (i = 0; i < IGB_VFTA_SIZE; i++){
2934                 vfta = shadow_vfta->vfta[i];
2935                 if(vfta){
2936                         mask = 1;
2937                         for (j = 0; j < 32; j++){
2938                                 if(vfta & mask)
2939                                         igbvf_set_vfta(hw,
2940                                                 (uint16_t)((i<<5)+j), on);
2941                                 mask<<=1;
2942                         }
2943                 }
2944         }
2945
2946 }
2947
2948 static int
2949 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2950 {
2951         struct e1000_hw *hw =
2952                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2953         struct e1000_vfta * shadow_vfta =
2954                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2955         uint32_t vid_idx = 0;
2956         uint32_t vid_bit = 0;
2957         int ret = 0;
2958
2959         PMD_INIT_FUNC_TRACE();
2960
2961         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2962         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2963         if(ret){
2964                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2965                 return ret;
2966         }
2967         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2968         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2969
2970         /*Save what we set and retore it after device reset*/
2971         if (on)
2972                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2973         else
2974                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2975
2976         return 0;
2977 }
2978
2979 static void
2980 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
2981 {
2982         struct e1000_hw *hw =
2983                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2984
2985         /* index is not used by rar_set() */
2986         hw->mac.ops.rar_set(hw, (void *)addr, 0);
2987 }
2988
2989
2990 static int
2991 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2992                         struct rte_eth_rss_reta_entry64 *reta_conf,
2993                         uint16_t reta_size)
2994 {
2995         uint8_t i, j, mask;
2996         uint32_t reta, r;
2997         uint16_t idx, shift;
2998         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2999
3000         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3001                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3002                         "(%d) doesn't match the number hardware can supported "
3003                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3004                 return -EINVAL;
3005         }
3006
3007         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3008                 idx = i / RTE_RETA_GROUP_SIZE;
3009                 shift = i % RTE_RETA_GROUP_SIZE;
3010                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3011                                                 IGB_4_BIT_MASK);
3012                 if (!mask)
3013                         continue;
3014                 if (mask == IGB_4_BIT_MASK)
3015                         r = 0;
3016                 else
3017                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3018                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3019                         if (mask & (0x1 << j))
3020                                 reta |= reta_conf[idx].reta[shift + j] <<
3021                                                         (CHAR_BIT * j);
3022                         else
3023                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3024                 }
3025                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3026         }
3027
3028         return 0;
3029 }
3030
3031 static int
3032 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3033                        struct rte_eth_rss_reta_entry64 *reta_conf,
3034                        uint16_t reta_size)
3035 {
3036         uint8_t i, j, mask;
3037         uint32_t reta;
3038         uint16_t idx, shift;
3039         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3040
3041         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3042                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3043                         "(%d) doesn't match the number hardware can supported "
3044                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3045                 return -EINVAL;
3046         }
3047
3048         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3049                 idx = i / RTE_RETA_GROUP_SIZE;
3050                 shift = i % RTE_RETA_GROUP_SIZE;
3051                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3052                                                 IGB_4_BIT_MASK);
3053                 if (!mask)
3054                         continue;
3055                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3056                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3057                         if (mask & (0x1 << j))
3058                                 reta_conf[idx].reta[shift + j] =
3059                                         ((reta >> (CHAR_BIT * j)) &
3060                                                 IGB_8_BIT_MASK);
3061                 }
3062         }
3063
3064         return 0;
3065 }
3066
3067 #define MAC_TYPE_FILTER_SUP(type)    do {\
3068         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3069                 (type) != e1000_82576)\
3070                 return -ENOTSUP;\
3071 } while (0)
3072
3073 static int
3074 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3075                         struct rte_eth_syn_filter *filter,
3076                         bool add)
3077 {
3078         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3079         uint32_t synqf, rfctl;
3080
3081         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3082                 return -EINVAL;
3083
3084         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3085
3086         if (add) {
3087                 if (synqf & E1000_SYN_FILTER_ENABLE)
3088                         return -EINVAL;
3089
3090                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3091                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3092
3093                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3094                 if (filter->hig_pri)
3095                         rfctl |= E1000_RFCTL_SYNQFP;
3096                 else
3097                         rfctl &= ~E1000_RFCTL_SYNQFP;
3098
3099                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3100         } else {
3101                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3102                         return -ENOENT;
3103                 synqf = 0;
3104         }
3105
3106         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3107         E1000_WRITE_FLUSH(hw);
3108         return 0;
3109 }
3110
3111 static int
3112 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3113                         struct rte_eth_syn_filter *filter)
3114 {
3115         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3116         uint32_t synqf, rfctl;
3117
3118         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3119         if (synqf & E1000_SYN_FILTER_ENABLE) {
3120                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3121                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3122                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3123                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3124                 return 0;
3125         }
3126
3127         return -ENOENT;
3128 }
3129
3130 static int
3131 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3132                         enum rte_filter_op filter_op,
3133                         void *arg)
3134 {
3135         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3136         int ret;
3137
3138         MAC_TYPE_FILTER_SUP(hw->mac.type);
3139
3140         if (filter_op == RTE_ETH_FILTER_NOP)
3141                 return 0;
3142
3143         if (arg == NULL) {
3144                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3145                             filter_op);
3146                 return -EINVAL;
3147         }
3148
3149         switch (filter_op) {
3150         case RTE_ETH_FILTER_ADD:
3151                 ret = eth_igb_syn_filter_set(dev,
3152                                 (struct rte_eth_syn_filter *)arg,
3153                                 TRUE);
3154                 break;
3155         case RTE_ETH_FILTER_DELETE:
3156                 ret = eth_igb_syn_filter_set(dev,
3157                                 (struct rte_eth_syn_filter *)arg,
3158                                 FALSE);
3159                 break;
3160         case RTE_ETH_FILTER_GET:
3161                 ret = eth_igb_syn_filter_get(dev,
3162                                 (struct rte_eth_syn_filter *)arg);
3163                 break;
3164         default:
3165                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3166                 ret = -EINVAL;
3167                 break;
3168         }
3169
3170         return ret;
3171 }
3172
3173 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3174         if ((type) != e1000_82580 && (type) != e1000_i350)\
3175                 return -ENOSYS; \
3176 } while (0)
3177
3178 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3179 static inline int
3180 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3181                         struct e1000_2tuple_filter_info *filter_info)
3182 {
3183         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3184                 return -EINVAL;
3185         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3186                 return -EINVAL;  /* filter index is out of range. */
3187         if (filter->tcp_flags > TCP_FLAG_ALL)
3188                 return -EINVAL;  /* flags is invalid. */
3189
3190         switch (filter->dst_port_mask) {
3191         case UINT16_MAX:
3192                 filter_info->dst_port_mask = 0;
3193                 filter_info->dst_port = filter->dst_port;
3194                 break;
3195         case 0:
3196                 filter_info->dst_port_mask = 1;
3197                 break;
3198         default:
3199                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3200                 return -EINVAL;
3201         }
3202
3203         switch (filter->proto_mask) {
3204         case UINT8_MAX:
3205                 filter_info->proto_mask = 0;
3206                 filter_info->proto = filter->proto;
3207                 break;
3208         case 0:
3209                 filter_info->proto_mask = 1;
3210                 break;
3211         default:
3212                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3213                 return -EINVAL;
3214         }
3215
3216         filter_info->priority = (uint8_t)filter->priority;
3217         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3218                 filter_info->tcp_flags = filter->tcp_flags;
3219         else
3220                 filter_info->tcp_flags = 0;
3221
3222         return 0;
3223 }
3224
3225 static inline struct e1000_2tuple_filter *
3226 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3227                         struct e1000_2tuple_filter_info *key)
3228 {
3229         struct e1000_2tuple_filter *it;
3230
3231         TAILQ_FOREACH(it, filter_list, entries) {
3232                 if (memcmp(key, &it->filter_info,
3233                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3234                         return it;
3235                 }
3236         }
3237         return NULL;
3238 }
3239
3240 /*
3241  * igb_add_2tuple_filter - add a 2tuple filter
3242  *
3243  * @param
3244  * dev: Pointer to struct rte_eth_dev.
3245  * ntuple_filter: ponter to the filter that will be added.
3246  *
3247  * @return
3248  *    - On success, zero.
3249  *    - On failure, a negative value.
3250  */
3251 static int
3252 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3253                         struct rte_eth_ntuple_filter *ntuple_filter)
3254 {
3255         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3256         struct e1000_filter_info *filter_info =
3257                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3258         struct e1000_2tuple_filter *filter;
3259         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3260         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3261         int i, ret;
3262
3263         filter = rte_zmalloc("e1000_2tuple_filter",
3264                         sizeof(struct e1000_2tuple_filter), 0);
3265         if (filter == NULL)
3266                 return -ENOMEM;
3267
3268         ret = ntuple_filter_to_2tuple(ntuple_filter,
3269                                       &filter->filter_info);
3270         if (ret < 0) {
3271                 rte_free(filter);
3272                 return ret;
3273         }
3274         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3275                                          &filter->filter_info) != NULL) {
3276                 PMD_DRV_LOG(ERR, "filter exists.");
3277                 rte_free(filter);
3278                 return -EEXIST;
3279         }
3280         filter->queue = ntuple_filter->queue;
3281
3282         /*
3283          * look for an unused 2tuple filter index,
3284          * and insert the filter to list.
3285          */
3286         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3287                 if (!(filter_info->twotuple_mask & (1 << i))) {
3288                         filter_info->twotuple_mask |= 1 << i;
3289                         filter->index = i;
3290                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3291                                           filter,
3292                                           entries);
3293                         break;
3294                 }
3295         }
3296         if (i >= E1000_MAX_TTQF_FILTERS) {
3297                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3298                 rte_free(filter);
3299                 return -ENOSYS;
3300         }
3301
3302         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3303         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3304                 imir |= E1000_IMIR_PORT_BP;
3305         else
3306                 imir &= ~E1000_IMIR_PORT_BP;
3307
3308         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3309
3310         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3311         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3312         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3313         if (filter->filter_info.proto_mask == 0)
3314                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3315
3316         /* tcp flags bits setting. */
3317         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3318                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3319                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3320                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3321                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3322                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3323                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3324                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3325                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3326                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3327                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3328                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3329                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3330         } else
3331                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3332         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3333         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3334         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3335         return 0;
3336 }
3337
3338 /*
3339  * igb_remove_2tuple_filter - remove a 2tuple filter
3340  *
3341  * @param
3342  * dev: Pointer to struct rte_eth_dev.
3343  * ntuple_filter: ponter to the filter that will be removed.
3344  *
3345  * @return
3346  *    - On success, zero.
3347  *    - On failure, a negative value.
3348  */
3349 static int
3350 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3351                         struct rte_eth_ntuple_filter *ntuple_filter)
3352 {
3353         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3354         struct e1000_filter_info *filter_info =
3355                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3356         struct e1000_2tuple_filter_info filter_2tuple;
3357         struct e1000_2tuple_filter *filter;
3358         int ret;
3359
3360         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3361         ret = ntuple_filter_to_2tuple(ntuple_filter,
3362                                       &filter_2tuple);
3363         if (ret < 0)
3364                 return ret;
3365
3366         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3367                                          &filter_2tuple);
3368         if (filter == NULL) {
3369                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3370                 return -ENOENT;
3371         }
3372
3373         filter_info->twotuple_mask &= ~(1 << filter->index);
3374         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3375         rte_free(filter);
3376
3377         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3378         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3379         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3380         return 0;
3381 }
3382
3383 static inline struct e1000_flex_filter *
3384 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3385                         struct e1000_flex_filter_info *key)
3386 {
3387         struct e1000_flex_filter *it;
3388
3389         TAILQ_FOREACH(it, filter_list, entries) {
3390                 if (memcmp(key, &it->filter_info,
3391                         sizeof(struct e1000_flex_filter_info)) == 0)
3392                         return it;
3393         }
3394
3395         return NULL;
3396 }
3397
3398 static int
3399 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3400                         struct rte_eth_flex_filter *filter,
3401                         bool add)
3402 {
3403         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3404         struct e1000_filter_info *filter_info =
3405                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3406         struct e1000_flex_filter *flex_filter, *it;
3407         uint32_t wufc, queueing, mask;
3408         uint32_t reg_off;
3409         uint8_t shift, i, j = 0;
3410
3411         flex_filter = rte_zmalloc("e1000_flex_filter",
3412                         sizeof(struct e1000_flex_filter), 0);
3413         if (flex_filter == NULL)
3414                 return -ENOMEM;
3415
3416         flex_filter->filter_info.len = filter->len;
3417         flex_filter->filter_info.priority = filter->priority;
3418         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3419         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3420                 mask = 0;
3421                 /* reverse bits in flex filter's mask*/
3422                 for (shift = 0; shift < CHAR_BIT; shift++) {
3423                         if (filter->mask[i] & (0x01 << shift))
3424                                 mask |= (0x80 >> shift);
3425                 }
3426                 flex_filter->filter_info.mask[i] = mask;
3427         }
3428
3429         wufc = E1000_READ_REG(hw, E1000_WUFC);
3430         if (flex_filter->index < E1000_MAX_FHFT)
3431                 reg_off = E1000_FHFT(flex_filter->index);
3432         else
3433                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3434
3435         if (add) {
3436                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3437                                 &flex_filter->filter_info) != NULL) {
3438                         PMD_DRV_LOG(ERR, "filter exists.");
3439                         rte_free(flex_filter);
3440                         return -EEXIST;
3441                 }
3442                 flex_filter->queue = filter->queue;
3443                 /*
3444                  * look for an unused flex filter index
3445                  * and insert the filter into the list.
3446                  */
3447                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3448                         if (!(filter_info->flex_mask & (1 << i))) {
3449                                 filter_info->flex_mask |= 1 << i;
3450                                 flex_filter->index = i;
3451                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3452                                         flex_filter,
3453                                         entries);
3454                                 break;
3455                         }
3456                 }
3457                 if (i >= E1000_MAX_FLEX_FILTERS) {
3458                         PMD_DRV_LOG(ERR, "flex filters are full.");
3459                         rte_free(flex_filter);
3460                         return -ENOSYS;
3461                 }
3462
3463                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3464                                 (E1000_WUFC_FLX0 << flex_filter->index));
3465                 queueing = filter->len |
3466                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3467                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3468                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3469                                 queueing);
3470                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3471                         E1000_WRITE_REG(hw, reg_off,
3472                                         flex_filter->filter_info.dwords[j]);
3473                         reg_off += sizeof(uint32_t);
3474                         E1000_WRITE_REG(hw, reg_off,
3475                                         flex_filter->filter_info.dwords[++j]);
3476                         reg_off += sizeof(uint32_t);
3477                         E1000_WRITE_REG(hw, reg_off,
3478                                 (uint32_t)flex_filter->filter_info.mask[i]);
3479                         reg_off += sizeof(uint32_t) * 2;
3480                         ++j;
3481                 }
3482         } else {
3483                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3484                                 &flex_filter->filter_info);
3485                 if (it == NULL) {
3486                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3487                         rte_free(flex_filter);
3488                         return -ENOENT;
3489                 }
3490
3491                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3492                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3493                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3494                         (~(E1000_WUFC_FLX0 << it->index)));
3495
3496                 filter_info->flex_mask &= ~(1 << it->index);
3497                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3498                 rte_free(it);
3499                 rte_free(flex_filter);
3500         }
3501
3502         return 0;
3503 }
3504
3505 static int
3506 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3507                         struct rte_eth_flex_filter *filter)
3508 {
3509         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3510         struct e1000_filter_info *filter_info =
3511                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3512         struct e1000_flex_filter flex_filter, *it;
3513         uint32_t wufc, queueing, wufc_en = 0;
3514
3515         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3516         flex_filter.filter_info.len = filter->len;
3517         flex_filter.filter_info.priority = filter->priority;
3518         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3519         memcpy(flex_filter.filter_info.mask, filter->mask,
3520                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3521
3522         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3523                                 &flex_filter.filter_info);
3524         if (it == NULL) {
3525                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3526                 return -ENOENT;
3527         }
3528
3529         wufc = E1000_READ_REG(hw, E1000_WUFC);
3530         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3531
3532         if ((wufc & wufc_en) == wufc_en) {
3533                 uint32_t reg_off = 0;
3534                 if (it->index < E1000_MAX_FHFT)
3535                         reg_off = E1000_FHFT(it->index);
3536                 else
3537                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3538
3539                 queueing = E1000_READ_REG(hw,
3540                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3541                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3542                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3543                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3544                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3545                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3546                 return 0;
3547         }
3548         return -ENOENT;
3549 }
3550
3551 static int
3552 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3553                         enum rte_filter_op filter_op,
3554                         void *arg)
3555 {
3556         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3557         struct rte_eth_flex_filter *filter;
3558         int ret = 0;
3559
3560         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3561
3562         if (filter_op == RTE_ETH_FILTER_NOP)
3563                 return ret;
3564
3565         if (arg == NULL) {
3566                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3567                             filter_op);
3568                 return -EINVAL;
3569         }
3570
3571         filter = (struct rte_eth_flex_filter *)arg;
3572         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3573             || filter->len % sizeof(uint64_t) != 0) {
3574                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3575                 return -EINVAL;
3576         }
3577         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3578                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3579                 return -EINVAL;
3580         }
3581
3582         switch (filter_op) {
3583         case RTE_ETH_FILTER_ADD:
3584                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3585                 break;
3586         case RTE_ETH_FILTER_DELETE:
3587                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3588                 break;
3589         case RTE_ETH_FILTER_GET:
3590                 ret = eth_igb_get_flex_filter(dev, filter);
3591                 break;
3592         default:
3593                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3594                 ret = -EINVAL;
3595                 break;
3596         }
3597
3598         return ret;
3599 }
3600
3601 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3602 static inline int
3603 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3604                         struct e1000_5tuple_filter_info *filter_info)
3605 {
3606         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3607                 return -EINVAL;
3608         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3609                 return -EINVAL;  /* filter index is out of range. */
3610         if (filter->tcp_flags > TCP_FLAG_ALL)
3611                 return -EINVAL;  /* flags is invalid. */
3612
3613         switch (filter->dst_ip_mask) {
3614         case UINT32_MAX:
3615                 filter_info->dst_ip_mask = 0;
3616                 filter_info->dst_ip = filter->dst_ip;
3617                 break;
3618         case 0:
3619                 filter_info->dst_ip_mask = 1;
3620                 break;
3621         default:
3622                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3623                 return -EINVAL;
3624         }
3625
3626         switch (filter->src_ip_mask) {
3627         case UINT32_MAX:
3628                 filter_info->src_ip_mask = 0;
3629                 filter_info->src_ip = filter->src_ip;
3630                 break;
3631         case 0:
3632                 filter_info->src_ip_mask = 1;
3633                 break;
3634         default:
3635                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3636                 return -EINVAL;
3637         }
3638
3639         switch (filter->dst_port_mask) {
3640         case UINT16_MAX:
3641                 filter_info->dst_port_mask = 0;
3642                 filter_info->dst_port = filter->dst_port;
3643                 break;
3644         case 0:
3645                 filter_info->dst_port_mask = 1;
3646                 break;
3647         default:
3648                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3649                 return -EINVAL;
3650         }
3651
3652         switch (filter->src_port_mask) {
3653         case UINT16_MAX:
3654                 filter_info->src_port_mask = 0;
3655                 filter_info->src_port = filter->src_port;
3656                 break;
3657         case 0:
3658                 filter_info->src_port_mask = 1;
3659                 break;
3660         default:
3661                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3662                 return -EINVAL;
3663         }
3664
3665         switch (filter->proto_mask) {
3666         case UINT8_MAX:
3667                 filter_info->proto_mask = 0;
3668                 filter_info->proto = filter->proto;
3669                 break;
3670         case 0:
3671                 filter_info->proto_mask = 1;
3672                 break;
3673         default:
3674                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3675                 return -EINVAL;
3676         }
3677
3678         filter_info->priority = (uint8_t)filter->priority;
3679         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3680                 filter_info->tcp_flags = filter->tcp_flags;
3681         else
3682                 filter_info->tcp_flags = 0;
3683
3684         return 0;
3685 }
3686
3687 static inline struct e1000_5tuple_filter *
3688 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3689                         struct e1000_5tuple_filter_info *key)
3690 {
3691         struct e1000_5tuple_filter *it;
3692
3693         TAILQ_FOREACH(it, filter_list, entries) {
3694                 if (memcmp(key, &it->filter_info,
3695                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3696                         return it;
3697                 }
3698         }
3699         return NULL;
3700 }
3701
3702 /*
3703  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3704  *
3705  * @param
3706  * dev: Pointer to struct rte_eth_dev.
3707  * ntuple_filter: ponter to the filter that will be added.
3708  *
3709  * @return
3710  *    - On success, zero.
3711  *    - On failure, a negative value.
3712  */
3713 static int
3714 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3715                         struct rte_eth_ntuple_filter *ntuple_filter)
3716 {
3717         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3718         struct e1000_filter_info *filter_info =
3719                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3720         struct e1000_5tuple_filter *filter;
3721         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3722         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3723         uint8_t i;
3724         int ret;
3725
3726         filter = rte_zmalloc("e1000_5tuple_filter",
3727                         sizeof(struct e1000_5tuple_filter), 0);
3728         if (filter == NULL)
3729                 return -ENOMEM;
3730
3731         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3732                                             &filter->filter_info);
3733         if (ret < 0) {
3734                 rte_free(filter);
3735                 return ret;
3736         }
3737
3738         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3739                                          &filter->filter_info) != NULL) {
3740                 PMD_DRV_LOG(ERR, "filter exists.");
3741                 rte_free(filter);
3742                 return -EEXIST;
3743         }
3744         filter->queue = ntuple_filter->queue;
3745
3746         /*
3747          * look for an unused 5tuple filter index,
3748          * and insert the filter to list.
3749          */
3750         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3751                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3752                         filter_info->fivetuple_mask |= 1 << i;
3753                         filter->index = i;
3754                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3755                                           filter,
3756                                           entries);
3757                         break;
3758                 }
3759         }
3760         if (i >= E1000_MAX_FTQF_FILTERS) {
3761                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3762                 rte_free(filter);
3763                 return -ENOSYS;
3764         }
3765
3766         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3767         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3768                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3769         if (filter->filter_info.dst_ip_mask == 0)
3770                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3771         if (filter->filter_info.src_port_mask == 0)
3772                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3773         if (filter->filter_info.proto_mask == 0)
3774                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3775         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3776                 E1000_FTQF_QUEUE_MASK;
3777         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3778         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3779         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3780         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3781
3782         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3783         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3784
3785         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3786         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3787                 imir |= E1000_IMIR_PORT_BP;
3788         else
3789                 imir &= ~E1000_IMIR_PORT_BP;
3790         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3791
3792         /* tcp flags bits setting. */
3793         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3794                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3795                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3796                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3797                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3798                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3799                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3800                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3801                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3802                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3803                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3804                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3805                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3806         } else
3807                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3808         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3809         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3810         return 0;
3811 }
3812
3813 /*
3814  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3815  *
3816  * @param
3817  * dev: Pointer to struct rte_eth_dev.
3818  * ntuple_filter: ponter to the filter that will be removed.
3819  *
3820  * @return
3821  *    - On success, zero.
3822  *    - On failure, a negative value.
3823  */
3824 static int
3825 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3826                                 struct rte_eth_ntuple_filter *ntuple_filter)
3827 {
3828         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3829         struct e1000_filter_info *filter_info =
3830                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3831         struct e1000_5tuple_filter_info filter_5tuple;
3832         struct e1000_5tuple_filter *filter;
3833         int ret;
3834
3835         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3836         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3837                                             &filter_5tuple);
3838         if (ret < 0)
3839                 return ret;
3840
3841         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3842                                          &filter_5tuple);
3843         if (filter == NULL) {
3844                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3845                 return -ENOENT;
3846         }
3847
3848         filter_info->fivetuple_mask &= ~(1 << filter->index);
3849         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3850         rte_free(filter);
3851
3852         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3853                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3854         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3855         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3856         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3857         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3858         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3859         return 0;
3860 }
3861
3862 static int
3863 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3864 {
3865         uint32_t rctl;
3866         struct e1000_hw *hw;
3867         struct rte_eth_dev_info dev_info;
3868         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3869                                      VLAN_TAG_SIZE);
3870
3871         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3872
3873 #ifdef RTE_LIBRTE_82571_SUPPORT
3874         /* XXX: not bigger than max_rx_pktlen */
3875         if (hw->mac.type == e1000_82571)
3876                 return -ENOTSUP;
3877 #endif
3878         eth_igb_infos_get(dev, &dev_info);
3879
3880         /* check that mtu is within the allowed range */
3881         if ((mtu < ETHER_MIN_MTU) ||
3882             (frame_size > dev_info.max_rx_pktlen))
3883                 return -EINVAL;
3884
3885         /* refuse mtu that requires the support of scattered packets when this
3886          * feature has not been enabled before. */
3887         if (!dev->data->scattered_rx &&
3888             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3889                 return -EINVAL;
3890
3891         rctl = E1000_READ_REG(hw, E1000_RCTL);
3892
3893         /* switch to jumbo mode if needed */
3894         if (frame_size > ETHER_MAX_LEN) {
3895                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3896                 rctl |= E1000_RCTL_LPE;
3897         } else {
3898                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3899                 rctl &= ~E1000_RCTL_LPE;
3900         }
3901         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3902
3903         /* update max frame size */
3904         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3905
3906         E1000_WRITE_REG(hw, E1000_RLPML,
3907                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3908
3909         return 0;
3910 }
3911
3912 /*
3913  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3914  *
3915  * @param
3916  * dev: Pointer to struct rte_eth_dev.
3917  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3918  * add: if true, add filter, if false, remove filter
3919  *
3920  * @return
3921  *    - On success, zero.
3922  *    - On failure, a negative value.
3923  */
3924 static int
3925 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3926                         struct rte_eth_ntuple_filter *ntuple_filter,
3927                         bool add)
3928 {
3929         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3930         int ret;
3931
3932         switch (ntuple_filter->flags) {
3933         case RTE_5TUPLE_FLAGS:
3934         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3935                 if (hw->mac.type != e1000_82576)
3936                         return -ENOTSUP;
3937                 if (add)
3938                         ret = igb_add_5tuple_filter_82576(dev,
3939                                                           ntuple_filter);
3940                 else
3941                         ret = igb_remove_5tuple_filter_82576(dev,
3942                                                              ntuple_filter);
3943                 break;
3944         case RTE_2TUPLE_FLAGS:
3945         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3946                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3947                         return -ENOTSUP;
3948                 if (add)
3949                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3950                 else
3951                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3952                 break;
3953         default:
3954                 ret = -EINVAL;
3955                 break;
3956         }
3957
3958         return ret;
3959 }
3960
3961 /*
3962  * igb_get_ntuple_filter - get a ntuple filter
3963  *
3964  * @param
3965  * dev: Pointer to struct rte_eth_dev.
3966  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3967  *
3968  * @return
3969  *    - On success, zero.
3970  *    - On failure, a negative value.
3971  */
3972 static int
3973 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3974                         struct rte_eth_ntuple_filter *ntuple_filter)
3975 {
3976         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3977         struct e1000_filter_info *filter_info =
3978                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3979         struct e1000_5tuple_filter_info filter_5tuple;
3980         struct e1000_2tuple_filter_info filter_2tuple;
3981         struct e1000_5tuple_filter *p_5tuple_filter;
3982         struct e1000_2tuple_filter *p_2tuple_filter;
3983         int ret;
3984
3985         switch (ntuple_filter->flags) {
3986         case RTE_5TUPLE_FLAGS:
3987         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3988                 if (hw->mac.type != e1000_82576)
3989                         return -ENOTSUP;
3990                 memset(&filter_5tuple,
3991                         0,
3992                         sizeof(struct e1000_5tuple_filter_info));
3993                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3994                                                     &filter_5tuple);
3995                 if (ret < 0)
3996                         return ret;
3997                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3998                                         &filter_info->fivetuple_list,
3999                                         &filter_5tuple);
4000                 if (p_5tuple_filter == NULL) {
4001                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4002                         return -ENOENT;
4003                 }
4004                 ntuple_filter->queue = p_5tuple_filter->queue;
4005                 break;
4006         case RTE_2TUPLE_FLAGS:
4007         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4008                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4009                         return -ENOTSUP;
4010                 memset(&filter_2tuple,
4011                         0,
4012                         sizeof(struct e1000_2tuple_filter_info));
4013                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4014                 if (ret < 0)
4015                         return ret;
4016                 p_2tuple_filter = igb_2tuple_filter_lookup(
4017                                         &filter_info->twotuple_list,
4018                                         &filter_2tuple);
4019                 if (p_2tuple_filter == NULL) {
4020                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4021                         return -ENOENT;
4022                 }
4023                 ntuple_filter->queue = p_2tuple_filter->queue;
4024                 break;
4025         default:
4026                 ret = -EINVAL;
4027                 break;
4028         }
4029
4030         return 0;
4031 }
4032
4033 /*
4034  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4035  * @dev: pointer to rte_eth_dev structure
4036  * @filter_op:operation will be taken.
4037  * @arg: a pointer to specific structure corresponding to the filter_op
4038  */
4039 static int
4040 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4041                                 enum rte_filter_op filter_op,
4042                                 void *arg)
4043 {
4044         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4045         int ret;
4046
4047         MAC_TYPE_FILTER_SUP(hw->mac.type);
4048
4049         if (filter_op == RTE_ETH_FILTER_NOP)
4050                 return 0;
4051
4052         if (arg == NULL) {
4053                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4054                             filter_op);
4055                 return -EINVAL;
4056         }
4057
4058         switch (filter_op) {
4059         case RTE_ETH_FILTER_ADD:
4060                 ret = igb_add_del_ntuple_filter(dev,
4061                         (struct rte_eth_ntuple_filter *)arg,
4062                         TRUE);
4063                 break;
4064         case RTE_ETH_FILTER_DELETE:
4065                 ret = igb_add_del_ntuple_filter(dev,
4066                         (struct rte_eth_ntuple_filter *)arg,
4067                         FALSE);
4068                 break;
4069         case RTE_ETH_FILTER_GET:
4070                 ret = igb_get_ntuple_filter(dev,
4071                         (struct rte_eth_ntuple_filter *)arg);
4072                 break;
4073         default:
4074                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4075                 ret = -EINVAL;
4076                 break;
4077         }
4078         return ret;
4079 }
4080
4081 static inline int
4082 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4083                         uint16_t ethertype)
4084 {
4085         int i;
4086
4087         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4088                 if (filter_info->ethertype_filters[i] == ethertype &&
4089                     (filter_info->ethertype_mask & (1 << i)))
4090                         return i;
4091         }
4092         return -1;
4093 }
4094
4095 static inline int
4096 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4097                         uint16_t ethertype)
4098 {
4099         int i;
4100
4101         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4102                 if (!(filter_info->ethertype_mask & (1 << i))) {
4103                         filter_info->ethertype_mask |= 1 << i;
4104                         filter_info->ethertype_filters[i] = ethertype;
4105                         return i;
4106                 }
4107         }
4108         return -1;
4109 }
4110
4111 static inline int
4112 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4113                         uint8_t idx)
4114 {
4115         if (idx >= E1000_MAX_ETQF_FILTERS)
4116                 return -1;
4117         filter_info->ethertype_mask &= ~(1 << idx);
4118         filter_info->ethertype_filters[idx] = 0;
4119         return idx;
4120 }
4121
4122
4123 static int
4124 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4125                         struct rte_eth_ethertype_filter *filter,
4126                         bool add)
4127 {
4128         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4129         struct e1000_filter_info *filter_info =
4130                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4131         uint32_t etqf = 0;
4132         int ret;
4133
4134         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4135                 filter->ether_type == ETHER_TYPE_IPv6) {
4136                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4137                         " ethertype filter.", filter->ether_type);
4138                 return -EINVAL;
4139         }
4140
4141         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4142                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4143                 return -EINVAL;
4144         }
4145         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4146                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4147                 return -EINVAL;
4148         }
4149
4150         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4151         if (ret >= 0 && add) {
4152                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4153                             filter->ether_type);
4154                 return -EEXIST;
4155         }
4156         if (ret < 0 && !add) {
4157                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4158                             filter->ether_type);
4159                 return -ENOENT;
4160         }
4161
4162         if (add) {
4163                 ret = igb_ethertype_filter_insert(filter_info,
4164                         filter->ether_type);
4165                 if (ret < 0) {
4166                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4167                         return -ENOSYS;
4168                 }
4169
4170                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4171                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4172                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4173         } else {
4174                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4175                 if (ret < 0)
4176                         return -ENOSYS;
4177         }
4178         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4179         E1000_WRITE_FLUSH(hw);
4180
4181         return 0;
4182 }
4183
4184 static int
4185 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4186                         struct rte_eth_ethertype_filter *filter)
4187 {
4188         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4189         struct e1000_filter_info *filter_info =
4190                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4191         uint32_t etqf;
4192         int ret;
4193
4194         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4195         if (ret < 0) {
4196                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4197                             filter->ether_type);
4198                 return -ENOENT;
4199         }
4200
4201         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4202         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4203                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4204                 filter->flags = 0;
4205                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4206                                 E1000_ETQF_QUEUE_SHIFT;
4207                 return 0;
4208         }
4209
4210         return -ENOENT;
4211 }
4212
4213 /*
4214  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4215  * @dev: pointer to rte_eth_dev structure
4216  * @filter_op:operation will be taken.
4217  * @arg: a pointer to specific structure corresponding to the filter_op
4218  */
4219 static int
4220 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4221                                 enum rte_filter_op filter_op,
4222                                 void *arg)
4223 {
4224         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4225         int ret;
4226
4227         MAC_TYPE_FILTER_SUP(hw->mac.type);
4228
4229         if (filter_op == RTE_ETH_FILTER_NOP)
4230                 return 0;
4231
4232         if (arg == NULL) {
4233                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4234                             filter_op);
4235                 return -EINVAL;
4236         }
4237
4238         switch (filter_op) {
4239         case RTE_ETH_FILTER_ADD:
4240                 ret = igb_add_del_ethertype_filter(dev,
4241                         (struct rte_eth_ethertype_filter *)arg,
4242                         TRUE);
4243                 break;
4244         case RTE_ETH_FILTER_DELETE:
4245                 ret = igb_add_del_ethertype_filter(dev,
4246                         (struct rte_eth_ethertype_filter *)arg,
4247                         FALSE);
4248                 break;
4249         case RTE_ETH_FILTER_GET:
4250                 ret = igb_get_ethertype_filter(dev,
4251                         (struct rte_eth_ethertype_filter *)arg);
4252                 break;
4253         default:
4254                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4255                 ret = -EINVAL;
4256                 break;
4257         }
4258         return ret;
4259 }
4260
4261 static int
4262 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4263                      enum rte_filter_type filter_type,
4264                      enum rte_filter_op filter_op,
4265                      void *arg)
4266 {
4267         int ret = -EINVAL;
4268
4269         switch (filter_type) {
4270         case RTE_ETH_FILTER_NTUPLE:
4271                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4272                 break;
4273         case RTE_ETH_FILTER_ETHERTYPE:
4274                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4275                 break;
4276         case RTE_ETH_FILTER_SYN:
4277                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4278                 break;
4279         case RTE_ETH_FILTER_FLEXIBLE:
4280                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4281                 break;
4282         default:
4283                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4284                                                         filter_type);
4285                 break;
4286         }
4287
4288         return ret;
4289 }
4290
4291 static int
4292 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4293                          struct ether_addr *mc_addr_set,
4294                          uint32_t nb_mc_addr)
4295 {
4296         struct e1000_hw *hw;
4297
4298         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4299         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4300         return 0;
4301 }
4302
4303 static uint64_t
4304 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4305 {
4306         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4307         uint64_t systime_cycles;
4308
4309         switch (hw->mac.type) {
4310         case e1000_i210:
4311         case e1000_i211:
4312                 /*
4313                  * Need to read System Time Residue Register to be able
4314                  * to read the other two registers.
4315                  */
4316                 E1000_READ_REG(hw, E1000_SYSTIMR);
4317                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4318                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4319                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4320                                 * NSEC_PER_SEC;
4321                 break;
4322         case e1000_82580:
4323         case e1000_i350:
4324         case e1000_i354:
4325                 /*
4326                  * Need to read System Time Residue Register to be able
4327                  * to read the other two registers.
4328                  */
4329                 E1000_READ_REG(hw, E1000_SYSTIMR);
4330                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4331                 /* Only the 8 LSB are valid. */
4332                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4333                                 & 0xff) << 32;
4334                 break;
4335         default:
4336                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4337                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4338                                 << 32;
4339                 break;
4340         }
4341
4342         return systime_cycles;
4343 }
4344
4345 static uint64_t
4346 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4347 {
4348         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4349         uint64_t rx_tstamp_cycles;
4350
4351         switch (hw->mac.type) {
4352         case e1000_i210:
4353         case e1000_i211:
4354                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4355                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4356                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4357                                 * NSEC_PER_SEC;
4358                 break;
4359         case e1000_82580:
4360         case e1000_i350:
4361         case e1000_i354:
4362                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4363                 /* Only the 8 LSB are valid. */
4364                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4365                                 & 0xff) << 32;
4366                 break;
4367         default:
4368                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4369                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4370                                 << 32;
4371                 break;
4372         }
4373
4374         return rx_tstamp_cycles;
4375 }
4376
4377 static uint64_t
4378 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4379 {
4380         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4381         uint64_t tx_tstamp_cycles;
4382
4383         switch (hw->mac.type) {
4384         case e1000_i210:
4385         case e1000_i211:
4386                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4387                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4388                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4389                                 * NSEC_PER_SEC;
4390                 break;
4391         case e1000_82580:
4392         case e1000_i350:
4393         case e1000_i354:
4394                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4395                 /* Only the 8 LSB are valid. */
4396                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4397                                 & 0xff) << 32;
4398                 break;
4399         default:
4400                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4401                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4402                                 << 32;
4403                 break;
4404         }
4405
4406         return tx_tstamp_cycles;
4407 }
4408
4409 static void
4410 igb_start_timecounters(struct rte_eth_dev *dev)
4411 {
4412         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4413         struct e1000_adapter *adapter =
4414                 (struct e1000_adapter *)dev->data->dev_private;
4415         uint32_t incval = 1;
4416         uint32_t shift = 0;
4417         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4418
4419         switch (hw->mac.type) {
4420         case e1000_82580:
4421         case e1000_i350:
4422         case e1000_i354:
4423                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4424                 mask = (1ULL << 40) - 1;
4425                 /* fall-through */
4426         case e1000_i210:
4427         case e1000_i211:
4428                 /*
4429                  * Start incrementing the register
4430                  * used to timestamp PTP packets.
4431                  */
4432                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4433                 break;
4434         case e1000_82576:
4435                 incval = E1000_INCVALUE_82576;
4436                 shift = IGB_82576_TSYNC_SHIFT;
4437                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4438                                 E1000_INCPERIOD_82576 | incval);
4439                 break;
4440         default:
4441                 /* Not supported */
4442                 return;
4443         }
4444
4445         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4446         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4447         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4448
4449         adapter->systime_tc.cc_mask = mask;
4450         adapter->systime_tc.cc_shift = shift;
4451         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4452
4453         adapter->rx_tstamp_tc.cc_mask = mask;
4454         adapter->rx_tstamp_tc.cc_shift = shift;
4455         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4456
4457         adapter->tx_tstamp_tc.cc_mask = mask;
4458         adapter->tx_tstamp_tc.cc_shift = shift;
4459         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4460 }
4461
4462 static int
4463 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4464 {
4465         struct e1000_adapter *adapter =
4466                         (struct e1000_adapter *)dev->data->dev_private;
4467
4468         adapter->systime_tc.nsec += delta;
4469         adapter->rx_tstamp_tc.nsec += delta;
4470         adapter->tx_tstamp_tc.nsec += delta;
4471
4472         return 0;
4473 }
4474
4475 static int
4476 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4477 {
4478         uint64_t ns;
4479         struct e1000_adapter *adapter =
4480                         (struct e1000_adapter *)dev->data->dev_private;
4481
4482         ns = rte_timespec_to_ns(ts);
4483
4484         /* Set the timecounters to a new value. */
4485         adapter->systime_tc.nsec = ns;
4486         adapter->rx_tstamp_tc.nsec = ns;
4487         adapter->tx_tstamp_tc.nsec = ns;
4488
4489         return 0;
4490 }
4491
4492 static int
4493 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4494 {
4495         uint64_t ns, systime_cycles;
4496         struct e1000_adapter *adapter =
4497                         (struct e1000_adapter *)dev->data->dev_private;
4498
4499         systime_cycles = igb_read_systime_cyclecounter(dev);
4500         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4501         *ts = rte_ns_to_timespec(ns);
4502
4503         return 0;
4504 }
4505
4506 static int
4507 igb_timesync_enable(struct rte_eth_dev *dev)
4508 {
4509         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4510         uint32_t tsync_ctl;
4511         uint32_t tsauxc;
4512
4513         /* Stop the timesync system time. */
4514         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4515         /* Reset the timesync system time value. */
4516         switch (hw->mac.type) {
4517         case e1000_82580:
4518         case e1000_i350:
4519         case e1000_i354:
4520         case e1000_i210:
4521         case e1000_i211:
4522                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4523                 /* fall-through */
4524         case e1000_82576:
4525                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4526                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4527                 break;
4528         default:
4529                 /* Not supported. */
4530                 return -ENOTSUP;
4531         }
4532
4533         /* Enable system time for it isn't on by default. */
4534         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4535         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4536         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4537
4538         igb_start_timecounters(dev);
4539
4540         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4541         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4542                         (ETHER_TYPE_1588 |
4543                          E1000_ETQF_FILTER_ENABLE |
4544                          E1000_ETQF_1588));
4545
4546         /* Enable timestamping of received PTP packets. */
4547         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4548         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4549         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4550
4551         /* Enable Timestamping of transmitted PTP packets. */
4552         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4553         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4554         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4555
4556         return 0;
4557 }
4558
4559 static int
4560 igb_timesync_disable(struct rte_eth_dev *dev)
4561 {
4562         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4563         uint32_t tsync_ctl;
4564
4565         /* Disable timestamping of transmitted PTP packets. */
4566         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4567         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4568         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4569
4570         /* Disable timestamping of received PTP packets. */
4571         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4572         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4573         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4574
4575         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4576         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4577
4578         /* Stop incrementating the System Time registers. */
4579         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4580
4581         return 0;
4582 }
4583
4584 static int
4585 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4586                                struct timespec *timestamp,
4587                                uint32_t flags __rte_unused)
4588 {
4589         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4590         struct e1000_adapter *adapter =
4591                         (struct e1000_adapter *)dev->data->dev_private;
4592         uint32_t tsync_rxctl;
4593         uint64_t rx_tstamp_cycles;
4594         uint64_t ns;
4595
4596         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4597         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4598                 return -EINVAL;
4599
4600         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4601         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4602         *timestamp = rte_ns_to_timespec(ns);
4603
4604         return  0;
4605 }
4606
4607 static int
4608 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4609                                struct timespec *timestamp)
4610 {
4611         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4612         struct e1000_adapter *adapter =
4613                         (struct e1000_adapter *)dev->data->dev_private;
4614         uint32_t tsync_txctl;
4615         uint64_t tx_tstamp_cycles;
4616         uint64_t ns;
4617
4618         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4619         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4620                 return -EINVAL;
4621
4622         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4623         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4624         *timestamp = rte_ns_to_timespec(ns);
4625
4626         return  0;
4627 }
4628
4629 static int
4630 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4631 {
4632         int count = 0;
4633         int g_ind = 0;
4634         const struct reg_info *reg_group;
4635
4636         while ((reg_group = igb_regs[g_ind++]))
4637                 count += igb_reg_group_count(reg_group);
4638
4639         return count;
4640 }
4641
4642 static int
4643 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4644 {
4645         int count = 0;
4646         int g_ind = 0;
4647         const struct reg_info *reg_group;
4648
4649         while ((reg_group = igbvf_regs[g_ind++]))
4650                 count += igb_reg_group_count(reg_group);
4651
4652         return count;
4653 }
4654
4655 static int
4656 eth_igb_get_regs(struct rte_eth_dev *dev,
4657         struct rte_dev_reg_info *regs)
4658 {
4659         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4660         uint32_t *data = regs->data;
4661         int g_ind = 0;
4662         int count = 0;
4663         const struct reg_info *reg_group;
4664
4665         /* Support only full register dump */
4666         if ((regs->length == 0) ||
4667             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4668                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4669                         hw->device_id;
4670                 while ((reg_group = igb_regs[g_ind++]))
4671                         count += igb_read_regs_group(dev, &data[count],
4672                                                         reg_group);
4673                 return 0;
4674         }
4675
4676         return -ENOTSUP;
4677 }
4678
4679 static int
4680 igbvf_get_regs(struct rte_eth_dev *dev,
4681         struct rte_dev_reg_info *regs)
4682 {
4683         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4684         uint32_t *data = regs->data;
4685         int g_ind = 0;
4686         int count = 0;
4687         const struct reg_info *reg_group;
4688
4689         /* Support only full register dump */
4690         if ((regs->length == 0) ||
4691             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4692                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4693                         hw->device_id;
4694                 while ((reg_group = igbvf_regs[g_ind++]))
4695                         count += igb_read_regs_group(dev, &data[count],
4696                                                         reg_group);
4697                 return 0;
4698         }
4699
4700         return -ENOTSUP;
4701 }
4702
4703 static int
4704 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4705 {
4706         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4707
4708         /* Return unit is byte count */
4709         return hw->nvm.word_size * 2;
4710 }
4711
4712 static int
4713 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4714         struct rte_dev_eeprom_info *in_eeprom)
4715 {
4716         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4717         struct e1000_nvm_info *nvm = &hw->nvm;
4718         uint16_t *data = in_eeprom->data;
4719         int first, length;
4720
4721         first = in_eeprom->offset >> 1;
4722         length = in_eeprom->length >> 1;
4723         if ((first >= hw->nvm.word_size) ||
4724             ((first + length) >= hw->nvm.word_size))
4725                 return -EINVAL;
4726
4727         in_eeprom->magic = hw->vendor_id |
4728                 ((uint32_t)hw->device_id << 16);
4729
4730         if ((nvm->ops.read) == NULL)
4731                 return -ENOTSUP;
4732
4733         return nvm->ops.read(hw, first, length, data);
4734 }
4735
4736 static int
4737 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4738         struct rte_dev_eeprom_info *in_eeprom)
4739 {
4740         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4741         struct e1000_nvm_info *nvm = &hw->nvm;
4742         uint16_t *data = in_eeprom->data;
4743         int first, length;
4744
4745         first = in_eeprom->offset >> 1;
4746         length = in_eeprom->length >> 1;
4747         if ((first >= hw->nvm.word_size) ||
4748             ((first + length) >= hw->nvm.word_size))
4749                 return -EINVAL;
4750
4751         in_eeprom->magic = (uint32_t)hw->vendor_id |
4752                 ((uint32_t)hw->device_id << 16);
4753
4754         if ((nvm->ops.write) == NULL)
4755                 return -ENOTSUP;
4756         return nvm->ops.write(hw,  first, length, data);
4757 }
4758
4759 static struct rte_driver pmd_igb_drv = {
4760         .type = PMD_PDEV,
4761         .init = rte_igb_pmd_init,
4762 };
4763
4764 static struct rte_driver pmd_igbvf_drv = {
4765         .type = PMD_PDEV,
4766         .init = rte_igbvf_pmd_init,
4767 };
4768
4769 static int
4770 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4771 {
4772         struct e1000_hw *hw =
4773                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4774         uint32_t mask = 1 << queue_id;
4775
4776         E1000_WRITE_REG(hw, E1000_EIMC, mask);
4777         E1000_WRITE_FLUSH(hw);
4778
4779         return 0;
4780 }
4781
4782 static int
4783 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4784 {
4785         struct e1000_hw *hw =
4786                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4787         uint32_t mask = 1 << queue_id;
4788         uint32_t regval;
4789
4790         regval = E1000_READ_REG(hw, E1000_EIMS);
4791         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4792         E1000_WRITE_FLUSH(hw);
4793
4794         rte_intr_enable(&dev->pci_dev->intr_handle);
4795
4796         return 0;
4797 }
4798
4799 static void
4800 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
4801                    uint8_t index, uint8_t offset)
4802 {
4803         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4804
4805         /* clear bits */
4806         val &= ~((uint32_t)0xFF << offset);
4807
4808         /* write vector and valid bit */
4809         val |= (msix_vector | E1000_IVAR_VALID) << offset;
4810
4811         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4812 }
4813
4814 static void
4815 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4816                            uint8_t queue, uint8_t msix_vector)
4817 {
4818         uint32_t tmp = 0;
4819
4820         if (hw->mac.type == e1000_82575) {
4821                 if (direction == 0)
4822                         tmp = E1000_EICR_RX_QUEUE0 << queue;
4823                 else if (direction == 1)
4824                         tmp = E1000_EICR_TX_QUEUE0 << queue;
4825                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4826         } else if (hw->mac.type == e1000_82576) {
4827                 if ((direction == 0) || (direction == 1))
4828                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4829                                            ((queue & 0x8) << 1) +
4830                                            8 * direction);
4831         } else if ((hw->mac.type == e1000_82580) ||
4832                         (hw->mac.type == e1000_i350) ||
4833                         (hw->mac.type == e1000_i354) ||
4834                         (hw->mac.type == e1000_i210) ||
4835                         (hw->mac.type == e1000_i211)) {
4836                 if ((direction == 0) || (direction == 1))
4837                         eth_igb_write_ivar(hw, msix_vector,
4838                                            queue >> 1,
4839                                            ((queue & 0x1) << 4) +
4840                                            8 * direction);
4841         }
4842 }
4843
4844 /* Sets up the hardware to generate MSI-X interrupts properly
4845  * @hw
4846  *  board private structure
4847  */
4848 static void
4849 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4850 {
4851         int queue_id;
4852         uint32_t tmpval, regval, intr_mask;
4853         struct e1000_hw *hw =
4854                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4855         uint32_t vec = E1000_MISC_VEC_ID;
4856         uint32_t base = E1000_MISC_VEC_ID;
4857         uint32_t misc_shift = 0;
4858
4859         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4860
4861         /* won't configure msix register if no mapping is done
4862          * between intr vector and event fd
4863          */
4864         if (!rte_intr_dp_is_en(intr_handle))
4865                 return;
4866
4867         if (rte_intr_allow_others(intr_handle)) {
4868                 vec = base = E1000_RX_VEC_START;
4869                 misc_shift = 1;
4870         }
4871
4872         /* set interrupt vector for other causes */
4873         if (hw->mac.type == e1000_82575) {
4874                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4875                 /* enable MSI-X PBA support */
4876                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4877
4878                 /* Auto-Mask interrupts upon ICR read */
4879                 tmpval |= E1000_CTRL_EXT_EIAME;
4880                 tmpval |= E1000_CTRL_EXT_IRCA;
4881
4882                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4883
4884                 /* enable msix_other interrupt */
4885                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4886                 regval = E1000_READ_REG(hw, E1000_EIAC);
4887                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4888                 regval = E1000_READ_REG(hw, E1000_EIAM);
4889                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4890         } else if ((hw->mac.type == e1000_82576) ||
4891                         (hw->mac.type == e1000_82580) ||
4892                         (hw->mac.type == e1000_i350) ||
4893                         (hw->mac.type == e1000_i354) ||
4894                         (hw->mac.type == e1000_i210) ||
4895                         (hw->mac.type == e1000_i211)) {
4896                 /* turn on MSI-X capability first */
4897                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4898                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
4899                                         E1000_GPIE_NSICR);
4900                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4901                         misc_shift;
4902                 regval = E1000_READ_REG(hw, E1000_EIAC);
4903                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4904
4905                 /* enable msix_other interrupt */
4906                 regval = E1000_READ_REG(hw, E1000_EIMS);
4907                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4908                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4909                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4910         }
4911
4912         /* use EIAM to auto-mask when MSI-X interrupt
4913          * is asserted, this saves a register write for every interrupt
4914          */
4915         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4916                 misc_shift;
4917         regval = E1000_READ_REG(hw, E1000_EIAM);
4918         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4919
4920         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4921                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4922                 intr_handle->intr_vec[queue_id] = vec;
4923                 if (vec < base + intr_handle->nb_efd - 1)
4924                         vec++;
4925         }
4926
4927         E1000_WRITE_FLUSH(hw);
4928 }
4929
4930 PMD_REGISTER_DRIVER(pmd_igb_drv);
4931 PMD_REGISTER_DRIVER(pmd_igbvf_drv);