drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_string_fns.h>
  12 #include <rte_common.h>
  13 #include <rte_interrupts.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_log.h>
  16 #include <rte_debug.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memory.h>
  23 #include <rte_eal.h>
  24 #include <rte_malloc.h>
  25 #include <rte_dev.h>
  26
  27 #include "e1000_logs.h"
  28 #include "base/e1000_api.h"
  29 #include "e1000_ethdev.h"
  30 #include "igb_regs.h"
  31
  32 /*
  33  * Default values for port configuration
  34  */
  35 #define IGB_DEFAULT_RX_FREE_THRESH  32
  36
  37 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  38 #define IGB_DEFAULT_RX_HTHRESH      8
  39 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  40
  41 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  42 #define IGB_DEFAULT_TX_HTHRESH      1
  43 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  44
  45 /* Bit shift and mask */
  46 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  47 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  48 #define IGB_8_BIT_WIDTH  CHAR_BIT
  49 #define IGB_8_BIT_MASK   UINT8_MAX
  50
  51 /* Additional timesync values. */
  52 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  53 #define E1000_ETQF_FILTER_1588       3
  54 #define IGB_82576_TSYNC_SHIFT        16
  55 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  56 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  58
  59 #define E1000_VTIVAR_MISC                0x01740
  60 #define E1000_VTIVAR_MISC_MASK           0xFF
  61 #define E1000_VTIVAR_VALID               0x80
  62 #define E1000_VTIVAR_MISC_MAILBOX        0
  63 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  64
  65 /* External VLAN Enable bit mask */
  66 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  67
  68 /* External VLAN Ether Type bit mask and shift */
  69 #define E1000_VET_VET_EXT            0xFFFF0000
  70 #define E1000_VET_VET_EXT_SHIFT      16
  71
  72 /* MSI-X other interrupt vector */
  73 #define IGB_MSIX_OTHER_INTR_VEC      0
  74
  75 static int  eth_igb_configure(struct rte_eth_dev *dev);
  76 static int  eth_igb_start(struct rte_eth_dev *dev);
  77 static void eth_igb_stop(struct rte_eth_dev *dev);
  78 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  79 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  80 static int eth_igb_close(struct rte_eth_dev *dev);
  81 static int eth_igb_reset(struct rte_eth_dev *dev);
  82 static int  eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  83 static int  eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  84 static int  eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  85 static int  eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  87                                 int wait_to_complete);
  88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  89                                 struct rte_eth_stats *rte_stats);
  90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  91                               struct rte_eth_xstat *xstats, unsigned n);
  92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  93                 const uint64_t *ids,
  94                 uint64_t *values, unsigned int n);
  95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  96                                     struct rte_eth_xstat_name *xstats_names,
  97                                     unsigned int size);
  98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  99                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 100                 unsigned int limit);
 101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
 102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
 103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 104                                    char *fw_version, size_t fw_size);
 105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
 106                               struct rte_eth_dev_info *dev_info);
 107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_dev_info *dev_info);
 110 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 113                                 struct rte_eth_fc_conf *fc_conf);
 114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 118                                     struct rte_intr_handle *handle);
 119 static void eth_igb_interrupt_handler(void *param);
 120 static int  igb_hardware_init(struct e1000_hw *hw);
 121 static void igb_hw_control_acquire(struct e1000_hw *hw);
 122 static void igb_hw_control_release(struct e1000_hw *hw);
 123 static void igb_init_manageability(struct e1000_hw *hw);
 124 static void igb_release_manageability(struct e1000_hw *hw);
 125
 126 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 127
 128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 129                 uint16_t vlan_id, int on);
 130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 131                                  enum rte_vlan_type vlan_type,
 132                                  uint16_t tpid_id);
 133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134
 135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 141
 142 static int eth_igb_led_on(struct rte_eth_dev *dev);
 143 static int eth_igb_led_off(struct rte_eth_dev *dev);
 144
 145 static void igb_intr_disable(struct rte_eth_dev *dev);
 146 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 148                            struct rte_ether_addr *mac_addr,
 149                            uint32_t index, uint32_t pool);
 150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 152                 struct rte_ether_addr *addr);
 153
 154 static void igbvf_intr_disable(struct e1000_hw *hw);
 155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 156 static int igbvf_dev_start(struct rte_eth_dev *dev);
 157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 158 static int igbvf_dev_close(struct rte_eth_dev *dev);
 159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 163 static int eth_igbvf_link_update(struct e1000_hw *hw);
 164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_stats *rte_stats);
 166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 167                                 struct rte_eth_xstat *xstats, unsigned n);
 168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 169                                       struct rte_eth_xstat_name *xstats_names,
 170                                       unsigned limit);
 171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 173                 uint16_t vlan_id, int on);
 174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 177                 struct rte_ether_addr *addr);
 178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 179 static int igbvf_get_regs(struct rte_eth_dev *dev,
 180                 struct rte_dev_reg_info *regs);
 181
 182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 183                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                    uint16_t reta_size);
 185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 186                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 187                                   uint16_t reta_size);
 188
 189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 190                         struct rte_eth_syn_filter *filter);
 191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 192                         enum rte_filter_op filter_op,
 193                         void *arg);
 194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_ntuple_filter *ntuple_filter);
 198 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 199                         struct rte_eth_flex_filter *filter);
 200 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 201                         enum rte_filter_op filter_op,
 202                         void *arg);
 203 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 204                         struct rte_eth_ntuple_filter *ntuple_filter);
 205 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 206                         struct rte_eth_ntuple_filter *ntuple_filter);
 207 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 208                         struct rte_eth_ntuple_filter *filter);
 209 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 213                                 enum rte_filter_op filter_op,
 214                                 void *arg);
 215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ethertype_filter *filter);
 217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 218                      enum rte_filter_type filter_type,
 219                      enum rte_filter_op filter_op,
 220                      void *arg);
 221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 223                 struct rte_dev_reg_info *regs);
 224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 226                 struct rte_dev_eeprom_info *eeprom);
 227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 228                 struct rte_dev_eeprom_info *eeprom);
 229 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
 230                                    struct rte_eth_dev_module_info *modinfo);
 231 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
 232                                      struct rte_dev_eeprom_info *info);
 233 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 234                                     struct rte_ether_addr *mc_addr_set,
 235                                     uint32_t nb_mc_addr);
 236 static int igb_timesync_enable(struct rte_eth_dev *dev);
 237 static int igb_timesync_disable(struct rte_eth_dev *dev);
 238 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 239                                           struct timespec *timestamp,
 240                                           uint32_t flags);
 241 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 242                                           struct timespec *timestamp);
 243 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 244 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 245                                   struct timespec *timestamp);
 246 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 247                                    const struct timespec *timestamp);
 248 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 249                                         uint16_t queue_id);
 250 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 251                                          uint16_t queue_id);
 252 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 253                                        uint8_t queue, uint8_t msix_vector);
 254 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 255                                uint8_t index, uint8_t offset);
 256 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 257 static void eth_igbvf_interrupt_handler(void *param);
 258 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 259 static int igb_filter_restore(struct rte_eth_dev *dev);
 260
 261 /*
 262  * Define VF Stats MACRO for Non "cleared on read" register
 263  */
 264 #define UPDATE_VF_STAT(reg, last, cur)            \
 265 {                                                 \
 266         u32 latest = E1000_READ_REG(hw, reg);     \
 267         cur += (latest - last) & UINT_MAX;        \
 268         last = latest;                            \
 269 }
 270
 271 #define IGB_FC_PAUSE_TIME 0x0680
 272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 274
 275 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 276
 277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 278
 279 /*
 280  * The set of PCI devices this driver supports
 281  */
 282 static const struct rte_pci_id pci_id_igb_map[] = {
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 284         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 285         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 286         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 287         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 288         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 289         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 290         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 291
 292         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 295
 296         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 297         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 302
 303         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 304         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 305         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 324         { .vendor_id = 0, /* sentinel */ },
 325 };
 326
 327 /*
 328  * The set of PCI devices this driver supports (for 82576&I350 VF)
 329  */
 330 static const struct rte_pci_id pci_id_igbvf_map[] = {
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 335         { .vendor_id = 0, /* sentinel */ },
 336 };
 337
 338 static const struct rte_eth_desc_lim rx_desc_lim = {
 339         .nb_max = E1000_MAX_RING_DESC,
 340         .nb_min = E1000_MIN_RING_DESC,
 341         .nb_align = IGB_RXD_ALIGN,
 342 };
 343
 344 static const struct rte_eth_desc_lim tx_desc_lim = {
 345         .nb_max = E1000_MAX_RING_DESC,
 346         .nb_min = E1000_MIN_RING_DESC,
 347         .nb_align = IGB_RXD_ALIGN,
 348         .nb_seg_max = IGB_TX_MAX_SEG,
 349         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 350 };
 351
 352 static const struct eth_dev_ops eth_igb_ops = {
 353         .dev_configure        = eth_igb_configure,
 354         .dev_start            = eth_igb_start,
 355         .dev_stop             = eth_igb_stop,
 356         .dev_set_link_up      = eth_igb_dev_set_link_up,
 357         .dev_set_link_down    = eth_igb_dev_set_link_down,
 358         .dev_close            = eth_igb_close,
 359         .dev_reset            = eth_igb_reset,
 360         .promiscuous_enable   = eth_igb_promiscuous_enable,
 361         .promiscuous_disable  = eth_igb_promiscuous_disable,
 362         .allmulticast_enable  = eth_igb_allmulticast_enable,
 363         .allmulticast_disable = eth_igb_allmulticast_disable,
 364         .link_update          = eth_igb_link_update,
 365         .stats_get            = eth_igb_stats_get,
 366         .xstats_get           = eth_igb_xstats_get,
 367         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 368         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 369         .xstats_get_names     = eth_igb_xstats_get_names,
 370         .stats_reset          = eth_igb_stats_reset,
 371         .xstats_reset         = eth_igb_xstats_reset,
 372         .fw_version_get       = eth_igb_fw_version_get,
 373         .dev_infos_get        = eth_igb_infos_get,
 374         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 375         .mtu_set              = eth_igb_mtu_set,
 376         .vlan_filter_set      = eth_igb_vlan_filter_set,
 377         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 378         .vlan_offload_set     = eth_igb_vlan_offload_set,
 379         .rx_queue_setup       = eth_igb_rx_queue_setup,
 380         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 381         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 382         .rx_queue_release     = eth_igb_rx_queue_release,
 383         .tx_queue_setup       = eth_igb_tx_queue_setup,
 384         .tx_queue_release     = eth_igb_tx_queue_release,
 385         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 386         .dev_led_on           = eth_igb_led_on,
 387         .dev_led_off          = eth_igb_led_off,
 388         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 389         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 390         .mac_addr_add         = eth_igb_rar_set,
 391         .mac_addr_remove      = eth_igb_rar_clear,
 392         .mac_addr_set         = eth_igb_default_mac_addr_set,
 393         .reta_update          = eth_igb_rss_reta_update,
 394         .reta_query           = eth_igb_rss_reta_query,
 395         .rss_hash_update      = eth_igb_rss_hash_update,
 396         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 397         .filter_ctrl          = eth_igb_filter_ctrl,
 398         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 399         .rxq_info_get         = igb_rxq_info_get,
 400         .txq_info_get         = igb_txq_info_get,
 401         .timesync_enable      = igb_timesync_enable,
 402         .timesync_disable     = igb_timesync_disable,
 403         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 404         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 405         .get_reg              = eth_igb_get_regs,
 406         .get_eeprom_length    = eth_igb_get_eeprom_length,
 407         .get_eeprom           = eth_igb_get_eeprom,
 408         .set_eeprom           = eth_igb_set_eeprom,
 409         .get_module_info      = eth_igb_get_module_info,
 410         .get_module_eeprom    = eth_igb_get_module_eeprom,
 411         .timesync_adjust_time = igb_timesync_adjust_time,
 412         .timesync_read_time   = igb_timesync_read_time,
 413         .timesync_write_time  = igb_timesync_write_time,
 414 };
 415
 416 /*
 417  * dev_ops for virtual function, bare necessities for basic vf
 418  * operation have been implemented
 419  */
 420 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 421         .dev_configure        = igbvf_dev_configure,
 422         .dev_start            = igbvf_dev_start,
 423         .dev_stop             = igbvf_dev_stop,
 424         .dev_close            = igbvf_dev_close,
 425         .promiscuous_enable   = igbvf_promiscuous_enable,
 426         .promiscuous_disable  = igbvf_promiscuous_disable,
 427         .allmulticast_enable  = igbvf_allmulticast_enable,
 428         .allmulticast_disable = igbvf_allmulticast_disable,
 429         .link_update          = eth_igb_link_update,
 430         .stats_get            = eth_igbvf_stats_get,
 431         .xstats_get           = eth_igbvf_xstats_get,
 432         .xstats_get_names     = eth_igbvf_xstats_get_names,
 433         .stats_reset          = eth_igbvf_stats_reset,
 434         .xstats_reset         = eth_igbvf_stats_reset,
 435         .vlan_filter_set      = igbvf_vlan_filter_set,
 436         .dev_infos_get        = eth_igbvf_infos_get,
 437         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 438         .rx_queue_setup       = eth_igb_rx_queue_setup,
 439         .rx_queue_release     = eth_igb_rx_queue_release,
 440         .tx_queue_setup       = eth_igb_tx_queue_setup,
 441         .tx_queue_release     = eth_igb_tx_queue_release,
 442         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 443         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 444         .rxq_info_get         = igb_rxq_info_get,
 445         .txq_info_get         = igb_txq_info_get,
 446         .mac_addr_set         = igbvf_default_mac_addr_set,
 447         .get_reg              = igbvf_get_regs,
 448 };
 449
 450 /* store statistics names and its offset in stats structure */
 451 struct rte_igb_xstats_name_off {
 452         char name[RTE_ETH_XSTATS_NAME_SIZE];
 453         unsigned offset;
 454 };
 455
 456 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 457         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 458         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 459         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 460         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 461         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 462         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 463         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 464                 ecol)},
 465         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 466         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 467         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 468         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 469         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 470         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 471         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 472         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 473         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 474         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 475         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 476                 fcruc)},
 477         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 478         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 479         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 480         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 481         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 482                 prc1023)},
 483         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 484                 prc1522)},
 485         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 486         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 487         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 488         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 489         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 490         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 491         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 492         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 493         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 494         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 495         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 496         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 497         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 498         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 499         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 500         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 501         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 502         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 503                 ptc1023)},
 504         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 505                 ptc1522)},
 506         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 507         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 508         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 509         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 510         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 511         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 512         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 513
 514         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 515 };
 516
 517 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 518                 sizeof(rte_igb_stats_strings[0]))
 519
 520 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 521         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 522         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 523         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 524         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 525         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 526 };
 527
 528 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 529                 sizeof(rte_igbvf_stats_strings[0]))
 530
 531
 532 static inline void
 533 igb_intr_enable(struct rte_eth_dev *dev)
 534 {
 535         struct e1000_interrupt *intr =
 536                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 537         struct e1000_hw *hw =
 538                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 539         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 540         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 541
 542         if (rte_intr_allow_others(intr_handle) &&
 543                 dev->data->dev_conf.intr_conf.lsc != 0) {
 544                 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
 545         }
 546
 547         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 548         E1000_WRITE_FLUSH(hw);
 549 }
 550
 551 static void
 552 igb_intr_disable(struct rte_eth_dev *dev)
 553 {
 554         struct e1000_hw *hw =
 555                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 556         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 557         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 558
 559         if (rte_intr_allow_others(intr_handle) &&
 560                 dev->data->dev_conf.intr_conf.lsc != 0) {
 561                 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
 562         }
 563
 564         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 565         E1000_WRITE_FLUSH(hw);
 566 }
 567
 568 static inline void
 569 igbvf_intr_enable(struct rte_eth_dev *dev)
 570 {
 571         struct e1000_hw *hw =
 572                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 573
 574         /* only for mailbox */
 575         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 576         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 577         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 578         E1000_WRITE_FLUSH(hw);
 579 }
 580
 581 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 582 static void
 583 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 584 {
 585         uint32_t tmp = 0;
 586
 587         /* mailbox */
 588         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 589         tmp |= E1000_VTIVAR_VALID;
 590         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 591 }
 592
 593 static void
 594 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 595 {
 596         struct e1000_hw *hw =
 597                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 598
 599         /* Configure VF other cause ivar */
 600         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 601 }
 602
 603 static inline int32_t
 604 igb_pf_reset_hw(struct e1000_hw *hw)
 605 {
 606         uint32_t ctrl_ext;
 607         int32_t status;
 608
 609         status = e1000_reset_hw(hw);
 610
 611         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 612         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 613         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 614         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 615         E1000_WRITE_FLUSH(hw);
 616
 617         return status;
 618 }
 619
 620 static void
 621 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 622 {
 623         struct e1000_hw *hw =
 624                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 625
 626
 627         hw->vendor_id = pci_dev->id.vendor_id;
 628         hw->device_id = pci_dev->id.device_id;
 629         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 630         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 631
 632         e1000_set_mac_type(hw);
 633
 634         /* need to check if it is a vf device below */
 635 }
 636
 637 static int
 638 igb_reset_swfw_lock(struct e1000_hw *hw)
 639 {
 640         int ret_val;
 641
 642         /*
 643          * Do mac ops initialization manually here, since we will need
 644          * some function pointers set by this call.
 645          */
 646         ret_val = e1000_init_mac_params(hw);
 647         if (ret_val)
 648                 return ret_val;
 649
 650         /*
 651          * SMBI lock should not fail in this early stage. If this is the case,
 652          * it is due to an improper exit of the application.
 653          * So force the release of the faulty lock.
 654          */
 655         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 656                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 657         }
 658         e1000_put_hw_semaphore_generic(hw);
 659
 660         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 661                 uint16_t mask;
 662
 663                 /*
 664                  * Phy lock should not fail in this early stage. If this is the case,
 665                  * it is due to an improper exit of the application.
 666                  * So force the release of the faulty lock.
 667                  */
 668                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 669                 if (hw->bus.func > E1000_FUNC_1)
 670                         mask <<= 2;
 671                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 672                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 673                                     hw->bus.func);
 674                 }
 675                 hw->mac.ops.release_swfw_sync(hw, mask);
 676
 677                 /*
 678                  * This one is more tricky since it is common to all ports; but
 679                  * swfw_sync retries last long enough (1s) to be almost sure that if
 680                  * lock can not be taken it is due to an improper lock of the
 681                  * semaphore.
 682                  */
 683                 mask = E1000_SWFW_EEP_SM;
 684                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 685                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 686                 }
 687                 hw->mac.ops.release_swfw_sync(hw, mask);
 688         }
 689
 690         return E1000_SUCCESS;
 691 }
 692
 693 /* Remove all ntuple filters of the device */
 694 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 695 {
 696         struct e1000_filter_info *filter_info =
 697                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 698         struct e1000_5tuple_filter *p_5tuple;
 699         struct e1000_2tuple_filter *p_2tuple;
 700
 701         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 702                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 703                         p_5tuple, entries);
 704                         rte_free(p_5tuple);
 705         }
 706         filter_info->fivetuple_mask = 0;
 707         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 708                 TAILQ_REMOVE(&filter_info->twotuple_list,
 709                         p_2tuple, entries);
 710                         rte_free(p_2tuple);
 711         }
 712         filter_info->twotuple_mask = 0;
 713
 714         return 0;
 715 }
 716
 717 /* Remove all flex filters of the device */
 718 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 719 {
 720         struct e1000_filter_info *filter_info =
 721                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 722         struct e1000_flex_filter *p_flex;
 723
 724         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 725                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 726                 rte_free(p_flex);
 727         }
 728         filter_info->flex_mask = 0;
 729
 730         return 0;
 731 }
 732
 733 static int
 734 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 735 {
 736         int error = 0;
 737         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 738         struct e1000_hw *hw =
 739                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 740         struct e1000_vfta * shadow_vfta =
 741                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 742         struct e1000_filter_info *filter_info =
 743                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 744         struct e1000_adapter *adapter =
 745                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 746
 747         uint32_t ctrl_ext;
 748
 749         eth_dev->dev_ops = &eth_igb_ops;
 750         eth_dev->rx_queue_count = eth_igb_rx_queue_count;
 751         eth_dev->rx_descriptor_done   = eth_igb_rx_descriptor_done;
 752         eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
 753         eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
 754         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 755         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 756         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 757
 758         /* for secondary processes, we don't initialise any further as primary
 759          * has already done this work. Only check we don't need a different
 760          * RX function */
 761         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 762                 if (eth_dev->data->scattered_rx)
 763                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 764                 return 0;
 765         }
 766
 767         rte_eth_copy_pci_info(eth_dev, pci_dev);
 768
 769         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 770
 771         igb_identify_hardware(eth_dev, pci_dev);
 772         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 773                 error = -EIO;
 774                 goto err_late;
 775         }
 776
 777         e1000_get_bus_info(hw);
 778
 779         /* Reset any pending lock */
 780         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 781                 error = -EIO;
 782                 goto err_late;
 783         }
 784
 785         /* Finish initialization */
 786         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 787                 error = -EIO;
 788                 goto err_late;
 789         }
 790
 791         hw->mac.autoneg = 1;
 792         hw->phy.autoneg_wait_to_complete = 0;
 793         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 794
 795         /* Copper options */
 796         if (hw->phy.media_type == e1000_media_type_copper) {
 797                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 798                 hw->phy.disable_polarity_correction = 0;
 799                 hw->phy.ms_type = e1000_ms_hw_default;
 800         }
 801
 802         /*
 803          * Start from a known state, this is important in reading the nvm
 804          * and mac from that.
 805          */
 806         igb_pf_reset_hw(hw);
 807
 808         /* Make sure we have a good EEPROM before we read from it */
 809         if (e1000_validate_nvm_checksum(hw) < 0) {
 810                 /*
 811                  * Some PCI-E parts fail the first check due to
 812                  * the link being in sleep state, call it again,
 813                  * if it fails a second time its a real issue.
 814                  */
 815                 if (e1000_validate_nvm_checksum(hw) < 0) {
 816                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 817                         error = -EIO;
 818                         goto err_late;
 819                 }
 820         }
 821
 822         /* Read the permanent MAC address out of the EEPROM */
 823         if (e1000_read_mac_addr(hw) != 0) {
 824                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 825                 error = -EIO;
 826                 goto err_late;
 827         }
 828
 829         /* Allocate memory for storing MAC addresses */
 830         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 831                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 832         if (eth_dev->data->mac_addrs == NULL) {
 833                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 834                                                 "store MAC addresses",
 835                                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 836                 error = -ENOMEM;
 837                 goto err_late;
 838         }
 839
 840         /* Copy the permanent MAC address */
 841         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 842                         &eth_dev->data->mac_addrs[0]);
 843
 844         /* initialize the vfta */
 845         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 846
 847         /* Now initialize the hardware */
 848         if (igb_hardware_init(hw) != 0) {
 849                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 850                 rte_free(eth_dev->data->mac_addrs);
 851                 eth_dev->data->mac_addrs = NULL;
 852                 error = -ENODEV;
 853                 goto err_late;
 854         }
 855         hw->mac.get_link_status = 1;
 856         adapter->stopped = 0;
 857
 858         /* Indicate SOL/IDER usage */
 859         if (e1000_check_reset_block(hw) < 0) {
 860                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 861                                         "SOL/IDER session");
 862         }
 863
 864         /* initialize PF if max_vfs not zero */
 865         igb_pf_host_init(eth_dev);
 866
 867         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 868         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 869         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 870         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 871         E1000_WRITE_FLUSH(hw);
 872
 873         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 874                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 875                      pci_dev->id.device_id);
 876
 877         rte_intr_callback_register(&pci_dev->intr_handle,
 878                                    eth_igb_interrupt_handler,
 879                                    (void *)eth_dev);
 880
 881         /* enable uio/vfio intr/eventfd mapping */
 882         rte_intr_enable(&pci_dev->intr_handle);
 883
 884         /* enable support intr */
 885         igb_intr_enable(eth_dev);
 886
 887         eth_igb_dev_set_link_down(eth_dev);
 888
 889         /* initialize filter info */
 890         memset(filter_info, 0,
 891                sizeof(struct e1000_filter_info));
 892
 893         TAILQ_INIT(&filter_info->flex_list);
 894         TAILQ_INIT(&filter_info->twotuple_list);
 895         TAILQ_INIT(&filter_info->fivetuple_list);
 896
 897         TAILQ_INIT(&igb_filter_ntuple_list);
 898         TAILQ_INIT(&igb_filter_ethertype_list);
 899         TAILQ_INIT(&igb_filter_syn_list);
 900         TAILQ_INIT(&igb_filter_flex_list);
 901         TAILQ_INIT(&igb_filter_rss_list);
 902         TAILQ_INIT(&igb_flow_list);
 903
 904         return 0;
 905
 906 err_late:
 907         igb_hw_control_release(hw);
 908
 909         return error;
 910 }
 911
 912 static int
 913 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 914 {
 915         PMD_INIT_FUNC_TRACE();
 916
 917         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 918                 return 0;
 919
 920         eth_igb_close(eth_dev);
 921
 922         return 0;
 923 }
 924
 925 /*
 926  * Virtual Function device init
 927  */
 928 static int
 929 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 930 {
 931         struct rte_pci_device *pci_dev;
 932         struct rte_intr_handle *intr_handle;
 933         struct e1000_adapter *adapter =
 934                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 935         struct e1000_hw *hw =
 936                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 937         int diag;
 938         struct rte_ether_addr *perm_addr =
 939                 (struct rte_ether_addr *)hw->mac.perm_addr;
 940
 941         PMD_INIT_FUNC_TRACE();
 942
 943         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 944         eth_dev->rx_descriptor_done   = eth_igb_rx_descriptor_done;
 945         eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
 946         eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
 947         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 948         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 949         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 950
 951         /* for secondary processes, we don't initialise any further as primary
 952          * has already done this work. Only check we don't need a different
 953          * RX function */
 954         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 955                 if (eth_dev->data->scattered_rx)
 956                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 957                 return 0;
 958         }
 959
 960         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 961         rte_eth_copy_pci_info(eth_dev, pci_dev);
 962
 963         hw->device_id = pci_dev->id.device_id;
 964         hw->vendor_id = pci_dev->id.vendor_id;
 965         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 966         adapter->stopped = 0;
 967
 968         /* Initialize the shared code (base driver) */
 969         diag = e1000_setup_init_funcs(hw, TRUE);
 970         if (diag != 0) {
 971                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 972                         diag);
 973                 return -EIO;
 974         }
 975
 976         /* init_mailbox_params */
 977         hw->mbx.ops.init_params(hw);
 978
 979         /* Disable the interrupts for VF */
 980         igbvf_intr_disable(hw);
 981
 982         diag = hw->mac.ops.reset_hw(hw);
 983
 984         /* Allocate memory for storing MAC addresses */
 985         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
 986                 hw->mac.rar_entry_count, 0);
 987         if (eth_dev->data->mac_addrs == NULL) {
 988                 PMD_INIT_LOG(ERR,
 989                         "Failed to allocate %d bytes needed to store MAC "
 990                         "addresses",
 991                         RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 992                 return -ENOMEM;
 993         }
 994
 995         /* Generate a random MAC address, if none was assigned by PF. */
 996         if (rte_is_zero_ether_addr(perm_addr)) {
 997                 rte_eth_random_addr(perm_addr->addr_bytes);
 998                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
 999                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1000                              "%02x:%02x:%02x:%02x:%02x:%02x",
1001                              perm_addr->addr_bytes[0],
1002                              perm_addr->addr_bytes[1],
1003                              perm_addr->addr_bytes[2],
1004                              perm_addr->addr_bytes[3],
1005                              perm_addr->addr_bytes[4],
1006                              perm_addr->addr_bytes[5]);
1007         }
1008
1009         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1010         if (diag) {
1011                 rte_free(eth_dev->data->mac_addrs);
1012                 eth_dev->data->mac_addrs = NULL;
1013                 return diag;
1014         }
1015         /* Copy the permanent MAC address */
1016         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1017                         &eth_dev->data->mac_addrs[0]);
1018
1019         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1020                      "mac.type=%s",
1021                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1022                      pci_dev->id.device_id, "igb_mac_82576_vf");
1023
1024         intr_handle = &pci_dev->intr_handle;
1025         rte_intr_callback_register(intr_handle,
1026                                    eth_igbvf_interrupt_handler, eth_dev);
1027
1028         return 0;
1029 }
1030
1031 static int
1032 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1033 {
1034         PMD_INIT_FUNC_TRACE();
1035
1036         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1037                 return 0;
1038
1039         igbvf_dev_close(eth_dev);
1040
1041         return 0;
1042 }
1043
1044 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1045         struct rte_pci_device *pci_dev)
1046 {
1047         return rte_eth_dev_pci_generic_probe(pci_dev,
1048                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1049 }
1050
1051 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1052 {
1053         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1054 }
1055
1056 static struct rte_pci_driver rte_igb_pmd = {
1057         .id_table = pci_id_igb_map,
1058         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1059         .probe = eth_igb_pci_probe,
1060         .remove = eth_igb_pci_remove,
1061 };
1062
1063
1064 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1065         struct rte_pci_device *pci_dev)
1066 {
1067         return rte_eth_dev_pci_generic_probe(pci_dev,
1068                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1069 }
1070
1071 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1072 {
1073         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1074 }
1075
1076 /*
1077  * virtual function driver struct
1078  */
1079 static struct rte_pci_driver rte_igbvf_pmd = {
1080         .id_table = pci_id_igbvf_map,
1081         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1082         .probe = eth_igbvf_pci_probe,
1083         .remove = eth_igbvf_pci_remove,
1084 };
1085
1086 static void
1087 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1088 {
1089         struct e1000_hw *hw =
1090                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1091         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1092         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1093         rctl |= E1000_RCTL_VFE;
1094         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1095 }
1096
1097 static int
1098 igb_check_mq_mode(struct rte_eth_dev *dev)
1099 {
1100         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1101         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1102         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1103         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1104
1105         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1106             tx_mq_mode == ETH_MQ_TX_DCB ||
1107             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1108                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1109                 return -EINVAL;
1110         }
1111         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1112                 /* Check multi-queue mode.
1113                  * To no break software we accept ETH_MQ_RX_NONE as this might
1114                  * be used to turn off VLAN filter.
1115                  */
1116
1117                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1118                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1119                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1120                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1121                 } else {
1122                         /* Only support one queue on VFs.
1123                          * RSS together with SRIOV is not supported.
1124                          */
1125                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1126                                         " wrong mq_mode rx %d.",
1127                                         rx_mq_mode);
1128                         return -EINVAL;
1129                 }
1130                 /* TX mode is not used here, so mode might be ignored.*/
1131                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1132                         /* SRIOV only works in VMDq enable mode */
1133                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1134                                         " TX mode %d is not supported. "
1135                                         " Driver will behave as %d mode.",
1136                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1137                 }
1138
1139                 /* check valid queue number */
1140                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1141                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1142                                         " only support one queue on VFs.");
1143                         return -EINVAL;
1144                 }
1145         } else {
1146                 /* To no break software that set invalid mode, only display
1147                  * warning if invalid mode is used.
1148                  */
1149                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1150                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1151                     rx_mq_mode != ETH_MQ_RX_RSS) {
1152                         /* RSS together with VMDq not supported*/
1153                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1154                                      rx_mq_mode);
1155                         return -EINVAL;
1156                 }
1157
1158                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1159                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1160                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1161                                         " Due to txmode is meaningless in this"
1162                                         " driver, just ignore.",
1163                                         tx_mq_mode);
1164                 }
1165         }
1166         return 0;
1167 }
1168
1169 static int
1170 eth_igb_configure(struct rte_eth_dev *dev)
1171 {
1172         struct e1000_interrupt *intr =
1173                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1174         int ret;
1175
1176         PMD_INIT_FUNC_TRACE();
1177
1178         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1179                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1180
1181         /* multipe queue mode checking */
1182         ret  = igb_check_mq_mode(dev);
1183         if (ret != 0) {
1184                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1185                             ret);
1186                 return ret;
1187         }
1188
1189         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1190         PMD_INIT_FUNC_TRACE();
1191
1192         return 0;
1193 }
1194
1195 static void
1196 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1197                      bool enable)
1198 {
1199         struct e1000_hw *hw =
1200                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1201         uint32_t tctl, rctl;
1202
1203         tctl = E1000_READ_REG(hw, E1000_TCTL);
1204         rctl = E1000_READ_REG(hw, E1000_RCTL);
1205
1206         if (enable) {
1207                 /* enable Tx/Rx */
1208                 tctl |= E1000_TCTL_EN;
1209                 rctl |= E1000_RCTL_EN;
1210         } else {
1211                 /* disable Tx/Rx */
1212                 tctl &= ~E1000_TCTL_EN;
1213                 rctl &= ~E1000_RCTL_EN;
1214         }
1215         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1216         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1217         E1000_WRITE_FLUSH(hw);
1218 }
1219
1220 static int
1221 eth_igb_start(struct rte_eth_dev *dev)
1222 {
1223         struct e1000_hw *hw =
1224                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1225         struct e1000_adapter *adapter =
1226                 E1000_DEV_PRIVATE(dev->data->dev_private);
1227         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1228         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1229         int ret, mask;
1230         uint32_t intr_vector = 0;
1231         uint32_t ctrl_ext;
1232         uint32_t *speeds;
1233         int num_speeds;
1234         bool autoneg;
1235
1236         PMD_INIT_FUNC_TRACE();
1237
1238         /* disable uio/vfio intr/eventfd mapping */
1239         rte_intr_disable(intr_handle);
1240
1241         /* Power up the phy. Needed to make the link go Up */
1242         eth_igb_dev_set_link_up(dev);
1243
1244         /*
1245          * Packet Buffer Allocation (PBA)
1246          * Writing PBA sets the receive portion of the buffer
1247          * the remainder is used for the transmit buffer.
1248          */
1249         if (hw->mac.type == e1000_82575) {
1250                 uint32_t pba;
1251
1252                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1253                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1254         }
1255
1256         /* Put the address into the Receive Address Array */
1257         e1000_rar_set(hw, hw->mac.addr, 0);
1258
1259         /* Initialize the hardware */
1260         if (igb_hardware_init(hw)) {
1261                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1262                 return -EIO;
1263         }
1264         adapter->stopped = 0;
1265
1266         E1000_WRITE_REG(hw, E1000_VET,
1267                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1268
1269         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1270         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1271         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1272         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1273         E1000_WRITE_FLUSH(hw);
1274
1275         /* configure PF module if SRIOV enabled */
1276         igb_pf_host_configure(dev);
1277
1278         /* check and configure queue intr-vector mapping */
1279         if ((rte_intr_cap_multiple(intr_handle) ||
1280              !RTE_ETH_DEV_SRIOV(dev).active) &&
1281             dev->data->dev_conf.intr_conf.rxq != 0) {
1282                 intr_vector = dev->data->nb_rx_queues;
1283                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1284                         return -1;
1285         }
1286
1287         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1288                 intr_handle->intr_vec =
1289                         rte_zmalloc("intr_vec",
1290                                     dev->data->nb_rx_queues * sizeof(int), 0);
1291                 if (intr_handle->intr_vec == NULL) {
1292                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1293                                      " intr_vec", dev->data->nb_rx_queues);
1294                         return -ENOMEM;
1295                 }
1296         }
1297
1298         /* confiugre msix for rx interrupt */
1299         eth_igb_configure_msix_intr(dev);
1300
1301         /* Configure for OS presence */
1302         igb_init_manageability(hw);
1303
1304         eth_igb_tx_init(dev);
1305
1306         /* This can fail when allocating mbufs for descriptor rings */
1307         ret = eth_igb_rx_init(dev);
1308         if (ret) {
1309                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1310                 igb_dev_clear_queues(dev);
1311                 return ret;
1312         }
1313
1314         e1000_clear_hw_cntrs_base_generic(hw);
1315
1316         /*
1317          * VLAN Offload Settings
1318          */
1319         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1320                         ETH_VLAN_EXTEND_MASK;
1321         ret = eth_igb_vlan_offload_set(dev, mask);
1322         if (ret) {
1323                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1324                 igb_dev_clear_queues(dev);
1325                 return ret;
1326         }
1327
1328         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1329                 /* Enable VLAN filter since VMDq always use VLAN filter */
1330                 igb_vmdq_vlan_hw_filter_enable(dev);
1331         }
1332
1333         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1334                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1335                 (hw->mac.type == e1000_i211)) {
1336                 /* Configure EITR with the maximum possible value (0xFFFF) */
1337                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1338         }
1339
1340         /* Setup link speed and duplex */
1341         speeds = &dev->data->dev_conf.link_speeds;
1342         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1343                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1344                 hw->mac.autoneg = 1;
1345         } else {
1346                 num_speeds = 0;
1347                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1348
1349                 /* Reset */
1350                 hw->phy.autoneg_advertised = 0;
1351
1352                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1353                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1354                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1355                         num_speeds = -1;
1356                         goto error_invalid_config;
1357                 }
1358                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1359                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1360                         num_speeds++;
1361                 }
1362                 if (*speeds & ETH_LINK_SPEED_10M) {
1363                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1364                         num_speeds++;
1365                 }
1366                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1367                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1368                         num_speeds++;
1369                 }
1370                 if (*speeds & ETH_LINK_SPEED_100M) {
1371                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1372                         num_speeds++;
1373                 }
1374                 if (*speeds & ETH_LINK_SPEED_1G) {
1375                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1376                         num_speeds++;
1377                 }
1378                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1379                         goto error_invalid_config;
1380
1381                 /* Set/reset the mac.autoneg based on the link speed,
1382                  * fixed or not
1383                  */
1384                 if (!autoneg) {
1385                         hw->mac.autoneg = 0;
1386                         hw->mac.forced_speed_duplex =
1387                                         hw->phy.autoneg_advertised;
1388                 } else {
1389                         hw->mac.autoneg = 1;
1390                 }
1391         }
1392
1393         e1000_setup_link(hw);
1394
1395         if (rte_intr_allow_others(intr_handle)) {
1396                 /* check if lsc interrupt is enabled */
1397                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1398                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1399                 else
1400                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1401         } else {
1402                 rte_intr_callback_unregister(intr_handle,
1403                                              eth_igb_interrupt_handler,
1404                                              (void *)dev);
1405                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1406                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1407                                      " no intr multiplex");
1408         }
1409
1410         /* check if rxq interrupt is enabled */
1411         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1412             rte_intr_dp_is_en(intr_handle))
1413                 eth_igb_rxq_interrupt_setup(dev);
1414
1415         /* enable uio/vfio intr/eventfd mapping */
1416         rte_intr_enable(intr_handle);
1417
1418         /* resume enabled intr since hw reset */
1419         igb_intr_enable(dev);
1420
1421         /* restore all types filter */
1422         igb_filter_restore(dev);
1423
1424         eth_igb_rxtx_control(dev, true);
1425         eth_igb_link_update(dev, 0);
1426
1427         PMD_INIT_LOG(DEBUG, "<<");
1428
1429         return 0;
1430
1431 error_invalid_config:
1432         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1433                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1434         igb_dev_clear_queues(dev);
1435         return -EINVAL;
1436 }
1437
1438 /*********************************************************************
1439  *
1440  *  This routine disables all traffic on the adapter by issuing a
1441  *  global reset on the MAC.
1442  *
1443  **********************************************************************/
1444 static void
1445 eth_igb_stop(struct rte_eth_dev *dev)
1446 {
1447         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1448         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1449         struct rte_eth_link link;
1450         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1451         struct e1000_adapter *adapter =
1452                 E1000_DEV_PRIVATE(dev->data->dev_private);
1453
1454         if (adapter->stopped)
1455                 return;
1456
1457         eth_igb_rxtx_control(dev, false);
1458
1459         igb_intr_disable(dev);
1460
1461         /* disable intr eventfd mapping */
1462         rte_intr_disable(intr_handle);
1463
1464         igb_pf_reset_hw(hw);
1465         E1000_WRITE_REG(hw, E1000_WUC, 0);
1466
1467         /* Set bit for Go Link disconnect if PHY reset is not blocked */
1468         if (hw->mac.type >= e1000_82580 &&
1469             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1470                 uint32_t phpm_reg;
1471
1472                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1473                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1474                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1475         }
1476
1477         /* Power down the phy. Needed to make the link go Down */
1478         eth_igb_dev_set_link_down(dev);
1479
1480         igb_dev_clear_queues(dev);
1481
1482         /* clear the recorded link status */
1483         memset(&link, 0, sizeof(link));
1484         rte_eth_linkstatus_set(dev, &link);
1485
1486         if (!rte_intr_allow_others(intr_handle))
1487                 /* resume to the default handler */
1488                 rte_intr_callback_register(intr_handle,
1489                                            eth_igb_interrupt_handler,
1490                                            (void *)dev);
1491
1492         /* Clean datapath event and queue/vec mapping */
1493         rte_intr_efd_disable(intr_handle);
1494         if (intr_handle->intr_vec != NULL) {
1495                 rte_free(intr_handle->intr_vec);
1496                 intr_handle->intr_vec = NULL;
1497         }
1498
1499         adapter->stopped = true;
1500         dev->data->dev_started = 0;
1501 }
1502
1503 static int
1504 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1505 {
1506         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1507
1508         if (hw->phy.media_type == e1000_media_type_copper)
1509                 e1000_power_up_phy(hw);
1510         else
1511                 e1000_power_up_fiber_serdes_link(hw);
1512
1513         return 0;
1514 }
1515
1516 static int
1517 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1518 {
1519         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1520
1521         if (hw->phy.media_type == e1000_media_type_copper)
1522                 e1000_power_down_phy(hw);
1523         else
1524                 e1000_shutdown_fiber_serdes_link(hw);
1525
1526         return 0;
1527 }
1528
1529 static int
1530 eth_igb_close(struct rte_eth_dev *dev)
1531 {
1532         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1533         struct rte_eth_link link;
1534         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1535         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1536         struct e1000_filter_info *filter_info =
1537                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1538
1539         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1540                 return 0;
1541
1542         eth_igb_stop(dev);
1543
1544         e1000_phy_hw_reset(hw);
1545         igb_release_manageability(hw);
1546         igb_hw_control_release(hw);
1547
1548         /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1549         if (hw->mac.type >= e1000_82580 &&
1550             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1551                 uint32_t phpm_reg;
1552
1553                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1554                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1555                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1556         }
1557
1558         igb_dev_free_queues(dev);
1559
1560         if (intr_handle->intr_vec) {
1561                 rte_free(intr_handle->intr_vec);
1562                 intr_handle->intr_vec = NULL;
1563         }
1564
1565         memset(&link, 0, sizeof(link));
1566         rte_eth_linkstatus_set(dev, &link);
1567
1568         dev->dev_ops = NULL;
1569         dev->rx_pkt_burst = NULL;
1570         dev->tx_pkt_burst = NULL;
1571
1572         /* Reset any pending lock */
1573         igb_reset_swfw_lock(hw);
1574
1575         /* uninitialize PF if max_vfs not zero */
1576         igb_pf_host_uninit(dev);
1577
1578         rte_intr_callback_unregister(intr_handle,
1579                                      eth_igb_interrupt_handler, dev);
1580
1581         /* clear the SYN filter info */
1582         filter_info->syn_info = 0;
1583
1584         /* clear the ethertype filters info */
1585         filter_info->ethertype_mask = 0;
1586         memset(filter_info->ethertype_filters, 0,
1587                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1588
1589         /* clear the rss filter info */
1590         memset(&filter_info->rss_info, 0,
1591                 sizeof(struct igb_rte_flow_rss_conf));
1592
1593         /* remove all ntuple filters of the device */
1594         igb_ntuple_filter_uninit(dev);
1595
1596         /* remove all flex filters of the device */
1597         igb_flex_filter_uninit(dev);
1598
1599         /* clear all the filters list */
1600         igb_filterlist_flush(dev);
1601
1602         return 0;
1603 }
1604
1605 /*
1606  * Reset PF device.
1607  */
1608 static int
1609 eth_igb_reset(struct rte_eth_dev *dev)
1610 {
1611         int ret;
1612
1613         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1614          * its VF to make them align with it. The detailed notification
1615          * mechanism is PMD specific and is currently not implemented.
1616          * To avoid unexpected behavior in VF, currently reset of PF with
1617          * SR-IOV activation is not supported. It might be supported later.
1618          */
1619         if (dev->data->sriov.active)
1620                 return -ENOTSUP;
1621
1622         ret = eth_igb_dev_uninit(dev);
1623         if (ret)
1624                 return ret;
1625
1626         ret = eth_igb_dev_init(dev);
1627
1628         return ret;
1629 }
1630
1631
1632 static int
1633 igb_get_rx_buffer_size(struct e1000_hw *hw)
1634 {
1635         uint32_t rx_buf_size;
1636         if (hw->mac.type == e1000_82576) {
1637                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1638         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1639                 /* PBS needs to be translated according to a lookup table */
1640                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1641                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1642                 rx_buf_size = (rx_buf_size << 10);
1643         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1644                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1645         } else {
1646                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1647         }
1648
1649         return rx_buf_size;
1650 }
1651
1652 /*********************************************************************
1653  *
1654  *  Initialize the hardware
1655  *
1656  **********************************************************************/
1657 static int
1658 igb_hardware_init(struct e1000_hw *hw)
1659 {
1660         uint32_t rx_buf_size;
1661         int diag;
1662
1663         /* Let the firmware know the OS is in control */
1664         igb_hw_control_acquire(hw);
1665
1666         /*
1667          * These parameters control the automatic generation (Tx) and
1668          * response (Rx) to Ethernet PAUSE frames.
1669          * - High water mark should allow for at least two standard size (1518)
1670          *   frames to be received after sending an XOFF.
1671          * - Low water mark works best when it is very near the high water mark.
1672          *   This allows the receiver to restart by sending XON when it has
1673          *   drained a bit. Here we use an arbitrary value of 1500 which will
1674          *   restart after one full frame is pulled from the buffer. There
1675          *   could be several smaller frames in the buffer and if so they will
1676          *   not trigger the XON until their total number reduces the buffer
1677          *   by 1500.
1678          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1679          */
1680         rx_buf_size = igb_get_rx_buffer_size(hw);
1681
1682         hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1683         hw->fc.low_water = hw->fc.high_water - 1500;
1684         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1685         hw->fc.send_xon = 1;
1686
1687         /* Set Flow control, use the tunable location if sane */
1688         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1689                 hw->fc.requested_mode = igb_fc_setting;
1690         else
1691                 hw->fc.requested_mode = e1000_fc_none;
1692
1693         /* Issue a global reset */
1694         igb_pf_reset_hw(hw);
1695         E1000_WRITE_REG(hw, E1000_WUC, 0);
1696
1697         diag = e1000_init_hw(hw);
1698         if (diag < 0)
1699                 return diag;
1700
1701         E1000_WRITE_REG(hw, E1000_VET,
1702                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1703         e1000_get_phy_info(hw);
1704         e1000_check_for_link(hw);
1705
1706         return 0;
1707 }
1708
1709 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1710 static void
1711 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1712 {
1713         int pause_frames;
1714
1715         uint64_t old_gprc  = stats->gprc;
1716         uint64_t old_gptc  = stats->gptc;
1717         uint64_t old_tpr   = stats->tpr;
1718         uint64_t old_tpt   = stats->tpt;
1719         uint64_t old_rpthc = stats->rpthc;
1720         uint64_t old_hgptc = stats->hgptc;
1721
1722         if(hw->phy.media_type == e1000_media_type_copper ||
1723             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1724                 stats->symerrs +=
1725                     E1000_READ_REG(hw,E1000_SYMERRS);
1726                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1727         }
1728
1729         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1730         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1731         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1732         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1733
1734         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1735         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1736         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1737         stats->dc += E1000_READ_REG(hw, E1000_DC);
1738         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1739         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1740         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1741         /*
1742         ** For watchdog management we need to know if we have been
1743         ** paused during the last interval, so capture that here.
1744         */
1745         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1746         stats->xoffrxc += pause_frames;
1747         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1748         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1749         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1750         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1751         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1752         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1753         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1754         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1755         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1756         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1757         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1758         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1759
1760         /* For the 64-bit byte counters the low dword must be read first. */
1761         /* Both registers clear on the read of the high dword */
1762
1763         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1764         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1765         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1766         stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1767         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1768         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1769         stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1770
1771         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1772         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1773         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1774         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1775         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1776
1777         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1778         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1779
1780         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1781         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1782         stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1783         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1784         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1785         stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1786
1787         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1788         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1789         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1790         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1791         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1792         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1793         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1794         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1795
1796         /* Interrupt Counts */
1797
1798         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1799         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1800         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1801         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1802         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1803         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1804         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1805         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1806         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1807
1808         /* Host to Card Statistics */
1809
1810         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1811         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1812         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1813         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1814         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1815         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1816         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1817         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1818         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1819         stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1820         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1821         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1822         stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1823         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1824         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1825         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1826
1827         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1828         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1829         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1830         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1831         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1832         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1833 }
1834
1835 static int
1836 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1837 {
1838         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1839         struct e1000_hw_stats *stats =
1840                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1841
1842         igb_read_stats_registers(hw, stats);
1843
1844         if (rte_stats == NULL)
1845                 return -EINVAL;
1846
1847         /* Rx Errors */
1848         rte_stats->imissed = stats->mpc;
1849         rte_stats->ierrors = stats->crcerrs +
1850                              stats->rlec + stats->ruc + stats->roc +
1851                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1852
1853         /* Tx Errors */
1854         rte_stats->oerrors = stats->ecol + stats->latecol;
1855
1856         rte_stats->ipackets = stats->gprc;
1857         rte_stats->opackets = stats->gptc;
1858         rte_stats->ibytes   = stats->gorc;
1859         rte_stats->obytes   = stats->gotc;
1860         return 0;
1861 }
1862
1863 static int
1864 eth_igb_stats_reset(struct rte_eth_dev *dev)
1865 {
1866         struct e1000_hw_stats *hw_stats =
1867                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1868
1869         /* HW registers are cleared on read */
1870         eth_igb_stats_get(dev, NULL);
1871
1872         /* Reset software totals */
1873         memset(hw_stats, 0, sizeof(*hw_stats));
1874
1875         return 0;
1876 }
1877
1878 static int
1879 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1880 {
1881         struct e1000_hw_stats *stats =
1882                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1883
1884         /* HW registers are cleared on read */
1885         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1886
1887         /* Reset software totals */
1888         memset(stats, 0, sizeof(*stats));
1889
1890         return 0;
1891 }
1892
1893 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1894         struct rte_eth_xstat_name *xstats_names,
1895         __rte_unused unsigned int size)
1896 {
1897         unsigned i;
1898
1899         if (xstats_names == NULL)
1900                 return IGB_NB_XSTATS;
1901
1902         /* Note: limit checked in rte_eth_xstats_names() */
1903
1904         for (i = 0; i < IGB_NB_XSTATS; i++) {
1905                 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1906                         sizeof(xstats_names[i].name));
1907         }
1908
1909         return IGB_NB_XSTATS;
1910 }
1911
1912 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1913                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1914                 unsigned int limit)
1915 {
1916         unsigned int i;
1917
1918         if (!ids) {
1919                 if (xstats_names == NULL)
1920                         return IGB_NB_XSTATS;
1921
1922                 for (i = 0; i < IGB_NB_XSTATS; i++)
1923                         strlcpy(xstats_names[i].name,
1924                                 rte_igb_stats_strings[i].name,
1925                                 sizeof(xstats_names[i].name));
1926
1927                 return IGB_NB_XSTATS;
1928
1929         } else {
1930                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1931
1932                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1933                                 IGB_NB_XSTATS);
1934
1935                 for (i = 0; i < limit; i++) {
1936                         if (ids[i] >= IGB_NB_XSTATS) {
1937                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1938                                 return -1;
1939                         }
1940                         strcpy(xstats_names[i].name,
1941                                         xstats_names_copy[ids[i]].name);
1942                 }
1943                 return limit;
1944         }
1945 }
1946
1947 static int
1948 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1949                    unsigned n)
1950 {
1951         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1952         struct e1000_hw_stats *hw_stats =
1953                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1954         unsigned i;
1955
1956         if (n < IGB_NB_XSTATS)
1957                 return IGB_NB_XSTATS;
1958
1959         igb_read_stats_registers(hw, hw_stats);
1960
1961         /* If this is a reset xstats is NULL, and we have cleared the
1962          * registers by reading them.
1963          */
1964         if (!xstats)
1965                 return 0;
1966
1967         /* Extended stats */
1968         for (i = 0; i < IGB_NB_XSTATS; i++) {
1969                 xstats[i].id = i;
1970                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1971                         rte_igb_stats_strings[i].offset);
1972         }
1973
1974         return IGB_NB_XSTATS;
1975 }
1976
1977 static int
1978 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1979                 uint64_t *values, unsigned int n)
1980 {
1981         unsigned int i;
1982
1983         if (!ids) {
1984                 struct e1000_hw *hw =
1985                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1986                 struct e1000_hw_stats *hw_stats =
1987                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1988
1989                 if (n < IGB_NB_XSTATS)
1990                         return IGB_NB_XSTATS;
1991
1992                 igb_read_stats_registers(hw, hw_stats);
1993
1994                 /* If this is a reset xstats is NULL, and we have cleared the
1995                  * registers by reading them.
1996                  */
1997                 if (!values)
1998                         return 0;
1999
2000                 /* Extended stats */
2001                 for (i = 0; i < IGB_NB_XSTATS; i++)
2002                         values[i] = *(uint64_t *)(((char *)hw_stats) +
2003                                         rte_igb_stats_strings[i].offset);
2004
2005                 return IGB_NB_XSTATS;
2006
2007         } else {
2008                 uint64_t values_copy[IGB_NB_XSTATS];
2009
2010                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2011                                 IGB_NB_XSTATS);
2012
2013                 for (i = 0; i < n; i++) {
2014                         if (ids[i] >= IGB_NB_XSTATS) {
2015                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2016                                 return -1;
2017                         }
2018                         values[i] = values_copy[ids[i]];
2019                 }
2020                 return n;
2021         }
2022 }
2023
2024 static void
2025 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2026 {
2027         /* Good Rx packets, include VF loopback */
2028         UPDATE_VF_STAT(E1000_VFGPRC,
2029             hw_stats->last_gprc, hw_stats->gprc);
2030
2031         /* Good Rx octets, include VF loopback */
2032         UPDATE_VF_STAT(E1000_VFGORC,
2033             hw_stats->last_gorc, hw_stats->gorc);
2034
2035         /* Good Tx packets, include VF loopback */
2036         UPDATE_VF_STAT(E1000_VFGPTC,
2037             hw_stats->last_gptc, hw_stats->gptc);
2038
2039         /* Good Tx octets, include VF loopback */
2040         UPDATE_VF_STAT(E1000_VFGOTC,
2041             hw_stats->last_gotc, hw_stats->gotc);
2042
2043         /* Rx Multicst packets */
2044         UPDATE_VF_STAT(E1000_VFMPRC,
2045             hw_stats->last_mprc, hw_stats->mprc);
2046
2047         /* Good Rx loopback packets */
2048         UPDATE_VF_STAT(E1000_VFGPRLBC,
2049             hw_stats->last_gprlbc, hw_stats->gprlbc);
2050
2051         /* Good Rx loopback octets */
2052         UPDATE_VF_STAT(E1000_VFGORLBC,
2053             hw_stats->last_gorlbc, hw_stats->gorlbc);
2054
2055         /* Good Tx loopback packets */
2056         UPDATE_VF_STAT(E1000_VFGPTLBC,
2057             hw_stats->last_gptlbc, hw_stats->gptlbc);
2058
2059         /* Good Tx loopback octets */
2060         UPDATE_VF_STAT(E1000_VFGOTLBC,
2061             hw_stats->last_gotlbc, hw_stats->gotlbc);
2062 }
2063
2064 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2065                                      struct rte_eth_xstat_name *xstats_names,
2066                                      __rte_unused unsigned limit)
2067 {
2068         unsigned i;
2069
2070         if (xstats_names != NULL)
2071                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2072                         strlcpy(xstats_names[i].name,
2073                                 rte_igbvf_stats_strings[i].name,
2074                                 sizeof(xstats_names[i].name));
2075                 }
2076         return IGBVF_NB_XSTATS;
2077 }
2078
2079 static int
2080 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2081                      unsigned n)
2082 {
2083         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2085                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2086         unsigned i;
2087
2088         if (n < IGBVF_NB_XSTATS)
2089                 return IGBVF_NB_XSTATS;
2090
2091         igbvf_read_stats_registers(hw, hw_stats);
2092
2093         if (!xstats)
2094                 return 0;
2095
2096         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2097                 xstats[i].id = i;
2098                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2099                         rte_igbvf_stats_strings[i].offset);
2100         }
2101
2102         return IGBVF_NB_XSTATS;
2103 }
2104
2105 static int
2106 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2107 {
2108         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2109         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2110                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2111
2112         igbvf_read_stats_registers(hw, hw_stats);
2113
2114         if (rte_stats == NULL)
2115                 return -EINVAL;
2116
2117         rte_stats->ipackets = hw_stats->gprc;
2118         rte_stats->ibytes = hw_stats->gorc;
2119         rte_stats->opackets = hw_stats->gptc;
2120         rte_stats->obytes = hw_stats->gotc;
2121         return 0;
2122 }
2123
2124 static int
2125 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2126 {
2127         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2128                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2129
2130         /* Sync HW register to the last stats */
2131         eth_igbvf_stats_get(dev, NULL);
2132
2133         /* reset HW current stats*/
2134         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2135                offsetof(struct e1000_vf_stats, gprc));
2136
2137         return 0;
2138 }
2139
2140 static int
2141 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2142                        size_t fw_size)
2143 {
2144         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2145         struct e1000_fw_version fw;
2146         int ret;
2147
2148         e1000_get_fw_version(hw, &fw);
2149
2150         switch (hw->mac.type) {
2151         case e1000_i210:
2152         case e1000_i211:
2153                 if (!(e1000_get_flash_presence_i210(hw))) {
2154                         ret = snprintf(fw_version, fw_size,
2155                                  "%2d.%2d-%d",
2156                                  fw.invm_major, fw.invm_minor,
2157                                  fw.invm_img_type);
2158                         break;
2159                 }
2160                 /* fall through */
2161         default:
2162                 /* if option rom is valid, display its version too */
2163                 if (fw.or_valid) {
2164                         ret = snprintf(fw_version, fw_size,
2165                                  "%d.%d, 0x%08x, %d.%d.%d",
2166                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2167                                  fw.or_major, fw.or_build, fw.or_patch);
2168                 /* no option rom */
2169                 } else {
2170                         if (fw.etrack_id != 0X0000) {
2171                                 ret = snprintf(fw_version, fw_size,
2172                                          "%d.%d, 0x%08x",
2173                                          fw.eep_major, fw.eep_minor,
2174                                          fw.etrack_id);
2175                         } else {
2176                                 ret = snprintf(fw_version, fw_size,
2177                                          "%d.%d.%d",
2178                                          fw.eep_major, fw.eep_minor,
2179                                          fw.eep_build);
2180                         }
2181                 }
2182                 break;
2183         }
2184
2185         ret += 1; /* add the size of '\0' */
2186         if (fw_size < (u32)ret)
2187                 return ret;
2188         else
2189                 return 0;
2190 }
2191
2192 static int
2193 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2194 {
2195         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2196
2197         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2198         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2199         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2200         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2201         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2202                                     dev_info->rx_queue_offload_capa;
2203         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2204         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2205                                     dev_info->tx_queue_offload_capa;
2206
2207         switch (hw->mac.type) {
2208         case e1000_82575:
2209                 dev_info->max_rx_queues = 4;
2210                 dev_info->max_tx_queues = 4;
2211                 dev_info->max_vmdq_pools = 0;
2212                 break;
2213
2214         case e1000_82576:
2215                 dev_info->max_rx_queues = 16;
2216                 dev_info->max_tx_queues = 16;
2217                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2218                 dev_info->vmdq_queue_num = 16;
2219                 break;
2220
2221         case e1000_82580:
2222                 dev_info->max_rx_queues = 8;
2223                 dev_info->max_tx_queues = 8;
2224                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2225                 dev_info->vmdq_queue_num = 8;
2226                 break;
2227
2228         case e1000_i350:
2229                 dev_info->max_rx_queues = 8;
2230                 dev_info->max_tx_queues = 8;
2231                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2232                 dev_info->vmdq_queue_num = 8;
2233                 break;
2234
2235         case e1000_i354:
2236                 dev_info->max_rx_queues = 8;
2237                 dev_info->max_tx_queues = 8;
2238                 break;
2239
2240         case e1000_i210:
2241                 dev_info->max_rx_queues = 4;
2242                 dev_info->max_tx_queues = 4;
2243                 dev_info->max_vmdq_pools = 0;
2244                 break;
2245
2246         case e1000_i211:
2247                 dev_info->max_rx_queues = 2;
2248                 dev_info->max_tx_queues = 2;
2249                 dev_info->max_vmdq_pools = 0;
2250                 break;
2251
2252         default:
2253                 /* Should not happen */
2254                 return -EINVAL;
2255         }
2256         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2257         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2258         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2259
2260         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2261                 .rx_thresh = {
2262                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2263                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2264                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2265                 },
2266                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2267                 .rx_drop_en = 0,
2268                 .offloads = 0,
2269         };
2270
2271         dev_info->default_txconf = (struct rte_eth_txconf) {
2272                 .tx_thresh = {
2273                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2274                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2275                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2276                 },
2277                 .offloads = 0,
2278         };
2279
2280         dev_info->rx_desc_lim = rx_desc_lim;
2281         dev_info->tx_desc_lim = tx_desc_lim;
2282
2283         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2284                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2285                         ETH_LINK_SPEED_1G;
2286
2287         dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2288         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2289
2290         return 0;
2291 }
2292
2293 static const uint32_t *
2294 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2295 {
2296         static const uint32_t ptypes[] = {
2297                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2298                 RTE_PTYPE_L2_ETHER,
2299                 RTE_PTYPE_L3_IPV4,
2300                 RTE_PTYPE_L3_IPV4_EXT,
2301                 RTE_PTYPE_L3_IPV6,
2302                 RTE_PTYPE_L3_IPV6_EXT,
2303                 RTE_PTYPE_L4_TCP,
2304                 RTE_PTYPE_L4_UDP,
2305                 RTE_PTYPE_L4_SCTP,
2306                 RTE_PTYPE_TUNNEL_IP,
2307                 RTE_PTYPE_INNER_L3_IPV6,
2308                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2309                 RTE_PTYPE_INNER_L4_TCP,
2310                 RTE_PTYPE_INNER_L4_UDP,
2311                 RTE_PTYPE_UNKNOWN
2312         };
2313
2314         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2315             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2316                 return ptypes;
2317         return NULL;
2318 }
2319
2320 static int
2321 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2322 {
2323         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2324
2325         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2326         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2327         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2328         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2329                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2330                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2331                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2332                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2333                                 DEV_TX_OFFLOAD_TCP_TSO;
2334         switch (hw->mac.type) {
2335         case e1000_vfadapt:
2336                 dev_info->max_rx_queues = 2;
2337                 dev_info->max_tx_queues = 2;
2338                 break;
2339         case e1000_vfadapt_i350:
2340                 dev_info->max_rx_queues = 1;
2341                 dev_info->max_tx_queues = 1;
2342                 break;
2343         default:
2344                 /* Should not happen */
2345                 return -EINVAL;
2346         }
2347
2348         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2349         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2350                                     dev_info->rx_queue_offload_capa;
2351         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2352         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2353                                     dev_info->tx_queue_offload_capa;
2354
2355         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2356                 .rx_thresh = {
2357                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2358                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2359                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2360                 },
2361                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2362                 .rx_drop_en = 0,
2363                 .offloads = 0,
2364         };
2365
2366         dev_info->default_txconf = (struct rte_eth_txconf) {
2367                 .tx_thresh = {
2368                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2369                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2370                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2371                 },
2372                 .offloads = 0,
2373         };
2374
2375         dev_info->rx_desc_lim = rx_desc_lim;
2376         dev_info->tx_desc_lim = tx_desc_lim;
2377
2378         return 0;
2379 }
2380
2381 /* return 0 means link status changed, -1 means not changed */
2382 static int
2383 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2384 {
2385         struct e1000_hw *hw =
2386                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2387         struct rte_eth_link link;
2388         int link_check, count;
2389
2390         link_check = 0;
2391         hw->mac.get_link_status = 1;
2392
2393         /* possible wait-to-complete in up to 9 seconds */
2394         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2395                 /* Read the real link status */
2396                 switch (hw->phy.media_type) {
2397                 case e1000_media_type_copper:
2398                         /* Do the work to read phy */
2399                         e1000_check_for_link(hw);
2400                         link_check = !hw->mac.get_link_status;
2401                         break;
2402
2403                 case e1000_media_type_fiber:
2404                         e1000_check_for_link(hw);
2405                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2406                                       E1000_STATUS_LU);
2407                         break;
2408
2409                 case e1000_media_type_internal_serdes:
2410                         e1000_check_for_link(hw);
2411                         link_check = hw->mac.serdes_has_link;
2412                         break;
2413
2414                 /* VF device is type_unknown */
2415                 case e1000_media_type_unknown:
2416                         eth_igbvf_link_update(hw);
2417                         link_check = !hw->mac.get_link_status;
2418                         break;
2419
2420                 default:
2421                         break;
2422                 }
2423                 if (link_check || wait_to_complete == 0)
2424                         break;
2425                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2426         }
2427         memset(&link, 0, sizeof(link));
2428
2429         /* Now we check if a transition has happened */
2430         if (link_check) {
2431                 uint16_t duplex, speed;
2432                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2433                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2434                                 ETH_LINK_FULL_DUPLEX :
2435                                 ETH_LINK_HALF_DUPLEX;
2436                 link.link_speed = speed;
2437                 link.link_status = ETH_LINK_UP;
2438                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2439                                 ETH_LINK_SPEED_FIXED);
2440         } else if (!link_check) {
2441                 link.link_speed = 0;
2442                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2443                 link.link_status = ETH_LINK_DOWN;
2444                 link.link_autoneg = ETH_LINK_FIXED;
2445         }
2446
2447         return rte_eth_linkstatus_set(dev, &link);
2448 }
2449
2450 /*
2451  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2452  * For ASF and Pass Through versions of f/w this means
2453  * that the driver is loaded.
2454  */
2455 static void
2456 igb_hw_control_acquire(struct e1000_hw *hw)
2457 {
2458         uint32_t ctrl_ext;
2459
2460         /* Let firmware know the driver has taken over */
2461         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2462         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2463 }
2464
2465 /*
2466  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2467  * For ASF and Pass Through versions of f/w this means that the
2468  * driver is no longer loaded.
2469  */
2470 static void
2471 igb_hw_control_release(struct e1000_hw *hw)
2472 {
2473         uint32_t ctrl_ext;
2474
2475         /* Let firmware taken over control of h/w */
2476         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2477         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2478                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2479 }
2480
2481 /*
2482  * Bit of a misnomer, what this really means is
2483  * to enable OS management of the system... aka
2484  * to disable special hardware management features.
2485  */
2486 static void
2487 igb_init_manageability(struct e1000_hw *hw)
2488 {
2489         if (e1000_enable_mng_pass_thru(hw)) {
2490                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2491                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2492
2493                 /* disable hardware interception of ARP */
2494                 manc &= ~(E1000_MANC_ARP_EN);
2495
2496                 /* enable receiving management packets to the host */
2497                 manc |= E1000_MANC_EN_MNG2HOST;
2498                 manc2h |= 1 << 5;  /* Mng Port 623 */
2499                 manc2h |= 1 << 6;  /* Mng Port 664 */
2500                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2501                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2502         }
2503 }
2504
2505 static void
2506 igb_release_manageability(struct e1000_hw *hw)
2507 {
2508         if (e1000_enable_mng_pass_thru(hw)) {
2509                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2510
2511                 manc |= E1000_MANC_ARP_EN;
2512                 manc &= ~E1000_MANC_EN_MNG2HOST;
2513
2514                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2515         }
2516 }
2517
2518 static int
2519 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2520 {
2521         struct e1000_hw *hw =
2522                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523         uint32_t rctl;
2524
2525         rctl = E1000_READ_REG(hw, E1000_RCTL);
2526         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2527         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2528
2529         return 0;
2530 }
2531
2532 static int
2533 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2534 {
2535         struct e1000_hw *hw =
2536                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2537         uint32_t rctl;
2538
2539         rctl = E1000_READ_REG(hw, E1000_RCTL);
2540         rctl &= (~E1000_RCTL_UPE);
2541         if (dev->data->all_multicast == 1)
2542                 rctl |= E1000_RCTL_MPE;
2543         else
2544                 rctl &= (~E1000_RCTL_MPE);
2545         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2546
2547         return 0;
2548 }
2549
2550 static int
2551 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2552 {
2553         struct e1000_hw *hw =
2554                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2555         uint32_t rctl;
2556
2557         rctl = E1000_READ_REG(hw, E1000_RCTL);
2558         rctl |= E1000_RCTL_MPE;
2559         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2560
2561         return 0;
2562 }
2563
2564 static int
2565 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2566 {
2567         struct e1000_hw *hw =
2568                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2569         uint32_t rctl;
2570
2571         if (dev->data->promiscuous == 1)
2572                 return 0; /* must remain in all_multicast mode */
2573         rctl = E1000_READ_REG(hw, E1000_RCTL);
2574         rctl &= (~E1000_RCTL_MPE);
2575         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2576
2577         return 0;
2578 }
2579
2580 static int
2581 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2582 {
2583         struct e1000_hw *hw =
2584                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2585         struct e1000_vfta * shadow_vfta =
2586                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2587         uint32_t vfta;
2588         uint32_t vid_idx;
2589         uint32_t vid_bit;
2590
2591         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2592                               E1000_VFTA_ENTRY_MASK);
2593         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2594         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2595         if (on)
2596                 vfta |= vid_bit;
2597         else
2598                 vfta &= ~vid_bit;
2599         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2600
2601         /* update local VFTA copy */
2602         shadow_vfta->vfta[vid_idx] = vfta;
2603
2604         return 0;
2605 }
2606
2607 static int
2608 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2609                       enum rte_vlan_type vlan_type,
2610                       uint16_t tpid)
2611 {
2612         struct e1000_hw *hw =
2613                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2614         uint32_t reg, qinq;
2615
2616         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2617         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2618
2619         /* only outer TPID of double VLAN can be configured*/
2620         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2621                 reg = E1000_READ_REG(hw, E1000_VET);
2622                 reg = (reg & (~E1000_VET_VET_EXT)) |
2623                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2624                 E1000_WRITE_REG(hw, E1000_VET, reg);
2625
2626                 return 0;
2627         }
2628
2629         /* all other TPID values are read-only*/
2630         PMD_DRV_LOG(ERR, "Not supported");
2631
2632         return -ENOTSUP;
2633 }
2634
2635 static void
2636 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2637 {
2638         struct e1000_hw *hw =
2639                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640         uint32_t reg;
2641
2642         /* Filter Table Disable */
2643         reg = E1000_READ_REG(hw, E1000_RCTL);
2644         reg &= ~E1000_RCTL_CFIEN;
2645         reg &= ~E1000_RCTL_VFE;
2646         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2647 }
2648
2649 static void
2650 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2651 {
2652         struct e1000_hw *hw =
2653                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2654         struct e1000_vfta * shadow_vfta =
2655                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2656         uint32_t reg;
2657         int i;
2658
2659         /* Filter Table Enable, CFI not used for packet acceptance */
2660         reg = E1000_READ_REG(hw, E1000_RCTL);
2661         reg &= ~E1000_RCTL_CFIEN;
2662         reg |= E1000_RCTL_VFE;
2663         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2664
2665         /* restore VFTA table */
2666         for (i = 0; i < IGB_VFTA_SIZE; i++)
2667                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2668 }
2669
2670 static void
2671 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2672 {
2673         struct e1000_hw *hw =
2674                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2675         uint32_t reg;
2676
2677         /* VLAN Mode Disable */
2678         reg = E1000_READ_REG(hw, E1000_CTRL);
2679         reg &= ~E1000_CTRL_VME;
2680         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2681 }
2682
2683 static void
2684 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2685 {
2686         struct e1000_hw *hw =
2687                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2688         uint32_t reg;
2689
2690         /* VLAN Mode Enable */
2691         reg = E1000_READ_REG(hw, E1000_CTRL);
2692         reg |= E1000_CTRL_VME;
2693         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2694 }
2695
2696 static void
2697 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2698 {
2699         struct e1000_hw *hw =
2700                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2701         uint32_t reg;
2702
2703         /* CTRL_EXT: Extended VLAN */
2704         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2705         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2706         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2707
2708         /* Update maximum packet length */
2709         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2710                 E1000_WRITE_REG(hw, E1000_RLPML,
2711                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2712                                                 VLAN_TAG_SIZE);
2713 }
2714
2715 static void
2716 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2717 {
2718         struct e1000_hw *hw =
2719                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2720         uint32_t reg;
2721
2722         /* CTRL_EXT: Extended VLAN */
2723         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2724         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2725         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2726
2727         /* Update maximum packet length */
2728         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2729                 E1000_WRITE_REG(hw, E1000_RLPML,
2730                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2731                                                 2 * VLAN_TAG_SIZE);
2732 }
2733
2734 static int
2735 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2736 {
2737         struct rte_eth_rxmode *rxmode;
2738
2739         rxmode = &dev->data->dev_conf.rxmode;
2740         if(mask & ETH_VLAN_STRIP_MASK){
2741                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2742                         igb_vlan_hw_strip_enable(dev);
2743                 else
2744                         igb_vlan_hw_strip_disable(dev);
2745         }
2746
2747         if(mask & ETH_VLAN_FILTER_MASK){
2748                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2749                         igb_vlan_hw_filter_enable(dev);
2750                 else
2751                         igb_vlan_hw_filter_disable(dev);
2752         }
2753
2754         if(mask & ETH_VLAN_EXTEND_MASK){
2755                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2756                         igb_vlan_hw_extend_enable(dev);
2757                 else
2758                         igb_vlan_hw_extend_disable(dev);
2759         }
2760
2761         return 0;
2762 }
2763
2764
2765 /**
2766  * It enables the interrupt mask and then enable the interrupt.
2767  *
2768  * @param dev
2769  *  Pointer to struct rte_eth_dev.
2770  * @param on
2771  *  Enable or Disable
2772  *
2773  * @return
2774  *  - On success, zero.
2775  *  - On failure, a negative value.
2776  */
2777 static int
2778 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2779 {
2780         struct e1000_interrupt *intr =
2781                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2782
2783         if (on)
2784                 intr->mask |= E1000_ICR_LSC;
2785         else
2786                 intr->mask &= ~E1000_ICR_LSC;
2787
2788         return 0;
2789 }
2790
2791 /* It clears the interrupt causes and enables the interrupt.
2792  * It will be called once only during nic initialized.
2793  *
2794  * @param dev
2795  *  Pointer to struct rte_eth_dev.
2796  *
2797  * @return
2798  *  - On success, zero.
2799  *  - On failure, a negative value.
2800  */
2801 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2802 {
2803         uint32_t mask, regval;
2804         int ret;
2805         struct e1000_hw *hw =
2806                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2808         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2809         int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2810         struct rte_eth_dev_info dev_info;
2811
2812         memset(&dev_info, 0, sizeof(dev_info));
2813         ret = eth_igb_infos_get(dev, &dev_info);
2814         if (ret != 0)
2815                 return ret;
2816
2817         mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2818         regval = E1000_READ_REG(hw, E1000_EIMS);
2819         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2820
2821         return 0;
2822 }
2823
2824 /*
2825  * It reads ICR and gets interrupt causes, check it and set a bit flag
2826  * to update link status.
2827  *
2828  * @param dev
2829  *  Pointer to struct rte_eth_dev.
2830  *
2831  * @return
2832  *  - On success, zero.
2833  *  - On failure, a negative value.
2834  */
2835 static int
2836 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2837 {
2838         uint32_t icr;
2839         struct e1000_hw *hw =
2840                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2841         struct e1000_interrupt *intr =
2842                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2843
2844         igb_intr_disable(dev);
2845
2846         /* read-on-clear nic registers here */
2847         icr = E1000_READ_REG(hw, E1000_ICR);
2848
2849         intr->flags = 0;
2850         if (icr & E1000_ICR_LSC) {
2851                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2852         }
2853
2854         if (icr & E1000_ICR_VMMB)
2855                 intr->flags |= E1000_FLAG_MAILBOX;
2856
2857         return 0;
2858 }
2859
2860 /*
2861  * It executes link_update after knowing an interrupt is prsent.
2862  *
2863  * @param dev
2864  *  Pointer to struct rte_eth_dev.
2865  *
2866  * @return
2867  *  - On success, zero.
2868  *  - On failure, a negative value.
2869  */
2870 static int
2871 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2872                          struct rte_intr_handle *intr_handle)
2873 {
2874         struct e1000_hw *hw =
2875                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876         struct e1000_interrupt *intr =
2877                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2878         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2879         struct rte_eth_link link;
2880         int ret;
2881
2882         if (intr->flags & E1000_FLAG_MAILBOX) {
2883                 igb_pf_mbx_process(dev);
2884                 intr->flags &= ~E1000_FLAG_MAILBOX;
2885         }
2886
2887         igb_intr_enable(dev);
2888         rte_intr_ack(intr_handle);
2889
2890         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2891                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2892
2893                 /* set get_link_status to check register later */
2894                 hw->mac.get_link_status = 1;
2895                 ret = eth_igb_link_update(dev, 0);
2896
2897                 /* check if link has changed */
2898                 if (ret < 0)
2899                         return 0;
2900
2901                 rte_eth_linkstatus_get(dev, &link);
2902                 if (link.link_status) {
2903                         PMD_INIT_LOG(INFO,
2904                                      " Port %d: Link Up - speed %u Mbps - %s",
2905                                      dev->data->port_id,
2906                                      (unsigned)link.link_speed,
2907                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2908                                      "full-duplex" : "half-duplex");
2909                 } else {
2910                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2911                                      dev->data->port_id);
2912                 }
2913
2914                 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2915                              pci_dev->addr.domain,
2916                              pci_dev->addr.bus,
2917                              pci_dev->addr.devid,
2918                              pci_dev->addr.function);
2919                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2920         }
2921
2922         return 0;
2923 }
2924
2925 /**
2926  * Interrupt handler which shall be registered at first.
2927  *
2928  * @param handle
2929  *  Pointer to interrupt handle.
2930  * @param param
2931  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2932  *
2933  * @return
2934  *  void
2935  */
2936 static void
2937 eth_igb_interrupt_handler(void *param)
2938 {
2939         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2940
2941         eth_igb_interrupt_get_status(dev);
2942         eth_igb_interrupt_action(dev, dev->intr_handle);
2943 }
2944
2945 static int
2946 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2947 {
2948         uint32_t eicr;
2949         struct e1000_hw *hw =
2950                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2951         struct e1000_interrupt *intr =
2952                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2953
2954         igbvf_intr_disable(hw);
2955
2956         /* read-on-clear nic registers here */
2957         eicr = E1000_READ_REG(hw, E1000_EICR);
2958         intr->flags = 0;
2959
2960         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2961                 intr->flags |= E1000_FLAG_MAILBOX;
2962
2963         return 0;
2964 }
2965
2966 void igbvf_mbx_process(struct rte_eth_dev *dev)
2967 {
2968         struct e1000_hw *hw =
2969                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2970         struct e1000_mbx_info *mbx = &hw->mbx;
2971         u32 in_msg = 0;
2972
2973         /* peek the message first */
2974         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2975
2976         /* PF reset VF event */
2977         if (in_msg == E1000_PF_CONTROL_MSG) {
2978                 /* dummy mbx read to ack pf */
2979                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2980                         return;
2981                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2982                                              NULL);
2983         }
2984 }
2985
2986 static int
2987 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2988 {
2989         struct e1000_interrupt *intr =
2990                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2991
2992         if (intr->flags & E1000_FLAG_MAILBOX) {
2993                 igbvf_mbx_process(dev);
2994                 intr->flags &= ~E1000_FLAG_MAILBOX;
2995         }
2996
2997         igbvf_intr_enable(dev);
2998         rte_intr_ack(intr_handle);
2999
3000         return 0;
3001 }
3002
3003 static void
3004 eth_igbvf_interrupt_handler(void *param)
3005 {
3006         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3007
3008         eth_igbvf_interrupt_get_status(dev);
3009         eth_igbvf_interrupt_action(dev, dev->intr_handle);
3010 }
3011
3012 static int
3013 eth_igb_led_on(struct rte_eth_dev *dev)
3014 {
3015         struct e1000_hw *hw;
3016
3017         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3018         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3019 }
3020
3021 static int
3022 eth_igb_led_off(struct rte_eth_dev *dev)
3023 {
3024         struct e1000_hw *hw;
3025
3026         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3027         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3028 }
3029
3030 static int
3031 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3032 {
3033         struct e1000_hw *hw;
3034         uint32_t ctrl;
3035         int tx_pause;
3036         int rx_pause;
3037
3038         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3039         fc_conf->pause_time = hw->fc.pause_time;
3040         fc_conf->high_water = hw->fc.high_water;
3041         fc_conf->low_water = hw->fc.low_water;
3042         fc_conf->send_xon = hw->fc.send_xon;
3043         fc_conf->autoneg = hw->mac.autoneg;
3044
3045         /*
3046          * Return rx_pause and tx_pause status according to actual setting of
3047          * the TFCE and RFCE bits in the CTRL register.
3048          */
3049         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3050         if (ctrl & E1000_CTRL_TFCE)
3051                 tx_pause = 1;
3052         else
3053                 tx_pause = 0;
3054
3055         if (ctrl & E1000_CTRL_RFCE)
3056                 rx_pause = 1;
3057         else
3058                 rx_pause = 0;
3059
3060         if (rx_pause && tx_pause)
3061                 fc_conf->mode = RTE_FC_FULL;
3062         else if (rx_pause)
3063                 fc_conf->mode = RTE_FC_RX_PAUSE;
3064         else if (tx_pause)
3065                 fc_conf->mode = RTE_FC_TX_PAUSE;
3066         else
3067                 fc_conf->mode = RTE_FC_NONE;
3068
3069         return 0;
3070 }
3071
3072 static int
3073 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3074 {
3075         struct e1000_hw *hw;
3076         int err;
3077         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3078                 e1000_fc_none,
3079                 e1000_fc_rx_pause,
3080                 e1000_fc_tx_pause,
3081                 e1000_fc_full
3082         };
3083         uint32_t rx_buf_size;
3084         uint32_t max_high_water;
3085         uint32_t rctl;
3086
3087         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3088         if (fc_conf->autoneg != hw->mac.autoneg)
3089                 return -ENOTSUP;
3090         rx_buf_size = igb_get_rx_buffer_size(hw);
3091         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3092
3093         /* At least reserve one Ethernet frame for watermark */
3094         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3095         if ((fc_conf->high_water > max_high_water) ||
3096             (fc_conf->high_water < fc_conf->low_water)) {
3097                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3098                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3099                 return -EINVAL;
3100         }
3101
3102         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3103         hw->fc.pause_time     = fc_conf->pause_time;
3104         hw->fc.high_water     = fc_conf->high_water;
3105         hw->fc.low_water      = fc_conf->low_water;
3106         hw->fc.send_xon       = fc_conf->send_xon;
3107
3108         err = e1000_setup_link_generic(hw);
3109         if (err == E1000_SUCCESS) {
3110
3111                 /* check if we want to forward MAC frames - driver doesn't have native
3112                  * capability to do that, so we'll write the registers ourselves */
3113
3114                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3115
3116                 /* set or clear MFLCN.PMCF bit depending on configuration */
3117                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3118                         rctl |= E1000_RCTL_PMCF;
3119                 else
3120                         rctl &= ~E1000_RCTL_PMCF;
3121
3122                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3123                 E1000_WRITE_FLUSH(hw);
3124
3125                 return 0;
3126         }
3127
3128         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3129         return -EIO;
3130 }
3131
3132 #define E1000_RAH_POOLSEL_SHIFT      (18)
3133 static int
3134 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3135                 uint32_t index, uint32_t pool)
3136 {
3137         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3138         uint32_t rah;
3139
3140         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3141         rah = E1000_READ_REG(hw, E1000_RAH(index));
3142         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3143         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3144         return 0;
3145 }
3146
3147 static void
3148 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3149 {
3150         uint8_t addr[RTE_ETHER_ADDR_LEN];
3151         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3152
3153         memset(addr, 0, sizeof(addr));
3154
3155         e1000_rar_set(hw, addr, index);
3156 }
3157
3158 static int
3159 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3160                                 struct rte_ether_addr *addr)
3161 {
3162         eth_igb_rar_clear(dev, 0);
3163         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3164
3165         return 0;
3166 }
3167 /*
3168  * Virtual Function operations
3169  */
3170 static void
3171 igbvf_intr_disable(struct e1000_hw *hw)
3172 {
3173         PMD_INIT_FUNC_TRACE();
3174
3175         /* Clear interrupt mask to stop from interrupts being generated */
3176         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3177
3178         E1000_WRITE_FLUSH(hw);
3179 }
3180
3181 static void
3182 igbvf_stop_adapter(struct rte_eth_dev *dev)
3183 {
3184         u32 reg_val;
3185         u16 i;
3186         struct rte_eth_dev_info dev_info;
3187         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3188         int ret;
3189
3190         memset(&dev_info, 0, sizeof(dev_info));
3191         ret = eth_igbvf_infos_get(dev, &dev_info);
3192         if (ret != 0)
3193                 return;
3194
3195         /* Clear interrupt mask to stop from interrupts being generated */
3196         igbvf_intr_disable(hw);
3197
3198         /* Clear any pending interrupts, flush previous writes */
3199         E1000_READ_REG(hw, E1000_EICR);
3200
3201         /* Disable the transmit unit.  Each queue must be disabled. */
3202         for (i = 0; i < dev_info.max_tx_queues; i++)
3203                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3204
3205         /* Disable the receive unit by stopping each queue */
3206         for (i = 0; i < dev_info.max_rx_queues; i++) {
3207                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3208                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3209                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3210                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3211                         ;
3212         }
3213
3214         /* flush all queues disables */
3215         E1000_WRITE_FLUSH(hw);
3216         msec_delay(2);
3217 }
3218
3219 static int eth_igbvf_link_update(struct e1000_hw *hw)
3220 {
3221         struct e1000_mbx_info *mbx = &hw->mbx;
3222         struct e1000_mac_info *mac = &hw->mac;
3223         int ret_val = E1000_SUCCESS;
3224
3225         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3226
3227         /*
3228          * We only want to run this if there has been a rst asserted.
3229          * in this case that could mean a link change, device reset,
3230          * or a virtual function reset
3231          */
3232
3233         /* If we were hit with a reset or timeout drop the link */
3234         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3235                 mac->get_link_status = TRUE;
3236
3237         if (!mac->get_link_status)
3238                 goto out;
3239
3240         /* if link status is down no point in checking to see if pf is up */
3241         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3242                 goto out;
3243
3244         /* if we passed all the tests above then the link is up and we no
3245          * longer need to check for link */
3246         mac->get_link_status = FALSE;
3247
3248 out:
3249         return ret_val;
3250 }
3251
3252
3253 static int
3254 igbvf_dev_configure(struct rte_eth_dev *dev)
3255 {
3256         struct rte_eth_conf* conf = &dev->data->dev_conf;
3257
3258         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3259                      dev->data->port_id);
3260
3261         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3262                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3263
3264         /*
3265          * VF has no ability to enable/disable HW CRC
3266          * Keep the persistent behavior the same as Host PF
3267          */
3268 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3269         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3270                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3271                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3272         }
3273 #else
3274         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3275                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3276                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3277         }
3278 #endif
3279
3280         return 0;
3281 }
3282
3283 static int
3284 igbvf_dev_start(struct rte_eth_dev *dev)
3285 {
3286         struct e1000_hw *hw =
3287                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288         struct e1000_adapter *adapter =
3289                 E1000_DEV_PRIVATE(dev->data->dev_private);
3290         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3291         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3292         int ret;
3293         uint32_t intr_vector = 0;
3294
3295         PMD_INIT_FUNC_TRACE();
3296
3297         hw->mac.ops.reset_hw(hw);
3298         adapter->stopped = 0;
3299
3300         /* Set all vfta */
3301         igbvf_set_vfta_all(dev,1);
3302
3303         eth_igbvf_tx_init(dev);
3304
3305         /* This can fail when allocating mbufs for descriptor rings */
3306         ret = eth_igbvf_rx_init(dev);
3307         if (ret) {
3308                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3309                 igb_dev_clear_queues(dev);
3310                 return ret;
3311         }
3312
3313         /* check and configure queue intr-vector mapping */
3314         if (rte_intr_cap_multiple(intr_handle) &&
3315             dev->data->dev_conf.intr_conf.rxq) {
3316                 intr_vector = dev->data->nb_rx_queues;
3317                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3318                 if (ret)
3319                         return ret;
3320         }
3321
3322         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3323                 intr_handle->intr_vec =
3324                         rte_zmalloc("intr_vec",
3325                                     dev->data->nb_rx_queues * sizeof(int), 0);
3326                 if (!intr_handle->intr_vec) {
3327                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3328                                      " intr_vec", dev->data->nb_rx_queues);
3329                         return -ENOMEM;
3330                 }
3331         }
3332
3333         eth_igbvf_configure_msix_intr(dev);
3334
3335         /* enable uio/vfio intr/eventfd mapping */
3336         rte_intr_enable(intr_handle);
3337
3338         /* resume enabled intr since hw reset */
3339         igbvf_intr_enable(dev);
3340
3341         return 0;
3342 }
3343
3344 static void
3345 igbvf_dev_stop(struct rte_eth_dev *dev)
3346 {
3347         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3348         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3349         struct e1000_adapter *adapter =
3350                 E1000_DEV_PRIVATE(dev->data->dev_private);
3351
3352         if (adapter->stopped)
3353                 return;
3354
3355         PMD_INIT_FUNC_TRACE();
3356
3357         igbvf_stop_adapter(dev);
3358
3359         /*
3360           * Clear what we set, but we still keep shadow_vfta to
3361           * restore after device starts
3362           */
3363         igbvf_set_vfta_all(dev,0);
3364
3365         igb_dev_clear_queues(dev);
3366
3367         /* disable intr eventfd mapping */
3368         rte_intr_disable(intr_handle);
3369
3370         /* Clean datapath event and queue/vec mapping */
3371         rte_intr_efd_disable(intr_handle);
3372         if (intr_handle->intr_vec) {
3373                 rte_free(intr_handle->intr_vec);
3374                 intr_handle->intr_vec = NULL;
3375         }
3376
3377         adapter->stopped = true;
3378         dev->data->dev_started = 0;
3379 }
3380
3381 static int
3382 igbvf_dev_close(struct rte_eth_dev *dev)
3383 {
3384         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3385         struct rte_ether_addr addr;
3386         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3387
3388         PMD_INIT_FUNC_TRACE();
3389
3390         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3391                 return 0;
3392
3393         e1000_reset_hw(hw);
3394
3395         igbvf_dev_stop(dev);
3396
3397         igb_dev_free_queues(dev);
3398
3399         /**
3400          * reprogram the RAR with a zero mac address,
3401          * to ensure that the VF traffic goes to the PF
3402          * after stop, close and detach of the VF.
3403          **/
3404
3405         memset(&addr, 0, sizeof(addr));
3406         igbvf_default_mac_addr_set(dev, &addr);
3407
3408         dev->dev_ops = NULL;
3409         dev->rx_pkt_burst = NULL;
3410         dev->tx_pkt_burst = NULL;
3411
3412         rte_intr_callback_unregister(&pci_dev->intr_handle,
3413                                      eth_igbvf_interrupt_handler,
3414                                      (void *)dev);
3415
3416         return 0;
3417 }
3418
3419 static int
3420 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3421 {
3422         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3423
3424         /* Set both unicast and multicast promisc */
3425         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3426
3427         return 0;
3428 }
3429
3430 static int
3431 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3432 {
3433         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3434
3435         /* If in allmulticast mode leave multicast promisc */
3436         if (dev->data->all_multicast == 1)
3437                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3438         else
3439                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3440
3441         return 0;
3442 }
3443
3444 static int
3445 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3446 {
3447         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3448
3449         /* In promiscuous mode multicast promisc already set */
3450         if (dev->data->promiscuous == 0)
3451                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3452
3453         return 0;
3454 }
3455
3456 static int
3457 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3458 {
3459         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3460
3461         /* In promiscuous mode leave multicast promisc enabled */
3462         if (dev->data->promiscuous == 0)
3463                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3464
3465         return 0;
3466 }
3467
3468 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3469 {
3470         struct e1000_mbx_info *mbx = &hw->mbx;
3471         uint32_t msgbuf[2];
3472         s32 err;
3473
3474         /* After set vlan, vlan strip will also be enabled in igb driver*/
3475         msgbuf[0] = E1000_VF_SET_VLAN;
3476         msgbuf[1] = vid;
3477         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3478         if (on)
3479                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3480
3481         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3482         if (err)
3483                 goto mbx_err;
3484
3485         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3486         if (err)
3487                 goto mbx_err;
3488
3489         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3490         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3491                 err = -EINVAL;
3492
3493 mbx_err:
3494         return err;
3495 }
3496
3497 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3498 {
3499         struct e1000_hw *hw =
3500                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3501         struct e1000_vfta * shadow_vfta =
3502                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3503         int i = 0, j = 0, vfta = 0, mask = 1;
3504
3505         for (i = 0; i < IGB_VFTA_SIZE; i++){
3506                 vfta = shadow_vfta->vfta[i];
3507                 if(vfta){
3508                         mask = 1;
3509                         for (j = 0; j < 32; j++){
3510                                 if(vfta & mask)
3511                                         igbvf_set_vfta(hw,
3512                                                 (uint16_t)((i<<5)+j), on);
3513                                 mask<<=1;
3514                         }
3515                 }
3516         }
3517
3518 }
3519
3520 static int
3521 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3522 {
3523         struct e1000_hw *hw =
3524                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3525         struct e1000_vfta * shadow_vfta =
3526                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3527         uint32_t vid_idx = 0;
3528         uint32_t vid_bit = 0;
3529         int ret = 0;
3530
3531         PMD_INIT_FUNC_TRACE();
3532
3533         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3534         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3535         if(ret){
3536                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3537                 return ret;
3538         }
3539         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3540         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3541
3542         /*Save what we set and retore it after device reset*/
3543         if (on)
3544                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3545         else
3546                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3547
3548         return 0;
3549 }
3550
3551 static int
3552 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3553 {
3554         struct e1000_hw *hw =
3555                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3556
3557         /* index is not used by rar_set() */
3558         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3559         return 0;
3560 }
3561
3562
3563 static int
3564 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3565                         struct rte_eth_rss_reta_entry64 *reta_conf,
3566                         uint16_t reta_size)
3567 {
3568         uint8_t i, j, mask;
3569         uint32_t reta, r;
3570         uint16_t idx, shift;
3571         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3572
3573         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3574                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3575                         "(%d) doesn't match the number hardware can supported "
3576                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3577                 return -EINVAL;
3578         }
3579
3580         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3581                 idx = i / RTE_RETA_GROUP_SIZE;
3582                 shift = i % RTE_RETA_GROUP_SIZE;
3583                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3584                                                 IGB_4_BIT_MASK);
3585                 if (!mask)
3586                         continue;
3587                 if (mask == IGB_4_BIT_MASK)
3588                         r = 0;
3589                 else
3590                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3591                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3592                         if (mask & (0x1 << j))
3593                                 reta |= reta_conf[idx].reta[shift + j] <<
3594                                                         (CHAR_BIT * j);
3595                         else
3596                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3597                 }
3598                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3599         }
3600
3601         return 0;
3602 }
3603
3604 static int
3605 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3606                        struct rte_eth_rss_reta_entry64 *reta_conf,
3607                        uint16_t reta_size)
3608 {
3609         uint8_t i, j, mask;
3610         uint32_t reta;
3611         uint16_t idx, shift;
3612         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3613
3614         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3615                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3616                         "(%d) doesn't match the number hardware can supported "
3617                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3618                 return -EINVAL;
3619         }
3620
3621         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3622                 idx = i / RTE_RETA_GROUP_SIZE;
3623                 shift = i % RTE_RETA_GROUP_SIZE;
3624                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3625                                                 IGB_4_BIT_MASK);
3626                 if (!mask)
3627                         continue;
3628                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3629                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3630                         if (mask & (0x1 << j))
3631                                 reta_conf[idx].reta[shift + j] =
3632                                         ((reta >> (CHAR_BIT * j)) &
3633                                                 IGB_8_BIT_MASK);
3634                 }
3635         }
3636
3637         return 0;
3638 }
3639
3640 int
3641 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3642                         struct rte_eth_syn_filter *filter,
3643                         bool add)
3644 {
3645         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3646         struct e1000_filter_info *filter_info =
3647                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3648         uint32_t synqf, rfctl;
3649
3650         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3651                 return -EINVAL;
3652
3653         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3654
3655         if (add) {
3656                 if (synqf & E1000_SYN_FILTER_ENABLE)
3657                         return -EINVAL;
3658
3659                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3660                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3661
3662                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3663                 if (filter->hig_pri)
3664                         rfctl |= E1000_RFCTL_SYNQFP;
3665                 else
3666                         rfctl &= ~E1000_RFCTL_SYNQFP;
3667
3668                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3669         } else {
3670                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3671                         return -ENOENT;
3672                 synqf = 0;
3673         }
3674
3675         filter_info->syn_info = synqf;
3676         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3677         E1000_WRITE_FLUSH(hw);
3678         return 0;
3679 }
3680
3681 static int
3682 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3683                         struct rte_eth_syn_filter *filter)
3684 {
3685         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3686         uint32_t synqf, rfctl;
3687
3688         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3689         if (synqf & E1000_SYN_FILTER_ENABLE) {
3690                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3691                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3692                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3693                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3694                 return 0;
3695         }
3696
3697         return -ENOENT;
3698 }
3699
3700 static int
3701 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3702                         enum rte_filter_op filter_op,
3703                         void *arg)
3704 {
3705         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3706         int ret;
3707
3708         MAC_TYPE_FILTER_SUP(hw->mac.type);
3709
3710         if (filter_op == RTE_ETH_FILTER_NOP)
3711                 return 0;
3712
3713         if (arg == NULL) {
3714                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3715                             filter_op);
3716                 return -EINVAL;
3717         }
3718
3719         switch (filter_op) {
3720         case RTE_ETH_FILTER_ADD:
3721                 ret = eth_igb_syn_filter_set(dev,
3722                                 (struct rte_eth_syn_filter *)arg,
3723                                 TRUE);
3724                 break;
3725         case RTE_ETH_FILTER_DELETE:
3726                 ret = eth_igb_syn_filter_set(dev,
3727                                 (struct rte_eth_syn_filter *)arg,
3728                                 FALSE);
3729                 break;
3730         case RTE_ETH_FILTER_GET:
3731                 ret = eth_igb_syn_filter_get(dev,
3732                                 (struct rte_eth_syn_filter *)arg);
3733                 break;
3734         default:
3735                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3736                 ret = -EINVAL;
3737                 break;
3738         }
3739
3740         return ret;
3741 }
3742
3743 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3744 static inline int
3745 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3746                         struct e1000_2tuple_filter_info *filter_info)
3747 {
3748         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3749                 return -EINVAL;
3750         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3751                 return -EINVAL;  /* filter index is out of range. */
3752         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3753                 return -EINVAL;  /* flags is invalid. */
3754
3755         switch (filter->dst_port_mask) {
3756         case UINT16_MAX:
3757                 filter_info->dst_port_mask = 0;
3758                 filter_info->dst_port = filter->dst_port;
3759                 break;
3760         case 0:
3761                 filter_info->dst_port_mask = 1;
3762                 break;
3763         default:
3764                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3765                 return -EINVAL;
3766         }
3767
3768         switch (filter->proto_mask) {
3769         case UINT8_MAX:
3770                 filter_info->proto_mask = 0;
3771                 filter_info->proto = filter->proto;
3772                 break;
3773         case 0:
3774                 filter_info->proto_mask = 1;
3775                 break;
3776         default:
3777                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3778                 return -EINVAL;
3779         }
3780
3781         filter_info->priority = (uint8_t)filter->priority;
3782         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3783                 filter_info->tcp_flags = filter->tcp_flags;
3784         else
3785                 filter_info->tcp_flags = 0;
3786
3787         return 0;
3788 }
3789
3790 static inline struct e1000_2tuple_filter *
3791 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3792                         struct e1000_2tuple_filter_info *key)
3793 {
3794         struct e1000_2tuple_filter *it;
3795
3796         TAILQ_FOREACH(it, filter_list, entries) {
3797                 if (memcmp(key, &it->filter_info,
3798                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3799                         return it;
3800                 }
3801         }
3802         return NULL;
3803 }
3804
3805 /* inject a igb 2tuple filter to HW */
3806 static inline void
3807 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3808                            struct e1000_2tuple_filter *filter)
3809 {
3810         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3811         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3812         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3813         int i;
3814
3815         i = filter->index;
3816         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3817         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3818                 imir |= E1000_IMIR_PORT_BP;
3819         else
3820                 imir &= ~E1000_IMIR_PORT_BP;
3821
3822         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3823
3824         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3825         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3826         ttqf |= (uint32_t)(filter->filter_info.proto &
3827                                                 E1000_TTQF_PROTOCOL_MASK);
3828         if (filter->filter_info.proto_mask == 0)
3829                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3830
3831         /* tcp flags bits setting. */
3832         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3833                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3834                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3835                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3836                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3837                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3838                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3839                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3840                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3841                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3842                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3843                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3844                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3845         } else {
3846                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3847         }
3848         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3849         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3850         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3851 }
3852
3853 /*
3854  * igb_add_2tuple_filter - add a 2tuple filter
3855  *
3856  * @param
3857  * dev: Pointer to struct rte_eth_dev.
3858  * ntuple_filter: ponter to the filter that will be added.
3859  *
3860  * @return
3861  *    - On success, zero.
3862  *    - On failure, a negative value.
3863  */
3864 static int
3865 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3866                         struct rte_eth_ntuple_filter *ntuple_filter)
3867 {
3868         struct e1000_filter_info *filter_info =
3869                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3870         struct e1000_2tuple_filter *filter;
3871         int i, ret;
3872
3873         filter = rte_zmalloc("e1000_2tuple_filter",
3874                         sizeof(struct e1000_2tuple_filter), 0);
3875         if (filter == NULL)
3876                 return -ENOMEM;
3877
3878         ret = ntuple_filter_to_2tuple(ntuple_filter,
3879                                       &filter->filter_info);
3880         if (ret < 0) {
3881                 rte_free(filter);
3882                 return ret;
3883         }
3884         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3885                                          &filter->filter_info) != NULL) {
3886                 PMD_DRV_LOG(ERR, "filter exists.");
3887                 rte_free(filter);
3888                 return -EEXIST;
3889         }
3890         filter->queue = ntuple_filter->queue;
3891
3892         /*
3893          * look for an unused 2tuple filter index,
3894          * and insert the filter to list.
3895          */
3896         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3897                 if (!(filter_info->twotuple_mask & (1 << i))) {
3898                         filter_info->twotuple_mask |= 1 << i;
3899                         filter->index = i;
3900                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3901                                           filter,
3902                                           entries);
3903                         break;
3904                 }
3905         }
3906         if (i >= E1000_MAX_TTQF_FILTERS) {
3907                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3908                 rte_free(filter);
3909                 return -ENOSYS;
3910         }
3911
3912         igb_inject_2uple_filter(dev, filter);
3913         return 0;
3914 }
3915
3916 int
3917 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3918                         struct e1000_2tuple_filter *filter)
3919 {
3920         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3921         struct e1000_filter_info *filter_info =
3922                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3923
3924         filter_info->twotuple_mask &= ~(1 << filter->index);
3925         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3926         rte_free(filter);
3927
3928         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3929         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3930         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3931         return 0;
3932 }
3933
3934 /*
3935  * igb_remove_2tuple_filter - remove a 2tuple filter
3936  *
3937  * @param
3938  * dev: Pointer to struct rte_eth_dev.
3939  * ntuple_filter: ponter to the filter that will be removed.
3940  *
3941  * @return
3942  *    - On success, zero.
3943  *    - On failure, a negative value.
3944  */
3945 static int
3946 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3947                         struct rte_eth_ntuple_filter *ntuple_filter)
3948 {
3949         struct e1000_filter_info *filter_info =
3950                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3951         struct e1000_2tuple_filter_info filter_2tuple;
3952         struct e1000_2tuple_filter *filter;
3953         int ret;
3954
3955         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3956         ret = ntuple_filter_to_2tuple(ntuple_filter,
3957                                       &filter_2tuple);
3958         if (ret < 0)
3959                 return ret;
3960
3961         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3962                                          &filter_2tuple);
3963         if (filter == NULL) {
3964                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3965                 return -ENOENT;
3966         }
3967
3968         igb_delete_2tuple_filter(dev, filter);
3969
3970         return 0;
3971 }
3972
3973 /* inject a igb flex filter to HW */
3974 static inline void
3975 igb_inject_flex_filter(struct rte_eth_dev *dev,
3976                            struct e1000_flex_filter *filter)
3977 {
3978         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3979         uint32_t wufc, queueing;
3980         uint32_t reg_off;
3981         uint8_t i, j = 0;
3982
3983         wufc = E1000_READ_REG(hw, E1000_WUFC);
3984         if (filter->index < E1000_MAX_FHFT)
3985                 reg_off = E1000_FHFT(filter->index);
3986         else
3987                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3988
3989         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3990                         (E1000_WUFC_FLX0 << filter->index));
3991         queueing = filter->filter_info.len |
3992                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3993                 (filter->filter_info.priority <<
3994                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3995         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3996                         queueing);
3997
3998         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3999                 E1000_WRITE_REG(hw, reg_off,
4000                                 filter->filter_info.dwords[j]);
4001                 reg_off += sizeof(uint32_t);
4002                 E1000_WRITE_REG(hw, reg_off,
4003                                 filter->filter_info.dwords[++j]);
4004                 reg_off += sizeof(uint32_t);
4005                 E1000_WRITE_REG(hw, reg_off,
4006                         (uint32_t)filter->filter_info.mask[i]);
4007                 reg_off += sizeof(uint32_t) * 2;
4008                 ++j;
4009         }
4010 }
4011
4012 static inline struct e1000_flex_filter *
4013 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
4014                         struct e1000_flex_filter_info *key)
4015 {
4016         struct e1000_flex_filter *it;
4017
4018         TAILQ_FOREACH(it, filter_list, entries) {
4019                 if (memcmp(key, &it->filter_info,
4020                         sizeof(struct e1000_flex_filter_info)) == 0)
4021                         return it;
4022         }
4023
4024         return NULL;
4025 }
4026
4027 /* remove a flex byte filter
4028  * @param
4029  * dev: Pointer to struct rte_eth_dev.
4030  * filter: the pointer of the filter will be removed.
4031  */
4032 void
4033 igb_remove_flex_filter(struct rte_eth_dev *dev,
4034                         struct e1000_flex_filter *filter)
4035 {
4036         struct e1000_filter_info *filter_info =
4037                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4038         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4039         uint32_t wufc, i;
4040         uint32_t reg_off;
4041
4042         wufc = E1000_READ_REG(hw, E1000_WUFC);
4043         if (filter->index < E1000_MAX_FHFT)
4044                 reg_off = E1000_FHFT(filter->index);
4045         else
4046                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4047
4048         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4049                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4050
4051         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4052                 (~(E1000_WUFC_FLX0 << filter->index)));
4053
4054         filter_info->flex_mask &= ~(1 << filter->index);
4055         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4056         rte_free(filter);
4057 }
4058
4059 int
4060 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4061                         struct rte_eth_flex_filter *filter,
4062                         bool add)
4063 {
4064         struct e1000_filter_info *filter_info =
4065                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4066         struct e1000_flex_filter *flex_filter, *it;
4067         uint32_t mask;
4068         uint8_t shift, i;
4069
4070         flex_filter = rte_zmalloc("e1000_flex_filter",
4071                         sizeof(struct e1000_flex_filter), 0);
4072         if (flex_filter == NULL)
4073                 return -ENOMEM;
4074
4075         flex_filter->filter_info.len = filter->len;
4076         flex_filter->filter_info.priority = filter->priority;
4077         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4078         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4079                 mask = 0;
4080                 /* reverse bits in flex filter's mask*/
4081                 for (shift = 0; shift < CHAR_BIT; shift++) {
4082                         if (filter->mask[i] & (0x01 << shift))
4083                                 mask |= (0x80 >> shift);
4084                 }
4085                 flex_filter->filter_info.mask[i] = mask;
4086         }
4087
4088         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4089                                 &flex_filter->filter_info);
4090         if (it == NULL && !add) {
4091                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4092                 rte_free(flex_filter);
4093                 return -ENOENT;
4094         }
4095         if (it != NULL && add) {
4096                 PMD_DRV_LOG(ERR, "filter exists.");
4097                 rte_free(flex_filter);
4098                 return -EEXIST;
4099         }
4100
4101         if (add) {
4102                 flex_filter->queue = filter->queue;
4103                 /*
4104                  * look for an unused flex filter index
4105                  * and insert the filter into the list.
4106                  */
4107                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4108                         if (!(filter_info->flex_mask & (1 << i))) {
4109                                 filter_info->flex_mask |= 1 << i;
4110                                 flex_filter->index = i;
4111                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4112                                         flex_filter,
4113                                         entries);
4114                                 break;
4115                         }
4116                 }
4117                 if (i >= E1000_MAX_FLEX_FILTERS) {
4118                         PMD_DRV_LOG(ERR, "flex filters are full.");
4119                         rte_free(flex_filter);
4120                         return -ENOSYS;
4121                 }
4122
4123                 igb_inject_flex_filter(dev, flex_filter);
4124
4125         } else {
4126                 igb_remove_flex_filter(dev, it);
4127                 rte_free(flex_filter);
4128         }
4129
4130         return 0;
4131 }
4132
4133 static int
4134 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4135                         struct rte_eth_flex_filter *filter)
4136 {
4137         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4138         struct e1000_filter_info *filter_info =
4139                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4140         struct e1000_flex_filter flex_filter, *it;
4141         uint32_t wufc, queueing, wufc_en = 0;
4142
4143         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4144         flex_filter.filter_info.len = filter->len;
4145         flex_filter.filter_info.priority = filter->priority;
4146         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4147         memcpy(flex_filter.filter_info.mask, filter->mask,
4148                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4149
4150         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4151                                 &flex_filter.filter_info);
4152         if (it == NULL) {
4153                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4154                 return -ENOENT;
4155         }
4156
4157         wufc = E1000_READ_REG(hw, E1000_WUFC);
4158         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4159
4160         if ((wufc & wufc_en) == wufc_en) {
4161                 uint32_t reg_off = 0;
4162                 if (it->index < E1000_MAX_FHFT)
4163                         reg_off = E1000_FHFT(it->index);
4164                 else
4165                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4166
4167                 queueing = E1000_READ_REG(hw,
4168                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4169                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4170                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4171                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4172                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4173                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4174                 return 0;
4175         }
4176         return -ENOENT;
4177 }
4178
4179 static int
4180 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4181                         enum rte_filter_op filter_op,
4182                         void *arg)
4183 {
4184         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4185         struct rte_eth_flex_filter *filter;
4186         int ret = 0;
4187
4188         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4189
4190         if (filter_op == RTE_ETH_FILTER_NOP)
4191                 return ret;
4192
4193         if (arg == NULL) {
4194                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4195                             filter_op);
4196                 return -EINVAL;
4197         }
4198
4199         filter = (struct rte_eth_flex_filter *)arg;
4200         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4201             || filter->len % sizeof(uint64_t) != 0) {
4202                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4203                 return -EINVAL;
4204         }
4205         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4206                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4207                 return -EINVAL;
4208         }
4209
4210         switch (filter_op) {
4211         case RTE_ETH_FILTER_ADD:
4212                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4213                 break;
4214         case RTE_ETH_FILTER_DELETE:
4215                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4216                 break;
4217         case RTE_ETH_FILTER_GET:
4218                 ret = eth_igb_get_flex_filter(dev, filter);
4219                 break;
4220         default:
4221                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4222                 ret = -EINVAL;
4223                 break;
4224         }
4225
4226         return ret;
4227 }
4228
4229 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4230 static inline int
4231 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4232                         struct e1000_5tuple_filter_info *filter_info)
4233 {
4234         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4235                 return -EINVAL;
4236         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4237                 return -EINVAL;  /* filter index is out of range. */
4238         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4239                 return -EINVAL;  /* flags is invalid. */
4240
4241         switch (filter->dst_ip_mask) {
4242         case UINT32_MAX:
4243                 filter_info->dst_ip_mask = 0;
4244                 filter_info->dst_ip = filter->dst_ip;
4245                 break;
4246         case 0:
4247                 filter_info->dst_ip_mask = 1;
4248                 break;
4249         default:
4250                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4251                 return -EINVAL;
4252         }
4253
4254         switch (filter->src_ip_mask) {
4255         case UINT32_MAX:
4256                 filter_info->src_ip_mask = 0;
4257                 filter_info->src_ip = filter->src_ip;
4258                 break;
4259         case 0:
4260                 filter_info->src_ip_mask = 1;
4261                 break;
4262         default:
4263                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4264                 return -EINVAL;
4265         }
4266
4267         switch (filter->dst_port_mask) {
4268         case UINT16_MAX:
4269                 filter_info->dst_port_mask = 0;
4270                 filter_info->dst_port = filter->dst_port;
4271                 break;
4272         case 0:
4273                 filter_info->dst_port_mask = 1;
4274                 break;
4275         default:
4276                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4277                 return -EINVAL;
4278         }
4279
4280         switch (filter->src_port_mask) {
4281         case UINT16_MAX:
4282                 filter_info->src_port_mask = 0;
4283                 filter_info->src_port = filter->src_port;
4284                 break;
4285         case 0:
4286                 filter_info->src_port_mask = 1;
4287                 break;
4288         default:
4289                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4290                 return -EINVAL;
4291         }
4292
4293         switch (filter->proto_mask) {
4294         case UINT8_MAX:
4295                 filter_info->proto_mask = 0;
4296                 filter_info->proto = filter->proto;
4297                 break;
4298         case 0:
4299                 filter_info->proto_mask = 1;
4300                 break;
4301         default:
4302                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4303                 return -EINVAL;
4304         }
4305
4306         filter_info->priority = (uint8_t)filter->priority;
4307         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4308                 filter_info->tcp_flags = filter->tcp_flags;
4309         else
4310                 filter_info->tcp_flags = 0;
4311
4312         return 0;
4313 }
4314
4315 static inline struct e1000_5tuple_filter *
4316 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4317                         struct e1000_5tuple_filter_info *key)
4318 {
4319         struct e1000_5tuple_filter *it;
4320
4321         TAILQ_FOREACH(it, filter_list, entries) {
4322                 if (memcmp(key, &it->filter_info,
4323                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4324                         return it;
4325                 }
4326         }
4327         return NULL;
4328 }
4329
4330 /* inject a igb 5-tuple filter to HW */
4331 static inline void
4332 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4333                            struct e1000_5tuple_filter *filter)
4334 {
4335         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4336         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4337         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4338         uint8_t i;
4339
4340         i = filter->index;
4341         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4342         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4343                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4344         if (filter->filter_info.dst_ip_mask == 0)
4345                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4346         if (filter->filter_info.src_port_mask == 0)
4347                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4348         if (filter->filter_info.proto_mask == 0)
4349                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4350         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4351                 E1000_FTQF_QUEUE_MASK;
4352         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4353         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4354         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4355         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4356
4357         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4358         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4359
4360         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4361         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4362                 imir |= E1000_IMIR_PORT_BP;
4363         else
4364                 imir &= ~E1000_IMIR_PORT_BP;
4365         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4366
4367         /* tcp flags bits setting. */
4368         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4369                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4370                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4371                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4372                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4373                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4374                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4375                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4376                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4377                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4378                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4379                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4380                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4381         } else {
4382                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4383         }
4384         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4385         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4386 }
4387
4388 /*
4389  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4390  *
4391  * @param
4392  * dev: Pointer to struct rte_eth_dev.
4393  * ntuple_filter: ponter to the filter that will be added.
4394  *
4395  * @return
4396  *    - On success, zero.
4397  *    - On failure, a negative value.
4398  */
4399 static int
4400 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4401                         struct rte_eth_ntuple_filter *ntuple_filter)
4402 {
4403         struct e1000_filter_info *filter_info =
4404                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4405         struct e1000_5tuple_filter *filter;
4406         uint8_t i;
4407         int ret;
4408
4409         filter = rte_zmalloc("e1000_5tuple_filter",
4410                         sizeof(struct e1000_5tuple_filter), 0);
4411         if (filter == NULL)
4412                 return -ENOMEM;
4413
4414         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4415                                             &filter->filter_info);
4416         if (ret < 0) {
4417                 rte_free(filter);
4418                 return ret;
4419         }
4420
4421         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4422                                          &filter->filter_info) != NULL) {
4423                 PMD_DRV_LOG(ERR, "filter exists.");
4424                 rte_free(filter);
4425                 return -EEXIST;
4426         }
4427         filter->queue = ntuple_filter->queue;
4428
4429         /*
4430          * look for an unused 5tuple filter index,
4431          * and insert the filter to list.
4432          */
4433         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4434                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4435                         filter_info->fivetuple_mask |= 1 << i;
4436                         filter->index = i;
4437                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4438                                           filter,
4439                                           entries);
4440                         break;
4441                 }
4442         }
4443         if (i >= E1000_MAX_FTQF_FILTERS) {
4444                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4445                 rte_free(filter);
4446                 return -ENOSYS;
4447         }
4448
4449         igb_inject_5tuple_filter_82576(dev, filter);
4450         return 0;
4451 }
4452
4453 int
4454 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4455                                 struct e1000_5tuple_filter *filter)
4456 {
4457         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4458         struct e1000_filter_info *filter_info =
4459                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4460
4461         filter_info->fivetuple_mask &= ~(1 << filter->index);
4462         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4463         rte_free(filter);
4464
4465         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4466                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4467         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4468         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4469         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4470         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4471         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4472         return 0;
4473 }
4474
4475 /*
4476  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4477  *
4478  * @param
4479  * dev: Pointer to struct rte_eth_dev.
4480  * ntuple_filter: ponter to the filter that will be removed.
4481  *
4482  * @return
4483  *    - On success, zero.
4484  *    - On failure, a negative value.
4485  */
4486 static int
4487 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4488                                 struct rte_eth_ntuple_filter *ntuple_filter)
4489 {
4490         struct e1000_filter_info *filter_info =
4491                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4492         struct e1000_5tuple_filter_info filter_5tuple;
4493         struct e1000_5tuple_filter *filter;
4494         int ret;
4495
4496         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4497         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4498                                             &filter_5tuple);
4499         if (ret < 0)
4500                 return ret;
4501
4502         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4503                                          &filter_5tuple);
4504         if (filter == NULL) {
4505                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4506                 return -ENOENT;
4507         }
4508
4509         igb_delete_5tuple_filter_82576(dev, filter);
4510
4511         return 0;
4512 }
4513
4514 static int
4515 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4516 {
4517         uint32_t rctl;
4518         struct e1000_hw *hw;
4519         struct rte_eth_dev_info dev_info;
4520         uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4521         int ret;
4522
4523         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4524
4525 #ifdef RTE_LIBRTE_82571_SUPPORT
4526         /* XXX: not bigger than max_rx_pktlen */
4527         if (hw->mac.type == e1000_82571)
4528                 return -ENOTSUP;
4529 #endif
4530         ret = eth_igb_infos_get(dev, &dev_info);
4531         if (ret != 0)
4532                 return ret;
4533
4534         /* check that mtu is within the allowed range */
4535         if (mtu < RTE_ETHER_MIN_MTU ||
4536                         frame_size > dev_info.max_rx_pktlen)
4537                 return -EINVAL;
4538
4539         /* refuse mtu that requires the support of scattered packets when this
4540          * feature has not been enabled before. */
4541         if (!dev->data->scattered_rx &&
4542             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4543                 return -EINVAL;
4544
4545         rctl = E1000_READ_REG(hw, E1000_RCTL);
4546
4547         /* switch to jumbo mode if needed */
4548         if (frame_size > RTE_ETHER_MAX_LEN) {
4549                 dev->data->dev_conf.rxmode.offloads |=
4550                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4551                 rctl |= E1000_RCTL_LPE;
4552         } else {
4553                 dev->data->dev_conf.rxmode.offloads &=
4554                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4555                 rctl &= ~E1000_RCTL_LPE;
4556         }
4557         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4558
4559         /* update max frame size */
4560         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4561
4562         E1000_WRITE_REG(hw, E1000_RLPML,
4563                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4564
4565         return 0;
4566 }
4567
4568 /*
4569  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4570  *
4571  * @param
4572  * dev: Pointer to struct rte_eth_dev.
4573  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4574  * add: if true, add filter, if false, remove filter
4575  *
4576  * @return
4577  *    - On success, zero.
4578  *    - On failure, a negative value.
4579  */
4580 int
4581 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4582                         struct rte_eth_ntuple_filter *ntuple_filter,
4583                         bool add)
4584 {
4585         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4586         int ret;
4587
4588         switch (ntuple_filter->flags) {
4589         case RTE_5TUPLE_FLAGS:
4590         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4591                 if (hw->mac.type != e1000_82576)
4592                         return -ENOTSUP;
4593                 if (add)
4594                         ret = igb_add_5tuple_filter_82576(dev,
4595                                                           ntuple_filter);
4596                 else
4597                         ret = igb_remove_5tuple_filter_82576(dev,
4598                                                              ntuple_filter);
4599                 break;
4600         case RTE_2TUPLE_FLAGS:
4601         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4602                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4603                         hw->mac.type != e1000_i210 &&
4604                         hw->mac.type != e1000_i211)
4605                         return -ENOTSUP;
4606                 if (add)
4607                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4608                 else
4609                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4610                 break;
4611         default:
4612                 ret = -EINVAL;
4613                 break;
4614         }
4615
4616         return ret;
4617 }
4618
4619 /*
4620  * igb_get_ntuple_filter - get a ntuple filter
4621  *
4622  * @param
4623  * dev: Pointer to struct rte_eth_dev.
4624  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4625  *
4626  * @return
4627  *    - On success, zero.
4628  *    - On failure, a negative value.
4629  */
4630 static int
4631 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4632                         struct rte_eth_ntuple_filter *ntuple_filter)
4633 {
4634         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4635         struct e1000_filter_info *filter_info =
4636                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4637         struct e1000_5tuple_filter_info filter_5tuple;
4638         struct e1000_2tuple_filter_info filter_2tuple;
4639         struct e1000_5tuple_filter *p_5tuple_filter;
4640         struct e1000_2tuple_filter *p_2tuple_filter;
4641         int ret;
4642
4643         switch (ntuple_filter->flags) {
4644         case RTE_5TUPLE_FLAGS:
4645         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4646                 if (hw->mac.type != e1000_82576)
4647                         return -ENOTSUP;
4648                 memset(&filter_5tuple,
4649                         0,
4650                         sizeof(struct e1000_5tuple_filter_info));
4651                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4652                                                     &filter_5tuple);
4653                 if (ret < 0)
4654                         return ret;
4655                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4656                                         &filter_info->fivetuple_list,
4657                                         &filter_5tuple);
4658                 if (p_5tuple_filter == NULL) {
4659                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4660                         return -ENOENT;
4661                 }
4662                 ntuple_filter->queue = p_5tuple_filter->queue;
4663                 break;
4664         case RTE_2TUPLE_FLAGS:
4665         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4666                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4667                         return -ENOTSUP;
4668                 memset(&filter_2tuple,
4669                         0,
4670                         sizeof(struct e1000_2tuple_filter_info));
4671                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4672                 if (ret < 0)
4673                         return ret;
4674                 p_2tuple_filter = igb_2tuple_filter_lookup(
4675                                         &filter_info->twotuple_list,
4676                                         &filter_2tuple);
4677                 if (p_2tuple_filter == NULL) {
4678                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4679                         return -ENOENT;
4680                 }
4681                 ntuple_filter->queue = p_2tuple_filter->queue;
4682                 break;
4683         default:
4684                 ret = -EINVAL;
4685                 break;
4686         }
4687
4688         return 0;
4689 }
4690
4691 /*
4692  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4693  * @dev: pointer to rte_eth_dev structure
4694  * @filter_op:operation will be taken.
4695  * @arg: a pointer to specific structure corresponding to the filter_op
4696  */
4697 static int
4698 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4699                                 enum rte_filter_op filter_op,
4700                                 void *arg)
4701 {
4702         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4703         int ret;
4704
4705         MAC_TYPE_FILTER_SUP(hw->mac.type);
4706
4707         if (filter_op == RTE_ETH_FILTER_NOP)
4708                 return 0;
4709
4710         if (arg == NULL) {
4711                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4712                             filter_op);
4713                 return -EINVAL;
4714         }
4715
4716         switch (filter_op) {
4717         case RTE_ETH_FILTER_ADD:
4718                 ret = igb_add_del_ntuple_filter(dev,
4719                         (struct rte_eth_ntuple_filter *)arg,
4720                         TRUE);
4721                 break;
4722         case RTE_ETH_FILTER_DELETE:
4723                 ret = igb_add_del_ntuple_filter(dev,
4724                         (struct rte_eth_ntuple_filter *)arg,
4725                         FALSE);
4726                 break;
4727         case RTE_ETH_FILTER_GET:
4728                 ret = igb_get_ntuple_filter(dev,
4729                         (struct rte_eth_ntuple_filter *)arg);
4730                 break;
4731         default:
4732                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4733                 ret = -EINVAL;
4734                 break;
4735         }
4736         return ret;
4737 }
4738
4739 static inline int
4740 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4741                         uint16_t ethertype)
4742 {
4743         int i;
4744
4745         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4746                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4747                     (filter_info->ethertype_mask & (1 << i)))
4748                         return i;
4749         }
4750         return -1;
4751 }
4752
4753 static inline int
4754 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4755                         uint16_t ethertype, uint32_t etqf)
4756 {
4757         int i;
4758
4759         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4760                 if (!(filter_info->ethertype_mask & (1 << i))) {
4761                         filter_info->ethertype_mask |= 1 << i;
4762                         filter_info->ethertype_filters[i].ethertype = ethertype;
4763                         filter_info->ethertype_filters[i].etqf = etqf;
4764                         return i;
4765                 }
4766         }
4767         return -1;
4768 }
4769
4770 int
4771 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4772                         uint8_t idx)
4773 {
4774         if (idx >= E1000_MAX_ETQF_FILTERS)
4775                 return -1;
4776         filter_info->ethertype_mask &= ~(1 << idx);
4777         filter_info->ethertype_filters[idx].ethertype = 0;
4778         filter_info->ethertype_filters[idx].etqf = 0;
4779         return idx;
4780 }
4781
4782
4783 int
4784 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4785                         struct rte_eth_ethertype_filter *filter,
4786                         bool add)
4787 {
4788         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4789         struct e1000_filter_info *filter_info =
4790                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4791         uint32_t etqf = 0;
4792         int ret;
4793
4794         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4795                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4796                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4797                         " ethertype filter.", filter->ether_type);
4798                 return -EINVAL;
4799         }
4800
4801         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4802                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4803                 return -EINVAL;
4804         }
4805         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4806                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4807                 return -EINVAL;
4808         }
4809
4810         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4811         if (ret >= 0 && add) {
4812                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4813                             filter->ether_type);
4814                 return -EEXIST;
4815         }
4816         if (ret < 0 && !add) {
4817                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4818                             filter->ether_type);
4819                 return -ENOENT;
4820         }
4821
4822         if (add) {
4823                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4824                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4825                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4826                 ret = igb_ethertype_filter_insert(filter_info,
4827                                 filter->ether_type, etqf);
4828                 if (ret < 0) {
4829                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4830                         return -ENOSYS;
4831                 }
4832         } else {
4833                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4834                 if (ret < 0)
4835                         return -ENOSYS;
4836         }
4837         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4838         E1000_WRITE_FLUSH(hw);
4839
4840         return 0;
4841 }
4842
4843 static int
4844 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4845                         struct rte_eth_ethertype_filter *filter)
4846 {
4847         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4848         struct e1000_filter_info *filter_info =
4849                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4850         uint32_t etqf;
4851         int ret;
4852
4853         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4854         if (ret < 0) {
4855                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4856                             filter->ether_type);
4857                 return -ENOENT;
4858         }
4859
4860         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4861         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4862                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4863                 filter->flags = 0;
4864                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4865                                 E1000_ETQF_QUEUE_SHIFT;
4866                 return 0;
4867         }
4868
4869         return -ENOENT;
4870 }
4871
4872 /*
4873  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4874  * @dev: pointer to rte_eth_dev structure
4875  * @filter_op:operation will be taken.
4876  * @arg: a pointer to specific structure corresponding to the filter_op
4877  */
4878 static int
4879 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4880                                 enum rte_filter_op filter_op,
4881                                 void *arg)
4882 {
4883         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4884         int ret;
4885
4886         MAC_TYPE_FILTER_SUP(hw->mac.type);
4887
4888         if (filter_op == RTE_ETH_FILTER_NOP)
4889                 return 0;
4890
4891         if (arg == NULL) {
4892                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4893                             filter_op);
4894                 return -EINVAL;
4895         }
4896
4897         switch (filter_op) {
4898         case RTE_ETH_FILTER_ADD:
4899                 ret = igb_add_del_ethertype_filter(dev,
4900                         (struct rte_eth_ethertype_filter *)arg,
4901                         TRUE);
4902                 break;
4903         case RTE_ETH_FILTER_DELETE:
4904                 ret = igb_add_del_ethertype_filter(dev,
4905                         (struct rte_eth_ethertype_filter *)arg,
4906                         FALSE);
4907                 break;
4908         case RTE_ETH_FILTER_GET:
4909                 ret = igb_get_ethertype_filter(dev,
4910                         (struct rte_eth_ethertype_filter *)arg);
4911                 break;
4912         default:
4913                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4914                 ret = -EINVAL;
4915                 break;
4916         }
4917         return ret;
4918 }
4919
4920 static int
4921 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4922                      enum rte_filter_type filter_type,
4923                      enum rte_filter_op filter_op,
4924                      void *arg)
4925 {
4926         int ret = 0;
4927
4928         switch (filter_type) {
4929         case RTE_ETH_FILTER_NTUPLE:
4930                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4931                 break;
4932         case RTE_ETH_FILTER_ETHERTYPE:
4933                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4934                 break;
4935         case RTE_ETH_FILTER_SYN:
4936                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4937                 break;
4938         case RTE_ETH_FILTER_FLEXIBLE:
4939                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4940                 break;
4941         case RTE_ETH_FILTER_GENERIC:
4942                 if (filter_op != RTE_ETH_FILTER_GET)
4943                         return -EINVAL;
4944                 *(const void **)arg = &igb_flow_ops;
4945                 break;
4946         default:
4947                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4948                                                         filter_type);
4949                 break;
4950         }
4951
4952         return ret;
4953 }
4954
4955 static int
4956 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4957                          struct rte_ether_addr *mc_addr_set,
4958                          uint32_t nb_mc_addr)
4959 {
4960         struct e1000_hw *hw;
4961
4962         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4963         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4964         return 0;
4965 }
4966
4967 static uint64_t
4968 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4969 {
4970         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4971         uint64_t systime_cycles;
4972
4973         switch (hw->mac.type) {
4974         case e1000_i210:
4975         case e1000_i211:
4976                 /*
4977                  * Need to read System Time Residue Register to be able
4978                  * to read the other two registers.
4979                  */
4980                 E1000_READ_REG(hw, E1000_SYSTIMR);
4981                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4982                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4983                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4984                                 * NSEC_PER_SEC;
4985                 break;
4986         case e1000_82580:
4987         case e1000_i350:
4988         case e1000_i354:
4989                 /*
4990                  * Need to read System Time Residue Register to be able
4991                  * to read the other two registers.
4992                  */
4993                 E1000_READ_REG(hw, E1000_SYSTIMR);
4994                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4995                 /* Only the 8 LSB are valid. */
4996                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4997                                 & 0xff) << 32;
4998                 break;
4999         default:
5000                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
5001                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
5002                                 << 32;
5003                 break;
5004         }
5005
5006         return systime_cycles;
5007 }
5008
5009 static uint64_t
5010 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5011 {
5012         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5013         uint64_t rx_tstamp_cycles;
5014
5015         switch (hw->mac.type) {
5016         case e1000_i210:
5017         case e1000_i211:
5018                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5019                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5020                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5021                                 * NSEC_PER_SEC;
5022                 break;
5023         case e1000_82580:
5024         case e1000_i350:
5025         case e1000_i354:
5026                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5027                 /* Only the 8 LSB are valid. */
5028                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
5029                                 & 0xff) << 32;
5030                 break;
5031         default:
5032                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5033                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5034                                 << 32;
5035                 break;
5036         }
5037
5038         return rx_tstamp_cycles;
5039 }
5040
5041 static uint64_t
5042 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5043 {
5044         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5045         uint64_t tx_tstamp_cycles;
5046
5047         switch (hw->mac.type) {
5048         case e1000_i210:
5049         case e1000_i211:
5050                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5051                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5052                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5053                                 * NSEC_PER_SEC;
5054                 break;
5055         case e1000_82580:
5056         case e1000_i350:
5057         case e1000_i354:
5058                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5059                 /* Only the 8 LSB are valid. */
5060                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5061                                 & 0xff) << 32;
5062                 break;
5063         default:
5064                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5065                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5066                                 << 32;
5067                 break;
5068         }
5069
5070         return tx_tstamp_cycles;
5071 }
5072
5073 static void
5074 igb_start_timecounters(struct rte_eth_dev *dev)
5075 {
5076         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5077         struct e1000_adapter *adapter = dev->data->dev_private;
5078         uint32_t incval = 1;
5079         uint32_t shift = 0;
5080         uint64_t mask = E1000_CYCLECOUNTER_MASK;
5081
5082         switch (hw->mac.type) {
5083         case e1000_82580:
5084         case e1000_i350:
5085         case e1000_i354:
5086                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5087                 mask = (1ULL << 40) - 1;
5088                 /* fall-through */
5089         case e1000_i210:
5090         case e1000_i211:
5091                 /*
5092                  * Start incrementing the register
5093                  * used to timestamp PTP packets.
5094                  */
5095                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5096                 break;
5097         case e1000_82576:
5098                 incval = E1000_INCVALUE_82576;
5099                 shift = IGB_82576_TSYNC_SHIFT;
5100                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5101                                 E1000_INCPERIOD_82576 | incval);
5102                 break;
5103         default:
5104                 /* Not supported */
5105                 return;
5106         }
5107
5108         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5109         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5110         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5111
5112         adapter->systime_tc.cc_mask = mask;
5113         adapter->systime_tc.cc_shift = shift;
5114         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5115
5116         adapter->rx_tstamp_tc.cc_mask = mask;
5117         adapter->rx_tstamp_tc.cc_shift = shift;
5118         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5119
5120         adapter->tx_tstamp_tc.cc_mask = mask;
5121         adapter->tx_tstamp_tc.cc_shift = shift;
5122         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5123 }
5124
5125 static int
5126 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5127 {
5128         struct e1000_adapter *adapter = dev->data->dev_private;
5129
5130         adapter->systime_tc.nsec += delta;
5131         adapter->rx_tstamp_tc.nsec += delta;
5132         adapter->tx_tstamp_tc.nsec += delta;
5133
5134         return 0;
5135 }
5136
5137 static int
5138 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5139 {
5140         uint64_t ns;
5141         struct e1000_adapter *adapter = dev->data->dev_private;
5142
5143         ns = rte_timespec_to_ns(ts);
5144
5145         /* Set the timecounters to a new value. */
5146         adapter->systime_tc.nsec = ns;
5147         adapter->rx_tstamp_tc.nsec = ns;
5148         adapter->tx_tstamp_tc.nsec = ns;
5149
5150         return 0;
5151 }
5152
5153 static int
5154 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5155 {
5156         uint64_t ns, systime_cycles;
5157         struct e1000_adapter *adapter = dev->data->dev_private;
5158
5159         systime_cycles = igb_read_systime_cyclecounter(dev);
5160         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5161         *ts = rte_ns_to_timespec(ns);
5162
5163         return 0;
5164 }
5165
5166 static int
5167 igb_timesync_enable(struct rte_eth_dev *dev)
5168 {
5169         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5170         uint32_t tsync_ctl;
5171         uint32_t tsauxc;
5172
5173         /* Stop the timesync system time. */
5174         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5175         /* Reset the timesync system time value. */
5176         switch (hw->mac.type) {
5177         case e1000_82580:
5178         case e1000_i350:
5179         case e1000_i354:
5180         case e1000_i210:
5181         case e1000_i211:
5182                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5183                 /* fall-through */
5184         case e1000_82576:
5185                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5186                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5187                 break;
5188         default:
5189                 /* Not supported. */
5190                 return -ENOTSUP;
5191         }
5192
5193         /* Enable system time for it isn't on by default. */
5194         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5195         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5196         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5197
5198         igb_start_timecounters(dev);
5199
5200         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5201         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5202                         (RTE_ETHER_TYPE_1588 |
5203                          E1000_ETQF_FILTER_ENABLE |
5204                          E1000_ETQF_1588));
5205
5206         /* Enable timestamping of received PTP packets. */
5207         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5208         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5209         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5210
5211         /* Enable Timestamping of transmitted PTP packets. */
5212         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5213         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5214         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5215
5216         return 0;
5217 }
5218
5219 static int
5220 igb_timesync_disable(struct rte_eth_dev *dev)
5221 {
5222         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5223         uint32_t tsync_ctl;
5224
5225         /* Disable timestamping of transmitted PTP packets. */
5226         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5227         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5228         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5229
5230         /* Disable timestamping of received PTP packets. */
5231         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5232         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5233         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5234
5235         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5236         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5237
5238         /* Stop incrementating the System Time registers. */
5239         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5240
5241         return 0;
5242 }
5243
5244 static int
5245 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5246                                struct timespec *timestamp,
5247                                uint32_t flags __rte_unused)
5248 {
5249         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5250         struct e1000_adapter *adapter = dev->data->dev_private;
5251         uint32_t tsync_rxctl;
5252         uint64_t rx_tstamp_cycles;
5253         uint64_t ns;
5254
5255         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5256         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5257                 return -EINVAL;
5258
5259         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5260         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5261         *timestamp = rte_ns_to_timespec(ns);
5262
5263         return  0;
5264 }
5265
5266 static int
5267 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5268                                struct timespec *timestamp)
5269 {
5270         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5271         struct e1000_adapter *adapter = dev->data->dev_private;
5272         uint32_t tsync_txctl;
5273         uint64_t tx_tstamp_cycles;
5274         uint64_t ns;
5275
5276         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5277         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5278                 return -EINVAL;
5279
5280         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5281         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5282         *timestamp = rte_ns_to_timespec(ns);
5283
5284         return  0;
5285 }
5286
5287 static int
5288 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5289 {
5290         int count = 0;
5291         int g_ind = 0;
5292         const struct reg_info *reg_group;
5293
5294         while ((reg_group = igb_regs[g_ind++]))
5295                 count += igb_reg_group_count(reg_group);
5296
5297         return count;
5298 }
5299
5300 static int
5301 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5302 {
5303         int count = 0;
5304         int g_ind = 0;
5305         const struct reg_info *reg_group;
5306
5307         while ((reg_group = igbvf_regs[g_ind++]))
5308                 count += igb_reg_group_count(reg_group);
5309
5310         return count;
5311 }
5312
5313 static int
5314 eth_igb_get_regs(struct rte_eth_dev *dev,
5315         struct rte_dev_reg_info *regs)
5316 {
5317         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5318         uint32_t *data = regs->data;
5319         int g_ind = 0;
5320         int count = 0;
5321         const struct reg_info *reg_group;
5322
5323         if (data == NULL) {
5324                 regs->length = eth_igb_get_reg_length(dev);
5325                 regs->width = sizeof(uint32_t);
5326                 return 0;
5327         }
5328
5329         /* Support only full register dump */
5330         if ((regs->length == 0) ||
5331             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5332                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5333                         hw->device_id;
5334                 while ((reg_group = igb_regs[g_ind++]))
5335                         count += igb_read_regs_group(dev, &data[count],
5336                                                         reg_group);
5337                 return 0;
5338         }
5339
5340         return -ENOTSUP;
5341 }
5342
5343 static int
5344 igbvf_get_regs(struct rte_eth_dev *dev,
5345         struct rte_dev_reg_info *regs)
5346 {
5347         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5348         uint32_t *data = regs->data;
5349         int g_ind = 0;
5350         int count = 0;
5351         const struct reg_info *reg_group;
5352
5353         if (data == NULL) {
5354                 regs->length = igbvf_get_reg_length(dev);
5355                 regs->width = sizeof(uint32_t);
5356                 return 0;
5357         }
5358
5359         /* Support only full register dump */
5360         if ((regs->length == 0) ||
5361             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5362                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5363                         hw->device_id;
5364                 while ((reg_group = igbvf_regs[g_ind++]))
5365                         count += igb_read_regs_group(dev, &data[count],
5366                                                         reg_group);
5367                 return 0;
5368         }
5369
5370         return -ENOTSUP;
5371 }
5372
5373 static int
5374 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5375 {
5376         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5377
5378         /* Return unit is byte count */
5379         return hw->nvm.word_size * 2;
5380 }
5381
5382 static int
5383 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5384         struct rte_dev_eeprom_info *in_eeprom)
5385 {
5386         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5387         struct e1000_nvm_info *nvm = &hw->nvm;
5388         uint16_t *data = in_eeprom->data;
5389         int first, length;
5390
5391         first = in_eeprom->offset >> 1;
5392         length = in_eeprom->length >> 1;
5393         if ((first >= hw->nvm.word_size) ||
5394             ((first + length) >= hw->nvm.word_size))
5395                 return -EINVAL;
5396
5397         in_eeprom->magic = hw->vendor_id |
5398                 ((uint32_t)hw->device_id << 16);
5399
5400         if ((nvm->ops.read) == NULL)
5401                 return -ENOTSUP;
5402
5403         return nvm->ops.read(hw, first, length, data);
5404 }
5405
5406 static int
5407 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5408         struct rte_dev_eeprom_info *in_eeprom)
5409 {
5410         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5411         struct e1000_nvm_info *nvm = &hw->nvm;
5412         uint16_t *data = in_eeprom->data;
5413         int first, length;
5414
5415         first = in_eeprom->offset >> 1;
5416         length = in_eeprom->length >> 1;
5417         if ((first >= hw->nvm.word_size) ||
5418             ((first + length) >= hw->nvm.word_size))
5419                 return -EINVAL;
5420
5421         in_eeprom->magic = (uint32_t)hw->vendor_id |
5422                 ((uint32_t)hw->device_id << 16);
5423
5424         if ((nvm->ops.write) == NULL)
5425                 return -ENOTSUP;
5426         return nvm->ops.write(hw,  first, length, data);
5427 }
5428
5429 static int
5430 eth_igb_get_module_info(struct rte_eth_dev *dev,
5431                         struct rte_eth_dev_module_info *modinfo)
5432 {
5433         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5434
5435         uint32_t status = 0;
5436         uint16_t sff8472_rev, addr_mode;
5437         bool page_swap = false;
5438
5439         if (hw->phy.media_type == e1000_media_type_copper ||
5440             hw->phy.media_type == e1000_media_type_unknown)
5441                 return -EOPNOTSUPP;
5442
5443         /* Check whether we support SFF-8472 or not */
5444         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5445         if (status)
5446                 return -EIO;
5447
5448         /* addressing mode is not supported */
5449         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5450         if (status)
5451                 return -EIO;
5452
5453         /* addressing mode is not supported */
5454         if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5455                 PMD_DRV_LOG(ERR,
5456                             "Address change required to access page 0xA2, "
5457                             "but not supported. Please report the module "
5458                             "type to the driver maintainers.\n");
5459                 page_swap = true;
5460         }
5461
5462         if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5463                 /* We have an SFP, but it does not support SFF-8472 */
5464                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5465                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5466         } else {
5467                 /* We have an SFP which supports a revision of SFF-8472 */
5468                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5469                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5470         }
5471
5472         return 0;
5473 }
5474
5475 static int
5476 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5477                           struct rte_dev_eeprom_info *info)
5478 {
5479         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5480
5481         uint32_t status = 0;
5482         uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5483         u16 first_word, last_word;
5484         int i = 0;
5485
5486         if (info->length == 0)
5487                 return -EINVAL;
5488
5489         first_word = info->offset >> 1;
5490         last_word = (info->offset + info->length - 1) >> 1;
5491
5492         /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5493         for (i = 0; i < last_word - first_word + 1; i++) {
5494                 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5495                                                 &dataword[i]);
5496                 if (status) {
5497                         /* Error occurred while reading module */
5498                         return -EIO;
5499                 }
5500
5501                 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5502         }
5503
5504         memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5505
5506         return 0;
5507 }
5508
5509 static int
5510 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5511 {
5512         struct e1000_hw *hw =
5513                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5514         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5515         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5516         uint32_t vec = E1000_MISC_VEC_ID;
5517
5518         if (rte_intr_allow_others(intr_handle))
5519                 vec = E1000_RX_VEC_START;
5520
5521         uint32_t mask = 1 << (queue_id + vec);
5522
5523         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5524         E1000_WRITE_FLUSH(hw);
5525
5526         return 0;
5527 }
5528
5529 static int
5530 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5531 {
5532         struct e1000_hw *hw =
5533                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5534         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5535         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5536         uint32_t vec = E1000_MISC_VEC_ID;
5537
5538         if (rte_intr_allow_others(intr_handle))
5539                 vec = E1000_RX_VEC_START;
5540
5541         uint32_t mask = 1 << (queue_id + vec);
5542         uint32_t regval;
5543
5544         regval = E1000_READ_REG(hw, E1000_EIMS);
5545         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5546         E1000_WRITE_FLUSH(hw);
5547
5548         rte_intr_ack(intr_handle);
5549
5550         return 0;
5551 }
5552
5553 static void
5554 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5555                    uint8_t index, uint8_t offset)
5556 {
5557         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5558
5559         /* clear bits */
5560         val &= ~((uint32_t)0xFF << offset);
5561
5562         /* write vector and valid bit */
5563         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5564
5565         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5566 }
5567
5568 static void
5569 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5570                            uint8_t queue, uint8_t msix_vector)
5571 {
5572         uint32_t tmp = 0;
5573
5574         if (hw->mac.type == e1000_82575) {
5575                 if (direction == 0)
5576                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5577                 else if (direction == 1)
5578                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5579                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5580         } else if (hw->mac.type == e1000_82576) {
5581                 if ((direction == 0) || (direction == 1))
5582                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5583                                            ((queue & 0x8) << 1) +
5584                                            8 * direction);
5585         } else if ((hw->mac.type == e1000_82580) ||
5586                         (hw->mac.type == e1000_i350) ||
5587                         (hw->mac.type == e1000_i354) ||
5588                         (hw->mac.type == e1000_i210) ||
5589                         (hw->mac.type == e1000_i211)) {
5590                 if ((direction == 0) || (direction == 1))
5591                         eth_igb_write_ivar(hw, msix_vector,
5592                                            queue >> 1,
5593                                            ((queue & 0x1) << 4) +
5594                                            8 * direction);
5595         }
5596 }
5597
5598 /* Sets up the hardware to generate MSI-X interrupts properly
5599  * @hw
5600  *  board private structure
5601  */
5602 static void
5603 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5604 {
5605         int queue_id;
5606         uint32_t tmpval, regval, intr_mask;
5607         struct e1000_hw *hw =
5608                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5609         uint32_t vec = E1000_MISC_VEC_ID;
5610         uint32_t base = E1000_MISC_VEC_ID;
5611         uint32_t misc_shift = 0;
5612         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5613         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5614
5615         /* won't configure msix register if no mapping is done
5616          * between intr vector and event fd
5617          */
5618         if (!rte_intr_dp_is_en(intr_handle))
5619                 return;
5620
5621         if (rte_intr_allow_others(intr_handle)) {
5622                 vec = base = E1000_RX_VEC_START;
5623                 misc_shift = 1;
5624         }
5625
5626         /* set interrupt vector for other causes */
5627         if (hw->mac.type == e1000_82575) {
5628                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5629                 /* enable MSI-X PBA support */
5630                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5631
5632                 /* Auto-Mask interrupts upon ICR read */
5633                 tmpval |= E1000_CTRL_EXT_EIAME;
5634                 tmpval |= E1000_CTRL_EXT_IRCA;
5635
5636                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5637
5638                 /* enable msix_other interrupt */
5639                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5640                 regval = E1000_READ_REG(hw, E1000_EIAC);
5641                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5642                 regval = E1000_READ_REG(hw, E1000_EIAM);
5643                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5644         } else if ((hw->mac.type == e1000_82576) ||
5645                         (hw->mac.type == e1000_82580) ||
5646                         (hw->mac.type == e1000_i350) ||
5647                         (hw->mac.type == e1000_i354) ||
5648                         (hw->mac.type == e1000_i210) ||
5649                         (hw->mac.type == e1000_i211)) {
5650                 /* turn on MSI-X capability first */
5651                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5652                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5653                                         E1000_GPIE_NSICR);
5654                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5655                         misc_shift;
5656
5657                 if (dev->data->dev_conf.intr_conf.lsc != 0)
5658                         intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5659
5660                 regval = E1000_READ_REG(hw, E1000_EIAC);
5661                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5662
5663                 /* enable msix_other interrupt */
5664                 regval = E1000_READ_REG(hw, E1000_EIMS);
5665                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5666                 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5667                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5668         }
5669
5670         /* use EIAM to auto-mask when MSI-X interrupt
5671          * is asserted, this saves a register write for every interrupt
5672          */
5673         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5674                 misc_shift;
5675
5676         if (dev->data->dev_conf.intr_conf.lsc != 0)
5677                 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5678
5679         regval = E1000_READ_REG(hw, E1000_EIAM);
5680         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5681
5682         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5683                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5684                 intr_handle->intr_vec[queue_id] = vec;
5685                 if (vec < base + intr_handle->nb_efd - 1)
5686                         vec++;
5687         }
5688
5689         E1000_WRITE_FLUSH(hw);
5690 }
5691
5692 /* restore n-tuple filter */
5693 static inline void
5694 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5695 {
5696         struct e1000_filter_info *filter_info =
5697                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5698         struct e1000_5tuple_filter *p_5tuple;
5699         struct e1000_2tuple_filter *p_2tuple;
5700
5701         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5702                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5703         }
5704
5705         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5706                 igb_inject_2uple_filter(dev, p_2tuple);
5707         }
5708 }
5709
5710 /* restore SYN filter */
5711 static inline void
5712 igb_syn_filter_restore(struct rte_eth_dev *dev)
5713 {
5714         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5715         struct e1000_filter_info *filter_info =
5716                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5717         uint32_t synqf;
5718
5719         synqf = filter_info->syn_info;
5720
5721         if (synqf & E1000_SYN_FILTER_ENABLE) {
5722                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5723                 E1000_WRITE_FLUSH(hw);
5724         }
5725 }
5726
5727 /* restore ethernet type filter */
5728 static inline void
5729 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5730 {
5731         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5732         struct e1000_filter_info *filter_info =
5733                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5734         int i;
5735
5736         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5737                 if (filter_info->ethertype_mask & (1 << i)) {
5738                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5739                                 filter_info->ethertype_filters[i].etqf);
5740                         E1000_WRITE_FLUSH(hw);
5741                 }
5742         }
5743 }
5744
5745 /* restore flex byte filter */
5746 static inline void
5747 igb_flex_filter_restore(struct rte_eth_dev *dev)
5748 {
5749         struct e1000_filter_info *filter_info =
5750                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5751         struct e1000_flex_filter *flex_filter;
5752
5753         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5754                 igb_inject_flex_filter(dev, flex_filter);
5755         }
5756 }
5757
5758 /* restore rss filter */
5759 static inline void
5760 igb_rss_filter_restore(struct rte_eth_dev *dev)
5761 {
5762         struct e1000_filter_info *filter_info =
5763                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5764
5765         if (filter_info->rss_info.conf.queue_num)
5766                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5767 }
5768
5769 /* restore all types filter */
5770 static int
5771 igb_filter_restore(struct rte_eth_dev *dev)
5772 {
5773         igb_ntuple_filter_restore(dev);
5774         igb_ethertype_filter_restore(dev);
5775         igb_syn_filter_restore(dev);
5776         igb_flex_filter_restore(dev);
5777         igb_rss_filter_restore(dev);
5778
5779         return 0;
5780 }
5781
5782 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5783 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5784 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5785 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5786 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5787 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5788
5789 /* see e1000_logs.c */
5790 RTE_INIT(e1000_init_log)
5791 {
5792         e1000_igb_init_log();
5793 }