drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_string_fns.h>
  12 #include <rte_common.h>
  13 #include <rte_interrupts.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_log.h>
  16 #include <rte_debug.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memory.h>
  23 #include <rte_eal.h>
  24 #include <rte_malloc.h>
  25 #include <rte_dev.h>
  26
  27 #include "e1000_logs.h"
  28 #include "base/e1000_api.h"
  29 #include "e1000_ethdev.h"
  30 #include "igb_regs.h"
  31
  32 /*
  33  * Default values for port configuration
  34  */
  35 #define IGB_DEFAULT_RX_FREE_THRESH  32
  36
  37 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  38 #define IGB_DEFAULT_RX_HTHRESH      8
  39 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  40
  41 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  42 #define IGB_DEFAULT_TX_HTHRESH      1
  43 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  44
  45 /* Bit shift and mask */
  46 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  47 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  48 #define IGB_8_BIT_WIDTH  CHAR_BIT
  49 #define IGB_8_BIT_MASK   UINT8_MAX
  50
  51 /* Additional timesync values. */
  52 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  53 #define E1000_ETQF_FILTER_1588       3
  54 #define IGB_82576_TSYNC_SHIFT        16
  55 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  56 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  58
  59 #define E1000_VTIVAR_MISC                0x01740
  60 #define E1000_VTIVAR_MISC_MASK           0xFF
  61 #define E1000_VTIVAR_VALID               0x80
  62 #define E1000_VTIVAR_MISC_MAILBOX        0
  63 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  64
  65 /* External VLAN Enable bit mask */
  66 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  67
  68 /* External VLAN Ether Type bit mask and shift */
  69 #define E1000_VET_VET_EXT            0xFFFF0000
  70 #define E1000_VET_VET_EXT_SHIFT      16
  71
  72 /* MSI-X other interrupt vector */
  73 #define IGB_MSIX_OTHER_INTR_VEC      0
  74
  75 static int  eth_igb_configure(struct rte_eth_dev *dev);
  76 static int  eth_igb_start(struct rte_eth_dev *dev);
  77 static void eth_igb_stop(struct rte_eth_dev *dev);
  78 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  79 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  80 static void eth_igb_close(struct rte_eth_dev *dev);
  81 static int eth_igb_reset(struct rte_eth_dev *dev);
  82 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  83 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  84 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  85 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  87                                 int wait_to_complete);
  88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  89                                 struct rte_eth_stats *rte_stats);
  90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  91                               struct rte_eth_xstat *xstats, unsigned n);
  92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  93                 const uint64_t *ids,
  94                 uint64_t *values, unsigned int n);
  95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  96                                     struct rte_eth_xstat_name *xstats_names,
  97                                     unsigned int size);
  98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  99                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 100                 unsigned int limit);
 101 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 102 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 104                                    char *fw_version, size_t fw_size);
 105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
 106                               struct rte_eth_dev_info *dev_info);
 107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_dev_info *dev_info);
 110 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 113                                 struct rte_eth_fc_conf *fc_conf);
 114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 118                                     struct rte_intr_handle *handle);
 119 static void eth_igb_interrupt_handler(void *param);
 120 static int  igb_hardware_init(struct e1000_hw *hw);
 121 static void igb_hw_control_acquire(struct e1000_hw *hw);
 122 static void igb_hw_control_release(struct e1000_hw *hw);
 123 static void igb_init_manageability(struct e1000_hw *hw);
 124 static void igb_release_manageability(struct e1000_hw *hw);
 125
 126 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 127
 128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 129                 uint16_t vlan_id, int on);
 130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 131                                  enum rte_vlan_type vlan_type,
 132                                  uint16_t tpid_id);
 133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134
 135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 141
 142 static int eth_igb_led_on(struct rte_eth_dev *dev);
 143 static int eth_igb_led_off(struct rte_eth_dev *dev);
 144
 145 static void igb_intr_disable(struct rte_eth_dev *dev);
 146 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 148                            struct rte_ether_addr *mac_addr,
 149                            uint32_t index, uint32_t pool);
 150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 152                 struct rte_ether_addr *addr);
 153
 154 static void igbvf_intr_disable(struct e1000_hw *hw);
 155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 156 static int igbvf_dev_start(struct rte_eth_dev *dev);
 157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 158 static void igbvf_dev_close(struct rte_eth_dev *dev);
 159 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 160 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 161 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 162 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 163 static int eth_igbvf_link_update(struct e1000_hw *hw);
 164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_stats *rte_stats);
 166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 167                                 struct rte_eth_xstat *xstats, unsigned n);
 168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 169                                       struct rte_eth_xstat_name *xstats_names,
 170                                       unsigned limit);
 171 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 173                 uint16_t vlan_id, int on);
 174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 177                 struct rte_ether_addr *addr);
 178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 179 static int igbvf_get_regs(struct rte_eth_dev *dev,
 180                 struct rte_dev_reg_info *regs);
 181
 182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 183                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                    uint16_t reta_size);
 185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 186                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 187                                   uint16_t reta_size);
 188
 189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 190                         struct rte_eth_syn_filter *filter);
 191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 192                         enum rte_filter_op filter_op,
 193                         void *arg);
 194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_ntuple_filter *ntuple_filter);
 198 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 199                         struct rte_eth_flex_filter *filter);
 200 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 201                         enum rte_filter_op filter_op,
 202                         void *arg);
 203 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 204                         struct rte_eth_ntuple_filter *ntuple_filter);
 205 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 206                         struct rte_eth_ntuple_filter *ntuple_filter);
 207 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 208                         struct rte_eth_ntuple_filter *filter);
 209 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 213                                 enum rte_filter_op filter_op,
 214                                 void *arg);
 215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ethertype_filter *filter);
 217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 218                      enum rte_filter_type filter_type,
 219                      enum rte_filter_op filter_op,
 220                      void *arg);
 221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 223                 struct rte_dev_reg_info *regs);
 224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 226                 struct rte_dev_eeprom_info *eeprom);
 227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 228                 struct rte_dev_eeprom_info *eeprom);
 229 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
 230                                    struct rte_eth_dev_module_info *modinfo);
 231 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
 232                                      struct rte_dev_eeprom_info *info);
 233 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 234                                     struct rte_ether_addr *mc_addr_set,
 235                                     uint32_t nb_mc_addr);
 236 static int igb_timesync_enable(struct rte_eth_dev *dev);
 237 static int igb_timesync_disable(struct rte_eth_dev *dev);
 238 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 239                                           struct timespec *timestamp,
 240                                           uint32_t flags);
 241 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 242                                           struct timespec *timestamp);
 243 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 244 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 245                                   struct timespec *timestamp);
 246 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 247                                    const struct timespec *timestamp);
 248 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 249                                         uint16_t queue_id);
 250 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 251                                          uint16_t queue_id);
 252 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 253                                        uint8_t queue, uint8_t msix_vector);
 254 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 255                                uint8_t index, uint8_t offset);
 256 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 257 static void eth_igbvf_interrupt_handler(void *param);
 258 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 259 static int igb_filter_restore(struct rte_eth_dev *dev);
 260
 261 /*
 262  * Define VF Stats MACRO for Non "cleared on read" register
 263  */
 264 #define UPDATE_VF_STAT(reg, last, cur)            \
 265 {                                                 \
 266         u32 latest = E1000_READ_REG(hw, reg);     \
 267         cur += (latest - last) & UINT_MAX;        \
 268         last = latest;                            \
 269 }
 270
 271 #define IGB_FC_PAUSE_TIME 0x0680
 272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 274
 275 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 276
 277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 278
 279 /*
 280  * The set of PCI devices this driver supports
 281  */
 282 static const struct rte_pci_id pci_id_igb_map[] = {
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 284         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 285         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 286         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 287         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 288         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 289         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 290         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 291
 292         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 295
 296         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 297         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 302
 303         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 304         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 305         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 324         { .vendor_id = 0, /* sentinel */ },
 325 };
 326
 327 /*
 328  * The set of PCI devices this driver supports (for 82576&I350 VF)
 329  */
 330 static const struct rte_pci_id pci_id_igbvf_map[] = {
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 335         { .vendor_id = 0, /* sentinel */ },
 336 };
 337
 338 static const struct rte_eth_desc_lim rx_desc_lim = {
 339         .nb_max = E1000_MAX_RING_DESC,
 340         .nb_min = E1000_MIN_RING_DESC,
 341         .nb_align = IGB_RXD_ALIGN,
 342 };
 343
 344 static const struct rte_eth_desc_lim tx_desc_lim = {
 345         .nb_max = E1000_MAX_RING_DESC,
 346         .nb_min = E1000_MIN_RING_DESC,
 347         .nb_align = IGB_RXD_ALIGN,
 348         .nb_seg_max = IGB_TX_MAX_SEG,
 349         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 350 };
 351
 352 static const struct eth_dev_ops eth_igb_ops = {
 353         .dev_configure        = eth_igb_configure,
 354         .dev_start            = eth_igb_start,
 355         .dev_stop             = eth_igb_stop,
 356         .dev_set_link_up      = eth_igb_dev_set_link_up,
 357         .dev_set_link_down    = eth_igb_dev_set_link_down,
 358         .dev_close            = eth_igb_close,
 359         .dev_reset            = eth_igb_reset,
 360         .promiscuous_enable   = eth_igb_promiscuous_enable,
 361         .promiscuous_disable  = eth_igb_promiscuous_disable,
 362         .allmulticast_enable  = eth_igb_allmulticast_enable,
 363         .allmulticast_disable = eth_igb_allmulticast_disable,
 364         .link_update          = eth_igb_link_update,
 365         .stats_get            = eth_igb_stats_get,
 366         .xstats_get           = eth_igb_xstats_get,
 367         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 368         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 369         .xstats_get_names     = eth_igb_xstats_get_names,
 370         .stats_reset          = eth_igb_stats_reset,
 371         .xstats_reset         = eth_igb_xstats_reset,
 372         .fw_version_get       = eth_igb_fw_version_get,
 373         .dev_infos_get        = eth_igb_infos_get,
 374         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 375         .mtu_set              = eth_igb_mtu_set,
 376         .vlan_filter_set      = eth_igb_vlan_filter_set,
 377         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 378         .vlan_offload_set     = eth_igb_vlan_offload_set,
 379         .rx_queue_setup       = eth_igb_rx_queue_setup,
 380         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 381         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 382         .rx_queue_release     = eth_igb_rx_queue_release,
 383         .rx_queue_count       = eth_igb_rx_queue_count,
 384         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 385         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 386         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 387         .tx_queue_setup       = eth_igb_tx_queue_setup,
 388         .tx_queue_release     = eth_igb_tx_queue_release,
 389         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 390         .dev_led_on           = eth_igb_led_on,
 391         .dev_led_off          = eth_igb_led_off,
 392         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 393         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 394         .mac_addr_add         = eth_igb_rar_set,
 395         .mac_addr_remove      = eth_igb_rar_clear,
 396         .mac_addr_set         = eth_igb_default_mac_addr_set,
 397         .reta_update          = eth_igb_rss_reta_update,
 398         .reta_query           = eth_igb_rss_reta_query,
 399         .rss_hash_update      = eth_igb_rss_hash_update,
 400         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 401         .filter_ctrl          = eth_igb_filter_ctrl,
 402         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 403         .rxq_info_get         = igb_rxq_info_get,
 404         .txq_info_get         = igb_txq_info_get,
 405         .timesync_enable      = igb_timesync_enable,
 406         .timesync_disable     = igb_timesync_disable,
 407         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 408         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 409         .get_reg              = eth_igb_get_regs,
 410         .get_eeprom_length    = eth_igb_get_eeprom_length,
 411         .get_eeprom           = eth_igb_get_eeprom,
 412         .set_eeprom           = eth_igb_set_eeprom,
 413         .get_module_info      = eth_igb_get_module_info,
 414         .get_module_eeprom    = eth_igb_get_module_eeprom,
 415         .timesync_adjust_time = igb_timesync_adjust_time,
 416         .timesync_read_time   = igb_timesync_read_time,
 417         .timesync_write_time  = igb_timesync_write_time,
 418 };
 419
 420 /*
 421  * dev_ops for virtual function, bare necessities for basic vf
 422  * operation have been implemented
 423  */
 424 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 425         .dev_configure        = igbvf_dev_configure,
 426         .dev_start            = igbvf_dev_start,
 427         .dev_stop             = igbvf_dev_stop,
 428         .dev_close            = igbvf_dev_close,
 429         .promiscuous_enable   = igbvf_promiscuous_enable,
 430         .promiscuous_disable  = igbvf_promiscuous_disable,
 431         .allmulticast_enable  = igbvf_allmulticast_enable,
 432         .allmulticast_disable = igbvf_allmulticast_disable,
 433         .link_update          = eth_igb_link_update,
 434         .stats_get            = eth_igbvf_stats_get,
 435         .xstats_get           = eth_igbvf_xstats_get,
 436         .xstats_get_names     = eth_igbvf_xstats_get_names,
 437         .stats_reset          = eth_igbvf_stats_reset,
 438         .xstats_reset         = eth_igbvf_stats_reset,
 439         .vlan_filter_set      = igbvf_vlan_filter_set,
 440         .dev_infos_get        = eth_igbvf_infos_get,
 441         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 442         .rx_queue_setup       = eth_igb_rx_queue_setup,
 443         .rx_queue_release     = eth_igb_rx_queue_release,
 444         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 445         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 446         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 447         .tx_queue_setup       = eth_igb_tx_queue_setup,
 448         .tx_queue_release     = eth_igb_tx_queue_release,
 449         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 450         .rxq_info_get         = igb_rxq_info_get,
 451         .txq_info_get         = igb_txq_info_get,
 452         .mac_addr_set         = igbvf_default_mac_addr_set,
 453         .get_reg              = igbvf_get_regs,
 454 };
 455
 456 /* store statistics names and its offset in stats structure */
 457 struct rte_igb_xstats_name_off {
 458         char name[RTE_ETH_XSTATS_NAME_SIZE];
 459         unsigned offset;
 460 };
 461
 462 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 463         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 464         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 465         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 466         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 467         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 468         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 469         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 470                 ecol)},
 471         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 472         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 473         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 474         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 475         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 476         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 477         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 478         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 479         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 480         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 481         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 482                 fcruc)},
 483         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 484         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 485         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 486         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 487         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 488                 prc1023)},
 489         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 490                 prc1522)},
 491         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 492         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 493         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 494         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 495         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 496         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 497         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 498         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 499         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 500         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 501         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 502         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 503         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 504         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 505         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 506         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 507         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 508         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 509                 ptc1023)},
 510         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 511                 ptc1522)},
 512         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 513         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 514         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 515         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 516         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 517         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 518         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 519
 520         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 521 };
 522
 523 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 524                 sizeof(rte_igb_stats_strings[0]))
 525
 526 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 527         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 528         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 529         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 530         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 531         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 532 };
 533
 534 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 535                 sizeof(rte_igbvf_stats_strings[0]))
 536
 537
 538 static inline void
 539 igb_intr_enable(struct rte_eth_dev *dev)
 540 {
 541         struct e1000_interrupt *intr =
 542                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 543         struct e1000_hw *hw =
 544                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 545         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 546         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 547
 548         if (rte_intr_allow_others(intr_handle) &&
 549                 dev->data->dev_conf.intr_conf.lsc != 0) {
 550                 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
 551         }
 552
 553         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 554         E1000_WRITE_FLUSH(hw);
 555 }
 556
 557 static void
 558 igb_intr_disable(struct rte_eth_dev *dev)
 559 {
 560         struct e1000_hw *hw =
 561                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 562         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 563         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 564
 565         if (rte_intr_allow_others(intr_handle) &&
 566                 dev->data->dev_conf.intr_conf.lsc != 0) {
 567                 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
 568         }
 569
 570         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 571         E1000_WRITE_FLUSH(hw);
 572 }
 573
 574 static inline void
 575 igbvf_intr_enable(struct rte_eth_dev *dev)
 576 {
 577         struct e1000_hw *hw =
 578                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 579
 580         /* only for mailbox */
 581         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 582         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 583         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 584         E1000_WRITE_FLUSH(hw);
 585 }
 586
 587 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 588 static void
 589 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 590 {
 591         uint32_t tmp = 0;
 592
 593         /* mailbox */
 594         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 595         tmp |= E1000_VTIVAR_VALID;
 596         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 597 }
 598
 599 static void
 600 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 601 {
 602         struct e1000_hw *hw =
 603                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 604
 605         /* Configure VF other cause ivar */
 606         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 607 }
 608
 609 static inline int32_t
 610 igb_pf_reset_hw(struct e1000_hw *hw)
 611 {
 612         uint32_t ctrl_ext;
 613         int32_t status;
 614
 615         status = e1000_reset_hw(hw);
 616
 617         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 618         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 619         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 620         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 621         E1000_WRITE_FLUSH(hw);
 622
 623         return status;
 624 }
 625
 626 static void
 627 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 628 {
 629         struct e1000_hw *hw =
 630                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 631
 632
 633         hw->vendor_id = pci_dev->id.vendor_id;
 634         hw->device_id = pci_dev->id.device_id;
 635         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 636         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 637
 638         e1000_set_mac_type(hw);
 639
 640         /* need to check if it is a vf device below */
 641 }
 642
 643 static int
 644 igb_reset_swfw_lock(struct e1000_hw *hw)
 645 {
 646         int ret_val;
 647
 648         /*
 649          * Do mac ops initialization manually here, since we will need
 650          * some function pointers set by this call.
 651          */
 652         ret_val = e1000_init_mac_params(hw);
 653         if (ret_val)
 654                 return ret_val;
 655
 656         /*
 657          * SMBI lock should not fail in this early stage. If this is the case,
 658          * it is due to an improper exit of the application.
 659          * So force the release of the faulty lock.
 660          */
 661         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 662                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 663         }
 664         e1000_put_hw_semaphore_generic(hw);
 665
 666         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 667                 uint16_t mask;
 668
 669                 /*
 670                  * Phy lock should not fail in this early stage. If this is the case,
 671                  * it is due to an improper exit of the application.
 672                  * So force the release of the faulty lock.
 673                  */
 674                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 675                 if (hw->bus.func > E1000_FUNC_1)
 676                         mask <<= 2;
 677                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 678                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 679                                     hw->bus.func);
 680                 }
 681                 hw->mac.ops.release_swfw_sync(hw, mask);
 682
 683                 /*
 684                  * This one is more tricky since it is common to all ports; but
 685                  * swfw_sync retries last long enough (1s) to be almost sure that if
 686                  * lock can not be taken it is due to an improper lock of the
 687                  * semaphore.
 688                  */
 689                 mask = E1000_SWFW_EEP_SM;
 690                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 691                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 692                 }
 693                 hw->mac.ops.release_swfw_sync(hw, mask);
 694         }
 695
 696         return E1000_SUCCESS;
 697 }
 698
 699 /* Remove all ntuple filters of the device */
 700 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 701 {
 702         struct e1000_filter_info *filter_info =
 703                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 704         struct e1000_5tuple_filter *p_5tuple;
 705         struct e1000_2tuple_filter *p_2tuple;
 706
 707         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 708                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 709                         p_5tuple, entries);
 710                         rte_free(p_5tuple);
 711         }
 712         filter_info->fivetuple_mask = 0;
 713         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 714                 TAILQ_REMOVE(&filter_info->twotuple_list,
 715                         p_2tuple, entries);
 716                         rte_free(p_2tuple);
 717         }
 718         filter_info->twotuple_mask = 0;
 719
 720         return 0;
 721 }
 722
 723 /* Remove all flex filters of the device */
 724 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 725 {
 726         struct e1000_filter_info *filter_info =
 727                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 728         struct e1000_flex_filter *p_flex;
 729
 730         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 731                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 732                 rte_free(p_flex);
 733         }
 734         filter_info->flex_mask = 0;
 735
 736         return 0;
 737 }
 738
 739 static int
 740 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 741 {
 742         int error = 0;
 743         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 744         struct e1000_hw *hw =
 745                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 746         struct e1000_vfta * shadow_vfta =
 747                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 748         struct e1000_filter_info *filter_info =
 749                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 750         struct e1000_adapter *adapter =
 751                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 752
 753         uint32_t ctrl_ext;
 754
 755         eth_dev->dev_ops = &eth_igb_ops;
 756         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 757         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 758         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 759
 760         /* for secondary processes, we don't initialise any further as primary
 761          * has already done this work. Only check we don't need a different
 762          * RX function */
 763         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 764                 if (eth_dev->data->scattered_rx)
 765                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 766                 return 0;
 767         }
 768
 769         rte_eth_copy_pci_info(eth_dev, pci_dev);
 770
 771         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 772
 773         igb_identify_hardware(eth_dev, pci_dev);
 774         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 775                 error = -EIO;
 776                 goto err_late;
 777         }
 778
 779         e1000_get_bus_info(hw);
 780
 781         /* Reset any pending lock */
 782         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 783                 error = -EIO;
 784                 goto err_late;
 785         }
 786
 787         /* Finish initialization */
 788         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 789                 error = -EIO;
 790                 goto err_late;
 791         }
 792
 793         hw->mac.autoneg = 1;
 794         hw->phy.autoneg_wait_to_complete = 0;
 795         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 796
 797         /* Copper options */
 798         if (hw->phy.media_type == e1000_media_type_copper) {
 799                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 800                 hw->phy.disable_polarity_correction = 0;
 801                 hw->phy.ms_type = e1000_ms_hw_default;
 802         }
 803
 804         /*
 805          * Start from a known state, this is important in reading the nvm
 806          * and mac from that.
 807          */
 808         igb_pf_reset_hw(hw);
 809
 810         /* Make sure we have a good EEPROM before we read from it */
 811         if (e1000_validate_nvm_checksum(hw) < 0) {
 812                 /*
 813                  * Some PCI-E parts fail the first check due to
 814                  * the link being in sleep state, call it again,
 815                  * if it fails a second time its a real issue.
 816                  */
 817                 if (e1000_validate_nvm_checksum(hw) < 0) {
 818                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 819                         error = -EIO;
 820                         goto err_late;
 821                 }
 822         }
 823
 824         /* Read the permanent MAC address out of the EEPROM */
 825         if (e1000_read_mac_addr(hw) != 0) {
 826                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 827                 error = -EIO;
 828                 goto err_late;
 829         }
 830
 831         /* Allocate memory for storing MAC addresses */
 832         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 833                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 834         if (eth_dev->data->mac_addrs == NULL) {
 835                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 836                                                 "store MAC addresses",
 837                                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 838                 error = -ENOMEM;
 839                 goto err_late;
 840         }
 841
 842         /* Copy the permanent MAC address */
 843         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 844                         &eth_dev->data->mac_addrs[0]);
 845
 846         /* initialize the vfta */
 847         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 848
 849         /* Now initialize the hardware */
 850         if (igb_hardware_init(hw) != 0) {
 851                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 852                 rte_free(eth_dev->data->mac_addrs);
 853                 eth_dev->data->mac_addrs = NULL;
 854                 error = -ENODEV;
 855                 goto err_late;
 856         }
 857         hw->mac.get_link_status = 1;
 858         adapter->stopped = 0;
 859
 860         /* Indicate SOL/IDER usage */
 861         if (e1000_check_reset_block(hw) < 0) {
 862                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 863                                         "SOL/IDER session");
 864         }
 865
 866         /* initialize PF if max_vfs not zero */
 867         igb_pf_host_init(eth_dev);
 868
 869         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 870         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 871         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 872         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 873         E1000_WRITE_FLUSH(hw);
 874
 875         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 876                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 877                      pci_dev->id.device_id);
 878
 879         rte_intr_callback_register(&pci_dev->intr_handle,
 880                                    eth_igb_interrupt_handler,
 881                                    (void *)eth_dev);
 882
 883         /* enable uio/vfio intr/eventfd mapping */
 884         rte_intr_enable(&pci_dev->intr_handle);
 885
 886         /* enable support intr */
 887         igb_intr_enable(eth_dev);
 888
 889         /* initialize filter info */
 890         memset(filter_info, 0,
 891                sizeof(struct e1000_filter_info));
 892
 893         TAILQ_INIT(&filter_info->flex_list);
 894         TAILQ_INIT(&filter_info->twotuple_list);
 895         TAILQ_INIT(&filter_info->fivetuple_list);
 896
 897         TAILQ_INIT(&igb_filter_ntuple_list);
 898         TAILQ_INIT(&igb_filter_ethertype_list);
 899         TAILQ_INIT(&igb_filter_syn_list);
 900         TAILQ_INIT(&igb_filter_flex_list);
 901         TAILQ_INIT(&igb_filter_rss_list);
 902         TAILQ_INIT(&igb_flow_list);
 903
 904         return 0;
 905
 906 err_late:
 907         igb_hw_control_release(hw);
 908
 909         return error;
 910 }
 911
 912 static int
 913 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 914 {
 915         struct rte_pci_device *pci_dev;
 916         struct rte_intr_handle *intr_handle;
 917         struct e1000_hw *hw;
 918         struct e1000_adapter *adapter =
 919                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 920         struct e1000_filter_info *filter_info =
 921                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 922
 923         PMD_INIT_FUNC_TRACE();
 924
 925         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 926                 return -EPERM;
 927
 928         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 929         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 930         intr_handle = &pci_dev->intr_handle;
 931
 932         if (adapter->stopped == 0)
 933                 eth_igb_close(eth_dev);
 934
 935         eth_dev->dev_ops = NULL;
 936         eth_dev->rx_pkt_burst = NULL;
 937         eth_dev->tx_pkt_burst = NULL;
 938
 939         /* Reset any pending lock */
 940         igb_reset_swfw_lock(hw);
 941
 942         /* uninitialize PF if max_vfs not zero */
 943         igb_pf_host_uninit(eth_dev);
 944
 945         /* disable uio intr before callback unregister */
 946         rte_intr_disable(intr_handle);
 947         rte_intr_callback_unregister(intr_handle,
 948                                      eth_igb_interrupt_handler, eth_dev);
 949
 950         /* clear the SYN filter info */
 951         filter_info->syn_info = 0;
 952
 953         /* clear the ethertype filters info */
 954         filter_info->ethertype_mask = 0;
 955         memset(filter_info->ethertype_filters, 0,
 956                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
 957
 958         /* clear the rss filter info */
 959         memset(&filter_info->rss_info, 0,
 960                 sizeof(struct igb_rte_flow_rss_conf));
 961
 962         /* remove all ntuple filters of the device */
 963         igb_ntuple_filter_uninit(eth_dev);
 964
 965         /* remove all flex filters of the device */
 966         igb_flex_filter_uninit(eth_dev);
 967
 968         /* clear all the filters list */
 969         igb_filterlist_flush(eth_dev);
 970
 971         return 0;
 972 }
 973
 974 /*
 975  * Virtual Function device init
 976  */
 977 static int
 978 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 979 {
 980         struct rte_pci_device *pci_dev;
 981         struct rte_intr_handle *intr_handle;
 982         struct e1000_adapter *adapter =
 983                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 984         struct e1000_hw *hw =
 985                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 986         int diag;
 987         struct rte_ether_addr *perm_addr =
 988                 (struct rte_ether_addr *)hw->mac.perm_addr;
 989
 990         PMD_INIT_FUNC_TRACE();
 991
 992         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 993         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 994         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 995         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 996
 997         /* for secondary processes, we don't initialise any further as primary
 998          * has already done this work. Only check we don't need a different
 999          * RX function */
1000         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1001                 if (eth_dev->data->scattered_rx)
1002                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
1003                 return 0;
1004         }
1005
1006         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1007         rte_eth_copy_pci_info(eth_dev, pci_dev);
1008
1009         hw->device_id = pci_dev->id.device_id;
1010         hw->vendor_id = pci_dev->id.vendor_id;
1011         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1012         adapter->stopped = 0;
1013
1014         /* Initialize the shared code (base driver) */
1015         diag = e1000_setup_init_funcs(hw, TRUE);
1016         if (diag != 0) {
1017                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1018                         diag);
1019                 return -EIO;
1020         }
1021
1022         /* init_mailbox_params */
1023         hw->mbx.ops.init_params(hw);
1024
1025         /* Disable the interrupts for VF */
1026         igbvf_intr_disable(hw);
1027
1028         diag = hw->mac.ops.reset_hw(hw);
1029
1030         /* Allocate memory for storing MAC addresses */
1031         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
1032                 hw->mac.rar_entry_count, 0);
1033         if (eth_dev->data->mac_addrs == NULL) {
1034                 PMD_INIT_LOG(ERR,
1035                         "Failed to allocate %d bytes needed to store MAC "
1036                         "addresses",
1037                         RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1038                 return -ENOMEM;
1039         }
1040
1041         /* Generate a random MAC address, if none was assigned by PF. */
1042         if (rte_is_zero_ether_addr(perm_addr)) {
1043                 rte_eth_random_addr(perm_addr->addr_bytes);
1044                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1045                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1046                              "%02x:%02x:%02x:%02x:%02x:%02x",
1047                              perm_addr->addr_bytes[0],
1048                              perm_addr->addr_bytes[1],
1049                              perm_addr->addr_bytes[2],
1050                              perm_addr->addr_bytes[3],
1051                              perm_addr->addr_bytes[4],
1052                              perm_addr->addr_bytes[5]);
1053         }
1054
1055         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1056         if (diag) {
1057                 rte_free(eth_dev->data->mac_addrs);
1058                 eth_dev->data->mac_addrs = NULL;
1059                 return diag;
1060         }
1061         /* Copy the permanent MAC address */
1062         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1063                         &eth_dev->data->mac_addrs[0]);
1064
1065         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1066                      "mac.type=%s",
1067                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1068                      pci_dev->id.device_id, "igb_mac_82576_vf");
1069
1070         intr_handle = &pci_dev->intr_handle;
1071         rte_intr_callback_register(intr_handle,
1072                                    eth_igbvf_interrupt_handler, eth_dev);
1073
1074         return 0;
1075 }
1076
1077 static int
1078 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1079 {
1080         struct e1000_adapter *adapter =
1081                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1082         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1083
1084         PMD_INIT_FUNC_TRACE();
1085
1086         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1087                 return -EPERM;
1088
1089         if (adapter->stopped == 0)
1090                 igbvf_dev_close(eth_dev);
1091
1092         eth_dev->dev_ops = NULL;
1093         eth_dev->rx_pkt_burst = NULL;
1094         eth_dev->tx_pkt_burst = NULL;
1095
1096         /* disable uio intr before callback unregister */
1097         rte_intr_disable(&pci_dev->intr_handle);
1098         rte_intr_callback_unregister(&pci_dev->intr_handle,
1099                                      eth_igbvf_interrupt_handler,
1100                                      (void *)eth_dev);
1101
1102         return 0;
1103 }
1104
1105 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1106         struct rte_pci_device *pci_dev)
1107 {
1108         return rte_eth_dev_pci_generic_probe(pci_dev,
1109                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1110 }
1111
1112 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1113 {
1114         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1115 }
1116
1117 static struct rte_pci_driver rte_igb_pmd = {
1118         .id_table = pci_id_igb_map,
1119         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1120         .probe = eth_igb_pci_probe,
1121         .remove = eth_igb_pci_remove,
1122 };
1123
1124
1125 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1126         struct rte_pci_device *pci_dev)
1127 {
1128         return rte_eth_dev_pci_generic_probe(pci_dev,
1129                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1130 }
1131
1132 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1133 {
1134         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1135 }
1136
1137 /*
1138  * virtual function driver struct
1139  */
1140 static struct rte_pci_driver rte_igbvf_pmd = {
1141         .id_table = pci_id_igbvf_map,
1142         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1143         .probe = eth_igbvf_pci_probe,
1144         .remove = eth_igbvf_pci_remove,
1145 };
1146
1147 static void
1148 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1149 {
1150         struct e1000_hw *hw =
1151                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1152         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1153         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1154         rctl |= E1000_RCTL_VFE;
1155         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1156 }
1157
1158 static int
1159 igb_check_mq_mode(struct rte_eth_dev *dev)
1160 {
1161         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1162         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1163         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1164         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1165
1166         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1167             tx_mq_mode == ETH_MQ_TX_DCB ||
1168             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1169                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1170                 return -EINVAL;
1171         }
1172         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1173                 /* Check multi-queue mode.
1174                  * To no break software we accept ETH_MQ_RX_NONE as this might
1175                  * be used to turn off VLAN filter.
1176                  */
1177
1178                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1179                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1180                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1181                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1182                 } else {
1183                         /* Only support one queue on VFs.
1184                          * RSS together with SRIOV is not supported.
1185                          */
1186                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1187                                         " wrong mq_mode rx %d.",
1188                                         rx_mq_mode);
1189                         return -EINVAL;
1190                 }
1191                 /* TX mode is not used here, so mode might be ignored.*/
1192                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1193                         /* SRIOV only works in VMDq enable mode */
1194                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1195                                         " TX mode %d is not supported. "
1196                                         " Driver will behave as %d mode.",
1197                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1198                 }
1199
1200                 /* check valid queue number */
1201                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1202                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1203                                         " only support one queue on VFs.");
1204                         return -EINVAL;
1205                 }
1206         } else {
1207                 /* To no break software that set invalid mode, only display
1208                  * warning if invalid mode is used.
1209                  */
1210                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1211                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1212                     rx_mq_mode != ETH_MQ_RX_RSS) {
1213                         /* RSS together with VMDq not supported*/
1214                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1215                                      rx_mq_mode);
1216                         return -EINVAL;
1217                 }
1218
1219                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1220                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1221                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1222                                         " Due to txmode is meaningless in this"
1223                                         " driver, just ignore.",
1224                                         tx_mq_mode);
1225                 }
1226         }
1227         return 0;
1228 }
1229
1230 static int
1231 eth_igb_configure(struct rte_eth_dev *dev)
1232 {
1233         struct e1000_interrupt *intr =
1234                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1235         int ret;
1236
1237         PMD_INIT_FUNC_TRACE();
1238
1239         /* multipe queue mode checking */
1240         ret  = igb_check_mq_mode(dev);
1241         if (ret != 0) {
1242                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1243                             ret);
1244                 return ret;
1245         }
1246
1247         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1248         PMD_INIT_FUNC_TRACE();
1249
1250         return 0;
1251 }
1252
1253 static void
1254 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1255                      bool enable)
1256 {
1257         struct e1000_hw *hw =
1258                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1259         uint32_t tctl, rctl;
1260
1261         tctl = E1000_READ_REG(hw, E1000_TCTL);
1262         rctl = E1000_READ_REG(hw, E1000_RCTL);
1263
1264         if (enable) {
1265                 /* enable Tx/Rx */
1266                 tctl |= E1000_TCTL_EN;
1267                 rctl |= E1000_RCTL_EN;
1268         } else {
1269                 /* disable Tx/Rx */
1270                 tctl &= ~E1000_TCTL_EN;
1271                 rctl &= ~E1000_RCTL_EN;
1272         }
1273         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1274         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1275         E1000_WRITE_FLUSH(hw);
1276 }
1277
1278 static int
1279 eth_igb_start(struct rte_eth_dev *dev)
1280 {
1281         struct e1000_hw *hw =
1282                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1283         struct e1000_adapter *adapter =
1284                 E1000_DEV_PRIVATE(dev->data->dev_private);
1285         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1286         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1287         int ret, mask;
1288         uint32_t intr_vector = 0;
1289         uint32_t ctrl_ext;
1290         uint32_t *speeds;
1291         int num_speeds;
1292         bool autoneg;
1293
1294         PMD_INIT_FUNC_TRACE();
1295
1296         /* disable uio/vfio intr/eventfd mapping */
1297         rte_intr_disable(intr_handle);
1298
1299         /* Power up the phy. Needed to make the link go Up */
1300         eth_igb_dev_set_link_up(dev);
1301
1302         /*
1303          * Packet Buffer Allocation (PBA)
1304          * Writing PBA sets the receive portion of the buffer
1305          * the remainder is used for the transmit buffer.
1306          */
1307         if (hw->mac.type == e1000_82575) {
1308                 uint32_t pba;
1309
1310                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1311                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1312         }
1313
1314         /* Put the address into the Receive Address Array */
1315         e1000_rar_set(hw, hw->mac.addr, 0);
1316
1317         /* Initialize the hardware */
1318         if (igb_hardware_init(hw)) {
1319                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1320                 return -EIO;
1321         }
1322         adapter->stopped = 0;
1323
1324         E1000_WRITE_REG(hw, E1000_VET,
1325                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1326
1327         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1328         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1329         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1330         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1331         E1000_WRITE_FLUSH(hw);
1332
1333         /* configure PF module if SRIOV enabled */
1334         igb_pf_host_configure(dev);
1335
1336         /* check and configure queue intr-vector mapping */
1337         if ((rte_intr_cap_multiple(intr_handle) ||
1338              !RTE_ETH_DEV_SRIOV(dev).active) &&
1339             dev->data->dev_conf.intr_conf.rxq != 0) {
1340                 intr_vector = dev->data->nb_rx_queues;
1341                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1342                         return -1;
1343         }
1344
1345         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1346                 intr_handle->intr_vec =
1347                         rte_zmalloc("intr_vec",
1348                                     dev->data->nb_rx_queues * sizeof(int), 0);
1349                 if (intr_handle->intr_vec == NULL) {
1350                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1351                                      " intr_vec", dev->data->nb_rx_queues);
1352                         return -ENOMEM;
1353                 }
1354         }
1355
1356         /* confiugre msix for rx interrupt */
1357         eth_igb_configure_msix_intr(dev);
1358
1359         /* Configure for OS presence */
1360         igb_init_manageability(hw);
1361
1362         eth_igb_tx_init(dev);
1363
1364         /* This can fail when allocating mbufs for descriptor rings */
1365         ret = eth_igb_rx_init(dev);
1366         if (ret) {
1367                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1368                 igb_dev_clear_queues(dev);
1369                 return ret;
1370         }
1371
1372         e1000_clear_hw_cntrs_base_generic(hw);
1373
1374         /*
1375          * VLAN Offload Settings
1376          */
1377         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1378                         ETH_VLAN_EXTEND_MASK;
1379         ret = eth_igb_vlan_offload_set(dev, mask);
1380         if (ret) {
1381                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1382                 igb_dev_clear_queues(dev);
1383                 return ret;
1384         }
1385
1386         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1387                 /* Enable VLAN filter since VMDq always use VLAN filter */
1388                 igb_vmdq_vlan_hw_filter_enable(dev);
1389         }
1390
1391         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1392                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1393                 (hw->mac.type == e1000_i211)) {
1394                 /* Configure EITR with the maximum possible value (0xFFFF) */
1395                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1396         }
1397
1398         /* Setup link speed and duplex */
1399         speeds = &dev->data->dev_conf.link_speeds;
1400         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1401                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1402                 hw->mac.autoneg = 1;
1403         } else {
1404                 num_speeds = 0;
1405                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1406
1407                 /* Reset */
1408                 hw->phy.autoneg_advertised = 0;
1409
1410                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1411                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1412                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1413                         num_speeds = -1;
1414                         goto error_invalid_config;
1415                 }
1416                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1417                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1418                         num_speeds++;
1419                 }
1420                 if (*speeds & ETH_LINK_SPEED_10M) {
1421                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1422                         num_speeds++;
1423                 }
1424                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1425                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1426                         num_speeds++;
1427                 }
1428                 if (*speeds & ETH_LINK_SPEED_100M) {
1429                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1430                         num_speeds++;
1431                 }
1432                 if (*speeds & ETH_LINK_SPEED_1G) {
1433                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1434                         num_speeds++;
1435                 }
1436                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1437                         goto error_invalid_config;
1438
1439                 /* Set/reset the mac.autoneg based on the link speed,
1440                  * fixed or not
1441                  */
1442                 if (!autoneg) {
1443                         hw->mac.autoneg = 0;
1444                         hw->mac.forced_speed_duplex =
1445                                         hw->phy.autoneg_advertised;
1446                 } else {
1447                         hw->mac.autoneg = 1;
1448                 }
1449         }
1450
1451         e1000_setup_link(hw);
1452
1453         if (rte_intr_allow_others(intr_handle)) {
1454                 /* check if lsc interrupt is enabled */
1455                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1456                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1457                 else
1458                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1459         } else {
1460                 rte_intr_callback_unregister(intr_handle,
1461                                              eth_igb_interrupt_handler,
1462                                              (void *)dev);
1463                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1464                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1465                                      " no intr multiplex");
1466         }
1467
1468         /* check if rxq interrupt is enabled */
1469         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1470             rte_intr_dp_is_en(intr_handle))
1471                 eth_igb_rxq_interrupt_setup(dev);
1472
1473         /* enable uio/vfio intr/eventfd mapping */
1474         rte_intr_enable(intr_handle);
1475
1476         /* resume enabled intr since hw reset */
1477         igb_intr_enable(dev);
1478
1479         /* restore all types filter */
1480         igb_filter_restore(dev);
1481
1482         eth_igb_rxtx_control(dev, true);
1483         eth_igb_link_update(dev, 0);
1484
1485         PMD_INIT_LOG(DEBUG, "<<");
1486
1487         return 0;
1488
1489 error_invalid_config:
1490         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1491                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1492         igb_dev_clear_queues(dev);
1493         return -EINVAL;
1494 }
1495
1496 /*********************************************************************
1497  *
1498  *  This routine disables all traffic on the adapter by issuing a
1499  *  global reset on the MAC.
1500  *
1501  **********************************************************************/
1502 static void
1503 eth_igb_stop(struct rte_eth_dev *dev)
1504 {
1505         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1506         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1507         struct rte_eth_link link;
1508         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1509
1510         eth_igb_rxtx_control(dev, false);
1511
1512         igb_intr_disable(dev);
1513
1514         /* disable intr eventfd mapping */
1515         rte_intr_disable(intr_handle);
1516
1517         igb_pf_reset_hw(hw);
1518         E1000_WRITE_REG(hw, E1000_WUC, 0);
1519
1520         /* Set bit for Go Link disconnect */
1521         if (hw->mac.type >= e1000_82580) {
1522                 uint32_t phpm_reg;
1523
1524                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1525                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1526                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1527         }
1528
1529         /* Power down the phy. Needed to make the link go Down */
1530         eth_igb_dev_set_link_down(dev);
1531
1532         igb_dev_clear_queues(dev);
1533
1534         /* clear the recorded link status */
1535         memset(&link, 0, sizeof(link));
1536         rte_eth_linkstatus_set(dev, &link);
1537
1538         if (!rte_intr_allow_others(intr_handle))
1539                 /* resume to the default handler */
1540                 rte_intr_callback_register(intr_handle,
1541                                            eth_igb_interrupt_handler,
1542                                            (void *)dev);
1543
1544         /* Clean datapath event and queue/vec mapping */
1545         rte_intr_efd_disable(intr_handle);
1546         if (intr_handle->intr_vec != NULL) {
1547                 rte_free(intr_handle->intr_vec);
1548                 intr_handle->intr_vec = NULL;
1549         }
1550 }
1551
1552 static int
1553 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1554 {
1555         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1556
1557         if (hw->phy.media_type == e1000_media_type_copper)
1558                 e1000_power_up_phy(hw);
1559         else
1560                 e1000_power_up_fiber_serdes_link(hw);
1561
1562         return 0;
1563 }
1564
1565 static int
1566 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1567 {
1568         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1569
1570         if (hw->phy.media_type == e1000_media_type_copper)
1571                 e1000_power_down_phy(hw);
1572         else
1573                 e1000_shutdown_fiber_serdes_link(hw);
1574
1575         return 0;
1576 }
1577
1578 static void
1579 eth_igb_close(struct rte_eth_dev *dev)
1580 {
1581         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1582         struct e1000_adapter *adapter =
1583                 E1000_DEV_PRIVATE(dev->data->dev_private);
1584         struct rte_eth_link link;
1585         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1586         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1587
1588         eth_igb_stop(dev);
1589         adapter->stopped = 1;
1590
1591         e1000_phy_hw_reset(hw);
1592         igb_release_manageability(hw);
1593         igb_hw_control_release(hw);
1594
1595         /* Clear bit for Go Link disconnect */
1596         if (hw->mac.type >= e1000_82580) {
1597                 uint32_t phpm_reg;
1598
1599                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1600                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1601                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1602         }
1603
1604         igb_dev_free_queues(dev);
1605
1606         if (intr_handle->intr_vec) {
1607                 rte_free(intr_handle->intr_vec);
1608                 intr_handle->intr_vec = NULL;
1609         }
1610
1611         memset(&link, 0, sizeof(link));
1612         rte_eth_linkstatus_set(dev, &link);
1613 }
1614
1615 /*
1616  * Reset PF device.
1617  */
1618 static int
1619 eth_igb_reset(struct rte_eth_dev *dev)
1620 {
1621         int ret;
1622
1623         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1624          * its VF to make them align with it. The detailed notification
1625          * mechanism is PMD specific and is currently not implemented.
1626          * To avoid unexpected behavior in VF, currently reset of PF with
1627          * SR-IOV activation is not supported. It might be supported later.
1628          */
1629         if (dev->data->sriov.active)
1630                 return -ENOTSUP;
1631
1632         ret = eth_igb_dev_uninit(dev);
1633         if (ret)
1634                 return ret;
1635
1636         ret = eth_igb_dev_init(dev);
1637
1638         return ret;
1639 }
1640
1641
1642 static int
1643 igb_get_rx_buffer_size(struct e1000_hw *hw)
1644 {
1645         uint32_t rx_buf_size;
1646         if (hw->mac.type == e1000_82576) {
1647                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1648         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1649                 /* PBS needs to be translated according to a lookup table */
1650                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1651                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1652                 rx_buf_size = (rx_buf_size << 10);
1653         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1654                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1655         } else {
1656                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1657         }
1658
1659         return rx_buf_size;
1660 }
1661
1662 /*********************************************************************
1663  *
1664  *  Initialize the hardware
1665  *
1666  **********************************************************************/
1667 static int
1668 igb_hardware_init(struct e1000_hw *hw)
1669 {
1670         uint32_t rx_buf_size;
1671         int diag;
1672
1673         /* Let the firmware know the OS is in control */
1674         igb_hw_control_acquire(hw);
1675
1676         /*
1677          * These parameters control the automatic generation (Tx) and
1678          * response (Rx) to Ethernet PAUSE frames.
1679          * - High water mark should allow for at least two standard size (1518)
1680          *   frames to be received after sending an XOFF.
1681          * - Low water mark works best when it is very near the high water mark.
1682          *   This allows the receiver to restart by sending XON when it has
1683          *   drained a bit. Here we use an arbitrary value of 1500 which will
1684          *   restart after one full frame is pulled from the buffer. There
1685          *   could be several smaller frames in the buffer and if so they will
1686          *   not trigger the XON until their total number reduces the buffer
1687          *   by 1500.
1688          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1689          */
1690         rx_buf_size = igb_get_rx_buffer_size(hw);
1691
1692         hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1693         hw->fc.low_water = hw->fc.high_water - 1500;
1694         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1695         hw->fc.send_xon = 1;
1696
1697         /* Set Flow control, use the tunable location if sane */
1698         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1699                 hw->fc.requested_mode = igb_fc_setting;
1700         else
1701                 hw->fc.requested_mode = e1000_fc_none;
1702
1703         /* Issue a global reset */
1704         igb_pf_reset_hw(hw);
1705         E1000_WRITE_REG(hw, E1000_WUC, 0);
1706
1707         diag = e1000_init_hw(hw);
1708         if (diag < 0)
1709                 return diag;
1710
1711         E1000_WRITE_REG(hw, E1000_VET,
1712                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1713         e1000_get_phy_info(hw);
1714         e1000_check_for_link(hw);
1715
1716         return 0;
1717 }
1718
1719 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1720 static void
1721 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1722 {
1723         int pause_frames;
1724
1725         uint64_t old_gprc  = stats->gprc;
1726         uint64_t old_gptc  = stats->gptc;
1727         uint64_t old_tpr   = stats->tpr;
1728         uint64_t old_tpt   = stats->tpt;
1729         uint64_t old_rpthc = stats->rpthc;
1730         uint64_t old_hgptc = stats->hgptc;
1731
1732         if(hw->phy.media_type == e1000_media_type_copper ||
1733             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1734                 stats->symerrs +=
1735                     E1000_READ_REG(hw,E1000_SYMERRS);
1736                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1737         }
1738
1739         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1740         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1741         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1742         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1743
1744         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1745         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1746         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1747         stats->dc += E1000_READ_REG(hw, E1000_DC);
1748         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1749         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1750         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1751         /*
1752         ** For watchdog management we need to know if we have been
1753         ** paused during the last interval, so capture that here.
1754         */
1755         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1756         stats->xoffrxc += pause_frames;
1757         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1758         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1759         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1760         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1761         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1762         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1763         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1764         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1765         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1766         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1767         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1768         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1769
1770         /* For the 64-bit byte counters the low dword must be read first. */
1771         /* Both registers clear on the read of the high dword */
1772
1773         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1774         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1775         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1776         stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1777         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1778         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1779         stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1780
1781         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1782         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1783         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1784         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1785         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1786
1787         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1788         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1789
1790         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1791         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1792         stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1793         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1794         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1795         stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1796
1797         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1798         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1799         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1800         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1801         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1802         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1803         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1804         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1805
1806         /* Interrupt Counts */
1807
1808         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1809         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1810         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1811         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1812         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1813         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1814         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1815         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1816         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1817
1818         /* Host to Card Statistics */
1819
1820         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1821         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1822         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1823         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1824         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1825         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1826         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1827         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1828         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1829         stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1830         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1831         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1832         stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1833         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1834         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1835         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1836
1837         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1838         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1839         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1840         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1841         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1842         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1843 }
1844
1845 static int
1846 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1847 {
1848         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1849         struct e1000_hw_stats *stats =
1850                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1851
1852         igb_read_stats_registers(hw, stats);
1853
1854         if (rte_stats == NULL)
1855                 return -EINVAL;
1856
1857         /* Rx Errors */
1858         rte_stats->imissed = stats->mpc;
1859         rte_stats->ierrors = stats->crcerrs +
1860                              stats->rlec + stats->ruc + stats->roc +
1861                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1862
1863         /* Tx Errors */
1864         rte_stats->oerrors = stats->ecol + stats->latecol;
1865
1866         rte_stats->ipackets = stats->gprc;
1867         rte_stats->opackets = stats->gptc;
1868         rte_stats->ibytes   = stats->gorc;
1869         rte_stats->obytes   = stats->gotc;
1870         return 0;
1871 }
1872
1873 static void
1874 eth_igb_stats_reset(struct rte_eth_dev *dev)
1875 {
1876         struct e1000_hw_stats *hw_stats =
1877                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1878
1879         /* HW registers are cleared on read */
1880         eth_igb_stats_get(dev, NULL);
1881
1882         /* Reset software totals */
1883         memset(hw_stats, 0, sizeof(*hw_stats));
1884 }
1885
1886 static void
1887 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1888 {
1889         struct e1000_hw_stats *stats =
1890                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1891
1892         /* HW registers are cleared on read */
1893         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1894
1895         /* Reset software totals */
1896         memset(stats, 0, sizeof(*stats));
1897 }
1898
1899 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1900         struct rte_eth_xstat_name *xstats_names,
1901         __rte_unused unsigned int size)
1902 {
1903         unsigned i;
1904
1905         if (xstats_names == NULL)
1906                 return IGB_NB_XSTATS;
1907
1908         /* Note: limit checked in rte_eth_xstats_names() */
1909
1910         for (i = 0; i < IGB_NB_XSTATS; i++) {
1911                 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1912                         sizeof(xstats_names[i].name));
1913         }
1914
1915         return IGB_NB_XSTATS;
1916 }
1917
1918 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1919                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1920                 unsigned int limit)
1921 {
1922         unsigned int i;
1923
1924         if (!ids) {
1925                 if (xstats_names == NULL)
1926                         return IGB_NB_XSTATS;
1927
1928                 for (i = 0; i < IGB_NB_XSTATS; i++)
1929                         strlcpy(xstats_names[i].name,
1930                                 rte_igb_stats_strings[i].name,
1931                                 sizeof(xstats_names[i].name));
1932
1933                 return IGB_NB_XSTATS;
1934
1935         } else {
1936                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1937
1938                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1939                                 IGB_NB_XSTATS);
1940
1941                 for (i = 0; i < limit; i++) {
1942                         if (ids[i] >= IGB_NB_XSTATS) {
1943                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1944                                 return -1;
1945                         }
1946                         strcpy(xstats_names[i].name,
1947                                         xstats_names_copy[ids[i]].name);
1948                 }
1949                 return limit;
1950         }
1951 }
1952
1953 static int
1954 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1955                    unsigned n)
1956 {
1957         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1958         struct e1000_hw_stats *hw_stats =
1959                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1960         unsigned i;
1961
1962         if (n < IGB_NB_XSTATS)
1963                 return IGB_NB_XSTATS;
1964
1965         igb_read_stats_registers(hw, hw_stats);
1966
1967         /* If this is a reset xstats is NULL, and we have cleared the
1968          * registers by reading them.
1969          */
1970         if (!xstats)
1971                 return 0;
1972
1973         /* Extended stats */
1974         for (i = 0; i < IGB_NB_XSTATS; i++) {
1975                 xstats[i].id = i;
1976                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1977                         rte_igb_stats_strings[i].offset);
1978         }
1979
1980         return IGB_NB_XSTATS;
1981 }
1982
1983 static int
1984 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1985                 uint64_t *values, unsigned int n)
1986 {
1987         unsigned int i;
1988
1989         if (!ids) {
1990                 struct e1000_hw *hw =
1991                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1992                 struct e1000_hw_stats *hw_stats =
1993                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1994
1995                 if (n < IGB_NB_XSTATS)
1996                         return IGB_NB_XSTATS;
1997
1998                 igb_read_stats_registers(hw, hw_stats);
1999
2000                 /* If this is a reset xstats is NULL, and we have cleared the
2001                  * registers by reading them.
2002                  */
2003                 if (!values)
2004                         return 0;
2005
2006                 /* Extended stats */
2007                 for (i = 0; i < IGB_NB_XSTATS; i++)
2008                         values[i] = *(uint64_t *)(((char *)hw_stats) +
2009                                         rte_igb_stats_strings[i].offset);
2010
2011                 return IGB_NB_XSTATS;
2012
2013         } else {
2014                 uint64_t values_copy[IGB_NB_XSTATS];
2015
2016                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2017                                 IGB_NB_XSTATS);
2018
2019                 for (i = 0; i < n; i++) {
2020                         if (ids[i] >= IGB_NB_XSTATS) {
2021                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2022                                 return -1;
2023                         }
2024                         values[i] = values_copy[ids[i]];
2025                 }
2026                 return n;
2027         }
2028 }
2029
2030 static void
2031 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2032 {
2033         /* Good Rx packets, include VF loopback */
2034         UPDATE_VF_STAT(E1000_VFGPRC,
2035             hw_stats->last_gprc, hw_stats->gprc);
2036
2037         /* Good Rx octets, include VF loopback */
2038         UPDATE_VF_STAT(E1000_VFGORC,
2039             hw_stats->last_gorc, hw_stats->gorc);
2040
2041         /* Good Tx packets, include VF loopback */
2042         UPDATE_VF_STAT(E1000_VFGPTC,
2043             hw_stats->last_gptc, hw_stats->gptc);
2044
2045         /* Good Tx octets, include VF loopback */
2046         UPDATE_VF_STAT(E1000_VFGOTC,
2047             hw_stats->last_gotc, hw_stats->gotc);
2048
2049         /* Rx Multicst packets */
2050         UPDATE_VF_STAT(E1000_VFMPRC,
2051             hw_stats->last_mprc, hw_stats->mprc);
2052
2053         /* Good Rx loopback packets */
2054         UPDATE_VF_STAT(E1000_VFGPRLBC,
2055             hw_stats->last_gprlbc, hw_stats->gprlbc);
2056
2057         /* Good Rx loopback octets */
2058         UPDATE_VF_STAT(E1000_VFGORLBC,
2059             hw_stats->last_gorlbc, hw_stats->gorlbc);
2060
2061         /* Good Tx loopback packets */
2062         UPDATE_VF_STAT(E1000_VFGPTLBC,
2063             hw_stats->last_gptlbc, hw_stats->gptlbc);
2064
2065         /* Good Tx loopback octets */
2066         UPDATE_VF_STAT(E1000_VFGOTLBC,
2067             hw_stats->last_gotlbc, hw_stats->gotlbc);
2068 }
2069
2070 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2071                                      struct rte_eth_xstat_name *xstats_names,
2072                                      __rte_unused unsigned limit)
2073 {
2074         unsigned i;
2075
2076         if (xstats_names != NULL)
2077                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2078                         strlcpy(xstats_names[i].name,
2079                                 rte_igbvf_stats_strings[i].name,
2080                                 sizeof(xstats_names[i].name));
2081                 }
2082         return IGBVF_NB_XSTATS;
2083 }
2084
2085 static int
2086 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2087                      unsigned n)
2088 {
2089         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2090         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2091                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2092         unsigned i;
2093
2094         if (n < IGBVF_NB_XSTATS)
2095                 return IGBVF_NB_XSTATS;
2096
2097         igbvf_read_stats_registers(hw, hw_stats);
2098
2099         if (!xstats)
2100                 return 0;
2101
2102         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2103                 xstats[i].id = i;
2104                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2105                         rte_igbvf_stats_strings[i].offset);
2106         }
2107
2108         return IGBVF_NB_XSTATS;
2109 }
2110
2111 static int
2112 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2113 {
2114         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2115         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2116                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2117
2118         igbvf_read_stats_registers(hw, hw_stats);
2119
2120         if (rte_stats == NULL)
2121                 return -EINVAL;
2122
2123         rte_stats->ipackets = hw_stats->gprc;
2124         rte_stats->ibytes = hw_stats->gorc;
2125         rte_stats->opackets = hw_stats->gptc;
2126         rte_stats->obytes = hw_stats->gotc;
2127         return 0;
2128 }
2129
2130 static void
2131 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2132 {
2133         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2134                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2135
2136         /* Sync HW register to the last stats */
2137         eth_igbvf_stats_get(dev, NULL);
2138
2139         /* reset HW current stats*/
2140         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2141                offsetof(struct e1000_vf_stats, gprc));
2142 }
2143
2144 static int
2145 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2146                        size_t fw_size)
2147 {
2148         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2149         struct e1000_fw_version fw;
2150         int ret;
2151
2152         e1000_get_fw_version(hw, &fw);
2153
2154         switch (hw->mac.type) {
2155         case e1000_i210:
2156         case e1000_i211:
2157                 if (!(e1000_get_flash_presence_i210(hw))) {
2158                         ret = snprintf(fw_version, fw_size,
2159                                  "%2d.%2d-%d",
2160                                  fw.invm_major, fw.invm_minor,
2161                                  fw.invm_img_type);
2162                         break;
2163                 }
2164                 /* fall through */
2165         default:
2166                 /* if option rom is valid, display its version too */
2167                 if (fw.or_valid) {
2168                         ret = snprintf(fw_version, fw_size,
2169                                  "%d.%d, 0x%08x, %d.%d.%d",
2170                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2171                                  fw.or_major, fw.or_build, fw.or_patch);
2172                 /* no option rom */
2173                 } else {
2174                         if (fw.etrack_id != 0X0000) {
2175                                 ret = snprintf(fw_version, fw_size,
2176                                          "%d.%d, 0x%08x",
2177                                          fw.eep_major, fw.eep_minor,
2178                                          fw.etrack_id);
2179                         } else {
2180                                 ret = snprintf(fw_version, fw_size,
2181                                          "%d.%d.%d",
2182                                          fw.eep_major, fw.eep_minor,
2183                                          fw.eep_build);
2184                         }
2185                 }
2186                 break;
2187         }
2188
2189         ret += 1; /* add the size of '\0' */
2190         if (fw_size < (u32)ret)
2191                 return ret;
2192         else
2193                 return 0;
2194 }
2195
2196 static int
2197 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2198 {
2199         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200
2201         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2202         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2203         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2204         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2205         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2206                                     dev_info->rx_queue_offload_capa;
2207         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2208         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2209                                     dev_info->tx_queue_offload_capa;
2210
2211         switch (hw->mac.type) {
2212         case e1000_82575:
2213                 dev_info->max_rx_queues = 4;
2214                 dev_info->max_tx_queues = 4;
2215                 dev_info->max_vmdq_pools = 0;
2216                 break;
2217
2218         case e1000_82576:
2219                 dev_info->max_rx_queues = 16;
2220                 dev_info->max_tx_queues = 16;
2221                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2222                 dev_info->vmdq_queue_num = 16;
2223                 break;
2224
2225         case e1000_82580:
2226                 dev_info->max_rx_queues = 8;
2227                 dev_info->max_tx_queues = 8;
2228                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2229                 dev_info->vmdq_queue_num = 8;
2230                 break;
2231
2232         case e1000_i350:
2233                 dev_info->max_rx_queues = 8;
2234                 dev_info->max_tx_queues = 8;
2235                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2236                 dev_info->vmdq_queue_num = 8;
2237                 break;
2238
2239         case e1000_i354:
2240                 dev_info->max_rx_queues = 8;
2241                 dev_info->max_tx_queues = 8;
2242                 break;
2243
2244         case e1000_i210:
2245                 dev_info->max_rx_queues = 4;
2246                 dev_info->max_tx_queues = 4;
2247                 dev_info->max_vmdq_pools = 0;
2248                 break;
2249
2250         case e1000_i211:
2251                 dev_info->max_rx_queues = 2;
2252                 dev_info->max_tx_queues = 2;
2253                 dev_info->max_vmdq_pools = 0;
2254                 break;
2255
2256         default:
2257                 /* Should not happen */
2258                 return -EINVAL;
2259         }
2260         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2261         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2262         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2263
2264         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2265                 .rx_thresh = {
2266                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2267                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2268                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2269                 },
2270                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2271                 .rx_drop_en = 0,
2272                 .offloads = 0,
2273         };
2274
2275         dev_info->default_txconf = (struct rte_eth_txconf) {
2276                 .tx_thresh = {
2277                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2278                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2279                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2280                 },
2281                 .offloads = 0,
2282         };
2283
2284         dev_info->rx_desc_lim = rx_desc_lim;
2285         dev_info->tx_desc_lim = tx_desc_lim;
2286
2287         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2288                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2289                         ETH_LINK_SPEED_1G;
2290
2291         dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2292         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2293
2294         return 0;
2295 }
2296
2297 static const uint32_t *
2298 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2299 {
2300         static const uint32_t ptypes[] = {
2301                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2302                 RTE_PTYPE_L2_ETHER,
2303                 RTE_PTYPE_L3_IPV4,
2304                 RTE_PTYPE_L3_IPV4_EXT,
2305                 RTE_PTYPE_L3_IPV6,
2306                 RTE_PTYPE_L3_IPV6_EXT,
2307                 RTE_PTYPE_L4_TCP,
2308                 RTE_PTYPE_L4_UDP,
2309                 RTE_PTYPE_L4_SCTP,
2310                 RTE_PTYPE_TUNNEL_IP,
2311                 RTE_PTYPE_INNER_L3_IPV6,
2312                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2313                 RTE_PTYPE_INNER_L4_TCP,
2314                 RTE_PTYPE_INNER_L4_UDP,
2315                 RTE_PTYPE_UNKNOWN
2316         };
2317
2318         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2319             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2320                 return ptypes;
2321         return NULL;
2322 }
2323
2324 static int
2325 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2326 {
2327         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2328
2329         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2330         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2331         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2332         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2333                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2334                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2335                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2336                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2337                                 DEV_TX_OFFLOAD_TCP_TSO;
2338         switch (hw->mac.type) {
2339         case e1000_vfadapt:
2340                 dev_info->max_rx_queues = 2;
2341                 dev_info->max_tx_queues = 2;
2342                 break;
2343         case e1000_vfadapt_i350:
2344                 dev_info->max_rx_queues = 1;
2345                 dev_info->max_tx_queues = 1;
2346                 break;
2347         default:
2348                 /* Should not happen */
2349                 return -EINVAL;
2350         }
2351
2352         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2353         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2354                                     dev_info->rx_queue_offload_capa;
2355         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2356         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2357                                     dev_info->tx_queue_offload_capa;
2358
2359         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2360                 .rx_thresh = {
2361                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2362                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2363                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2364                 },
2365                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2366                 .rx_drop_en = 0,
2367                 .offloads = 0,
2368         };
2369
2370         dev_info->default_txconf = (struct rte_eth_txconf) {
2371                 .tx_thresh = {
2372                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2373                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2374                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2375                 },
2376                 .offloads = 0,
2377         };
2378
2379         dev_info->rx_desc_lim = rx_desc_lim;
2380         dev_info->tx_desc_lim = tx_desc_lim;
2381
2382         return 0;
2383 }
2384
2385 /* return 0 means link status changed, -1 means not changed */
2386 static int
2387 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2388 {
2389         struct e1000_hw *hw =
2390                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2391         struct rte_eth_link link;
2392         int link_check, count;
2393
2394         link_check = 0;
2395         hw->mac.get_link_status = 1;
2396
2397         /* possible wait-to-complete in up to 9 seconds */
2398         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2399                 /* Read the real link status */
2400                 switch (hw->phy.media_type) {
2401                 case e1000_media_type_copper:
2402                         /* Do the work to read phy */
2403                         e1000_check_for_link(hw);
2404                         link_check = !hw->mac.get_link_status;
2405                         break;
2406
2407                 case e1000_media_type_fiber:
2408                         e1000_check_for_link(hw);
2409                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2410                                       E1000_STATUS_LU);
2411                         break;
2412
2413                 case e1000_media_type_internal_serdes:
2414                         e1000_check_for_link(hw);
2415                         link_check = hw->mac.serdes_has_link;
2416                         break;
2417
2418                 /* VF device is type_unknown */
2419                 case e1000_media_type_unknown:
2420                         eth_igbvf_link_update(hw);
2421                         link_check = !hw->mac.get_link_status;
2422                         break;
2423
2424                 default:
2425                         break;
2426                 }
2427                 if (link_check || wait_to_complete == 0)
2428                         break;
2429                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2430         }
2431         memset(&link, 0, sizeof(link));
2432
2433         /* Now we check if a transition has happened */
2434         if (link_check) {
2435                 uint16_t duplex, speed;
2436                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2437                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2438                                 ETH_LINK_FULL_DUPLEX :
2439                                 ETH_LINK_HALF_DUPLEX;
2440                 link.link_speed = speed;
2441                 link.link_status = ETH_LINK_UP;
2442                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2443                                 ETH_LINK_SPEED_FIXED);
2444         } else if (!link_check) {
2445                 link.link_speed = 0;
2446                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2447                 link.link_status = ETH_LINK_DOWN;
2448                 link.link_autoneg = ETH_LINK_FIXED;
2449         }
2450
2451         return rte_eth_linkstatus_set(dev, &link);
2452 }
2453
2454 /*
2455  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2456  * For ASF and Pass Through versions of f/w this means
2457  * that the driver is loaded.
2458  */
2459 static void
2460 igb_hw_control_acquire(struct e1000_hw *hw)
2461 {
2462         uint32_t ctrl_ext;
2463
2464         /* Let firmware know the driver has taken over */
2465         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2466         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2467 }
2468
2469 /*
2470  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2471  * For ASF and Pass Through versions of f/w this means that the
2472  * driver is no longer loaded.
2473  */
2474 static void
2475 igb_hw_control_release(struct e1000_hw *hw)
2476 {
2477         uint32_t ctrl_ext;
2478
2479         /* Let firmware taken over control of h/w */
2480         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2481         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2482                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2483 }
2484
2485 /*
2486  * Bit of a misnomer, what this really means is
2487  * to enable OS management of the system... aka
2488  * to disable special hardware management features.
2489  */
2490 static void
2491 igb_init_manageability(struct e1000_hw *hw)
2492 {
2493         if (e1000_enable_mng_pass_thru(hw)) {
2494                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2495                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2496
2497                 /* disable hardware interception of ARP */
2498                 manc &= ~(E1000_MANC_ARP_EN);
2499
2500                 /* enable receiving management packets to the host */
2501                 manc |= E1000_MANC_EN_MNG2HOST;
2502                 manc2h |= 1 << 5;  /* Mng Port 623 */
2503                 manc2h |= 1 << 6;  /* Mng Port 664 */
2504                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2505                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2506         }
2507 }
2508
2509 static void
2510 igb_release_manageability(struct e1000_hw *hw)
2511 {
2512         if (e1000_enable_mng_pass_thru(hw)) {
2513                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2514
2515                 manc |= E1000_MANC_ARP_EN;
2516                 manc &= ~E1000_MANC_EN_MNG2HOST;
2517
2518                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2519         }
2520 }
2521
2522 static void
2523 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2524 {
2525         struct e1000_hw *hw =
2526                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2527         uint32_t rctl;
2528
2529         rctl = E1000_READ_REG(hw, E1000_RCTL);
2530         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2531         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2532 }
2533
2534 static void
2535 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2536 {
2537         struct e1000_hw *hw =
2538                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539         uint32_t rctl;
2540
2541         rctl = E1000_READ_REG(hw, E1000_RCTL);
2542         rctl &= (~E1000_RCTL_UPE);
2543         if (dev->data->all_multicast == 1)
2544                 rctl |= E1000_RCTL_MPE;
2545         else
2546                 rctl &= (~E1000_RCTL_MPE);
2547         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2548 }
2549
2550 static void
2551 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2552 {
2553         struct e1000_hw *hw =
2554                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2555         uint32_t rctl;
2556
2557         rctl = E1000_READ_REG(hw, E1000_RCTL);
2558         rctl |= E1000_RCTL_MPE;
2559         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2560 }
2561
2562 static void
2563 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2564 {
2565         struct e1000_hw *hw =
2566                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2567         uint32_t rctl;
2568
2569         if (dev->data->promiscuous == 1)
2570                 return; /* must remain in all_multicast mode */
2571         rctl = E1000_READ_REG(hw, E1000_RCTL);
2572         rctl &= (~E1000_RCTL_MPE);
2573         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2574 }
2575
2576 static int
2577 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2578 {
2579         struct e1000_hw *hw =
2580                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2581         struct e1000_vfta * shadow_vfta =
2582                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2583         uint32_t vfta;
2584         uint32_t vid_idx;
2585         uint32_t vid_bit;
2586
2587         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2588                               E1000_VFTA_ENTRY_MASK);
2589         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2590         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2591         if (on)
2592                 vfta |= vid_bit;
2593         else
2594                 vfta &= ~vid_bit;
2595         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2596
2597         /* update local VFTA copy */
2598         shadow_vfta->vfta[vid_idx] = vfta;
2599
2600         return 0;
2601 }
2602
2603 static int
2604 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2605                       enum rte_vlan_type vlan_type,
2606                       uint16_t tpid)
2607 {
2608         struct e1000_hw *hw =
2609                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2610         uint32_t reg, qinq;
2611
2612         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2613         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2614
2615         /* only outer TPID of double VLAN can be configured*/
2616         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2617                 reg = E1000_READ_REG(hw, E1000_VET);
2618                 reg = (reg & (~E1000_VET_VET_EXT)) |
2619                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2620                 E1000_WRITE_REG(hw, E1000_VET, reg);
2621
2622                 return 0;
2623         }
2624
2625         /* all other TPID values are read-only*/
2626         PMD_DRV_LOG(ERR, "Not supported");
2627
2628         return -ENOTSUP;
2629 }
2630
2631 static void
2632 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2633 {
2634         struct e1000_hw *hw =
2635                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2636         uint32_t reg;
2637
2638         /* Filter Table Disable */
2639         reg = E1000_READ_REG(hw, E1000_RCTL);
2640         reg &= ~E1000_RCTL_CFIEN;
2641         reg &= ~E1000_RCTL_VFE;
2642         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2643 }
2644
2645 static void
2646 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2647 {
2648         struct e1000_hw *hw =
2649                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2650         struct e1000_vfta * shadow_vfta =
2651                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2652         uint32_t reg;
2653         int i;
2654
2655         /* Filter Table Enable, CFI not used for packet acceptance */
2656         reg = E1000_READ_REG(hw, E1000_RCTL);
2657         reg &= ~E1000_RCTL_CFIEN;
2658         reg |= E1000_RCTL_VFE;
2659         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2660
2661         /* restore VFTA table */
2662         for (i = 0; i < IGB_VFTA_SIZE; i++)
2663                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2664 }
2665
2666 static void
2667 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2668 {
2669         struct e1000_hw *hw =
2670                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2671         uint32_t reg;
2672
2673         /* VLAN Mode Disable */
2674         reg = E1000_READ_REG(hw, E1000_CTRL);
2675         reg &= ~E1000_CTRL_VME;
2676         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2677 }
2678
2679 static void
2680 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2681 {
2682         struct e1000_hw *hw =
2683                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2684         uint32_t reg;
2685
2686         /* VLAN Mode Enable */
2687         reg = E1000_READ_REG(hw, E1000_CTRL);
2688         reg |= E1000_CTRL_VME;
2689         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2690 }
2691
2692 static void
2693 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2694 {
2695         struct e1000_hw *hw =
2696                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2697         uint32_t reg;
2698
2699         /* CTRL_EXT: Extended VLAN */
2700         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2701         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2702         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2703
2704         /* Update maximum packet length */
2705         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2706                 E1000_WRITE_REG(hw, E1000_RLPML,
2707                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2708                                                 VLAN_TAG_SIZE);
2709 }
2710
2711 static void
2712 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2713 {
2714         struct e1000_hw *hw =
2715                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2716         uint32_t reg;
2717
2718         /* CTRL_EXT: Extended VLAN */
2719         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2720         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2721         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2722
2723         /* Update maximum packet length */
2724         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2725                 E1000_WRITE_REG(hw, E1000_RLPML,
2726                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2727                                                 2 * VLAN_TAG_SIZE);
2728 }
2729
2730 static int
2731 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2732 {
2733         struct rte_eth_rxmode *rxmode;
2734
2735         rxmode = &dev->data->dev_conf.rxmode;
2736         if(mask & ETH_VLAN_STRIP_MASK){
2737                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2738                         igb_vlan_hw_strip_enable(dev);
2739                 else
2740                         igb_vlan_hw_strip_disable(dev);
2741         }
2742
2743         if(mask & ETH_VLAN_FILTER_MASK){
2744                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2745                         igb_vlan_hw_filter_enable(dev);
2746                 else
2747                         igb_vlan_hw_filter_disable(dev);
2748         }
2749
2750         if(mask & ETH_VLAN_EXTEND_MASK){
2751                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2752                         igb_vlan_hw_extend_enable(dev);
2753                 else
2754                         igb_vlan_hw_extend_disable(dev);
2755         }
2756
2757         return 0;
2758 }
2759
2760
2761 /**
2762  * It enables the interrupt mask and then enable the interrupt.
2763  *
2764  * @param dev
2765  *  Pointer to struct rte_eth_dev.
2766  * @param on
2767  *  Enable or Disable
2768  *
2769  * @return
2770  *  - On success, zero.
2771  *  - On failure, a negative value.
2772  */
2773 static int
2774 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2775 {
2776         struct e1000_interrupt *intr =
2777                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2778
2779         if (on)
2780                 intr->mask |= E1000_ICR_LSC;
2781         else
2782                 intr->mask &= ~E1000_ICR_LSC;
2783
2784         return 0;
2785 }
2786
2787 /* It clears the interrupt causes and enables the interrupt.
2788  * It will be called once only during nic initialized.
2789  *
2790  * @param dev
2791  *  Pointer to struct rte_eth_dev.
2792  *
2793  * @return
2794  *  - On success, zero.
2795  *  - On failure, a negative value.
2796  */
2797 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2798 {
2799         uint32_t mask, regval;
2800         int ret;
2801         struct e1000_hw *hw =
2802                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2803         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2804         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2805         int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2806         struct rte_eth_dev_info dev_info;
2807
2808         memset(&dev_info, 0, sizeof(dev_info));
2809         ret = eth_igb_infos_get(dev, &dev_info);
2810         if (ret != 0)
2811                 return ret;
2812
2813         mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2814         regval = E1000_READ_REG(hw, E1000_EIMS);
2815         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2816
2817         return 0;
2818 }
2819
2820 /*
2821  * It reads ICR and gets interrupt causes, check it and set a bit flag
2822  * to update link status.
2823  *
2824  * @param dev
2825  *  Pointer to struct rte_eth_dev.
2826  *
2827  * @return
2828  *  - On success, zero.
2829  *  - On failure, a negative value.
2830  */
2831 static int
2832 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2833 {
2834         uint32_t icr;
2835         struct e1000_hw *hw =
2836                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2837         struct e1000_interrupt *intr =
2838                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2839
2840         igb_intr_disable(dev);
2841
2842         /* read-on-clear nic registers here */
2843         icr = E1000_READ_REG(hw, E1000_ICR);
2844
2845         intr->flags = 0;
2846         if (icr & E1000_ICR_LSC) {
2847                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2848         }
2849
2850         if (icr & E1000_ICR_VMMB)
2851                 intr->flags |= E1000_FLAG_MAILBOX;
2852
2853         return 0;
2854 }
2855
2856 /*
2857  * It executes link_update after knowing an interrupt is prsent.
2858  *
2859  * @param dev
2860  *  Pointer to struct rte_eth_dev.
2861  *
2862  * @return
2863  *  - On success, zero.
2864  *  - On failure, a negative value.
2865  */
2866 static int
2867 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2868                          struct rte_intr_handle *intr_handle)
2869 {
2870         struct e1000_hw *hw =
2871                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2872         struct e1000_interrupt *intr =
2873                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2874         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2875         struct rte_eth_link link;
2876         int ret;
2877
2878         if (intr->flags & E1000_FLAG_MAILBOX) {
2879                 igb_pf_mbx_process(dev);
2880                 intr->flags &= ~E1000_FLAG_MAILBOX;
2881         }
2882
2883         igb_intr_enable(dev);
2884         rte_intr_ack(intr_handle);
2885
2886         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2887                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2888
2889                 /* set get_link_status to check register later */
2890                 hw->mac.get_link_status = 1;
2891                 ret = eth_igb_link_update(dev, 0);
2892
2893                 /* check if link has changed */
2894                 if (ret < 0)
2895                         return 0;
2896
2897                 rte_eth_linkstatus_get(dev, &link);
2898                 if (link.link_status) {
2899                         PMD_INIT_LOG(INFO,
2900                                      " Port %d: Link Up - speed %u Mbps - %s",
2901                                      dev->data->port_id,
2902                                      (unsigned)link.link_speed,
2903                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2904                                      "full-duplex" : "half-duplex");
2905                 } else {
2906                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2907                                      dev->data->port_id);
2908                 }
2909
2910                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2911                              pci_dev->addr.domain,
2912                              pci_dev->addr.bus,
2913                              pci_dev->addr.devid,
2914                              pci_dev->addr.function);
2915                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2916                                               NULL);
2917         }
2918
2919         return 0;
2920 }
2921
2922 /**
2923  * Interrupt handler which shall be registered at first.
2924  *
2925  * @param handle
2926  *  Pointer to interrupt handle.
2927  * @param param
2928  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2929  *
2930  * @return
2931  *  void
2932  */
2933 static void
2934 eth_igb_interrupt_handler(void *param)
2935 {
2936         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2937
2938         eth_igb_interrupt_get_status(dev);
2939         eth_igb_interrupt_action(dev, dev->intr_handle);
2940 }
2941
2942 static int
2943 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2944 {
2945         uint32_t eicr;
2946         struct e1000_hw *hw =
2947                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2948         struct e1000_interrupt *intr =
2949                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2950
2951         igbvf_intr_disable(hw);
2952
2953         /* read-on-clear nic registers here */
2954         eicr = E1000_READ_REG(hw, E1000_EICR);
2955         intr->flags = 0;
2956
2957         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2958                 intr->flags |= E1000_FLAG_MAILBOX;
2959
2960         return 0;
2961 }
2962
2963 void igbvf_mbx_process(struct rte_eth_dev *dev)
2964 {
2965         struct e1000_hw *hw =
2966                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2967         struct e1000_mbx_info *mbx = &hw->mbx;
2968         u32 in_msg = 0;
2969
2970         /* peek the message first */
2971         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2972
2973         /* PF reset VF event */
2974         if (in_msg == E1000_PF_CONTROL_MSG) {
2975                 /* dummy mbx read to ack pf */
2976                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2977                         return;
2978                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2979                                               NULL);
2980         }
2981 }
2982
2983 static int
2984 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2985 {
2986         struct e1000_interrupt *intr =
2987                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2988
2989         if (intr->flags & E1000_FLAG_MAILBOX) {
2990                 igbvf_mbx_process(dev);
2991                 intr->flags &= ~E1000_FLAG_MAILBOX;
2992         }
2993
2994         igbvf_intr_enable(dev);
2995         rte_intr_ack(intr_handle);
2996
2997         return 0;
2998 }
2999
3000 static void
3001 eth_igbvf_interrupt_handler(void *param)
3002 {
3003         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3004
3005         eth_igbvf_interrupt_get_status(dev);
3006         eth_igbvf_interrupt_action(dev, dev->intr_handle);
3007 }
3008
3009 static int
3010 eth_igb_led_on(struct rte_eth_dev *dev)
3011 {
3012         struct e1000_hw *hw;
3013
3014         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3015         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3016 }
3017
3018 static int
3019 eth_igb_led_off(struct rte_eth_dev *dev)
3020 {
3021         struct e1000_hw *hw;
3022
3023         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3024         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3025 }
3026
3027 static int
3028 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3029 {
3030         struct e1000_hw *hw;
3031         uint32_t ctrl;
3032         int tx_pause;
3033         int rx_pause;
3034
3035         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3036         fc_conf->pause_time = hw->fc.pause_time;
3037         fc_conf->high_water = hw->fc.high_water;
3038         fc_conf->low_water = hw->fc.low_water;
3039         fc_conf->send_xon = hw->fc.send_xon;
3040         fc_conf->autoneg = hw->mac.autoneg;
3041
3042         /*
3043          * Return rx_pause and tx_pause status according to actual setting of
3044          * the TFCE and RFCE bits in the CTRL register.
3045          */
3046         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3047         if (ctrl & E1000_CTRL_TFCE)
3048                 tx_pause = 1;
3049         else
3050                 tx_pause = 0;
3051
3052         if (ctrl & E1000_CTRL_RFCE)
3053                 rx_pause = 1;
3054         else
3055                 rx_pause = 0;
3056
3057         if (rx_pause && tx_pause)
3058                 fc_conf->mode = RTE_FC_FULL;
3059         else if (rx_pause)
3060                 fc_conf->mode = RTE_FC_RX_PAUSE;
3061         else if (tx_pause)
3062                 fc_conf->mode = RTE_FC_TX_PAUSE;
3063         else
3064                 fc_conf->mode = RTE_FC_NONE;
3065
3066         return 0;
3067 }
3068
3069 static int
3070 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3071 {
3072         struct e1000_hw *hw;
3073         int err;
3074         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3075                 e1000_fc_none,
3076                 e1000_fc_rx_pause,
3077                 e1000_fc_tx_pause,
3078                 e1000_fc_full
3079         };
3080         uint32_t rx_buf_size;
3081         uint32_t max_high_water;
3082         uint32_t rctl;
3083
3084         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3085         if (fc_conf->autoneg != hw->mac.autoneg)
3086                 return -ENOTSUP;
3087         rx_buf_size = igb_get_rx_buffer_size(hw);
3088         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3089
3090         /* At least reserve one Ethernet frame for watermark */
3091         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3092         if ((fc_conf->high_water > max_high_water) ||
3093             (fc_conf->high_water < fc_conf->low_water)) {
3094                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3095                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3096                 return -EINVAL;
3097         }
3098
3099         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3100         hw->fc.pause_time     = fc_conf->pause_time;
3101         hw->fc.high_water     = fc_conf->high_water;
3102         hw->fc.low_water      = fc_conf->low_water;
3103         hw->fc.send_xon       = fc_conf->send_xon;
3104
3105         err = e1000_setup_link_generic(hw);
3106         if (err == E1000_SUCCESS) {
3107
3108                 /* check if we want to forward MAC frames - driver doesn't have native
3109                  * capability to do that, so we'll write the registers ourselves */
3110
3111                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3112
3113                 /* set or clear MFLCN.PMCF bit depending on configuration */
3114                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3115                         rctl |= E1000_RCTL_PMCF;
3116                 else
3117                         rctl &= ~E1000_RCTL_PMCF;
3118
3119                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3120                 E1000_WRITE_FLUSH(hw);
3121
3122                 return 0;
3123         }
3124
3125         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3126         return -EIO;
3127 }
3128
3129 #define E1000_RAH_POOLSEL_SHIFT      (18)
3130 static int
3131 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3132                 uint32_t index, uint32_t pool)
3133 {
3134         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3135         uint32_t rah;
3136
3137         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3138         rah = E1000_READ_REG(hw, E1000_RAH(index));
3139         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3140         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3141         return 0;
3142 }
3143
3144 static void
3145 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3146 {
3147         uint8_t addr[RTE_ETHER_ADDR_LEN];
3148         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3149
3150         memset(addr, 0, sizeof(addr));
3151
3152         e1000_rar_set(hw, addr, index);
3153 }
3154
3155 static int
3156 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3157                                 struct rte_ether_addr *addr)
3158 {
3159         eth_igb_rar_clear(dev, 0);
3160         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3161
3162         return 0;
3163 }
3164 /*
3165  * Virtual Function operations
3166  */
3167 static void
3168 igbvf_intr_disable(struct e1000_hw *hw)
3169 {
3170         PMD_INIT_FUNC_TRACE();
3171
3172         /* Clear interrupt mask to stop from interrupts being generated */
3173         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3174
3175         E1000_WRITE_FLUSH(hw);
3176 }
3177
3178 static void
3179 igbvf_stop_adapter(struct rte_eth_dev *dev)
3180 {
3181         u32 reg_val;
3182         u16 i;
3183         struct rte_eth_dev_info dev_info;
3184         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3185         int ret;
3186
3187         memset(&dev_info, 0, sizeof(dev_info));
3188         ret = eth_igbvf_infos_get(dev, &dev_info);
3189         if (ret != 0)
3190                 return;
3191
3192         /* Clear interrupt mask to stop from interrupts being generated */
3193         igbvf_intr_disable(hw);
3194
3195         /* Clear any pending interrupts, flush previous writes */
3196         E1000_READ_REG(hw, E1000_EICR);
3197
3198         /* Disable the transmit unit.  Each queue must be disabled. */
3199         for (i = 0; i < dev_info.max_tx_queues; i++)
3200                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3201
3202         /* Disable the receive unit by stopping each queue */
3203         for (i = 0; i < dev_info.max_rx_queues; i++) {
3204                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3205                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3206                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3207                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3208                         ;
3209         }
3210
3211         /* flush all queues disables */
3212         E1000_WRITE_FLUSH(hw);
3213         msec_delay(2);
3214 }
3215
3216 static int eth_igbvf_link_update(struct e1000_hw *hw)
3217 {
3218         struct e1000_mbx_info *mbx = &hw->mbx;
3219         struct e1000_mac_info *mac = &hw->mac;
3220         int ret_val = E1000_SUCCESS;
3221
3222         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3223
3224         /*
3225          * We only want to run this if there has been a rst asserted.
3226          * in this case that could mean a link change, device reset,
3227          * or a virtual function reset
3228          */
3229
3230         /* If we were hit with a reset or timeout drop the link */
3231         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3232                 mac->get_link_status = TRUE;
3233
3234         if (!mac->get_link_status)
3235                 goto out;
3236
3237         /* if link status is down no point in checking to see if pf is up */
3238         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3239                 goto out;
3240
3241         /* if we passed all the tests above then the link is up and we no
3242          * longer need to check for link */
3243         mac->get_link_status = FALSE;
3244
3245 out:
3246         return ret_val;
3247 }
3248
3249
3250 static int
3251 igbvf_dev_configure(struct rte_eth_dev *dev)
3252 {
3253         struct rte_eth_conf* conf = &dev->data->dev_conf;
3254
3255         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3256                      dev->data->port_id);
3257
3258         /*
3259          * VF has no ability to enable/disable HW CRC
3260          * Keep the persistent behavior the same as Host PF
3261          */
3262 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3263         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3264                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3265                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3266         }
3267 #else
3268         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3269                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3270                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3271         }
3272 #endif
3273
3274         return 0;
3275 }
3276
3277 static int
3278 igbvf_dev_start(struct rte_eth_dev *dev)
3279 {
3280         struct e1000_hw *hw =
3281                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3282         struct e1000_adapter *adapter =
3283                 E1000_DEV_PRIVATE(dev->data->dev_private);
3284         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3285         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3286         int ret;
3287         uint32_t intr_vector = 0;
3288
3289         PMD_INIT_FUNC_TRACE();
3290
3291         hw->mac.ops.reset_hw(hw);
3292         adapter->stopped = 0;
3293
3294         /* Set all vfta */
3295         igbvf_set_vfta_all(dev,1);
3296
3297         eth_igbvf_tx_init(dev);
3298
3299         /* This can fail when allocating mbufs for descriptor rings */
3300         ret = eth_igbvf_rx_init(dev);
3301         if (ret) {
3302                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3303                 igb_dev_clear_queues(dev);
3304                 return ret;
3305         }
3306
3307         /* check and configure queue intr-vector mapping */
3308         if (rte_intr_cap_multiple(intr_handle) &&
3309             dev->data->dev_conf.intr_conf.rxq) {
3310                 intr_vector = dev->data->nb_rx_queues;
3311                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3312                 if (ret)
3313                         return ret;
3314         }
3315
3316         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3317                 intr_handle->intr_vec =
3318                         rte_zmalloc("intr_vec",
3319                                     dev->data->nb_rx_queues * sizeof(int), 0);
3320                 if (!intr_handle->intr_vec) {
3321                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3322                                      " intr_vec", dev->data->nb_rx_queues);
3323                         return -ENOMEM;
3324                 }
3325         }
3326
3327         eth_igbvf_configure_msix_intr(dev);
3328
3329         /* enable uio/vfio intr/eventfd mapping */
3330         rte_intr_enable(intr_handle);
3331
3332         /* resume enabled intr since hw reset */
3333         igbvf_intr_enable(dev);
3334
3335         return 0;
3336 }
3337
3338 static void
3339 igbvf_dev_stop(struct rte_eth_dev *dev)
3340 {
3341         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3342         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3343
3344         PMD_INIT_FUNC_TRACE();
3345
3346         igbvf_stop_adapter(dev);
3347
3348         /*
3349           * Clear what we set, but we still keep shadow_vfta to
3350           * restore after device starts
3351           */
3352         igbvf_set_vfta_all(dev,0);
3353
3354         igb_dev_clear_queues(dev);
3355
3356         /* disable intr eventfd mapping */
3357         rte_intr_disable(intr_handle);
3358
3359         /* Clean datapath event and queue/vec mapping */
3360         rte_intr_efd_disable(intr_handle);
3361         if (intr_handle->intr_vec) {
3362                 rte_free(intr_handle->intr_vec);
3363                 intr_handle->intr_vec = NULL;
3364         }
3365 }
3366
3367 static void
3368 igbvf_dev_close(struct rte_eth_dev *dev)
3369 {
3370         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3371         struct e1000_adapter *adapter =
3372                 E1000_DEV_PRIVATE(dev->data->dev_private);
3373         struct rte_ether_addr addr;
3374
3375         PMD_INIT_FUNC_TRACE();
3376
3377         e1000_reset_hw(hw);
3378
3379         igbvf_dev_stop(dev);
3380         adapter->stopped = 1;
3381         igb_dev_free_queues(dev);
3382
3383         /**
3384          * reprogram the RAR with a zero mac address,
3385          * to ensure that the VF traffic goes to the PF
3386          * after stop, close and detach of the VF.
3387          **/
3388
3389         memset(&addr, 0, sizeof(addr));
3390         igbvf_default_mac_addr_set(dev, &addr);
3391 }
3392
3393 static void
3394 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3395 {
3396         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3397
3398         /* Set both unicast and multicast promisc */
3399         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3400 }
3401
3402 static void
3403 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3404 {
3405         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3406
3407         /* If in allmulticast mode leave multicast promisc */
3408         if (dev->data->all_multicast == 1)
3409                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3410         else
3411                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3412 }
3413
3414 static void
3415 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3416 {
3417         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3418
3419         /* In promiscuous mode multicast promisc already set */
3420         if (dev->data->promiscuous == 0)
3421                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3422 }
3423
3424 static void
3425 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3426 {
3427         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3428
3429         /* In promiscuous mode leave multicast promisc enabled */
3430         if (dev->data->promiscuous == 0)
3431                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3432 }
3433
3434 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3435 {
3436         struct e1000_mbx_info *mbx = &hw->mbx;
3437         uint32_t msgbuf[2];
3438         s32 err;
3439
3440         /* After set vlan, vlan strip will also be enabled in igb driver*/
3441         msgbuf[0] = E1000_VF_SET_VLAN;
3442         msgbuf[1] = vid;
3443         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3444         if (on)
3445                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3446
3447         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3448         if (err)
3449                 goto mbx_err;
3450
3451         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3452         if (err)
3453                 goto mbx_err;
3454
3455         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3456         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3457                 err = -EINVAL;
3458
3459 mbx_err:
3460         return err;
3461 }
3462
3463 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3464 {
3465         struct e1000_hw *hw =
3466                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3467         struct e1000_vfta * shadow_vfta =
3468                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3469         int i = 0, j = 0, vfta = 0, mask = 1;
3470
3471         for (i = 0; i < IGB_VFTA_SIZE; i++){
3472                 vfta = shadow_vfta->vfta[i];
3473                 if(vfta){
3474                         mask = 1;
3475                         for (j = 0; j < 32; j++){
3476                                 if(vfta & mask)
3477                                         igbvf_set_vfta(hw,
3478                                                 (uint16_t)((i<<5)+j), on);
3479                                 mask<<=1;
3480                         }
3481                 }
3482         }
3483
3484 }
3485
3486 static int
3487 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3488 {
3489         struct e1000_hw *hw =
3490                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3491         struct e1000_vfta * shadow_vfta =
3492                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3493         uint32_t vid_idx = 0;
3494         uint32_t vid_bit = 0;
3495         int ret = 0;
3496
3497         PMD_INIT_FUNC_TRACE();
3498
3499         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3500         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3501         if(ret){
3502                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3503                 return ret;
3504         }
3505         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3506         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3507
3508         /*Save what we set and retore it after device reset*/
3509         if (on)
3510                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3511         else
3512                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3513
3514         return 0;
3515 }
3516
3517 static int
3518 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3519 {
3520         struct e1000_hw *hw =
3521                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3522
3523         /* index is not used by rar_set() */
3524         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3525         return 0;
3526 }
3527
3528
3529 static int
3530 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3531                         struct rte_eth_rss_reta_entry64 *reta_conf,
3532                         uint16_t reta_size)
3533 {
3534         uint8_t i, j, mask;
3535         uint32_t reta, r;
3536         uint16_t idx, shift;
3537         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3538
3539         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3540                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3541                         "(%d) doesn't match the number hardware can supported "
3542                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3543                 return -EINVAL;
3544         }
3545
3546         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3547                 idx = i / RTE_RETA_GROUP_SIZE;
3548                 shift = i % RTE_RETA_GROUP_SIZE;
3549                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3550                                                 IGB_4_BIT_MASK);
3551                 if (!mask)
3552                         continue;
3553                 if (mask == IGB_4_BIT_MASK)
3554                         r = 0;
3555                 else
3556                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3557                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3558                         if (mask & (0x1 << j))
3559                                 reta |= reta_conf[idx].reta[shift + j] <<
3560                                                         (CHAR_BIT * j);
3561                         else
3562                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3563                 }
3564                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3565         }
3566
3567         return 0;
3568 }
3569
3570 static int
3571 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3572                        struct rte_eth_rss_reta_entry64 *reta_conf,
3573                        uint16_t reta_size)
3574 {
3575         uint8_t i, j, mask;
3576         uint32_t reta;
3577         uint16_t idx, shift;
3578         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3579
3580         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3581                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3582                         "(%d) doesn't match the number hardware can supported "
3583                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3584                 return -EINVAL;
3585         }
3586
3587         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3588                 idx = i / RTE_RETA_GROUP_SIZE;
3589                 shift = i % RTE_RETA_GROUP_SIZE;
3590                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3591                                                 IGB_4_BIT_MASK);
3592                 if (!mask)
3593                         continue;
3594                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3595                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3596                         if (mask & (0x1 << j))
3597                                 reta_conf[idx].reta[shift + j] =
3598                                         ((reta >> (CHAR_BIT * j)) &
3599                                                 IGB_8_BIT_MASK);
3600                 }
3601         }
3602
3603         return 0;
3604 }
3605
3606 int
3607 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3608                         struct rte_eth_syn_filter *filter,
3609                         bool add)
3610 {
3611         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3612         struct e1000_filter_info *filter_info =
3613                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3614         uint32_t synqf, rfctl;
3615
3616         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3617                 return -EINVAL;
3618
3619         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3620
3621         if (add) {
3622                 if (synqf & E1000_SYN_FILTER_ENABLE)
3623                         return -EINVAL;
3624
3625                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3626                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3627
3628                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3629                 if (filter->hig_pri)
3630                         rfctl |= E1000_RFCTL_SYNQFP;
3631                 else
3632                         rfctl &= ~E1000_RFCTL_SYNQFP;
3633
3634                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3635         } else {
3636                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3637                         return -ENOENT;
3638                 synqf = 0;
3639         }
3640
3641         filter_info->syn_info = synqf;
3642         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3643         E1000_WRITE_FLUSH(hw);
3644         return 0;
3645 }
3646
3647 static int
3648 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3649                         struct rte_eth_syn_filter *filter)
3650 {
3651         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3652         uint32_t synqf, rfctl;
3653
3654         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3655         if (synqf & E1000_SYN_FILTER_ENABLE) {
3656                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3657                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3658                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3659                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3660                 return 0;
3661         }
3662
3663         return -ENOENT;
3664 }
3665
3666 static int
3667 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3668                         enum rte_filter_op filter_op,
3669                         void *arg)
3670 {
3671         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3672         int ret;
3673
3674         MAC_TYPE_FILTER_SUP(hw->mac.type);
3675
3676         if (filter_op == RTE_ETH_FILTER_NOP)
3677                 return 0;
3678
3679         if (arg == NULL) {
3680                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3681                             filter_op);
3682                 return -EINVAL;
3683         }
3684
3685         switch (filter_op) {
3686         case RTE_ETH_FILTER_ADD:
3687                 ret = eth_igb_syn_filter_set(dev,
3688                                 (struct rte_eth_syn_filter *)arg,
3689                                 TRUE);
3690                 break;
3691         case RTE_ETH_FILTER_DELETE:
3692                 ret = eth_igb_syn_filter_set(dev,
3693                                 (struct rte_eth_syn_filter *)arg,
3694                                 FALSE);
3695                 break;
3696         case RTE_ETH_FILTER_GET:
3697                 ret = eth_igb_syn_filter_get(dev,
3698                                 (struct rte_eth_syn_filter *)arg);
3699                 break;
3700         default:
3701                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3702                 ret = -EINVAL;
3703                 break;
3704         }
3705
3706         return ret;
3707 }
3708
3709 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3710 static inline int
3711 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3712                         struct e1000_2tuple_filter_info *filter_info)
3713 {
3714         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3715                 return -EINVAL;
3716         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3717                 return -EINVAL;  /* filter index is out of range. */
3718         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3719                 return -EINVAL;  /* flags is invalid. */
3720
3721         switch (filter->dst_port_mask) {
3722         case UINT16_MAX:
3723                 filter_info->dst_port_mask = 0;
3724                 filter_info->dst_port = filter->dst_port;
3725                 break;
3726         case 0:
3727                 filter_info->dst_port_mask = 1;
3728                 break;
3729         default:
3730                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3731                 return -EINVAL;
3732         }
3733
3734         switch (filter->proto_mask) {
3735         case UINT8_MAX:
3736                 filter_info->proto_mask = 0;
3737                 filter_info->proto = filter->proto;
3738                 break;
3739         case 0:
3740                 filter_info->proto_mask = 1;
3741                 break;
3742         default:
3743                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3744                 return -EINVAL;
3745         }
3746
3747         filter_info->priority = (uint8_t)filter->priority;
3748         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3749                 filter_info->tcp_flags = filter->tcp_flags;
3750         else
3751                 filter_info->tcp_flags = 0;
3752
3753         return 0;
3754 }
3755
3756 static inline struct e1000_2tuple_filter *
3757 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3758                         struct e1000_2tuple_filter_info *key)
3759 {
3760         struct e1000_2tuple_filter *it;
3761
3762         TAILQ_FOREACH(it, filter_list, entries) {
3763                 if (memcmp(key, &it->filter_info,
3764                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3765                         return it;
3766                 }
3767         }
3768         return NULL;
3769 }
3770
3771 /* inject a igb 2tuple filter to HW */
3772 static inline void
3773 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3774                            struct e1000_2tuple_filter *filter)
3775 {
3776         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3777         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3778         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3779         int i;
3780
3781         i = filter->index;
3782         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3783         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3784                 imir |= E1000_IMIR_PORT_BP;
3785         else
3786                 imir &= ~E1000_IMIR_PORT_BP;
3787
3788         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3789
3790         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3791         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3792         ttqf |= (uint32_t)(filter->filter_info.proto &
3793                                                 E1000_TTQF_PROTOCOL_MASK);
3794         if (filter->filter_info.proto_mask == 0)
3795                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3796
3797         /* tcp flags bits setting. */
3798         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3799                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3800                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3801                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3802                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3803                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3804                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3805                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3806                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3807                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3808                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3809                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3810                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3811         } else {
3812                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3813         }
3814         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3815         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3816         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3817 }
3818
3819 /*
3820  * igb_add_2tuple_filter - add a 2tuple filter
3821  *
3822  * @param
3823  * dev: Pointer to struct rte_eth_dev.
3824  * ntuple_filter: ponter to the filter that will be added.
3825  *
3826  * @return
3827  *    - On success, zero.
3828  *    - On failure, a negative value.
3829  */
3830 static int
3831 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3832                         struct rte_eth_ntuple_filter *ntuple_filter)
3833 {
3834         struct e1000_filter_info *filter_info =
3835                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3836         struct e1000_2tuple_filter *filter;
3837         int i, ret;
3838
3839         filter = rte_zmalloc("e1000_2tuple_filter",
3840                         sizeof(struct e1000_2tuple_filter), 0);
3841         if (filter == NULL)
3842                 return -ENOMEM;
3843
3844         ret = ntuple_filter_to_2tuple(ntuple_filter,
3845                                       &filter->filter_info);
3846         if (ret < 0) {
3847                 rte_free(filter);
3848                 return ret;
3849         }
3850         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3851                                          &filter->filter_info) != NULL) {
3852                 PMD_DRV_LOG(ERR, "filter exists.");
3853                 rte_free(filter);
3854                 return -EEXIST;
3855         }
3856         filter->queue = ntuple_filter->queue;
3857
3858         /*
3859          * look for an unused 2tuple filter index,
3860          * and insert the filter to list.
3861          */
3862         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3863                 if (!(filter_info->twotuple_mask & (1 << i))) {
3864                         filter_info->twotuple_mask |= 1 << i;
3865                         filter->index = i;
3866                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3867                                           filter,
3868                                           entries);
3869                         break;
3870                 }
3871         }
3872         if (i >= E1000_MAX_TTQF_FILTERS) {
3873                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3874                 rte_free(filter);
3875                 return -ENOSYS;
3876         }
3877
3878         igb_inject_2uple_filter(dev, filter);
3879         return 0;
3880 }
3881
3882 int
3883 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3884                         struct e1000_2tuple_filter *filter)
3885 {
3886         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3887         struct e1000_filter_info *filter_info =
3888                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3889
3890         filter_info->twotuple_mask &= ~(1 << filter->index);
3891         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3892         rte_free(filter);
3893
3894         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3895         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3896         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3897         return 0;
3898 }
3899
3900 /*
3901  * igb_remove_2tuple_filter - remove a 2tuple filter
3902  *
3903  * @param
3904  * dev: Pointer to struct rte_eth_dev.
3905  * ntuple_filter: ponter to the filter that will be removed.
3906  *
3907  * @return
3908  *    - On success, zero.
3909  *    - On failure, a negative value.
3910  */
3911 static int
3912 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3913                         struct rte_eth_ntuple_filter *ntuple_filter)
3914 {
3915         struct e1000_filter_info *filter_info =
3916                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3917         struct e1000_2tuple_filter_info filter_2tuple;
3918         struct e1000_2tuple_filter *filter;
3919         int ret;
3920
3921         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3922         ret = ntuple_filter_to_2tuple(ntuple_filter,
3923                                       &filter_2tuple);
3924         if (ret < 0)
3925                 return ret;
3926
3927         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3928                                          &filter_2tuple);
3929         if (filter == NULL) {
3930                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3931                 return -ENOENT;
3932         }
3933
3934         igb_delete_2tuple_filter(dev, filter);
3935
3936         return 0;
3937 }
3938
3939 /* inject a igb flex filter to HW */
3940 static inline void
3941 igb_inject_flex_filter(struct rte_eth_dev *dev,
3942                            struct e1000_flex_filter *filter)
3943 {
3944         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3945         uint32_t wufc, queueing;
3946         uint32_t reg_off;
3947         uint8_t i, j = 0;
3948
3949         wufc = E1000_READ_REG(hw, E1000_WUFC);
3950         if (filter->index < E1000_MAX_FHFT)
3951                 reg_off = E1000_FHFT(filter->index);
3952         else
3953                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3954
3955         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3956                         (E1000_WUFC_FLX0 << filter->index));
3957         queueing = filter->filter_info.len |
3958                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3959                 (filter->filter_info.priority <<
3960                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3961         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3962                         queueing);
3963
3964         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3965                 E1000_WRITE_REG(hw, reg_off,
3966                                 filter->filter_info.dwords[j]);
3967                 reg_off += sizeof(uint32_t);
3968                 E1000_WRITE_REG(hw, reg_off,
3969                                 filter->filter_info.dwords[++j]);
3970                 reg_off += sizeof(uint32_t);
3971                 E1000_WRITE_REG(hw, reg_off,
3972                         (uint32_t)filter->filter_info.mask[i]);
3973                 reg_off += sizeof(uint32_t) * 2;
3974                 ++j;
3975         }
3976 }
3977
3978 static inline struct e1000_flex_filter *
3979 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3980                         struct e1000_flex_filter_info *key)
3981 {
3982         struct e1000_flex_filter *it;
3983
3984         TAILQ_FOREACH(it, filter_list, entries) {
3985                 if (memcmp(key, &it->filter_info,
3986                         sizeof(struct e1000_flex_filter_info)) == 0)
3987                         return it;
3988         }
3989
3990         return NULL;
3991 }
3992
3993 /* remove a flex byte filter
3994  * @param
3995  * dev: Pointer to struct rte_eth_dev.
3996  * filter: the pointer of the filter will be removed.
3997  */
3998 void
3999 igb_remove_flex_filter(struct rte_eth_dev *dev,
4000                         struct e1000_flex_filter *filter)
4001 {
4002         struct e1000_filter_info *filter_info =
4003                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4004         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4005         uint32_t wufc, i;
4006         uint32_t reg_off;
4007
4008         wufc = E1000_READ_REG(hw, E1000_WUFC);
4009         if (filter->index < E1000_MAX_FHFT)
4010                 reg_off = E1000_FHFT(filter->index);
4011         else
4012                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4013
4014         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4015                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4016
4017         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4018                 (~(E1000_WUFC_FLX0 << filter->index)));
4019
4020         filter_info->flex_mask &= ~(1 << filter->index);
4021         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4022         rte_free(filter);
4023 }
4024
4025 int
4026 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4027                         struct rte_eth_flex_filter *filter,
4028                         bool add)
4029 {
4030         struct e1000_filter_info *filter_info =
4031                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4032         struct e1000_flex_filter *flex_filter, *it;
4033         uint32_t mask;
4034         uint8_t shift, i;
4035
4036         flex_filter = rte_zmalloc("e1000_flex_filter",
4037                         sizeof(struct e1000_flex_filter), 0);
4038         if (flex_filter == NULL)
4039                 return -ENOMEM;
4040
4041         flex_filter->filter_info.len = filter->len;
4042         flex_filter->filter_info.priority = filter->priority;
4043         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4044         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4045                 mask = 0;
4046                 /* reverse bits in flex filter's mask*/
4047                 for (shift = 0; shift < CHAR_BIT; shift++) {
4048                         if (filter->mask[i] & (0x01 << shift))
4049                                 mask |= (0x80 >> shift);
4050                 }
4051                 flex_filter->filter_info.mask[i] = mask;
4052         }
4053
4054         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4055                                 &flex_filter->filter_info);
4056         if (it == NULL && !add) {
4057                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4058                 rte_free(flex_filter);
4059                 return -ENOENT;
4060         }
4061         if (it != NULL && add) {
4062                 PMD_DRV_LOG(ERR, "filter exists.");
4063                 rte_free(flex_filter);
4064                 return -EEXIST;
4065         }
4066
4067         if (add) {
4068                 flex_filter->queue = filter->queue;
4069                 /*
4070                  * look for an unused flex filter index
4071                  * and insert the filter into the list.
4072                  */
4073                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4074                         if (!(filter_info->flex_mask & (1 << i))) {
4075                                 filter_info->flex_mask |= 1 << i;
4076                                 flex_filter->index = i;
4077                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4078                                         flex_filter,
4079                                         entries);
4080                                 break;
4081                         }
4082                 }
4083                 if (i >= E1000_MAX_FLEX_FILTERS) {
4084                         PMD_DRV_LOG(ERR, "flex filters are full.");
4085                         rte_free(flex_filter);
4086                         return -ENOSYS;
4087                 }
4088
4089                 igb_inject_flex_filter(dev, flex_filter);
4090
4091         } else {
4092                 igb_remove_flex_filter(dev, it);
4093                 rte_free(flex_filter);
4094         }
4095
4096         return 0;
4097 }
4098
4099 static int
4100 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4101                         struct rte_eth_flex_filter *filter)
4102 {
4103         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4104         struct e1000_filter_info *filter_info =
4105                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4106         struct e1000_flex_filter flex_filter, *it;
4107         uint32_t wufc, queueing, wufc_en = 0;
4108
4109         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4110         flex_filter.filter_info.len = filter->len;
4111         flex_filter.filter_info.priority = filter->priority;
4112         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4113         memcpy(flex_filter.filter_info.mask, filter->mask,
4114                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4115
4116         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4117                                 &flex_filter.filter_info);
4118         if (it == NULL) {
4119                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4120                 return -ENOENT;
4121         }
4122
4123         wufc = E1000_READ_REG(hw, E1000_WUFC);
4124         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4125
4126         if ((wufc & wufc_en) == wufc_en) {
4127                 uint32_t reg_off = 0;
4128                 if (it->index < E1000_MAX_FHFT)
4129                         reg_off = E1000_FHFT(it->index);
4130                 else
4131                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4132
4133                 queueing = E1000_READ_REG(hw,
4134                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4135                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4136                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4137                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4138                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4139                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4140                 return 0;
4141         }
4142         return -ENOENT;
4143 }
4144
4145 static int
4146 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4147                         enum rte_filter_op filter_op,
4148                         void *arg)
4149 {
4150         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4151         struct rte_eth_flex_filter *filter;
4152         int ret = 0;
4153
4154         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4155
4156         if (filter_op == RTE_ETH_FILTER_NOP)
4157                 return ret;
4158
4159         if (arg == NULL) {
4160                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4161                             filter_op);
4162                 return -EINVAL;
4163         }
4164
4165         filter = (struct rte_eth_flex_filter *)arg;
4166         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4167             || filter->len % sizeof(uint64_t) != 0) {
4168                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4169                 return -EINVAL;
4170         }
4171         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4172                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4173                 return -EINVAL;
4174         }
4175
4176         switch (filter_op) {
4177         case RTE_ETH_FILTER_ADD:
4178                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4179                 break;
4180         case RTE_ETH_FILTER_DELETE:
4181                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4182                 break;
4183         case RTE_ETH_FILTER_GET:
4184                 ret = eth_igb_get_flex_filter(dev, filter);
4185                 break;
4186         default:
4187                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4188                 ret = -EINVAL;
4189                 break;
4190         }
4191
4192         return ret;
4193 }
4194
4195 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4196 static inline int
4197 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4198                         struct e1000_5tuple_filter_info *filter_info)
4199 {
4200         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4201                 return -EINVAL;
4202         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4203                 return -EINVAL;  /* filter index is out of range. */
4204         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4205                 return -EINVAL;  /* flags is invalid. */
4206
4207         switch (filter->dst_ip_mask) {
4208         case UINT32_MAX:
4209                 filter_info->dst_ip_mask = 0;
4210                 filter_info->dst_ip = filter->dst_ip;
4211                 break;
4212         case 0:
4213                 filter_info->dst_ip_mask = 1;
4214                 break;
4215         default:
4216                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4217                 return -EINVAL;
4218         }
4219
4220         switch (filter->src_ip_mask) {
4221         case UINT32_MAX:
4222                 filter_info->src_ip_mask = 0;
4223                 filter_info->src_ip = filter->src_ip;
4224                 break;
4225         case 0:
4226                 filter_info->src_ip_mask = 1;
4227                 break;
4228         default:
4229                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4230                 return -EINVAL;
4231         }
4232
4233         switch (filter->dst_port_mask) {
4234         case UINT16_MAX:
4235                 filter_info->dst_port_mask = 0;
4236                 filter_info->dst_port = filter->dst_port;
4237                 break;
4238         case 0:
4239                 filter_info->dst_port_mask = 1;
4240                 break;
4241         default:
4242                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4243                 return -EINVAL;
4244         }
4245
4246         switch (filter->src_port_mask) {
4247         case UINT16_MAX:
4248                 filter_info->src_port_mask = 0;
4249                 filter_info->src_port = filter->src_port;
4250                 break;
4251         case 0:
4252                 filter_info->src_port_mask = 1;
4253                 break;
4254         default:
4255                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4256                 return -EINVAL;
4257         }
4258
4259         switch (filter->proto_mask) {
4260         case UINT8_MAX:
4261                 filter_info->proto_mask = 0;
4262                 filter_info->proto = filter->proto;
4263                 break;
4264         case 0:
4265                 filter_info->proto_mask = 1;
4266                 break;
4267         default:
4268                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4269                 return -EINVAL;
4270         }
4271
4272         filter_info->priority = (uint8_t)filter->priority;
4273         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4274                 filter_info->tcp_flags = filter->tcp_flags;
4275         else
4276                 filter_info->tcp_flags = 0;
4277
4278         return 0;
4279 }
4280
4281 static inline struct e1000_5tuple_filter *
4282 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4283                         struct e1000_5tuple_filter_info *key)
4284 {
4285         struct e1000_5tuple_filter *it;
4286
4287         TAILQ_FOREACH(it, filter_list, entries) {
4288                 if (memcmp(key, &it->filter_info,
4289                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4290                         return it;
4291                 }
4292         }
4293         return NULL;
4294 }
4295
4296 /* inject a igb 5-tuple filter to HW */
4297 static inline void
4298 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4299                            struct e1000_5tuple_filter *filter)
4300 {
4301         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4302         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4303         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4304         uint8_t i;
4305
4306         i = filter->index;
4307         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4308         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4309                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4310         if (filter->filter_info.dst_ip_mask == 0)
4311                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4312         if (filter->filter_info.src_port_mask == 0)
4313                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4314         if (filter->filter_info.proto_mask == 0)
4315                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4316         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4317                 E1000_FTQF_QUEUE_MASK;
4318         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4319         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4320         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4321         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4322
4323         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4324         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4325
4326         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4327         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4328                 imir |= E1000_IMIR_PORT_BP;
4329         else
4330                 imir &= ~E1000_IMIR_PORT_BP;
4331         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4332
4333         /* tcp flags bits setting. */
4334         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4335                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4336                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4337                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4338                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4339                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4340                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4341                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4342                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4343                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4344                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4345                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4346                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4347         } else {
4348                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4349         }
4350         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4351         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4352 }
4353
4354 /*
4355  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4356  *
4357  * @param
4358  * dev: Pointer to struct rte_eth_dev.
4359  * ntuple_filter: ponter to the filter that will be added.
4360  *
4361  * @return
4362  *    - On success, zero.
4363  *    - On failure, a negative value.
4364  */
4365 static int
4366 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4367                         struct rte_eth_ntuple_filter *ntuple_filter)
4368 {
4369         struct e1000_filter_info *filter_info =
4370                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4371         struct e1000_5tuple_filter *filter;
4372         uint8_t i;
4373         int ret;
4374
4375         filter = rte_zmalloc("e1000_5tuple_filter",
4376                         sizeof(struct e1000_5tuple_filter), 0);
4377         if (filter == NULL)
4378                 return -ENOMEM;
4379
4380         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4381                                             &filter->filter_info);
4382         if (ret < 0) {
4383                 rte_free(filter);
4384                 return ret;
4385         }
4386
4387         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4388                                          &filter->filter_info) != NULL) {
4389                 PMD_DRV_LOG(ERR, "filter exists.");
4390                 rte_free(filter);
4391                 return -EEXIST;
4392         }
4393         filter->queue = ntuple_filter->queue;
4394
4395         /*
4396          * look for an unused 5tuple filter index,
4397          * and insert the filter to list.
4398          */
4399         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4400                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4401                         filter_info->fivetuple_mask |= 1 << i;
4402                         filter->index = i;
4403                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4404                                           filter,
4405                                           entries);
4406                         break;
4407                 }
4408         }
4409         if (i >= E1000_MAX_FTQF_FILTERS) {
4410                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4411                 rte_free(filter);
4412                 return -ENOSYS;
4413         }
4414
4415         igb_inject_5tuple_filter_82576(dev, filter);
4416         return 0;
4417 }
4418
4419 int
4420 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4421                                 struct e1000_5tuple_filter *filter)
4422 {
4423         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4424         struct e1000_filter_info *filter_info =
4425                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4426
4427         filter_info->fivetuple_mask &= ~(1 << filter->index);
4428         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4429         rte_free(filter);
4430
4431         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4432                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4433         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4434         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4435         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4436         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4437         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4438         return 0;
4439 }
4440
4441 /*
4442  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4443  *
4444  * @param
4445  * dev: Pointer to struct rte_eth_dev.
4446  * ntuple_filter: ponter to the filter that will be removed.
4447  *
4448  * @return
4449  *    - On success, zero.
4450  *    - On failure, a negative value.
4451  */
4452 static int
4453 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4454                                 struct rte_eth_ntuple_filter *ntuple_filter)
4455 {
4456         struct e1000_filter_info *filter_info =
4457                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4458         struct e1000_5tuple_filter_info filter_5tuple;
4459         struct e1000_5tuple_filter *filter;
4460         int ret;
4461
4462         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4463         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4464                                             &filter_5tuple);
4465         if (ret < 0)
4466                 return ret;
4467
4468         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4469                                          &filter_5tuple);
4470         if (filter == NULL) {
4471                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4472                 return -ENOENT;
4473         }
4474
4475         igb_delete_5tuple_filter_82576(dev, filter);
4476
4477         return 0;
4478 }
4479
4480 static int
4481 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4482 {
4483         uint32_t rctl;
4484         struct e1000_hw *hw;
4485         struct rte_eth_dev_info dev_info;
4486         uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4487         int ret;
4488
4489         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4490
4491 #ifdef RTE_LIBRTE_82571_SUPPORT
4492         /* XXX: not bigger than max_rx_pktlen */
4493         if (hw->mac.type == e1000_82571)
4494                 return -ENOTSUP;
4495 #endif
4496         ret = eth_igb_infos_get(dev, &dev_info);
4497         if (ret != 0)
4498                 return ret;
4499
4500         /* check that mtu is within the allowed range */
4501         if (mtu < RTE_ETHER_MIN_MTU ||
4502                         frame_size > dev_info.max_rx_pktlen)
4503                 return -EINVAL;
4504
4505         /* refuse mtu that requires the support of scattered packets when this
4506          * feature has not been enabled before. */
4507         if (!dev->data->scattered_rx &&
4508             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4509                 return -EINVAL;
4510
4511         rctl = E1000_READ_REG(hw, E1000_RCTL);
4512
4513         /* switch to jumbo mode if needed */
4514         if (frame_size > RTE_ETHER_MAX_LEN) {
4515                 dev->data->dev_conf.rxmode.offloads |=
4516                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4517                 rctl |= E1000_RCTL_LPE;
4518         } else {
4519                 dev->data->dev_conf.rxmode.offloads &=
4520                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4521                 rctl &= ~E1000_RCTL_LPE;
4522         }
4523         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4524
4525         /* update max frame size */
4526         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4527
4528         E1000_WRITE_REG(hw, E1000_RLPML,
4529                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4530
4531         return 0;
4532 }
4533
4534 /*
4535  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4536  *
4537  * @param
4538  * dev: Pointer to struct rte_eth_dev.
4539  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4540  * add: if true, add filter, if false, remove filter
4541  *
4542  * @return
4543  *    - On success, zero.
4544  *    - On failure, a negative value.
4545  */
4546 int
4547 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4548                         struct rte_eth_ntuple_filter *ntuple_filter,
4549                         bool add)
4550 {
4551         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4552         int ret;
4553
4554         switch (ntuple_filter->flags) {
4555         case RTE_5TUPLE_FLAGS:
4556         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4557                 if (hw->mac.type != e1000_82576)
4558                         return -ENOTSUP;
4559                 if (add)
4560                         ret = igb_add_5tuple_filter_82576(dev,
4561                                                           ntuple_filter);
4562                 else
4563                         ret = igb_remove_5tuple_filter_82576(dev,
4564                                                              ntuple_filter);
4565                 break;
4566         case RTE_2TUPLE_FLAGS:
4567         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4568                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4569                         hw->mac.type != e1000_i210 &&
4570                         hw->mac.type != e1000_i211)
4571                         return -ENOTSUP;
4572                 if (add)
4573                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4574                 else
4575                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4576                 break;
4577         default:
4578                 ret = -EINVAL;
4579                 break;
4580         }
4581
4582         return ret;
4583 }
4584
4585 /*
4586  * igb_get_ntuple_filter - get a ntuple filter
4587  *
4588  * @param
4589  * dev: Pointer to struct rte_eth_dev.
4590  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4591  *
4592  * @return
4593  *    - On success, zero.
4594  *    - On failure, a negative value.
4595  */
4596 static int
4597 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4598                         struct rte_eth_ntuple_filter *ntuple_filter)
4599 {
4600         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4601         struct e1000_filter_info *filter_info =
4602                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4603         struct e1000_5tuple_filter_info filter_5tuple;
4604         struct e1000_2tuple_filter_info filter_2tuple;
4605         struct e1000_5tuple_filter *p_5tuple_filter;
4606         struct e1000_2tuple_filter *p_2tuple_filter;
4607         int ret;
4608
4609         switch (ntuple_filter->flags) {
4610         case RTE_5TUPLE_FLAGS:
4611         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4612                 if (hw->mac.type != e1000_82576)
4613                         return -ENOTSUP;
4614                 memset(&filter_5tuple,
4615                         0,
4616                         sizeof(struct e1000_5tuple_filter_info));
4617                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4618                                                     &filter_5tuple);
4619                 if (ret < 0)
4620                         return ret;
4621                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4622                                         &filter_info->fivetuple_list,
4623                                         &filter_5tuple);
4624                 if (p_5tuple_filter == NULL) {
4625                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4626                         return -ENOENT;
4627                 }
4628                 ntuple_filter->queue = p_5tuple_filter->queue;
4629                 break;
4630         case RTE_2TUPLE_FLAGS:
4631         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4632                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4633                         return -ENOTSUP;
4634                 memset(&filter_2tuple,
4635                         0,
4636                         sizeof(struct e1000_2tuple_filter_info));
4637                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4638                 if (ret < 0)
4639                         return ret;
4640                 p_2tuple_filter = igb_2tuple_filter_lookup(
4641                                         &filter_info->twotuple_list,
4642                                         &filter_2tuple);
4643                 if (p_2tuple_filter == NULL) {
4644                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4645                         return -ENOENT;
4646                 }
4647                 ntuple_filter->queue = p_2tuple_filter->queue;
4648                 break;
4649         default:
4650                 ret = -EINVAL;
4651                 break;
4652         }
4653
4654         return 0;
4655 }
4656
4657 /*
4658  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4659  * @dev: pointer to rte_eth_dev structure
4660  * @filter_op:operation will be taken.
4661  * @arg: a pointer to specific structure corresponding to the filter_op
4662  */
4663 static int
4664 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4665                                 enum rte_filter_op filter_op,
4666                                 void *arg)
4667 {
4668         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4669         int ret;
4670
4671         MAC_TYPE_FILTER_SUP(hw->mac.type);
4672
4673         if (filter_op == RTE_ETH_FILTER_NOP)
4674                 return 0;
4675
4676         if (arg == NULL) {
4677                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4678                             filter_op);
4679                 return -EINVAL;
4680         }
4681
4682         switch (filter_op) {
4683         case RTE_ETH_FILTER_ADD:
4684                 ret = igb_add_del_ntuple_filter(dev,
4685                         (struct rte_eth_ntuple_filter *)arg,
4686                         TRUE);
4687                 break;
4688         case RTE_ETH_FILTER_DELETE:
4689                 ret = igb_add_del_ntuple_filter(dev,
4690                         (struct rte_eth_ntuple_filter *)arg,
4691                         FALSE);
4692                 break;
4693         case RTE_ETH_FILTER_GET:
4694                 ret = igb_get_ntuple_filter(dev,
4695                         (struct rte_eth_ntuple_filter *)arg);
4696                 break;
4697         default:
4698                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4699                 ret = -EINVAL;
4700                 break;
4701         }
4702         return ret;
4703 }
4704
4705 static inline int
4706 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4707                         uint16_t ethertype)
4708 {
4709         int i;
4710
4711         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4712                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4713                     (filter_info->ethertype_mask & (1 << i)))
4714                         return i;
4715         }
4716         return -1;
4717 }
4718
4719 static inline int
4720 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4721                         uint16_t ethertype, uint32_t etqf)
4722 {
4723         int i;
4724
4725         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4726                 if (!(filter_info->ethertype_mask & (1 << i))) {
4727                         filter_info->ethertype_mask |= 1 << i;
4728                         filter_info->ethertype_filters[i].ethertype = ethertype;
4729                         filter_info->ethertype_filters[i].etqf = etqf;
4730                         return i;
4731                 }
4732         }
4733         return -1;
4734 }
4735
4736 int
4737 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4738                         uint8_t idx)
4739 {
4740         if (idx >= E1000_MAX_ETQF_FILTERS)
4741                 return -1;
4742         filter_info->ethertype_mask &= ~(1 << idx);
4743         filter_info->ethertype_filters[idx].ethertype = 0;
4744         filter_info->ethertype_filters[idx].etqf = 0;
4745         return idx;
4746 }
4747
4748
4749 int
4750 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4751                         struct rte_eth_ethertype_filter *filter,
4752                         bool add)
4753 {
4754         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4755         struct e1000_filter_info *filter_info =
4756                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4757         uint32_t etqf = 0;
4758         int ret;
4759
4760         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4761                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4762                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4763                         " ethertype filter.", filter->ether_type);
4764                 return -EINVAL;
4765         }
4766
4767         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4768                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4769                 return -EINVAL;
4770         }
4771         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4772                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4773                 return -EINVAL;
4774         }
4775
4776         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4777         if (ret >= 0 && add) {
4778                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4779                             filter->ether_type);
4780                 return -EEXIST;
4781         }
4782         if (ret < 0 && !add) {
4783                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4784                             filter->ether_type);
4785                 return -ENOENT;
4786         }
4787
4788         if (add) {
4789                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4790                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4791                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4792                 ret = igb_ethertype_filter_insert(filter_info,
4793                                 filter->ether_type, etqf);
4794                 if (ret < 0) {
4795                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4796                         return -ENOSYS;
4797                 }
4798         } else {
4799                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4800                 if (ret < 0)
4801                         return -ENOSYS;
4802         }
4803         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4804         E1000_WRITE_FLUSH(hw);
4805
4806         return 0;
4807 }
4808
4809 static int
4810 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4811                         struct rte_eth_ethertype_filter *filter)
4812 {
4813         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4814         struct e1000_filter_info *filter_info =
4815                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4816         uint32_t etqf;
4817         int ret;
4818
4819         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4820         if (ret < 0) {
4821                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4822                             filter->ether_type);
4823                 return -ENOENT;
4824         }
4825
4826         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4827         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4828                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4829                 filter->flags = 0;
4830                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4831                                 E1000_ETQF_QUEUE_SHIFT;
4832                 return 0;
4833         }
4834
4835         return -ENOENT;
4836 }
4837
4838 /*
4839  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4840  * @dev: pointer to rte_eth_dev structure
4841  * @filter_op:operation will be taken.
4842  * @arg: a pointer to specific structure corresponding to the filter_op
4843  */
4844 static int
4845 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4846                                 enum rte_filter_op filter_op,
4847                                 void *arg)
4848 {
4849         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4850         int ret;
4851
4852         MAC_TYPE_FILTER_SUP(hw->mac.type);
4853
4854         if (filter_op == RTE_ETH_FILTER_NOP)
4855                 return 0;
4856
4857         if (arg == NULL) {
4858                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4859                             filter_op);
4860                 return -EINVAL;
4861         }
4862
4863         switch (filter_op) {
4864         case RTE_ETH_FILTER_ADD:
4865                 ret = igb_add_del_ethertype_filter(dev,
4866                         (struct rte_eth_ethertype_filter *)arg,
4867                         TRUE);
4868                 break;
4869         case RTE_ETH_FILTER_DELETE:
4870                 ret = igb_add_del_ethertype_filter(dev,
4871                         (struct rte_eth_ethertype_filter *)arg,
4872                         FALSE);
4873                 break;
4874         case RTE_ETH_FILTER_GET:
4875                 ret = igb_get_ethertype_filter(dev,
4876                         (struct rte_eth_ethertype_filter *)arg);
4877                 break;
4878         default:
4879                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4880                 ret = -EINVAL;
4881                 break;
4882         }
4883         return ret;
4884 }
4885
4886 static int
4887 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4888                      enum rte_filter_type filter_type,
4889                      enum rte_filter_op filter_op,
4890                      void *arg)
4891 {
4892         int ret = 0;
4893
4894         switch (filter_type) {
4895         case RTE_ETH_FILTER_NTUPLE:
4896                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4897                 break;
4898         case RTE_ETH_FILTER_ETHERTYPE:
4899                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4900                 break;
4901         case RTE_ETH_FILTER_SYN:
4902                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4903                 break;
4904         case RTE_ETH_FILTER_FLEXIBLE:
4905                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4906                 break;
4907         case RTE_ETH_FILTER_GENERIC:
4908                 if (filter_op != RTE_ETH_FILTER_GET)
4909                         return -EINVAL;
4910                 *(const void **)arg = &igb_flow_ops;
4911                 break;
4912         default:
4913                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4914                                                         filter_type);
4915                 break;
4916         }
4917
4918         return ret;
4919 }
4920
4921 static int
4922 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4923                          struct rte_ether_addr *mc_addr_set,
4924                          uint32_t nb_mc_addr)
4925 {
4926         struct e1000_hw *hw;
4927
4928         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4929         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4930         return 0;
4931 }
4932
4933 static uint64_t
4934 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4935 {
4936         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4937         uint64_t systime_cycles;
4938
4939         switch (hw->mac.type) {
4940         case e1000_i210:
4941         case e1000_i211:
4942                 /*
4943                  * Need to read System Time Residue Register to be able
4944                  * to read the other two registers.
4945                  */
4946                 E1000_READ_REG(hw, E1000_SYSTIMR);
4947                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4948                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4949                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4950                                 * NSEC_PER_SEC;
4951                 break;
4952         case e1000_82580:
4953         case e1000_i350:
4954         case e1000_i354:
4955                 /*
4956                  * Need to read System Time Residue Register to be able
4957                  * to read the other two registers.
4958                  */
4959                 E1000_READ_REG(hw, E1000_SYSTIMR);
4960                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4961                 /* Only the 8 LSB are valid. */
4962                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4963                                 & 0xff) << 32;
4964                 break;
4965         default:
4966                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4967                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4968                                 << 32;
4969                 break;
4970         }
4971
4972         return systime_cycles;
4973 }
4974
4975 static uint64_t
4976 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4977 {
4978         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4979         uint64_t rx_tstamp_cycles;
4980
4981         switch (hw->mac.type) {
4982         case e1000_i210:
4983         case e1000_i211:
4984                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4985                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4986                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4987                                 * NSEC_PER_SEC;
4988                 break;
4989         case e1000_82580:
4990         case e1000_i350:
4991         case e1000_i354:
4992                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4993                 /* Only the 8 LSB are valid. */
4994                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4995                                 & 0xff) << 32;
4996                 break;
4997         default:
4998                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4999                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5000                                 << 32;
5001                 break;
5002         }
5003
5004         return rx_tstamp_cycles;
5005 }
5006
5007 static uint64_t
5008 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5009 {
5010         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5011         uint64_t tx_tstamp_cycles;
5012
5013         switch (hw->mac.type) {
5014         case e1000_i210:
5015         case e1000_i211:
5016                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5017                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5018                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5019                                 * NSEC_PER_SEC;
5020                 break;
5021         case e1000_82580:
5022         case e1000_i350:
5023         case e1000_i354:
5024                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5025                 /* Only the 8 LSB are valid. */
5026                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5027                                 & 0xff) << 32;
5028                 break;
5029         default:
5030                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5031                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5032                                 << 32;
5033                 break;
5034         }
5035
5036         return tx_tstamp_cycles;
5037 }
5038
5039 static void
5040 igb_start_timecounters(struct rte_eth_dev *dev)
5041 {
5042         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5043         struct e1000_adapter *adapter = dev->data->dev_private;
5044         uint32_t incval = 1;
5045         uint32_t shift = 0;
5046         uint64_t mask = E1000_CYCLECOUNTER_MASK;
5047
5048         switch (hw->mac.type) {
5049         case e1000_82580:
5050         case e1000_i350:
5051         case e1000_i354:
5052                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5053                 mask = (1ULL << 40) - 1;
5054                 /* fall-through */
5055         case e1000_i210:
5056         case e1000_i211:
5057                 /*
5058                  * Start incrementing the register
5059                  * used to timestamp PTP packets.
5060                  */
5061                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5062                 break;
5063         case e1000_82576:
5064                 incval = E1000_INCVALUE_82576;
5065                 shift = IGB_82576_TSYNC_SHIFT;
5066                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5067                                 E1000_INCPERIOD_82576 | incval);
5068                 break;
5069         default:
5070                 /* Not supported */
5071                 return;
5072         }
5073
5074         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5075         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5076         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5077
5078         adapter->systime_tc.cc_mask = mask;
5079         adapter->systime_tc.cc_shift = shift;
5080         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5081
5082         adapter->rx_tstamp_tc.cc_mask = mask;
5083         adapter->rx_tstamp_tc.cc_shift = shift;
5084         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5085
5086         adapter->tx_tstamp_tc.cc_mask = mask;
5087         adapter->tx_tstamp_tc.cc_shift = shift;
5088         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5089 }
5090
5091 static int
5092 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5093 {
5094         struct e1000_adapter *adapter = dev->data->dev_private;
5095
5096         adapter->systime_tc.nsec += delta;
5097         adapter->rx_tstamp_tc.nsec += delta;
5098         adapter->tx_tstamp_tc.nsec += delta;
5099
5100         return 0;
5101 }
5102
5103 static int
5104 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5105 {
5106         uint64_t ns;
5107         struct e1000_adapter *adapter = dev->data->dev_private;
5108
5109         ns = rte_timespec_to_ns(ts);
5110
5111         /* Set the timecounters to a new value. */
5112         adapter->systime_tc.nsec = ns;
5113         adapter->rx_tstamp_tc.nsec = ns;
5114         adapter->tx_tstamp_tc.nsec = ns;
5115
5116         return 0;
5117 }
5118
5119 static int
5120 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5121 {
5122         uint64_t ns, systime_cycles;
5123         struct e1000_adapter *adapter = dev->data->dev_private;
5124
5125         systime_cycles = igb_read_systime_cyclecounter(dev);
5126         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5127         *ts = rte_ns_to_timespec(ns);
5128
5129         return 0;
5130 }
5131
5132 static int
5133 igb_timesync_enable(struct rte_eth_dev *dev)
5134 {
5135         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5136         uint32_t tsync_ctl;
5137         uint32_t tsauxc;
5138
5139         /* Stop the timesync system time. */
5140         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5141         /* Reset the timesync system time value. */
5142         switch (hw->mac.type) {
5143         case e1000_82580:
5144         case e1000_i350:
5145         case e1000_i354:
5146         case e1000_i210:
5147         case e1000_i211:
5148                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5149                 /* fall-through */
5150         case e1000_82576:
5151                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5152                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5153                 break;
5154         default:
5155                 /* Not supported. */
5156                 return -ENOTSUP;
5157         }
5158
5159         /* Enable system time for it isn't on by default. */
5160         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5161         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5162         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5163
5164         igb_start_timecounters(dev);
5165
5166         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5167         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5168                         (RTE_ETHER_TYPE_1588 |
5169                          E1000_ETQF_FILTER_ENABLE |
5170                          E1000_ETQF_1588));
5171
5172         /* Enable timestamping of received PTP packets. */
5173         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5174         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5175         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5176
5177         /* Enable Timestamping of transmitted PTP packets. */
5178         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5179         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5180         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5181
5182         return 0;
5183 }
5184
5185 static int
5186 igb_timesync_disable(struct rte_eth_dev *dev)
5187 {
5188         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5189         uint32_t tsync_ctl;
5190
5191         /* Disable timestamping of transmitted PTP packets. */
5192         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5193         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5194         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5195
5196         /* Disable timestamping of received PTP packets. */
5197         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5198         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5199         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5200
5201         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5202         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5203
5204         /* Stop incrementating the System Time registers. */
5205         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5206
5207         return 0;
5208 }
5209
5210 static int
5211 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5212                                struct timespec *timestamp,
5213                                uint32_t flags __rte_unused)
5214 {
5215         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5216         struct e1000_adapter *adapter = dev->data->dev_private;
5217         uint32_t tsync_rxctl;
5218         uint64_t rx_tstamp_cycles;
5219         uint64_t ns;
5220
5221         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5222         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5223                 return -EINVAL;
5224
5225         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5226         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5227         *timestamp = rte_ns_to_timespec(ns);
5228
5229         return  0;
5230 }
5231
5232 static int
5233 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5234                                struct timespec *timestamp)
5235 {
5236         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5237         struct e1000_adapter *adapter = dev->data->dev_private;
5238         uint32_t tsync_txctl;
5239         uint64_t tx_tstamp_cycles;
5240         uint64_t ns;
5241
5242         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5243         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5244                 return -EINVAL;
5245
5246         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5247         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5248         *timestamp = rte_ns_to_timespec(ns);
5249
5250         return  0;
5251 }
5252
5253 static int
5254 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5255 {
5256         int count = 0;
5257         int g_ind = 0;
5258         const struct reg_info *reg_group;
5259
5260         while ((reg_group = igb_regs[g_ind++]))
5261                 count += igb_reg_group_count(reg_group);
5262
5263         return count;
5264 }
5265
5266 static int
5267 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5268 {
5269         int count = 0;
5270         int g_ind = 0;
5271         const struct reg_info *reg_group;
5272
5273         while ((reg_group = igbvf_regs[g_ind++]))
5274                 count += igb_reg_group_count(reg_group);
5275
5276         return count;
5277 }
5278
5279 static int
5280 eth_igb_get_regs(struct rte_eth_dev *dev,
5281         struct rte_dev_reg_info *regs)
5282 {
5283         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5284         uint32_t *data = regs->data;
5285         int g_ind = 0;
5286         int count = 0;
5287         const struct reg_info *reg_group;
5288
5289         if (data == NULL) {
5290                 regs->length = eth_igb_get_reg_length(dev);
5291                 regs->width = sizeof(uint32_t);
5292                 return 0;
5293         }
5294
5295         /* Support only full register dump */
5296         if ((regs->length == 0) ||
5297             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5298                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5299                         hw->device_id;
5300                 while ((reg_group = igb_regs[g_ind++]))
5301                         count += igb_read_regs_group(dev, &data[count],
5302                                                         reg_group);
5303                 return 0;
5304         }
5305
5306         return -ENOTSUP;
5307 }
5308
5309 static int
5310 igbvf_get_regs(struct rte_eth_dev *dev,
5311         struct rte_dev_reg_info *regs)
5312 {
5313         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5314         uint32_t *data = regs->data;
5315         int g_ind = 0;
5316         int count = 0;
5317         const struct reg_info *reg_group;
5318
5319         if (data == NULL) {
5320                 regs->length = igbvf_get_reg_length(dev);
5321                 regs->width = sizeof(uint32_t);
5322                 return 0;
5323         }
5324
5325         /* Support only full register dump */
5326         if ((regs->length == 0) ||
5327             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5328                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5329                         hw->device_id;
5330                 while ((reg_group = igbvf_regs[g_ind++]))
5331                         count += igb_read_regs_group(dev, &data[count],
5332                                                         reg_group);
5333                 return 0;
5334         }
5335
5336         return -ENOTSUP;
5337 }
5338
5339 static int
5340 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5341 {
5342         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5343
5344         /* Return unit is byte count */
5345         return hw->nvm.word_size * 2;
5346 }
5347
5348 static int
5349 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5350         struct rte_dev_eeprom_info *in_eeprom)
5351 {
5352         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5353         struct e1000_nvm_info *nvm = &hw->nvm;
5354         uint16_t *data = in_eeprom->data;
5355         int first, length;
5356
5357         first = in_eeprom->offset >> 1;
5358         length = in_eeprom->length >> 1;
5359         if ((first >= hw->nvm.word_size) ||
5360             ((first + length) >= hw->nvm.word_size))
5361                 return -EINVAL;
5362
5363         in_eeprom->magic = hw->vendor_id |
5364                 ((uint32_t)hw->device_id << 16);
5365
5366         if ((nvm->ops.read) == NULL)
5367                 return -ENOTSUP;
5368
5369         return nvm->ops.read(hw, first, length, data);
5370 }
5371
5372 static int
5373 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5374         struct rte_dev_eeprom_info *in_eeprom)
5375 {
5376         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5377         struct e1000_nvm_info *nvm = &hw->nvm;
5378         uint16_t *data = in_eeprom->data;
5379         int first, length;
5380
5381         first = in_eeprom->offset >> 1;
5382         length = in_eeprom->length >> 1;
5383         if ((first >= hw->nvm.word_size) ||
5384             ((first + length) >= hw->nvm.word_size))
5385                 return -EINVAL;
5386
5387         in_eeprom->magic = (uint32_t)hw->vendor_id |
5388                 ((uint32_t)hw->device_id << 16);
5389
5390         if ((nvm->ops.write) == NULL)
5391                 return -ENOTSUP;
5392         return nvm->ops.write(hw,  first, length, data);
5393 }
5394
5395 static int
5396 eth_igb_get_module_info(struct rte_eth_dev *dev,
5397                         struct rte_eth_dev_module_info *modinfo)
5398 {
5399         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5400
5401         uint32_t status = 0;
5402         uint16_t sff8472_rev, addr_mode;
5403         bool page_swap = false;
5404
5405         if (hw->phy.media_type == e1000_media_type_copper ||
5406             hw->phy.media_type == e1000_media_type_unknown)
5407                 return -EOPNOTSUPP;
5408
5409         /* Check whether we support SFF-8472 or not */
5410         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5411         if (status)
5412                 return -EIO;
5413
5414         /* addressing mode is not supported */
5415         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5416         if (status)
5417                 return -EIO;
5418
5419         /* addressing mode is not supported */
5420         if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5421                 PMD_DRV_LOG(ERR,
5422                             "Address change required to access page 0xA2, "
5423                             "but not supported. Please report the module "
5424                             "type to the driver maintainers.\n");
5425                 page_swap = true;
5426         }
5427
5428         if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5429                 /* We have an SFP, but it does not support SFF-8472 */
5430                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5431                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5432         } else {
5433                 /* We have an SFP which supports a revision of SFF-8472 */
5434                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5435                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5436         }
5437
5438         return 0;
5439 }
5440
5441 static int
5442 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5443                           struct rte_dev_eeprom_info *info)
5444 {
5445         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5446
5447         uint32_t status = 0;
5448         uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5449         u16 first_word, last_word;
5450         int i = 0;
5451
5452         if (info->length == 0)
5453                 return -EINVAL;
5454
5455         first_word = info->offset >> 1;
5456         last_word = (info->offset + info->length - 1) >> 1;
5457
5458         /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5459         for (i = 0; i < last_word - first_word + 1; i++) {
5460                 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5461                                                 &dataword[i]);
5462                 if (status) {
5463                         /* Error occurred while reading module */
5464                         return -EIO;
5465                 }
5466
5467                 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5468         }
5469
5470         memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5471
5472         return 0;
5473 }
5474
5475 static int
5476 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5477 {
5478         struct e1000_hw *hw =
5479                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5480         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5481         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5482         uint32_t vec = E1000_MISC_VEC_ID;
5483
5484         if (rte_intr_allow_others(intr_handle))
5485                 vec = E1000_RX_VEC_START;
5486
5487         uint32_t mask = 1 << (queue_id + vec);
5488
5489         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5490         E1000_WRITE_FLUSH(hw);
5491
5492         return 0;
5493 }
5494
5495 static int
5496 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5497 {
5498         struct e1000_hw *hw =
5499                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5500         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5501         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5502         uint32_t vec = E1000_MISC_VEC_ID;
5503
5504         if (rte_intr_allow_others(intr_handle))
5505                 vec = E1000_RX_VEC_START;
5506
5507         uint32_t mask = 1 << (queue_id + vec);
5508         uint32_t regval;
5509
5510         regval = E1000_READ_REG(hw, E1000_EIMS);
5511         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5512         E1000_WRITE_FLUSH(hw);
5513
5514         rte_intr_ack(intr_handle);
5515
5516         return 0;
5517 }
5518
5519 static void
5520 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5521                    uint8_t index, uint8_t offset)
5522 {
5523         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5524
5525         /* clear bits */
5526         val &= ~((uint32_t)0xFF << offset);
5527
5528         /* write vector and valid bit */
5529         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5530
5531         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5532 }
5533
5534 static void
5535 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5536                            uint8_t queue, uint8_t msix_vector)
5537 {
5538         uint32_t tmp = 0;
5539
5540         if (hw->mac.type == e1000_82575) {
5541                 if (direction == 0)
5542                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5543                 else if (direction == 1)
5544                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5545                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5546         } else if (hw->mac.type == e1000_82576) {
5547                 if ((direction == 0) || (direction == 1))
5548                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5549                                            ((queue & 0x8) << 1) +
5550                                            8 * direction);
5551         } else if ((hw->mac.type == e1000_82580) ||
5552                         (hw->mac.type == e1000_i350) ||
5553                         (hw->mac.type == e1000_i354) ||
5554                         (hw->mac.type == e1000_i210) ||
5555                         (hw->mac.type == e1000_i211)) {
5556                 if ((direction == 0) || (direction == 1))
5557                         eth_igb_write_ivar(hw, msix_vector,
5558                                            queue >> 1,
5559                                            ((queue & 0x1) << 4) +
5560                                            8 * direction);
5561         }
5562 }
5563
5564 /* Sets up the hardware to generate MSI-X interrupts properly
5565  * @hw
5566  *  board private structure
5567  */
5568 static void
5569 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5570 {
5571         int queue_id;
5572         uint32_t tmpval, regval, intr_mask;
5573         struct e1000_hw *hw =
5574                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5575         uint32_t vec = E1000_MISC_VEC_ID;
5576         uint32_t base = E1000_MISC_VEC_ID;
5577         uint32_t misc_shift = 0;
5578         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5579         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5580
5581         /* won't configure msix register if no mapping is done
5582          * between intr vector and event fd
5583          */
5584         if (!rte_intr_dp_is_en(intr_handle))
5585                 return;
5586
5587         if (rte_intr_allow_others(intr_handle)) {
5588                 vec = base = E1000_RX_VEC_START;
5589                 misc_shift = 1;
5590         }
5591
5592         /* set interrupt vector for other causes */
5593         if (hw->mac.type == e1000_82575) {
5594                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5595                 /* enable MSI-X PBA support */
5596                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5597
5598                 /* Auto-Mask interrupts upon ICR read */
5599                 tmpval |= E1000_CTRL_EXT_EIAME;
5600                 tmpval |= E1000_CTRL_EXT_IRCA;
5601
5602                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5603
5604                 /* enable msix_other interrupt */
5605                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5606                 regval = E1000_READ_REG(hw, E1000_EIAC);
5607                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5608                 regval = E1000_READ_REG(hw, E1000_EIAM);
5609                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5610         } else if ((hw->mac.type == e1000_82576) ||
5611                         (hw->mac.type == e1000_82580) ||
5612                         (hw->mac.type == e1000_i350) ||
5613                         (hw->mac.type == e1000_i354) ||
5614                         (hw->mac.type == e1000_i210) ||
5615                         (hw->mac.type == e1000_i211)) {
5616                 /* turn on MSI-X capability first */
5617                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5618                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5619                                         E1000_GPIE_NSICR);
5620                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5621                         misc_shift;
5622
5623                 if (dev->data->dev_conf.intr_conf.lsc != 0)
5624                         intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5625
5626                 regval = E1000_READ_REG(hw, E1000_EIAC);
5627                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5628
5629                 /* enable msix_other interrupt */
5630                 regval = E1000_READ_REG(hw, E1000_EIMS);
5631                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5632                 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5633                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5634         }
5635
5636         /* use EIAM to auto-mask when MSI-X interrupt
5637          * is asserted, this saves a register write for every interrupt
5638          */
5639         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5640                 misc_shift;
5641
5642         if (dev->data->dev_conf.intr_conf.lsc != 0)
5643                 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5644
5645         regval = E1000_READ_REG(hw, E1000_EIAM);
5646         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5647
5648         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5649                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5650                 intr_handle->intr_vec[queue_id] = vec;
5651                 if (vec < base + intr_handle->nb_efd - 1)
5652                         vec++;
5653         }
5654
5655         E1000_WRITE_FLUSH(hw);
5656 }
5657
5658 /* restore n-tuple filter */
5659 static inline void
5660 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5661 {
5662         struct e1000_filter_info *filter_info =
5663                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5664         struct e1000_5tuple_filter *p_5tuple;
5665         struct e1000_2tuple_filter *p_2tuple;
5666
5667         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5668                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5669         }
5670
5671         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5672                 igb_inject_2uple_filter(dev, p_2tuple);
5673         }
5674 }
5675
5676 /* restore SYN filter */
5677 static inline void
5678 igb_syn_filter_restore(struct rte_eth_dev *dev)
5679 {
5680         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5681         struct e1000_filter_info *filter_info =
5682                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5683         uint32_t synqf;
5684
5685         synqf = filter_info->syn_info;
5686
5687         if (synqf & E1000_SYN_FILTER_ENABLE) {
5688                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5689                 E1000_WRITE_FLUSH(hw);
5690         }
5691 }
5692
5693 /* restore ethernet type filter */
5694 static inline void
5695 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5696 {
5697         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5698         struct e1000_filter_info *filter_info =
5699                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5700         int i;
5701
5702         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5703                 if (filter_info->ethertype_mask & (1 << i)) {
5704                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5705                                 filter_info->ethertype_filters[i].etqf);
5706                         E1000_WRITE_FLUSH(hw);
5707                 }
5708         }
5709 }
5710
5711 /* restore flex byte filter */
5712 static inline void
5713 igb_flex_filter_restore(struct rte_eth_dev *dev)
5714 {
5715         struct e1000_filter_info *filter_info =
5716                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5717         struct e1000_flex_filter *flex_filter;
5718
5719         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5720                 igb_inject_flex_filter(dev, flex_filter);
5721         }
5722 }
5723
5724 /* restore rss filter */
5725 static inline void
5726 igb_rss_filter_restore(struct rte_eth_dev *dev)
5727 {
5728         struct e1000_filter_info *filter_info =
5729                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5730
5731         if (filter_info->rss_info.conf.queue_num)
5732                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5733 }
5734
5735 /* restore all types filter */
5736 static int
5737 igb_filter_restore(struct rte_eth_dev *dev)
5738 {
5739         igb_ntuple_filter_restore(dev);
5740         igb_ethertype_filter_restore(dev);
5741         igb_syn_filter_restore(dev);
5742         igb_flex_filter_restore(dev);
5743         igb_rss_filter_restore(dev);
5744
5745         return 0;
5746 }
5747
5748 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5749 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5750 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5751 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5752 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5753 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5754
5755 /* see e1000_logs.c */
5756 RTE_INIT(e1000_init_log)
5757 {
5758         e1000_igb_init_log();
5759 }