drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_string_fns.h>
  12 #include <rte_common.h>
  13 #include <rte_interrupts.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_log.h>
  16 #include <rte_debug.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <ethdev_pci.h>
  22 #include <rte_memory.h>
  23 #include <rte_eal.h>
  24 #include <rte_malloc.h>
  25 #include <rte_dev.h>
  26
  27 #include "e1000_logs.h"
  28 #include "base/e1000_api.h"
  29 #include "e1000_ethdev.h"
  30 #include "igb_regs.h"
  31
  32 /*
  33  * Default values for port configuration
  34  */
  35 #define IGB_DEFAULT_RX_FREE_THRESH  32
  36
  37 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  38 #define IGB_DEFAULT_RX_HTHRESH      8
  39 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  40
  41 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  42 #define IGB_DEFAULT_TX_HTHRESH      1
  43 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  44
  45 /* Bit shift and mask */
  46 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  47 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  48 #define IGB_8_BIT_WIDTH  CHAR_BIT
  49 #define IGB_8_BIT_MASK   UINT8_MAX
  50
  51 /* Additional timesync values. */
  52 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  53 #define E1000_ETQF_FILTER_1588       3
  54 #define IGB_82576_TSYNC_SHIFT        16
  55 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  56 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  58
  59 #define E1000_VTIVAR_MISC                0x01740
  60 #define E1000_VTIVAR_MISC_MASK           0xFF
  61 #define E1000_VTIVAR_VALID               0x80
  62 #define E1000_VTIVAR_MISC_MAILBOX        0
  63 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  64
  65 /* External VLAN Enable bit mask */
  66 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  67
  68 /* External VLAN Ether Type bit mask and shift */
  69 #define E1000_VET_VET_EXT            0xFFFF0000
  70 #define E1000_VET_VET_EXT_SHIFT      16
  71
  72 /* MSI-X other interrupt vector */
  73 #define IGB_MSIX_OTHER_INTR_VEC      0
  74
  75 static int  eth_igb_configure(struct rte_eth_dev *dev);
  76 static int  eth_igb_start(struct rte_eth_dev *dev);
  77 static int  eth_igb_stop(struct rte_eth_dev *dev);
  78 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  79 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  80 static int eth_igb_close(struct rte_eth_dev *dev);
  81 static int eth_igb_reset(struct rte_eth_dev *dev);
  82 static int  eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  83 static int  eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  84 static int  eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  85 static int  eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  87                                 int wait_to_complete);
  88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  89                                 struct rte_eth_stats *rte_stats);
  90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  91                               struct rte_eth_xstat *xstats, unsigned n);
  92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  93                 const uint64_t *ids,
  94                 uint64_t *values, unsigned int n);
  95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  96                                     struct rte_eth_xstat_name *xstats_names,
  97                                     unsigned int size);
  98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  99                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 100                 unsigned int limit);
 101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
 102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
 103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 104                                    char *fw_version, size_t fw_size);
 105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
 106                               struct rte_eth_dev_info *dev_info);
 107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_dev_info *dev_info);
 110 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 113                                 struct rte_eth_fc_conf *fc_conf);
 114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 118                                     struct rte_intr_handle *handle);
 119 static void eth_igb_interrupt_handler(void *param);
 120 static int  igb_hardware_init(struct e1000_hw *hw);
 121 static void igb_hw_control_acquire(struct e1000_hw *hw);
 122 static void igb_hw_control_release(struct e1000_hw *hw);
 123 static void igb_init_manageability(struct e1000_hw *hw);
 124 static void igb_release_manageability(struct e1000_hw *hw);
 125
 126 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 127
 128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 129                 uint16_t vlan_id, int on);
 130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 131                                  enum rte_vlan_type vlan_type,
 132                                  uint16_t tpid_id);
 133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134
 135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 141
 142 static int eth_igb_led_on(struct rte_eth_dev *dev);
 143 static int eth_igb_led_off(struct rte_eth_dev *dev);
 144
 145 static void igb_intr_disable(struct rte_eth_dev *dev);
 146 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 148                            struct rte_ether_addr *mac_addr,
 149                            uint32_t index, uint32_t pool);
 150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 152                 struct rte_ether_addr *addr);
 153
 154 static void igbvf_intr_disable(struct e1000_hw *hw);
 155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 156 static int igbvf_dev_start(struct rte_eth_dev *dev);
 157 static int igbvf_dev_stop(struct rte_eth_dev *dev);
 158 static int igbvf_dev_close(struct rte_eth_dev *dev);
 159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 163 static int eth_igbvf_link_update(struct e1000_hw *hw);
 164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_stats *rte_stats);
 166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 167                                 struct rte_eth_xstat *xstats, unsigned n);
 168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 169                                       struct rte_eth_xstat_name *xstats_names,
 170                                       unsigned limit);
 171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 173                 uint16_t vlan_id, int on);
 174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 177                 struct rte_ether_addr *addr);
 178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 179 static int igbvf_get_regs(struct rte_eth_dev *dev,
 180                 struct rte_dev_reg_info *regs);
 181
 182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 183                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                    uint16_t reta_size);
 185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 186                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 187                                   uint16_t reta_size);
 188
 189 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 190                         struct rte_eth_ntuple_filter *ntuple_filter);
 191 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 192                         struct rte_eth_ntuple_filter *ntuple_filter);
 193 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 194                         struct rte_eth_ntuple_filter *ntuple_filter);
 195 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 196                         struct rte_eth_ntuple_filter *ntuple_filter);
 197 static int eth_igb_flow_ops_get(struct rte_eth_dev *dev,
 198                                 const struct rte_flow_ops **ops);
 199 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 200 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 201                 struct rte_dev_reg_info *regs);
 202 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 203 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 204                 struct rte_dev_eeprom_info *eeprom);
 205 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 206                 struct rte_dev_eeprom_info *eeprom);
 207 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
 208                                    struct rte_eth_dev_module_info *modinfo);
 209 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
 210                                      struct rte_dev_eeprom_info *info);
 211 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 212                                     struct rte_ether_addr *mc_addr_set,
 213                                     uint32_t nb_mc_addr);
 214 static int igb_timesync_enable(struct rte_eth_dev *dev);
 215 static int igb_timesync_disable(struct rte_eth_dev *dev);
 216 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 217                                           struct timespec *timestamp,
 218                                           uint32_t flags);
 219 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 220                                           struct timespec *timestamp);
 221 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 222 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 223                                   struct timespec *timestamp);
 224 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 225                                    const struct timespec *timestamp);
 226 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 227                                         uint16_t queue_id);
 228 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 229                                          uint16_t queue_id);
 230 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 231                                        uint8_t queue, uint8_t msix_vector);
 232 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 233                                uint8_t index, uint8_t offset);
 234 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 235 static void eth_igbvf_interrupt_handler(void *param);
 236 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 237 static int igb_filter_restore(struct rte_eth_dev *dev);
 238
 239 /*
 240  * Define VF Stats MACRO for Non "cleared on read" register
 241  */
 242 #define UPDATE_VF_STAT(reg, last, cur)            \
 243 {                                                 \
 244         u32 latest = E1000_READ_REG(hw, reg);     \
 245         cur += (latest - last) & UINT_MAX;        \
 246         last = latest;                            \
 247 }
 248
 249 #define IGB_FC_PAUSE_TIME 0x0680
 250 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 251 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 252
 253 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 254
 255 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 256
 257 /*
 258  * The set of PCI devices this driver supports
 259  */
 260 static const struct rte_pci_id pci_id_igb_map[] = {
 261         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 262         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 263         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 264         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 265         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 266         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 267         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 268         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 269
 270         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 271         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 272         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 273
 274         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 275         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 276         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 277         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 278         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 279         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 280
 281         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 282         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 284         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 285         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 286         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 287         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 288         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 289         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 290         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 291         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 292         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 295         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 296         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 297         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 302         { .vendor_id = 0, /* sentinel */ },
 303 };
 304
 305 /*
 306  * The set of PCI devices this driver supports (for 82576&I350 VF)
 307  */
 308 static const struct rte_pci_id pci_id_igbvf_map[] = {
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 313         { .vendor_id = 0, /* sentinel */ },
 314 };
 315
 316 static const struct rte_eth_desc_lim rx_desc_lim = {
 317         .nb_max = E1000_MAX_RING_DESC,
 318         .nb_min = E1000_MIN_RING_DESC,
 319         .nb_align = IGB_RXD_ALIGN,
 320 };
 321
 322 static const struct rte_eth_desc_lim tx_desc_lim = {
 323         .nb_max = E1000_MAX_RING_DESC,
 324         .nb_min = E1000_MIN_RING_DESC,
 325         .nb_align = IGB_RXD_ALIGN,
 326         .nb_seg_max = IGB_TX_MAX_SEG,
 327         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 328 };
 329
 330 static const struct eth_dev_ops eth_igb_ops = {
 331         .dev_configure        = eth_igb_configure,
 332         .dev_start            = eth_igb_start,
 333         .dev_stop             = eth_igb_stop,
 334         .dev_set_link_up      = eth_igb_dev_set_link_up,
 335         .dev_set_link_down    = eth_igb_dev_set_link_down,
 336         .dev_close            = eth_igb_close,
 337         .dev_reset            = eth_igb_reset,
 338         .promiscuous_enable   = eth_igb_promiscuous_enable,
 339         .promiscuous_disable  = eth_igb_promiscuous_disable,
 340         .allmulticast_enable  = eth_igb_allmulticast_enable,
 341         .allmulticast_disable = eth_igb_allmulticast_disable,
 342         .link_update          = eth_igb_link_update,
 343         .stats_get            = eth_igb_stats_get,
 344         .xstats_get           = eth_igb_xstats_get,
 345         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 346         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 347         .xstats_get_names     = eth_igb_xstats_get_names,
 348         .stats_reset          = eth_igb_stats_reset,
 349         .xstats_reset         = eth_igb_xstats_reset,
 350         .fw_version_get       = eth_igb_fw_version_get,
 351         .dev_infos_get        = eth_igb_infos_get,
 352         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 353         .mtu_set              = eth_igb_mtu_set,
 354         .vlan_filter_set      = eth_igb_vlan_filter_set,
 355         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 356         .vlan_offload_set     = eth_igb_vlan_offload_set,
 357         .rx_queue_setup       = eth_igb_rx_queue_setup,
 358         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 359         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 360         .rx_queue_release     = eth_igb_rx_queue_release,
 361         .tx_queue_setup       = eth_igb_tx_queue_setup,
 362         .tx_queue_release     = eth_igb_tx_queue_release,
 363         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 364         .dev_led_on           = eth_igb_led_on,
 365         .dev_led_off          = eth_igb_led_off,
 366         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 367         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 368         .mac_addr_add         = eth_igb_rar_set,
 369         .mac_addr_remove      = eth_igb_rar_clear,
 370         .mac_addr_set         = eth_igb_default_mac_addr_set,
 371         .reta_update          = eth_igb_rss_reta_update,
 372         .reta_query           = eth_igb_rss_reta_query,
 373         .rss_hash_update      = eth_igb_rss_hash_update,
 374         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 375         .flow_ops_get         = eth_igb_flow_ops_get,
 376         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 377         .rxq_info_get         = igb_rxq_info_get,
 378         .txq_info_get         = igb_txq_info_get,
 379         .timesync_enable      = igb_timesync_enable,
 380         .timesync_disable     = igb_timesync_disable,
 381         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 382         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 383         .get_reg              = eth_igb_get_regs,
 384         .get_eeprom_length    = eth_igb_get_eeprom_length,
 385         .get_eeprom           = eth_igb_get_eeprom,
 386         .set_eeprom           = eth_igb_set_eeprom,
 387         .get_module_info      = eth_igb_get_module_info,
 388         .get_module_eeprom    = eth_igb_get_module_eeprom,
 389         .timesync_adjust_time = igb_timesync_adjust_time,
 390         .timesync_read_time   = igb_timesync_read_time,
 391         .timesync_write_time  = igb_timesync_write_time,
 392 };
 393
 394 /*
 395  * dev_ops for virtual function, bare necessities for basic vf
 396  * operation have been implemented
 397  */
 398 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 399         .dev_configure        = igbvf_dev_configure,
 400         .dev_start            = igbvf_dev_start,
 401         .dev_stop             = igbvf_dev_stop,
 402         .dev_close            = igbvf_dev_close,
 403         .promiscuous_enable   = igbvf_promiscuous_enable,
 404         .promiscuous_disable  = igbvf_promiscuous_disable,
 405         .allmulticast_enable  = igbvf_allmulticast_enable,
 406         .allmulticast_disable = igbvf_allmulticast_disable,
 407         .link_update          = eth_igb_link_update,
 408         .stats_get            = eth_igbvf_stats_get,
 409         .xstats_get           = eth_igbvf_xstats_get,
 410         .xstats_get_names     = eth_igbvf_xstats_get_names,
 411         .stats_reset          = eth_igbvf_stats_reset,
 412         .xstats_reset         = eth_igbvf_stats_reset,
 413         .vlan_filter_set      = igbvf_vlan_filter_set,
 414         .dev_infos_get        = eth_igbvf_infos_get,
 415         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 416         .rx_queue_setup       = eth_igb_rx_queue_setup,
 417         .rx_queue_release     = eth_igb_rx_queue_release,
 418         .tx_queue_setup       = eth_igb_tx_queue_setup,
 419         .tx_queue_release     = eth_igb_tx_queue_release,
 420         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 421         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 422         .rxq_info_get         = igb_rxq_info_get,
 423         .txq_info_get         = igb_txq_info_get,
 424         .mac_addr_set         = igbvf_default_mac_addr_set,
 425         .get_reg              = igbvf_get_regs,
 426 };
 427
 428 /* store statistics names and its offset in stats structure */
 429 struct rte_igb_xstats_name_off {
 430         char name[RTE_ETH_XSTATS_NAME_SIZE];
 431         unsigned offset;
 432 };
 433
 434 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 435         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 436         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 437         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 438         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 439         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 440         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 441         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 442                 ecol)},
 443         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 444         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 445         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 446         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 447         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 448         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 449         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 450         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 451         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 452         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 453         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 454                 fcruc)},
 455         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 456         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 457         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 458         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 459         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 460                 prc1023)},
 461         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 462                 prc1522)},
 463         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 464         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 465         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 466         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 467         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 468         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 469         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 470         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 471         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 472         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 473         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 474         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 475         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 476         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 477         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 478         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 479         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 480         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 481                 ptc1023)},
 482         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 483                 ptc1522)},
 484         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 485         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 486         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 487         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 488         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 489         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 490         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 491
 492         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 493 };
 494
 495 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 496                 sizeof(rte_igb_stats_strings[0]))
 497
 498 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 499         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 500         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 501         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 502         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 503         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 504 };
 505
 506 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 507                 sizeof(rte_igbvf_stats_strings[0]))
 508
 509
 510 static inline void
 511 igb_intr_enable(struct rte_eth_dev *dev)
 512 {
 513         struct e1000_interrupt *intr =
 514                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 515         struct e1000_hw *hw =
 516                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 517         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 518         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 519
 520         if (rte_intr_allow_others(intr_handle) &&
 521                 dev->data->dev_conf.intr_conf.lsc != 0) {
 522                 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
 523         }
 524
 525         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 526         E1000_WRITE_FLUSH(hw);
 527 }
 528
 529 static void
 530 igb_intr_disable(struct rte_eth_dev *dev)
 531 {
 532         struct e1000_hw *hw =
 533                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 534         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 535         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 536
 537         if (rte_intr_allow_others(intr_handle) &&
 538                 dev->data->dev_conf.intr_conf.lsc != 0) {
 539                 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
 540         }
 541
 542         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 543         E1000_WRITE_FLUSH(hw);
 544 }
 545
 546 static inline void
 547 igbvf_intr_enable(struct rte_eth_dev *dev)
 548 {
 549         struct e1000_hw *hw =
 550                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 551
 552         /* only for mailbox */
 553         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 554         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 555         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 556         E1000_WRITE_FLUSH(hw);
 557 }
 558
 559 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 560 static void
 561 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 562 {
 563         uint32_t tmp = 0;
 564
 565         /* mailbox */
 566         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 567         tmp |= E1000_VTIVAR_VALID;
 568         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 569 }
 570
 571 static void
 572 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 573 {
 574         struct e1000_hw *hw =
 575                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 576
 577         /* Configure VF other cause ivar */
 578         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 579 }
 580
 581 static inline int32_t
 582 igb_pf_reset_hw(struct e1000_hw *hw)
 583 {
 584         uint32_t ctrl_ext;
 585         int32_t status;
 586
 587         status = e1000_reset_hw(hw);
 588
 589         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 590         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 591         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 592         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 593         E1000_WRITE_FLUSH(hw);
 594
 595         return status;
 596 }
 597
 598 static void
 599 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 600 {
 601         struct e1000_hw *hw =
 602                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 603
 604
 605         hw->vendor_id = pci_dev->id.vendor_id;
 606         hw->device_id = pci_dev->id.device_id;
 607         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 608         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 609
 610         e1000_set_mac_type(hw);
 611
 612         /* need to check if it is a vf device below */
 613 }
 614
 615 static int
 616 igb_reset_swfw_lock(struct e1000_hw *hw)
 617 {
 618         int ret_val;
 619
 620         /*
 621          * Do mac ops initialization manually here, since we will need
 622          * some function pointers set by this call.
 623          */
 624         ret_val = e1000_init_mac_params(hw);
 625         if (ret_val)
 626                 return ret_val;
 627
 628         /*
 629          * SMBI lock should not fail in this early stage. If this is the case,
 630          * it is due to an improper exit of the application.
 631          * So force the release of the faulty lock.
 632          */
 633         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 634                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 635         }
 636         e1000_put_hw_semaphore_generic(hw);
 637
 638         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 639                 uint16_t mask;
 640
 641                 /*
 642                  * Phy lock should not fail in this early stage. If this is the case,
 643                  * it is due to an improper exit of the application.
 644                  * So force the release of the faulty lock.
 645                  */
 646                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 647                 if (hw->bus.func > E1000_FUNC_1)
 648                         mask <<= 2;
 649                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 650                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 651                                     hw->bus.func);
 652                 }
 653                 hw->mac.ops.release_swfw_sync(hw, mask);
 654
 655                 /*
 656                  * This one is more tricky since it is common to all ports; but
 657                  * swfw_sync retries last long enough (1s) to be almost sure that if
 658                  * lock can not be taken it is due to an improper lock of the
 659                  * semaphore.
 660                  */
 661                 mask = E1000_SWFW_EEP_SM;
 662                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 663                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 664                 }
 665                 hw->mac.ops.release_swfw_sync(hw, mask);
 666         }
 667
 668         return E1000_SUCCESS;
 669 }
 670
 671 /* Remove all ntuple filters of the device */
 672 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 673 {
 674         struct e1000_filter_info *filter_info =
 675                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 676         struct e1000_5tuple_filter *p_5tuple;
 677         struct e1000_2tuple_filter *p_2tuple;
 678
 679         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 680                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 681                         p_5tuple, entries);
 682                         rte_free(p_5tuple);
 683         }
 684         filter_info->fivetuple_mask = 0;
 685         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 686                 TAILQ_REMOVE(&filter_info->twotuple_list,
 687                         p_2tuple, entries);
 688                         rte_free(p_2tuple);
 689         }
 690         filter_info->twotuple_mask = 0;
 691
 692         return 0;
 693 }
 694
 695 /* Remove all flex filters of the device */
 696 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 697 {
 698         struct e1000_filter_info *filter_info =
 699                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 700         struct e1000_flex_filter *p_flex;
 701
 702         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 703                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 704                 rte_free(p_flex);
 705         }
 706         filter_info->flex_mask = 0;
 707
 708         return 0;
 709 }
 710
 711 static int
 712 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 713 {
 714         int error = 0;
 715         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 716         struct e1000_hw *hw =
 717                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 718         struct e1000_vfta * shadow_vfta =
 719                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 720         struct e1000_filter_info *filter_info =
 721                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 722         struct e1000_adapter *adapter =
 723                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 724
 725         uint32_t ctrl_ext;
 726
 727         eth_dev->dev_ops = &eth_igb_ops;
 728         eth_dev->rx_queue_count = eth_igb_rx_queue_count;
 729         eth_dev->rx_descriptor_done   = eth_igb_rx_descriptor_done;
 730         eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
 731         eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
 732         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 733         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 734         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 735
 736         /* for secondary processes, we don't initialise any further as primary
 737          * has already done this work. Only check we don't need a different
 738          * RX function */
 739         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 740                 if (eth_dev->data->scattered_rx)
 741                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 742                 return 0;
 743         }
 744
 745         rte_eth_copy_pci_info(eth_dev, pci_dev);
 746         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 747
 748         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 749
 750         igb_identify_hardware(eth_dev, pci_dev);
 751         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 752                 error = -EIO;
 753                 goto err_late;
 754         }
 755
 756         e1000_get_bus_info(hw);
 757
 758         /* Reset any pending lock */
 759         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 760                 error = -EIO;
 761                 goto err_late;
 762         }
 763
 764         /* Finish initialization */
 765         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 766                 error = -EIO;
 767                 goto err_late;
 768         }
 769
 770         hw->mac.autoneg = 1;
 771         hw->phy.autoneg_wait_to_complete = 0;
 772         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 773
 774         /* Copper options */
 775         if (hw->phy.media_type == e1000_media_type_copper) {
 776                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 777                 hw->phy.disable_polarity_correction = 0;
 778                 hw->phy.ms_type = e1000_ms_hw_default;
 779         }
 780
 781         /*
 782          * Start from a known state, this is important in reading the nvm
 783          * and mac from that.
 784          */
 785         igb_pf_reset_hw(hw);
 786
 787         /* Make sure we have a good EEPROM before we read from it */
 788         if (e1000_validate_nvm_checksum(hw) < 0) {
 789                 /*
 790                  * Some PCI-E parts fail the first check due to
 791                  * the link being in sleep state, call it again,
 792                  * if it fails a second time its a real issue.
 793                  */
 794                 if (e1000_validate_nvm_checksum(hw) < 0) {
 795                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 796                         error = -EIO;
 797                         goto err_late;
 798                 }
 799         }
 800
 801         /* Read the permanent MAC address out of the EEPROM */
 802         if (e1000_read_mac_addr(hw) != 0) {
 803                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 804                 error = -EIO;
 805                 goto err_late;
 806         }
 807
 808         /* Allocate memory for storing MAC addresses */
 809         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 810                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 811         if (eth_dev->data->mac_addrs == NULL) {
 812                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 813                                                 "store MAC addresses",
 814                                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 815                 error = -ENOMEM;
 816                 goto err_late;
 817         }
 818
 819         /* Copy the permanent MAC address */
 820         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 821                         &eth_dev->data->mac_addrs[0]);
 822
 823         /* initialize the vfta */
 824         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 825
 826         /* Now initialize the hardware */
 827         if (igb_hardware_init(hw) != 0) {
 828                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 829                 rte_free(eth_dev->data->mac_addrs);
 830                 eth_dev->data->mac_addrs = NULL;
 831                 error = -ENODEV;
 832                 goto err_late;
 833         }
 834         hw->mac.get_link_status = 1;
 835         adapter->stopped = 0;
 836
 837         /* Indicate SOL/IDER usage */
 838         if (e1000_check_reset_block(hw) < 0) {
 839                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 840                                         "SOL/IDER session");
 841         }
 842
 843         /* initialize PF if max_vfs not zero */
 844         igb_pf_host_init(eth_dev);
 845
 846         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 847         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 848         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 849         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 850         E1000_WRITE_FLUSH(hw);
 851
 852         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 853                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 854                      pci_dev->id.device_id);
 855
 856         rte_intr_callback_register(&pci_dev->intr_handle,
 857                                    eth_igb_interrupt_handler,
 858                                    (void *)eth_dev);
 859
 860         /* enable uio/vfio intr/eventfd mapping */
 861         rte_intr_enable(&pci_dev->intr_handle);
 862
 863         /* enable support intr */
 864         igb_intr_enable(eth_dev);
 865
 866         eth_igb_dev_set_link_down(eth_dev);
 867
 868         /* initialize filter info */
 869         memset(filter_info, 0,
 870                sizeof(struct e1000_filter_info));
 871
 872         TAILQ_INIT(&filter_info->flex_list);
 873         TAILQ_INIT(&filter_info->twotuple_list);
 874         TAILQ_INIT(&filter_info->fivetuple_list);
 875
 876         TAILQ_INIT(&igb_filter_ntuple_list);
 877         TAILQ_INIT(&igb_filter_ethertype_list);
 878         TAILQ_INIT(&igb_filter_syn_list);
 879         TAILQ_INIT(&igb_filter_flex_list);
 880         TAILQ_INIT(&igb_filter_rss_list);
 881         TAILQ_INIT(&igb_flow_list);
 882
 883         return 0;
 884
 885 err_late:
 886         igb_hw_control_release(hw);
 887
 888         return error;
 889 }
 890
 891 static int
 892 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 893 {
 894         PMD_INIT_FUNC_TRACE();
 895
 896         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 897                 return 0;
 898
 899         eth_igb_close(eth_dev);
 900
 901         return 0;
 902 }
 903
 904 /*
 905  * Virtual Function device init
 906  */
 907 static int
 908 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 909 {
 910         struct rte_pci_device *pci_dev;
 911         struct rte_intr_handle *intr_handle;
 912         struct e1000_adapter *adapter =
 913                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 914         struct e1000_hw *hw =
 915                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 916         int diag;
 917         struct rte_ether_addr *perm_addr =
 918                 (struct rte_ether_addr *)hw->mac.perm_addr;
 919
 920         PMD_INIT_FUNC_TRACE();
 921
 922         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 923         eth_dev->rx_descriptor_done   = eth_igb_rx_descriptor_done;
 924         eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
 925         eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
 926         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 927         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 928         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 929
 930         /* for secondary processes, we don't initialise any further as primary
 931          * has already done this work. Only check we don't need a different
 932          * RX function */
 933         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 934                 if (eth_dev->data->scattered_rx)
 935                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 936                 return 0;
 937         }
 938
 939         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 940         rte_eth_copy_pci_info(eth_dev, pci_dev);
 941         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 942
 943         hw->device_id = pci_dev->id.device_id;
 944         hw->vendor_id = pci_dev->id.vendor_id;
 945         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 946         adapter->stopped = 0;
 947
 948         /* Initialize the shared code (base driver) */
 949         diag = e1000_setup_init_funcs(hw, TRUE);
 950         if (diag != 0) {
 951                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 952                         diag);
 953                 return -EIO;
 954         }
 955
 956         /* init_mailbox_params */
 957         hw->mbx.ops.init_params(hw);
 958
 959         /* Disable the interrupts for VF */
 960         igbvf_intr_disable(hw);
 961
 962         diag = hw->mac.ops.reset_hw(hw);
 963
 964         /* Allocate memory for storing MAC addresses */
 965         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
 966                 hw->mac.rar_entry_count, 0);
 967         if (eth_dev->data->mac_addrs == NULL) {
 968                 PMD_INIT_LOG(ERR,
 969                         "Failed to allocate %d bytes needed to store MAC "
 970                         "addresses",
 971                         RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 972                 return -ENOMEM;
 973         }
 974
 975         /* Generate a random MAC address, if none was assigned by PF. */
 976         if (rte_is_zero_ether_addr(perm_addr)) {
 977                 rte_eth_random_addr(perm_addr->addr_bytes);
 978                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
 979                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
 980                              "%02x:%02x:%02x:%02x:%02x:%02x",
 981                              perm_addr->addr_bytes[0],
 982                              perm_addr->addr_bytes[1],
 983                              perm_addr->addr_bytes[2],
 984                              perm_addr->addr_bytes[3],
 985                              perm_addr->addr_bytes[4],
 986                              perm_addr->addr_bytes[5]);
 987         }
 988
 989         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
 990         if (diag) {
 991                 rte_free(eth_dev->data->mac_addrs);
 992                 eth_dev->data->mac_addrs = NULL;
 993                 return diag;
 994         }
 995         /* Copy the permanent MAC address */
 996         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
 997                         &eth_dev->data->mac_addrs[0]);
 998
 999         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1000                      "mac.type=%s",
1001                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1002                      pci_dev->id.device_id, "igb_mac_82576_vf");
1003
1004         intr_handle = &pci_dev->intr_handle;
1005         rte_intr_callback_register(intr_handle,
1006                                    eth_igbvf_interrupt_handler, eth_dev);
1007
1008         return 0;
1009 }
1010
1011 static int
1012 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1013 {
1014         PMD_INIT_FUNC_TRACE();
1015
1016         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1017                 return 0;
1018
1019         igbvf_dev_close(eth_dev);
1020
1021         return 0;
1022 }
1023
1024 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1025         struct rte_pci_device *pci_dev)
1026 {
1027         return rte_eth_dev_pci_generic_probe(pci_dev,
1028                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1029 }
1030
1031 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1032 {
1033         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1034 }
1035
1036 static struct rte_pci_driver rte_igb_pmd = {
1037         .id_table = pci_id_igb_map,
1038         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1039         .probe = eth_igb_pci_probe,
1040         .remove = eth_igb_pci_remove,
1041 };
1042
1043
1044 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1045         struct rte_pci_device *pci_dev)
1046 {
1047         return rte_eth_dev_pci_generic_probe(pci_dev,
1048                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1049 }
1050
1051 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1052 {
1053         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1054 }
1055
1056 /*
1057  * virtual function driver struct
1058  */
1059 static struct rte_pci_driver rte_igbvf_pmd = {
1060         .id_table = pci_id_igbvf_map,
1061         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1062         .probe = eth_igbvf_pci_probe,
1063         .remove = eth_igbvf_pci_remove,
1064 };
1065
1066 static void
1067 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1068 {
1069         struct e1000_hw *hw =
1070                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1071         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1072         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1073         rctl |= E1000_RCTL_VFE;
1074         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1075 }
1076
1077 static int
1078 igb_check_mq_mode(struct rte_eth_dev *dev)
1079 {
1080         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1081         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1082         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1083         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1084
1085         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1086             tx_mq_mode == ETH_MQ_TX_DCB ||
1087             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1088                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1089                 return -EINVAL;
1090         }
1091         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1092                 /* Check multi-queue mode.
1093                  * To no break software we accept ETH_MQ_RX_NONE as this might
1094                  * be used to turn off VLAN filter.
1095                  */
1096
1097                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1098                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1099                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1100                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1101                 } else {
1102                         /* Only support one queue on VFs.
1103                          * RSS together with SRIOV is not supported.
1104                          */
1105                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1106                                         " wrong mq_mode rx %d.",
1107                                         rx_mq_mode);
1108                         return -EINVAL;
1109                 }
1110                 /* TX mode is not used here, so mode might be ignored.*/
1111                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1112                         /* SRIOV only works in VMDq enable mode */
1113                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1114                                         " TX mode %d is not supported. "
1115                                         " Driver will behave as %d mode.",
1116                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1117                 }
1118
1119                 /* check valid queue number */
1120                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1121                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1122                                         " only support one queue on VFs.");
1123                         return -EINVAL;
1124                 }
1125         } else {
1126                 /* To no break software that set invalid mode, only display
1127                  * warning if invalid mode is used.
1128                  */
1129                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1130                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1131                     rx_mq_mode != ETH_MQ_RX_RSS) {
1132                         /* RSS together with VMDq not supported*/
1133                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1134                                      rx_mq_mode);
1135                         return -EINVAL;
1136                 }
1137
1138                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1139                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1140                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1141                                         " Due to txmode is meaningless in this"
1142                                         " driver, just ignore.",
1143                                         tx_mq_mode);
1144                 }
1145         }
1146         return 0;
1147 }
1148
1149 static int
1150 eth_igb_configure(struct rte_eth_dev *dev)
1151 {
1152         struct e1000_interrupt *intr =
1153                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1154         int ret;
1155
1156         PMD_INIT_FUNC_TRACE();
1157
1158         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1159                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1160
1161         /* multipe queue mode checking */
1162         ret  = igb_check_mq_mode(dev);
1163         if (ret != 0) {
1164                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1165                             ret);
1166                 return ret;
1167         }
1168
1169         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1170         PMD_INIT_FUNC_TRACE();
1171
1172         return 0;
1173 }
1174
1175 static void
1176 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1177                      bool enable)
1178 {
1179         struct e1000_hw *hw =
1180                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1181         uint32_t tctl, rctl;
1182
1183         tctl = E1000_READ_REG(hw, E1000_TCTL);
1184         rctl = E1000_READ_REG(hw, E1000_RCTL);
1185
1186         if (enable) {
1187                 /* enable Tx/Rx */
1188                 tctl |= E1000_TCTL_EN;
1189                 rctl |= E1000_RCTL_EN;
1190         } else {
1191                 /* disable Tx/Rx */
1192                 tctl &= ~E1000_TCTL_EN;
1193                 rctl &= ~E1000_RCTL_EN;
1194         }
1195         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1196         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1197         E1000_WRITE_FLUSH(hw);
1198 }
1199
1200 static int
1201 eth_igb_start(struct rte_eth_dev *dev)
1202 {
1203         struct e1000_hw *hw =
1204                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205         struct e1000_adapter *adapter =
1206                 E1000_DEV_PRIVATE(dev->data->dev_private);
1207         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1208         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1209         int ret, mask;
1210         uint32_t intr_vector = 0;
1211         uint32_t ctrl_ext;
1212         uint32_t *speeds;
1213         int num_speeds;
1214         bool autoneg;
1215
1216         PMD_INIT_FUNC_TRACE();
1217
1218         /* disable uio/vfio intr/eventfd mapping */
1219         rte_intr_disable(intr_handle);
1220
1221         /* Power up the phy. Needed to make the link go Up */
1222         eth_igb_dev_set_link_up(dev);
1223
1224         /*
1225          * Packet Buffer Allocation (PBA)
1226          * Writing PBA sets the receive portion of the buffer
1227          * the remainder is used for the transmit buffer.
1228          */
1229         if (hw->mac.type == e1000_82575) {
1230                 uint32_t pba;
1231
1232                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1233                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1234         }
1235
1236         /* Put the address into the Receive Address Array */
1237         e1000_rar_set(hw, hw->mac.addr, 0);
1238
1239         /* Initialize the hardware */
1240         if (igb_hardware_init(hw)) {
1241                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1242                 return -EIO;
1243         }
1244         adapter->stopped = 0;
1245
1246         E1000_WRITE_REG(hw, E1000_VET,
1247                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1248
1249         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1250         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1251         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1252         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1253         E1000_WRITE_FLUSH(hw);
1254
1255         /* configure PF module if SRIOV enabled */
1256         igb_pf_host_configure(dev);
1257
1258         /* check and configure queue intr-vector mapping */
1259         if ((rte_intr_cap_multiple(intr_handle) ||
1260              !RTE_ETH_DEV_SRIOV(dev).active) &&
1261             dev->data->dev_conf.intr_conf.rxq != 0) {
1262                 intr_vector = dev->data->nb_rx_queues;
1263                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1264                         return -1;
1265         }
1266
1267         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1268                 intr_handle->intr_vec =
1269                         rte_zmalloc("intr_vec",
1270                                     dev->data->nb_rx_queues * sizeof(int), 0);
1271                 if (intr_handle->intr_vec == NULL) {
1272                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1273                                      " intr_vec", dev->data->nb_rx_queues);
1274                         return -ENOMEM;
1275                 }
1276         }
1277
1278         /* confiugre msix for rx interrupt */
1279         eth_igb_configure_msix_intr(dev);
1280
1281         /* Configure for OS presence */
1282         igb_init_manageability(hw);
1283
1284         eth_igb_tx_init(dev);
1285
1286         /* This can fail when allocating mbufs for descriptor rings */
1287         ret = eth_igb_rx_init(dev);
1288         if (ret) {
1289                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1290                 igb_dev_clear_queues(dev);
1291                 return ret;
1292         }
1293
1294         e1000_clear_hw_cntrs_base_generic(hw);
1295
1296         /*
1297          * VLAN Offload Settings
1298          */
1299         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1300                         ETH_VLAN_EXTEND_MASK;
1301         ret = eth_igb_vlan_offload_set(dev, mask);
1302         if (ret) {
1303                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1304                 igb_dev_clear_queues(dev);
1305                 return ret;
1306         }
1307
1308         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1309                 /* Enable VLAN filter since VMDq always use VLAN filter */
1310                 igb_vmdq_vlan_hw_filter_enable(dev);
1311         }
1312
1313         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1314                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1315                 (hw->mac.type == e1000_i211)) {
1316                 /* Configure EITR with the maximum possible value (0xFFFF) */
1317                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1318         }
1319
1320         /* Setup link speed and duplex */
1321         speeds = &dev->data->dev_conf.link_speeds;
1322         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1323                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1324                 hw->mac.autoneg = 1;
1325         } else {
1326                 num_speeds = 0;
1327                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1328
1329                 /* Reset */
1330                 hw->phy.autoneg_advertised = 0;
1331
1332                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1333                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1334                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1335                         num_speeds = -1;
1336                         goto error_invalid_config;
1337                 }
1338                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1339                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1340                         num_speeds++;
1341                 }
1342                 if (*speeds & ETH_LINK_SPEED_10M) {
1343                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1344                         num_speeds++;
1345                 }
1346                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1347                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1348                         num_speeds++;
1349                 }
1350                 if (*speeds & ETH_LINK_SPEED_100M) {
1351                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1352                         num_speeds++;
1353                 }
1354                 if (*speeds & ETH_LINK_SPEED_1G) {
1355                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1356                         num_speeds++;
1357                 }
1358                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1359                         goto error_invalid_config;
1360
1361                 /* Set/reset the mac.autoneg based on the link speed,
1362                  * fixed or not
1363                  */
1364                 if (!autoneg) {
1365                         hw->mac.autoneg = 0;
1366                         hw->mac.forced_speed_duplex =
1367                                         hw->phy.autoneg_advertised;
1368                 } else {
1369                         hw->mac.autoneg = 1;
1370                 }
1371         }
1372
1373         e1000_setup_link(hw);
1374
1375         if (rte_intr_allow_others(intr_handle)) {
1376                 /* check if lsc interrupt is enabled */
1377                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1378                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1379                 else
1380                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1381         } else {
1382                 rte_intr_callback_unregister(intr_handle,
1383                                              eth_igb_interrupt_handler,
1384                                              (void *)dev);
1385                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1386                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1387                                      " no intr multiplex");
1388         }
1389
1390         /* check if rxq interrupt is enabled */
1391         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1392             rte_intr_dp_is_en(intr_handle))
1393                 eth_igb_rxq_interrupt_setup(dev);
1394
1395         /* enable uio/vfio intr/eventfd mapping */
1396         rte_intr_enable(intr_handle);
1397
1398         /* resume enabled intr since hw reset */
1399         igb_intr_enable(dev);
1400
1401         /* restore all types filter */
1402         igb_filter_restore(dev);
1403
1404         eth_igb_rxtx_control(dev, true);
1405         eth_igb_link_update(dev, 0);
1406
1407         PMD_INIT_LOG(DEBUG, "<<");
1408
1409         return 0;
1410
1411 error_invalid_config:
1412         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1413                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1414         igb_dev_clear_queues(dev);
1415         return -EINVAL;
1416 }
1417
1418 /*********************************************************************
1419  *
1420  *  This routine disables all traffic on the adapter by issuing a
1421  *  global reset on the MAC.
1422  *
1423  **********************************************************************/
1424 static int
1425 eth_igb_stop(struct rte_eth_dev *dev)
1426 {
1427         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1429         struct rte_eth_link link;
1430         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1431         struct e1000_adapter *adapter =
1432                 E1000_DEV_PRIVATE(dev->data->dev_private);
1433
1434         if (adapter->stopped)
1435                 return 0;
1436
1437         eth_igb_rxtx_control(dev, false);
1438
1439         igb_intr_disable(dev);
1440
1441         /* disable intr eventfd mapping */
1442         rte_intr_disable(intr_handle);
1443
1444         igb_pf_reset_hw(hw);
1445         E1000_WRITE_REG(hw, E1000_WUC, 0);
1446
1447         /* Set bit for Go Link disconnect if PHY reset is not blocked */
1448         if (hw->mac.type >= e1000_82580 &&
1449             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1450                 uint32_t phpm_reg;
1451
1452                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1453                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1454                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1455         }
1456
1457         /* Power down the phy. Needed to make the link go Down */
1458         eth_igb_dev_set_link_down(dev);
1459
1460         igb_dev_clear_queues(dev);
1461
1462         /* clear the recorded link status */
1463         memset(&link, 0, sizeof(link));
1464         rte_eth_linkstatus_set(dev, &link);
1465
1466         if (!rte_intr_allow_others(intr_handle))
1467                 /* resume to the default handler */
1468                 rte_intr_callback_register(intr_handle,
1469                                            eth_igb_interrupt_handler,
1470                                            (void *)dev);
1471
1472         /* Clean datapath event and queue/vec mapping */
1473         rte_intr_efd_disable(intr_handle);
1474         if (intr_handle->intr_vec != NULL) {
1475                 rte_free(intr_handle->intr_vec);
1476                 intr_handle->intr_vec = NULL;
1477         }
1478
1479         adapter->stopped = true;
1480         dev->data->dev_started = 0;
1481
1482         return 0;
1483 }
1484
1485 static int
1486 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1487 {
1488         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1489
1490         if (hw->phy.media_type == e1000_media_type_copper)
1491                 e1000_power_up_phy(hw);
1492         else
1493                 e1000_power_up_fiber_serdes_link(hw);
1494
1495         return 0;
1496 }
1497
1498 static int
1499 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1500 {
1501         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1502
1503         if (hw->phy.media_type == e1000_media_type_copper)
1504                 e1000_power_down_phy(hw);
1505         else
1506                 e1000_shutdown_fiber_serdes_link(hw);
1507
1508         return 0;
1509 }
1510
1511 static int
1512 eth_igb_close(struct rte_eth_dev *dev)
1513 {
1514         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1515         struct rte_eth_link link;
1516         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1517         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1518         struct e1000_filter_info *filter_info =
1519                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1520         int ret;
1521
1522         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1523                 return 0;
1524
1525         ret = eth_igb_stop(dev);
1526
1527         e1000_phy_hw_reset(hw);
1528         igb_release_manageability(hw);
1529         igb_hw_control_release(hw);
1530
1531         /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1532         if (hw->mac.type >= e1000_82580 &&
1533             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1534                 uint32_t phpm_reg;
1535
1536                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1537                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1538                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1539         }
1540
1541         igb_dev_free_queues(dev);
1542
1543         if (intr_handle->intr_vec) {
1544                 rte_free(intr_handle->intr_vec);
1545                 intr_handle->intr_vec = NULL;
1546         }
1547
1548         memset(&link, 0, sizeof(link));
1549         rte_eth_linkstatus_set(dev, &link);
1550
1551         /* Reset any pending lock */
1552         igb_reset_swfw_lock(hw);
1553
1554         /* uninitialize PF if max_vfs not zero */
1555         igb_pf_host_uninit(dev);
1556
1557         rte_intr_callback_unregister(intr_handle,
1558                                      eth_igb_interrupt_handler, dev);
1559
1560         /* clear the SYN filter info */
1561         filter_info->syn_info = 0;
1562
1563         /* clear the ethertype filters info */
1564         filter_info->ethertype_mask = 0;
1565         memset(filter_info->ethertype_filters, 0,
1566                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1567
1568         /* clear the rss filter info */
1569         memset(&filter_info->rss_info, 0,
1570                 sizeof(struct igb_rte_flow_rss_conf));
1571
1572         /* remove all ntuple filters of the device */
1573         igb_ntuple_filter_uninit(dev);
1574
1575         /* remove all flex filters of the device */
1576         igb_flex_filter_uninit(dev);
1577
1578         /* clear all the filters list */
1579         igb_filterlist_flush(dev);
1580
1581         return ret;
1582 }
1583
1584 /*
1585  * Reset PF device.
1586  */
1587 static int
1588 eth_igb_reset(struct rte_eth_dev *dev)
1589 {
1590         int ret;
1591
1592         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1593          * its VF to make them align with it. The detailed notification
1594          * mechanism is PMD specific and is currently not implemented.
1595          * To avoid unexpected behavior in VF, currently reset of PF with
1596          * SR-IOV activation is not supported. It might be supported later.
1597          */
1598         if (dev->data->sriov.active)
1599                 return -ENOTSUP;
1600
1601         ret = eth_igb_dev_uninit(dev);
1602         if (ret)
1603                 return ret;
1604
1605         ret = eth_igb_dev_init(dev);
1606
1607         return ret;
1608 }
1609
1610
1611 static int
1612 igb_get_rx_buffer_size(struct e1000_hw *hw)
1613 {
1614         uint32_t rx_buf_size;
1615         if (hw->mac.type == e1000_82576) {
1616                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1617         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1618                 /* PBS needs to be translated according to a lookup table */
1619                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1620                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1621                 rx_buf_size = (rx_buf_size << 10);
1622         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1623                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1624         } else {
1625                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1626         }
1627
1628         return rx_buf_size;
1629 }
1630
1631 /*********************************************************************
1632  *
1633  *  Initialize the hardware
1634  *
1635  **********************************************************************/
1636 static int
1637 igb_hardware_init(struct e1000_hw *hw)
1638 {
1639         uint32_t rx_buf_size;
1640         int diag;
1641
1642         /* Let the firmware know the OS is in control */
1643         igb_hw_control_acquire(hw);
1644
1645         /*
1646          * These parameters control the automatic generation (Tx) and
1647          * response (Rx) to Ethernet PAUSE frames.
1648          * - High water mark should allow for at least two standard size (1518)
1649          *   frames to be received after sending an XOFF.
1650          * - Low water mark works best when it is very near the high water mark.
1651          *   This allows the receiver to restart by sending XON when it has
1652          *   drained a bit. Here we use an arbitrary value of 1500 which will
1653          *   restart after one full frame is pulled from the buffer. There
1654          *   could be several smaller frames in the buffer and if so they will
1655          *   not trigger the XON until their total number reduces the buffer
1656          *   by 1500.
1657          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1658          */
1659         rx_buf_size = igb_get_rx_buffer_size(hw);
1660
1661         hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1662         hw->fc.low_water = hw->fc.high_water - 1500;
1663         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1664         hw->fc.send_xon = 1;
1665
1666         /* Set Flow control, use the tunable location if sane */
1667         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1668                 hw->fc.requested_mode = igb_fc_setting;
1669         else
1670                 hw->fc.requested_mode = e1000_fc_none;
1671
1672         /* Issue a global reset */
1673         igb_pf_reset_hw(hw);
1674         E1000_WRITE_REG(hw, E1000_WUC, 0);
1675
1676         diag = e1000_init_hw(hw);
1677         if (diag < 0)
1678                 return diag;
1679
1680         E1000_WRITE_REG(hw, E1000_VET,
1681                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1682         e1000_get_phy_info(hw);
1683         e1000_check_for_link(hw);
1684
1685         return 0;
1686 }
1687
1688 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1689 static void
1690 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1691 {
1692         int pause_frames;
1693
1694         uint64_t old_gprc  = stats->gprc;
1695         uint64_t old_gptc  = stats->gptc;
1696         uint64_t old_tpr   = stats->tpr;
1697         uint64_t old_tpt   = stats->tpt;
1698         uint64_t old_rpthc = stats->rpthc;
1699         uint64_t old_hgptc = stats->hgptc;
1700
1701         if(hw->phy.media_type == e1000_media_type_copper ||
1702             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1703                 stats->symerrs +=
1704                     E1000_READ_REG(hw,E1000_SYMERRS);
1705                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1706         }
1707
1708         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1709         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1710         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1711         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1712
1713         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1714         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1715         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1716         stats->dc += E1000_READ_REG(hw, E1000_DC);
1717         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1718         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1719         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1720         /*
1721         ** For watchdog management we need to know if we have been
1722         ** paused during the last interval, so capture that here.
1723         */
1724         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1725         stats->xoffrxc += pause_frames;
1726         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1727         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1728         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1729         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1730         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1731         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1732         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1733         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1734         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1735         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1736         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1737         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1738
1739         /* For the 64-bit byte counters the low dword must be read first. */
1740         /* Both registers clear on the read of the high dword */
1741
1742         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1743         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1744         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1745         stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1746         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1747         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1748         stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1749
1750         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1751         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1752         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1753         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1754         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1755
1756         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1757         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1758
1759         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1760         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1761         stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1762         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1763         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1764         stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1765
1766         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1767         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1768         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1769         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1770         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1771         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1772         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1773         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1774
1775         /* Interrupt Counts */
1776
1777         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1778         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1779         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1780         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1781         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1782         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1783         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1784         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1785         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1786
1787         /* Host to Card Statistics */
1788
1789         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1790         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1791         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1792         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1793         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1794         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1795         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1796         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1797         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1798         stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1799         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1800         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1801         stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1802         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1803         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1804         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1805
1806         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1807         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1808         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1809         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1810         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1811         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1812 }
1813
1814 static int
1815 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1816 {
1817         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1818         struct e1000_hw_stats *stats =
1819                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1820
1821         igb_read_stats_registers(hw, stats);
1822
1823         if (rte_stats == NULL)
1824                 return -EINVAL;
1825
1826         /* Rx Errors */
1827         rte_stats->imissed = stats->mpc;
1828         rte_stats->ierrors = stats->crcerrs + stats->rlec +
1829                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1830
1831         /* Tx Errors */
1832         rte_stats->oerrors = stats->ecol + stats->latecol;
1833
1834         rte_stats->ipackets = stats->gprc;
1835         rte_stats->opackets = stats->gptc;
1836         rte_stats->ibytes   = stats->gorc;
1837         rte_stats->obytes   = stats->gotc;
1838         return 0;
1839 }
1840
1841 static int
1842 eth_igb_stats_reset(struct rte_eth_dev *dev)
1843 {
1844         struct e1000_hw_stats *hw_stats =
1845                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1846
1847         /* HW registers are cleared on read */
1848         eth_igb_stats_get(dev, NULL);
1849
1850         /* Reset software totals */
1851         memset(hw_stats, 0, sizeof(*hw_stats));
1852
1853         return 0;
1854 }
1855
1856 static int
1857 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1858 {
1859         struct e1000_hw_stats *stats =
1860                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1861
1862         /* HW registers are cleared on read */
1863         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1864
1865         /* Reset software totals */
1866         memset(stats, 0, sizeof(*stats));
1867
1868         return 0;
1869 }
1870
1871 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1872         struct rte_eth_xstat_name *xstats_names,
1873         __rte_unused unsigned int size)
1874 {
1875         unsigned i;
1876
1877         if (xstats_names == NULL)
1878                 return IGB_NB_XSTATS;
1879
1880         /* Note: limit checked in rte_eth_xstats_names() */
1881
1882         for (i = 0; i < IGB_NB_XSTATS; i++) {
1883                 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1884                         sizeof(xstats_names[i].name));
1885         }
1886
1887         return IGB_NB_XSTATS;
1888 }
1889
1890 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1891                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1892                 unsigned int limit)
1893 {
1894         unsigned int i;
1895
1896         if (!ids) {
1897                 if (xstats_names == NULL)
1898                         return IGB_NB_XSTATS;
1899
1900                 for (i = 0; i < IGB_NB_XSTATS; i++)
1901                         strlcpy(xstats_names[i].name,
1902                                 rte_igb_stats_strings[i].name,
1903                                 sizeof(xstats_names[i].name));
1904
1905                 return IGB_NB_XSTATS;
1906
1907         } else {
1908                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1909
1910                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1911                                 IGB_NB_XSTATS);
1912
1913                 for (i = 0; i < limit; i++) {
1914                         if (ids[i] >= IGB_NB_XSTATS) {
1915                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1916                                 return -1;
1917                         }
1918                         strcpy(xstats_names[i].name,
1919                                         xstats_names_copy[ids[i]].name);
1920                 }
1921                 return limit;
1922         }
1923 }
1924
1925 static int
1926 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1927                    unsigned n)
1928 {
1929         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930         struct e1000_hw_stats *hw_stats =
1931                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1932         unsigned i;
1933
1934         if (n < IGB_NB_XSTATS)
1935                 return IGB_NB_XSTATS;
1936
1937         igb_read_stats_registers(hw, hw_stats);
1938
1939         /* If this is a reset xstats is NULL, and we have cleared the
1940          * registers by reading them.
1941          */
1942         if (!xstats)
1943                 return 0;
1944
1945         /* Extended stats */
1946         for (i = 0; i < IGB_NB_XSTATS; i++) {
1947                 xstats[i].id = i;
1948                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1949                         rte_igb_stats_strings[i].offset);
1950         }
1951
1952         return IGB_NB_XSTATS;
1953 }
1954
1955 static int
1956 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1957                 uint64_t *values, unsigned int n)
1958 {
1959         unsigned int i;
1960
1961         if (!ids) {
1962                 struct e1000_hw *hw =
1963                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1964                 struct e1000_hw_stats *hw_stats =
1965                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1966
1967                 if (n < IGB_NB_XSTATS)
1968                         return IGB_NB_XSTATS;
1969
1970                 igb_read_stats_registers(hw, hw_stats);
1971
1972                 /* If this is a reset xstats is NULL, and we have cleared the
1973                  * registers by reading them.
1974                  */
1975                 if (!values)
1976                         return 0;
1977
1978                 /* Extended stats */
1979                 for (i = 0; i < IGB_NB_XSTATS; i++)
1980                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1981                                         rte_igb_stats_strings[i].offset);
1982
1983                 return IGB_NB_XSTATS;
1984
1985         } else {
1986                 uint64_t values_copy[IGB_NB_XSTATS];
1987
1988                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1989                                 IGB_NB_XSTATS);
1990
1991                 for (i = 0; i < n; i++) {
1992                         if (ids[i] >= IGB_NB_XSTATS) {
1993                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1994                                 return -1;
1995                         }
1996                         values[i] = values_copy[ids[i]];
1997                 }
1998                 return n;
1999         }
2000 }
2001
2002 static void
2003 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2004 {
2005         /* Good Rx packets, include VF loopback */
2006         UPDATE_VF_STAT(E1000_VFGPRC,
2007             hw_stats->last_gprc, hw_stats->gprc);
2008
2009         /* Good Rx octets, include VF loopback */
2010         UPDATE_VF_STAT(E1000_VFGORC,
2011             hw_stats->last_gorc, hw_stats->gorc);
2012
2013         /* Good Tx packets, include VF loopback */
2014         UPDATE_VF_STAT(E1000_VFGPTC,
2015             hw_stats->last_gptc, hw_stats->gptc);
2016
2017         /* Good Tx octets, include VF loopback */
2018         UPDATE_VF_STAT(E1000_VFGOTC,
2019             hw_stats->last_gotc, hw_stats->gotc);
2020
2021         /* Rx Multicst packets */
2022         UPDATE_VF_STAT(E1000_VFMPRC,
2023             hw_stats->last_mprc, hw_stats->mprc);
2024
2025         /* Good Rx loopback packets */
2026         UPDATE_VF_STAT(E1000_VFGPRLBC,
2027             hw_stats->last_gprlbc, hw_stats->gprlbc);
2028
2029         /* Good Rx loopback octets */
2030         UPDATE_VF_STAT(E1000_VFGORLBC,
2031             hw_stats->last_gorlbc, hw_stats->gorlbc);
2032
2033         /* Good Tx loopback packets */
2034         UPDATE_VF_STAT(E1000_VFGPTLBC,
2035             hw_stats->last_gptlbc, hw_stats->gptlbc);
2036
2037         /* Good Tx loopback octets */
2038         UPDATE_VF_STAT(E1000_VFGOTLBC,
2039             hw_stats->last_gotlbc, hw_stats->gotlbc);
2040 }
2041
2042 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2043                                      struct rte_eth_xstat_name *xstats_names,
2044                                      __rte_unused unsigned limit)
2045 {
2046         unsigned i;
2047
2048         if (xstats_names != NULL)
2049                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2050                         strlcpy(xstats_names[i].name,
2051                                 rte_igbvf_stats_strings[i].name,
2052                                 sizeof(xstats_names[i].name));
2053                 }
2054         return IGBVF_NB_XSTATS;
2055 }
2056
2057 static int
2058 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2059                      unsigned n)
2060 {
2061         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2062         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2063                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2064         unsigned i;
2065
2066         if (n < IGBVF_NB_XSTATS)
2067                 return IGBVF_NB_XSTATS;
2068
2069         igbvf_read_stats_registers(hw, hw_stats);
2070
2071         if (!xstats)
2072                 return 0;
2073
2074         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2075                 xstats[i].id = i;
2076                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2077                         rte_igbvf_stats_strings[i].offset);
2078         }
2079
2080         return IGBVF_NB_XSTATS;
2081 }
2082
2083 static int
2084 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2085 {
2086         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2088                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2089
2090         igbvf_read_stats_registers(hw, hw_stats);
2091
2092         if (rte_stats == NULL)
2093                 return -EINVAL;
2094
2095         rte_stats->ipackets = hw_stats->gprc;
2096         rte_stats->ibytes = hw_stats->gorc;
2097         rte_stats->opackets = hw_stats->gptc;
2098         rte_stats->obytes = hw_stats->gotc;
2099         return 0;
2100 }
2101
2102 static int
2103 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2104 {
2105         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2106                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2107
2108         /* Sync HW register to the last stats */
2109         eth_igbvf_stats_get(dev, NULL);
2110
2111         /* reset HW current stats*/
2112         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2113                offsetof(struct e1000_vf_stats, gprc));
2114
2115         return 0;
2116 }
2117
2118 static int
2119 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2120                        size_t fw_size)
2121 {
2122         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2123         struct e1000_fw_version fw;
2124         int ret;
2125
2126         e1000_get_fw_version(hw, &fw);
2127
2128         switch (hw->mac.type) {
2129         case e1000_i210:
2130         case e1000_i211:
2131                 if (!(e1000_get_flash_presence_i210(hw))) {
2132                         ret = snprintf(fw_version, fw_size,
2133                                  "%2d.%2d-%d",
2134                                  fw.invm_major, fw.invm_minor,
2135                                  fw.invm_img_type);
2136                         break;
2137                 }
2138                 /* fall through */
2139         default:
2140                 /* if option rom is valid, display its version too */
2141                 if (fw.or_valid) {
2142                         ret = snprintf(fw_version, fw_size,
2143                                  "%d.%d, 0x%08x, %d.%d.%d",
2144                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2145                                  fw.or_major, fw.or_build, fw.or_patch);
2146                 /* no option rom */
2147                 } else {
2148                         if (fw.etrack_id != 0X0000) {
2149                                 ret = snprintf(fw_version, fw_size,
2150                                          "%d.%d, 0x%08x",
2151                                          fw.eep_major, fw.eep_minor,
2152                                          fw.etrack_id);
2153                         } else {
2154                                 ret = snprintf(fw_version, fw_size,
2155                                          "%d.%d.%d",
2156                                          fw.eep_major, fw.eep_minor,
2157                                          fw.eep_build);
2158                         }
2159                 }
2160                 break;
2161         }
2162
2163         ret += 1; /* add the size of '\0' */
2164         if (fw_size < (u32)ret)
2165                 return ret;
2166         else
2167                 return 0;
2168 }
2169
2170 static int
2171 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2172 {
2173         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2174
2175         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2176         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2177         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2178         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2179         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2180                                     dev_info->rx_queue_offload_capa;
2181         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2182         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2183                                     dev_info->tx_queue_offload_capa;
2184
2185         switch (hw->mac.type) {
2186         case e1000_82575:
2187                 dev_info->max_rx_queues = 4;
2188                 dev_info->max_tx_queues = 4;
2189                 dev_info->max_vmdq_pools = 0;
2190                 break;
2191
2192         case e1000_82576:
2193                 dev_info->max_rx_queues = 16;
2194                 dev_info->max_tx_queues = 16;
2195                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2196                 dev_info->vmdq_queue_num = 16;
2197                 break;
2198
2199         case e1000_82580:
2200                 dev_info->max_rx_queues = 8;
2201                 dev_info->max_tx_queues = 8;
2202                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2203                 dev_info->vmdq_queue_num = 8;
2204                 break;
2205
2206         case e1000_i350:
2207                 dev_info->max_rx_queues = 8;
2208                 dev_info->max_tx_queues = 8;
2209                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2210                 dev_info->vmdq_queue_num = 8;
2211                 break;
2212
2213         case e1000_i354:
2214                 dev_info->max_rx_queues = 8;
2215                 dev_info->max_tx_queues = 8;
2216                 break;
2217
2218         case e1000_i210:
2219                 dev_info->max_rx_queues = 4;
2220                 dev_info->max_tx_queues = 4;
2221                 dev_info->max_vmdq_pools = 0;
2222                 break;
2223
2224         case e1000_i211:
2225                 dev_info->max_rx_queues = 2;
2226                 dev_info->max_tx_queues = 2;
2227                 dev_info->max_vmdq_pools = 0;
2228                 break;
2229
2230         default:
2231                 /* Should not happen */
2232                 return -EINVAL;
2233         }
2234         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2235         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2236         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2237
2238         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2239                 .rx_thresh = {
2240                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2241                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2242                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2243                 },
2244                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2245                 .rx_drop_en = 0,
2246                 .offloads = 0,
2247         };
2248
2249         dev_info->default_txconf = (struct rte_eth_txconf) {
2250                 .tx_thresh = {
2251                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2252                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2253                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2254                 },
2255                 .offloads = 0,
2256         };
2257
2258         dev_info->rx_desc_lim = rx_desc_lim;
2259         dev_info->tx_desc_lim = tx_desc_lim;
2260
2261         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2262                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2263                         ETH_LINK_SPEED_1G;
2264
2265         dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2266         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2267
2268         return 0;
2269 }
2270
2271 static const uint32_t *
2272 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2273 {
2274         static const uint32_t ptypes[] = {
2275                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2276                 RTE_PTYPE_L2_ETHER,
2277                 RTE_PTYPE_L3_IPV4,
2278                 RTE_PTYPE_L3_IPV4_EXT,
2279                 RTE_PTYPE_L3_IPV6,
2280                 RTE_PTYPE_L3_IPV6_EXT,
2281                 RTE_PTYPE_L4_TCP,
2282                 RTE_PTYPE_L4_UDP,
2283                 RTE_PTYPE_L4_SCTP,
2284                 RTE_PTYPE_TUNNEL_IP,
2285                 RTE_PTYPE_INNER_L3_IPV6,
2286                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2287                 RTE_PTYPE_INNER_L4_TCP,
2288                 RTE_PTYPE_INNER_L4_UDP,
2289                 RTE_PTYPE_UNKNOWN
2290         };
2291
2292         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2293             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2294                 return ptypes;
2295         return NULL;
2296 }
2297
2298 static int
2299 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2300 {
2301         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2302
2303         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2304         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2305         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2306         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2307                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2308                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2309                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2310                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2311                                 DEV_TX_OFFLOAD_TCP_TSO;
2312         switch (hw->mac.type) {
2313         case e1000_vfadapt:
2314                 dev_info->max_rx_queues = 2;
2315                 dev_info->max_tx_queues = 2;
2316                 break;
2317         case e1000_vfadapt_i350:
2318                 dev_info->max_rx_queues = 1;
2319                 dev_info->max_tx_queues = 1;
2320                 break;
2321         default:
2322                 /* Should not happen */
2323                 return -EINVAL;
2324         }
2325
2326         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2327         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2328                                     dev_info->rx_queue_offload_capa;
2329         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2330         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2331                                     dev_info->tx_queue_offload_capa;
2332
2333         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2334                 .rx_thresh = {
2335                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2336                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2337                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2338                 },
2339                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2340                 .rx_drop_en = 0,
2341                 .offloads = 0,
2342         };
2343
2344         dev_info->default_txconf = (struct rte_eth_txconf) {
2345                 .tx_thresh = {
2346                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2347                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2348                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2349                 },
2350                 .offloads = 0,
2351         };
2352
2353         dev_info->rx_desc_lim = rx_desc_lim;
2354         dev_info->tx_desc_lim = tx_desc_lim;
2355
2356         return 0;
2357 }
2358
2359 /* return 0 means link status changed, -1 means not changed */
2360 static int
2361 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2362 {
2363         struct e1000_hw *hw =
2364                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2365         struct rte_eth_link link;
2366         int link_check, count;
2367
2368         link_check = 0;
2369         hw->mac.get_link_status = 1;
2370
2371         /* possible wait-to-complete in up to 9 seconds */
2372         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2373                 /* Read the real link status */
2374                 switch (hw->phy.media_type) {
2375                 case e1000_media_type_copper:
2376                         /* Do the work to read phy */
2377                         e1000_check_for_link(hw);
2378                         link_check = !hw->mac.get_link_status;
2379                         break;
2380
2381                 case e1000_media_type_fiber:
2382                         e1000_check_for_link(hw);
2383                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2384                                       E1000_STATUS_LU);
2385                         break;
2386
2387                 case e1000_media_type_internal_serdes:
2388                         e1000_check_for_link(hw);
2389                         link_check = hw->mac.serdes_has_link;
2390                         break;
2391
2392                 /* VF device is type_unknown */
2393                 case e1000_media_type_unknown:
2394                         eth_igbvf_link_update(hw);
2395                         link_check = !hw->mac.get_link_status;
2396                         break;
2397
2398                 default:
2399                         break;
2400                 }
2401                 if (link_check || wait_to_complete == 0)
2402                         break;
2403                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2404         }
2405         memset(&link, 0, sizeof(link));
2406
2407         /* Now we check if a transition has happened */
2408         if (link_check) {
2409                 uint16_t duplex, speed;
2410                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2411                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2412                                 ETH_LINK_FULL_DUPLEX :
2413                                 ETH_LINK_HALF_DUPLEX;
2414                 link.link_speed = speed;
2415                 link.link_status = ETH_LINK_UP;
2416                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2417                                 ETH_LINK_SPEED_FIXED);
2418         } else if (!link_check) {
2419                 link.link_speed = 0;
2420                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2421                 link.link_status = ETH_LINK_DOWN;
2422                 link.link_autoneg = ETH_LINK_FIXED;
2423         }
2424
2425         return rte_eth_linkstatus_set(dev, &link);
2426 }
2427
2428 /*
2429  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2430  * For ASF and Pass Through versions of f/w this means
2431  * that the driver is loaded.
2432  */
2433 static void
2434 igb_hw_control_acquire(struct e1000_hw *hw)
2435 {
2436         uint32_t ctrl_ext;
2437
2438         /* Let firmware know the driver has taken over */
2439         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2440         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2441 }
2442
2443 /*
2444  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2445  * For ASF and Pass Through versions of f/w this means that the
2446  * driver is no longer loaded.
2447  */
2448 static void
2449 igb_hw_control_release(struct e1000_hw *hw)
2450 {
2451         uint32_t ctrl_ext;
2452
2453         /* Let firmware taken over control of h/w */
2454         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2455         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2456                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2457 }
2458
2459 /*
2460  * Bit of a misnomer, what this really means is
2461  * to enable OS management of the system... aka
2462  * to disable special hardware management features.
2463  */
2464 static void
2465 igb_init_manageability(struct e1000_hw *hw)
2466 {
2467         if (e1000_enable_mng_pass_thru(hw)) {
2468                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2469                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2470
2471                 /* disable hardware interception of ARP */
2472                 manc &= ~(E1000_MANC_ARP_EN);
2473
2474                 /* enable receiving management packets to the host */
2475                 manc |= E1000_MANC_EN_MNG2HOST;
2476                 manc2h |= 1 << 5;  /* Mng Port 623 */
2477                 manc2h |= 1 << 6;  /* Mng Port 664 */
2478                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2479                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2480         }
2481 }
2482
2483 static void
2484 igb_release_manageability(struct e1000_hw *hw)
2485 {
2486         if (e1000_enable_mng_pass_thru(hw)) {
2487                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2488
2489                 manc |= E1000_MANC_ARP_EN;
2490                 manc &= ~E1000_MANC_EN_MNG2HOST;
2491
2492                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2493         }
2494 }
2495
2496 static int
2497 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2498 {
2499         struct e1000_hw *hw =
2500                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2501         uint32_t rctl;
2502
2503         rctl = E1000_READ_REG(hw, E1000_RCTL);
2504         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2505         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2506
2507         return 0;
2508 }
2509
2510 static int
2511 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2512 {
2513         struct e1000_hw *hw =
2514                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2515         uint32_t rctl;
2516
2517         rctl = E1000_READ_REG(hw, E1000_RCTL);
2518         rctl &= (~E1000_RCTL_UPE);
2519         if (dev->data->all_multicast == 1)
2520                 rctl |= E1000_RCTL_MPE;
2521         else
2522                 rctl &= (~E1000_RCTL_MPE);
2523         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2524
2525         return 0;
2526 }
2527
2528 static int
2529 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2530 {
2531         struct e1000_hw *hw =
2532                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2533         uint32_t rctl;
2534
2535         rctl = E1000_READ_REG(hw, E1000_RCTL);
2536         rctl |= E1000_RCTL_MPE;
2537         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2538
2539         return 0;
2540 }
2541
2542 static int
2543 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2544 {
2545         struct e1000_hw *hw =
2546                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2547         uint32_t rctl;
2548
2549         if (dev->data->promiscuous == 1)
2550                 return 0; /* must remain in all_multicast mode */
2551         rctl = E1000_READ_REG(hw, E1000_RCTL);
2552         rctl &= (~E1000_RCTL_MPE);
2553         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2554
2555         return 0;
2556 }
2557
2558 static int
2559 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2560 {
2561         struct e1000_hw *hw =
2562                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2563         struct e1000_vfta * shadow_vfta =
2564                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2565         uint32_t vfta;
2566         uint32_t vid_idx;
2567         uint32_t vid_bit;
2568
2569         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2570                               E1000_VFTA_ENTRY_MASK);
2571         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2572         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2573         if (on)
2574                 vfta |= vid_bit;
2575         else
2576                 vfta &= ~vid_bit;
2577         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2578
2579         /* update local VFTA copy */
2580         shadow_vfta->vfta[vid_idx] = vfta;
2581
2582         return 0;
2583 }
2584
2585 static int
2586 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2587                       enum rte_vlan_type vlan_type,
2588                       uint16_t tpid)
2589 {
2590         struct e1000_hw *hw =
2591                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2592         uint32_t reg, qinq;
2593
2594         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2595         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2596
2597         /* only outer TPID of double VLAN can be configured*/
2598         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2599                 reg = E1000_READ_REG(hw, E1000_VET);
2600                 reg = (reg & (~E1000_VET_VET_EXT)) |
2601                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2602                 E1000_WRITE_REG(hw, E1000_VET, reg);
2603
2604                 return 0;
2605         }
2606
2607         /* all other TPID values are read-only*/
2608         PMD_DRV_LOG(ERR, "Not supported");
2609
2610         return -ENOTSUP;
2611 }
2612
2613 static void
2614 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2615 {
2616         struct e1000_hw *hw =
2617                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2618         uint32_t reg;
2619
2620         /* Filter Table Disable */
2621         reg = E1000_READ_REG(hw, E1000_RCTL);
2622         reg &= ~E1000_RCTL_CFIEN;
2623         reg &= ~E1000_RCTL_VFE;
2624         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2625 }
2626
2627 static void
2628 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2629 {
2630         struct e1000_hw *hw =
2631                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2632         struct e1000_vfta * shadow_vfta =
2633                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2634         uint32_t reg;
2635         int i;
2636
2637         /* Filter Table Enable, CFI not used for packet acceptance */
2638         reg = E1000_READ_REG(hw, E1000_RCTL);
2639         reg &= ~E1000_RCTL_CFIEN;
2640         reg |= E1000_RCTL_VFE;
2641         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2642
2643         /* restore VFTA table */
2644         for (i = 0; i < IGB_VFTA_SIZE; i++)
2645                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2646 }
2647
2648 static void
2649 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2650 {
2651         struct e1000_hw *hw =
2652                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2653         uint32_t reg;
2654
2655         /* VLAN Mode Disable */
2656         reg = E1000_READ_REG(hw, E1000_CTRL);
2657         reg &= ~E1000_CTRL_VME;
2658         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2659 }
2660
2661 static void
2662 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2663 {
2664         struct e1000_hw *hw =
2665                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2666         uint32_t reg;
2667
2668         /* VLAN Mode Enable */
2669         reg = E1000_READ_REG(hw, E1000_CTRL);
2670         reg |= E1000_CTRL_VME;
2671         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2672 }
2673
2674 static void
2675 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2676 {
2677         struct e1000_hw *hw =
2678                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2679         uint32_t reg;
2680
2681         /* CTRL_EXT: Extended VLAN */
2682         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2683         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2684         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2685
2686         /* Update maximum packet length */
2687         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2688                 E1000_WRITE_REG(hw, E1000_RLPML,
2689                                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
2690 }
2691
2692 static void
2693 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2694 {
2695         struct e1000_hw *hw =
2696                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2697         uint32_t reg;
2698
2699         /* CTRL_EXT: Extended VLAN */
2700         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2701         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2702         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2703
2704         /* Update maximum packet length */
2705         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2706                 E1000_WRITE_REG(hw, E1000_RLPML,
2707                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2708                                                 VLAN_TAG_SIZE);
2709 }
2710
2711 static int
2712 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2713 {
2714         struct rte_eth_rxmode *rxmode;
2715
2716         rxmode = &dev->data->dev_conf.rxmode;
2717         if(mask & ETH_VLAN_STRIP_MASK){
2718                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2719                         igb_vlan_hw_strip_enable(dev);
2720                 else
2721                         igb_vlan_hw_strip_disable(dev);
2722         }
2723
2724         if(mask & ETH_VLAN_FILTER_MASK){
2725                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2726                         igb_vlan_hw_filter_enable(dev);
2727                 else
2728                         igb_vlan_hw_filter_disable(dev);
2729         }
2730
2731         if(mask & ETH_VLAN_EXTEND_MASK){
2732                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2733                         igb_vlan_hw_extend_enable(dev);
2734                 else
2735                         igb_vlan_hw_extend_disable(dev);
2736         }
2737
2738         return 0;
2739 }
2740
2741
2742 /**
2743  * It enables the interrupt mask and then enable the interrupt.
2744  *
2745  * @param dev
2746  *  Pointer to struct rte_eth_dev.
2747  * @param on
2748  *  Enable or Disable
2749  *
2750  * @return
2751  *  - On success, zero.
2752  *  - On failure, a negative value.
2753  */
2754 static int
2755 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2756 {
2757         struct e1000_interrupt *intr =
2758                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2759
2760         if (on)
2761                 intr->mask |= E1000_ICR_LSC;
2762         else
2763                 intr->mask &= ~E1000_ICR_LSC;
2764
2765         return 0;
2766 }
2767
2768 /* It clears the interrupt causes and enables the interrupt.
2769  * It will be called once only during nic initialized.
2770  *
2771  * @param dev
2772  *  Pointer to struct rte_eth_dev.
2773  *
2774  * @return
2775  *  - On success, zero.
2776  *  - On failure, a negative value.
2777  */
2778 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2779 {
2780         uint32_t mask, regval;
2781         int ret;
2782         struct e1000_hw *hw =
2783                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2785         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2786         int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2787         struct rte_eth_dev_info dev_info;
2788
2789         memset(&dev_info, 0, sizeof(dev_info));
2790         ret = eth_igb_infos_get(dev, &dev_info);
2791         if (ret != 0)
2792                 return ret;
2793
2794         mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2795         regval = E1000_READ_REG(hw, E1000_EIMS);
2796         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2797
2798         return 0;
2799 }
2800
2801 /*
2802  * It reads ICR and gets interrupt causes, check it and set a bit flag
2803  * to update link status.
2804  *
2805  * @param dev
2806  *  Pointer to struct rte_eth_dev.
2807  *
2808  * @return
2809  *  - On success, zero.
2810  *  - On failure, a negative value.
2811  */
2812 static int
2813 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2814 {
2815         uint32_t icr;
2816         struct e1000_hw *hw =
2817                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2818         struct e1000_interrupt *intr =
2819                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2820
2821         igb_intr_disable(dev);
2822
2823         /* read-on-clear nic registers here */
2824         icr = E1000_READ_REG(hw, E1000_ICR);
2825
2826         intr->flags = 0;
2827         if (icr & E1000_ICR_LSC) {
2828                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2829         }
2830
2831         if (icr & E1000_ICR_VMMB)
2832                 intr->flags |= E1000_FLAG_MAILBOX;
2833
2834         return 0;
2835 }
2836
2837 /*
2838  * It executes link_update after knowing an interrupt is prsent.
2839  *
2840  * @param dev
2841  *  Pointer to struct rte_eth_dev.
2842  *
2843  * @return
2844  *  - On success, zero.
2845  *  - On failure, a negative value.
2846  */
2847 static int
2848 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2849                          struct rte_intr_handle *intr_handle)
2850 {
2851         struct e1000_hw *hw =
2852                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2853         struct e1000_interrupt *intr =
2854                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2855         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2856         struct rte_eth_link link;
2857         int ret;
2858
2859         if (intr->flags & E1000_FLAG_MAILBOX) {
2860                 igb_pf_mbx_process(dev);
2861                 intr->flags &= ~E1000_FLAG_MAILBOX;
2862         }
2863
2864         igb_intr_enable(dev);
2865         rte_intr_ack(intr_handle);
2866
2867         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2868                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2869
2870                 /* set get_link_status to check register later */
2871                 hw->mac.get_link_status = 1;
2872                 ret = eth_igb_link_update(dev, 0);
2873
2874                 /* check if link has changed */
2875                 if (ret < 0)
2876                         return 0;
2877
2878                 rte_eth_linkstatus_get(dev, &link);
2879                 if (link.link_status) {
2880                         PMD_INIT_LOG(INFO,
2881                                      " Port %d: Link Up - speed %u Mbps - %s",
2882                                      dev->data->port_id,
2883                                      (unsigned)link.link_speed,
2884                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2885                                      "full-duplex" : "half-duplex");
2886                 } else {
2887                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2888                                      dev->data->port_id);
2889                 }
2890
2891                 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2892                              pci_dev->addr.domain,
2893                              pci_dev->addr.bus,
2894                              pci_dev->addr.devid,
2895                              pci_dev->addr.function);
2896                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2897         }
2898
2899         return 0;
2900 }
2901
2902 /**
2903  * Interrupt handler which shall be registered at first.
2904  *
2905  * @param handle
2906  *  Pointer to interrupt handle.
2907  * @param param
2908  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2909  *
2910  * @return
2911  *  void
2912  */
2913 static void
2914 eth_igb_interrupt_handler(void *param)
2915 {
2916         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2917
2918         eth_igb_interrupt_get_status(dev);
2919         eth_igb_interrupt_action(dev, dev->intr_handle);
2920 }
2921
2922 static int
2923 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2924 {
2925         uint32_t eicr;
2926         struct e1000_hw *hw =
2927                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2928         struct e1000_interrupt *intr =
2929                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2930
2931         igbvf_intr_disable(hw);
2932
2933         /* read-on-clear nic registers here */
2934         eicr = E1000_READ_REG(hw, E1000_EICR);
2935         intr->flags = 0;
2936
2937         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2938                 intr->flags |= E1000_FLAG_MAILBOX;
2939
2940         return 0;
2941 }
2942
2943 void igbvf_mbx_process(struct rte_eth_dev *dev)
2944 {
2945         struct e1000_hw *hw =
2946                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2947         struct e1000_mbx_info *mbx = &hw->mbx;
2948         u32 in_msg = 0;
2949
2950         /* peek the message first */
2951         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2952
2953         /* PF reset VF event */
2954         if (in_msg == E1000_PF_CONTROL_MSG) {
2955                 /* dummy mbx read to ack pf */
2956                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2957                         return;
2958                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2959                                              NULL);
2960         }
2961 }
2962
2963 static int
2964 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2965 {
2966         struct e1000_interrupt *intr =
2967                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2968
2969         if (intr->flags & E1000_FLAG_MAILBOX) {
2970                 igbvf_mbx_process(dev);
2971                 intr->flags &= ~E1000_FLAG_MAILBOX;
2972         }
2973
2974         igbvf_intr_enable(dev);
2975         rte_intr_ack(intr_handle);
2976
2977         return 0;
2978 }
2979
2980 static void
2981 eth_igbvf_interrupt_handler(void *param)
2982 {
2983         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2984
2985         eth_igbvf_interrupt_get_status(dev);
2986         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2987 }
2988
2989 static int
2990 eth_igb_led_on(struct rte_eth_dev *dev)
2991 {
2992         struct e1000_hw *hw;
2993
2994         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2995         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2996 }
2997
2998 static int
2999 eth_igb_led_off(struct rte_eth_dev *dev)
3000 {
3001         struct e1000_hw *hw;
3002
3003         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3004         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3005 }
3006
3007 static int
3008 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3009 {
3010         struct e1000_hw *hw;
3011         uint32_t ctrl;
3012         int tx_pause;
3013         int rx_pause;
3014
3015         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3016         fc_conf->pause_time = hw->fc.pause_time;
3017         fc_conf->high_water = hw->fc.high_water;
3018         fc_conf->low_water = hw->fc.low_water;
3019         fc_conf->send_xon = hw->fc.send_xon;
3020         fc_conf->autoneg = hw->mac.autoneg;
3021
3022         /*
3023          * Return rx_pause and tx_pause status according to actual setting of
3024          * the TFCE and RFCE bits in the CTRL register.
3025          */
3026         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3027         if (ctrl & E1000_CTRL_TFCE)
3028                 tx_pause = 1;
3029         else
3030                 tx_pause = 0;
3031
3032         if (ctrl & E1000_CTRL_RFCE)
3033                 rx_pause = 1;
3034         else
3035                 rx_pause = 0;
3036
3037         if (rx_pause && tx_pause)
3038                 fc_conf->mode = RTE_FC_FULL;
3039         else if (rx_pause)
3040                 fc_conf->mode = RTE_FC_RX_PAUSE;
3041         else if (tx_pause)
3042                 fc_conf->mode = RTE_FC_TX_PAUSE;
3043         else
3044                 fc_conf->mode = RTE_FC_NONE;
3045
3046         return 0;
3047 }
3048
3049 static int
3050 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3051 {
3052         struct e1000_hw *hw;
3053         int err;
3054         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3055                 e1000_fc_none,
3056                 e1000_fc_rx_pause,
3057                 e1000_fc_tx_pause,
3058                 e1000_fc_full
3059         };
3060         uint32_t rx_buf_size;
3061         uint32_t max_high_water;
3062         uint32_t rctl;
3063         uint32_t ctrl;
3064
3065         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3066         if (fc_conf->autoneg != hw->mac.autoneg)
3067                 return -ENOTSUP;
3068         rx_buf_size = igb_get_rx_buffer_size(hw);
3069         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3070
3071         /* At least reserve one Ethernet frame for watermark */
3072         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3073         if ((fc_conf->high_water > max_high_water) ||
3074             (fc_conf->high_water < fc_conf->low_water)) {
3075                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3076                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3077                 return -EINVAL;
3078         }
3079
3080         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3081         hw->fc.pause_time     = fc_conf->pause_time;
3082         hw->fc.high_water     = fc_conf->high_water;
3083         hw->fc.low_water      = fc_conf->low_water;
3084         hw->fc.send_xon       = fc_conf->send_xon;
3085
3086         err = e1000_setup_link_generic(hw);
3087         if (err == E1000_SUCCESS) {
3088
3089                 /* check if we want to forward MAC frames - driver doesn't have native
3090                  * capability to do that, so we'll write the registers ourselves */
3091
3092                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3093
3094                 /* set or clear MFLCN.PMCF bit depending on configuration */
3095                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3096                         rctl |= E1000_RCTL_PMCF;
3097                 else
3098                         rctl &= ~E1000_RCTL_PMCF;
3099
3100                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3101
3102                 /*
3103                  * check if we want to change flow control mode - driver doesn't have native
3104                  * capability to do that, so we'll write the registers ourselves
3105                  */
3106                 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3107
3108                 /*
3109                  * set or clear E1000_CTRL_RFCE and E1000_CTRL_TFCE bits depending
3110                  * on configuration
3111                  */
3112                 switch (fc_conf->mode) {
3113                 case RTE_FC_NONE:
3114                         ctrl &= ~E1000_CTRL_RFCE & ~E1000_CTRL_TFCE;
3115                         break;
3116                 case RTE_FC_RX_PAUSE:
3117                         ctrl |= E1000_CTRL_RFCE;
3118                         ctrl &= ~E1000_CTRL_TFCE;
3119                         break;
3120                 case RTE_FC_TX_PAUSE:
3121                         ctrl |= E1000_CTRL_TFCE;
3122                         ctrl &= ~E1000_CTRL_RFCE;
3123                         break;
3124                 case RTE_FC_FULL:
3125                         ctrl |= E1000_CTRL_RFCE | E1000_CTRL_TFCE;
3126                         break;
3127                 default:
3128                         PMD_INIT_LOG(ERR, "invalid flow control mode");
3129                         return -EINVAL;
3130                 }
3131
3132                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
3133
3134                 E1000_WRITE_FLUSH(hw);
3135
3136                 return 0;
3137         }
3138
3139         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3140         return -EIO;
3141 }
3142
3143 #define E1000_RAH_POOLSEL_SHIFT      (18)
3144 static int
3145 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3146                 uint32_t index, uint32_t pool)
3147 {
3148         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3149         uint32_t rah;
3150
3151         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3152         rah = E1000_READ_REG(hw, E1000_RAH(index));
3153         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3154         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3155         return 0;
3156 }
3157
3158 static void
3159 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3160 {
3161         uint8_t addr[RTE_ETHER_ADDR_LEN];
3162         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3163
3164         memset(addr, 0, sizeof(addr));
3165
3166         e1000_rar_set(hw, addr, index);
3167 }
3168
3169 static int
3170 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3171                                 struct rte_ether_addr *addr)
3172 {
3173         eth_igb_rar_clear(dev, 0);
3174         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3175
3176         return 0;
3177 }
3178 /*
3179  * Virtual Function operations
3180  */
3181 static void
3182 igbvf_intr_disable(struct e1000_hw *hw)
3183 {
3184         PMD_INIT_FUNC_TRACE();
3185
3186         /* Clear interrupt mask to stop from interrupts being generated */
3187         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3188
3189         E1000_WRITE_FLUSH(hw);
3190 }
3191
3192 static void
3193 igbvf_stop_adapter(struct rte_eth_dev *dev)
3194 {
3195         u32 reg_val;
3196         u16 i;
3197         struct rte_eth_dev_info dev_info;
3198         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3199         int ret;
3200
3201         memset(&dev_info, 0, sizeof(dev_info));
3202         ret = eth_igbvf_infos_get(dev, &dev_info);
3203         if (ret != 0)
3204                 return;
3205
3206         /* Clear interrupt mask to stop from interrupts being generated */
3207         igbvf_intr_disable(hw);
3208
3209         /* Clear any pending interrupts, flush previous writes */
3210         E1000_READ_REG(hw, E1000_EICR);
3211
3212         /* Disable the transmit unit.  Each queue must be disabled. */
3213         for (i = 0; i < dev_info.max_tx_queues; i++)
3214                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3215
3216         /* Disable the receive unit by stopping each queue */
3217         for (i = 0; i < dev_info.max_rx_queues; i++) {
3218                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3219                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3220                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3221                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3222                         ;
3223         }
3224
3225         /* flush all queues disables */
3226         E1000_WRITE_FLUSH(hw);
3227         msec_delay(2);
3228 }
3229
3230 static int eth_igbvf_link_update(struct e1000_hw *hw)
3231 {
3232         struct e1000_mbx_info *mbx = &hw->mbx;
3233         struct e1000_mac_info *mac = &hw->mac;
3234         int ret_val = E1000_SUCCESS;
3235
3236         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3237
3238         /*
3239          * We only want to run this if there has been a rst asserted.
3240          * in this case that could mean a link change, device reset,
3241          * or a virtual function reset
3242          */
3243
3244         /* If we were hit with a reset or timeout drop the link */
3245         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3246                 mac->get_link_status = TRUE;
3247
3248         if (!mac->get_link_status)
3249                 goto out;
3250
3251         /* if link status is down no point in checking to see if pf is up */
3252         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3253                 goto out;
3254
3255         /* if we passed all the tests above then the link is up and we no
3256          * longer need to check for link */
3257         mac->get_link_status = FALSE;
3258
3259 out:
3260         return ret_val;
3261 }
3262
3263
3264 static int
3265 igbvf_dev_configure(struct rte_eth_dev *dev)
3266 {
3267         struct rte_eth_conf* conf = &dev->data->dev_conf;
3268
3269         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3270                      dev->data->port_id);
3271
3272         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3273                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3274
3275         /*
3276          * VF has no ability to enable/disable HW CRC
3277          * Keep the persistent behavior the same as Host PF
3278          */
3279 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3280         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3281                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3282                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3283         }
3284 #else
3285         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3286                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3287                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3288         }
3289 #endif
3290
3291         return 0;
3292 }
3293
3294 static int
3295 igbvf_dev_start(struct rte_eth_dev *dev)
3296 {
3297         struct e1000_hw *hw =
3298                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3299         struct e1000_adapter *adapter =
3300                 E1000_DEV_PRIVATE(dev->data->dev_private);
3301         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3302         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3303         int ret;
3304         uint32_t intr_vector = 0;
3305
3306         PMD_INIT_FUNC_TRACE();
3307
3308         hw->mac.ops.reset_hw(hw);
3309         adapter->stopped = 0;
3310
3311         /* Set all vfta */
3312         igbvf_set_vfta_all(dev,1);
3313
3314         eth_igbvf_tx_init(dev);
3315
3316         /* This can fail when allocating mbufs for descriptor rings */
3317         ret = eth_igbvf_rx_init(dev);
3318         if (ret) {
3319                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3320                 igb_dev_clear_queues(dev);
3321                 return ret;
3322         }
3323
3324         /* check and configure queue intr-vector mapping */
3325         if (rte_intr_cap_multiple(intr_handle) &&
3326             dev->data->dev_conf.intr_conf.rxq) {
3327                 intr_vector = dev->data->nb_rx_queues;
3328                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3329                 if (ret)
3330                         return ret;
3331         }
3332
3333         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3334                 intr_handle->intr_vec =
3335                         rte_zmalloc("intr_vec",
3336                                     dev->data->nb_rx_queues * sizeof(int), 0);
3337                 if (!intr_handle->intr_vec) {
3338                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3339                                      " intr_vec", dev->data->nb_rx_queues);
3340                         return -ENOMEM;
3341                 }
3342         }
3343
3344         eth_igbvf_configure_msix_intr(dev);
3345
3346         /* enable uio/vfio intr/eventfd mapping */
3347         rte_intr_enable(intr_handle);
3348
3349         /* resume enabled intr since hw reset */
3350         igbvf_intr_enable(dev);
3351
3352         return 0;
3353 }
3354
3355 static int
3356 igbvf_dev_stop(struct rte_eth_dev *dev)
3357 {
3358         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3359         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3360         struct e1000_adapter *adapter =
3361                 E1000_DEV_PRIVATE(dev->data->dev_private);
3362
3363         if (adapter->stopped)
3364                 return 0;
3365
3366         PMD_INIT_FUNC_TRACE();
3367
3368         igbvf_stop_adapter(dev);
3369
3370         /*
3371           * Clear what we set, but we still keep shadow_vfta to
3372           * restore after device starts
3373           */
3374         igbvf_set_vfta_all(dev,0);
3375
3376         igb_dev_clear_queues(dev);
3377
3378         /* disable intr eventfd mapping */
3379         rte_intr_disable(intr_handle);
3380
3381         /* Clean datapath event and queue/vec mapping */
3382         rte_intr_efd_disable(intr_handle);
3383         if (intr_handle->intr_vec) {
3384                 rte_free(intr_handle->intr_vec);
3385                 intr_handle->intr_vec = NULL;
3386         }
3387
3388         adapter->stopped = true;
3389         dev->data->dev_started = 0;
3390
3391         return 0;
3392 }
3393
3394 static int
3395 igbvf_dev_close(struct rte_eth_dev *dev)
3396 {
3397         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3398         struct rte_ether_addr addr;
3399         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3400         int ret;
3401
3402         PMD_INIT_FUNC_TRACE();
3403
3404         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3405                 return 0;
3406
3407         e1000_reset_hw(hw);
3408
3409         ret = igbvf_dev_stop(dev);
3410         if (ret != 0)
3411                 return ret;
3412
3413         igb_dev_free_queues(dev);
3414
3415         /**
3416          * reprogram the RAR with a zero mac address,
3417          * to ensure that the VF traffic goes to the PF
3418          * after stop, close and detach of the VF.
3419          **/
3420
3421         memset(&addr, 0, sizeof(addr));
3422         igbvf_default_mac_addr_set(dev, &addr);
3423
3424         rte_intr_callback_unregister(&pci_dev->intr_handle,
3425                                      eth_igbvf_interrupt_handler,
3426                                      (void *)dev);
3427
3428         return 0;
3429 }
3430
3431 static int
3432 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3433 {
3434         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3435
3436         /* Set both unicast and multicast promisc */
3437         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3438
3439         return 0;
3440 }
3441
3442 static int
3443 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3444 {
3445         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3446
3447         /* If in allmulticast mode leave multicast promisc */
3448         if (dev->data->all_multicast == 1)
3449                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3450         else
3451                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3452
3453         return 0;
3454 }
3455
3456 static int
3457 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3458 {
3459         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3460
3461         /* In promiscuous mode multicast promisc already set */
3462         if (dev->data->promiscuous == 0)
3463                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3464
3465         return 0;
3466 }
3467
3468 static int
3469 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3470 {
3471         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3472
3473         /* In promiscuous mode leave multicast promisc enabled */
3474         if (dev->data->promiscuous == 0)
3475                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3476
3477         return 0;
3478 }
3479
3480 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3481 {
3482         struct e1000_mbx_info *mbx = &hw->mbx;
3483         uint32_t msgbuf[2];
3484         s32 err;
3485
3486         /* After set vlan, vlan strip will also be enabled in igb driver*/
3487         msgbuf[0] = E1000_VF_SET_VLAN;
3488         msgbuf[1] = vid;
3489         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3490         if (on)
3491                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3492
3493         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3494         if (err)
3495                 goto mbx_err;
3496
3497         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3498         if (err)
3499                 goto mbx_err;
3500
3501         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3502         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3503                 err = -EINVAL;
3504
3505 mbx_err:
3506         return err;
3507 }
3508
3509 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3510 {
3511         struct e1000_hw *hw =
3512                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3513         struct e1000_vfta * shadow_vfta =
3514                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3515         int i = 0, j = 0, vfta = 0, mask = 1;
3516
3517         for (i = 0; i < IGB_VFTA_SIZE; i++){
3518                 vfta = shadow_vfta->vfta[i];
3519                 if(vfta){
3520                         mask = 1;
3521                         for (j = 0; j < 32; j++){
3522                                 if(vfta & mask)
3523                                         igbvf_set_vfta(hw,
3524                                                 (uint16_t)((i<<5)+j), on);
3525                                 mask<<=1;
3526                         }
3527                 }
3528         }
3529
3530 }
3531
3532 static int
3533 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3534 {
3535         struct e1000_hw *hw =
3536                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3537         struct e1000_vfta * shadow_vfta =
3538                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3539         uint32_t vid_idx = 0;
3540         uint32_t vid_bit = 0;
3541         int ret = 0;
3542
3543         PMD_INIT_FUNC_TRACE();
3544
3545         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3546         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3547         if(ret){
3548                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3549                 return ret;
3550         }
3551         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3552         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3553
3554         /*Save what we set and retore it after device reset*/
3555         if (on)
3556                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3557         else
3558                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3559
3560         return 0;
3561 }
3562
3563 static int
3564 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3565 {
3566         struct e1000_hw *hw =
3567                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3568
3569         /* index is not used by rar_set() */
3570         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3571         return 0;
3572 }
3573
3574
3575 static int
3576 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3577                         struct rte_eth_rss_reta_entry64 *reta_conf,
3578                         uint16_t reta_size)
3579 {
3580         uint8_t i, j, mask;
3581         uint32_t reta, r;
3582         uint16_t idx, shift;
3583         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3584
3585         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3586                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3587                         "(%d) doesn't match the number hardware can supported "
3588                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3589                 return -EINVAL;
3590         }
3591
3592         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3593                 idx = i / RTE_RETA_GROUP_SIZE;
3594                 shift = i % RTE_RETA_GROUP_SIZE;
3595                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3596                                                 IGB_4_BIT_MASK);
3597                 if (!mask)
3598                         continue;
3599                 if (mask == IGB_4_BIT_MASK)
3600                         r = 0;
3601                 else
3602                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3603                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3604                         if (mask & (0x1 << j))
3605                                 reta |= reta_conf[idx].reta[shift + j] <<
3606                                                         (CHAR_BIT * j);
3607                         else
3608                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3609                 }
3610                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3611         }
3612
3613         return 0;
3614 }
3615
3616 static int
3617 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3618                        struct rte_eth_rss_reta_entry64 *reta_conf,
3619                        uint16_t reta_size)
3620 {
3621         uint8_t i, j, mask;
3622         uint32_t reta;
3623         uint16_t idx, shift;
3624         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3625
3626         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3627                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3628                         "(%d) doesn't match the number hardware can supported "
3629                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3630                 return -EINVAL;
3631         }
3632
3633         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3634                 idx = i / RTE_RETA_GROUP_SIZE;
3635                 shift = i % RTE_RETA_GROUP_SIZE;
3636                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3637                                                 IGB_4_BIT_MASK);
3638                 if (!mask)
3639                         continue;
3640                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3641                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3642                         if (mask & (0x1 << j))
3643                                 reta_conf[idx].reta[shift + j] =
3644                                         ((reta >> (CHAR_BIT * j)) &
3645                                                 IGB_8_BIT_MASK);
3646                 }
3647         }
3648
3649         return 0;
3650 }
3651
3652 int
3653 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3654                         struct rte_eth_syn_filter *filter,
3655                         bool add)
3656 {
3657         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3658         struct e1000_filter_info *filter_info =
3659                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3660         uint32_t synqf, rfctl;
3661
3662         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3663                 return -EINVAL;
3664
3665         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3666
3667         if (add) {
3668                 if (synqf & E1000_SYN_FILTER_ENABLE)
3669                         return -EINVAL;
3670
3671                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3672                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3673
3674                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3675                 if (filter->hig_pri)
3676                         rfctl |= E1000_RFCTL_SYNQFP;
3677                 else
3678                         rfctl &= ~E1000_RFCTL_SYNQFP;
3679
3680                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3681         } else {
3682                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3683                         return -ENOENT;
3684                 synqf = 0;
3685         }
3686
3687         filter_info->syn_info = synqf;
3688         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3689         E1000_WRITE_FLUSH(hw);
3690         return 0;
3691 }
3692
3693 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3694 static inline int
3695 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3696                         struct e1000_2tuple_filter_info *filter_info)
3697 {
3698         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3699                 return -EINVAL;
3700         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3701                 return -EINVAL;  /* filter index is out of range. */
3702         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3703                 return -EINVAL;  /* flags is invalid. */
3704
3705         switch (filter->dst_port_mask) {
3706         case UINT16_MAX:
3707                 filter_info->dst_port_mask = 0;
3708                 filter_info->dst_port = filter->dst_port;
3709                 break;
3710         case 0:
3711                 filter_info->dst_port_mask = 1;
3712                 break;
3713         default:
3714                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3715                 return -EINVAL;
3716         }
3717
3718         switch (filter->proto_mask) {
3719         case UINT8_MAX:
3720                 filter_info->proto_mask = 0;
3721                 filter_info->proto = filter->proto;
3722                 break;
3723         case 0:
3724                 filter_info->proto_mask = 1;
3725                 break;
3726         default:
3727                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3728                 return -EINVAL;
3729         }
3730
3731         filter_info->priority = (uint8_t)filter->priority;
3732         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3733                 filter_info->tcp_flags = filter->tcp_flags;
3734         else
3735                 filter_info->tcp_flags = 0;
3736
3737         return 0;
3738 }
3739
3740 static inline struct e1000_2tuple_filter *
3741 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3742                         struct e1000_2tuple_filter_info *key)
3743 {
3744         struct e1000_2tuple_filter *it;
3745
3746         TAILQ_FOREACH(it, filter_list, entries) {
3747                 if (memcmp(key, &it->filter_info,
3748                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3749                         return it;
3750                 }
3751         }
3752         return NULL;
3753 }
3754
3755 /* inject a igb 2tuple filter to HW */
3756 static inline void
3757 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3758                            struct e1000_2tuple_filter *filter)
3759 {
3760         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3761         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3762         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3763         int i;
3764
3765         i = filter->index;
3766         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3767         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3768                 imir |= E1000_IMIR_PORT_BP;
3769         else
3770                 imir &= ~E1000_IMIR_PORT_BP;
3771
3772         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3773
3774         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3775         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3776         ttqf |= (uint32_t)(filter->filter_info.proto &
3777                                                 E1000_TTQF_PROTOCOL_MASK);
3778         if (filter->filter_info.proto_mask == 0)
3779                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3780
3781         /* tcp flags bits setting. */
3782         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3783                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3784                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3785                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3786                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3787                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3788                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3789                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3790                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3791                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3792                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3793                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3794                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3795         } else {
3796                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3797         }
3798         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3799         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3800         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3801 }
3802
3803 /*
3804  * igb_add_2tuple_filter - add a 2tuple filter
3805  *
3806  * @param
3807  * dev: Pointer to struct rte_eth_dev.
3808  * ntuple_filter: ponter to the filter that will be added.
3809  *
3810  * @return
3811  *    - On success, zero.
3812  *    - On failure, a negative value.
3813  */
3814 static int
3815 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3816                         struct rte_eth_ntuple_filter *ntuple_filter)
3817 {
3818         struct e1000_filter_info *filter_info =
3819                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3820         struct e1000_2tuple_filter *filter;
3821         int i, ret;
3822
3823         filter = rte_zmalloc("e1000_2tuple_filter",
3824                         sizeof(struct e1000_2tuple_filter), 0);
3825         if (filter == NULL)
3826                 return -ENOMEM;
3827
3828         ret = ntuple_filter_to_2tuple(ntuple_filter,
3829                                       &filter->filter_info);
3830         if (ret < 0) {
3831                 rte_free(filter);
3832                 return ret;
3833         }
3834         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3835                                          &filter->filter_info) != NULL) {
3836                 PMD_DRV_LOG(ERR, "filter exists.");
3837                 rte_free(filter);
3838                 return -EEXIST;
3839         }
3840         filter->queue = ntuple_filter->queue;
3841
3842         /*
3843          * look for an unused 2tuple filter index,
3844          * and insert the filter to list.
3845          */
3846         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3847                 if (!(filter_info->twotuple_mask & (1 << i))) {
3848                         filter_info->twotuple_mask |= 1 << i;
3849                         filter->index = i;
3850                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3851                                           filter,
3852                                           entries);
3853                         break;
3854                 }
3855         }
3856         if (i >= E1000_MAX_TTQF_FILTERS) {
3857                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3858                 rte_free(filter);
3859                 return -ENOSYS;
3860         }
3861
3862         igb_inject_2uple_filter(dev, filter);
3863         return 0;
3864 }
3865
3866 int
3867 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3868                         struct e1000_2tuple_filter *filter)
3869 {
3870         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3871         struct e1000_filter_info *filter_info =
3872                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3873
3874         filter_info->twotuple_mask &= ~(1 << filter->index);
3875         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3876         rte_free(filter);
3877
3878         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3879         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3880         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3881         return 0;
3882 }
3883
3884 /*
3885  * igb_remove_2tuple_filter - remove a 2tuple filter
3886  *
3887  * @param
3888  * dev: Pointer to struct rte_eth_dev.
3889  * ntuple_filter: ponter to the filter that will be removed.
3890  *
3891  * @return
3892  *    - On success, zero.
3893  *    - On failure, a negative value.
3894  */
3895 static int
3896 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3897                         struct rte_eth_ntuple_filter *ntuple_filter)
3898 {
3899         struct e1000_filter_info *filter_info =
3900                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3901         struct e1000_2tuple_filter_info filter_2tuple;
3902         struct e1000_2tuple_filter *filter;
3903         int ret;
3904
3905         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3906         ret = ntuple_filter_to_2tuple(ntuple_filter,
3907                                       &filter_2tuple);
3908         if (ret < 0)
3909                 return ret;
3910
3911         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3912                                          &filter_2tuple);
3913         if (filter == NULL) {
3914                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3915                 return -ENOENT;
3916         }
3917
3918         igb_delete_2tuple_filter(dev, filter);
3919
3920         return 0;
3921 }
3922
3923 /* inject a igb flex filter to HW */
3924 static inline void
3925 igb_inject_flex_filter(struct rte_eth_dev *dev,
3926                            struct e1000_flex_filter *filter)
3927 {
3928         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3929         uint32_t wufc, queueing;
3930         uint32_t reg_off;
3931         uint8_t i, j = 0;
3932
3933         wufc = E1000_READ_REG(hw, E1000_WUFC);
3934         if (filter->index < E1000_MAX_FHFT)
3935                 reg_off = E1000_FHFT(filter->index);
3936         else
3937                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3938
3939         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3940                         (E1000_WUFC_FLX0 << filter->index));
3941         queueing = filter->filter_info.len |
3942                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3943                 (filter->filter_info.priority <<
3944                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3945         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3946                         queueing);
3947
3948         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3949                 E1000_WRITE_REG(hw, reg_off,
3950                                 filter->filter_info.dwords[j]);
3951                 reg_off += sizeof(uint32_t);
3952                 E1000_WRITE_REG(hw, reg_off,
3953                                 filter->filter_info.dwords[++j]);
3954                 reg_off += sizeof(uint32_t);
3955                 E1000_WRITE_REG(hw, reg_off,
3956                         (uint32_t)filter->filter_info.mask[i]);
3957                 reg_off += sizeof(uint32_t) * 2;
3958                 ++j;
3959         }
3960 }
3961
3962 static inline struct e1000_flex_filter *
3963 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3964                         struct e1000_flex_filter_info *key)
3965 {
3966         struct e1000_flex_filter *it;
3967
3968         TAILQ_FOREACH(it, filter_list, entries) {
3969                 if (memcmp(key, &it->filter_info,
3970                         sizeof(struct e1000_flex_filter_info)) == 0)
3971                         return it;
3972         }
3973
3974         return NULL;
3975 }
3976
3977 /* remove a flex byte filter
3978  * @param
3979  * dev: Pointer to struct rte_eth_dev.
3980  * filter: the pointer of the filter will be removed.
3981  */
3982 void
3983 igb_remove_flex_filter(struct rte_eth_dev *dev,
3984                         struct e1000_flex_filter *filter)
3985 {
3986         struct e1000_filter_info *filter_info =
3987                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3988         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3989         uint32_t wufc, i;
3990         uint32_t reg_off;
3991
3992         wufc = E1000_READ_REG(hw, E1000_WUFC);
3993         if (filter->index < E1000_MAX_FHFT)
3994                 reg_off = E1000_FHFT(filter->index);
3995         else
3996                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3997
3998         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3999                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4000
4001         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4002                 (~(E1000_WUFC_FLX0 << filter->index)));
4003
4004         filter_info->flex_mask &= ~(1 << filter->index);
4005         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4006         rte_free(filter);
4007 }
4008
4009 int
4010 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4011                         struct igb_flex_filter *filter,
4012                         bool add)
4013 {
4014         struct e1000_filter_info *filter_info =
4015                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4016         struct e1000_flex_filter *flex_filter, *it;
4017         uint32_t mask;
4018         uint8_t shift, i;
4019
4020         flex_filter = rte_zmalloc("e1000_flex_filter",
4021                         sizeof(struct e1000_flex_filter), 0);
4022         if (flex_filter == NULL)
4023                 return -ENOMEM;
4024
4025         flex_filter->filter_info.len = filter->len;
4026         flex_filter->filter_info.priority = filter->priority;
4027         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4028         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4029                 mask = 0;
4030                 /* reverse bits in flex filter's mask*/
4031                 for (shift = 0; shift < CHAR_BIT; shift++) {
4032                         if (filter->mask[i] & (0x01 << shift))
4033                                 mask |= (0x80 >> shift);
4034                 }
4035                 flex_filter->filter_info.mask[i] = mask;
4036         }
4037
4038         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4039                                 &flex_filter->filter_info);
4040         if (it == NULL && !add) {
4041                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4042                 rte_free(flex_filter);
4043                 return -ENOENT;
4044         }
4045         if (it != NULL && add) {
4046                 PMD_DRV_LOG(ERR, "filter exists.");
4047                 rte_free(flex_filter);
4048                 return -EEXIST;
4049         }
4050
4051         if (add) {
4052                 flex_filter->queue = filter->queue;
4053                 /*
4054                  * look for an unused flex filter index
4055                  * and insert the filter into the list.
4056                  */
4057                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4058                         if (!(filter_info->flex_mask & (1 << i))) {
4059                                 filter_info->flex_mask |= 1 << i;
4060                                 flex_filter->index = i;
4061                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4062                                         flex_filter,
4063                                         entries);
4064                                 break;
4065                         }
4066                 }
4067                 if (i >= E1000_MAX_FLEX_FILTERS) {
4068                         PMD_DRV_LOG(ERR, "flex filters are full.");
4069                         rte_free(flex_filter);
4070                         return -ENOSYS;
4071                 }
4072
4073                 igb_inject_flex_filter(dev, flex_filter);
4074
4075         } else {
4076                 igb_remove_flex_filter(dev, it);
4077                 rte_free(flex_filter);
4078         }
4079
4080         return 0;
4081 }
4082
4083 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4084 static inline int
4085 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4086                         struct e1000_5tuple_filter_info *filter_info)
4087 {
4088         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4089                 return -EINVAL;
4090         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4091                 return -EINVAL;  /* filter index is out of range. */
4092         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4093                 return -EINVAL;  /* flags is invalid. */
4094
4095         switch (filter->dst_ip_mask) {
4096         case UINT32_MAX:
4097                 filter_info->dst_ip_mask = 0;
4098                 filter_info->dst_ip = filter->dst_ip;
4099                 break;
4100         case 0:
4101                 filter_info->dst_ip_mask = 1;
4102                 break;
4103         default:
4104                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4105                 return -EINVAL;
4106         }
4107
4108         switch (filter->src_ip_mask) {
4109         case UINT32_MAX:
4110                 filter_info->src_ip_mask = 0;
4111                 filter_info->src_ip = filter->src_ip;
4112                 break;
4113         case 0:
4114                 filter_info->src_ip_mask = 1;
4115                 break;
4116         default:
4117                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4118                 return -EINVAL;
4119         }
4120
4121         switch (filter->dst_port_mask) {
4122         case UINT16_MAX:
4123                 filter_info->dst_port_mask = 0;
4124                 filter_info->dst_port = filter->dst_port;
4125                 break;
4126         case 0:
4127                 filter_info->dst_port_mask = 1;
4128                 break;
4129         default:
4130                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4131                 return -EINVAL;
4132         }
4133
4134         switch (filter->src_port_mask) {
4135         case UINT16_MAX:
4136                 filter_info->src_port_mask = 0;
4137                 filter_info->src_port = filter->src_port;
4138                 break;
4139         case 0:
4140                 filter_info->src_port_mask = 1;
4141                 break;
4142         default:
4143                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4144                 return -EINVAL;
4145         }
4146
4147         switch (filter->proto_mask) {
4148         case UINT8_MAX:
4149                 filter_info->proto_mask = 0;
4150                 filter_info->proto = filter->proto;
4151                 break;
4152         case 0:
4153                 filter_info->proto_mask = 1;
4154                 break;
4155         default:
4156                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4157                 return -EINVAL;
4158         }
4159
4160         filter_info->priority = (uint8_t)filter->priority;
4161         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4162                 filter_info->tcp_flags = filter->tcp_flags;
4163         else
4164                 filter_info->tcp_flags = 0;
4165
4166         return 0;
4167 }
4168
4169 static inline struct e1000_5tuple_filter *
4170 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4171                         struct e1000_5tuple_filter_info *key)
4172 {
4173         struct e1000_5tuple_filter *it;
4174
4175         TAILQ_FOREACH(it, filter_list, entries) {
4176                 if (memcmp(key, &it->filter_info,
4177                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4178                         return it;
4179                 }
4180         }
4181         return NULL;
4182 }
4183
4184 /* inject a igb 5-tuple filter to HW */
4185 static inline void
4186 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4187                            struct e1000_5tuple_filter *filter)
4188 {
4189         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4190         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4191         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4192         uint8_t i;
4193
4194         i = filter->index;
4195         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4196         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4197                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4198         if (filter->filter_info.dst_ip_mask == 0)
4199                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4200         if (filter->filter_info.src_port_mask == 0)
4201                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4202         if (filter->filter_info.proto_mask == 0)
4203                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4204         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4205                 E1000_FTQF_QUEUE_MASK;
4206         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4207         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4208         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4209         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4210
4211         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4212         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4213
4214         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4215         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4216                 imir |= E1000_IMIR_PORT_BP;
4217         else
4218                 imir &= ~E1000_IMIR_PORT_BP;
4219         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4220
4221         /* tcp flags bits setting. */
4222         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4223                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4224                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4225                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4226                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4227                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4228                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4229                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4230                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4231                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4232                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4233                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4234                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4235         } else {
4236                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4237         }
4238         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4239         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4240 }
4241
4242 /*
4243  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4244  *
4245  * @param
4246  * dev: Pointer to struct rte_eth_dev.
4247  * ntuple_filter: ponter to the filter that will be added.
4248  *
4249  * @return
4250  *    - On success, zero.
4251  *    - On failure, a negative value.
4252  */
4253 static int
4254 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4255                         struct rte_eth_ntuple_filter *ntuple_filter)
4256 {
4257         struct e1000_filter_info *filter_info =
4258                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4259         struct e1000_5tuple_filter *filter;
4260         uint8_t i;
4261         int ret;
4262
4263         filter = rte_zmalloc("e1000_5tuple_filter",
4264                         sizeof(struct e1000_5tuple_filter), 0);
4265         if (filter == NULL)
4266                 return -ENOMEM;
4267
4268         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4269                                             &filter->filter_info);
4270         if (ret < 0) {
4271                 rte_free(filter);
4272                 return ret;
4273         }
4274
4275         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4276                                          &filter->filter_info) != NULL) {
4277                 PMD_DRV_LOG(ERR, "filter exists.");
4278                 rte_free(filter);
4279                 return -EEXIST;
4280         }
4281         filter->queue = ntuple_filter->queue;
4282
4283         /*
4284          * look for an unused 5tuple filter index,
4285          * and insert the filter to list.
4286          */
4287         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4288                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4289                         filter_info->fivetuple_mask |= 1 << i;
4290                         filter->index = i;
4291                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4292                                           filter,
4293                                           entries);
4294                         break;
4295                 }
4296         }
4297         if (i >= E1000_MAX_FTQF_FILTERS) {
4298                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4299                 rte_free(filter);
4300                 return -ENOSYS;
4301         }
4302
4303         igb_inject_5tuple_filter_82576(dev, filter);
4304         return 0;
4305 }
4306
4307 int
4308 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4309                                 struct e1000_5tuple_filter *filter)
4310 {
4311         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4312         struct e1000_filter_info *filter_info =
4313                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4314
4315         filter_info->fivetuple_mask &= ~(1 << filter->index);
4316         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4317         rte_free(filter);
4318
4319         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4320                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4321         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4322         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4323         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4324         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4325         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4326         return 0;
4327 }
4328
4329 /*
4330  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4331  *
4332  * @param
4333  * dev: Pointer to struct rte_eth_dev.
4334  * ntuple_filter: ponter to the filter that will be removed.
4335  *
4336  * @return
4337  *    - On success, zero.
4338  *    - On failure, a negative value.
4339  */
4340 static int
4341 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4342                                 struct rte_eth_ntuple_filter *ntuple_filter)
4343 {
4344         struct e1000_filter_info *filter_info =
4345                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4346         struct e1000_5tuple_filter_info filter_5tuple;
4347         struct e1000_5tuple_filter *filter;
4348         int ret;
4349
4350         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4351         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4352                                             &filter_5tuple);
4353         if (ret < 0)
4354                 return ret;
4355
4356         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4357                                          &filter_5tuple);
4358         if (filter == NULL) {
4359                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4360                 return -ENOENT;
4361         }
4362
4363         igb_delete_5tuple_filter_82576(dev, filter);
4364
4365         return 0;
4366 }
4367
4368 static int
4369 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4370 {
4371         uint32_t rctl;
4372         struct e1000_hw *hw;
4373         struct rte_eth_dev_info dev_info;
4374         uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4375         int ret;
4376
4377         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4378
4379 #ifdef RTE_LIBRTE_82571_SUPPORT
4380         /* XXX: not bigger than max_rx_pktlen */
4381         if (hw->mac.type == e1000_82571)
4382                 return -ENOTSUP;
4383 #endif
4384         ret = eth_igb_infos_get(dev, &dev_info);
4385         if (ret != 0)
4386                 return ret;
4387
4388         /* check that mtu is within the allowed range */
4389         if (mtu < RTE_ETHER_MIN_MTU ||
4390                         frame_size > dev_info.max_rx_pktlen)
4391                 return -EINVAL;
4392
4393         /*
4394          * If device is started, refuse mtu that requires the support of
4395          * scattered packets when this feature has not been enabled before.
4396          */
4397         if (dev->data->dev_started && !dev->data->scattered_rx &&
4398             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
4399                 PMD_INIT_LOG(ERR, "Stop port first.");
4400                 return -EINVAL;
4401         }
4402
4403         rctl = E1000_READ_REG(hw, E1000_RCTL);
4404
4405         /* switch to jumbo mode if needed */
4406         if (frame_size > E1000_ETH_MAX_LEN) {
4407                 dev->data->dev_conf.rxmode.offloads |=
4408                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4409                 rctl |= E1000_RCTL_LPE;
4410         } else {
4411                 dev->data->dev_conf.rxmode.offloads &=
4412                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4413                 rctl &= ~E1000_RCTL_LPE;
4414         }
4415         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4416
4417         /* update max frame size */
4418         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4419
4420         E1000_WRITE_REG(hw, E1000_RLPML,
4421                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4422
4423         return 0;
4424 }
4425
4426 /*
4427  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4428  *
4429  * @param
4430  * dev: Pointer to struct rte_eth_dev.
4431  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4432  * add: if true, add filter, if false, remove filter
4433  *
4434  * @return
4435  *    - On success, zero.
4436  *    - On failure, a negative value.
4437  */
4438 int
4439 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4440                         struct rte_eth_ntuple_filter *ntuple_filter,
4441                         bool add)
4442 {
4443         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4444         int ret;
4445
4446         switch (ntuple_filter->flags) {
4447         case RTE_5TUPLE_FLAGS:
4448         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4449                 if (hw->mac.type != e1000_82576)
4450                         return -ENOTSUP;
4451                 if (add)
4452                         ret = igb_add_5tuple_filter_82576(dev,
4453                                                           ntuple_filter);
4454                 else
4455                         ret = igb_remove_5tuple_filter_82576(dev,
4456                                                              ntuple_filter);
4457                 break;
4458         case RTE_2TUPLE_FLAGS:
4459         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4460                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4461                         hw->mac.type != e1000_i210 &&
4462                         hw->mac.type != e1000_i211)
4463                         return -ENOTSUP;
4464                 if (add)
4465                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4466                 else
4467                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4468                 break;
4469         default:
4470                 ret = -EINVAL;
4471                 break;
4472         }
4473
4474         return ret;
4475 }
4476
4477 static inline int
4478 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4479                         uint16_t ethertype)
4480 {
4481         int i;
4482
4483         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4484                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4485                     (filter_info->ethertype_mask & (1 << i)))
4486                         return i;
4487         }
4488         return -1;
4489 }
4490
4491 static inline int
4492 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4493                         uint16_t ethertype, uint32_t etqf)
4494 {
4495         int i;
4496
4497         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4498                 if (!(filter_info->ethertype_mask & (1 << i))) {
4499                         filter_info->ethertype_mask |= 1 << i;
4500                         filter_info->ethertype_filters[i].ethertype = ethertype;
4501                         filter_info->ethertype_filters[i].etqf = etqf;
4502                         return i;
4503                 }
4504         }
4505         return -1;
4506 }
4507
4508 int
4509 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4510                         uint8_t idx)
4511 {
4512         if (idx >= E1000_MAX_ETQF_FILTERS)
4513                 return -1;
4514         filter_info->ethertype_mask &= ~(1 << idx);
4515         filter_info->ethertype_filters[idx].ethertype = 0;
4516         filter_info->ethertype_filters[idx].etqf = 0;
4517         return idx;
4518 }
4519
4520
4521 int
4522 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4523                         struct rte_eth_ethertype_filter *filter,
4524                         bool add)
4525 {
4526         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4527         struct e1000_filter_info *filter_info =
4528                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4529         uint32_t etqf = 0;
4530         int ret;
4531
4532         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4533                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4534                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4535                         " ethertype filter.", filter->ether_type);
4536                 return -EINVAL;
4537         }
4538
4539         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4540                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4541                 return -EINVAL;
4542         }
4543         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4544                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4545                 return -EINVAL;
4546         }
4547
4548         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4549         if (ret >= 0 && add) {
4550                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4551                             filter->ether_type);
4552                 return -EEXIST;
4553         }
4554         if (ret < 0 && !add) {
4555                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4556                             filter->ether_type);
4557                 return -ENOENT;
4558         }
4559
4560         if (add) {
4561                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4562                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4563                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4564                 ret = igb_ethertype_filter_insert(filter_info,
4565                                 filter->ether_type, etqf);
4566                 if (ret < 0) {
4567                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4568                         return -ENOSYS;
4569                 }
4570         } else {
4571                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4572                 if (ret < 0)
4573                         return -ENOSYS;
4574         }
4575         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4576         E1000_WRITE_FLUSH(hw);
4577
4578         return 0;
4579 }
4580
4581 static int
4582 eth_igb_flow_ops_get(struct rte_eth_dev *dev __rte_unused,
4583                      const struct rte_flow_ops **ops)
4584 {
4585         *ops = &igb_flow_ops;
4586         return 0;
4587 }
4588
4589 static int
4590 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4591                          struct rte_ether_addr *mc_addr_set,
4592                          uint32_t nb_mc_addr)
4593 {
4594         struct e1000_hw *hw;
4595
4596         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4597         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4598         return 0;
4599 }
4600
4601 static uint64_t
4602 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4603 {
4604         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4605         uint64_t systime_cycles;
4606
4607         switch (hw->mac.type) {
4608         case e1000_i210:
4609         case e1000_i211:
4610                 /*
4611                  * Need to read System Time Residue Register to be able
4612                  * to read the other two registers.
4613                  */
4614                 E1000_READ_REG(hw, E1000_SYSTIMR);
4615                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4616                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4617                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4618                                 * NSEC_PER_SEC;
4619                 break;
4620         case e1000_82580:
4621         case e1000_i350:
4622         case e1000_i354:
4623                 /*
4624                  * Need to read System Time Residue Register to be able
4625                  * to read the other two registers.
4626                  */
4627                 E1000_READ_REG(hw, E1000_SYSTIMR);
4628                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4629                 /* Only the 8 LSB are valid. */
4630                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4631                                 & 0xff) << 32;
4632                 break;
4633         default:
4634                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4635                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4636                                 << 32;
4637                 break;
4638         }
4639
4640         return systime_cycles;
4641 }
4642
4643 static uint64_t
4644 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4645 {
4646         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4647         uint64_t rx_tstamp_cycles;
4648
4649         switch (hw->mac.type) {
4650         case e1000_i210:
4651         case e1000_i211:
4652                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4653                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4654                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4655                                 * NSEC_PER_SEC;
4656                 break;
4657         case e1000_82580:
4658         case e1000_i350:
4659         case e1000_i354:
4660                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4661                 /* Only the 8 LSB are valid. */
4662                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4663                                 & 0xff) << 32;
4664                 break;
4665         default:
4666                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4667                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4668                                 << 32;
4669                 break;
4670         }
4671
4672         return rx_tstamp_cycles;
4673 }
4674
4675 static uint64_t
4676 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4677 {
4678         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4679         uint64_t tx_tstamp_cycles;
4680
4681         switch (hw->mac.type) {
4682         case e1000_i210:
4683         case e1000_i211:
4684                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4685                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4686                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4687                                 * NSEC_PER_SEC;
4688                 break;
4689         case e1000_82580:
4690         case e1000_i350:
4691         case e1000_i354:
4692                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4693                 /* Only the 8 LSB are valid. */
4694                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4695                                 & 0xff) << 32;
4696                 break;
4697         default:
4698                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4699                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4700                                 << 32;
4701                 break;
4702         }
4703
4704         return tx_tstamp_cycles;
4705 }
4706
4707 static void
4708 igb_start_timecounters(struct rte_eth_dev *dev)
4709 {
4710         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4711         struct e1000_adapter *adapter = dev->data->dev_private;
4712         uint32_t incval = 1;
4713         uint32_t shift = 0;
4714         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4715
4716         switch (hw->mac.type) {
4717         case e1000_82580:
4718         case e1000_i350:
4719         case e1000_i354:
4720                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4721                 mask = (1ULL << 40) - 1;
4722                 /* fall-through */
4723         case e1000_i210:
4724         case e1000_i211:
4725                 /*
4726                  * Start incrementing the register
4727                  * used to timestamp PTP packets.
4728                  */
4729                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4730                 break;
4731         case e1000_82576:
4732                 incval = E1000_INCVALUE_82576;
4733                 shift = IGB_82576_TSYNC_SHIFT;
4734                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4735                                 E1000_INCPERIOD_82576 | incval);
4736                 break;
4737         default:
4738                 /* Not supported */
4739                 return;
4740         }
4741
4742         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4743         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4744         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4745
4746         adapter->systime_tc.cc_mask = mask;
4747         adapter->systime_tc.cc_shift = shift;
4748         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4749
4750         adapter->rx_tstamp_tc.cc_mask = mask;
4751         adapter->rx_tstamp_tc.cc_shift = shift;
4752         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4753
4754         adapter->tx_tstamp_tc.cc_mask = mask;
4755         adapter->tx_tstamp_tc.cc_shift = shift;
4756         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4757 }
4758
4759 static int
4760 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4761 {
4762         struct e1000_adapter *adapter = dev->data->dev_private;
4763
4764         adapter->systime_tc.nsec += delta;
4765         adapter->rx_tstamp_tc.nsec += delta;
4766         adapter->tx_tstamp_tc.nsec += delta;
4767
4768         return 0;
4769 }
4770
4771 static int
4772 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4773 {
4774         uint64_t ns;
4775         struct e1000_adapter *adapter = dev->data->dev_private;
4776
4777         ns = rte_timespec_to_ns(ts);
4778
4779         /* Set the timecounters to a new value. */
4780         adapter->systime_tc.nsec = ns;
4781         adapter->rx_tstamp_tc.nsec = ns;
4782         adapter->tx_tstamp_tc.nsec = ns;
4783
4784         return 0;
4785 }
4786
4787 static int
4788 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4789 {
4790         uint64_t ns, systime_cycles;
4791         struct e1000_adapter *adapter = dev->data->dev_private;
4792
4793         systime_cycles = igb_read_systime_cyclecounter(dev);
4794         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4795         *ts = rte_ns_to_timespec(ns);
4796
4797         return 0;
4798 }
4799
4800 static int
4801 igb_timesync_enable(struct rte_eth_dev *dev)
4802 {
4803         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4804         uint32_t tsync_ctl;
4805         uint32_t tsauxc;
4806
4807         /* Stop the timesync system time. */
4808         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4809         /* Reset the timesync system time value. */
4810         switch (hw->mac.type) {
4811         case e1000_82580:
4812         case e1000_i350:
4813         case e1000_i354:
4814         case e1000_i210:
4815         case e1000_i211:
4816                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4817                 /* fall-through */
4818         case e1000_82576:
4819                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4820                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4821                 break;
4822         default:
4823                 /* Not supported. */
4824                 return -ENOTSUP;
4825         }
4826
4827         /* Enable system time for it isn't on by default. */
4828         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4829         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4830         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4831
4832         igb_start_timecounters(dev);
4833
4834         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4835         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4836                         (RTE_ETHER_TYPE_1588 |
4837                          E1000_ETQF_FILTER_ENABLE |
4838                          E1000_ETQF_1588));
4839
4840         /* Enable timestamping of received PTP packets. */
4841         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4842         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4843         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4844
4845         /* Enable Timestamping of transmitted PTP packets. */
4846         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4847         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4848         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4849
4850         return 0;
4851 }
4852
4853 static int
4854 igb_timesync_disable(struct rte_eth_dev *dev)
4855 {
4856         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4857         uint32_t tsync_ctl;
4858
4859         /* Disable timestamping of transmitted PTP packets. */
4860         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4861         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4862         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4863
4864         /* Disable timestamping of received PTP packets. */
4865         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4866         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4867         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4868
4869         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4870         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4871
4872         /* Stop incrementating the System Time registers. */
4873         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4874
4875         return 0;
4876 }
4877
4878 static int
4879 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4880                                struct timespec *timestamp,
4881                                uint32_t flags __rte_unused)
4882 {
4883         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4884         struct e1000_adapter *adapter = dev->data->dev_private;
4885         uint32_t tsync_rxctl;
4886         uint64_t rx_tstamp_cycles;
4887         uint64_t ns;
4888
4889         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4890         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4891                 return -EINVAL;
4892
4893         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4894         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4895         *timestamp = rte_ns_to_timespec(ns);
4896
4897         return  0;
4898 }
4899
4900 static int
4901 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4902                                struct timespec *timestamp)
4903 {
4904         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4905         struct e1000_adapter *adapter = dev->data->dev_private;
4906         uint32_t tsync_txctl;
4907         uint64_t tx_tstamp_cycles;
4908         uint64_t ns;
4909
4910         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4911         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4912                 return -EINVAL;
4913
4914         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4915         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4916         *timestamp = rte_ns_to_timespec(ns);
4917
4918         return  0;
4919 }
4920
4921 static int
4922 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4923 {
4924         int count = 0;
4925         int g_ind = 0;
4926         const struct reg_info *reg_group;
4927
4928         while ((reg_group = igb_regs[g_ind++]))
4929                 count += igb_reg_group_count(reg_group);
4930
4931         return count;
4932 }
4933
4934 static int
4935 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4936 {
4937         int count = 0;
4938         int g_ind = 0;
4939         const struct reg_info *reg_group;
4940
4941         while ((reg_group = igbvf_regs[g_ind++]))
4942                 count += igb_reg_group_count(reg_group);
4943
4944         return count;
4945 }
4946
4947 static int
4948 eth_igb_get_regs(struct rte_eth_dev *dev,
4949         struct rte_dev_reg_info *regs)
4950 {
4951         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4952         uint32_t *data = regs->data;
4953         int g_ind = 0;
4954         int count = 0;
4955         const struct reg_info *reg_group;
4956
4957         if (data == NULL) {
4958                 regs->length = eth_igb_get_reg_length(dev);
4959                 regs->width = sizeof(uint32_t);
4960                 return 0;
4961         }
4962
4963         /* Support only full register dump */
4964         if ((regs->length == 0) ||
4965             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4966                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4967                         hw->device_id;
4968                 while ((reg_group = igb_regs[g_ind++]))
4969                         count += igb_read_regs_group(dev, &data[count],
4970                                                         reg_group);
4971                 return 0;
4972         }
4973
4974         return -ENOTSUP;
4975 }
4976
4977 static int
4978 igbvf_get_regs(struct rte_eth_dev *dev,
4979         struct rte_dev_reg_info *regs)
4980 {
4981         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4982         uint32_t *data = regs->data;
4983         int g_ind = 0;
4984         int count = 0;
4985         const struct reg_info *reg_group;
4986
4987         if (data == NULL) {
4988                 regs->length = igbvf_get_reg_length(dev);
4989                 regs->width = sizeof(uint32_t);
4990                 return 0;
4991         }
4992
4993         /* Support only full register dump */
4994         if ((regs->length == 0) ||
4995             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4996                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4997                         hw->device_id;
4998                 while ((reg_group = igbvf_regs[g_ind++]))
4999                         count += igb_read_regs_group(dev, &data[count],
5000                                                         reg_group);
5001                 return 0;
5002         }
5003
5004         return -ENOTSUP;
5005 }
5006
5007 static int
5008 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5009 {
5010         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5011
5012         /* Return unit is byte count */
5013         return hw->nvm.word_size * 2;
5014 }
5015
5016 static int
5017 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5018         struct rte_dev_eeprom_info *in_eeprom)
5019 {
5020         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5021         struct e1000_nvm_info *nvm = &hw->nvm;
5022         uint16_t *data = in_eeprom->data;
5023         int first, length;
5024
5025         first = in_eeprom->offset >> 1;
5026         length = in_eeprom->length >> 1;
5027         if ((first >= hw->nvm.word_size) ||
5028             ((first + length) >= hw->nvm.word_size))
5029                 return -EINVAL;
5030
5031         in_eeprom->magic = hw->vendor_id |
5032                 ((uint32_t)hw->device_id << 16);
5033
5034         if ((nvm->ops.read) == NULL)
5035                 return -ENOTSUP;
5036
5037         return nvm->ops.read(hw, first, length, data);
5038 }
5039
5040 static int
5041 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5042         struct rte_dev_eeprom_info *in_eeprom)
5043 {
5044         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5045         struct e1000_nvm_info *nvm = &hw->nvm;
5046         uint16_t *data = in_eeprom->data;
5047         int first, length;
5048
5049         first = in_eeprom->offset >> 1;
5050         length = in_eeprom->length >> 1;
5051         if ((first >= hw->nvm.word_size) ||
5052             ((first + length) >= hw->nvm.word_size))
5053                 return -EINVAL;
5054
5055         in_eeprom->magic = (uint32_t)hw->vendor_id |
5056                 ((uint32_t)hw->device_id << 16);
5057
5058         if ((nvm->ops.write) == NULL)
5059                 return -ENOTSUP;
5060         return nvm->ops.write(hw,  first, length, data);
5061 }
5062
5063 static int
5064 eth_igb_get_module_info(struct rte_eth_dev *dev,
5065                         struct rte_eth_dev_module_info *modinfo)
5066 {
5067         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5068
5069         uint32_t status = 0;
5070         uint16_t sff8472_rev, addr_mode;
5071         bool page_swap = false;
5072
5073         if (hw->phy.media_type == e1000_media_type_copper ||
5074             hw->phy.media_type == e1000_media_type_unknown)
5075                 return -EOPNOTSUPP;
5076
5077         /* Check whether we support SFF-8472 or not */
5078         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5079         if (status)
5080                 return -EIO;
5081
5082         /* addressing mode is not supported */
5083         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5084         if (status)
5085                 return -EIO;
5086
5087         /* addressing mode is not supported */
5088         if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5089                 PMD_DRV_LOG(ERR,
5090                             "Address change required to access page 0xA2, "
5091                             "but not supported. Please report the module "
5092                             "type to the driver maintainers.\n");
5093                 page_swap = true;
5094         }
5095
5096         if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5097                 /* We have an SFP, but it does not support SFF-8472 */
5098                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5099                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5100         } else {
5101                 /* We have an SFP which supports a revision of SFF-8472 */
5102                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5103                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5104         }
5105
5106         return 0;
5107 }
5108
5109 static int
5110 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5111                           struct rte_dev_eeprom_info *info)
5112 {
5113         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5114
5115         uint32_t status = 0;
5116         uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5117         u16 first_word, last_word;
5118         int i = 0;
5119
5120         first_word = info->offset >> 1;
5121         last_word = (info->offset + info->length - 1) >> 1;
5122
5123         /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5124         for (i = 0; i < last_word - first_word + 1; i++) {
5125                 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5126                                                 &dataword[i]);
5127                 if (status) {
5128                         /* Error occurred while reading module */
5129                         return -EIO;
5130                 }
5131
5132                 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5133         }
5134
5135         memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5136
5137         return 0;
5138 }
5139
5140 static int
5141 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5142 {
5143         struct e1000_hw *hw =
5144                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5145         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5146         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5147         uint32_t vec = E1000_MISC_VEC_ID;
5148
5149         if (rte_intr_allow_others(intr_handle))
5150                 vec = E1000_RX_VEC_START;
5151
5152         uint32_t mask = 1 << (queue_id + vec);
5153
5154         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5155         E1000_WRITE_FLUSH(hw);
5156
5157         return 0;
5158 }
5159
5160 static int
5161 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5162 {
5163         struct e1000_hw *hw =
5164                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5165         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5166         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5167         uint32_t vec = E1000_MISC_VEC_ID;
5168
5169         if (rte_intr_allow_others(intr_handle))
5170                 vec = E1000_RX_VEC_START;
5171
5172         uint32_t mask = 1 << (queue_id + vec);
5173         uint32_t regval;
5174
5175         regval = E1000_READ_REG(hw, E1000_EIMS);
5176         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5177         E1000_WRITE_FLUSH(hw);
5178
5179         rte_intr_ack(intr_handle);
5180
5181         return 0;
5182 }
5183
5184 static void
5185 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5186                    uint8_t index, uint8_t offset)
5187 {
5188         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5189
5190         /* clear bits */
5191         val &= ~((uint32_t)0xFF << offset);
5192
5193         /* write vector and valid bit */
5194         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5195
5196         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5197 }
5198
5199 static void
5200 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5201                            uint8_t queue, uint8_t msix_vector)
5202 {
5203         uint32_t tmp = 0;
5204
5205         if (hw->mac.type == e1000_82575) {
5206                 if (direction == 0)
5207                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5208                 else if (direction == 1)
5209                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5210                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5211         } else if (hw->mac.type == e1000_82576) {
5212                 if ((direction == 0) || (direction == 1))
5213                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5214                                            ((queue & 0x8) << 1) +
5215                                            8 * direction);
5216         } else if ((hw->mac.type == e1000_82580) ||
5217                         (hw->mac.type == e1000_i350) ||
5218                         (hw->mac.type == e1000_i354) ||
5219                         (hw->mac.type == e1000_i210) ||
5220                         (hw->mac.type == e1000_i211)) {
5221                 if ((direction == 0) || (direction == 1))
5222                         eth_igb_write_ivar(hw, msix_vector,
5223                                            queue >> 1,
5224                                            ((queue & 0x1) << 4) +
5225                                            8 * direction);
5226         }
5227 }
5228
5229 /* Sets up the hardware to generate MSI-X interrupts properly
5230  * @hw
5231  *  board private structure
5232  */
5233 static void
5234 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5235 {
5236         int queue_id;
5237         uint32_t tmpval, regval, intr_mask;
5238         struct e1000_hw *hw =
5239                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5240         uint32_t vec = E1000_MISC_VEC_ID;
5241         uint32_t base = E1000_MISC_VEC_ID;
5242         uint32_t misc_shift = 0;
5243         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5244         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5245
5246         /* won't configure msix register if no mapping is done
5247          * between intr vector and event fd
5248          */
5249         if (!rte_intr_dp_is_en(intr_handle))
5250                 return;
5251
5252         if (rte_intr_allow_others(intr_handle)) {
5253                 vec = base = E1000_RX_VEC_START;
5254                 misc_shift = 1;
5255         }
5256
5257         /* set interrupt vector for other causes */
5258         if (hw->mac.type == e1000_82575) {
5259                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5260                 /* enable MSI-X PBA support */
5261                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5262
5263                 /* Auto-Mask interrupts upon ICR read */
5264                 tmpval |= E1000_CTRL_EXT_EIAME;
5265                 tmpval |= E1000_CTRL_EXT_IRCA;
5266
5267                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5268
5269                 /* enable msix_other interrupt */
5270                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5271                 regval = E1000_READ_REG(hw, E1000_EIAC);
5272                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5273                 regval = E1000_READ_REG(hw, E1000_EIAM);
5274                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5275         } else if ((hw->mac.type == e1000_82576) ||
5276                         (hw->mac.type == e1000_82580) ||
5277                         (hw->mac.type == e1000_i350) ||
5278                         (hw->mac.type == e1000_i354) ||
5279                         (hw->mac.type == e1000_i210) ||
5280                         (hw->mac.type == e1000_i211)) {
5281                 /* turn on MSI-X capability first */
5282                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5283                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5284                                         E1000_GPIE_NSICR);
5285                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5286                         misc_shift;
5287
5288                 if (dev->data->dev_conf.intr_conf.lsc != 0)
5289                         intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5290
5291                 regval = E1000_READ_REG(hw, E1000_EIAC);
5292                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5293
5294                 /* enable msix_other interrupt */
5295                 regval = E1000_READ_REG(hw, E1000_EIMS);
5296                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5297                 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5298                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5299         }
5300
5301         /* use EIAM to auto-mask when MSI-X interrupt
5302          * is asserted, this saves a register write for every interrupt
5303          */
5304         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5305                 misc_shift;
5306
5307         if (dev->data->dev_conf.intr_conf.lsc != 0)
5308                 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5309
5310         regval = E1000_READ_REG(hw, E1000_EIAM);
5311         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5312
5313         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5314                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5315                 intr_handle->intr_vec[queue_id] = vec;
5316                 if (vec < base + intr_handle->nb_efd - 1)
5317                         vec++;
5318         }
5319
5320         E1000_WRITE_FLUSH(hw);
5321 }
5322
5323 /* restore n-tuple filter */
5324 static inline void
5325 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5326 {
5327         struct e1000_filter_info *filter_info =
5328                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5329         struct e1000_5tuple_filter *p_5tuple;
5330         struct e1000_2tuple_filter *p_2tuple;
5331
5332         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5333                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5334         }
5335
5336         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5337                 igb_inject_2uple_filter(dev, p_2tuple);
5338         }
5339 }
5340
5341 /* restore SYN filter */
5342 static inline void
5343 igb_syn_filter_restore(struct rte_eth_dev *dev)
5344 {
5345         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5346         struct e1000_filter_info *filter_info =
5347                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5348         uint32_t synqf;
5349
5350         synqf = filter_info->syn_info;
5351
5352         if (synqf & E1000_SYN_FILTER_ENABLE) {
5353                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5354                 E1000_WRITE_FLUSH(hw);
5355         }
5356 }
5357
5358 /* restore ethernet type filter */
5359 static inline void
5360 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5361 {
5362         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5363         struct e1000_filter_info *filter_info =
5364                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5365         int i;
5366
5367         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5368                 if (filter_info->ethertype_mask & (1 << i)) {
5369                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5370                                 filter_info->ethertype_filters[i].etqf);
5371                         E1000_WRITE_FLUSH(hw);
5372                 }
5373         }
5374 }
5375
5376 /* restore flex byte filter */
5377 static inline void
5378 igb_flex_filter_restore(struct rte_eth_dev *dev)
5379 {
5380         struct e1000_filter_info *filter_info =
5381                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5382         struct e1000_flex_filter *flex_filter;
5383
5384         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5385                 igb_inject_flex_filter(dev, flex_filter);
5386         }
5387 }
5388
5389 /* restore rss filter */
5390 static inline void
5391 igb_rss_filter_restore(struct rte_eth_dev *dev)
5392 {
5393         struct e1000_filter_info *filter_info =
5394                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5395
5396         if (filter_info->rss_info.conf.queue_num)
5397                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5398 }
5399
5400 /* restore all types filter */
5401 static int
5402 igb_filter_restore(struct rte_eth_dev *dev)
5403 {
5404         igb_ntuple_filter_restore(dev);
5405         igb_ethertype_filter_restore(dev);
5406         igb_syn_filter_restore(dev);
5407         igb_flex_filter_restore(dev);
5408         igb_rss_filter_restore(dev);
5409
5410         return 0;
5411 }
5412
5413 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5414 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5415 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5416 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5417 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5418 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");