drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_interrupts.h>
  13 #include <rte_byteorder.h>
  14 #include <rte_log.h>
  15 #include <rte_debug.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memory.h>
  22 #include <rte_eal.h>
  23 #include <rte_malloc.h>
  24 #include <rte_dev.h>
  25
  26 #include "e1000_logs.h"
  27 #include "base/e1000_api.h"
  28 #include "e1000_ethdev.h"
  29 #include "igb_regs.h"
  30
  31 /*
  32  * Default values for port configuration
  33  */
  34 #define IGB_DEFAULT_RX_FREE_THRESH  32
  35
  36 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  37 #define IGB_DEFAULT_RX_HTHRESH      8
  38 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  39
  40 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  41 #define IGB_DEFAULT_TX_HTHRESH      1
  42 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  43
  44 #define IGB_HKEY_MAX_INDEX 10
  45
  46 /* Bit shift and mask */
  47 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  48 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  49 #define IGB_8_BIT_WIDTH  CHAR_BIT
  50 #define IGB_8_BIT_MASK   UINT8_MAX
  51
  52 /* Additional timesync values. */
  53 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  54 #define E1000_ETQF_FILTER_1588       3
  55 #define IGB_82576_TSYNC_SHIFT        16
  56 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  57 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  58 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  59
  60 #define E1000_VTIVAR_MISC                0x01740
  61 #define E1000_VTIVAR_MISC_MASK           0xFF
  62 #define E1000_VTIVAR_VALID               0x80
  63 #define E1000_VTIVAR_MISC_MAILBOX        0
  64 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  65
  66 /* External VLAN Enable bit mask */
  67 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  68
  69 /* External VLAN Ether Type bit mask and shift */
  70 #define E1000_VET_VET_EXT            0xFFFF0000
  71 #define E1000_VET_VET_EXT_SHIFT      16
  72
  73 static int  eth_igb_configure(struct rte_eth_dev *dev);
  74 static int  eth_igb_start(struct rte_eth_dev *dev);
  75 static void eth_igb_stop(struct rte_eth_dev *dev);
  76 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  77 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  78 static void eth_igb_close(struct rte_eth_dev *dev);
  79 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  80 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  81 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  82 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  83 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  84                                 int wait_to_complete);
  85 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  86                                 struct rte_eth_stats *rte_stats);
  87 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  88                               struct rte_eth_xstat *xstats, unsigned n);
  89 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  90                 const uint64_t *ids,
  91                 uint64_t *values, unsigned int n);
  92 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  93                                     struct rte_eth_xstat_name *xstats_names,
  94                                     unsigned int size);
  95 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  96                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
  97                 unsigned int limit);
  98 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  99 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 100 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 101                                    char *fw_version, size_t fw_size);
 102 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 103                               struct rte_eth_dev_info *dev_info);
 104 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 105 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 106                                 struct rte_eth_dev_info *dev_info);
 107 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_fc_conf *fc_conf);
 109 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 110                                 struct rte_eth_fc_conf *fc_conf);
 111 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 112 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 113 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 114 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 115                                     struct rte_intr_handle *handle);
 116 static void eth_igb_interrupt_handler(void *param);
 117 static int  igb_hardware_init(struct e1000_hw *hw);
 118 static void igb_hw_control_acquire(struct e1000_hw *hw);
 119 static void igb_hw_control_release(struct e1000_hw *hw);
 120 static void igb_init_manageability(struct e1000_hw *hw);
 121 static void igb_release_manageability(struct e1000_hw *hw);
 122
 123 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 124
 125 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 126                 uint16_t vlan_id, int on);
 127 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 128                                  enum rte_vlan_type vlan_type,
 129                                  uint16_t tpid_id);
 130 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 131
 132 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 133 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 134 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 135 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 138
 139 static int eth_igb_led_on(struct rte_eth_dev *dev);
 140 static int eth_igb_led_off(struct rte_eth_dev *dev);
 141
 142 static void igb_intr_disable(struct e1000_hw *hw);
 143 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 144 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 145                            struct ether_addr *mac_addr,
 146                            uint32_t index, uint32_t pool);
 147 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 148 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 149                 struct ether_addr *addr);
 150
 151 static void igbvf_intr_disable(struct e1000_hw *hw);
 152 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 153 static int igbvf_dev_start(struct rte_eth_dev *dev);
 154 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 155 static void igbvf_dev_close(struct rte_eth_dev *dev);
 156 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 157 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 158 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 159 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 160 static int eth_igbvf_link_update(struct e1000_hw *hw);
 161 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 162                                 struct rte_eth_stats *rte_stats);
 163 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 164                                 struct rte_eth_xstat *xstats, unsigned n);
 165 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 166                                       struct rte_eth_xstat_name *xstats_names,
 167                                       unsigned limit);
 168 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 169 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 170                 uint16_t vlan_id, int on);
 171 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 172 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 173 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 174                 struct ether_addr *addr);
 175 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 176 static int igbvf_get_regs(struct rte_eth_dev *dev,
 177                 struct rte_dev_reg_info *regs);
 178
 179 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 180                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 181                                    uint16_t reta_size);
 182 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 183                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                   uint16_t reta_size);
 185
 186 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 187                         struct rte_eth_syn_filter *filter);
 188 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 189                         enum rte_filter_op filter_op,
 190                         void *arg);
 191 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 192                         struct rte_eth_ntuple_filter *ntuple_filter);
 193 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 194                         struct rte_eth_ntuple_filter *ntuple_filter);
 195 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 196                         struct rte_eth_flex_filter *filter);
 197 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 198                         enum rte_filter_op filter_op,
 199                         void *arg);
 200 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 201                         struct rte_eth_ntuple_filter *ntuple_filter);
 202 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 203                         struct rte_eth_ntuple_filter *ntuple_filter);
 204 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 205                         struct rte_eth_ntuple_filter *filter);
 206 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 207                                 enum rte_filter_op filter_op,
 208                                 void *arg);
 209 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 213                         struct rte_eth_ethertype_filter *filter);
 214 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 215                      enum rte_filter_type filter_type,
 216                      enum rte_filter_op filter_op,
 217                      void *arg);
 218 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 219 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 220                 struct rte_dev_reg_info *regs);
 221 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 222 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 223                 struct rte_dev_eeprom_info *eeprom);
 224 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 225                 struct rte_dev_eeprom_info *eeprom);
 226 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 227                                     struct ether_addr *mc_addr_set,
 228                                     uint32_t nb_mc_addr);
 229 static int igb_timesync_enable(struct rte_eth_dev *dev);
 230 static int igb_timesync_disable(struct rte_eth_dev *dev);
 231 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 232                                           struct timespec *timestamp,
 233                                           uint32_t flags);
 234 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 235                                           struct timespec *timestamp);
 236 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 237 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 238                                   struct timespec *timestamp);
 239 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 240                                    const struct timespec *timestamp);
 241 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 242                                         uint16_t queue_id);
 243 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 244                                          uint16_t queue_id);
 245 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 246                                        uint8_t queue, uint8_t msix_vector);
 247 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 248                                uint8_t index, uint8_t offset);
 249 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 250 static void eth_igbvf_interrupt_handler(void *param);
 251 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 252 static int igb_filter_restore(struct rte_eth_dev *dev);
 253
 254 /*
 255  * Define VF Stats MACRO for Non "cleared on read" register
 256  */
 257 #define UPDATE_VF_STAT(reg, last, cur)            \
 258 {                                                 \
 259         u32 latest = E1000_READ_REG(hw, reg);     \
 260         cur += (latest - last) & UINT_MAX;        \
 261         last = latest;                            \
 262 }
 263
 264 #define IGB_FC_PAUSE_TIME 0x0680
 265 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 266 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 267
 268 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 269
 270 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 271
 272 /*
 273  * The set of PCI devices this driver supports
 274  */
 275 static const struct rte_pci_id pci_id_igb_map[] = {
 276         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 277         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 278         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 279         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 280         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 281         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 282         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 284
 285         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 286         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 287         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 288
 289         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 290         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 291         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 292         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 295
 296         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 297         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 302         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 303         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 304         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 305         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 317         { .vendor_id = 0, /* sentinel */ },
 318 };
 319
 320 /*
 321  * The set of PCI devices this driver supports (for 82576&I350 VF)
 322  */
 323 static const struct rte_pci_id pci_id_igbvf_map[] = {
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 328         { .vendor_id = 0, /* sentinel */ },
 329 };
 330
 331 static const struct rte_eth_desc_lim rx_desc_lim = {
 332         .nb_max = E1000_MAX_RING_DESC,
 333         .nb_min = E1000_MIN_RING_DESC,
 334         .nb_align = IGB_RXD_ALIGN,
 335 };
 336
 337 static const struct rte_eth_desc_lim tx_desc_lim = {
 338         .nb_max = E1000_MAX_RING_DESC,
 339         .nb_min = E1000_MIN_RING_DESC,
 340         .nb_align = IGB_RXD_ALIGN,
 341         .nb_seg_max = IGB_TX_MAX_SEG,
 342         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 343 };
 344
 345 static const struct eth_dev_ops eth_igb_ops = {
 346         .dev_configure        = eth_igb_configure,
 347         .dev_start            = eth_igb_start,
 348         .dev_stop             = eth_igb_stop,
 349         .dev_set_link_up      = eth_igb_dev_set_link_up,
 350         .dev_set_link_down    = eth_igb_dev_set_link_down,
 351         .dev_close            = eth_igb_close,
 352         .promiscuous_enable   = eth_igb_promiscuous_enable,
 353         .promiscuous_disable  = eth_igb_promiscuous_disable,
 354         .allmulticast_enable  = eth_igb_allmulticast_enable,
 355         .allmulticast_disable = eth_igb_allmulticast_disable,
 356         .link_update          = eth_igb_link_update,
 357         .stats_get            = eth_igb_stats_get,
 358         .xstats_get           = eth_igb_xstats_get,
 359         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 360         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 361         .xstats_get_names     = eth_igb_xstats_get_names,
 362         .stats_reset          = eth_igb_stats_reset,
 363         .xstats_reset         = eth_igb_xstats_reset,
 364         .fw_version_get       = eth_igb_fw_version_get,
 365         .dev_infos_get        = eth_igb_infos_get,
 366         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 367         .mtu_set              = eth_igb_mtu_set,
 368         .vlan_filter_set      = eth_igb_vlan_filter_set,
 369         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 370         .vlan_offload_set     = eth_igb_vlan_offload_set,
 371         .rx_queue_setup       = eth_igb_rx_queue_setup,
 372         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 373         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 374         .rx_queue_release     = eth_igb_rx_queue_release,
 375         .rx_queue_count       = eth_igb_rx_queue_count,
 376         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 377         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 378         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 379         .tx_queue_setup       = eth_igb_tx_queue_setup,
 380         .tx_queue_release     = eth_igb_tx_queue_release,
 381         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 382         .dev_led_on           = eth_igb_led_on,
 383         .dev_led_off          = eth_igb_led_off,
 384         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 385         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 386         .mac_addr_add         = eth_igb_rar_set,
 387         .mac_addr_remove      = eth_igb_rar_clear,
 388         .mac_addr_set         = eth_igb_default_mac_addr_set,
 389         .reta_update          = eth_igb_rss_reta_update,
 390         .reta_query           = eth_igb_rss_reta_query,
 391         .rss_hash_update      = eth_igb_rss_hash_update,
 392         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 393         .filter_ctrl          = eth_igb_filter_ctrl,
 394         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 395         .rxq_info_get         = igb_rxq_info_get,
 396         .txq_info_get         = igb_txq_info_get,
 397         .timesync_enable      = igb_timesync_enable,
 398         .timesync_disable     = igb_timesync_disable,
 399         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 400         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 401         .get_reg              = eth_igb_get_regs,
 402         .get_eeprom_length    = eth_igb_get_eeprom_length,
 403         .get_eeprom           = eth_igb_get_eeprom,
 404         .set_eeprom           = eth_igb_set_eeprom,
 405         .timesync_adjust_time = igb_timesync_adjust_time,
 406         .timesync_read_time   = igb_timesync_read_time,
 407         .timesync_write_time  = igb_timesync_write_time,
 408 };
 409
 410 /*
 411  * dev_ops for virtual function, bare necessities for basic vf
 412  * operation have been implemented
 413  */
 414 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 415         .dev_configure        = igbvf_dev_configure,
 416         .dev_start            = igbvf_dev_start,
 417         .dev_stop             = igbvf_dev_stop,
 418         .dev_close            = igbvf_dev_close,
 419         .promiscuous_enable   = igbvf_promiscuous_enable,
 420         .promiscuous_disable  = igbvf_promiscuous_disable,
 421         .allmulticast_enable  = igbvf_allmulticast_enable,
 422         .allmulticast_disable = igbvf_allmulticast_disable,
 423         .link_update          = eth_igb_link_update,
 424         .stats_get            = eth_igbvf_stats_get,
 425         .xstats_get           = eth_igbvf_xstats_get,
 426         .xstats_get_names     = eth_igbvf_xstats_get_names,
 427         .stats_reset          = eth_igbvf_stats_reset,
 428         .xstats_reset         = eth_igbvf_stats_reset,
 429         .vlan_filter_set      = igbvf_vlan_filter_set,
 430         .dev_infos_get        = eth_igbvf_infos_get,
 431         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 432         .rx_queue_setup       = eth_igb_rx_queue_setup,
 433         .rx_queue_release     = eth_igb_rx_queue_release,
 434         .tx_queue_setup       = eth_igb_tx_queue_setup,
 435         .tx_queue_release     = eth_igb_tx_queue_release,
 436         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 437         .rxq_info_get         = igb_rxq_info_get,
 438         .txq_info_get         = igb_txq_info_get,
 439         .mac_addr_set         = igbvf_default_mac_addr_set,
 440         .get_reg              = igbvf_get_regs,
 441 };
 442
 443 /* store statistics names and its offset in stats structure */
 444 struct rte_igb_xstats_name_off {
 445         char name[RTE_ETH_XSTATS_NAME_SIZE];
 446         unsigned offset;
 447 };
 448
 449 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 450         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 451         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 452         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 453         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 454         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 455         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 456         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 457                 ecol)},
 458         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 459         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 460         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 461         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 462         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 463         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 464         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 465         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 466         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 467         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 468         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 469                 fcruc)},
 470         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 471         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 472         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 473         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 474         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 475                 prc1023)},
 476         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 477                 prc1522)},
 478         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 479         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 480         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 481         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 482         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 483         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 484         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 485         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 486         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 487         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 488         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 489         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 490         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 491         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 492         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 493         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 494         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 495         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 496                 ptc1023)},
 497         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 498                 ptc1522)},
 499         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 500         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 501         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 502         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 503         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 504         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 505         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 506
 507         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 508 };
 509
 510 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 511                 sizeof(rte_igb_stats_strings[0]))
 512
 513 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 514         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 515         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 516         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 517         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 518         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 519 };
 520
 521 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 522                 sizeof(rte_igbvf_stats_strings[0]))
 523
 524
 525 static inline void
 526 igb_intr_enable(struct rte_eth_dev *dev)
 527 {
 528         struct e1000_interrupt *intr =
 529                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 530         struct e1000_hw *hw =
 531                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 532
 533         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 534         E1000_WRITE_FLUSH(hw);
 535 }
 536
 537 static void
 538 igb_intr_disable(struct e1000_hw *hw)
 539 {
 540         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 541         E1000_WRITE_FLUSH(hw);
 542 }
 543
 544 static inline void
 545 igbvf_intr_enable(struct rte_eth_dev *dev)
 546 {
 547         struct e1000_hw *hw =
 548                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 549
 550         /* only for mailbox */
 551         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 552         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 553         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 554         E1000_WRITE_FLUSH(hw);
 555 }
 556
 557 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 558 static void
 559 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 560 {
 561         uint32_t tmp = 0;
 562
 563         /* mailbox */
 564         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 565         tmp |= E1000_VTIVAR_VALID;
 566         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 567 }
 568
 569 static void
 570 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 571 {
 572         struct e1000_hw *hw =
 573                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 574
 575         /* Configure VF other cause ivar */
 576         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 577 }
 578
 579 static inline int32_t
 580 igb_pf_reset_hw(struct e1000_hw *hw)
 581 {
 582         uint32_t ctrl_ext;
 583         int32_t status;
 584
 585         status = e1000_reset_hw(hw);
 586
 587         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 588         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 589         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 590         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 591         E1000_WRITE_FLUSH(hw);
 592
 593         return status;
 594 }
 595
 596 static void
 597 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 598 {
 599         struct e1000_hw *hw =
 600                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 601
 602
 603         hw->vendor_id = pci_dev->id.vendor_id;
 604         hw->device_id = pci_dev->id.device_id;
 605         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 606         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 607
 608         e1000_set_mac_type(hw);
 609
 610         /* need to check if it is a vf device below */
 611 }
 612
 613 static int
 614 igb_reset_swfw_lock(struct e1000_hw *hw)
 615 {
 616         int ret_val;
 617
 618         /*
 619          * Do mac ops initialization manually here, since we will need
 620          * some function pointers set by this call.
 621          */
 622         ret_val = e1000_init_mac_params(hw);
 623         if (ret_val)
 624                 return ret_val;
 625
 626         /*
 627          * SMBI lock should not fail in this early stage. If this is the case,
 628          * it is due to an improper exit of the application.
 629          * So force the release of the faulty lock.
 630          */
 631         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 632                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 633         }
 634         e1000_put_hw_semaphore_generic(hw);
 635
 636         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 637                 uint16_t mask;
 638
 639                 /*
 640                  * Phy lock should not fail in this early stage. If this is the case,
 641                  * it is due to an improper exit of the application.
 642                  * So force the release of the faulty lock.
 643                  */
 644                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 645                 if (hw->bus.func > E1000_FUNC_1)
 646                         mask <<= 2;
 647                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 648                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 649                                     hw->bus.func);
 650                 }
 651                 hw->mac.ops.release_swfw_sync(hw, mask);
 652
 653                 /*
 654                  * This one is more tricky since it is common to all ports; but
 655                  * swfw_sync retries last long enough (1s) to be almost sure that if
 656                  * lock can not be taken it is due to an improper lock of the
 657                  * semaphore.
 658                  */
 659                 mask = E1000_SWFW_EEP_SM;
 660                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 661                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 662                 }
 663                 hw->mac.ops.release_swfw_sync(hw, mask);
 664         }
 665
 666         return E1000_SUCCESS;
 667 }
 668
 669 /* Remove all ntuple filters of the device */
 670 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 671 {
 672         struct e1000_filter_info *filter_info =
 673                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 674         struct e1000_5tuple_filter *p_5tuple;
 675         struct e1000_2tuple_filter *p_2tuple;
 676
 677         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 678                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 679                         p_5tuple, entries);
 680                         rte_free(p_5tuple);
 681         }
 682         filter_info->fivetuple_mask = 0;
 683         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 684                 TAILQ_REMOVE(&filter_info->twotuple_list,
 685                         p_2tuple, entries);
 686                         rte_free(p_2tuple);
 687         }
 688         filter_info->twotuple_mask = 0;
 689
 690         return 0;
 691 }
 692
 693 /* Remove all flex filters of the device */
 694 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 695 {
 696         struct e1000_filter_info *filter_info =
 697                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 698         struct e1000_flex_filter *p_flex;
 699
 700         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 701                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 702                 rte_free(p_flex);
 703         }
 704         filter_info->flex_mask = 0;
 705
 706         return 0;
 707 }
 708
 709 static int
 710 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 711 {
 712         int error = 0;
 713         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 714         struct e1000_hw *hw =
 715                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 716         struct e1000_vfta * shadow_vfta =
 717                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 718         struct e1000_filter_info *filter_info =
 719                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 720         struct e1000_adapter *adapter =
 721                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 722
 723         uint32_t ctrl_ext;
 724
 725         eth_dev->dev_ops = &eth_igb_ops;
 726         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 727         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 728         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 729
 730         /* for secondary processes, we don't initialise any further as primary
 731          * has already done this work. Only check we don't need a different
 732          * RX function */
 733         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 734                 if (eth_dev->data->scattered_rx)
 735                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 736                 return 0;
 737         }
 738
 739         rte_eth_copy_pci_info(eth_dev, pci_dev);
 740
 741         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 742
 743         igb_identify_hardware(eth_dev, pci_dev);
 744         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 745                 error = -EIO;
 746                 goto err_late;
 747         }
 748
 749         e1000_get_bus_info(hw);
 750
 751         /* Reset any pending lock */
 752         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 753                 error = -EIO;
 754                 goto err_late;
 755         }
 756
 757         /* Finish initialization */
 758         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 759                 error = -EIO;
 760                 goto err_late;
 761         }
 762
 763         hw->mac.autoneg = 1;
 764         hw->phy.autoneg_wait_to_complete = 0;
 765         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 766
 767         /* Copper options */
 768         if (hw->phy.media_type == e1000_media_type_copper) {
 769                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 770                 hw->phy.disable_polarity_correction = 0;
 771                 hw->phy.ms_type = e1000_ms_hw_default;
 772         }
 773
 774         /*
 775          * Start from a known state, this is important in reading the nvm
 776          * and mac from that.
 777          */
 778         igb_pf_reset_hw(hw);
 779
 780         /* Make sure we have a good EEPROM before we read from it */
 781         if (e1000_validate_nvm_checksum(hw) < 0) {
 782                 /*
 783                  * Some PCI-E parts fail the first check due to
 784                  * the link being in sleep state, call it again,
 785                  * if it fails a second time its a real issue.
 786                  */
 787                 if (e1000_validate_nvm_checksum(hw) < 0) {
 788                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 789                         error = -EIO;
 790                         goto err_late;
 791                 }
 792         }
 793
 794         /* Read the permanent MAC address out of the EEPROM */
 795         if (e1000_read_mac_addr(hw) != 0) {
 796                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 797                 error = -EIO;
 798                 goto err_late;
 799         }
 800
 801         /* Allocate memory for storing MAC addresses */
 802         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 803                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 804         if (eth_dev->data->mac_addrs == NULL) {
 805                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 806                                                 "store MAC addresses",
 807                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 808                 error = -ENOMEM;
 809                 goto err_late;
 810         }
 811
 812         /* Copy the permanent MAC address */
 813         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 814
 815         /* initialize the vfta */
 816         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 817
 818         /* Now initialize the hardware */
 819         if (igb_hardware_init(hw) != 0) {
 820                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 821                 rte_free(eth_dev->data->mac_addrs);
 822                 eth_dev->data->mac_addrs = NULL;
 823                 error = -ENODEV;
 824                 goto err_late;
 825         }
 826         hw->mac.get_link_status = 1;
 827         adapter->stopped = 0;
 828
 829         /* Indicate SOL/IDER usage */
 830         if (e1000_check_reset_block(hw) < 0) {
 831                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 832                                         "SOL/IDER session");
 833         }
 834
 835         /* initialize PF if max_vfs not zero */
 836         igb_pf_host_init(eth_dev);
 837
 838         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 839         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 840         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 841         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 842         E1000_WRITE_FLUSH(hw);
 843
 844         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 845                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 846                      pci_dev->id.device_id);
 847
 848         rte_intr_callback_register(&pci_dev->intr_handle,
 849                                    eth_igb_interrupt_handler,
 850                                    (void *)eth_dev);
 851
 852         /* enable uio/vfio intr/eventfd mapping */
 853         rte_intr_enable(&pci_dev->intr_handle);
 854
 855         /* enable support intr */
 856         igb_intr_enable(eth_dev);
 857
 858         /* initialize filter info */
 859         memset(filter_info, 0,
 860                sizeof(struct e1000_filter_info));
 861
 862         TAILQ_INIT(&filter_info->flex_list);
 863         TAILQ_INIT(&filter_info->twotuple_list);
 864         TAILQ_INIT(&filter_info->fivetuple_list);
 865
 866         TAILQ_INIT(&igb_filter_ntuple_list);
 867         TAILQ_INIT(&igb_filter_ethertype_list);
 868         TAILQ_INIT(&igb_filter_syn_list);
 869         TAILQ_INIT(&igb_filter_flex_list);
 870         TAILQ_INIT(&igb_filter_rss_list);
 871         TAILQ_INIT(&igb_flow_list);
 872
 873         return 0;
 874
 875 err_late:
 876         igb_hw_control_release(hw);
 877
 878         return error;
 879 }
 880
 881 static int
 882 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 883 {
 884         struct rte_pci_device *pci_dev;
 885         struct rte_intr_handle *intr_handle;
 886         struct e1000_hw *hw;
 887         struct e1000_adapter *adapter =
 888                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 889         struct e1000_filter_info *filter_info =
 890                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 891
 892         PMD_INIT_FUNC_TRACE();
 893
 894         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 895                 return -EPERM;
 896
 897         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 898         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 899         intr_handle = &pci_dev->intr_handle;
 900
 901         if (adapter->stopped == 0)
 902                 eth_igb_close(eth_dev);
 903
 904         eth_dev->dev_ops = NULL;
 905         eth_dev->rx_pkt_burst = NULL;
 906         eth_dev->tx_pkt_burst = NULL;
 907
 908         /* Reset any pending lock */
 909         igb_reset_swfw_lock(hw);
 910
 911         rte_free(eth_dev->data->mac_addrs);
 912         eth_dev->data->mac_addrs = NULL;
 913
 914         /* uninitialize PF if max_vfs not zero */
 915         igb_pf_host_uninit(eth_dev);
 916
 917         /* disable uio intr before callback unregister */
 918         rte_intr_disable(intr_handle);
 919         rte_intr_callback_unregister(intr_handle,
 920                                      eth_igb_interrupt_handler, eth_dev);
 921
 922         /* clear the SYN filter info */
 923         filter_info->syn_info = 0;
 924
 925         /* clear the ethertype filters info */
 926         filter_info->ethertype_mask = 0;
 927         memset(filter_info->ethertype_filters, 0,
 928                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
 929
 930         /* clear the rss filter info */
 931         memset(&filter_info->rss_info, 0,
 932                 sizeof(struct igb_rte_flow_rss_conf));
 933
 934         /* remove all ntuple filters of the device */
 935         igb_ntuple_filter_uninit(eth_dev);
 936
 937         /* remove all flex filters of the device */
 938         igb_flex_filter_uninit(eth_dev);
 939
 940         /* clear all the filters list */
 941         igb_filterlist_flush(eth_dev);
 942
 943         return 0;
 944 }
 945
 946 /*
 947  * Virtual Function device init
 948  */
 949 static int
 950 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 951 {
 952         struct rte_pci_device *pci_dev;
 953         struct rte_intr_handle *intr_handle;
 954         struct e1000_adapter *adapter =
 955                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 956         struct e1000_hw *hw =
 957                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 958         int diag;
 959         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 960
 961         PMD_INIT_FUNC_TRACE();
 962
 963         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 964         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 965         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 966         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 967
 968         /* for secondary processes, we don't initialise any further as primary
 969          * has already done this work. Only check we don't need a different
 970          * RX function */
 971         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 972                 if (eth_dev->data->scattered_rx)
 973                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 974                 return 0;
 975         }
 976
 977         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 978         rte_eth_copy_pci_info(eth_dev, pci_dev);
 979
 980         hw->device_id = pci_dev->id.device_id;
 981         hw->vendor_id = pci_dev->id.vendor_id;
 982         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 983         adapter->stopped = 0;
 984
 985         /* Initialize the shared code (base driver) */
 986         diag = e1000_setup_init_funcs(hw, TRUE);
 987         if (diag != 0) {
 988                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 989                         diag);
 990                 return -EIO;
 991         }
 992
 993         /* init_mailbox_params */
 994         hw->mbx.ops.init_params(hw);
 995
 996         /* Disable the interrupts for VF */
 997         igbvf_intr_disable(hw);
 998
 999         diag = hw->mac.ops.reset_hw(hw);
1000
1001         /* Allocate memory for storing MAC addresses */
1002         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1003                 hw->mac.rar_entry_count, 0);
1004         if (eth_dev->data->mac_addrs == NULL) {
1005                 PMD_INIT_LOG(ERR,
1006                         "Failed to allocate %d bytes needed to store MAC "
1007                         "addresses",
1008                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1009                 return -ENOMEM;
1010         }
1011
1012         /* Generate a random MAC address, if none was assigned by PF. */
1013         if (is_zero_ether_addr(perm_addr)) {
1014                 eth_random_addr(perm_addr->addr_bytes);
1015                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1016                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1017                              "%02x:%02x:%02x:%02x:%02x:%02x",
1018                              perm_addr->addr_bytes[0],
1019                              perm_addr->addr_bytes[1],
1020                              perm_addr->addr_bytes[2],
1021                              perm_addr->addr_bytes[3],
1022                              perm_addr->addr_bytes[4],
1023                              perm_addr->addr_bytes[5]);
1024         }
1025
1026         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1027         if (diag) {
1028                 rte_free(eth_dev->data->mac_addrs);
1029                 eth_dev->data->mac_addrs = NULL;
1030                 return diag;
1031         }
1032         /* Copy the permanent MAC address */
1033         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1034                         &eth_dev->data->mac_addrs[0]);
1035
1036         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1037                      "mac.type=%s",
1038                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1039                      pci_dev->id.device_id, "igb_mac_82576_vf");
1040
1041         intr_handle = &pci_dev->intr_handle;
1042         rte_intr_callback_register(intr_handle,
1043                                    eth_igbvf_interrupt_handler, eth_dev);
1044
1045         return 0;
1046 }
1047
1048 static int
1049 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1050 {
1051         struct e1000_adapter *adapter =
1052                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1053         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1054
1055         PMD_INIT_FUNC_TRACE();
1056
1057         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1058                 return -EPERM;
1059
1060         if (adapter->stopped == 0)
1061                 igbvf_dev_close(eth_dev);
1062
1063         eth_dev->dev_ops = NULL;
1064         eth_dev->rx_pkt_burst = NULL;
1065         eth_dev->tx_pkt_burst = NULL;
1066
1067         rte_free(eth_dev->data->mac_addrs);
1068         eth_dev->data->mac_addrs = NULL;
1069
1070         /* disable uio intr before callback unregister */
1071         rte_intr_disable(&pci_dev->intr_handle);
1072         rte_intr_callback_unregister(&pci_dev->intr_handle,
1073                                      eth_igbvf_interrupt_handler,
1074                                      (void *)eth_dev);
1075
1076         return 0;
1077 }
1078
1079 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1080         struct rte_pci_device *pci_dev)
1081 {
1082         return rte_eth_dev_pci_generic_probe(pci_dev,
1083                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1084 }
1085
1086 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1087 {
1088         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1089 }
1090
1091 static struct rte_pci_driver rte_igb_pmd = {
1092         .id_table = pci_id_igb_map,
1093         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1094                      RTE_PCI_DRV_IOVA_AS_VA,
1095         .probe = eth_igb_pci_probe,
1096         .remove = eth_igb_pci_remove,
1097 };
1098
1099
1100 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1101         struct rte_pci_device *pci_dev)
1102 {
1103         return rte_eth_dev_pci_generic_probe(pci_dev,
1104                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1105 }
1106
1107 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1108 {
1109         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1110 }
1111
1112 /*
1113  * virtual function driver struct
1114  */
1115 static struct rte_pci_driver rte_igbvf_pmd = {
1116         .id_table = pci_id_igbvf_map,
1117         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1118         .probe = eth_igbvf_pci_probe,
1119         .remove = eth_igbvf_pci_remove,
1120 };
1121
1122 static void
1123 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1124 {
1125         struct e1000_hw *hw =
1126                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1127         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1128         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1129         rctl |= E1000_RCTL_VFE;
1130         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1131 }
1132
1133 static int
1134 igb_check_mq_mode(struct rte_eth_dev *dev)
1135 {
1136         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1137         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1138         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1139         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1140
1141         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1142             tx_mq_mode == ETH_MQ_TX_DCB ||
1143             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1144                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1145                 return -EINVAL;
1146         }
1147         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1148                 /* Check multi-queue mode.
1149                  * To no break software we accept ETH_MQ_RX_NONE as this might
1150                  * be used to turn off VLAN filter.
1151                  */
1152
1153                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1154                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1155                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1156                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1157                 } else {
1158                         /* Only support one queue on VFs.
1159                          * RSS together with SRIOV is not supported.
1160                          */
1161                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1162                                         " wrong mq_mode rx %d.",
1163                                         rx_mq_mode);
1164                         return -EINVAL;
1165                 }
1166                 /* TX mode is not used here, so mode might be ignored.*/
1167                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1168                         /* SRIOV only works in VMDq enable mode */
1169                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1170                                         " TX mode %d is not supported. "
1171                                         " Driver will behave as %d mode.",
1172                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1173                 }
1174
1175                 /* check valid queue number */
1176                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1177                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1178                                         " only support one queue on VFs.");
1179                         return -EINVAL;
1180                 }
1181         } else {
1182                 /* To no break software that set invalid mode, only display
1183                  * warning if invalid mode is used.
1184                  */
1185                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1186                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1187                     rx_mq_mode != ETH_MQ_RX_RSS) {
1188                         /* RSS together with VMDq not supported*/
1189                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1190                                      rx_mq_mode);
1191                         return -EINVAL;
1192                 }
1193
1194                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1195                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1196                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1197                                         " Due to txmode is meaningless in this"
1198                                         " driver, just ignore.",
1199                                         tx_mq_mode);
1200                 }
1201         }
1202         return 0;
1203 }
1204
1205 static int
1206 eth_igb_configure(struct rte_eth_dev *dev)
1207 {
1208         struct e1000_interrupt *intr =
1209                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1210         int ret;
1211
1212         PMD_INIT_FUNC_TRACE();
1213
1214         /* multipe queue mode checking */
1215         ret  = igb_check_mq_mode(dev);
1216         if (ret != 0) {
1217                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1218                             ret);
1219                 return ret;
1220         }
1221
1222         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1223         PMD_INIT_FUNC_TRACE();
1224
1225         return 0;
1226 }
1227
1228 static void
1229 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1230                      bool enable)
1231 {
1232         struct e1000_hw *hw =
1233                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1234         uint32_t tctl, rctl;
1235
1236         tctl = E1000_READ_REG(hw, E1000_TCTL);
1237         rctl = E1000_READ_REG(hw, E1000_RCTL);
1238
1239         if (enable) {
1240                 /* enable Tx/Rx */
1241                 tctl |= E1000_TCTL_EN;
1242                 rctl |= E1000_RCTL_EN;
1243         } else {
1244                 /* disable Tx/Rx */
1245                 tctl &= ~E1000_TCTL_EN;
1246                 rctl &= ~E1000_RCTL_EN;
1247         }
1248         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1249         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1250         E1000_WRITE_FLUSH(hw);
1251 }
1252
1253 static int
1254 eth_igb_start(struct rte_eth_dev *dev)
1255 {
1256         struct e1000_hw *hw =
1257                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1258         struct e1000_adapter *adapter =
1259                 E1000_DEV_PRIVATE(dev->data->dev_private);
1260         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1261         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1262         int ret, mask;
1263         uint32_t intr_vector = 0;
1264         uint32_t ctrl_ext;
1265         uint32_t *speeds;
1266         int num_speeds;
1267         bool autoneg;
1268
1269         PMD_INIT_FUNC_TRACE();
1270
1271         /* disable uio/vfio intr/eventfd mapping */
1272         rte_intr_disable(intr_handle);
1273
1274         /* Power up the phy. Needed to make the link go Up */
1275         eth_igb_dev_set_link_up(dev);
1276
1277         /*
1278          * Packet Buffer Allocation (PBA)
1279          * Writing PBA sets the receive portion of the buffer
1280          * the remainder is used for the transmit buffer.
1281          */
1282         if (hw->mac.type == e1000_82575) {
1283                 uint32_t pba;
1284
1285                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1286                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1287         }
1288
1289         /* Put the address into the Receive Address Array */
1290         e1000_rar_set(hw, hw->mac.addr, 0);
1291
1292         /* Initialize the hardware */
1293         if (igb_hardware_init(hw)) {
1294                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1295                 return -EIO;
1296         }
1297         adapter->stopped = 0;
1298
1299         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1300
1301         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1302         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1303         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1304         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1305         E1000_WRITE_FLUSH(hw);
1306
1307         /* configure PF module if SRIOV enabled */
1308         igb_pf_host_configure(dev);
1309
1310         /* check and configure queue intr-vector mapping */
1311         if ((rte_intr_cap_multiple(intr_handle) ||
1312              !RTE_ETH_DEV_SRIOV(dev).active) &&
1313             dev->data->dev_conf.intr_conf.rxq != 0) {
1314                 intr_vector = dev->data->nb_rx_queues;
1315                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1316                         return -1;
1317         }
1318
1319         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1320                 intr_handle->intr_vec =
1321                         rte_zmalloc("intr_vec",
1322                                     dev->data->nb_rx_queues * sizeof(int), 0);
1323                 if (intr_handle->intr_vec == NULL) {
1324                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1325                                      " intr_vec", dev->data->nb_rx_queues);
1326                         return -ENOMEM;
1327                 }
1328         }
1329
1330         /* confiugre msix for rx interrupt */
1331         eth_igb_configure_msix_intr(dev);
1332
1333         /* Configure for OS presence */
1334         igb_init_manageability(hw);
1335
1336         eth_igb_tx_init(dev);
1337
1338         /* This can fail when allocating mbufs for descriptor rings */
1339         ret = eth_igb_rx_init(dev);
1340         if (ret) {
1341                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1342                 igb_dev_clear_queues(dev);
1343                 return ret;
1344         }
1345
1346         e1000_clear_hw_cntrs_base_generic(hw);
1347
1348         /*
1349          * VLAN Offload Settings
1350          */
1351         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1352                         ETH_VLAN_EXTEND_MASK;
1353         ret = eth_igb_vlan_offload_set(dev, mask);
1354         if (ret) {
1355                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1356                 igb_dev_clear_queues(dev);
1357                 return ret;
1358         }
1359
1360         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1361                 /* Enable VLAN filter since VMDq always use VLAN filter */
1362                 igb_vmdq_vlan_hw_filter_enable(dev);
1363         }
1364
1365         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1366                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1367                 (hw->mac.type == e1000_i211)) {
1368                 /* Configure EITR with the maximum possible value (0xFFFF) */
1369                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1370         }
1371
1372         /* Setup link speed and duplex */
1373         speeds = &dev->data->dev_conf.link_speeds;
1374         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1375                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1376                 hw->mac.autoneg = 1;
1377         } else {
1378                 num_speeds = 0;
1379                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1380
1381                 /* Reset */
1382                 hw->phy.autoneg_advertised = 0;
1383
1384                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1385                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1386                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1387                         num_speeds = -1;
1388                         goto error_invalid_config;
1389                 }
1390                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1391                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1392                         num_speeds++;
1393                 }
1394                 if (*speeds & ETH_LINK_SPEED_10M) {
1395                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1396                         num_speeds++;
1397                 }
1398                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1399                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1400                         num_speeds++;
1401                 }
1402                 if (*speeds & ETH_LINK_SPEED_100M) {
1403                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1404                         num_speeds++;
1405                 }
1406                 if (*speeds & ETH_LINK_SPEED_1G) {
1407                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1408                         num_speeds++;
1409                 }
1410                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1411                         goto error_invalid_config;
1412
1413                 /* Set/reset the mac.autoneg based on the link speed,
1414                  * fixed or not
1415                  */
1416                 if (!autoneg) {
1417                         hw->mac.autoneg = 0;
1418                         hw->mac.forced_speed_duplex =
1419                                         hw->phy.autoneg_advertised;
1420                 } else {
1421                         hw->mac.autoneg = 1;
1422                 }
1423         }
1424
1425         e1000_setup_link(hw);
1426
1427         if (rte_intr_allow_others(intr_handle)) {
1428                 /* check if lsc interrupt is enabled */
1429                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1430                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1431                 else
1432                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1433         } else {
1434                 rte_intr_callback_unregister(intr_handle,
1435                                              eth_igb_interrupt_handler,
1436                                              (void *)dev);
1437                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1438                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1439                                      " no intr multiplex");
1440         }
1441
1442         /* check if rxq interrupt is enabled */
1443         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1444             rte_intr_dp_is_en(intr_handle))
1445                 eth_igb_rxq_interrupt_setup(dev);
1446
1447         /* enable uio/vfio intr/eventfd mapping */
1448         rte_intr_enable(intr_handle);
1449
1450         /* resume enabled intr since hw reset */
1451         igb_intr_enable(dev);
1452
1453         /* restore all types filter */
1454         igb_filter_restore(dev);
1455
1456         eth_igb_rxtx_control(dev, true);
1457         eth_igb_link_update(dev, 0);
1458
1459         PMD_INIT_LOG(DEBUG, "<<");
1460
1461         return 0;
1462
1463 error_invalid_config:
1464         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1465                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1466         igb_dev_clear_queues(dev);
1467         return -EINVAL;
1468 }
1469
1470 /*********************************************************************
1471  *
1472  *  This routine disables all traffic on the adapter by issuing a
1473  *  global reset on the MAC.
1474  *
1475  **********************************************************************/
1476 static void
1477 eth_igb_stop(struct rte_eth_dev *dev)
1478 {
1479         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1480         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1481         struct rte_eth_link link;
1482         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1483
1484         eth_igb_rxtx_control(dev, false);
1485
1486         igb_intr_disable(hw);
1487
1488         /* disable intr eventfd mapping */
1489         rte_intr_disable(intr_handle);
1490
1491         igb_pf_reset_hw(hw);
1492         E1000_WRITE_REG(hw, E1000_WUC, 0);
1493
1494         /* Set bit for Go Link disconnect */
1495         if (hw->mac.type >= e1000_82580) {
1496                 uint32_t phpm_reg;
1497
1498                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1499                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1500                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1501         }
1502
1503         /* Power down the phy. Needed to make the link go Down */
1504         eth_igb_dev_set_link_down(dev);
1505
1506         igb_dev_clear_queues(dev);
1507
1508         /* clear the recorded link status */
1509         memset(&link, 0, sizeof(link));
1510         rte_eth_linkstatus_set(dev, &link);
1511
1512         if (!rte_intr_allow_others(intr_handle))
1513                 /* resume to the default handler */
1514                 rte_intr_callback_register(intr_handle,
1515                                            eth_igb_interrupt_handler,
1516                                            (void *)dev);
1517
1518         /* Clean datapath event and queue/vec mapping */
1519         rte_intr_efd_disable(intr_handle);
1520         if (intr_handle->intr_vec != NULL) {
1521                 rte_free(intr_handle->intr_vec);
1522                 intr_handle->intr_vec = NULL;
1523         }
1524 }
1525
1526 static int
1527 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1528 {
1529         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1530
1531         if (hw->phy.media_type == e1000_media_type_copper)
1532                 e1000_power_up_phy(hw);
1533         else
1534                 e1000_power_up_fiber_serdes_link(hw);
1535
1536         return 0;
1537 }
1538
1539 static int
1540 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1541 {
1542         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1543
1544         if (hw->phy.media_type == e1000_media_type_copper)
1545                 e1000_power_down_phy(hw);
1546         else
1547                 e1000_shutdown_fiber_serdes_link(hw);
1548
1549         return 0;
1550 }
1551
1552 static void
1553 eth_igb_close(struct rte_eth_dev *dev)
1554 {
1555         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1556         struct e1000_adapter *adapter =
1557                 E1000_DEV_PRIVATE(dev->data->dev_private);
1558         struct rte_eth_link link;
1559         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1560         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1561
1562         eth_igb_stop(dev);
1563         adapter->stopped = 1;
1564
1565         e1000_phy_hw_reset(hw);
1566         igb_release_manageability(hw);
1567         igb_hw_control_release(hw);
1568
1569         /* Clear bit for Go Link disconnect */
1570         if (hw->mac.type >= e1000_82580) {
1571                 uint32_t phpm_reg;
1572
1573                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1574                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1575                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1576         }
1577
1578         igb_dev_free_queues(dev);
1579
1580         if (intr_handle->intr_vec) {
1581                 rte_free(intr_handle->intr_vec);
1582                 intr_handle->intr_vec = NULL;
1583         }
1584
1585         memset(&link, 0, sizeof(link));
1586         rte_eth_linkstatus_set(dev, &link);
1587 }
1588
1589 static int
1590 igb_get_rx_buffer_size(struct e1000_hw *hw)
1591 {
1592         uint32_t rx_buf_size;
1593         if (hw->mac.type == e1000_82576) {
1594                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1595         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1596                 /* PBS needs to be translated according to a lookup table */
1597                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1598                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1599                 rx_buf_size = (rx_buf_size << 10);
1600         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1601                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1602         } else {
1603                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1604         }
1605
1606         return rx_buf_size;
1607 }
1608
1609 /*********************************************************************
1610  *
1611  *  Initialize the hardware
1612  *
1613  **********************************************************************/
1614 static int
1615 igb_hardware_init(struct e1000_hw *hw)
1616 {
1617         uint32_t rx_buf_size;
1618         int diag;
1619
1620         /* Let the firmware know the OS is in control */
1621         igb_hw_control_acquire(hw);
1622
1623         /*
1624          * These parameters control the automatic generation (Tx) and
1625          * response (Rx) to Ethernet PAUSE frames.
1626          * - High water mark should allow for at least two standard size (1518)
1627          *   frames to be received after sending an XOFF.
1628          * - Low water mark works best when it is very near the high water mark.
1629          *   This allows the receiver to restart by sending XON when it has
1630          *   drained a bit. Here we use an arbitrary value of 1500 which will
1631          *   restart after one full frame is pulled from the buffer. There
1632          *   could be several smaller frames in the buffer and if so they will
1633          *   not trigger the XON until their total number reduces the buffer
1634          *   by 1500.
1635          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1636          */
1637         rx_buf_size = igb_get_rx_buffer_size(hw);
1638
1639         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1640         hw->fc.low_water = hw->fc.high_water - 1500;
1641         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1642         hw->fc.send_xon = 1;
1643
1644         /* Set Flow control, use the tunable location if sane */
1645         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1646                 hw->fc.requested_mode = igb_fc_setting;
1647         else
1648                 hw->fc.requested_mode = e1000_fc_none;
1649
1650         /* Issue a global reset */
1651         igb_pf_reset_hw(hw);
1652         E1000_WRITE_REG(hw, E1000_WUC, 0);
1653
1654         diag = e1000_init_hw(hw);
1655         if (diag < 0)
1656                 return diag;
1657
1658         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1659         e1000_get_phy_info(hw);
1660         e1000_check_for_link(hw);
1661
1662         return 0;
1663 }
1664
1665 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1666 static void
1667 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1668 {
1669         int pause_frames;
1670
1671         uint64_t old_gprc  = stats->gprc;
1672         uint64_t old_gptc  = stats->gptc;
1673         uint64_t old_tpr   = stats->tpr;
1674         uint64_t old_tpt   = stats->tpt;
1675         uint64_t old_rpthc = stats->rpthc;
1676         uint64_t old_hgptc = stats->hgptc;
1677
1678         if(hw->phy.media_type == e1000_media_type_copper ||
1679             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1680                 stats->symerrs +=
1681                     E1000_READ_REG(hw,E1000_SYMERRS);
1682                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1683         }
1684
1685         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1686         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1687         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1688         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1689
1690         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1691         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1692         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1693         stats->dc += E1000_READ_REG(hw, E1000_DC);
1694         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1695         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1696         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1697         /*
1698         ** For watchdog management we need to know if we have been
1699         ** paused during the last interval, so capture that here.
1700         */
1701         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1702         stats->xoffrxc += pause_frames;
1703         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1704         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1705         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1706         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1707         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1708         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1709         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1710         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1711         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1712         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1713         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1714         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1715
1716         /* For the 64-bit byte counters the low dword must be read first. */
1717         /* Both registers clear on the read of the high dword */
1718
1719         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1720         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1721         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1722         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1723         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1724         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1725         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1726
1727         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1728         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1729         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1730         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1731         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1732
1733         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1734         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1735
1736         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1737         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1738         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1739         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1740         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1741         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1742
1743         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1744         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1745         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1746         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1747         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1748         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1749         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1750         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1751
1752         /* Interrupt Counts */
1753
1754         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1755         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1756         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1757         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1758         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1759         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1760         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1761         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1762         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1763
1764         /* Host to Card Statistics */
1765
1766         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1767         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1768         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1769         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1770         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1771         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1772         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1773         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1774         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1775         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1776         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1777         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1778         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1779         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1780         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1781         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1782
1783         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1784         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1785         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1786         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1787         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1788         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1789 }
1790
1791 static int
1792 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1793 {
1794         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1795         struct e1000_hw_stats *stats =
1796                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1797
1798         igb_read_stats_registers(hw, stats);
1799
1800         if (rte_stats == NULL)
1801                 return -EINVAL;
1802
1803         /* Rx Errors */
1804         rte_stats->imissed = stats->mpc;
1805         rte_stats->ierrors = stats->crcerrs +
1806                              stats->rlec + stats->ruc + stats->roc +
1807                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1808
1809         /* Tx Errors */
1810         rte_stats->oerrors = stats->ecol + stats->latecol;
1811
1812         rte_stats->ipackets = stats->gprc;
1813         rte_stats->opackets = stats->gptc;
1814         rte_stats->ibytes   = stats->gorc;
1815         rte_stats->obytes   = stats->gotc;
1816         return 0;
1817 }
1818
1819 static void
1820 eth_igb_stats_reset(struct rte_eth_dev *dev)
1821 {
1822         struct e1000_hw_stats *hw_stats =
1823                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1824
1825         /* HW registers are cleared on read */
1826         eth_igb_stats_get(dev, NULL);
1827
1828         /* Reset software totals */
1829         memset(hw_stats, 0, sizeof(*hw_stats));
1830 }
1831
1832 static void
1833 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1834 {
1835         struct e1000_hw_stats *stats =
1836                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1837
1838         /* HW registers are cleared on read */
1839         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1840
1841         /* Reset software totals */
1842         memset(stats, 0, sizeof(*stats));
1843 }
1844
1845 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1846         struct rte_eth_xstat_name *xstats_names,
1847         __rte_unused unsigned int size)
1848 {
1849         unsigned i;
1850
1851         if (xstats_names == NULL)
1852                 return IGB_NB_XSTATS;
1853
1854         /* Note: limit checked in rte_eth_xstats_names() */
1855
1856         for (i = 0; i < IGB_NB_XSTATS; i++) {
1857                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1858                          "%s", rte_igb_stats_strings[i].name);
1859         }
1860
1861         return IGB_NB_XSTATS;
1862 }
1863
1864 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1865                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1866                 unsigned int limit)
1867 {
1868         unsigned int i;
1869
1870         if (!ids) {
1871                 if (xstats_names == NULL)
1872                         return IGB_NB_XSTATS;
1873
1874                 for (i = 0; i < IGB_NB_XSTATS; i++)
1875                         snprintf(xstats_names[i].name,
1876                                         sizeof(xstats_names[i].name),
1877                                         "%s", rte_igb_stats_strings[i].name);
1878
1879                 return IGB_NB_XSTATS;
1880
1881         } else {
1882                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1883
1884                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1885                                 IGB_NB_XSTATS);
1886
1887                 for (i = 0; i < limit; i++) {
1888                         if (ids[i] >= IGB_NB_XSTATS) {
1889                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1890                                 return -1;
1891                         }
1892                         strcpy(xstats_names[i].name,
1893                                         xstats_names_copy[ids[i]].name);
1894                 }
1895                 return limit;
1896         }
1897 }
1898
1899 static int
1900 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1901                    unsigned n)
1902 {
1903         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904         struct e1000_hw_stats *hw_stats =
1905                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1906         unsigned i;
1907
1908         if (n < IGB_NB_XSTATS)
1909                 return IGB_NB_XSTATS;
1910
1911         igb_read_stats_registers(hw, hw_stats);
1912
1913         /* If this is a reset xstats is NULL, and we have cleared the
1914          * registers by reading them.
1915          */
1916         if (!xstats)
1917                 return 0;
1918
1919         /* Extended stats */
1920         for (i = 0; i < IGB_NB_XSTATS; i++) {
1921                 xstats[i].id = i;
1922                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1923                         rte_igb_stats_strings[i].offset);
1924         }
1925
1926         return IGB_NB_XSTATS;
1927 }
1928
1929 static int
1930 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1931                 uint64_t *values, unsigned int n)
1932 {
1933         unsigned int i;
1934
1935         if (!ids) {
1936                 struct e1000_hw *hw =
1937                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938                 struct e1000_hw_stats *hw_stats =
1939                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1940
1941                 if (n < IGB_NB_XSTATS)
1942                         return IGB_NB_XSTATS;
1943
1944                 igb_read_stats_registers(hw, hw_stats);
1945
1946                 /* If this is a reset xstats is NULL, and we have cleared the
1947                  * registers by reading them.
1948                  */
1949                 if (!values)
1950                         return 0;
1951
1952                 /* Extended stats */
1953                 for (i = 0; i < IGB_NB_XSTATS; i++)
1954                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1955                                         rte_igb_stats_strings[i].offset);
1956
1957                 return IGB_NB_XSTATS;
1958
1959         } else {
1960                 uint64_t values_copy[IGB_NB_XSTATS];
1961
1962                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1963                                 IGB_NB_XSTATS);
1964
1965                 for (i = 0; i < n; i++) {
1966                         if (ids[i] >= IGB_NB_XSTATS) {
1967                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1968                                 return -1;
1969                         }
1970                         values[i] = values_copy[ids[i]];
1971                 }
1972                 return n;
1973         }
1974 }
1975
1976 static void
1977 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1978 {
1979         /* Good Rx packets, include VF loopback */
1980         UPDATE_VF_STAT(E1000_VFGPRC,
1981             hw_stats->last_gprc, hw_stats->gprc);
1982
1983         /* Good Rx octets, include VF loopback */
1984         UPDATE_VF_STAT(E1000_VFGORC,
1985             hw_stats->last_gorc, hw_stats->gorc);
1986
1987         /* Good Tx packets, include VF loopback */
1988         UPDATE_VF_STAT(E1000_VFGPTC,
1989             hw_stats->last_gptc, hw_stats->gptc);
1990
1991         /* Good Tx octets, include VF loopback */
1992         UPDATE_VF_STAT(E1000_VFGOTC,
1993             hw_stats->last_gotc, hw_stats->gotc);
1994
1995         /* Rx Multicst packets */
1996         UPDATE_VF_STAT(E1000_VFMPRC,
1997             hw_stats->last_mprc, hw_stats->mprc);
1998
1999         /* Good Rx loopback packets */
2000         UPDATE_VF_STAT(E1000_VFGPRLBC,
2001             hw_stats->last_gprlbc, hw_stats->gprlbc);
2002
2003         /* Good Rx loopback octets */
2004         UPDATE_VF_STAT(E1000_VFGORLBC,
2005             hw_stats->last_gorlbc, hw_stats->gorlbc);
2006
2007         /* Good Tx loopback packets */
2008         UPDATE_VF_STAT(E1000_VFGPTLBC,
2009             hw_stats->last_gptlbc, hw_stats->gptlbc);
2010
2011         /* Good Tx loopback octets */
2012         UPDATE_VF_STAT(E1000_VFGOTLBC,
2013             hw_stats->last_gotlbc, hw_stats->gotlbc);
2014 }
2015
2016 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2017                                      struct rte_eth_xstat_name *xstats_names,
2018                                      __rte_unused unsigned limit)
2019 {
2020         unsigned i;
2021
2022         if (xstats_names != NULL)
2023                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2024                         snprintf(xstats_names[i].name,
2025                                 sizeof(xstats_names[i].name), "%s",
2026                                 rte_igbvf_stats_strings[i].name);
2027                 }
2028         return IGBVF_NB_XSTATS;
2029 }
2030
2031 static int
2032 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2033                      unsigned n)
2034 {
2035         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2036         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2037                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2038         unsigned i;
2039
2040         if (n < IGBVF_NB_XSTATS)
2041                 return IGBVF_NB_XSTATS;
2042
2043         igbvf_read_stats_registers(hw, hw_stats);
2044
2045         if (!xstats)
2046                 return 0;
2047
2048         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2049                 xstats[i].id = i;
2050                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2051                         rte_igbvf_stats_strings[i].offset);
2052         }
2053
2054         return IGBVF_NB_XSTATS;
2055 }
2056
2057 static int
2058 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2059 {
2060         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2061         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2062                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2063
2064         igbvf_read_stats_registers(hw, hw_stats);
2065
2066         if (rte_stats == NULL)
2067                 return -EINVAL;
2068
2069         rte_stats->ipackets = hw_stats->gprc;
2070         rte_stats->ibytes = hw_stats->gorc;
2071         rte_stats->opackets = hw_stats->gptc;
2072         rte_stats->obytes = hw_stats->gotc;
2073         return 0;
2074 }
2075
2076 static void
2077 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2078 {
2079         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2080                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2081
2082         /* Sync HW register to the last stats */
2083         eth_igbvf_stats_get(dev, NULL);
2084
2085         /* reset HW current stats*/
2086         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2087                offsetof(struct e1000_vf_stats, gprc));
2088 }
2089
2090 static int
2091 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2092                        size_t fw_size)
2093 {
2094         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095         struct e1000_fw_version fw;
2096         int ret;
2097
2098         e1000_get_fw_version(hw, &fw);
2099
2100         switch (hw->mac.type) {
2101         case e1000_i210:
2102         case e1000_i211:
2103                 if (!(e1000_get_flash_presence_i210(hw))) {
2104                         ret = snprintf(fw_version, fw_size,
2105                                  "%2d.%2d-%d",
2106                                  fw.invm_major, fw.invm_minor,
2107                                  fw.invm_img_type);
2108                         break;
2109                 }
2110                 /* fall through */
2111         default:
2112                 /* if option rom is valid, display its version too */
2113                 if (fw.or_valid) {
2114                         ret = snprintf(fw_version, fw_size,
2115                                  "%d.%d, 0x%08x, %d.%d.%d",
2116                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2117                                  fw.or_major, fw.or_build, fw.or_patch);
2118                 /* no option rom */
2119                 } else {
2120                         if (fw.etrack_id != 0X0000) {
2121                                 ret = snprintf(fw_version, fw_size,
2122                                          "%d.%d, 0x%08x",
2123                                          fw.eep_major, fw.eep_minor,
2124                                          fw.etrack_id);
2125                         } else {
2126                                 ret = snprintf(fw_version, fw_size,
2127                                          "%d.%d.%d",
2128                                          fw.eep_major, fw.eep_minor,
2129                                          fw.eep_build);
2130                         }
2131                 }
2132                 break;
2133         }
2134
2135         ret += 1; /* add the size of '\0' */
2136         if (fw_size < (u32)ret)
2137                 return ret;
2138         else
2139                 return 0;
2140 }
2141
2142 static void
2143 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2144 {
2145         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2146
2147         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2148         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2149         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2150         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2151         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2152         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2153                                     dev_info->rx_queue_offload_capa;
2154         dev_info->tx_offload_capa =
2155                 DEV_TX_OFFLOAD_VLAN_INSERT |
2156                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2157                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2158                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2159                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2160                 DEV_TX_OFFLOAD_TCP_TSO;
2161
2162         switch (hw->mac.type) {
2163         case e1000_82575:
2164                 dev_info->max_rx_queues = 4;
2165                 dev_info->max_tx_queues = 4;
2166                 dev_info->max_vmdq_pools = 0;
2167                 break;
2168
2169         case e1000_82576:
2170                 dev_info->max_rx_queues = 16;
2171                 dev_info->max_tx_queues = 16;
2172                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2173                 dev_info->vmdq_queue_num = 16;
2174                 break;
2175
2176         case e1000_82580:
2177                 dev_info->max_rx_queues = 8;
2178                 dev_info->max_tx_queues = 8;
2179                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2180                 dev_info->vmdq_queue_num = 8;
2181                 break;
2182
2183         case e1000_i350:
2184                 dev_info->max_rx_queues = 8;
2185                 dev_info->max_tx_queues = 8;
2186                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2187                 dev_info->vmdq_queue_num = 8;
2188                 break;
2189
2190         case e1000_i354:
2191                 dev_info->max_rx_queues = 8;
2192                 dev_info->max_tx_queues = 8;
2193                 break;
2194
2195         case e1000_i210:
2196                 dev_info->max_rx_queues = 4;
2197                 dev_info->max_tx_queues = 4;
2198                 dev_info->max_vmdq_pools = 0;
2199                 break;
2200
2201         case e1000_i211:
2202                 dev_info->max_rx_queues = 2;
2203                 dev_info->max_tx_queues = 2;
2204                 dev_info->max_vmdq_pools = 0;
2205                 break;
2206
2207         default:
2208                 /* Should not happen */
2209                 break;
2210         }
2211         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2212         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2213         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2214
2215         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2216                 .rx_thresh = {
2217                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2218                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2219                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2220                 },
2221                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2222                 .rx_drop_en = 0,
2223                 .offloads = 0,
2224         };
2225
2226         dev_info->default_txconf = (struct rte_eth_txconf) {
2227                 .tx_thresh = {
2228                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2229                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2230                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2231                 },
2232                 .txq_flags = 0,
2233         };
2234
2235         dev_info->rx_desc_lim = rx_desc_lim;
2236         dev_info->tx_desc_lim = tx_desc_lim;
2237
2238         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2239                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2240                         ETH_LINK_SPEED_1G;
2241 }
2242
2243 static const uint32_t *
2244 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2245 {
2246         static const uint32_t ptypes[] = {
2247                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2248                 RTE_PTYPE_L2_ETHER,
2249                 RTE_PTYPE_L3_IPV4,
2250                 RTE_PTYPE_L3_IPV4_EXT,
2251                 RTE_PTYPE_L3_IPV6,
2252                 RTE_PTYPE_L3_IPV6_EXT,
2253                 RTE_PTYPE_L4_TCP,
2254                 RTE_PTYPE_L4_UDP,
2255                 RTE_PTYPE_L4_SCTP,
2256                 RTE_PTYPE_TUNNEL_IP,
2257                 RTE_PTYPE_INNER_L3_IPV6,
2258                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2259                 RTE_PTYPE_INNER_L4_TCP,
2260                 RTE_PTYPE_INNER_L4_UDP,
2261                 RTE_PTYPE_UNKNOWN
2262         };
2263
2264         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2265             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2266                 return ptypes;
2267         return NULL;
2268 }
2269
2270 static void
2271 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2272 {
2273         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2274
2275         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2276         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2277         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2278         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2279         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2280                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2281                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2282                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2283                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2284                                 DEV_TX_OFFLOAD_TCP_TSO;
2285         switch (hw->mac.type) {
2286         case e1000_vfadapt:
2287                 dev_info->max_rx_queues = 2;
2288                 dev_info->max_tx_queues = 2;
2289                 break;
2290         case e1000_vfadapt_i350:
2291                 dev_info->max_rx_queues = 1;
2292                 dev_info->max_tx_queues = 1;
2293                 break;
2294         default:
2295                 /* Should not happen */
2296                 break;
2297         }
2298
2299         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2300         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2301                                     dev_info->rx_queue_offload_capa;
2302
2303         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2304                 .rx_thresh = {
2305                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2306                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2307                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2308                 },
2309                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2310                 .rx_drop_en = 0,
2311                 .offloads = 0,
2312         };
2313
2314         dev_info->default_txconf = (struct rte_eth_txconf) {
2315                 .tx_thresh = {
2316                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2317                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2318                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2319                 },
2320                 .txq_flags = 0,
2321         };
2322
2323         dev_info->rx_desc_lim = rx_desc_lim;
2324         dev_info->tx_desc_lim = tx_desc_lim;
2325 }
2326
2327 /* return 0 means link status changed, -1 means not changed */
2328 static int
2329 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2330 {
2331         struct e1000_hw *hw =
2332                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2333         struct rte_eth_link link;
2334         int link_check, count;
2335
2336         link_check = 0;
2337         hw->mac.get_link_status = 1;
2338
2339         /* possible wait-to-complete in up to 9 seconds */
2340         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2341                 /* Read the real link status */
2342                 switch (hw->phy.media_type) {
2343                 case e1000_media_type_copper:
2344                         /* Do the work to read phy */
2345                         e1000_check_for_link(hw);
2346                         link_check = !hw->mac.get_link_status;
2347                         break;
2348
2349                 case e1000_media_type_fiber:
2350                         e1000_check_for_link(hw);
2351                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2352                                       E1000_STATUS_LU);
2353                         break;
2354
2355                 case e1000_media_type_internal_serdes:
2356                         e1000_check_for_link(hw);
2357                         link_check = hw->mac.serdes_has_link;
2358                         break;
2359
2360                 /* VF device is type_unknown */
2361                 case e1000_media_type_unknown:
2362                         eth_igbvf_link_update(hw);
2363                         link_check = !hw->mac.get_link_status;
2364                         break;
2365
2366                 default:
2367                         break;
2368                 }
2369                 if (link_check || wait_to_complete == 0)
2370                         break;
2371                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2372         }
2373         memset(&link, 0, sizeof(link));
2374
2375         /* Now we check if a transition has happened */
2376         if (link_check) {
2377                 uint16_t duplex, speed;
2378                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2379                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2380                                 ETH_LINK_FULL_DUPLEX :
2381                                 ETH_LINK_HALF_DUPLEX;
2382                 link.link_speed = speed;
2383                 link.link_status = ETH_LINK_UP;
2384                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2385                                 ETH_LINK_SPEED_FIXED);
2386         } else if (!link_check) {
2387                 link.link_speed = 0;
2388                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2389                 link.link_status = ETH_LINK_DOWN;
2390                 link.link_autoneg = ETH_LINK_FIXED;
2391         }
2392
2393         return rte_eth_linkstatus_set(dev, &link);
2394 }
2395
2396 /*
2397  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2398  * For ASF and Pass Through versions of f/w this means
2399  * that the driver is loaded.
2400  */
2401 static void
2402 igb_hw_control_acquire(struct e1000_hw *hw)
2403 {
2404         uint32_t ctrl_ext;
2405
2406         /* Let firmware know the driver has taken over */
2407         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2408         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2409 }
2410
2411 /*
2412  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2413  * For ASF and Pass Through versions of f/w this means that the
2414  * driver is no longer loaded.
2415  */
2416 static void
2417 igb_hw_control_release(struct e1000_hw *hw)
2418 {
2419         uint32_t ctrl_ext;
2420
2421         /* Let firmware taken over control of h/w */
2422         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2423         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2424                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2425 }
2426
2427 /*
2428  * Bit of a misnomer, what this really means is
2429  * to enable OS management of the system... aka
2430  * to disable special hardware management features.
2431  */
2432 static void
2433 igb_init_manageability(struct e1000_hw *hw)
2434 {
2435         if (e1000_enable_mng_pass_thru(hw)) {
2436                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2437                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2438
2439                 /* disable hardware interception of ARP */
2440                 manc &= ~(E1000_MANC_ARP_EN);
2441
2442                 /* enable receiving management packets to the host */
2443                 manc |= E1000_MANC_EN_MNG2HOST;
2444                 manc2h |= 1 << 5;  /* Mng Port 623 */
2445                 manc2h |= 1 << 6;  /* Mng Port 664 */
2446                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2447                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2448         }
2449 }
2450
2451 static void
2452 igb_release_manageability(struct e1000_hw *hw)
2453 {
2454         if (e1000_enable_mng_pass_thru(hw)) {
2455                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2456
2457                 manc |= E1000_MANC_ARP_EN;
2458                 manc &= ~E1000_MANC_EN_MNG2HOST;
2459
2460                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2461         }
2462 }
2463
2464 static void
2465 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2466 {
2467         struct e1000_hw *hw =
2468                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469         uint32_t rctl;
2470
2471         rctl = E1000_READ_REG(hw, E1000_RCTL);
2472         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2473         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2474 }
2475
2476 static void
2477 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2478 {
2479         struct e1000_hw *hw =
2480                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2481         uint32_t rctl;
2482
2483         rctl = E1000_READ_REG(hw, E1000_RCTL);
2484         rctl &= (~E1000_RCTL_UPE);
2485         if (dev->data->all_multicast == 1)
2486                 rctl |= E1000_RCTL_MPE;
2487         else
2488                 rctl &= (~E1000_RCTL_MPE);
2489         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2490 }
2491
2492 static void
2493 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2494 {
2495         struct e1000_hw *hw =
2496                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2497         uint32_t rctl;
2498
2499         rctl = E1000_READ_REG(hw, E1000_RCTL);
2500         rctl |= E1000_RCTL_MPE;
2501         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2502 }
2503
2504 static void
2505 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2506 {
2507         struct e1000_hw *hw =
2508                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2509         uint32_t rctl;
2510
2511         if (dev->data->promiscuous == 1)
2512                 return; /* must remain in all_multicast mode */
2513         rctl = E1000_READ_REG(hw, E1000_RCTL);
2514         rctl &= (~E1000_RCTL_MPE);
2515         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2516 }
2517
2518 static int
2519 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2520 {
2521         struct e1000_hw *hw =
2522                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523         struct e1000_vfta * shadow_vfta =
2524                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2525         uint32_t vfta;
2526         uint32_t vid_idx;
2527         uint32_t vid_bit;
2528
2529         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2530                               E1000_VFTA_ENTRY_MASK);
2531         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2532         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2533         if (on)
2534                 vfta |= vid_bit;
2535         else
2536                 vfta &= ~vid_bit;
2537         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2538
2539         /* update local VFTA copy */
2540         shadow_vfta->vfta[vid_idx] = vfta;
2541
2542         return 0;
2543 }
2544
2545 static int
2546 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2547                       enum rte_vlan_type vlan_type,
2548                       uint16_t tpid)
2549 {
2550         struct e1000_hw *hw =
2551                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2552         uint32_t reg, qinq;
2553
2554         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2555         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2556
2557         /* only outer TPID of double VLAN can be configured*/
2558         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2559                 reg = E1000_READ_REG(hw, E1000_VET);
2560                 reg = (reg & (~E1000_VET_VET_EXT)) |
2561                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2562                 E1000_WRITE_REG(hw, E1000_VET, reg);
2563
2564                 return 0;
2565         }
2566
2567         /* all other TPID values are read-only*/
2568         PMD_DRV_LOG(ERR, "Not supported");
2569
2570         return -ENOTSUP;
2571 }
2572
2573 static void
2574 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2575 {
2576         struct e1000_hw *hw =
2577                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2578         uint32_t reg;
2579
2580         /* Filter Table Disable */
2581         reg = E1000_READ_REG(hw, E1000_RCTL);
2582         reg &= ~E1000_RCTL_CFIEN;
2583         reg &= ~E1000_RCTL_VFE;
2584         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2585 }
2586
2587 static void
2588 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2589 {
2590         struct e1000_hw *hw =
2591                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2592         struct e1000_vfta * shadow_vfta =
2593                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2594         uint32_t reg;
2595         int i;
2596
2597         /* Filter Table Enable, CFI not used for packet acceptance */
2598         reg = E1000_READ_REG(hw, E1000_RCTL);
2599         reg &= ~E1000_RCTL_CFIEN;
2600         reg |= E1000_RCTL_VFE;
2601         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2602
2603         /* restore VFTA table */
2604         for (i = 0; i < IGB_VFTA_SIZE; i++)
2605                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2606 }
2607
2608 static void
2609 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2610 {
2611         struct e1000_hw *hw =
2612                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2613         uint32_t reg;
2614
2615         /* VLAN Mode Disable */
2616         reg = E1000_READ_REG(hw, E1000_CTRL);
2617         reg &= ~E1000_CTRL_VME;
2618         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2619 }
2620
2621 static void
2622 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2623 {
2624         struct e1000_hw *hw =
2625                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2626         uint32_t reg;
2627
2628         /* VLAN Mode Enable */
2629         reg = E1000_READ_REG(hw, E1000_CTRL);
2630         reg |= E1000_CTRL_VME;
2631         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2632 }
2633
2634 static void
2635 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2636 {
2637         struct e1000_hw *hw =
2638                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2639         uint32_t reg;
2640
2641         /* CTRL_EXT: Extended VLAN */
2642         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2643         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2644         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2645
2646         /* Update maximum packet length */
2647         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2648                 E1000_WRITE_REG(hw, E1000_RLPML,
2649                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2650                                                 VLAN_TAG_SIZE);
2651 }
2652
2653 static void
2654 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2655 {
2656         struct e1000_hw *hw =
2657                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2658         uint32_t reg;
2659
2660         /* CTRL_EXT: Extended VLAN */
2661         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2662         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2663         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2664
2665         /* Update maximum packet length */
2666         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2667                 E1000_WRITE_REG(hw, E1000_RLPML,
2668                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2669                                                 2 * VLAN_TAG_SIZE);
2670 }
2671
2672 static int
2673 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2674 {
2675         struct rte_eth_rxmode *rxmode;
2676
2677         rxmode = &dev->data->dev_conf.rxmode;
2678         if(mask & ETH_VLAN_STRIP_MASK){
2679                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2680                         igb_vlan_hw_strip_enable(dev);
2681                 else
2682                         igb_vlan_hw_strip_disable(dev);
2683         }
2684
2685         if(mask & ETH_VLAN_FILTER_MASK){
2686                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2687                         igb_vlan_hw_filter_enable(dev);
2688                 else
2689                         igb_vlan_hw_filter_disable(dev);
2690         }
2691
2692         if(mask & ETH_VLAN_EXTEND_MASK){
2693                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2694                         igb_vlan_hw_extend_enable(dev);
2695                 else
2696                         igb_vlan_hw_extend_disable(dev);
2697         }
2698
2699         return 0;
2700 }
2701
2702
2703 /**
2704  * It enables the interrupt mask and then enable the interrupt.
2705  *
2706  * @param dev
2707  *  Pointer to struct rte_eth_dev.
2708  * @param on
2709  *  Enable or Disable
2710  *
2711  * @return
2712  *  - On success, zero.
2713  *  - On failure, a negative value.
2714  */
2715 static int
2716 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2717 {
2718         struct e1000_interrupt *intr =
2719                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2720
2721         if (on)
2722                 intr->mask |= E1000_ICR_LSC;
2723         else
2724                 intr->mask &= ~E1000_ICR_LSC;
2725
2726         return 0;
2727 }
2728
2729 /* It clears the interrupt causes and enables the interrupt.
2730  * It will be called once only during nic initialized.
2731  *
2732  * @param dev
2733  *  Pointer to struct rte_eth_dev.
2734  *
2735  * @return
2736  *  - On success, zero.
2737  *  - On failure, a negative value.
2738  */
2739 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2740 {
2741         uint32_t mask, regval;
2742         struct e1000_hw *hw =
2743                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2744         struct rte_eth_dev_info dev_info;
2745
2746         memset(&dev_info, 0, sizeof(dev_info));
2747         eth_igb_infos_get(dev, &dev_info);
2748
2749         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2750         regval = E1000_READ_REG(hw, E1000_EIMS);
2751         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2752
2753         return 0;
2754 }
2755
2756 /*
2757  * It reads ICR and gets interrupt causes, check it and set a bit flag
2758  * to update link status.
2759  *
2760  * @param dev
2761  *  Pointer to struct rte_eth_dev.
2762  *
2763  * @return
2764  *  - On success, zero.
2765  *  - On failure, a negative value.
2766  */
2767 static int
2768 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2769 {
2770         uint32_t icr;
2771         struct e1000_hw *hw =
2772                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2773         struct e1000_interrupt *intr =
2774                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2775
2776         igb_intr_disable(hw);
2777
2778         /* read-on-clear nic registers here */
2779         icr = E1000_READ_REG(hw, E1000_ICR);
2780
2781         intr->flags = 0;
2782         if (icr & E1000_ICR_LSC) {
2783                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2784         }
2785
2786         if (icr & E1000_ICR_VMMB)
2787                 intr->flags |= E1000_FLAG_MAILBOX;
2788
2789         return 0;
2790 }
2791
2792 /*
2793  * It executes link_update after knowing an interrupt is prsent.
2794  *
2795  * @param dev
2796  *  Pointer to struct rte_eth_dev.
2797  *
2798  * @return
2799  *  - On success, zero.
2800  *  - On failure, a negative value.
2801  */
2802 static int
2803 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2804                          struct rte_intr_handle *intr_handle)
2805 {
2806         struct e1000_hw *hw =
2807                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2808         struct e1000_interrupt *intr =
2809                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2810         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2811         struct rte_eth_link link;
2812         int ret;
2813
2814         if (intr->flags & E1000_FLAG_MAILBOX) {
2815                 igb_pf_mbx_process(dev);
2816                 intr->flags &= ~E1000_FLAG_MAILBOX;
2817         }
2818
2819         igb_intr_enable(dev);
2820         rte_intr_enable(intr_handle);
2821
2822         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2823                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2824
2825                 /* set get_link_status to check register later */
2826                 hw->mac.get_link_status = 1;
2827                 ret = eth_igb_link_update(dev, 0);
2828
2829                 /* check if link has changed */
2830                 if (ret < 0)
2831                         return 0;
2832
2833                 rte_eth_linkstatus_get(dev, &link);
2834                 if (link.link_status) {
2835                         PMD_INIT_LOG(INFO,
2836                                      " Port %d: Link Up - speed %u Mbps - %s",
2837                                      dev->data->port_id,
2838                                      (unsigned)link.link_speed,
2839                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2840                                      "full-duplex" : "half-duplex");
2841                 } else {
2842                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2843                                      dev->data->port_id);
2844                 }
2845
2846                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2847                              pci_dev->addr.domain,
2848                              pci_dev->addr.bus,
2849                              pci_dev->addr.devid,
2850                              pci_dev->addr.function);
2851                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2852                                               NULL);
2853         }
2854
2855         return 0;
2856 }
2857
2858 /**
2859  * Interrupt handler which shall be registered at first.
2860  *
2861  * @param handle
2862  *  Pointer to interrupt handle.
2863  * @param param
2864  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2865  *
2866  * @return
2867  *  void
2868  */
2869 static void
2870 eth_igb_interrupt_handler(void *param)
2871 {
2872         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2873
2874         eth_igb_interrupt_get_status(dev);
2875         eth_igb_interrupt_action(dev, dev->intr_handle);
2876 }
2877
2878 static int
2879 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2880 {
2881         uint32_t eicr;
2882         struct e1000_hw *hw =
2883                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2884         struct e1000_interrupt *intr =
2885                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2886
2887         igbvf_intr_disable(hw);
2888
2889         /* read-on-clear nic registers here */
2890         eicr = E1000_READ_REG(hw, E1000_EICR);
2891         intr->flags = 0;
2892
2893         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2894                 intr->flags |= E1000_FLAG_MAILBOX;
2895
2896         return 0;
2897 }
2898
2899 void igbvf_mbx_process(struct rte_eth_dev *dev)
2900 {
2901         struct e1000_hw *hw =
2902                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2903         struct e1000_mbx_info *mbx = &hw->mbx;
2904         u32 in_msg = 0;
2905
2906         /* peek the message first */
2907         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2908
2909         /* PF reset VF event */
2910         if (in_msg == E1000_PF_CONTROL_MSG) {
2911                 /* dummy mbx read to ack pf */
2912                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2913                         return;
2914                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2915                                               NULL);
2916         }
2917 }
2918
2919 static int
2920 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2921 {
2922         struct e1000_interrupt *intr =
2923                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2924
2925         if (intr->flags & E1000_FLAG_MAILBOX) {
2926                 igbvf_mbx_process(dev);
2927                 intr->flags &= ~E1000_FLAG_MAILBOX;
2928         }
2929
2930         igbvf_intr_enable(dev);
2931         rte_intr_enable(intr_handle);
2932
2933         return 0;
2934 }
2935
2936 static void
2937 eth_igbvf_interrupt_handler(void *param)
2938 {
2939         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2940
2941         eth_igbvf_interrupt_get_status(dev);
2942         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2943 }
2944
2945 static int
2946 eth_igb_led_on(struct rte_eth_dev *dev)
2947 {
2948         struct e1000_hw *hw;
2949
2950         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2951         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2952 }
2953
2954 static int
2955 eth_igb_led_off(struct rte_eth_dev *dev)
2956 {
2957         struct e1000_hw *hw;
2958
2959         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2960         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2961 }
2962
2963 static int
2964 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2965 {
2966         struct e1000_hw *hw;
2967         uint32_t ctrl;
2968         int tx_pause;
2969         int rx_pause;
2970
2971         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2972         fc_conf->pause_time = hw->fc.pause_time;
2973         fc_conf->high_water = hw->fc.high_water;
2974         fc_conf->low_water = hw->fc.low_water;
2975         fc_conf->send_xon = hw->fc.send_xon;
2976         fc_conf->autoneg = hw->mac.autoneg;
2977
2978         /*
2979          * Return rx_pause and tx_pause status according to actual setting of
2980          * the TFCE and RFCE bits in the CTRL register.
2981          */
2982         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2983         if (ctrl & E1000_CTRL_TFCE)
2984                 tx_pause = 1;
2985         else
2986                 tx_pause = 0;
2987
2988         if (ctrl & E1000_CTRL_RFCE)
2989                 rx_pause = 1;
2990         else
2991                 rx_pause = 0;
2992
2993         if (rx_pause && tx_pause)
2994                 fc_conf->mode = RTE_FC_FULL;
2995         else if (rx_pause)
2996                 fc_conf->mode = RTE_FC_RX_PAUSE;
2997         else if (tx_pause)
2998                 fc_conf->mode = RTE_FC_TX_PAUSE;
2999         else
3000                 fc_conf->mode = RTE_FC_NONE;
3001
3002         return 0;
3003 }
3004
3005 static int
3006 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3007 {
3008         struct e1000_hw *hw;
3009         int err;
3010         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3011                 e1000_fc_none,
3012                 e1000_fc_rx_pause,
3013                 e1000_fc_tx_pause,
3014                 e1000_fc_full
3015         };
3016         uint32_t rx_buf_size;
3017         uint32_t max_high_water;
3018         uint32_t rctl;
3019
3020         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3021         if (fc_conf->autoneg != hw->mac.autoneg)
3022                 return -ENOTSUP;
3023         rx_buf_size = igb_get_rx_buffer_size(hw);
3024         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3025
3026         /* At least reserve one Ethernet frame for watermark */
3027         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3028         if ((fc_conf->high_water > max_high_water) ||
3029             (fc_conf->high_water < fc_conf->low_water)) {
3030                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3031                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3032                 return -EINVAL;
3033         }
3034
3035         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3036         hw->fc.pause_time     = fc_conf->pause_time;
3037         hw->fc.high_water     = fc_conf->high_water;
3038         hw->fc.low_water      = fc_conf->low_water;
3039         hw->fc.send_xon       = fc_conf->send_xon;
3040
3041         err = e1000_setup_link_generic(hw);
3042         if (err == E1000_SUCCESS) {
3043
3044                 /* check if we want to forward MAC frames - driver doesn't have native
3045                  * capability to do that, so we'll write the registers ourselves */
3046
3047                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3048
3049                 /* set or clear MFLCN.PMCF bit depending on configuration */
3050                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3051                         rctl |= E1000_RCTL_PMCF;
3052                 else
3053                         rctl &= ~E1000_RCTL_PMCF;
3054
3055                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3056                 E1000_WRITE_FLUSH(hw);
3057
3058                 return 0;
3059         }
3060
3061         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3062         return -EIO;
3063 }
3064
3065 #define E1000_RAH_POOLSEL_SHIFT      (18)
3066 static int
3067 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3068                 uint32_t index, uint32_t pool)
3069 {
3070         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3071         uint32_t rah;
3072
3073         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3074         rah = E1000_READ_REG(hw, E1000_RAH(index));
3075         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3076         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3077         return 0;
3078 }
3079
3080 static void
3081 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3082 {
3083         uint8_t addr[ETHER_ADDR_LEN];
3084         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3085
3086         memset(addr, 0, sizeof(addr));
3087
3088         e1000_rar_set(hw, addr, index);
3089 }
3090
3091 static void
3092 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3093                                 struct ether_addr *addr)
3094 {
3095         eth_igb_rar_clear(dev, 0);
3096
3097         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3098 }
3099 /*
3100  * Virtual Function operations
3101  */
3102 static void
3103 igbvf_intr_disable(struct e1000_hw *hw)
3104 {
3105         PMD_INIT_FUNC_TRACE();
3106
3107         /* Clear interrupt mask to stop from interrupts being generated */
3108         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3109
3110         E1000_WRITE_FLUSH(hw);
3111 }
3112
3113 static void
3114 igbvf_stop_adapter(struct rte_eth_dev *dev)
3115 {
3116         u32 reg_val;
3117         u16 i;
3118         struct rte_eth_dev_info dev_info;
3119         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3120
3121         memset(&dev_info, 0, sizeof(dev_info));
3122         eth_igbvf_infos_get(dev, &dev_info);
3123
3124         /* Clear interrupt mask to stop from interrupts being generated */
3125         igbvf_intr_disable(hw);
3126
3127         /* Clear any pending interrupts, flush previous writes */
3128         E1000_READ_REG(hw, E1000_EICR);
3129
3130         /* Disable the transmit unit.  Each queue must be disabled. */
3131         for (i = 0; i < dev_info.max_tx_queues; i++)
3132                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3133
3134         /* Disable the receive unit by stopping each queue */
3135         for (i = 0; i < dev_info.max_rx_queues; i++) {
3136                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3137                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3138                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3139                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3140                         ;
3141         }
3142
3143         /* flush all queues disables */
3144         E1000_WRITE_FLUSH(hw);
3145         msec_delay(2);
3146 }
3147
3148 static int eth_igbvf_link_update(struct e1000_hw *hw)
3149 {
3150         struct e1000_mbx_info *mbx = &hw->mbx;
3151         struct e1000_mac_info *mac = &hw->mac;
3152         int ret_val = E1000_SUCCESS;
3153
3154         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3155
3156         /*
3157          * We only want to run this if there has been a rst asserted.
3158          * in this case that could mean a link change, device reset,
3159          * or a virtual function reset
3160          */
3161
3162         /* If we were hit with a reset or timeout drop the link */
3163         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3164                 mac->get_link_status = TRUE;
3165
3166         if (!mac->get_link_status)
3167                 goto out;
3168
3169         /* if link status is down no point in checking to see if pf is up */
3170         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3171                 goto out;
3172
3173         /* if we passed all the tests above then the link is up and we no
3174          * longer need to check for link */
3175         mac->get_link_status = FALSE;
3176
3177 out:
3178         return ret_val;
3179 }
3180
3181
3182 static int
3183 igbvf_dev_configure(struct rte_eth_dev *dev)
3184 {
3185         struct rte_eth_conf* conf = &dev->data->dev_conf;
3186
3187         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3188                      dev->data->port_id);
3189
3190         /*
3191          * VF has no ability to enable/disable HW CRC
3192          * Keep the persistent behavior the same as Host PF
3193          */
3194 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3195         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
3196                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3197                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
3198         }
3199 #else
3200         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
3201                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3202                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
3203         }
3204 #endif
3205
3206         return 0;
3207 }
3208
3209 static int
3210 igbvf_dev_start(struct rte_eth_dev *dev)
3211 {
3212         struct e1000_hw *hw =
3213                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3214         struct e1000_adapter *adapter =
3215                 E1000_DEV_PRIVATE(dev->data->dev_private);
3216         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3217         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3218         int ret;
3219         uint32_t intr_vector = 0;
3220
3221         PMD_INIT_FUNC_TRACE();
3222
3223         hw->mac.ops.reset_hw(hw);
3224         adapter->stopped = 0;
3225
3226         /* Set all vfta */
3227         igbvf_set_vfta_all(dev,1);
3228
3229         eth_igbvf_tx_init(dev);
3230
3231         /* This can fail when allocating mbufs for descriptor rings */
3232         ret = eth_igbvf_rx_init(dev);
3233         if (ret) {
3234                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3235                 igb_dev_clear_queues(dev);
3236                 return ret;
3237         }
3238
3239         /* check and configure queue intr-vector mapping */
3240         if (rte_intr_cap_multiple(intr_handle) &&
3241             dev->data->dev_conf.intr_conf.rxq) {
3242                 intr_vector = dev->data->nb_rx_queues;
3243                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3244                 if (ret)
3245                         return ret;
3246         }
3247
3248         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3249                 intr_handle->intr_vec =
3250                         rte_zmalloc("intr_vec",
3251                                     dev->data->nb_rx_queues * sizeof(int), 0);
3252                 if (!intr_handle->intr_vec) {
3253                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3254                                      " intr_vec", dev->data->nb_rx_queues);
3255                         return -ENOMEM;
3256                 }
3257         }
3258
3259         eth_igbvf_configure_msix_intr(dev);
3260
3261         /* enable uio/vfio intr/eventfd mapping */
3262         rte_intr_enable(intr_handle);
3263
3264         /* resume enabled intr since hw reset */
3265         igbvf_intr_enable(dev);
3266
3267         return 0;
3268 }
3269
3270 static void
3271 igbvf_dev_stop(struct rte_eth_dev *dev)
3272 {
3273         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3274         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3275
3276         PMD_INIT_FUNC_TRACE();
3277
3278         igbvf_stop_adapter(dev);
3279
3280         /*
3281           * Clear what we set, but we still keep shadow_vfta to
3282           * restore after device starts
3283           */
3284         igbvf_set_vfta_all(dev,0);
3285
3286         igb_dev_clear_queues(dev);
3287
3288         /* disable intr eventfd mapping */
3289         rte_intr_disable(intr_handle);
3290
3291         /* Clean datapath event and queue/vec mapping */
3292         rte_intr_efd_disable(intr_handle);
3293         if (intr_handle->intr_vec) {
3294                 rte_free(intr_handle->intr_vec);
3295                 intr_handle->intr_vec = NULL;
3296         }
3297 }
3298
3299 static void
3300 igbvf_dev_close(struct rte_eth_dev *dev)
3301 {
3302         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3303         struct e1000_adapter *adapter =
3304                 E1000_DEV_PRIVATE(dev->data->dev_private);
3305         struct ether_addr addr;
3306
3307         PMD_INIT_FUNC_TRACE();
3308
3309         e1000_reset_hw(hw);
3310
3311         igbvf_dev_stop(dev);
3312         adapter->stopped = 1;
3313         igb_dev_free_queues(dev);
3314
3315         /**
3316          * reprogram the RAR with a zero mac address,
3317          * to ensure that the VF traffic goes to the PF
3318          * after stop, close and detach of the VF.
3319          **/
3320
3321         memset(&addr, 0, sizeof(addr));
3322         igbvf_default_mac_addr_set(dev, &addr);
3323 }
3324
3325 static void
3326 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3327 {
3328         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3329
3330         /* Set both unicast and multicast promisc */
3331         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3332 }
3333
3334 static void
3335 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3336 {
3337         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3338
3339         /* If in allmulticast mode leave multicast promisc */
3340         if (dev->data->all_multicast == 1)
3341                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3342         else
3343                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3344 }
3345
3346 static void
3347 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3348 {
3349         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3350
3351         /* In promiscuous mode multicast promisc already set */
3352         if (dev->data->promiscuous == 0)
3353                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3354 }
3355
3356 static void
3357 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3358 {
3359         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360
3361         /* In promiscuous mode leave multicast promisc enabled */
3362         if (dev->data->promiscuous == 0)
3363                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3364 }
3365
3366 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3367 {
3368         struct e1000_mbx_info *mbx = &hw->mbx;
3369         uint32_t msgbuf[2];
3370         s32 err;
3371
3372         /* After set vlan, vlan strip will also be enabled in igb driver*/
3373         msgbuf[0] = E1000_VF_SET_VLAN;
3374         msgbuf[1] = vid;
3375         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3376         if (on)
3377                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3378
3379         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3380         if (err)
3381                 goto mbx_err;
3382
3383         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3384         if (err)
3385                 goto mbx_err;
3386
3387         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3388         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3389                 err = -EINVAL;
3390
3391 mbx_err:
3392         return err;
3393 }
3394
3395 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3396 {
3397         struct e1000_hw *hw =
3398                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3399         struct e1000_vfta * shadow_vfta =
3400                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3401         int i = 0, j = 0, vfta = 0, mask = 1;
3402
3403         for (i = 0; i < IGB_VFTA_SIZE; i++){
3404                 vfta = shadow_vfta->vfta[i];
3405                 if(vfta){
3406                         mask = 1;
3407                         for (j = 0; j < 32; j++){
3408                                 if(vfta & mask)
3409                                         igbvf_set_vfta(hw,
3410                                                 (uint16_t)((i<<5)+j), on);
3411                                 mask<<=1;
3412                         }
3413                 }
3414         }
3415
3416 }
3417
3418 static int
3419 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3420 {
3421         struct e1000_hw *hw =
3422                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3423         struct e1000_vfta * shadow_vfta =
3424                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3425         uint32_t vid_idx = 0;
3426         uint32_t vid_bit = 0;
3427         int ret = 0;
3428
3429         PMD_INIT_FUNC_TRACE();
3430
3431         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3432         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3433         if(ret){
3434                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3435                 return ret;
3436         }
3437         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3438         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3439
3440         /*Save what we set and retore it after device reset*/
3441         if (on)
3442                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3443         else
3444                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3445
3446         return 0;
3447 }
3448
3449 static void
3450 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3451 {
3452         struct e1000_hw *hw =
3453                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3454
3455         /* index is not used by rar_set() */
3456         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3457 }
3458
3459
3460 static int
3461 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3462                         struct rte_eth_rss_reta_entry64 *reta_conf,
3463                         uint16_t reta_size)
3464 {
3465         uint8_t i, j, mask;
3466         uint32_t reta, r;
3467         uint16_t idx, shift;
3468         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3469
3470         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3471                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3472                         "(%d) doesn't match the number hardware can supported "
3473                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3474                 return -EINVAL;
3475         }
3476
3477         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3478                 idx = i / RTE_RETA_GROUP_SIZE;
3479                 shift = i % RTE_RETA_GROUP_SIZE;
3480                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3481                                                 IGB_4_BIT_MASK);
3482                 if (!mask)
3483                         continue;
3484                 if (mask == IGB_4_BIT_MASK)
3485                         r = 0;
3486                 else
3487                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3488                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3489                         if (mask & (0x1 << j))
3490                                 reta |= reta_conf[idx].reta[shift + j] <<
3491                                                         (CHAR_BIT * j);
3492                         else
3493                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3494                 }
3495                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3496         }
3497
3498         return 0;
3499 }
3500
3501 static int
3502 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3503                        struct rte_eth_rss_reta_entry64 *reta_conf,
3504                        uint16_t reta_size)
3505 {
3506         uint8_t i, j, mask;
3507         uint32_t reta;
3508         uint16_t idx, shift;
3509         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3510
3511         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3512                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3513                         "(%d) doesn't match the number hardware can supported "
3514                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3515                 return -EINVAL;
3516         }
3517
3518         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3519                 idx = i / RTE_RETA_GROUP_SIZE;
3520                 shift = i % RTE_RETA_GROUP_SIZE;
3521                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3522                                                 IGB_4_BIT_MASK);
3523                 if (!mask)
3524                         continue;
3525                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3526                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3527                         if (mask & (0x1 << j))
3528                                 reta_conf[idx].reta[shift + j] =
3529                                         ((reta >> (CHAR_BIT * j)) &
3530                                                 IGB_8_BIT_MASK);
3531                 }
3532         }
3533
3534         return 0;
3535 }
3536
3537 int
3538 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3539                         struct rte_eth_syn_filter *filter,
3540                         bool add)
3541 {
3542         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3543         struct e1000_filter_info *filter_info =
3544                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3545         uint32_t synqf, rfctl;
3546
3547         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3548                 return -EINVAL;
3549
3550         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3551
3552         if (add) {
3553                 if (synqf & E1000_SYN_FILTER_ENABLE)
3554                         return -EINVAL;
3555
3556                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3557                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3558
3559                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3560                 if (filter->hig_pri)
3561                         rfctl |= E1000_RFCTL_SYNQFP;
3562                 else
3563                         rfctl &= ~E1000_RFCTL_SYNQFP;
3564
3565                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3566         } else {
3567                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3568                         return -ENOENT;
3569                 synqf = 0;
3570         }
3571
3572         filter_info->syn_info = synqf;
3573         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3574         E1000_WRITE_FLUSH(hw);
3575         return 0;
3576 }
3577
3578 static int
3579 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3580                         struct rte_eth_syn_filter *filter)
3581 {
3582         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3583         uint32_t synqf, rfctl;
3584
3585         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3586         if (synqf & E1000_SYN_FILTER_ENABLE) {
3587                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3588                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3589                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3590                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3591                 return 0;
3592         }
3593
3594         return -ENOENT;
3595 }
3596
3597 static int
3598 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3599                         enum rte_filter_op filter_op,
3600                         void *arg)
3601 {
3602         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3603         int ret;
3604
3605         MAC_TYPE_FILTER_SUP(hw->mac.type);
3606
3607         if (filter_op == RTE_ETH_FILTER_NOP)
3608                 return 0;
3609
3610         if (arg == NULL) {
3611                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3612                             filter_op);
3613                 return -EINVAL;
3614         }
3615
3616         switch (filter_op) {
3617         case RTE_ETH_FILTER_ADD:
3618                 ret = eth_igb_syn_filter_set(dev,
3619                                 (struct rte_eth_syn_filter *)arg,
3620                                 TRUE);
3621                 break;
3622         case RTE_ETH_FILTER_DELETE:
3623                 ret = eth_igb_syn_filter_set(dev,
3624                                 (struct rte_eth_syn_filter *)arg,
3625                                 FALSE);
3626                 break;
3627         case RTE_ETH_FILTER_GET:
3628                 ret = eth_igb_syn_filter_get(dev,
3629                                 (struct rte_eth_syn_filter *)arg);
3630                 break;
3631         default:
3632                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3633                 ret = -EINVAL;
3634                 break;
3635         }
3636
3637         return ret;
3638 }
3639
3640 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3641 static inline int
3642 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3643                         struct e1000_2tuple_filter_info *filter_info)
3644 {
3645         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3646                 return -EINVAL;
3647         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3648                 return -EINVAL;  /* filter index is out of range. */
3649         if (filter->tcp_flags > TCP_FLAG_ALL)
3650                 return -EINVAL;  /* flags is invalid. */
3651
3652         switch (filter->dst_port_mask) {
3653         case UINT16_MAX:
3654                 filter_info->dst_port_mask = 0;
3655                 filter_info->dst_port = filter->dst_port;
3656                 break;
3657         case 0:
3658                 filter_info->dst_port_mask = 1;
3659                 break;
3660         default:
3661                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3662                 return -EINVAL;
3663         }
3664
3665         switch (filter->proto_mask) {
3666         case UINT8_MAX:
3667                 filter_info->proto_mask = 0;
3668                 filter_info->proto = filter->proto;
3669                 break;
3670         case 0:
3671                 filter_info->proto_mask = 1;
3672                 break;
3673         default:
3674                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3675                 return -EINVAL;
3676         }
3677
3678         filter_info->priority = (uint8_t)filter->priority;
3679         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3680                 filter_info->tcp_flags = filter->tcp_flags;
3681         else
3682                 filter_info->tcp_flags = 0;
3683
3684         return 0;
3685 }
3686
3687 static inline struct e1000_2tuple_filter *
3688 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3689                         struct e1000_2tuple_filter_info *key)
3690 {
3691         struct e1000_2tuple_filter *it;
3692
3693         TAILQ_FOREACH(it, filter_list, entries) {
3694                 if (memcmp(key, &it->filter_info,
3695                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3696                         return it;
3697                 }
3698         }
3699         return NULL;
3700 }
3701
3702 /* inject a igb 2tuple filter to HW */
3703 static inline void
3704 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3705                            struct e1000_2tuple_filter *filter)
3706 {
3707         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3708         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3709         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3710         int i;
3711
3712         i = filter->index;
3713         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3714         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3715                 imir |= E1000_IMIR_PORT_BP;
3716         else
3717                 imir &= ~E1000_IMIR_PORT_BP;
3718
3719         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3720
3721         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3722         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3723         ttqf |= (uint32_t)(filter->filter_info.proto &
3724                                                 E1000_TTQF_PROTOCOL_MASK);
3725         if (filter->filter_info.proto_mask == 0)
3726                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3727
3728         /* tcp flags bits setting. */
3729         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3730                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3731                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3732                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3733                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3734                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3735                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3736                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3737                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3738                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3739                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3740                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3741                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3742         } else {
3743                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3744         }
3745         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3746         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3747         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3748 }
3749
3750 /*
3751  * igb_add_2tuple_filter - add a 2tuple filter
3752  *
3753  * @param
3754  * dev: Pointer to struct rte_eth_dev.
3755  * ntuple_filter: ponter to the filter that will be added.
3756  *
3757  * @return
3758  *    - On success, zero.
3759  *    - On failure, a negative value.
3760  */
3761 static int
3762 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3763                         struct rte_eth_ntuple_filter *ntuple_filter)
3764 {
3765         struct e1000_filter_info *filter_info =
3766                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3767         struct e1000_2tuple_filter *filter;
3768         int i, ret;
3769
3770         filter = rte_zmalloc("e1000_2tuple_filter",
3771                         sizeof(struct e1000_2tuple_filter), 0);
3772         if (filter == NULL)
3773                 return -ENOMEM;
3774
3775         ret = ntuple_filter_to_2tuple(ntuple_filter,
3776                                       &filter->filter_info);
3777         if (ret < 0) {
3778                 rte_free(filter);
3779                 return ret;
3780         }
3781         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3782                                          &filter->filter_info) != NULL) {
3783                 PMD_DRV_LOG(ERR, "filter exists.");
3784                 rte_free(filter);
3785                 return -EEXIST;
3786         }
3787         filter->queue = ntuple_filter->queue;
3788
3789         /*
3790          * look for an unused 2tuple filter index,
3791          * and insert the filter to list.
3792          */
3793         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3794                 if (!(filter_info->twotuple_mask & (1 << i))) {
3795                         filter_info->twotuple_mask |= 1 << i;
3796                         filter->index = i;
3797                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3798                                           filter,
3799                                           entries);
3800                         break;
3801                 }
3802         }
3803         if (i >= E1000_MAX_TTQF_FILTERS) {
3804                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3805                 rte_free(filter);
3806                 return -ENOSYS;
3807         }
3808
3809         igb_inject_2uple_filter(dev, filter);
3810         return 0;
3811 }
3812
3813 int
3814 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3815                         struct e1000_2tuple_filter *filter)
3816 {
3817         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3818         struct e1000_filter_info *filter_info =
3819                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3820
3821         filter_info->twotuple_mask &= ~(1 << filter->index);
3822         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3823         rte_free(filter);
3824
3825         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3826         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3827         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3828         return 0;
3829 }
3830
3831 /*
3832  * igb_remove_2tuple_filter - remove a 2tuple filter
3833  *
3834  * @param
3835  * dev: Pointer to struct rte_eth_dev.
3836  * ntuple_filter: ponter to the filter that will be removed.
3837  *
3838  * @return
3839  *    - On success, zero.
3840  *    - On failure, a negative value.
3841  */
3842 static int
3843 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3844                         struct rte_eth_ntuple_filter *ntuple_filter)
3845 {
3846         struct e1000_filter_info *filter_info =
3847                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3848         struct e1000_2tuple_filter_info filter_2tuple;
3849         struct e1000_2tuple_filter *filter;
3850         int ret;
3851
3852         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3853         ret = ntuple_filter_to_2tuple(ntuple_filter,
3854                                       &filter_2tuple);
3855         if (ret < 0)
3856                 return ret;
3857
3858         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3859                                          &filter_2tuple);
3860         if (filter == NULL) {
3861                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3862                 return -ENOENT;
3863         }
3864
3865         igb_delete_2tuple_filter(dev, filter);
3866
3867         return 0;
3868 }
3869
3870 /* inject a igb flex filter to HW */
3871 static inline void
3872 igb_inject_flex_filter(struct rte_eth_dev *dev,
3873                            struct e1000_flex_filter *filter)
3874 {
3875         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3876         uint32_t wufc, queueing;
3877         uint32_t reg_off;
3878         uint8_t i, j = 0;
3879
3880         wufc = E1000_READ_REG(hw, E1000_WUFC);
3881         if (filter->index < E1000_MAX_FHFT)
3882                 reg_off = E1000_FHFT(filter->index);
3883         else
3884                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3885
3886         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3887                         (E1000_WUFC_FLX0 << filter->index));
3888         queueing = filter->filter_info.len |
3889                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3890                 (filter->filter_info.priority <<
3891                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3892         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3893                         queueing);
3894
3895         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3896                 E1000_WRITE_REG(hw, reg_off,
3897                                 filter->filter_info.dwords[j]);
3898                 reg_off += sizeof(uint32_t);
3899                 E1000_WRITE_REG(hw, reg_off,
3900                                 filter->filter_info.dwords[++j]);
3901                 reg_off += sizeof(uint32_t);
3902                 E1000_WRITE_REG(hw, reg_off,
3903                         (uint32_t)filter->filter_info.mask[i]);
3904                 reg_off += sizeof(uint32_t) * 2;
3905                 ++j;
3906         }
3907 }
3908
3909 static inline struct e1000_flex_filter *
3910 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3911                         struct e1000_flex_filter_info *key)
3912 {
3913         struct e1000_flex_filter *it;
3914
3915         TAILQ_FOREACH(it, filter_list, entries) {
3916                 if (memcmp(key, &it->filter_info,
3917                         sizeof(struct e1000_flex_filter_info)) == 0)
3918                         return it;
3919         }
3920
3921         return NULL;
3922 }
3923
3924 /* remove a flex byte filter
3925  * @param
3926  * dev: Pointer to struct rte_eth_dev.
3927  * filter: the pointer of the filter will be removed.
3928  */
3929 void
3930 igb_remove_flex_filter(struct rte_eth_dev *dev,
3931                         struct e1000_flex_filter *filter)
3932 {
3933         struct e1000_filter_info *filter_info =
3934                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3935         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3936         uint32_t wufc, i;
3937         uint32_t reg_off;
3938
3939         wufc = E1000_READ_REG(hw, E1000_WUFC);
3940         if (filter->index < E1000_MAX_FHFT)
3941                 reg_off = E1000_FHFT(filter->index);
3942         else
3943                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3944
3945         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3946                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3947
3948         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3949                 (~(E1000_WUFC_FLX0 << filter->index)));
3950
3951         filter_info->flex_mask &= ~(1 << filter->index);
3952         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
3953         rte_free(filter);
3954 }
3955
3956 int
3957 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3958                         struct rte_eth_flex_filter *filter,
3959                         bool add)
3960 {
3961         struct e1000_filter_info *filter_info =
3962                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3963         struct e1000_flex_filter *flex_filter, *it;
3964         uint32_t mask;
3965         uint8_t shift, i;
3966
3967         flex_filter = rte_zmalloc("e1000_flex_filter",
3968                         sizeof(struct e1000_flex_filter), 0);
3969         if (flex_filter == NULL)
3970                 return -ENOMEM;
3971
3972         flex_filter->filter_info.len = filter->len;
3973         flex_filter->filter_info.priority = filter->priority;
3974         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3975         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3976                 mask = 0;
3977                 /* reverse bits in flex filter's mask*/
3978                 for (shift = 0; shift < CHAR_BIT; shift++) {
3979                         if (filter->mask[i] & (0x01 << shift))
3980                                 mask |= (0x80 >> shift);
3981                 }
3982                 flex_filter->filter_info.mask[i] = mask;
3983         }
3984
3985         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3986                                 &flex_filter->filter_info);
3987         if (it == NULL && !add) {
3988                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3989                 rte_free(flex_filter);
3990                 return -ENOENT;
3991         }
3992         if (it != NULL && add) {
3993                 PMD_DRV_LOG(ERR, "filter exists.");
3994                 rte_free(flex_filter);
3995                 return -EEXIST;
3996         }
3997
3998         if (add) {
3999                 flex_filter->queue = filter->queue;
4000                 /*
4001                  * look for an unused flex filter index
4002                  * and insert the filter into the list.
4003                  */
4004                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4005                         if (!(filter_info->flex_mask & (1 << i))) {
4006                                 filter_info->flex_mask |= 1 << i;
4007                                 flex_filter->index = i;
4008                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4009                                         flex_filter,
4010                                         entries);
4011                                 break;
4012                         }
4013                 }
4014                 if (i >= E1000_MAX_FLEX_FILTERS) {
4015                         PMD_DRV_LOG(ERR, "flex filters are full.");
4016                         rte_free(flex_filter);
4017                         return -ENOSYS;
4018                 }
4019
4020                 igb_inject_flex_filter(dev, flex_filter);
4021
4022         } else {
4023                 igb_remove_flex_filter(dev, it);
4024                 rte_free(flex_filter);
4025         }
4026
4027         return 0;
4028 }
4029
4030 static int
4031 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4032                         struct rte_eth_flex_filter *filter)
4033 {
4034         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4035         struct e1000_filter_info *filter_info =
4036                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4037         struct e1000_flex_filter flex_filter, *it;
4038         uint32_t wufc, queueing, wufc_en = 0;
4039
4040         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4041         flex_filter.filter_info.len = filter->len;
4042         flex_filter.filter_info.priority = filter->priority;
4043         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4044         memcpy(flex_filter.filter_info.mask, filter->mask,
4045                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4046
4047         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4048                                 &flex_filter.filter_info);
4049         if (it == NULL) {
4050                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4051                 return -ENOENT;
4052         }
4053
4054         wufc = E1000_READ_REG(hw, E1000_WUFC);
4055         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4056
4057         if ((wufc & wufc_en) == wufc_en) {
4058                 uint32_t reg_off = 0;
4059                 if (it->index < E1000_MAX_FHFT)
4060                         reg_off = E1000_FHFT(it->index);
4061                 else
4062                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4063
4064                 queueing = E1000_READ_REG(hw,
4065                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4066                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4067                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4068                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4069                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4070                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4071                 return 0;
4072         }
4073         return -ENOENT;
4074 }
4075
4076 static int
4077 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4078                         enum rte_filter_op filter_op,
4079                         void *arg)
4080 {
4081         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4082         struct rte_eth_flex_filter *filter;
4083         int ret = 0;
4084
4085         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4086
4087         if (filter_op == RTE_ETH_FILTER_NOP)
4088                 return ret;
4089
4090         if (arg == NULL) {
4091                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4092                             filter_op);
4093                 return -EINVAL;
4094         }
4095
4096         filter = (struct rte_eth_flex_filter *)arg;
4097         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4098             || filter->len % sizeof(uint64_t) != 0) {
4099                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4100                 return -EINVAL;
4101         }
4102         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4103                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4104                 return -EINVAL;
4105         }
4106
4107         switch (filter_op) {
4108         case RTE_ETH_FILTER_ADD:
4109                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4110                 break;
4111         case RTE_ETH_FILTER_DELETE:
4112                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4113                 break;
4114         case RTE_ETH_FILTER_GET:
4115                 ret = eth_igb_get_flex_filter(dev, filter);
4116                 break;
4117         default:
4118                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4119                 ret = -EINVAL;
4120                 break;
4121         }
4122
4123         return ret;
4124 }
4125
4126 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4127 static inline int
4128 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4129                         struct e1000_5tuple_filter_info *filter_info)
4130 {
4131         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4132                 return -EINVAL;
4133         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4134                 return -EINVAL;  /* filter index is out of range. */
4135         if (filter->tcp_flags > TCP_FLAG_ALL)
4136                 return -EINVAL;  /* flags is invalid. */
4137
4138         switch (filter->dst_ip_mask) {
4139         case UINT32_MAX:
4140                 filter_info->dst_ip_mask = 0;
4141                 filter_info->dst_ip = filter->dst_ip;
4142                 break;
4143         case 0:
4144                 filter_info->dst_ip_mask = 1;
4145                 break;
4146         default:
4147                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4148                 return -EINVAL;
4149         }
4150
4151         switch (filter->src_ip_mask) {
4152         case UINT32_MAX:
4153                 filter_info->src_ip_mask = 0;
4154                 filter_info->src_ip = filter->src_ip;
4155                 break;
4156         case 0:
4157                 filter_info->src_ip_mask = 1;
4158                 break;
4159         default:
4160                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4161                 return -EINVAL;
4162         }
4163
4164         switch (filter->dst_port_mask) {
4165         case UINT16_MAX:
4166                 filter_info->dst_port_mask = 0;
4167                 filter_info->dst_port = filter->dst_port;
4168                 break;
4169         case 0:
4170                 filter_info->dst_port_mask = 1;
4171                 break;
4172         default:
4173                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4174                 return -EINVAL;
4175         }
4176
4177         switch (filter->src_port_mask) {
4178         case UINT16_MAX:
4179                 filter_info->src_port_mask = 0;
4180                 filter_info->src_port = filter->src_port;
4181                 break;
4182         case 0:
4183                 filter_info->src_port_mask = 1;
4184                 break;
4185         default:
4186                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4187                 return -EINVAL;
4188         }
4189
4190         switch (filter->proto_mask) {
4191         case UINT8_MAX:
4192                 filter_info->proto_mask = 0;
4193                 filter_info->proto = filter->proto;
4194                 break;
4195         case 0:
4196                 filter_info->proto_mask = 1;
4197                 break;
4198         default:
4199                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4200                 return -EINVAL;
4201         }
4202
4203         filter_info->priority = (uint8_t)filter->priority;
4204         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4205                 filter_info->tcp_flags = filter->tcp_flags;
4206         else
4207                 filter_info->tcp_flags = 0;
4208
4209         return 0;
4210 }
4211
4212 static inline struct e1000_5tuple_filter *
4213 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4214                         struct e1000_5tuple_filter_info *key)
4215 {
4216         struct e1000_5tuple_filter *it;
4217
4218         TAILQ_FOREACH(it, filter_list, entries) {
4219                 if (memcmp(key, &it->filter_info,
4220                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4221                         return it;
4222                 }
4223         }
4224         return NULL;
4225 }
4226
4227 /* inject a igb 5-tuple filter to HW */
4228 static inline void
4229 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4230                            struct e1000_5tuple_filter *filter)
4231 {
4232         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4233         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4234         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4235         uint8_t i;
4236
4237         i = filter->index;
4238         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4239         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4240                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4241         if (filter->filter_info.dst_ip_mask == 0)
4242                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4243         if (filter->filter_info.src_port_mask == 0)
4244                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4245         if (filter->filter_info.proto_mask == 0)
4246                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4247         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4248                 E1000_FTQF_QUEUE_MASK;
4249         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4250         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4251         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4252         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4253
4254         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4255         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4256
4257         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4258         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4259                 imir |= E1000_IMIR_PORT_BP;
4260         else
4261                 imir &= ~E1000_IMIR_PORT_BP;
4262         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4263
4264         /* tcp flags bits setting. */
4265         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4266                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4267                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4268                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4269                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4270                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4271                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4272                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4273                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4274                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4275                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4276                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4277                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4278         } else {
4279                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4280         }
4281         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4282         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4283 }
4284
4285 /*
4286  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4287  *
4288  * @param
4289  * dev: Pointer to struct rte_eth_dev.
4290  * ntuple_filter: ponter to the filter that will be added.
4291  *
4292  * @return
4293  *    - On success, zero.
4294  *    - On failure, a negative value.
4295  */
4296 static int
4297 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4298                         struct rte_eth_ntuple_filter *ntuple_filter)
4299 {
4300         struct e1000_filter_info *filter_info =
4301                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4302         struct e1000_5tuple_filter *filter;
4303         uint8_t i;
4304         int ret;
4305
4306         filter = rte_zmalloc("e1000_5tuple_filter",
4307                         sizeof(struct e1000_5tuple_filter), 0);
4308         if (filter == NULL)
4309                 return -ENOMEM;
4310
4311         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4312                                             &filter->filter_info);
4313         if (ret < 0) {
4314                 rte_free(filter);
4315                 return ret;
4316         }
4317
4318         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4319                                          &filter->filter_info) != NULL) {
4320                 PMD_DRV_LOG(ERR, "filter exists.");
4321                 rte_free(filter);
4322                 return -EEXIST;
4323         }
4324         filter->queue = ntuple_filter->queue;
4325
4326         /*
4327          * look for an unused 5tuple filter index,
4328          * and insert the filter to list.
4329          */
4330         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4331                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4332                         filter_info->fivetuple_mask |= 1 << i;
4333                         filter->index = i;
4334                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4335                                           filter,
4336                                           entries);
4337                         break;
4338                 }
4339         }
4340         if (i >= E1000_MAX_FTQF_FILTERS) {
4341                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4342                 rte_free(filter);
4343                 return -ENOSYS;
4344         }
4345
4346         igb_inject_5tuple_filter_82576(dev, filter);
4347         return 0;
4348 }
4349
4350 int
4351 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4352                                 struct e1000_5tuple_filter *filter)
4353 {
4354         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4355         struct e1000_filter_info *filter_info =
4356                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4357
4358         filter_info->fivetuple_mask &= ~(1 << filter->index);
4359         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4360         rte_free(filter);
4361
4362         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4363                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4364         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4365         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4366         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4367         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4368         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4369         return 0;
4370 }
4371
4372 /*
4373  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4374  *
4375  * @param
4376  * dev: Pointer to struct rte_eth_dev.
4377  * ntuple_filter: ponter to the filter that will be removed.
4378  *
4379  * @return
4380  *    - On success, zero.
4381  *    - On failure, a negative value.
4382  */
4383 static int
4384 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4385                                 struct rte_eth_ntuple_filter *ntuple_filter)
4386 {
4387         struct e1000_filter_info *filter_info =
4388                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4389         struct e1000_5tuple_filter_info filter_5tuple;
4390         struct e1000_5tuple_filter *filter;
4391         int ret;
4392
4393         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4394         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4395                                             &filter_5tuple);
4396         if (ret < 0)
4397                 return ret;
4398
4399         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4400                                          &filter_5tuple);
4401         if (filter == NULL) {
4402                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4403                 return -ENOENT;
4404         }
4405
4406         igb_delete_5tuple_filter_82576(dev, filter);
4407
4408         return 0;
4409 }
4410
4411 static int
4412 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4413 {
4414         uint32_t rctl;
4415         struct e1000_hw *hw;
4416         struct rte_eth_dev_info dev_info;
4417         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4418                                      VLAN_TAG_SIZE);
4419
4420         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4421
4422 #ifdef RTE_LIBRTE_82571_SUPPORT
4423         /* XXX: not bigger than max_rx_pktlen */
4424         if (hw->mac.type == e1000_82571)
4425                 return -ENOTSUP;
4426 #endif
4427         eth_igb_infos_get(dev, &dev_info);
4428
4429         /* check that mtu is within the allowed range */
4430         if ((mtu < ETHER_MIN_MTU) ||
4431             (frame_size > dev_info.max_rx_pktlen))
4432                 return -EINVAL;
4433
4434         /* refuse mtu that requires the support of scattered packets when this
4435          * feature has not been enabled before. */
4436         if (!dev->data->scattered_rx &&
4437             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4438                 return -EINVAL;
4439
4440         rctl = E1000_READ_REG(hw, E1000_RCTL);
4441
4442         /* switch to jumbo mode if needed */
4443         if (frame_size > ETHER_MAX_LEN) {
4444                 dev->data->dev_conf.rxmode.offloads |=
4445                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4446                 rctl |= E1000_RCTL_LPE;
4447         } else {
4448                 dev->data->dev_conf.rxmode.offloads &=
4449                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4450                 rctl &= ~E1000_RCTL_LPE;
4451         }
4452         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4453
4454         /* update max frame size */
4455         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4456
4457         E1000_WRITE_REG(hw, E1000_RLPML,
4458                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4459
4460         return 0;
4461 }
4462
4463 /*
4464  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4465  *
4466  * @param
4467  * dev: Pointer to struct rte_eth_dev.
4468  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4469  * add: if true, add filter, if false, remove filter
4470  *
4471  * @return
4472  *    - On success, zero.
4473  *    - On failure, a negative value.
4474  */
4475 int
4476 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4477                         struct rte_eth_ntuple_filter *ntuple_filter,
4478                         bool add)
4479 {
4480         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4481         int ret;
4482
4483         switch (ntuple_filter->flags) {
4484         case RTE_5TUPLE_FLAGS:
4485         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4486                 if (hw->mac.type != e1000_82576)
4487                         return -ENOTSUP;
4488                 if (add)
4489                         ret = igb_add_5tuple_filter_82576(dev,
4490                                                           ntuple_filter);
4491                 else
4492                         ret = igb_remove_5tuple_filter_82576(dev,
4493                                                              ntuple_filter);
4494                 break;
4495         case RTE_2TUPLE_FLAGS:
4496         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4497                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4498                         hw->mac.type != e1000_i210 &&
4499                         hw->mac.type != e1000_i211)
4500                         return -ENOTSUP;
4501                 if (add)
4502                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4503                 else
4504                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4505                 break;
4506         default:
4507                 ret = -EINVAL;
4508                 break;
4509         }
4510
4511         return ret;
4512 }
4513
4514 /*
4515  * igb_get_ntuple_filter - get a ntuple filter
4516  *
4517  * @param
4518  * dev: Pointer to struct rte_eth_dev.
4519  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4520  *
4521  * @return
4522  *    - On success, zero.
4523  *    - On failure, a negative value.
4524  */
4525 static int
4526 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4527                         struct rte_eth_ntuple_filter *ntuple_filter)
4528 {
4529         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4530         struct e1000_filter_info *filter_info =
4531                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4532         struct e1000_5tuple_filter_info filter_5tuple;
4533         struct e1000_2tuple_filter_info filter_2tuple;
4534         struct e1000_5tuple_filter *p_5tuple_filter;
4535         struct e1000_2tuple_filter *p_2tuple_filter;
4536         int ret;
4537
4538         switch (ntuple_filter->flags) {
4539         case RTE_5TUPLE_FLAGS:
4540         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4541                 if (hw->mac.type != e1000_82576)
4542                         return -ENOTSUP;
4543                 memset(&filter_5tuple,
4544                         0,
4545                         sizeof(struct e1000_5tuple_filter_info));
4546                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4547                                                     &filter_5tuple);
4548                 if (ret < 0)
4549                         return ret;
4550                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4551                                         &filter_info->fivetuple_list,
4552                                         &filter_5tuple);
4553                 if (p_5tuple_filter == NULL) {
4554                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4555                         return -ENOENT;
4556                 }
4557                 ntuple_filter->queue = p_5tuple_filter->queue;
4558                 break;
4559         case RTE_2TUPLE_FLAGS:
4560         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4561                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4562                         return -ENOTSUP;
4563                 memset(&filter_2tuple,
4564                         0,
4565                         sizeof(struct e1000_2tuple_filter_info));
4566                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4567                 if (ret < 0)
4568                         return ret;
4569                 p_2tuple_filter = igb_2tuple_filter_lookup(
4570                                         &filter_info->twotuple_list,
4571                                         &filter_2tuple);
4572                 if (p_2tuple_filter == NULL) {
4573                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4574                         return -ENOENT;
4575                 }
4576                 ntuple_filter->queue = p_2tuple_filter->queue;
4577                 break;
4578         default:
4579                 ret = -EINVAL;
4580                 break;
4581         }
4582
4583         return 0;
4584 }
4585
4586 /*
4587  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4588  * @dev: pointer to rte_eth_dev structure
4589  * @filter_op:operation will be taken.
4590  * @arg: a pointer to specific structure corresponding to the filter_op
4591  */
4592 static int
4593 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4594                                 enum rte_filter_op filter_op,
4595                                 void *arg)
4596 {
4597         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4598         int ret;
4599
4600         MAC_TYPE_FILTER_SUP(hw->mac.type);
4601
4602         if (filter_op == RTE_ETH_FILTER_NOP)
4603                 return 0;
4604
4605         if (arg == NULL) {
4606                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4607                             filter_op);
4608                 return -EINVAL;
4609         }
4610
4611         switch (filter_op) {
4612         case RTE_ETH_FILTER_ADD:
4613                 ret = igb_add_del_ntuple_filter(dev,
4614                         (struct rte_eth_ntuple_filter *)arg,
4615                         TRUE);
4616                 break;
4617         case RTE_ETH_FILTER_DELETE:
4618                 ret = igb_add_del_ntuple_filter(dev,
4619                         (struct rte_eth_ntuple_filter *)arg,
4620                         FALSE);
4621                 break;
4622         case RTE_ETH_FILTER_GET:
4623                 ret = igb_get_ntuple_filter(dev,
4624                         (struct rte_eth_ntuple_filter *)arg);
4625                 break;
4626         default:
4627                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4628                 ret = -EINVAL;
4629                 break;
4630         }
4631         return ret;
4632 }
4633
4634 static inline int
4635 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4636                         uint16_t ethertype)
4637 {
4638         int i;
4639
4640         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4641                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4642                     (filter_info->ethertype_mask & (1 << i)))
4643                         return i;
4644         }
4645         return -1;
4646 }
4647
4648 static inline int
4649 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4650                         uint16_t ethertype, uint32_t etqf)
4651 {
4652         int i;
4653
4654         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4655                 if (!(filter_info->ethertype_mask & (1 << i))) {
4656                         filter_info->ethertype_mask |= 1 << i;
4657                         filter_info->ethertype_filters[i].ethertype = ethertype;
4658                         filter_info->ethertype_filters[i].etqf = etqf;
4659                         return i;
4660                 }
4661         }
4662         return -1;
4663 }
4664
4665 int
4666 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4667                         uint8_t idx)
4668 {
4669         if (idx >= E1000_MAX_ETQF_FILTERS)
4670                 return -1;
4671         filter_info->ethertype_mask &= ~(1 << idx);
4672         filter_info->ethertype_filters[idx].ethertype = 0;
4673         filter_info->ethertype_filters[idx].etqf = 0;
4674         return idx;
4675 }
4676
4677
4678 int
4679 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4680                         struct rte_eth_ethertype_filter *filter,
4681                         bool add)
4682 {
4683         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4684         struct e1000_filter_info *filter_info =
4685                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4686         uint32_t etqf = 0;
4687         int ret;
4688
4689         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4690                 filter->ether_type == ETHER_TYPE_IPv6) {
4691                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4692                         " ethertype filter.", filter->ether_type);
4693                 return -EINVAL;
4694         }
4695
4696         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4697                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4698                 return -EINVAL;
4699         }
4700         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4701                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4702                 return -EINVAL;
4703         }
4704
4705         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4706         if (ret >= 0 && add) {
4707                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4708                             filter->ether_type);
4709                 return -EEXIST;
4710         }
4711         if (ret < 0 && !add) {
4712                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4713                             filter->ether_type);
4714                 return -ENOENT;
4715         }
4716
4717         if (add) {
4718                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4719                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4720                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4721                 ret = igb_ethertype_filter_insert(filter_info,
4722                                 filter->ether_type, etqf);
4723                 if (ret < 0) {
4724                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4725                         return -ENOSYS;
4726                 }
4727         } else {
4728                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4729                 if (ret < 0)
4730                         return -ENOSYS;
4731         }
4732         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4733         E1000_WRITE_FLUSH(hw);
4734
4735         return 0;
4736 }
4737
4738 static int
4739 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4740                         struct rte_eth_ethertype_filter *filter)
4741 {
4742         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4743         struct e1000_filter_info *filter_info =
4744                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4745         uint32_t etqf;
4746         int ret;
4747
4748         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4749         if (ret < 0) {
4750                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4751                             filter->ether_type);
4752                 return -ENOENT;
4753         }
4754
4755         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4756         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4757                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4758                 filter->flags = 0;
4759                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4760                                 E1000_ETQF_QUEUE_SHIFT;
4761                 return 0;
4762         }
4763
4764         return -ENOENT;
4765 }
4766
4767 /*
4768  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4769  * @dev: pointer to rte_eth_dev structure
4770  * @filter_op:operation will be taken.
4771  * @arg: a pointer to specific structure corresponding to the filter_op
4772  */
4773 static int
4774 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4775                                 enum rte_filter_op filter_op,
4776                                 void *arg)
4777 {
4778         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4779         int ret;
4780
4781         MAC_TYPE_FILTER_SUP(hw->mac.type);
4782
4783         if (filter_op == RTE_ETH_FILTER_NOP)
4784                 return 0;
4785
4786         if (arg == NULL) {
4787                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4788                             filter_op);
4789                 return -EINVAL;
4790         }
4791
4792         switch (filter_op) {
4793         case RTE_ETH_FILTER_ADD:
4794                 ret = igb_add_del_ethertype_filter(dev,
4795                         (struct rte_eth_ethertype_filter *)arg,
4796                         TRUE);
4797                 break;
4798         case RTE_ETH_FILTER_DELETE:
4799                 ret = igb_add_del_ethertype_filter(dev,
4800                         (struct rte_eth_ethertype_filter *)arg,
4801                         FALSE);
4802                 break;
4803         case RTE_ETH_FILTER_GET:
4804                 ret = igb_get_ethertype_filter(dev,
4805                         (struct rte_eth_ethertype_filter *)arg);
4806                 break;
4807         default:
4808                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4809                 ret = -EINVAL;
4810                 break;
4811         }
4812         return ret;
4813 }
4814
4815 static int
4816 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4817                      enum rte_filter_type filter_type,
4818                      enum rte_filter_op filter_op,
4819                      void *arg)
4820 {
4821         int ret = 0;
4822
4823         switch (filter_type) {
4824         case RTE_ETH_FILTER_NTUPLE:
4825                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4826                 break;
4827         case RTE_ETH_FILTER_ETHERTYPE:
4828                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4829                 break;
4830         case RTE_ETH_FILTER_SYN:
4831                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4832                 break;
4833         case RTE_ETH_FILTER_FLEXIBLE:
4834                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4835                 break;
4836         case RTE_ETH_FILTER_GENERIC:
4837                 if (filter_op != RTE_ETH_FILTER_GET)
4838                         return -EINVAL;
4839                 *(const void **)arg = &igb_flow_ops;
4840                 break;
4841         default:
4842                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4843                                                         filter_type);
4844                 break;
4845         }
4846
4847         return ret;
4848 }
4849
4850 static int
4851 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4852                          struct ether_addr *mc_addr_set,
4853                          uint32_t nb_mc_addr)
4854 {
4855         struct e1000_hw *hw;
4856
4857         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4858         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4859         return 0;
4860 }
4861
4862 static uint64_t
4863 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4864 {
4865         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4866         uint64_t systime_cycles;
4867
4868         switch (hw->mac.type) {
4869         case e1000_i210:
4870         case e1000_i211:
4871                 /*
4872                  * Need to read System Time Residue Register to be able
4873                  * to read the other two registers.
4874                  */
4875                 E1000_READ_REG(hw, E1000_SYSTIMR);
4876                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4877                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4878                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4879                                 * NSEC_PER_SEC;
4880                 break;
4881         case e1000_82580:
4882         case e1000_i350:
4883         case e1000_i354:
4884                 /*
4885                  * Need to read System Time Residue Register to be able
4886                  * to read the other two registers.
4887                  */
4888                 E1000_READ_REG(hw, E1000_SYSTIMR);
4889                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4890                 /* Only the 8 LSB are valid. */
4891                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4892                                 & 0xff) << 32;
4893                 break;
4894         default:
4895                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4896                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4897                                 << 32;
4898                 break;
4899         }
4900
4901         return systime_cycles;
4902 }
4903
4904 static uint64_t
4905 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4906 {
4907         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4908         uint64_t rx_tstamp_cycles;
4909
4910         switch (hw->mac.type) {
4911         case e1000_i210:
4912         case e1000_i211:
4913                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4914                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4915                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4916                                 * NSEC_PER_SEC;
4917                 break;
4918         case e1000_82580:
4919         case e1000_i350:
4920         case e1000_i354:
4921                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4922                 /* Only the 8 LSB are valid. */
4923                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4924                                 & 0xff) << 32;
4925                 break;
4926         default:
4927                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4928                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4929                                 << 32;
4930                 break;
4931         }
4932
4933         return rx_tstamp_cycles;
4934 }
4935
4936 static uint64_t
4937 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4938 {
4939         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4940         uint64_t tx_tstamp_cycles;
4941
4942         switch (hw->mac.type) {
4943         case e1000_i210:
4944         case e1000_i211:
4945                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4946                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4947                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4948                                 * NSEC_PER_SEC;
4949                 break;
4950         case e1000_82580:
4951         case e1000_i350:
4952         case e1000_i354:
4953                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4954                 /* Only the 8 LSB are valid. */
4955                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4956                                 & 0xff) << 32;
4957                 break;
4958         default:
4959                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4960                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4961                                 << 32;
4962                 break;
4963         }
4964
4965         return tx_tstamp_cycles;
4966 }
4967
4968 static void
4969 igb_start_timecounters(struct rte_eth_dev *dev)
4970 {
4971         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4972         struct e1000_adapter *adapter =
4973                 (struct e1000_adapter *)dev->data->dev_private;
4974         uint32_t incval = 1;
4975         uint32_t shift = 0;
4976         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4977
4978         switch (hw->mac.type) {
4979         case e1000_82580:
4980         case e1000_i350:
4981         case e1000_i354:
4982                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4983                 mask = (1ULL << 40) - 1;
4984                 /* fall-through */
4985         case e1000_i210:
4986         case e1000_i211:
4987                 /*
4988                  * Start incrementing the register
4989                  * used to timestamp PTP packets.
4990                  */
4991                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4992                 break;
4993         case e1000_82576:
4994                 incval = E1000_INCVALUE_82576;
4995                 shift = IGB_82576_TSYNC_SHIFT;
4996                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4997                                 E1000_INCPERIOD_82576 | incval);
4998                 break;
4999         default:
5000                 /* Not supported */
5001                 return;
5002         }
5003
5004         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5005         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5006         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5007
5008         adapter->systime_tc.cc_mask = mask;
5009         adapter->systime_tc.cc_shift = shift;
5010         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5011
5012         adapter->rx_tstamp_tc.cc_mask = mask;
5013         adapter->rx_tstamp_tc.cc_shift = shift;
5014         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5015
5016         adapter->tx_tstamp_tc.cc_mask = mask;
5017         adapter->tx_tstamp_tc.cc_shift = shift;
5018         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5019 }
5020
5021 static int
5022 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5023 {
5024         struct e1000_adapter *adapter =
5025                         (struct e1000_adapter *)dev->data->dev_private;
5026
5027         adapter->systime_tc.nsec += delta;
5028         adapter->rx_tstamp_tc.nsec += delta;
5029         adapter->tx_tstamp_tc.nsec += delta;
5030
5031         return 0;
5032 }
5033
5034 static int
5035 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5036 {
5037         uint64_t ns;
5038         struct e1000_adapter *adapter =
5039                         (struct e1000_adapter *)dev->data->dev_private;
5040
5041         ns = rte_timespec_to_ns(ts);
5042
5043         /* Set the timecounters to a new value. */
5044         adapter->systime_tc.nsec = ns;
5045         adapter->rx_tstamp_tc.nsec = ns;
5046         adapter->tx_tstamp_tc.nsec = ns;
5047
5048         return 0;
5049 }
5050
5051 static int
5052 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5053 {
5054         uint64_t ns, systime_cycles;
5055         struct e1000_adapter *adapter =
5056                         (struct e1000_adapter *)dev->data->dev_private;
5057
5058         systime_cycles = igb_read_systime_cyclecounter(dev);
5059         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5060         *ts = rte_ns_to_timespec(ns);
5061
5062         return 0;
5063 }
5064
5065 static int
5066 igb_timesync_enable(struct rte_eth_dev *dev)
5067 {
5068         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5069         uint32_t tsync_ctl;
5070         uint32_t tsauxc;
5071
5072         /* Stop the timesync system time. */
5073         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5074         /* Reset the timesync system time value. */
5075         switch (hw->mac.type) {
5076         case e1000_82580:
5077         case e1000_i350:
5078         case e1000_i354:
5079         case e1000_i210:
5080         case e1000_i211:
5081                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5082                 /* fall-through */
5083         case e1000_82576:
5084                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5085                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5086                 break;
5087         default:
5088                 /* Not supported. */
5089                 return -ENOTSUP;
5090         }
5091
5092         /* Enable system time for it isn't on by default. */
5093         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5094         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5095         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5096
5097         igb_start_timecounters(dev);
5098
5099         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5100         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5101                         (ETHER_TYPE_1588 |
5102                          E1000_ETQF_FILTER_ENABLE |
5103                          E1000_ETQF_1588));
5104
5105         /* Enable timestamping of received PTP packets. */
5106         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5107         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5108         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5109
5110         /* Enable Timestamping of transmitted PTP packets. */
5111         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5112         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5113         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5114
5115         return 0;
5116 }
5117
5118 static int
5119 igb_timesync_disable(struct rte_eth_dev *dev)
5120 {
5121         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5122         uint32_t tsync_ctl;
5123
5124         /* Disable timestamping of transmitted PTP packets. */
5125         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5126         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5127         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5128
5129         /* Disable timestamping of received PTP packets. */
5130         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5131         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5132         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5133
5134         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5135         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5136
5137         /* Stop incrementating the System Time registers. */
5138         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5139
5140         return 0;
5141 }
5142
5143 static int
5144 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5145                                struct timespec *timestamp,
5146                                uint32_t flags __rte_unused)
5147 {
5148         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5149         struct e1000_adapter *adapter =
5150                         (struct e1000_adapter *)dev->data->dev_private;
5151         uint32_t tsync_rxctl;
5152         uint64_t rx_tstamp_cycles;
5153         uint64_t ns;
5154
5155         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5156         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5157                 return -EINVAL;
5158
5159         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5160         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5161         *timestamp = rte_ns_to_timespec(ns);
5162
5163         return  0;
5164 }
5165
5166 static int
5167 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5168                                struct timespec *timestamp)
5169 {
5170         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5171         struct e1000_adapter *adapter =
5172                         (struct e1000_adapter *)dev->data->dev_private;
5173         uint32_t tsync_txctl;
5174         uint64_t tx_tstamp_cycles;
5175         uint64_t ns;
5176
5177         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5178         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5179                 return -EINVAL;
5180
5181         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5182         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5183         *timestamp = rte_ns_to_timespec(ns);
5184
5185         return  0;
5186 }
5187
5188 static int
5189 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5190 {
5191         int count = 0;
5192         int g_ind = 0;
5193         const struct reg_info *reg_group;
5194
5195         while ((reg_group = igb_regs[g_ind++]))
5196                 count += igb_reg_group_count(reg_group);
5197
5198         return count;
5199 }
5200
5201 static int
5202 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5203 {
5204         int count = 0;
5205         int g_ind = 0;
5206         const struct reg_info *reg_group;
5207
5208         while ((reg_group = igbvf_regs[g_ind++]))
5209                 count += igb_reg_group_count(reg_group);
5210
5211         return count;
5212 }
5213
5214 static int
5215 eth_igb_get_regs(struct rte_eth_dev *dev,
5216         struct rte_dev_reg_info *regs)
5217 {
5218         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5219         uint32_t *data = regs->data;
5220         int g_ind = 0;
5221         int count = 0;
5222         const struct reg_info *reg_group;
5223
5224         if (data == NULL) {
5225                 regs->length = eth_igb_get_reg_length(dev);
5226                 regs->width = sizeof(uint32_t);
5227                 return 0;
5228         }
5229
5230         /* Support only full register dump */
5231         if ((regs->length == 0) ||
5232             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5233                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5234                         hw->device_id;
5235                 while ((reg_group = igb_regs[g_ind++]))
5236                         count += igb_read_regs_group(dev, &data[count],
5237                                                         reg_group);
5238                 return 0;
5239         }
5240
5241         return -ENOTSUP;
5242 }
5243
5244 static int
5245 igbvf_get_regs(struct rte_eth_dev *dev,
5246         struct rte_dev_reg_info *regs)
5247 {
5248         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5249         uint32_t *data = regs->data;
5250         int g_ind = 0;
5251         int count = 0;
5252         const struct reg_info *reg_group;
5253
5254         if (data == NULL) {
5255                 regs->length = igbvf_get_reg_length(dev);
5256                 regs->width = sizeof(uint32_t);
5257                 return 0;
5258         }
5259
5260         /* Support only full register dump */
5261         if ((regs->length == 0) ||
5262             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5263                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5264                         hw->device_id;
5265                 while ((reg_group = igbvf_regs[g_ind++]))
5266                         count += igb_read_regs_group(dev, &data[count],
5267                                                         reg_group);
5268                 return 0;
5269         }
5270
5271         return -ENOTSUP;
5272 }
5273
5274 static int
5275 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5276 {
5277         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5278
5279         /* Return unit is byte count */
5280         return hw->nvm.word_size * 2;
5281 }
5282
5283 static int
5284 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5285         struct rte_dev_eeprom_info *in_eeprom)
5286 {
5287         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5288         struct e1000_nvm_info *nvm = &hw->nvm;
5289         uint16_t *data = in_eeprom->data;
5290         int first, length;
5291
5292         first = in_eeprom->offset >> 1;
5293         length = in_eeprom->length >> 1;
5294         if ((first >= hw->nvm.word_size) ||
5295             ((first + length) >= hw->nvm.word_size))
5296                 return -EINVAL;
5297
5298         in_eeprom->magic = hw->vendor_id |
5299                 ((uint32_t)hw->device_id << 16);
5300
5301         if ((nvm->ops.read) == NULL)
5302                 return -ENOTSUP;
5303
5304         return nvm->ops.read(hw, first, length, data);
5305 }
5306
5307 static int
5308 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5309         struct rte_dev_eeprom_info *in_eeprom)
5310 {
5311         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5312         struct e1000_nvm_info *nvm = &hw->nvm;
5313         uint16_t *data = in_eeprom->data;
5314         int first, length;
5315
5316         first = in_eeprom->offset >> 1;
5317         length = in_eeprom->length >> 1;
5318         if ((first >= hw->nvm.word_size) ||
5319             ((first + length) >= hw->nvm.word_size))
5320                 return -EINVAL;
5321
5322         in_eeprom->magic = (uint32_t)hw->vendor_id |
5323                 ((uint32_t)hw->device_id << 16);
5324
5325         if ((nvm->ops.write) == NULL)
5326                 return -ENOTSUP;
5327         return nvm->ops.write(hw,  first, length, data);
5328 }
5329
5330 static int
5331 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5332 {
5333         struct e1000_hw *hw =
5334                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5335         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5336         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5337         uint32_t vec = E1000_MISC_VEC_ID;
5338
5339         if (rte_intr_allow_others(intr_handle))
5340                 vec = E1000_RX_VEC_START;
5341
5342         uint32_t mask = 1 << (queue_id + vec);
5343
5344         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5345         E1000_WRITE_FLUSH(hw);
5346
5347         return 0;
5348 }
5349
5350 static int
5351 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5352 {
5353         struct e1000_hw *hw =
5354                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5355         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5356         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5357         uint32_t vec = E1000_MISC_VEC_ID;
5358
5359         if (rte_intr_allow_others(intr_handle))
5360                 vec = E1000_RX_VEC_START;
5361
5362         uint32_t mask = 1 << (queue_id + vec);
5363         uint32_t regval;
5364
5365         regval = E1000_READ_REG(hw, E1000_EIMS);
5366         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5367         E1000_WRITE_FLUSH(hw);
5368
5369         rte_intr_enable(intr_handle);
5370
5371         return 0;
5372 }
5373
5374 static void
5375 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5376                    uint8_t index, uint8_t offset)
5377 {
5378         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5379
5380         /* clear bits */
5381         val &= ~((uint32_t)0xFF << offset);
5382
5383         /* write vector and valid bit */
5384         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5385
5386         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5387 }
5388
5389 static void
5390 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5391                            uint8_t queue, uint8_t msix_vector)
5392 {
5393         uint32_t tmp = 0;
5394
5395         if (hw->mac.type == e1000_82575) {
5396                 if (direction == 0)
5397                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5398                 else if (direction == 1)
5399                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5400                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5401         } else if (hw->mac.type == e1000_82576) {
5402                 if ((direction == 0) || (direction == 1))
5403                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5404                                            ((queue & 0x8) << 1) +
5405                                            8 * direction);
5406         } else if ((hw->mac.type == e1000_82580) ||
5407                         (hw->mac.type == e1000_i350) ||
5408                         (hw->mac.type == e1000_i354) ||
5409                         (hw->mac.type == e1000_i210) ||
5410                         (hw->mac.type == e1000_i211)) {
5411                 if ((direction == 0) || (direction == 1))
5412                         eth_igb_write_ivar(hw, msix_vector,
5413                                            queue >> 1,
5414                                            ((queue & 0x1) << 4) +
5415                                            8 * direction);
5416         }
5417 }
5418
5419 /* Sets up the hardware to generate MSI-X interrupts properly
5420  * @hw
5421  *  board private structure
5422  */
5423 static void
5424 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5425 {
5426         int queue_id;
5427         uint32_t tmpval, regval, intr_mask;
5428         struct e1000_hw *hw =
5429                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5430         uint32_t vec = E1000_MISC_VEC_ID;
5431         uint32_t base = E1000_MISC_VEC_ID;
5432         uint32_t misc_shift = 0;
5433         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5434         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5435
5436         /* won't configure msix register if no mapping is done
5437          * between intr vector and event fd
5438          */
5439         if (!rte_intr_dp_is_en(intr_handle))
5440                 return;
5441
5442         if (rte_intr_allow_others(intr_handle)) {
5443                 vec = base = E1000_RX_VEC_START;
5444                 misc_shift = 1;
5445         }
5446
5447         /* set interrupt vector for other causes */
5448         if (hw->mac.type == e1000_82575) {
5449                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5450                 /* enable MSI-X PBA support */
5451                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5452
5453                 /* Auto-Mask interrupts upon ICR read */
5454                 tmpval |= E1000_CTRL_EXT_EIAME;
5455                 tmpval |= E1000_CTRL_EXT_IRCA;
5456
5457                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5458
5459                 /* enable msix_other interrupt */
5460                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5461                 regval = E1000_READ_REG(hw, E1000_EIAC);
5462                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5463                 regval = E1000_READ_REG(hw, E1000_EIAM);
5464                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5465         } else if ((hw->mac.type == e1000_82576) ||
5466                         (hw->mac.type == e1000_82580) ||
5467                         (hw->mac.type == e1000_i350) ||
5468                         (hw->mac.type == e1000_i354) ||
5469                         (hw->mac.type == e1000_i210) ||
5470                         (hw->mac.type == e1000_i211)) {
5471                 /* turn on MSI-X capability first */
5472                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5473                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5474                                         E1000_GPIE_NSICR);
5475                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5476                         misc_shift;
5477                 regval = E1000_READ_REG(hw, E1000_EIAC);
5478                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5479
5480                 /* enable msix_other interrupt */
5481                 regval = E1000_READ_REG(hw, E1000_EIMS);
5482                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5483                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5484                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5485         }
5486
5487         /* use EIAM to auto-mask when MSI-X interrupt
5488          * is asserted, this saves a register write for every interrupt
5489          */
5490         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5491                 misc_shift;
5492         regval = E1000_READ_REG(hw, E1000_EIAM);
5493         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5494
5495         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5496                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5497                 intr_handle->intr_vec[queue_id] = vec;
5498                 if (vec < base + intr_handle->nb_efd - 1)
5499                         vec++;
5500         }
5501
5502         E1000_WRITE_FLUSH(hw);
5503 }
5504
5505 /* restore n-tuple filter */
5506 static inline void
5507 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5508 {
5509         struct e1000_filter_info *filter_info =
5510                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5511         struct e1000_5tuple_filter *p_5tuple;
5512         struct e1000_2tuple_filter *p_2tuple;
5513
5514         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5515                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5516         }
5517
5518         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5519                 igb_inject_2uple_filter(dev, p_2tuple);
5520         }
5521 }
5522
5523 /* restore SYN filter */
5524 static inline void
5525 igb_syn_filter_restore(struct rte_eth_dev *dev)
5526 {
5527         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5528         struct e1000_filter_info *filter_info =
5529                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5530         uint32_t synqf;
5531
5532         synqf = filter_info->syn_info;
5533
5534         if (synqf & E1000_SYN_FILTER_ENABLE) {
5535                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5536                 E1000_WRITE_FLUSH(hw);
5537         }
5538 }
5539
5540 /* restore ethernet type filter */
5541 static inline void
5542 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5543 {
5544         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5545         struct e1000_filter_info *filter_info =
5546                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5547         int i;
5548
5549         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5550                 if (filter_info->ethertype_mask & (1 << i)) {
5551                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5552                                 filter_info->ethertype_filters[i].etqf);
5553                         E1000_WRITE_FLUSH(hw);
5554                 }
5555         }
5556 }
5557
5558 /* restore flex byte filter */
5559 static inline void
5560 igb_flex_filter_restore(struct rte_eth_dev *dev)
5561 {
5562         struct e1000_filter_info *filter_info =
5563                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5564         struct e1000_flex_filter *flex_filter;
5565
5566         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5567                 igb_inject_flex_filter(dev, flex_filter);
5568         }
5569 }
5570
5571 /* restore rss filter */
5572 static inline void
5573 igb_rss_filter_restore(struct rte_eth_dev *dev)
5574 {
5575         struct e1000_filter_info *filter_info =
5576                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5577
5578         if (filter_info->rss_info.num)
5579                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5580 }
5581
5582 /* restore all types filter */
5583 static int
5584 igb_filter_restore(struct rte_eth_dev *dev)
5585 {
5586         igb_ntuple_filter_restore(dev);
5587         igb_ethertype_filter_restore(dev);
5588         igb_syn_filter_restore(dev);
5589         igb_flex_filter_restore(dev);
5590         igb_rss_filter_restore(dev);
5591
5592         return 0;
5593 }
5594
5595 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5596 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5597 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5598 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5599 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5600 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");