drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_string_fns.h>
  12 #include <rte_common.h>
  13 #include <rte_interrupts.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_log.h>
  16 #include <rte_debug.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memory.h>
  23 #include <rte_eal.h>
  24 #include <rte_malloc.h>
  25 #include <rte_dev.h>
  26
  27 #include "e1000_logs.h"
  28 #include "base/e1000_api.h"
  29 #include "e1000_ethdev.h"
  30 #include "igb_regs.h"
  31
  32 /*
  33  * Default values for port configuration
  34  */
  35 #define IGB_DEFAULT_RX_FREE_THRESH  32
  36
  37 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  38 #define IGB_DEFAULT_RX_HTHRESH      8
  39 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  40
  41 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  42 #define IGB_DEFAULT_TX_HTHRESH      1
  43 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  44
  45 /* Bit shift and mask */
  46 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  47 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  48 #define IGB_8_BIT_WIDTH  CHAR_BIT
  49 #define IGB_8_BIT_MASK   UINT8_MAX
  50
  51 /* Additional timesync values. */
  52 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  53 #define E1000_ETQF_FILTER_1588       3
  54 #define IGB_82576_TSYNC_SHIFT        16
  55 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  56 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  58
  59 #define E1000_VTIVAR_MISC                0x01740
  60 #define E1000_VTIVAR_MISC_MASK           0xFF
  61 #define E1000_VTIVAR_VALID               0x80
  62 #define E1000_VTIVAR_MISC_MAILBOX        0
  63 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  64
  65 /* External VLAN Enable bit mask */
  66 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  67
  68 /* External VLAN Ether Type bit mask and shift */
  69 #define E1000_VET_VET_EXT            0xFFFF0000
  70 #define E1000_VET_VET_EXT_SHIFT      16
  71
  72 /* MSI-X other interrupt vector */
  73 #define IGB_MSIX_OTHER_INTR_VEC      0
  74
  75 static int  eth_igb_configure(struct rte_eth_dev *dev);
  76 static int  eth_igb_start(struct rte_eth_dev *dev);
  77 static void eth_igb_stop(struct rte_eth_dev *dev);
  78 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  79 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  80 static int eth_igb_close(struct rte_eth_dev *dev);
  81 static int eth_igb_reset(struct rte_eth_dev *dev);
  82 static int  eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  83 static int  eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  84 static int  eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  85 static int  eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  87                                 int wait_to_complete);
  88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  89                                 struct rte_eth_stats *rte_stats);
  90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  91                               struct rte_eth_xstat *xstats, unsigned n);
  92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  93                 const uint64_t *ids,
  94                 uint64_t *values, unsigned int n);
  95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  96                                     struct rte_eth_xstat_name *xstats_names,
  97                                     unsigned int size);
  98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  99                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 100                 unsigned int limit);
 101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
 102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
 103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 104                                    char *fw_version, size_t fw_size);
 105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
 106                               struct rte_eth_dev_info *dev_info);
 107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_dev_info *dev_info);
 110 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 113                                 struct rte_eth_fc_conf *fc_conf);
 114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 118                                     struct rte_intr_handle *handle);
 119 static void eth_igb_interrupt_handler(void *param);
 120 static int  igb_hardware_init(struct e1000_hw *hw);
 121 static void igb_hw_control_acquire(struct e1000_hw *hw);
 122 static void igb_hw_control_release(struct e1000_hw *hw);
 123 static void igb_init_manageability(struct e1000_hw *hw);
 124 static void igb_release_manageability(struct e1000_hw *hw);
 125
 126 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 127
 128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 129                 uint16_t vlan_id, int on);
 130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 131                                  enum rte_vlan_type vlan_type,
 132                                  uint16_t tpid_id);
 133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134
 135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 141
 142 static int eth_igb_led_on(struct rte_eth_dev *dev);
 143 static int eth_igb_led_off(struct rte_eth_dev *dev);
 144
 145 static void igb_intr_disable(struct rte_eth_dev *dev);
 146 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 148                            struct rte_ether_addr *mac_addr,
 149                            uint32_t index, uint32_t pool);
 150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 152                 struct rte_ether_addr *addr);
 153
 154 static void igbvf_intr_disable(struct e1000_hw *hw);
 155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 156 static int igbvf_dev_start(struct rte_eth_dev *dev);
 157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 158 static int igbvf_dev_close(struct rte_eth_dev *dev);
 159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 163 static int eth_igbvf_link_update(struct e1000_hw *hw);
 164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_stats *rte_stats);
 166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 167                                 struct rte_eth_xstat *xstats, unsigned n);
 168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 169                                       struct rte_eth_xstat_name *xstats_names,
 170                                       unsigned limit);
 171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 173                 uint16_t vlan_id, int on);
 174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 177                 struct rte_ether_addr *addr);
 178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 179 static int igbvf_get_regs(struct rte_eth_dev *dev,
 180                 struct rte_dev_reg_info *regs);
 181
 182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 183                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                    uint16_t reta_size);
 185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 186                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 187                                   uint16_t reta_size);
 188
 189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 190                         struct rte_eth_syn_filter *filter);
 191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 192                         enum rte_filter_op filter_op,
 193                         void *arg);
 194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_ntuple_filter *ntuple_filter);
 198 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 199                         struct rte_eth_flex_filter *filter);
 200 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 201                         enum rte_filter_op filter_op,
 202                         void *arg);
 203 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 204                         struct rte_eth_ntuple_filter *ntuple_filter);
 205 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 206                         struct rte_eth_ntuple_filter *ntuple_filter);
 207 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 208                         struct rte_eth_ntuple_filter *filter);
 209 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 213                                 enum rte_filter_op filter_op,
 214                                 void *arg);
 215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ethertype_filter *filter);
 217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 218                      enum rte_filter_type filter_type,
 219                      enum rte_filter_op filter_op,
 220                      void *arg);
 221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 223                 struct rte_dev_reg_info *regs);
 224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 226                 struct rte_dev_eeprom_info *eeprom);
 227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 228                 struct rte_dev_eeprom_info *eeprom);
 229 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
 230                                    struct rte_eth_dev_module_info *modinfo);
 231 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
 232                                      struct rte_dev_eeprom_info *info);
 233 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 234                                     struct rte_ether_addr *mc_addr_set,
 235                                     uint32_t nb_mc_addr);
 236 static int igb_timesync_enable(struct rte_eth_dev *dev);
 237 static int igb_timesync_disable(struct rte_eth_dev *dev);
 238 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 239                                           struct timespec *timestamp,
 240                                           uint32_t flags);
 241 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 242                                           struct timespec *timestamp);
 243 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 244 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 245                                   struct timespec *timestamp);
 246 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 247                                    const struct timespec *timestamp);
 248 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 249                                         uint16_t queue_id);
 250 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 251                                          uint16_t queue_id);
 252 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 253                                        uint8_t queue, uint8_t msix_vector);
 254 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 255                                uint8_t index, uint8_t offset);
 256 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 257 static void eth_igbvf_interrupt_handler(void *param);
 258 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 259 static int igb_filter_restore(struct rte_eth_dev *dev);
 260
 261 /*
 262  * Define VF Stats MACRO for Non "cleared on read" register
 263  */
 264 #define UPDATE_VF_STAT(reg, last, cur)            \
 265 {                                                 \
 266         u32 latest = E1000_READ_REG(hw, reg);     \
 267         cur += (latest - last) & UINT_MAX;        \
 268         last = latest;                            \
 269 }
 270
 271 #define IGB_FC_PAUSE_TIME 0x0680
 272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 274
 275 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 276
 277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 278
 279 /*
 280  * The set of PCI devices this driver supports
 281  */
 282 static const struct rte_pci_id pci_id_igb_map[] = {
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 284         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 285         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 286         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 287         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 288         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 289         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 290         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 291
 292         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 295
 296         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 297         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 302
 303         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 304         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 305         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 324         { .vendor_id = 0, /* sentinel */ },
 325 };
 326
 327 /*
 328  * The set of PCI devices this driver supports (for 82576&I350 VF)
 329  */
 330 static const struct rte_pci_id pci_id_igbvf_map[] = {
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 335         { .vendor_id = 0, /* sentinel */ },
 336 };
 337
 338 static const struct rte_eth_desc_lim rx_desc_lim = {
 339         .nb_max = E1000_MAX_RING_DESC,
 340         .nb_min = E1000_MIN_RING_DESC,
 341         .nb_align = IGB_RXD_ALIGN,
 342 };
 343
 344 static const struct rte_eth_desc_lim tx_desc_lim = {
 345         .nb_max = E1000_MAX_RING_DESC,
 346         .nb_min = E1000_MIN_RING_DESC,
 347         .nb_align = IGB_RXD_ALIGN,
 348         .nb_seg_max = IGB_TX_MAX_SEG,
 349         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 350 };
 351
 352 static const struct eth_dev_ops eth_igb_ops = {
 353         .dev_configure        = eth_igb_configure,
 354         .dev_start            = eth_igb_start,
 355         .dev_stop             = eth_igb_stop,
 356         .dev_set_link_up      = eth_igb_dev_set_link_up,
 357         .dev_set_link_down    = eth_igb_dev_set_link_down,
 358         .dev_close            = eth_igb_close,
 359         .dev_reset            = eth_igb_reset,
 360         .promiscuous_enable   = eth_igb_promiscuous_enable,
 361         .promiscuous_disable  = eth_igb_promiscuous_disable,
 362         .allmulticast_enable  = eth_igb_allmulticast_enable,
 363         .allmulticast_disable = eth_igb_allmulticast_disable,
 364         .link_update          = eth_igb_link_update,
 365         .stats_get            = eth_igb_stats_get,
 366         .xstats_get           = eth_igb_xstats_get,
 367         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 368         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 369         .xstats_get_names     = eth_igb_xstats_get_names,
 370         .stats_reset          = eth_igb_stats_reset,
 371         .xstats_reset         = eth_igb_xstats_reset,
 372         .fw_version_get       = eth_igb_fw_version_get,
 373         .dev_infos_get        = eth_igb_infos_get,
 374         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 375         .mtu_set              = eth_igb_mtu_set,
 376         .vlan_filter_set      = eth_igb_vlan_filter_set,
 377         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 378         .vlan_offload_set     = eth_igb_vlan_offload_set,
 379         .rx_queue_setup       = eth_igb_rx_queue_setup,
 380         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 381         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 382         .rx_queue_release     = eth_igb_rx_queue_release,
 383         .tx_queue_setup       = eth_igb_tx_queue_setup,
 384         .tx_queue_release     = eth_igb_tx_queue_release,
 385         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 386         .dev_led_on           = eth_igb_led_on,
 387         .dev_led_off          = eth_igb_led_off,
 388         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 389         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 390         .mac_addr_add         = eth_igb_rar_set,
 391         .mac_addr_remove      = eth_igb_rar_clear,
 392         .mac_addr_set         = eth_igb_default_mac_addr_set,
 393         .reta_update          = eth_igb_rss_reta_update,
 394         .reta_query           = eth_igb_rss_reta_query,
 395         .rss_hash_update      = eth_igb_rss_hash_update,
 396         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 397         .filter_ctrl          = eth_igb_filter_ctrl,
 398         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 399         .rxq_info_get         = igb_rxq_info_get,
 400         .txq_info_get         = igb_txq_info_get,
 401         .timesync_enable      = igb_timesync_enable,
 402         .timesync_disable     = igb_timesync_disable,
 403         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 404         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 405         .get_reg              = eth_igb_get_regs,
 406         .get_eeprom_length    = eth_igb_get_eeprom_length,
 407         .get_eeprom           = eth_igb_get_eeprom,
 408         .set_eeprom           = eth_igb_set_eeprom,
 409         .get_module_info      = eth_igb_get_module_info,
 410         .get_module_eeprom    = eth_igb_get_module_eeprom,
 411         .timesync_adjust_time = igb_timesync_adjust_time,
 412         .timesync_read_time   = igb_timesync_read_time,
 413         .timesync_write_time  = igb_timesync_write_time,
 414 };
 415
 416 /*
 417  * dev_ops for virtual function, bare necessities for basic vf
 418  * operation have been implemented
 419  */
 420 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 421         .dev_configure        = igbvf_dev_configure,
 422         .dev_start            = igbvf_dev_start,
 423         .dev_stop             = igbvf_dev_stop,
 424         .dev_close            = igbvf_dev_close,
 425         .promiscuous_enable   = igbvf_promiscuous_enable,
 426         .promiscuous_disable  = igbvf_promiscuous_disable,
 427         .allmulticast_enable  = igbvf_allmulticast_enable,
 428         .allmulticast_disable = igbvf_allmulticast_disable,
 429         .link_update          = eth_igb_link_update,
 430         .stats_get            = eth_igbvf_stats_get,
 431         .xstats_get           = eth_igbvf_xstats_get,
 432         .xstats_get_names     = eth_igbvf_xstats_get_names,
 433         .stats_reset          = eth_igbvf_stats_reset,
 434         .xstats_reset         = eth_igbvf_stats_reset,
 435         .vlan_filter_set      = igbvf_vlan_filter_set,
 436         .dev_infos_get        = eth_igbvf_infos_get,
 437         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 438         .rx_queue_setup       = eth_igb_rx_queue_setup,
 439         .rx_queue_release     = eth_igb_rx_queue_release,
 440         .tx_queue_setup       = eth_igb_tx_queue_setup,
 441         .tx_queue_release     = eth_igb_tx_queue_release,
 442         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 443         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 444         .rxq_info_get         = igb_rxq_info_get,
 445         .txq_info_get         = igb_txq_info_get,
 446         .mac_addr_set         = igbvf_default_mac_addr_set,
 447         .get_reg              = igbvf_get_regs,
 448 };
 449
 450 /* store statistics names and its offset in stats structure */
 451 struct rte_igb_xstats_name_off {
 452         char name[RTE_ETH_XSTATS_NAME_SIZE];
 453         unsigned offset;
 454 };
 455
 456 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 457         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 458         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 459         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 460         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 461         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 462         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 463         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 464                 ecol)},
 465         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 466         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 467         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 468         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 469         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 470         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 471         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 472         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 473         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 474         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 475         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 476                 fcruc)},
 477         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 478         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 479         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 480         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 481         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 482                 prc1023)},
 483         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 484                 prc1522)},
 485         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 486         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 487         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 488         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 489         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 490         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 491         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 492         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 493         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 494         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 495         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 496         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 497         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 498         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 499         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 500         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 501         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 502         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 503                 ptc1023)},
 504         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 505                 ptc1522)},
 506         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 507         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 508         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 509         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 510         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 511         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 512         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 513
 514         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 515 };
 516
 517 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 518                 sizeof(rte_igb_stats_strings[0]))
 519
 520 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 521         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 522         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 523         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 524         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 525         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 526 };
 527
 528 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 529                 sizeof(rte_igbvf_stats_strings[0]))
 530
 531
 532 static inline void
 533 igb_intr_enable(struct rte_eth_dev *dev)
 534 {
 535         struct e1000_interrupt *intr =
 536                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 537         struct e1000_hw *hw =
 538                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 539         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 540         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 541
 542         if (rte_intr_allow_others(intr_handle) &&
 543                 dev->data->dev_conf.intr_conf.lsc != 0) {
 544                 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
 545         }
 546
 547         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 548         E1000_WRITE_FLUSH(hw);
 549 }
 550
 551 static void
 552 igb_intr_disable(struct rte_eth_dev *dev)
 553 {
 554         struct e1000_hw *hw =
 555                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 556         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 557         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 558
 559         if (rte_intr_allow_others(intr_handle) &&
 560                 dev->data->dev_conf.intr_conf.lsc != 0) {
 561                 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
 562         }
 563
 564         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 565         E1000_WRITE_FLUSH(hw);
 566 }
 567
 568 static inline void
 569 igbvf_intr_enable(struct rte_eth_dev *dev)
 570 {
 571         struct e1000_hw *hw =
 572                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 573
 574         /* only for mailbox */
 575         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 576         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 577         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 578         E1000_WRITE_FLUSH(hw);
 579 }
 580
 581 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 582 static void
 583 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 584 {
 585         uint32_t tmp = 0;
 586
 587         /* mailbox */
 588         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 589         tmp |= E1000_VTIVAR_VALID;
 590         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 591 }
 592
 593 static void
 594 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 595 {
 596         struct e1000_hw *hw =
 597                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 598
 599         /* Configure VF other cause ivar */
 600         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 601 }
 602
 603 static inline int32_t
 604 igb_pf_reset_hw(struct e1000_hw *hw)
 605 {
 606         uint32_t ctrl_ext;
 607         int32_t status;
 608
 609         status = e1000_reset_hw(hw);
 610
 611         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 612         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 613         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 614         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 615         E1000_WRITE_FLUSH(hw);
 616
 617         return status;
 618 }
 619
 620 static void
 621 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 622 {
 623         struct e1000_hw *hw =
 624                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 625
 626
 627         hw->vendor_id = pci_dev->id.vendor_id;
 628         hw->device_id = pci_dev->id.device_id;
 629         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 630         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 631
 632         e1000_set_mac_type(hw);
 633
 634         /* need to check if it is a vf device below */
 635 }
 636
 637 static int
 638 igb_reset_swfw_lock(struct e1000_hw *hw)
 639 {
 640         int ret_val;
 641
 642         /*
 643          * Do mac ops initialization manually here, since we will need
 644          * some function pointers set by this call.
 645          */
 646         ret_val = e1000_init_mac_params(hw);
 647         if (ret_val)
 648                 return ret_val;
 649
 650         /*
 651          * SMBI lock should not fail in this early stage. If this is the case,
 652          * it is due to an improper exit of the application.
 653          * So force the release of the faulty lock.
 654          */
 655         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 656                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 657         }
 658         e1000_put_hw_semaphore_generic(hw);
 659
 660         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 661                 uint16_t mask;
 662
 663                 /*
 664                  * Phy lock should not fail in this early stage. If this is the case,
 665                  * it is due to an improper exit of the application.
 666                  * So force the release of the faulty lock.
 667                  */
 668                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 669                 if (hw->bus.func > E1000_FUNC_1)
 670                         mask <<= 2;
 671                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 672                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 673                                     hw->bus.func);
 674                 }
 675                 hw->mac.ops.release_swfw_sync(hw, mask);
 676
 677                 /*
 678                  * This one is more tricky since it is common to all ports; but
 679                  * swfw_sync retries last long enough (1s) to be almost sure that if
 680                  * lock can not be taken it is due to an improper lock of the
 681                  * semaphore.
 682                  */
 683                 mask = E1000_SWFW_EEP_SM;
 684                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 685                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 686                 }
 687                 hw->mac.ops.release_swfw_sync(hw, mask);
 688         }
 689
 690         return E1000_SUCCESS;
 691 }
 692
 693 /* Remove all ntuple filters of the device */
 694 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 695 {
 696         struct e1000_filter_info *filter_info =
 697                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 698         struct e1000_5tuple_filter *p_5tuple;
 699         struct e1000_2tuple_filter *p_2tuple;
 700
 701         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 702                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 703                         p_5tuple, entries);
 704                         rte_free(p_5tuple);
 705         }
 706         filter_info->fivetuple_mask = 0;
 707         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 708                 TAILQ_REMOVE(&filter_info->twotuple_list,
 709                         p_2tuple, entries);
 710                         rte_free(p_2tuple);
 711         }
 712         filter_info->twotuple_mask = 0;
 713
 714         return 0;
 715 }
 716
 717 /* Remove all flex filters of the device */
 718 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 719 {
 720         struct e1000_filter_info *filter_info =
 721                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 722         struct e1000_flex_filter *p_flex;
 723
 724         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 725                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 726                 rte_free(p_flex);
 727         }
 728         filter_info->flex_mask = 0;
 729
 730         return 0;
 731 }
 732
 733 static int
 734 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 735 {
 736         int error = 0;
 737         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 738         struct e1000_hw *hw =
 739                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 740         struct e1000_vfta * shadow_vfta =
 741                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 742         struct e1000_filter_info *filter_info =
 743                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 744         struct e1000_adapter *adapter =
 745                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 746
 747         uint32_t ctrl_ext;
 748
 749         eth_dev->dev_ops = &eth_igb_ops;
 750         eth_dev->rx_queue_count = eth_igb_rx_queue_count;
 751         eth_dev->rx_descriptor_done   = eth_igb_rx_descriptor_done;
 752         eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
 753         eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
 754         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 755         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 756         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 757
 758         /* for secondary processes, we don't initialise any further as primary
 759          * has already done this work. Only check we don't need a different
 760          * RX function */
 761         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 762                 if (eth_dev->data->scattered_rx)
 763                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 764                 return 0;
 765         }
 766
 767         rte_eth_copy_pci_info(eth_dev, pci_dev);
 768
 769         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 770
 771         igb_identify_hardware(eth_dev, pci_dev);
 772         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 773                 error = -EIO;
 774                 goto err_late;
 775         }
 776
 777         e1000_get_bus_info(hw);
 778
 779         /* Reset any pending lock */
 780         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 781                 error = -EIO;
 782                 goto err_late;
 783         }
 784
 785         /* Finish initialization */
 786         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 787                 error = -EIO;
 788                 goto err_late;
 789         }
 790
 791         hw->mac.autoneg = 1;
 792         hw->phy.autoneg_wait_to_complete = 0;
 793         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 794
 795         /* Copper options */
 796         if (hw->phy.media_type == e1000_media_type_copper) {
 797                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 798                 hw->phy.disable_polarity_correction = 0;
 799                 hw->phy.ms_type = e1000_ms_hw_default;
 800         }
 801
 802         /*
 803          * Start from a known state, this is important in reading the nvm
 804          * and mac from that.
 805          */
 806         igb_pf_reset_hw(hw);
 807
 808         /* Make sure we have a good EEPROM before we read from it */
 809         if (e1000_validate_nvm_checksum(hw) < 0) {
 810                 /*
 811                  * Some PCI-E parts fail the first check due to
 812                  * the link being in sleep state, call it again,
 813                  * if it fails a second time its a real issue.
 814                  */
 815                 if (e1000_validate_nvm_checksum(hw) < 0) {
 816                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 817                         error = -EIO;
 818                         goto err_late;
 819                 }
 820         }
 821
 822         /* Read the permanent MAC address out of the EEPROM */
 823         if (e1000_read_mac_addr(hw) != 0) {
 824                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 825                 error = -EIO;
 826                 goto err_late;
 827         }
 828
 829         /* Allocate memory for storing MAC addresses */
 830         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 831                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 832         if (eth_dev->data->mac_addrs == NULL) {
 833                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 834                                                 "store MAC addresses",
 835                                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 836                 error = -ENOMEM;
 837                 goto err_late;
 838         }
 839
 840         /* Copy the permanent MAC address */
 841         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 842                         &eth_dev->data->mac_addrs[0]);
 843
 844         /* initialize the vfta */
 845         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 846
 847         /* Now initialize the hardware */
 848         if (igb_hardware_init(hw) != 0) {
 849                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 850                 rte_free(eth_dev->data->mac_addrs);
 851                 eth_dev->data->mac_addrs = NULL;
 852                 error = -ENODEV;
 853                 goto err_late;
 854         }
 855         hw->mac.get_link_status = 1;
 856         adapter->stopped = 0;
 857
 858         /* Indicate SOL/IDER usage */
 859         if (e1000_check_reset_block(hw) < 0) {
 860                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 861                                         "SOL/IDER session");
 862         }
 863
 864         /* initialize PF if max_vfs not zero */
 865         igb_pf_host_init(eth_dev);
 866
 867         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 868         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 869         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 870         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 871         E1000_WRITE_FLUSH(hw);
 872
 873         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 874                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 875                      pci_dev->id.device_id);
 876
 877         rte_intr_callback_register(&pci_dev->intr_handle,
 878                                    eth_igb_interrupt_handler,
 879                                    (void *)eth_dev);
 880
 881         /* enable uio/vfio intr/eventfd mapping */
 882         rte_intr_enable(&pci_dev->intr_handle);
 883
 884         /* enable support intr */
 885         igb_intr_enable(eth_dev);
 886
 887         eth_igb_dev_set_link_down(eth_dev);
 888
 889         /* initialize filter info */
 890         memset(filter_info, 0,
 891                sizeof(struct e1000_filter_info));
 892
 893         TAILQ_INIT(&filter_info->flex_list);
 894         TAILQ_INIT(&filter_info->twotuple_list);
 895         TAILQ_INIT(&filter_info->fivetuple_list);
 896
 897         TAILQ_INIT(&igb_filter_ntuple_list);
 898         TAILQ_INIT(&igb_filter_ethertype_list);
 899         TAILQ_INIT(&igb_filter_syn_list);
 900         TAILQ_INIT(&igb_filter_flex_list);
 901         TAILQ_INIT(&igb_filter_rss_list);
 902         TAILQ_INIT(&igb_flow_list);
 903
 904         return 0;
 905
 906 err_late:
 907         igb_hw_control_release(hw);
 908
 909         return error;
 910 }
 911
 912 static int
 913 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 914 {
 915         PMD_INIT_FUNC_TRACE();
 916
 917         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 918                 return 0;
 919
 920         eth_igb_close(eth_dev);
 921
 922         return 0;
 923 }
 924
 925 /*
 926  * Virtual Function device init
 927  */
 928 static int
 929 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 930 {
 931         struct rte_pci_device *pci_dev;
 932         struct rte_intr_handle *intr_handle;
 933         struct e1000_adapter *adapter =
 934                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 935         struct e1000_hw *hw =
 936                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 937         int diag;
 938         struct rte_ether_addr *perm_addr =
 939                 (struct rte_ether_addr *)hw->mac.perm_addr;
 940
 941         PMD_INIT_FUNC_TRACE();
 942
 943         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 944         eth_dev->rx_descriptor_done   = eth_igb_rx_descriptor_done;
 945         eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
 946         eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
 947         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 948         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 949         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 950
 951         /* for secondary processes, we don't initialise any further as primary
 952          * has already done this work. Only check we don't need a different
 953          * RX function */
 954         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 955                 if (eth_dev->data->scattered_rx)
 956                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 957                 return 0;
 958         }
 959
 960         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 961         rte_eth_copy_pci_info(eth_dev, pci_dev);
 962
 963         hw->device_id = pci_dev->id.device_id;
 964         hw->vendor_id = pci_dev->id.vendor_id;
 965         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 966         adapter->stopped = 0;
 967
 968         /* Initialize the shared code (base driver) */
 969         diag = e1000_setup_init_funcs(hw, TRUE);
 970         if (diag != 0) {
 971                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 972                         diag);
 973                 return -EIO;
 974         }
 975
 976         /* init_mailbox_params */
 977         hw->mbx.ops.init_params(hw);
 978
 979         /* Disable the interrupts for VF */
 980         igbvf_intr_disable(hw);
 981
 982         diag = hw->mac.ops.reset_hw(hw);
 983
 984         /* Allocate memory for storing MAC addresses */
 985         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
 986                 hw->mac.rar_entry_count, 0);
 987         if (eth_dev->data->mac_addrs == NULL) {
 988                 PMD_INIT_LOG(ERR,
 989                         "Failed to allocate %d bytes needed to store MAC "
 990                         "addresses",
 991                         RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 992                 return -ENOMEM;
 993         }
 994
 995         /* Generate a random MAC address, if none was assigned by PF. */
 996         if (rte_is_zero_ether_addr(perm_addr)) {
 997                 rte_eth_random_addr(perm_addr->addr_bytes);
 998                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
 999                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1000                              "%02x:%02x:%02x:%02x:%02x:%02x",
1001                              perm_addr->addr_bytes[0],
1002                              perm_addr->addr_bytes[1],
1003                              perm_addr->addr_bytes[2],
1004                              perm_addr->addr_bytes[3],
1005                              perm_addr->addr_bytes[4],
1006                              perm_addr->addr_bytes[5]);
1007         }
1008
1009         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1010         if (diag) {
1011                 rte_free(eth_dev->data->mac_addrs);
1012                 eth_dev->data->mac_addrs = NULL;
1013                 return diag;
1014         }
1015         /* Copy the permanent MAC address */
1016         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1017                         &eth_dev->data->mac_addrs[0]);
1018
1019         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1020                      "mac.type=%s",
1021                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1022                      pci_dev->id.device_id, "igb_mac_82576_vf");
1023
1024         intr_handle = &pci_dev->intr_handle;
1025         rte_intr_callback_register(intr_handle,
1026                                    eth_igbvf_interrupt_handler, eth_dev);
1027
1028         return 0;
1029 }
1030
1031 static int
1032 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1033 {
1034         PMD_INIT_FUNC_TRACE();
1035
1036         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1037                 return 0;
1038
1039         igbvf_dev_close(eth_dev);
1040
1041         return 0;
1042 }
1043
1044 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1045         struct rte_pci_device *pci_dev)
1046 {
1047         return rte_eth_dev_pci_generic_probe(pci_dev,
1048                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1049 }
1050
1051 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1052 {
1053         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1054 }
1055
1056 static struct rte_pci_driver rte_igb_pmd = {
1057         .id_table = pci_id_igb_map,
1058         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1059         .probe = eth_igb_pci_probe,
1060         .remove = eth_igb_pci_remove,
1061 };
1062
1063
1064 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1065         struct rte_pci_device *pci_dev)
1066 {
1067         return rte_eth_dev_pci_generic_probe(pci_dev,
1068                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1069 }
1070
1071 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1072 {
1073         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1074 }
1075
1076 /*
1077  * virtual function driver struct
1078  */
1079 static struct rte_pci_driver rte_igbvf_pmd = {
1080         .id_table = pci_id_igbvf_map,
1081         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1082         .probe = eth_igbvf_pci_probe,
1083         .remove = eth_igbvf_pci_remove,
1084 };
1085
1086 static void
1087 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1088 {
1089         struct e1000_hw *hw =
1090                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1091         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1092         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1093         rctl |= E1000_RCTL_VFE;
1094         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1095 }
1096
1097 static int
1098 igb_check_mq_mode(struct rte_eth_dev *dev)
1099 {
1100         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1101         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1102         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1103         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1104
1105         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1106             tx_mq_mode == ETH_MQ_TX_DCB ||
1107             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1108                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1109                 return -EINVAL;
1110         }
1111         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1112                 /* Check multi-queue mode.
1113                  * To no break software we accept ETH_MQ_RX_NONE as this might
1114                  * be used to turn off VLAN filter.
1115                  */
1116
1117                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1118                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1119                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1120                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1121                 } else {
1122                         /* Only support one queue on VFs.
1123                          * RSS together with SRIOV is not supported.
1124                          */
1125                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1126                                         " wrong mq_mode rx %d.",
1127                                         rx_mq_mode);
1128                         return -EINVAL;
1129                 }
1130                 /* TX mode is not used here, so mode might be ignored.*/
1131                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1132                         /* SRIOV only works in VMDq enable mode */
1133                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1134                                         " TX mode %d is not supported. "
1135                                         " Driver will behave as %d mode.",
1136                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1137                 }
1138
1139                 /* check valid queue number */
1140                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1141                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1142                                         " only support one queue on VFs.");
1143                         return -EINVAL;
1144                 }
1145         } else {
1146                 /* To no break software that set invalid mode, only display
1147                  * warning if invalid mode is used.
1148                  */
1149                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1150                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1151                     rx_mq_mode != ETH_MQ_RX_RSS) {
1152                         /* RSS together with VMDq not supported*/
1153                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1154                                      rx_mq_mode);
1155                         return -EINVAL;
1156                 }
1157
1158                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1159                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1160                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1161                                         " Due to txmode is meaningless in this"
1162                                         " driver, just ignore.",
1163                                         tx_mq_mode);
1164                 }
1165         }
1166         return 0;
1167 }
1168
1169 static int
1170 eth_igb_configure(struct rte_eth_dev *dev)
1171 {
1172         struct e1000_interrupt *intr =
1173                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1174         int ret;
1175
1176         PMD_INIT_FUNC_TRACE();
1177
1178         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1179                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1180
1181         /* multipe queue mode checking */
1182         ret  = igb_check_mq_mode(dev);
1183         if (ret != 0) {
1184                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1185                             ret);
1186                 return ret;
1187         }
1188
1189         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1190         PMD_INIT_FUNC_TRACE();
1191
1192         return 0;
1193 }
1194
1195 static void
1196 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1197                      bool enable)
1198 {
1199         struct e1000_hw *hw =
1200                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1201         uint32_t tctl, rctl;
1202
1203         tctl = E1000_READ_REG(hw, E1000_TCTL);
1204         rctl = E1000_READ_REG(hw, E1000_RCTL);
1205
1206         if (enable) {
1207                 /* enable Tx/Rx */
1208                 tctl |= E1000_TCTL_EN;
1209                 rctl |= E1000_RCTL_EN;
1210         } else {
1211                 /* disable Tx/Rx */
1212                 tctl &= ~E1000_TCTL_EN;
1213                 rctl &= ~E1000_RCTL_EN;
1214         }
1215         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1216         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1217         E1000_WRITE_FLUSH(hw);
1218 }
1219
1220 static int
1221 eth_igb_start(struct rte_eth_dev *dev)
1222 {
1223         struct e1000_hw *hw =
1224                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1225         struct e1000_adapter *adapter =
1226                 E1000_DEV_PRIVATE(dev->data->dev_private);
1227         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1228         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1229         int ret, mask;
1230         uint32_t intr_vector = 0;
1231         uint32_t ctrl_ext;
1232         uint32_t *speeds;
1233         int num_speeds;
1234         bool autoneg;
1235
1236         PMD_INIT_FUNC_TRACE();
1237
1238         /* disable uio/vfio intr/eventfd mapping */
1239         rte_intr_disable(intr_handle);
1240
1241         /* Power up the phy. Needed to make the link go Up */
1242         eth_igb_dev_set_link_up(dev);
1243
1244         /*
1245          * Packet Buffer Allocation (PBA)
1246          * Writing PBA sets the receive portion of the buffer
1247          * the remainder is used for the transmit buffer.
1248          */
1249         if (hw->mac.type == e1000_82575) {
1250                 uint32_t pba;
1251
1252                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1253                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1254         }
1255
1256         /* Put the address into the Receive Address Array */
1257         e1000_rar_set(hw, hw->mac.addr, 0);
1258
1259         /* Initialize the hardware */
1260         if (igb_hardware_init(hw)) {
1261                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1262                 return -EIO;
1263         }
1264         adapter->stopped = 0;
1265
1266         E1000_WRITE_REG(hw, E1000_VET,
1267                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1268
1269         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1270         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1271         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1272         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1273         E1000_WRITE_FLUSH(hw);
1274
1275         /* configure PF module if SRIOV enabled */
1276         igb_pf_host_configure(dev);
1277
1278         /* check and configure queue intr-vector mapping */
1279         if ((rte_intr_cap_multiple(intr_handle) ||
1280              !RTE_ETH_DEV_SRIOV(dev).active) &&
1281             dev->data->dev_conf.intr_conf.rxq != 0) {
1282                 intr_vector = dev->data->nb_rx_queues;
1283                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1284                         return -1;
1285         }
1286
1287         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1288                 intr_handle->intr_vec =
1289                         rte_zmalloc("intr_vec",
1290                                     dev->data->nb_rx_queues * sizeof(int), 0);
1291                 if (intr_handle->intr_vec == NULL) {
1292                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1293                                      " intr_vec", dev->data->nb_rx_queues);
1294                         return -ENOMEM;
1295                 }
1296         }
1297
1298         /* confiugre msix for rx interrupt */
1299         eth_igb_configure_msix_intr(dev);
1300
1301         /* Configure for OS presence */
1302         igb_init_manageability(hw);
1303
1304         eth_igb_tx_init(dev);
1305
1306         /* This can fail when allocating mbufs for descriptor rings */
1307         ret = eth_igb_rx_init(dev);
1308         if (ret) {
1309                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1310                 igb_dev_clear_queues(dev);
1311                 return ret;
1312         }
1313
1314         e1000_clear_hw_cntrs_base_generic(hw);
1315
1316         /*
1317          * VLAN Offload Settings
1318          */
1319         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1320                         ETH_VLAN_EXTEND_MASK;
1321         ret = eth_igb_vlan_offload_set(dev, mask);
1322         if (ret) {
1323                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1324                 igb_dev_clear_queues(dev);
1325                 return ret;
1326         }
1327
1328         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1329                 /* Enable VLAN filter since VMDq always use VLAN filter */
1330                 igb_vmdq_vlan_hw_filter_enable(dev);
1331         }
1332
1333         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1334                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1335                 (hw->mac.type == e1000_i211)) {
1336                 /* Configure EITR with the maximum possible value (0xFFFF) */
1337                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1338         }
1339
1340         /* Setup link speed and duplex */
1341         speeds = &dev->data->dev_conf.link_speeds;
1342         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1343                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1344                 hw->mac.autoneg = 1;
1345         } else {
1346                 num_speeds = 0;
1347                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1348
1349                 /* Reset */
1350                 hw->phy.autoneg_advertised = 0;
1351
1352                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1353                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1354                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1355                         num_speeds = -1;
1356                         goto error_invalid_config;
1357                 }
1358                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1359                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1360                         num_speeds++;
1361                 }
1362                 if (*speeds & ETH_LINK_SPEED_10M) {
1363                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1364                         num_speeds++;
1365                 }
1366                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1367                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1368                         num_speeds++;
1369                 }
1370                 if (*speeds & ETH_LINK_SPEED_100M) {
1371                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1372                         num_speeds++;
1373                 }
1374                 if (*speeds & ETH_LINK_SPEED_1G) {
1375                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1376                         num_speeds++;
1377                 }
1378                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1379                         goto error_invalid_config;
1380
1381                 /* Set/reset the mac.autoneg based on the link speed,
1382                  * fixed or not
1383                  */
1384                 if (!autoneg) {
1385                         hw->mac.autoneg = 0;
1386                         hw->mac.forced_speed_duplex =
1387                                         hw->phy.autoneg_advertised;
1388                 } else {
1389                         hw->mac.autoneg = 1;
1390                 }
1391         }
1392
1393         e1000_setup_link(hw);
1394
1395         if (rte_intr_allow_others(intr_handle)) {
1396                 /* check if lsc interrupt is enabled */
1397                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1398                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1399                 else
1400                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1401         } else {
1402                 rte_intr_callback_unregister(intr_handle,
1403                                              eth_igb_interrupt_handler,
1404                                              (void *)dev);
1405                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1406                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1407                                      " no intr multiplex");
1408         }
1409
1410         /* check if rxq interrupt is enabled */
1411         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1412             rte_intr_dp_is_en(intr_handle))
1413                 eth_igb_rxq_interrupt_setup(dev);
1414
1415         /* enable uio/vfio intr/eventfd mapping */
1416         rte_intr_enable(intr_handle);
1417
1418         /* resume enabled intr since hw reset */
1419         igb_intr_enable(dev);
1420
1421         /* restore all types filter */
1422         igb_filter_restore(dev);
1423
1424         eth_igb_rxtx_control(dev, true);
1425         eth_igb_link_update(dev, 0);
1426
1427         PMD_INIT_LOG(DEBUG, "<<");
1428
1429         return 0;
1430
1431 error_invalid_config:
1432         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1433                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1434         igb_dev_clear_queues(dev);
1435         return -EINVAL;
1436 }
1437
1438 /*********************************************************************
1439  *
1440  *  This routine disables all traffic on the adapter by issuing a
1441  *  global reset on the MAC.
1442  *
1443  **********************************************************************/
1444 static void
1445 eth_igb_stop(struct rte_eth_dev *dev)
1446 {
1447         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1448         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1449         struct rte_eth_link link;
1450         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1451         struct e1000_adapter *adapter =
1452                 E1000_DEV_PRIVATE(dev->data->dev_private);
1453
1454         if (adapter->stopped)
1455                 return;
1456
1457         eth_igb_rxtx_control(dev, false);
1458
1459         igb_intr_disable(dev);
1460
1461         /* disable intr eventfd mapping */
1462         rte_intr_disable(intr_handle);
1463
1464         igb_pf_reset_hw(hw);
1465         E1000_WRITE_REG(hw, E1000_WUC, 0);
1466
1467         /* Set bit for Go Link disconnect if PHY reset is not blocked */
1468         if (hw->mac.type >= e1000_82580 &&
1469             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1470                 uint32_t phpm_reg;
1471
1472                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1473                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1474                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1475         }
1476
1477         /* Power down the phy. Needed to make the link go Down */
1478         eth_igb_dev_set_link_down(dev);
1479
1480         igb_dev_clear_queues(dev);
1481
1482         /* clear the recorded link status */
1483         memset(&link, 0, sizeof(link));
1484         rte_eth_linkstatus_set(dev, &link);
1485
1486         if (!rte_intr_allow_others(intr_handle))
1487                 /* resume to the default handler */
1488                 rte_intr_callback_register(intr_handle,
1489                                            eth_igb_interrupt_handler,
1490                                            (void *)dev);
1491
1492         /* Clean datapath event and queue/vec mapping */
1493         rte_intr_efd_disable(intr_handle);
1494         if (intr_handle->intr_vec != NULL) {
1495                 rte_free(intr_handle->intr_vec);
1496                 intr_handle->intr_vec = NULL;
1497         }
1498
1499         adapter->stopped = true;
1500 }
1501
1502 static int
1503 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1504 {
1505         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1506
1507         if (hw->phy.media_type == e1000_media_type_copper)
1508                 e1000_power_up_phy(hw);
1509         else
1510                 e1000_power_up_fiber_serdes_link(hw);
1511
1512         return 0;
1513 }
1514
1515 static int
1516 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1517 {
1518         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1519
1520         if (hw->phy.media_type == e1000_media_type_copper)
1521                 e1000_power_down_phy(hw);
1522         else
1523                 e1000_shutdown_fiber_serdes_link(hw);
1524
1525         return 0;
1526 }
1527
1528 static int
1529 eth_igb_close(struct rte_eth_dev *dev)
1530 {
1531         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1532         struct rte_eth_link link;
1533         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1534         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1535         struct e1000_filter_info *filter_info =
1536                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1537
1538         eth_igb_stop(dev);
1539
1540         e1000_phy_hw_reset(hw);
1541         igb_release_manageability(hw);
1542         igb_hw_control_release(hw);
1543
1544         /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1545         if (hw->mac.type >= e1000_82580 &&
1546             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1547                 uint32_t phpm_reg;
1548
1549                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1550                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1551                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1552         }
1553
1554         igb_dev_free_queues(dev);
1555
1556         if (intr_handle->intr_vec) {
1557                 rte_free(intr_handle->intr_vec);
1558                 intr_handle->intr_vec = NULL;
1559         }
1560
1561         memset(&link, 0, sizeof(link));
1562         rte_eth_linkstatus_set(dev, &link);
1563
1564         dev->dev_ops = NULL;
1565         dev->rx_pkt_burst = NULL;
1566         dev->tx_pkt_burst = NULL;
1567
1568         /* Reset any pending lock */
1569         igb_reset_swfw_lock(hw);
1570
1571         /* uninitialize PF if max_vfs not zero */
1572         igb_pf_host_uninit(dev);
1573
1574         rte_intr_callback_unregister(intr_handle,
1575                                      eth_igb_interrupt_handler, dev);
1576
1577         /* clear the SYN filter info */
1578         filter_info->syn_info = 0;
1579
1580         /* clear the ethertype filters info */
1581         filter_info->ethertype_mask = 0;
1582         memset(filter_info->ethertype_filters, 0,
1583                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1584
1585         /* clear the rss filter info */
1586         memset(&filter_info->rss_info, 0,
1587                 sizeof(struct igb_rte_flow_rss_conf));
1588
1589         /* remove all ntuple filters of the device */
1590         igb_ntuple_filter_uninit(dev);
1591
1592         /* remove all flex filters of the device */
1593         igb_flex_filter_uninit(dev);
1594
1595         /* clear all the filters list */
1596         igb_filterlist_flush(dev);
1597
1598         return 0;
1599 }
1600
1601 /*
1602  * Reset PF device.
1603  */
1604 static int
1605 eth_igb_reset(struct rte_eth_dev *dev)
1606 {
1607         int ret;
1608
1609         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1610          * its VF to make them align with it. The detailed notification
1611          * mechanism is PMD specific and is currently not implemented.
1612          * To avoid unexpected behavior in VF, currently reset of PF with
1613          * SR-IOV activation is not supported. It might be supported later.
1614          */
1615         if (dev->data->sriov.active)
1616                 return -ENOTSUP;
1617
1618         ret = eth_igb_dev_uninit(dev);
1619         if (ret)
1620                 return ret;
1621
1622         ret = eth_igb_dev_init(dev);
1623
1624         return ret;
1625 }
1626
1627
1628 static int
1629 igb_get_rx_buffer_size(struct e1000_hw *hw)
1630 {
1631         uint32_t rx_buf_size;
1632         if (hw->mac.type == e1000_82576) {
1633                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1634         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1635                 /* PBS needs to be translated according to a lookup table */
1636                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1637                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1638                 rx_buf_size = (rx_buf_size << 10);
1639         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1640                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1641         } else {
1642                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1643         }
1644
1645         return rx_buf_size;
1646 }
1647
1648 /*********************************************************************
1649  *
1650  *  Initialize the hardware
1651  *
1652  **********************************************************************/
1653 static int
1654 igb_hardware_init(struct e1000_hw *hw)
1655 {
1656         uint32_t rx_buf_size;
1657         int diag;
1658
1659         /* Let the firmware know the OS is in control */
1660         igb_hw_control_acquire(hw);
1661
1662         /*
1663          * These parameters control the automatic generation (Tx) and
1664          * response (Rx) to Ethernet PAUSE frames.
1665          * - High water mark should allow for at least two standard size (1518)
1666          *   frames to be received after sending an XOFF.
1667          * - Low water mark works best when it is very near the high water mark.
1668          *   This allows the receiver to restart by sending XON when it has
1669          *   drained a bit. Here we use an arbitrary value of 1500 which will
1670          *   restart after one full frame is pulled from the buffer. There
1671          *   could be several smaller frames in the buffer and if so they will
1672          *   not trigger the XON until their total number reduces the buffer
1673          *   by 1500.
1674          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1675          */
1676         rx_buf_size = igb_get_rx_buffer_size(hw);
1677
1678         hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1679         hw->fc.low_water = hw->fc.high_water - 1500;
1680         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1681         hw->fc.send_xon = 1;
1682
1683         /* Set Flow control, use the tunable location if sane */
1684         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1685                 hw->fc.requested_mode = igb_fc_setting;
1686         else
1687                 hw->fc.requested_mode = e1000_fc_none;
1688
1689         /* Issue a global reset */
1690         igb_pf_reset_hw(hw);
1691         E1000_WRITE_REG(hw, E1000_WUC, 0);
1692
1693         diag = e1000_init_hw(hw);
1694         if (diag < 0)
1695                 return diag;
1696
1697         E1000_WRITE_REG(hw, E1000_VET,
1698                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1699         e1000_get_phy_info(hw);
1700         e1000_check_for_link(hw);
1701
1702         return 0;
1703 }
1704
1705 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1706 static void
1707 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1708 {
1709         int pause_frames;
1710
1711         uint64_t old_gprc  = stats->gprc;
1712         uint64_t old_gptc  = stats->gptc;
1713         uint64_t old_tpr   = stats->tpr;
1714         uint64_t old_tpt   = stats->tpt;
1715         uint64_t old_rpthc = stats->rpthc;
1716         uint64_t old_hgptc = stats->hgptc;
1717
1718         if(hw->phy.media_type == e1000_media_type_copper ||
1719             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1720                 stats->symerrs +=
1721                     E1000_READ_REG(hw,E1000_SYMERRS);
1722                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1723         }
1724
1725         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1726         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1727         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1728         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1729
1730         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1731         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1732         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1733         stats->dc += E1000_READ_REG(hw, E1000_DC);
1734         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1735         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1736         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1737         /*
1738         ** For watchdog management we need to know if we have been
1739         ** paused during the last interval, so capture that here.
1740         */
1741         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1742         stats->xoffrxc += pause_frames;
1743         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1744         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1745         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1746         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1747         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1748         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1749         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1750         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1751         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1752         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1753         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1754         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1755
1756         /* For the 64-bit byte counters the low dword must be read first. */
1757         /* Both registers clear on the read of the high dword */
1758
1759         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1760         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1761         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1762         stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1763         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1764         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1765         stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1766
1767         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1768         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1769         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1770         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1771         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1772
1773         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1774         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1775
1776         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1777         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1778         stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1779         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1780         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1781         stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1782
1783         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1784         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1785         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1786         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1787         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1788         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1789         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1790         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1791
1792         /* Interrupt Counts */
1793
1794         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1795         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1796         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1797         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1798         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1799         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1800         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1801         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1802         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1803
1804         /* Host to Card Statistics */
1805
1806         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1807         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1808         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1809         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1810         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1811         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1812         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1813         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1814         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1815         stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1816         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1817         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1818         stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1819         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1820         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1821         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1822
1823         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1824         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1825         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1826         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1827         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1828         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1829 }
1830
1831 static int
1832 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1833 {
1834         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1835         struct e1000_hw_stats *stats =
1836                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1837
1838         igb_read_stats_registers(hw, stats);
1839
1840         if (rte_stats == NULL)
1841                 return -EINVAL;
1842
1843         /* Rx Errors */
1844         rte_stats->imissed = stats->mpc;
1845         rte_stats->ierrors = stats->crcerrs +
1846                              stats->rlec + stats->ruc + stats->roc +
1847                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1848
1849         /* Tx Errors */
1850         rte_stats->oerrors = stats->ecol + stats->latecol;
1851
1852         rte_stats->ipackets = stats->gprc;
1853         rte_stats->opackets = stats->gptc;
1854         rte_stats->ibytes   = stats->gorc;
1855         rte_stats->obytes   = stats->gotc;
1856         return 0;
1857 }
1858
1859 static int
1860 eth_igb_stats_reset(struct rte_eth_dev *dev)
1861 {
1862         struct e1000_hw_stats *hw_stats =
1863                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1864
1865         /* HW registers are cleared on read */
1866         eth_igb_stats_get(dev, NULL);
1867
1868         /* Reset software totals */
1869         memset(hw_stats, 0, sizeof(*hw_stats));
1870
1871         return 0;
1872 }
1873
1874 static int
1875 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1876 {
1877         struct e1000_hw_stats *stats =
1878                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1879
1880         /* HW registers are cleared on read */
1881         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1882
1883         /* Reset software totals */
1884         memset(stats, 0, sizeof(*stats));
1885
1886         return 0;
1887 }
1888
1889 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1890         struct rte_eth_xstat_name *xstats_names,
1891         __rte_unused unsigned int size)
1892 {
1893         unsigned i;
1894
1895         if (xstats_names == NULL)
1896                 return IGB_NB_XSTATS;
1897
1898         /* Note: limit checked in rte_eth_xstats_names() */
1899
1900         for (i = 0; i < IGB_NB_XSTATS; i++) {
1901                 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1902                         sizeof(xstats_names[i].name));
1903         }
1904
1905         return IGB_NB_XSTATS;
1906 }
1907
1908 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1909                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1910                 unsigned int limit)
1911 {
1912         unsigned int i;
1913
1914         if (!ids) {
1915                 if (xstats_names == NULL)
1916                         return IGB_NB_XSTATS;
1917
1918                 for (i = 0; i < IGB_NB_XSTATS; i++)
1919                         strlcpy(xstats_names[i].name,
1920                                 rte_igb_stats_strings[i].name,
1921                                 sizeof(xstats_names[i].name));
1922
1923                 return IGB_NB_XSTATS;
1924
1925         } else {
1926                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1927
1928                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1929                                 IGB_NB_XSTATS);
1930
1931                 for (i = 0; i < limit; i++) {
1932                         if (ids[i] >= IGB_NB_XSTATS) {
1933                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1934                                 return -1;
1935                         }
1936                         strcpy(xstats_names[i].name,
1937                                         xstats_names_copy[ids[i]].name);
1938                 }
1939                 return limit;
1940         }
1941 }
1942
1943 static int
1944 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1945                    unsigned n)
1946 {
1947         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1948         struct e1000_hw_stats *hw_stats =
1949                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1950         unsigned i;
1951
1952         if (n < IGB_NB_XSTATS)
1953                 return IGB_NB_XSTATS;
1954
1955         igb_read_stats_registers(hw, hw_stats);
1956
1957         /* If this is a reset xstats is NULL, and we have cleared the
1958          * registers by reading them.
1959          */
1960         if (!xstats)
1961                 return 0;
1962
1963         /* Extended stats */
1964         for (i = 0; i < IGB_NB_XSTATS; i++) {
1965                 xstats[i].id = i;
1966                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1967                         rte_igb_stats_strings[i].offset);
1968         }
1969
1970         return IGB_NB_XSTATS;
1971 }
1972
1973 static int
1974 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1975                 uint64_t *values, unsigned int n)
1976 {
1977         unsigned int i;
1978
1979         if (!ids) {
1980                 struct e1000_hw *hw =
1981                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1982                 struct e1000_hw_stats *hw_stats =
1983                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1984
1985                 if (n < IGB_NB_XSTATS)
1986                         return IGB_NB_XSTATS;
1987
1988                 igb_read_stats_registers(hw, hw_stats);
1989
1990                 /* If this is a reset xstats is NULL, and we have cleared the
1991                  * registers by reading them.
1992                  */
1993                 if (!values)
1994                         return 0;
1995
1996                 /* Extended stats */
1997                 for (i = 0; i < IGB_NB_XSTATS; i++)
1998                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1999                                         rte_igb_stats_strings[i].offset);
2000
2001                 return IGB_NB_XSTATS;
2002
2003         } else {
2004                 uint64_t values_copy[IGB_NB_XSTATS];
2005
2006                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2007                                 IGB_NB_XSTATS);
2008
2009                 for (i = 0; i < n; i++) {
2010                         if (ids[i] >= IGB_NB_XSTATS) {
2011                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2012                                 return -1;
2013                         }
2014                         values[i] = values_copy[ids[i]];
2015                 }
2016                 return n;
2017         }
2018 }
2019
2020 static void
2021 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2022 {
2023         /* Good Rx packets, include VF loopback */
2024         UPDATE_VF_STAT(E1000_VFGPRC,
2025             hw_stats->last_gprc, hw_stats->gprc);
2026
2027         /* Good Rx octets, include VF loopback */
2028         UPDATE_VF_STAT(E1000_VFGORC,
2029             hw_stats->last_gorc, hw_stats->gorc);
2030
2031         /* Good Tx packets, include VF loopback */
2032         UPDATE_VF_STAT(E1000_VFGPTC,
2033             hw_stats->last_gptc, hw_stats->gptc);
2034
2035         /* Good Tx octets, include VF loopback */
2036         UPDATE_VF_STAT(E1000_VFGOTC,
2037             hw_stats->last_gotc, hw_stats->gotc);
2038
2039         /* Rx Multicst packets */
2040         UPDATE_VF_STAT(E1000_VFMPRC,
2041             hw_stats->last_mprc, hw_stats->mprc);
2042
2043         /* Good Rx loopback packets */
2044         UPDATE_VF_STAT(E1000_VFGPRLBC,
2045             hw_stats->last_gprlbc, hw_stats->gprlbc);
2046
2047         /* Good Rx loopback octets */
2048         UPDATE_VF_STAT(E1000_VFGORLBC,
2049             hw_stats->last_gorlbc, hw_stats->gorlbc);
2050
2051         /* Good Tx loopback packets */
2052         UPDATE_VF_STAT(E1000_VFGPTLBC,
2053             hw_stats->last_gptlbc, hw_stats->gptlbc);
2054
2055         /* Good Tx loopback octets */
2056         UPDATE_VF_STAT(E1000_VFGOTLBC,
2057             hw_stats->last_gotlbc, hw_stats->gotlbc);
2058 }
2059
2060 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2061                                      struct rte_eth_xstat_name *xstats_names,
2062                                      __rte_unused unsigned limit)
2063 {
2064         unsigned i;
2065
2066         if (xstats_names != NULL)
2067                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2068                         strlcpy(xstats_names[i].name,
2069                                 rte_igbvf_stats_strings[i].name,
2070                                 sizeof(xstats_names[i].name));
2071                 }
2072         return IGBVF_NB_XSTATS;
2073 }
2074
2075 static int
2076 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2077                      unsigned n)
2078 {
2079         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2081                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2082         unsigned i;
2083
2084         if (n < IGBVF_NB_XSTATS)
2085                 return IGBVF_NB_XSTATS;
2086
2087         igbvf_read_stats_registers(hw, hw_stats);
2088
2089         if (!xstats)
2090                 return 0;
2091
2092         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2093                 xstats[i].id = i;
2094                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2095                         rte_igbvf_stats_strings[i].offset);
2096         }
2097
2098         return IGBVF_NB_XSTATS;
2099 }
2100
2101 static int
2102 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2103 {
2104         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2106                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2107
2108         igbvf_read_stats_registers(hw, hw_stats);
2109
2110         if (rte_stats == NULL)
2111                 return -EINVAL;
2112
2113         rte_stats->ipackets = hw_stats->gprc;
2114         rte_stats->ibytes = hw_stats->gorc;
2115         rte_stats->opackets = hw_stats->gptc;
2116         rte_stats->obytes = hw_stats->gotc;
2117         return 0;
2118 }
2119
2120 static int
2121 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2122 {
2123         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2124                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2125
2126         /* Sync HW register to the last stats */
2127         eth_igbvf_stats_get(dev, NULL);
2128
2129         /* reset HW current stats*/
2130         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2131                offsetof(struct e1000_vf_stats, gprc));
2132
2133         return 0;
2134 }
2135
2136 static int
2137 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2138                        size_t fw_size)
2139 {
2140         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2141         struct e1000_fw_version fw;
2142         int ret;
2143
2144         e1000_get_fw_version(hw, &fw);
2145
2146         switch (hw->mac.type) {
2147         case e1000_i210:
2148         case e1000_i211:
2149                 if (!(e1000_get_flash_presence_i210(hw))) {
2150                         ret = snprintf(fw_version, fw_size,
2151                                  "%2d.%2d-%d",
2152                                  fw.invm_major, fw.invm_minor,
2153                                  fw.invm_img_type);
2154                         break;
2155                 }
2156                 /* fall through */
2157         default:
2158                 /* if option rom is valid, display its version too */
2159                 if (fw.or_valid) {
2160                         ret = snprintf(fw_version, fw_size,
2161                                  "%d.%d, 0x%08x, %d.%d.%d",
2162                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2163                                  fw.or_major, fw.or_build, fw.or_patch);
2164                 /* no option rom */
2165                 } else {
2166                         if (fw.etrack_id != 0X0000) {
2167                                 ret = snprintf(fw_version, fw_size,
2168                                          "%d.%d, 0x%08x",
2169                                          fw.eep_major, fw.eep_minor,
2170                                          fw.etrack_id);
2171                         } else {
2172                                 ret = snprintf(fw_version, fw_size,
2173                                          "%d.%d.%d",
2174                                          fw.eep_major, fw.eep_minor,
2175                                          fw.eep_build);
2176                         }
2177                 }
2178                 break;
2179         }
2180
2181         ret += 1; /* add the size of '\0' */
2182         if (fw_size < (u32)ret)
2183                 return ret;
2184         else
2185                 return 0;
2186 }
2187
2188 static int
2189 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2190 {
2191         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192
2193         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2194         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2195         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2196         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2197         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2198                                     dev_info->rx_queue_offload_capa;
2199         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2200         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2201                                     dev_info->tx_queue_offload_capa;
2202
2203         switch (hw->mac.type) {
2204         case e1000_82575:
2205                 dev_info->max_rx_queues = 4;
2206                 dev_info->max_tx_queues = 4;
2207                 dev_info->max_vmdq_pools = 0;
2208                 break;
2209
2210         case e1000_82576:
2211                 dev_info->max_rx_queues = 16;
2212                 dev_info->max_tx_queues = 16;
2213                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2214                 dev_info->vmdq_queue_num = 16;
2215                 break;
2216
2217         case e1000_82580:
2218                 dev_info->max_rx_queues = 8;
2219                 dev_info->max_tx_queues = 8;
2220                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2221                 dev_info->vmdq_queue_num = 8;
2222                 break;
2223
2224         case e1000_i350:
2225                 dev_info->max_rx_queues = 8;
2226                 dev_info->max_tx_queues = 8;
2227                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2228                 dev_info->vmdq_queue_num = 8;
2229                 break;
2230
2231         case e1000_i354:
2232                 dev_info->max_rx_queues = 8;
2233                 dev_info->max_tx_queues = 8;
2234                 break;
2235
2236         case e1000_i210:
2237                 dev_info->max_rx_queues = 4;
2238                 dev_info->max_tx_queues = 4;
2239                 dev_info->max_vmdq_pools = 0;
2240                 break;
2241
2242         case e1000_i211:
2243                 dev_info->max_rx_queues = 2;
2244                 dev_info->max_tx_queues = 2;
2245                 dev_info->max_vmdq_pools = 0;
2246                 break;
2247
2248         default:
2249                 /* Should not happen */
2250                 return -EINVAL;
2251         }
2252         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2253         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2254         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2255
2256         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2257                 .rx_thresh = {
2258                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2259                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2260                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2261                 },
2262                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2263                 .rx_drop_en = 0,
2264                 .offloads = 0,
2265         };
2266
2267         dev_info->default_txconf = (struct rte_eth_txconf) {
2268                 .tx_thresh = {
2269                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2270                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2271                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2272                 },
2273                 .offloads = 0,
2274         };
2275
2276         dev_info->rx_desc_lim = rx_desc_lim;
2277         dev_info->tx_desc_lim = tx_desc_lim;
2278
2279         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2280                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2281                         ETH_LINK_SPEED_1G;
2282
2283         dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2284         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2285
2286         return 0;
2287 }
2288
2289 static const uint32_t *
2290 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2291 {
2292         static const uint32_t ptypes[] = {
2293                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2294                 RTE_PTYPE_L2_ETHER,
2295                 RTE_PTYPE_L3_IPV4,
2296                 RTE_PTYPE_L3_IPV4_EXT,
2297                 RTE_PTYPE_L3_IPV6,
2298                 RTE_PTYPE_L3_IPV6_EXT,
2299                 RTE_PTYPE_L4_TCP,
2300                 RTE_PTYPE_L4_UDP,
2301                 RTE_PTYPE_L4_SCTP,
2302                 RTE_PTYPE_TUNNEL_IP,
2303                 RTE_PTYPE_INNER_L3_IPV6,
2304                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2305                 RTE_PTYPE_INNER_L4_TCP,
2306                 RTE_PTYPE_INNER_L4_UDP,
2307                 RTE_PTYPE_UNKNOWN
2308         };
2309
2310         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2311             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2312                 return ptypes;
2313         return NULL;
2314 }
2315
2316 static int
2317 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2318 {
2319         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2320
2321         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2322         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2323         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2324         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2325                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2326                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2327                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2328                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2329                                 DEV_TX_OFFLOAD_TCP_TSO;
2330         switch (hw->mac.type) {
2331         case e1000_vfadapt:
2332                 dev_info->max_rx_queues = 2;
2333                 dev_info->max_tx_queues = 2;
2334                 break;
2335         case e1000_vfadapt_i350:
2336                 dev_info->max_rx_queues = 1;
2337                 dev_info->max_tx_queues = 1;
2338                 break;
2339         default:
2340                 /* Should not happen */
2341                 return -EINVAL;
2342         }
2343
2344         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2345         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2346                                     dev_info->rx_queue_offload_capa;
2347         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2348         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2349                                     dev_info->tx_queue_offload_capa;
2350
2351         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2352                 .rx_thresh = {
2353                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2354                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2355                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2356                 },
2357                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2358                 .rx_drop_en = 0,
2359                 .offloads = 0,
2360         };
2361
2362         dev_info->default_txconf = (struct rte_eth_txconf) {
2363                 .tx_thresh = {
2364                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2365                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2366                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2367                 },
2368                 .offloads = 0,
2369         };
2370
2371         dev_info->rx_desc_lim = rx_desc_lim;
2372         dev_info->tx_desc_lim = tx_desc_lim;
2373
2374         return 0;
2375 }
2376
2377 /* return 0 means link status changed, -1 means not changed */
2378 static int
2379 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2380 {
2381         struct e1000_hw *hw =
2382                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2383         struct rte_eth_link link;
2384         int link_check, count;
2385
2386         link_check = 0;
2387         hw->mac.get_link_status = 1;
2388
2389         /* possible wait-to-complete in up to 9 seconds */
2390         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2391                 /* Read the real link status */
2392                 switch (hw->phy.media_type) {
2393                 case e1000_media_type_copper:
2394                         /* Do the work to read phy */
2395                         e1000_check_for_link(hw);
2396                         link_check = !hw->mac.get_link_status;
2397                         break;
2398
2399                 case e1000_media_type_fiber:
2400                         e1000_check_for_link(hw);
2401                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2402                                       E1000_STATUS_LU);
2403                         break;
2404
2405                 case e1000_media_type_internal_serdes:
2406                         e1000_check_for_link(hw);
2407                         link_check = hw->mac.serdes_has_link;
2408                         break;
2409
2410                 /* VF device is type_unknown */
2411                 case e1000_media_type_unknown:
2412                         eth_igbvf_link_update(hw);
2413                         link_check = !hw->mac.get_link_status;
2414                         break;
2415
2416                 default:
2417                         break;
2418                 }
2419                 if (link_check || wait_to_complete == 0)
2420                         break;
2421                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2422         }
2423         memset(&link, 0, sizeof(link));
2424
2425         /* Now we check if a transition has happened */
2426         if (link_check) {
2427                 uint16_t duplex, speed;
2428                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2429                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2430                                 ETH_LINK_FULL_DUPLEX :
2431                                 ETH_LINK_HALF_DUPLEX;
2432                 link.link_speed = speed;
2433                 link.link_status = ETH_LINK_UP;
2434                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2435                                 ETH_LINK_SPEED_FIXED);
2436         } else if (!link_check) {
2437                 link.link_speed = 0;
2438                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2439                 link.link_status = ETH_LINK_DOWN;
2440                 link.link_autoneg = ETH_LINK_FIXED;
2441         }
2442
2443         return rte_eth_linkstatus_set(dev, &link);
2444 }
2445
2446 /*
2447  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2448  * For ASF and Pass Through versions of f/w this means
2449  * that the driver is loaded.
2450  */
2451 static void
2452 igb_hw_control_acquire(struct e1000_hw *hw)
2453 {
2454         uint32_t ctrl_ext;
2455
2456         /* Let firmware know the driver has taken over */
2457         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2458         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2459 }
2460
2461 /*
2462  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2463  * For ASF and Pass Through versions of f/w this means that the
2464  * driver is no longer loaded.
2465  */
2466 static void
2467 igb_hw_control_release(struct e1000_hw *hw)
2468 {
2469         uint32_t ctrl_ext;
2470
2471         /* Let firmware taken over control of h/w */
2472         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2473         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2474                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2475 }
2476
2477 /*
2478  * Bit of a misnomer, what this really means is
2479  * to enable OS management of the system... aka
2480  * to disable special hardware management features.
2481  */
2482 static void
2483 igb_init_manageability(struct e1000_hw *hw)
2484 {
2485         if (e1000_enable_mng_pass_thru(hw)) {
2486                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2487                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2488
2489                 /* disable hardware interception of ARP */
2490                 manc &= ~(E1000_MANC_ARP_EN);
2491
2492                 /* enable receiving management packets to the host */
2493                 manc |= E1000_MANC_EN_MNG2HOST;
2494                 manc2h |= 1 << 5;  /* Mng Port 623 */
2495                 manc2h |= 1 << 6;  /* Mng Port 664 */
2496                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2497                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2498         }
2499 }
2500
2501 static void
2502 igb_release_manageability(struct e1000_hw *hw)
2503 {
2504         if (e1000_enable_mng_pass_thru(hw)) {
2505                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2506
2507                 manc |= E1000_MANC_ARP_EN;
2508                 manc &= ~E1000_MANC_EN_MNG2HOST;
2509
2510                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2511         }
2512 }
2513
2514 static int
2515 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2516 {
2517         struct e1000_hw *hw =
2518                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2519         uint32_t rctl;
2520
2521         rctl = E1000_READ_REG(hw, E1000_RCTL);
2522         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2523         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2524
2525         return 0;
2526 }
2527
2528 static int
2529 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2530 {
2531         struct e1000_hw *hw =
2532                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2533         uint32_t rctl;
2534
2535         rctl = E1000_READ_REG(hw, E1000_RCTL);
2536         rctl &= (~E1000_RCTL_UPE);
2537         if (dev->data->all_multicast == 1)
2538                 rctl |= E1000_RCTL_MPE;
2539         else
2540                 rctl &= (~E1000_RCTL_MPE);
2541         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2542
2543         return 0;
2544 }
2545
2546 static int
2547 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2548 {
2549         struct e1000_hw *hw =
2550                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2551         uint32_t rctl;
2552
2553         rctl = E1000_READ_REG(hw, E1000_RCTL);
2554         rctl |= E1000_RCTL_MPE;
2555         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2556
2557         return 0;
2558 }
2559
2560 static int
2561 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2562 {
2563         struct e1000_hw *hw =
2564                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2565         uint32_t rctl;
2566
2567         if (dev->data->promiscuous == 1)
2568                 return 0; /* must remain in all_multicast mode */
2569         rctl = E1000_READ_REG(hw, E1000_RCTL);
2570         rctl &= (~E1000_RCTL_MPE);
2571         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2572
2573         return 0;
2574 }
2575
2576 static int
2577 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2578 {
2579         struct e1000_hw *hw =
2580                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2581         struct e1000_vfta * shadow_vfta =
2582                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2583         uint32_t vfta;
2584         uint32_t vid_idx;
2585         uint32_t vid_bit;
2586
2587         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2588                               E1000_VFTA_ENTRY_MASK);
2589         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2590         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2591         if (on)
2592                 vfta |= vid_bit;
2593         else
2594                 vfta &= ~vid_bit;
2595         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2596
2597         /* update local VFTA copy */
2598         shadow_vfta->vfta[vid_idx] = vfta;
2599
2600         return 0;
2601 }
2602
2603 static int
2604 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2605                       enum rte_vlan_type vlan_type,
2606                       uint16_t tpid)
2607 {
2608         struct e1000_hw *hw =
2609                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2610         uint32_t reg, qinq;
2611
2612         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2613         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2614
2615         /* only outer TPID of double VLAN can be configured*/
2616         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2617                 reg = E1000_READ_REG(hw, E1000_VET);
2618                 reg = (reg & (~E1000_VET_VET_EXT)) |
2619                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2620                 E1000_WRITE_REG(hw, E1000_VET, reg);
2621
2622                 return 0;
2623         }
2624
2625         /* all other TPID values are read-only*/
2626         PMD_DRV_LOG(ERR, "Not supported");
2627
2628         return -ENOTSUP;
2629 }
2630
2631 static void
2632 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2633 {
2634         struct e1000_hw *hw =
2635                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2636         uint32_t reg;
2637
2638         /* Filter Table Disable */
2639         reg = E1000_READ_REG(hw, E1000_RCTL);
2640         reg &= ~E1000_RCTL_CFIEN;
2641         reg &= ~E1000_RCTL_VFE;
2642         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2643 }
2644
2645 static void
2646 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2647 {
2648         struct e1000_hw *hw =
2649                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2650         struct e1000_vfta * shadow_vfta =
2651                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2652         uint32_t reg;
2653         int i;
2654
2655         /* Filter Table Enable, CFI not used for packet acceptance */
2656         reg = E1000_READ_REG(hw, E1000_RCTL);
2657         reg &= ~E1000_RCTL_CFIEN;
2658         reg |= E1000_RCTL_VFE;
2659         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2660
2661         /* restore VFTA table */
2662         for (i = 0; i < IGB_VFTA_SIZE; i++)
2663                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2664 }
2665
2666 static void
2667 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2668 {
2669         struct e1000_hw *hw =
2670                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2671         uint32_t reg;
2672
2673         /* VLAN Mode Disable */
2674         reg = E1000_READ_REG(hw, E1000_CTRL);
2675         reg &= ~E1000_CTRL_VME;
2676         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2677 }
2678
2679 static void
2680 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2681 {
2682         struct e1000_hw *hw =
2683                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2684         uint32_t reg;
2685
2686         /* VLAN Mode Enable */
2687         reg = E1000_READ_REG(hw, E1000_CTRL);
2688         reg |= E1000_CTRL_VME;
2689         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2690 }
2691
2692 static void
2693 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2694 {
2695         struct e1000_hw *hw =
2696                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2697         uint32_t reg;
2698
2699         /* CTRL_EXT: Extended VLAN */
2700         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2701         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2702         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2703
2704         /* Update maximum packet length */
2705         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2706                 E1000_WRITE_REG(hw, E1000_RLPML,
2707                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2708                                                 VLAN_TAG_SIZE);
2709 }
2710
2711 static void
2712 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2713 {
2714         struct e1000_hw *hw =
2715                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2716         uint32_t reg;
2717
2718         /* CTRL_EXT: Extended VLAN */
2719         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2720         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2721         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2722
2723         /* Update maximum packet length */
2724         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2725                 E1000_WRITE_REG(hw, E1000_RLPML,
2726                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2727                                                 2 * VLAN_TAG_SIZE);
2728 }
2729
2730 static int
2731 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2732 {
2733         struct rte_eth_rxmode *rxmode;
2734
2735         rxmode = &dev->data->dev_conf.rxmode;
2736         if(mask & ETH_VLAN_STRIP_MASK){
2737                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2738                         igb_vlan_hw_strip_enable(dev);
2739                 else
2740                         igb_vlan_hw_strip_disable(dev);
2741         }
2742
2743         if(mask & ETH_VLAN_FILTER_MASK){
2744                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2745                         igb_vlan_hw_filter_enable(dev);
2746                 else
2747                         igb_vlan_hw_filter_disable(dev);
2748         }
2749
2750         if(mask & ETH_VLAN_EXTEND_MASK){
2751                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2752                         igb_vlan_hw_extend_enable(dev);
2753                 else
2754                         igb_vlan_hw_extend_disable(dev);
2755         }
2756
2757         return 0;
2758 }
2759
2760
2761 /**
2762  * It enables the interrupt mask and then enable the interrupt.
2763  *
2764  * @param dev
2765  *  Pointer to struct rte_eth_dev.
2766  * @param on
2767  *  Enable or Disable
2768  *
2769  * @return
2770  *  - On success, zero.
2771  *  - On failure, a negative value.
2772  */
2773 static int
2774 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2775 {
2776         struct e1000_interrupt *intr =
2777                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2778
2779         if (on)
2780                 intr->mask |= E1000_ICR_LSC;
2781         else
2782                 intr->mask &= ~E1000_ICR_LSC;
2783
2784         return 0;
2785 }
2786
2787 /* It clears the interrupt causes and enables the interrupt.
2788  * It will be called once only during nic initialized.
2789  *
2790  * @param dev
2791  *  Pointer to struct rte_eth_dev.
2792  *
2793  * @return
2794  *  - On success, zero.
2795  *  - On failure, a negative value.
2796  */
2797 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2798 {
2799         uint32_t mask, regval;
2800         int ret;
2801         struct e1000_hw *hw =
2802                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2803         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2804         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2805         int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2806         struct rte_eth_dev_info dev_info;
2807
2808         memset(&dev_info, 0, sizeof(dev_info));
2809         ret = eth_igb_infos_get(dev, &dev_info);
2810         if (ret != 0)
2811                 return ret;
2812
2813         mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2814         regval = E1000_READ_REG(hw, E1000_EIMS);
2815         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2816
2817         return 0;
2818 }
2819
2820 /*
2821  * It reads ICR and gets interrupt causes, check it and set a bit flag
2822  * to update link status.
2823  *
2824  * @param dev
2825  *  Pointer to struct rte_eth_dev.
2826  *
2827  * @return
2828  *  - On success, zero.
2829  *  - On failure, a negative value.
2830  */
2831 static int
2832 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2833 {
2834         uint32_t icr;
2835         struct e1000_hw *hw =
2836                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2837         struct e1000_interrupt *intr =
2838                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2839
2840         igb_intr_disable(dev);
2841
2842         /* read-on-clear nic registers here */
2843         icr = E1000_READ_REG(hw, E1000_ICR);
2844
2845         intr->flags = 0;
2846         if (icr & E1000_ICR_LSC) {
2847                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2848         }
2849
2850         if (icr & E1000_ICR_VMMB)
2851                 intr->flags |= E1000_FLAG_MAILBOX;
2852
2853         return 0;
2854 }
2855
2856 /*
2857  * It executes link_update after knowing an interrupt is prsent.
2858  *
2859  * @param dev
2860  *  Pointer to struct rte_eth_dev.
2861  *
2862  * @return
2863  *  - On success, zero.
2864  *  - On failure, a negative value.
2865  */
2866 static int
2867 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2868                          struct rte_intr_handle *intr_handle)
2869 {
2870         struct e1000_hw *hw =
2871                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2872         struct e1000_interrupt *intr =
2873                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2874         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2875         struct rte_eth_link link;
2876         int ret;
2877
2878         if (intr->flags & E1000_FLAG_MAILBOX) {
2879                 igb_pf_mbx_process(dev);
2880                 intr->flags &= ~E1000_FLAG_MAILBOX;
2881         }
2882
2883         igb_intr_enable(dev);
2884         rte_intr_ack(intr_handle);
2885
2886         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2887                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2888
2889                 /* set get_link_status to check register later */
2890                 hw->mac.get_link_status = 1;
2891                 ret = eth_igb_link_update(dev, 0);
2892
2893                 /* check if link has changed */
2894                 if (ret < 0)
2895                         return 0;
2896
2897                 rte_eth_linkstatus_get(dev, &link);
2898                 if (link.link_status) {
2899                         PMD_INIT_LOG(INFO,
2900                                      " Port %d: Link Up - speed %u Mbps - %s",
2901                                      dev->data->port_id,
2902                                      (unsigned)link.link_speed,
2903                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2904                                      "full-duplex" : "half-duplex");
2905                 } else {
2906                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2907                                      dev->data->port_id);
2908                 }
2909
2910                 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2911                              pci_dev->addr.domain,
2912                              pci_dev->addr.bus,
2913                              pci_dev->addr.devid,
2914                              pci_dev->addr.function);
2915                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2916         }
2917
2918         return 0;
2919 }
2920
2921 /**
2922  * Interrupt handler which shall be registered at first.
2923  *
2924  * @param handle
2925  *  Pointer to interrupt handle.
2926  * @param param
2927  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2928  *
2929  * @return
2930  *  void
2931  */
2932 static void
2933 eth_igb_interrupt_handler(void *param)
2934 {
2935         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2936
2937         eth_igb_interrupt_get_status(dev);
2938         eth_igb_interrupt_action(dev, dev->intr_handle);
2939 }
2940
2941 static int
2942 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2943 {
2944         uint32_t eicr;
2945         struct e1000_hw *hw =
2946                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2947         struct e1000_interrupt *intr =
2948                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2949
2950         igbvf_intr_disable(hw);
2951
2952         /* read-on-clear nic registers here */
2953         eicr = E1000_READ_REG(hw, E1000_EICR);
2954         intr->flags = 0;
2955
2956         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2957                 intr->flags |= E1000_FLAG_MAILBOX;
2958
2959         return 0;
2960 }
2961
2962 void igbvf_mbx_process(struct rte_eth_dev *dev)
2963 {
2964         struct e1000_hw *hw =
2965                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2966         struct e1000_mbx_info *mbx = &hw->mbx;
2967         u32 in_msg = 0;
2968
2969         /* peek the message first */
2970         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2971
2972         /* PF reset VF event */
2973         if (in_msg == E1000_PF_CONTROL_MSG) {
2974                 /* dummy mbx read to ack pf */
2975                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2976                         return;
2977                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2978                                              NULL);
2979         }
2980 }
2981
2982 static int
2983 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2984 {
2985         struct e1000_interrupt *intr =
2986                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2987
2988         if (intr->flags & E1000_FLAG_MAILBOX) {
2989                 igbvf_mbx_process(dev);
2990                 intr->flags &= ~E1000_FLAG_MAILBOX;
2991         }
2992
2993         igbvf_intr_enable(dev);
2994         rte_intr_ack(intr_handle);
2995
2996         return 0;
2997 }
2998
2999 static void
3000 eth_igbvf_interrupt_handler(void *param)
3001 {
3002         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3003
3004         eth_igbvf_interrupt_get_status(dev);
3005         eth_igbvf_interrupt_action(dev, dev->intr_handle);
3006 }
3007
3008 static int
3009 eth_igb_led_on(struct rte_eth_dev *dev)
3010 {
3011         struct e1000_hw *hw;
3012
3013         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3014         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3015 }
3016
3017 static int
3018 eth_igb_led_off(struct rte_eth_dev *dev)
3019 {
3020         struct e1000_hw *hw;
3021
3022         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3023         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3024 }
3025
3026 static int
3027 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3028 {
3029         struct e1000_hw *hw;
3030         uint32_t ctrl;
3031         int tx_pause;
3032         int rx_pause;
3033
3034         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3035         fc_conf->pause_time = hw->fc.pause_time;
3036         fc_conf->high_water = hw->fc.high_water;
3037         fc_conf->low_water = hw->fc.low_water;
3038         fc_conf->send_xon = hw->fc.send_xon;
3039         fc_conf->autoneg = hw->mac.autoneg;
3040
3041         /*
3042          * Return rx_pause and tx_pause status according to actual setting of
3043          * the TFCE and RFCE bits in the CTRL register.
3044          */
3045         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3046         if (ctrl & E1000_CTRL_TFCE)
3047                 tx_pause = 1;
3048         else
3049                 tx_pause = 0;
3050
3051         if (ctrl & E1000_CTRL_RFCE)
3052                 rx_pause = 1;
3053         else
3054                 rx_pause = 0;
3055
3056         if (rx_pause && tx_pause)
3057                 fc_conf->mode = RTE_FC_FULL;
3058         else if (rx_pause)
3059                 fc_conf->mode = RTE_FC_RX_PAUSE;
3060         else if (tx_pause)
3061                 fc_conf->mode = RTE_FC_TX_PAUSE;
3062         else
3063                 fc_conf->mode = RTE_FC_NONE;
3064
3065         return 0;
3066 }
3067
3068 static int
3069 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3070 {
3071         struct e1000_hw *hw;
3072         int err;
3073         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3074                 e1000_fc_none,
3075                 e1000_fc_rx_pause,
3076                 e1000_fc_tx_pause,
3077                 e1000_fc_full
3078         };
3079         uint32_t rx_buf_size;
3080         uint32_t max_high_water;
3081         uint32_t rctl;
3082
3083         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3084         if (fc_conf->autoneg != hw->mac.autoneg)
3085                 return -ENOTSUP;
3086         rx_buf_size = igb_get_rx_buffer_size(hw);
3087         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3088
3089         /* At least reserve one Ethernet frame for watermark */
3090         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3091         if ((fc_conf->high_water > max_high_water) ||
3092             (fc_conf->high_water < fc_conf->low_water)) {
3093                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3094                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3095                 return -EINVAL;
3096         }
3097
3098         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3099         hw->fc.pause_time     = fc_conf->pause_time;
3100         hw->fc.high_water     = fc_conf->high_water;
3101         hw->fc.low_water      = fc_conf->low_water;
3102         hw->fc.send_xon       = fc_conf->send_xon;
3103
3104         err = e1000_setup_link_generic(hw);
3105         if (err == E1000_SUCCESS) {
3106
3107                 /* check if we want to forward MAC frames - driver doesn't have native
3108                  * capability to do that, so we'll write the registers ourselves */
3109
3110                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3111
3112                 /* set or clear MFLCN.PMCF bit depending on configuration */
3113                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3114                         rctl |= E1000_RCTL_PMCF;
3115                 else
3116                         rctl &= ~E1000_RCTL_PMCF;
3117
3118                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3119                 E1000_WRITE_FLUSH(hw);
3120
3121                 return 0;
3122         }
3123
3124         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3125         return -EIO;
3126 }
3127
3128 #define E1000_RAH_POOLSEL_SHIFT      (18)
3129 static int
3130 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3131                 uint32_t index, uint32_t pool)
3132 {
3133         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3134         uint32_t rah;
3135
3136         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3137         rah = E1000_READ_REG(hw, E1000_RAH(index));
3138         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3139         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3140         return 0;
3141 }
3142
3143 static void
3144 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3145 {
3146         uint8_t addr[RTE_ETHER_ADDR_LEN];
3147         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3148
3149         memset(addr, 0, sizeof(addr));
3150
3151         e1000_rar_set(hw, addr, index);
3152 }
3153
3154 static int
3155 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3156                                 struct rte_ether_addr *addr)
3157 {
3158         eth_igb_rar_clear(dev, 0);
3159         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3160
3161         return 0;
3162 }
3163 /*
3164  * Virtual Function operations
3165  */
3166 static void
3167 igbvf_intr_disable(struct e1000_hw *hw)
3168 {
3169         PMD_INIT_FUNC_TRACE();
3170
3171         /* Clear interrupt mask to stop from interrupts being generated */
3172         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3173
3174         E1000_WRITE_FLUSH(hw);
3175 }
3176
3177 static void
3178 igbvf_stop_adapter(struct rte_eth_dev *dev)
3179 {
3180         u32 reg_val;
3181         u16 i;
3182         struct rte_eth_dev_info dev_info;
3183         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3184         int ret;
3185
3186         memset(&dev_info, 0, sizeof(dev_info));
3187         ret = eth_igbvf_infos_get(dev, &dev_info);
3188         if (ret != 0)
3189                 return;
3190
3191         /* Clear interrupt mask to stop from interrupts being generated */
3192         igbvf_intr_disable(hw);
3193
3194         /* Clear any pending interrupts, flush previous writes */
3195         E1000_READ_REG(hw, E1000_EICR);
3196
3197         /* Disable the transmit unit.  Each queue must be disabled. */
3198         for (i = 0; i < dev_info.max_tx_queues; i++)
3199                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3200
3201         /* Disable the receive unit by stopping each queue */
3202         for (i = 0; i < dev_info.max_rx_queues; i++) {
3203                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3204                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3205                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3206                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3207                         ;
3208         }
3209
3210         /* flush all queues disables */
3211         E1000_WRITE_FLUSH(hw);
3212         msec_delay(2);
3213 }
3214
3215 static int eth_igbvf_link_update(struct e1000_hw *hw)
3216 {
3217         struct e1000_mbx_info *mbx = &hw->mbx;
3218         struct e1000_mac_info *mac = &hw->mac;
3219         int ret_val = E1000_SUCCESS;
3220
3221         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3222
3223         /*
3224          * We only want to run this if there has been a rst asserted.
3225          * in this case that could mean a link change, device reset,
3226          * or a virtual function reset
3227          */
3228
3229         /* If we were hit with a reset or timeout drop the link */
3230         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3231                 mac->get_link_status = TRUE;
3232
3233         if (!mac->get_link_status)
3234                 goto out;
3235
3236         /* if link status is down no point in checking to see if pf is up */
3237         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3238                 goto out;
3239
3240         /* if we passed all the tests above then the link is up and we no
3241          * longer need to check for link */
3242         mac->get_link_status = FALSE;
3243
3244 out:
3245         return ret_val;
3246 }
3247
3248
3249 static int
3250 igbvf_dev_configure(struct rte_eth_dev *dev)
3251 {
3252         struct rte_eth_conf* conf = &dev->data->dev_conf;
3253
3254         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3255                      dev->data->port_id);
3256
3257         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3258                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3259
3260         /*
3261          * VF has no ability to enable/disable HW CRC
3262          * Keep the persistent behavior the same as Host PF
3263          */
3264 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3265         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3266                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3267                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3268         }
3269 #else
3270         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3271                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3272                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3273         }
3274 #endif
3275
3276         return 0;
3277 }
3278
3279 static int
3280 igbvf_dev_start(struct rte_eth_dev *dev)
3281 {
3282         struct e1000_hw *hw =
3283                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3284         struct e1000_adapter *adapter =
3285                 E1000_DEV_PRIVATE(dev->data->dev_private);
3286         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3287         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3288         int ret;
3289         uint32_t intr_vector = 0;
3290
3291         PMD_INIT_FUNC_TRACE();
3292
3293         hw->mac.ops.reset_hw(hw);
3294         adapter->stopped = 0;
3295
3296         /* Set all vfta */
3297         igbvf_set_vfta_all(dev,1);
3298
3299         eth_igbvf_tx_init(dev);
3300
3301         /* This can fail when allocating mbufs for descriptor rings */
3302         ret = eth_igbvf_rx_init(dev);
3303         if (ret) {
3304                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3305                 igb_dev_clear_queues(dev);
3306                 return ret;
3307         }
3308
3309         /* check and configure queue intr-vector mapping */
3310         if (rte_intr_cap_multiple(intr_handle) &&
3311             dev->data->dev_conf.intr_conf.rxq) {
3312                 intr_vector = dev->data->nb_rx_queues;
3313                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3314                 if (ret)
3315                         return ret;
3316         }
3317
3318         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3319                 intr_handle->intr_vec =
3320                         rte_zmalloc("intr_vec",
3321                                     dev->data->nb_rx_queues * sizeof(int), 0);
3322                 if (!intr_handle->intr_vec) {
3323                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3324                                      " intr_vec", dev->data->nb_rx_queues);
3325                         return -ENOMEM;
3326                 }
3327         }
3328
3329         eth_igbvf_configure_msix_intr(dev);
3330
3331         /* enable uio/vfio intr/eventfd mapping */
3332         rte_intr_enable(intr_handle);
3333
3334         /* resume enabled intr since hw reset */
3335         igbvf_intr_enable(dev);
3336
3337         return 0;
3338 }
3339
3340 static void
3341 igbvf_dev_stop(struct rte_eth_dev *dev)
3342 {
3343         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3344         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3345         struct e1000_adapter *adapter =
3346                 E1000_DEV_PRIVATE(dev->data->dev_private);
3347
3348         if (adapter->stopped)
3349                 return;
3350
3351         PMD_INIT_FUNC_TRACE();
3352
3353         igbvf_stop_adapter(dev);
3354
3355         /*
3356           * Clear what we set, but we still keep shadow_vfta to
3357           * restore after device starts
3358           */
3359         igbvf_set_vfta_all(dev,0);
3360
3361         igb_dev_clear_queues(dev);
3362
3363         /* disable intr eventfd mapping */
3364         rte_intr_disable(intr_handle);
3365
3366         /* Clean datapath event and queue/vec mapping */
3367         rte_intr_efd_disable(intr_handle);
3368         if (intr_handle->intr_vec) {
3369                 rte_free(intr_handle->intr_vec);
3370                 intr_handle->intr_vec = NULL;
3371         }
3372
3373         adapter->stopped = true;
3374 }
3375
3376 static int
3377 igbvf_dev_close(struct rte_eth_dev *dev)
3378 {
3379         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3380         struct rte_ether_addr addr;
3381         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3382
3383         PMD_INIT_FUNC_TRACE();
3384
3385         e1000_reset_hw(hw);
3386
3387         igbvf_dev_stop(dev);
3388
3389         igb_dev_free_queues(dev);
3390
3391         /**
3392          * reprogram the RAR with a zero mac address,
3393          * to ensure that the VF traffic goes to the PF
3394          * after stop, close and detach of the VF.
3395          **/
3396
3397         memset(&addr, 0, sizeof(addr));
3398         igbvf_default_mac_addr_set(dev, &addr);
3399
3400         dev->dev_ops = NULL;
3401         dev->rx_pkt_burst = NULL;
3402         dev->tx_pkt_burst = NULL;
3403
3404         rte_intr_callback_unregister(&pci_dev->intr_handle,
3405                                      eth_igbvf_interrupt_handler,
3406                                      (void *)dev);
3407
3408         return 0;
3409 }
3410
3411 static int
3412 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3413 {
3414         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3415
3416         /* Set both unicast and multicast promisc */
3417         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3418
3419         return 0;
3420 }
3421
3422 static int
3423 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3424 {
3425         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3426
3427         /* If in allmulticast mode leave multicast promisc */
3428         if (dev->data->all_multicast == 1)
3429                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3430         else
3431                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3432
3433         return 0;
3434 }
3435
3436 static int
3437 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3438 {
3439         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3440
3441         /* In promiscuous mode multicast promisc already set */
3442         if (dev->data->promiscuous == 0)
3443                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3444
3445         return 0;
3446 }
3447
3448 static int
3449 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3450 {
3451         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3452
3453         /* In promiscuous mode leave multicast promisc enabled */
3454         if (dev->data->promiscuous == 0)
3455                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3456
3457         return 0;
3458 }
3459
3460 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3461 {
3462         struct e1000_mbx_info *mbx = &hw->mbx;
3463         uint32_t msgbuf[2];
3464         s32 err;
3465
3466         /* After set vlan, vlan strip will also be enabled in igb driver*/
3467         msgbuf[0] = E1000_VF_SET_VLAN;
3468         msgbuf[1] = vid;
3469         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3470         if (on)
3471                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3472
3473         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3474         if (err)
3475                 goto mbx_err;
3476
3477         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3478         if (err)
3479                 goto mbx_err;
3480
3481         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3482         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3483                 err = -EINVAL;
3484
3485 mbx_err:
3486         return err;
3487 }
3488
3489 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3490 {
3491         struct e1000_hw *hw =
3492                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3493         struct e1000_vfta * shadow_vfta =
3494                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3495         int i = 0, j = 0, vfta = 0, mask = 1;
3496
3497         for (i = 0; i < IGB_VFTA_SIZE; i++){
3498                 vfta = shadow_vfta->vfta[i];
3499                 if(vfta){
3500                         mask = 1;
3501                         for (j = 0; j < 32; j++){
3502                                 if(vfta & mask)
3503                                         igbvf_set_vfta(hw,
3504                                                 (uint16_t)((i<<5)+j), on);
3505                                 mask<<=1;
3506                         }
3507                 }
3508         }
3509
3510 }
3511
3512 static int
3513 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3514 {
3515         struct e1000_hw *hw =
3516                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3517         struct e1000_vfta * shadow_vfta =
3518                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3519         uint32_t vid_idx = 0;
3520         uint32_t vid_bit = 0;
3521         int ret = 0;
3522
3523         PMD_INIT_FUNC_TRACE();
3524
3525         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3526         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3527         if(ret){
3528                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3529                 return ret;
3530         }
3531         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3532         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3533
3534         /*Save what we set and retore it after device reset*/
3535         if (on)
3536                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3537         else
3538                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3539
3540         return 0;
3541 }
3542
3543 static int
3544 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3545 {
3546         struct e1000_hw *hw =
3547                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3548
3549         /* index is not used by rar_set() */
3550         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3551         return 0;
3552 }
3553
3554
3555 static int
3556 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3557                         struct rte_eth_rss_reta_entry64 *reta_conf,
3558                         uint16_t reta_size)
3559 {
3560         uint8_t i, j, mask;
3561         uint32_t reta, r;
3562         uint16_t idx, shift;
3563         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3564
3565         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3566                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3567                         "(%d) doesn't match the number hardware can supported "
3568                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3569                 return -EINVAL;
3570         }
3571
3572         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3573                 idx = i / RTE_RETA_GROUP_SIZE;
3574                 shift = i % RTE_RETA_GROUP_SIZE;
3575                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3576                                                 IGB_4_BIT_MASK);
3577                 if (!mask)
3578                         continue;
3579                 if (mask == IGB_4_BIT_MASK)
3580                         r = 0;
3581                 else
3582                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3583                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3584                         if (mask & (0x1 << j))
3585                                 reta |= reta_conf[idx].reta[shift + j] <<
3586                                                         (CHAR_BIT * j);
3587                         else
3588                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3589                 }
3590                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3591         }
3592
3593         return 0;
3594 }
3595
3596 static int
3597 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3598                        struct rte_eth_rss_reta_entry64 *reta_conf,
3599                        uint16_t reta_size)
3600 {
3601         uint8_t i, j, mask;
3602         uint32_t reta;
3603         uint16_t idx, shift;
3604         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3605
3606         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3607                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3608                         "(%d) doesn't match the number hardware can supported "
3609                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3610                 return -EINVAL;
3611         }
3612
3613         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3614                 idx = i / RTE_RETA_GROUP_SIZE;
3615                 shift = i % RTE_RETA_GROUP_SIZE;
3616                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3617                                                 IGB_4_BIT_MASK);
3618                 if (!mask)
3619                         continue;
3620                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3621                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3622                         if (mask & (0x1 << j))
3623                                 reta_conf[idx].reta[shift + j] =
3624                                         ((reta >> (CHAR_BIT * j)) &
3625                                                 IGB_8_BIT_MASK);
3626                 }
3627         }
3628
3629         return 0;
3630 }
3631
3632 int
3633 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3634                         struct rte_eth_syn_filter *filter,
3635                         bool add)
3636 {
3637         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3638         struct e1000_filter_info *filter_info =
3639                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3640         uint32_t synqf, rfctl;
3641
3642         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3643                 return -EINVAL;
3644
3645         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3646
3647         if (add) {
3648                 if (synqf & E1000_SYN_FILTER_ENABLE)
3649                         return -EINVAL;
3650
3651                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3652                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3653
3654                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3655                 if (filter->hig_pri)
3656                         rfctl |= E1000_RFCTL_SYNQFP;
3657                 else
3658                         rfctl &= ~E1000_RFCTL_SYNQFP;
3659
3660                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3661         } else {
3662                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3663                         return -ENOENT;
3664                 synqf = 0;
3665         }
3666
3667         filter_info->syn_info = synqf;
3668         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3669         E1000_WRITE_FLUSH(hw);
3670         return 0;
3671 }
3672
3673 static int
3674 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3675                         struct rte_eth_syn_filter *filter)
3676 {
3677         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3678         uint32_t synqf, rfctl;
3679
3680         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3681         if (synqf & E1000_SYN_FILTER_ENABLE) {
3682                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3683                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3684                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3685                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3686                 return 0;
3687         }
3688
3689         return -ENOENT;
3690 }
3691
3692 static int
3693 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3694                         enum rte_filter_op filter_op,
3695                         void *arg)
3696 {
3697         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3698         int ret;
3699
3700         MAC_TYPE_FILTER_SUP(hw->mac.type);
3701
3702         if (filter_op == RTE_ETH_FILTER_NOP)
3703                 return 0;
3704
3705         if (arg == NULL) {
3706                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3707                             filter_op);
3708                 return -EINVAL;
3709         }
3710
3711         switch (filter_op) {
3712         case RTE_ETH_FILTER_ADD:
3713                 ret = eth_igb_syn_filter_set(dev,
3714                                 (struct rte_eth_syn_filter *)arg,
3715                                 TRUE);
3716                 break;
3717         case RTE_ETH_FILTER_DELETE:
3718                 ret = eth_igb_syn_filter_set(dev,
3719                                 (struct rte_eth_syn_filter *)arg,
3720                                 FALSE);
3721                 break;
3722         case RTE_ETH_FILTER_GET:
3723                 ret = eth_igb_syn_filter_get(dev,
3724                                 (struct rte_eth_syn_filter *)arg);
3725                 break;
3726         default:
3727                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3728                 ret = -EINVAL;
3729                 break;
3730         }
3731
3732         return ret;
3733 }
3734
3735 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3736 static inline int
3737 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3738                         struct e1000_2tuple_filter_info *filter_info)
3739 {
3740         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3741                 return -EINVAL;
3742         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3743                 return -EINVAL;  /* filter index is out of range. */
3744         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3745                 return -EINVAL;  /* flags is invalid. */
3746
3747         switch (filter->dst_port_mask) {
3748         case UINT16_MAX:
3749                 filter_info->dst_port_mask = 0;
3750                 filter_info->dst_port = filter->dst_port;
3751                 break;
3752         case 0:
3753                 filter_info->dst_port_mask = 1;
3754                 break;
3755         default:
3756                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3757                 return -EINVAL;
3758         }
3759
3760         switch (filter->proto_mask) {
3761         case UINT8_MAX:
3762                 filter_info->proto_mask = 0;
3763                 filter_info->proto = filter->proto;
3764                 break;
3765         case 0:
3766                 filter_info->proto_mask = 1;
3767                 break;
3768         default:
3769                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3770                 return -EINVAL;
3771         }
3772
3773         filter_info->priority = (uint8_t)filter->priority;
3774         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3775                 filter_info->tcp_flags = filter->tcp_flags;
3776         else
3777                 filter_info->tcp_flags = 0;
3778
3779         return 0;
3780 }
3781
3782 static inline struct e1000_2tuple_filter *
3783 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3784                         struct e1000_2tuple_filter_info *key)
3785 {
3786         struct e1000_2tuple_filter *it;
3787
3788         TAILQ_FOREACH(it, filter_list, entries) {
3789                 if (memcmp(key, &it->filter_info,
3790                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3791                         return it;
3792                 }
3793         }
3794         return NULL;
3795 }
3796
3797 /* inject a igb 2tuple filter to HW */
3798 static inline void
3799 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3800                            struct e1000_2tuple_filter *filter)
3801 {
3802         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3803         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3804         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3805         int i;
3806
3807         i = filter->index;
3808         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3809         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3810                 imir |= E1000_IMIR_PORT_BP;
3811         else
3812                 imir &= ~E1000_IMIR_PORT_BP;
3813
3814         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3815
3816         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3817         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3818         ttqf |= (uint32_t)(filter->filter_info.proto &
3819                                                 E1000_TTQF_PROTOCOL_MASK);
3820         if (filter->filter_info.proto_mask == 0)
3821                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3822
3823         /* tcp flags bits setting. */
3824         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3825                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3826                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3827                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3828                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3829                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3830                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3831                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3832                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3833                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3834                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3835                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3836                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3837         } else {
3838                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3839         }
3840         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3841         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3842         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3843 }
3844
3845 /*
3846  * igb_add_2tuple_filter - add a 2tuple filter
3847  *
3848  * @param
3849  * dev: Pointer to struct rte_eth_dev.
3850  * ntuple_filter: ponter to the filter that will be added.
3851  *
3852  * @return
3853  *    - On success, zero.
3854  *    - On failure, a negative value.
3855  */
3856 static int
3857 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3858                         struct rte_eth_ntuple_filter *ntuple_filter)
3859 {
3860         struct e1000_filter_info *filter_info =
3861                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3862         struct e1000_2tuple_filter *filter;
3863         int i, ret;
3864
3865         filter = rte_zmalloc("e1000_2tuple_filter",
3866                         sizeof(struct e1000_2tuple_filter), 0);
3867         if (filter == NULL)
3868                 return -ENOMEM;
3869
3870         ret = ntuple_filter_to_2tuple(ntuple_filter,
3871                                       &filter->filter_info);
3872         if (ret < 0) {
3873                 rte_free(filter);
3874                 return ret;
3875         }
3876         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3877                                          &filter->filter_info) != NULL) {
3878                 PMD_DRV_LOG(ERR, "filter exists.");
3879                 rte_free(filter);
3880                 return -EEXIST;
3881         }
3882         filter->queue = ntuple_filter->queue;
3883
3884         /*
3885          * look for an unused 2tuple filter index,
3886          * and insert the filter to list.
3887          */
3888         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3889                 if (!(filter_info->twotuple_mask & (1 << i))) {
3890                         filter_info->twotuple_mask |= 1 << i;
3891                         filter->index = i;
3892                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3893                                           filter,
3894                                           entries);
3895                         break;
3896                 }
3897         }
3898         if (i >= E1000_MAX_TTQF_FILTERS) {
3899                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3900                 rte_free(filter);
3901                 return -ENOSYS;
3902         }
3903
3904         igb_inject_2uple_filter(dev, filter);
3905         return 0;
3906 }
3907
3908 int
3909 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3910                         struct e1000_2tuple_filter *filter)
3911 {
3912         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3913         struct e1000_filter_info *filter_info =
3914                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3915
3916         filter_info->twotuple_mask &= ~(1 << filter->index);
3917         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3918         rte_free(filter);
3919
3920         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3921         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3922         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3923         return 0;
3924 }
3925
3926 /*
3927  * igb_remove_2tuple_filter - remove a 2tuple filter
3928  *
3929  * @param
3930  * dev: Pointer to struct rte_eth_dev.
3931  * ntuple_filter: ponter to the filter that will be removed.
3932  *
3933  * @return
3934  *    - On success, zero.
3935  *    - On failure, a negative value.
3936  */
3937 static int
3938 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3939                         struct rte_eth_ntuple_filter *ntuple_filter)
3940 {
3941         struct e1000_filter_info *filter_info =
3942                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3943         struct e1000_2tuple_filter_info filter_2tuple;
3944         struct e1000_2tuple_filter *filter;
3945         int ret;
3946
3947         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3948         ret = ntuple_filter_to_2tuple(ntuple_filter,
3949                                       &filter_2tuple);
3950         if (ret < 0)
3951                 return ret;
3952
3953         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3954                                          &filter_2tuple);
3955         if (filter == NULL) {
3956                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3957                 return -ENOENT;
3958         }
3959
3960         igb_delete_2tuple_filter(dev, filter);
3961
3962         return 0;
3963 }
3964
3965 /* inject a igb flex filter to HW */
3966 static inline void
3967 igb_inject_flex_filter(struct rte_eth_dev *dev,
3968                            struct e1000_flex_filter *filter)
3969 {
3970         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3971         uint32_t wufc, queueing;
3972         uint32_t reg_off;
3973         uint8_t i, j = 0;
3974
3975         wufc = E1000_READ_REG(hw, E1000_WUFC);
3976         if (filter->index < E1000_MAX_FHFT)
3977                 reg_off = E1000_FHFT(filter->index);
3978         else
3979                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3980
3981         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3982                         (E1000_WUFC_FLX0 << filter->index));
3983         queueing = filter->filter_info.len |
3984                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3985                 (filter->filter_info.priority <<
3986                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3987         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3988                         queueing);
3989
3990         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3991                 E1000_WRITE_REG(hw, reg_off,
3992                                 filter->filter_info.dwords[j]);
3993                 reg_off += sizeof(uint32_t);
3994                 E1000_WRITE_REG(hw, reg_off,
3995                                 filter->filter_info.dwords[++j]);
3996                 reg_off += sizeof(uint32_t);
3997                 E1000_WRITE_REG(hw, reg_off,
3998                         (uint32_t)filter->filter_info.mask[i]);
3999                 reg_off += sizeof(uint32_t) * 2;
4000                 ++j;
4001         }
4002 }
4003
4004 static inline struct e1000_flex_filter *
4005 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
4006                         struct e1000_flex_filter_info *key)
4007 {
4008         struct e1000_flex_filter *it;
4009
4010         TAILQ_FOREACH(it, filter_list, entries) {
4011                 if (memcmp(key, &it->filter_info,
4012                         sizeof(struct e1000_flex_filter_info)) == 0)
4013                         return it;
4014         }
4015
4016         return NULL;
4017 }
4018
4019 /* remove a flex byte filter
4020  * @param
4021  * dev: Pointer to struct rte_eth_dev.
4022  * filter: the pointer of the filter will be removed.
4023  */
4024 void
4025 igb_remove_flex_filter(struct rte_eth_dev *dev,
4026                         struct e1000_flex_filter *filter)
4027 {
4028         struct e1000_filter_info *filter_info =
4029                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4030         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4031         uint32_t wufc, i;
4032         uint32_t reg_off;
4033
4034         wufc = E1000_READ_REG(hw, E1000_WUFC);
4035         if (filter->index < E1000_MAX_FHFT)
4036                 reg_off = E1000_FHFT(filter->index);
4037         else
4038                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4039
4040         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4041                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4042
4043         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4044                 (~(E1000_WUFC_FLX0 << filter->index)));
4045
4046         filter_info->flex_mask &= ~(1 << filter->index);
4047         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4048         rte_free(filter);
4049 }
4050
4051 int
4052 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4053                         struct rte_eth_flex_filter *filter,
4054                         bool add)
4055 {
4056         struct e1000_filter_info *filter_info =
4057                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4058         struct e1000_flex_filter *flex_filter, *it;
4059         uint32_t mask;
4060         uint8_t shift, i;
4061
4062         flex_filter = rte_zmalloc("e1000_flex_filter",
4063                         sizeof(struct e1000_flex_filter), 0);
4064         if (flex_filter == NULL)
4065                 return -ENOMEM;
4066
4067         flex_filter->filter_info.len = filter->len;
4068         flex_filter->filter_info.priority = filter->priority;
4069         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4070         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4071                 mask = 0;
4072                 /* reverse bits in flex filter's mask*/
4073                 for (shift = 0; shift < CHAR_BIT; shift++) {
4074                         if (filter->mask[i] & (0x01 << shift))
4075                                 mask |= (0x80 >> shift);
4076                 }
4077                 flex_filter->filter_info.mask[i] = mask;
4078         }
4079
4080         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4081                                 &flex_filter->filter_info);
4082         if (it == NULL && !add) {
4083                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4084                 rte_free(flex_filter);
4085                 return -ENOENT;
4086         }
4087         if (it != NULL && add) {
4088                 PMD_DRV_LOG(ERR, "filter exists.");
4089                 rte_free(flex_filter);
4090                 return -EEXIST;
4091         }
4092
4093         if (add) {
4094                 flex_filter->queue = filter->queue;
4095                 /*
4096                  * look for an unused flex filter index
4097                  * and insert the filter into the list.
4098                  */
4099                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4100                         if (!(filter_info->flex_mask & (1 << i))) {
4101                                 filter_info->flex_mask |= 1 << i;
4102                                 flex_filter->index = i;
4103                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4104                                         flex_filter,
4105                                         entries);
4106                                 break;
4107                         }
4108                 }
4109                 if (i >= E1000_MAX_FLEX_FILTERS) {
4110                         PMD_DRV_LOG(ERR, "flex filters are full.");
4111                         rte_free(flex_filter);
4112                         return -ENOSYS;
4113                 }
4114
4115                 igb_inject_flex_filter(dev, flex_filter);
4116
4117         } else {
4118                 igb_remove_flex_filter(dev, it);
4119                 rte_free(flex_filter);
4120         }
4121
4122         return 0;
4123 }
4124
4125 static int
4126 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4127                         struct rte_eth_flex_filter *filter)
4128 {
4129         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4130         struct e1000_filter_info *filter_info =
4131                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4132         struct e1000_flex_filter flex_filter, *it;
4133         uint32_t wufc, queueing, wufc_en = 0;
4134
4135         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4136         flex_filter.filter_info.len = filter->len;
4137         flex_filter.filter_info.priority = filter->priority;
4138         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4139         memcpy(flex_filter.filter_info.mask, filter->mask,
4140                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4141
4142         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4143                                 &flex_filter.filter_info);
4144         if (it == NULL) {
4145                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4146                 return -ENOENT;
4147         }
4148
4149         wufc = E1000_READ_REG(hw, E1000_WUFC);
4150         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4151
4152         if ((wufc & wufc_en) == wufc_en) {
4153                 uint32_t reg_off = 0;
4154                 if (it->index < E1000_MAX_FHFT)
4155                         reg_off = E1000_FHFT(it->index);
4156                 else
4157                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4158
4159                 queueing = E1000_READ_REG(hw,
4160                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4161                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4162                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4163                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4164                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4165                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4166                 return 0;
4167         }
4168         return -ENOENT;
4169 }
4170
4171 static int
4172 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4173                         enum rte_filter_op filter_op,
4174                         void *arg)
4175 {
4176         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4177         struct rte_eth_flex_filter *filter;
4178         int ret = 0;
4179
4180         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4181
4182         if (filter_op == RTE_ETH_FILTER_NOP)
4183                 return ret;
4184
4185         if (arg == NULL) {
4186                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4187                             filter_op);
4188                 return -EINVAL;
4189         }
4190
4191         filter = (struct rte_eth_flex_filter *)arg;
4192         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4193             || filter->len % sizeof(uint64_t) != 0) {
4194                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4195                 return -EINVAL;
4196         }
4197         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4198                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4199                 return -EINVAL;
4200         }
4201
4202         switch (filter_op) {
4203         case RTE_ETH_FILTER_ADD:
4204                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4205                 break;
4206         case RTE_ETH_FILTER_DELETE:
4207                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4208                 break;
4209         case RTE_ETH_FILTER_GET:
4210                 ret = eth_igb_get_flex_filter(dev, filter);
4211                 break;
4212         default:
4213                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4214                 ret = -EINVAL;
4215                 break;
4216         }
4217
4218         return ret;
4219 }
4220
4221 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4222 static inline int
4223 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4224                         struct e1000_5tuple_filter_info *filter_info)
4225 {
4226         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4227                 return -EINVAL;
4228         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4229                 return -EINVAL;  /* filter index is out of range. */
4230         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4231                 return -EINVAL;  /* flags is invalid. */
4232
4233         switch (filter->dst_ip_mask) {
4234         case UINT32_MAX:
4235                 filter_info->dst_ip_mask = 0;
4236                 filter_info->dst_ip = filter->dst_ip;
4237                 break;
4238         case 0:
4239                 filter_info->dst_ip_mask = 1;
4240                 break;
4241         default:
4242                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4243                 return -EINVAL;
4244         }
4245
4246         switch (filter->src_ip_mask) {
4247         case UINT32_MAX:
4248                 filter_info->src_ip_mask = 0;
4249                 filter_info->src_ip = filter->src_ip;
4250                 break;
4251         case 0:
4252                 filter_info->src_ip_mask = 1;
4253                 break;
4254         default:
4255                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4256                 return -EINVAL;
4257         }
4258
4259         switch (filter->dst_port_mask) {
4260         case UINT16_MAX:
4261                 filter_info->dst_port_mask = 0;
4262                 filter_info->dst_port = filter->dst_port;
4263                 break;
4264         case 0:
4265                 filter_info->dst_port_mask = 1;
4266                 break;
4267         default:
4268                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4269                 return -EINVAL;
4270         }
4271
4272         switch (filter->src_port_mask) {
4273         case UINT16_MAX:
4274                 filter_info->src_port_mask = 0;
4275                 filter_info->src_port = filter->src_port;
4276                 break;
4277         case 0:
4278                 filter_info->src_port_mask = 1;
4279                 break;
4280         default:
4281                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4282                 return -EINVAL;
4283         }
4284
4285         switch (filter->proto_mask) {
4286         case UINT8_MAX:
4287                 filter_info->proto_mask = 0;
4288                 filter_info->proto = filter->proto;
4289                 break;
4290         case 0:
4291                 filter_info->proto_mask = 1;
4292                 break;
4293         default:
4294                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4295                 return -EINVAL;
4296         }
4297
4298         filter_info->priority = (uint8_t)filter->priority;
4299         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4300                 filter_info->tcp_flags = filter->tcp_flags;
4301         else
4302                 filter_info->tcp_flags = 0;
4303
4304         return 0;
4305 }
4306
4307 static inline struct e1000_5tuple_filter *
4308 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4309                         struct e1000_5tuple_filter_info *key)
4310 {
4311         struct e1000_5tuple_filter *it;
4312
4313         TAILQ_FOREACH(it, filter_list, entries) {
4314                 if (memcmp(key, &it->filter_info,
4315                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4316                         return it;
4317                 }
4318         }
4319         return NULL;
4320 }
4321
4322 /* inject a igb 5-tuple filter to HW */
4323 static inline void
4324 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4325                            struct e1000_5tuple_filter *filter)
4326 {
4327         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4328         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4329         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4330         uint8_t i;
4331
4332         i = filter->index;
4333         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4334         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4335                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4336         if (filter->filter_info.dst_ip_mask == 0)
4337                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4338         if (filter->filter_info.src_port_mask == 0)
4339                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4340         if (filter->filter_info.proto_mask == 0)
4341                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4342         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4343                 E1000_FTQF_QUEUE_MASK;
4344         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4345         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4346         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4347         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4348
4349         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4350         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4351
4352         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4353         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4354                 imir |= E1000_IMIR_PORT_BP;
4355         else
4356                 imir &= ~E1000_IMIR_PORT_BP;
4357         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4358
4359         /* tcp flags bits setting. */
4360         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4361                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4362                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4363                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4364                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4365                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4366                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4367                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4368                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4369                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4370                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4371                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4372                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4373         } else {
4374                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4375         }
4376         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4377         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4378 }
4379
4380 /*
4381  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4382  *
4383  * @param
4384  * dev: Pointer to struct rte_eth_dev.
4385  * ntuple_filter: ponter to the filter that will be added.
4386  *
4387  * @return
4388  *    - On success, zero.
4389  *    - On failure, a negative value.
4390  */
4391 static int
4392 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4393                         struct rte_eth_ntuple_filter *ntuple_filter)
4394 {
4395         struct e1000_filter_info *filter_info =
4396                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4397         struct e1000_5tuple_filter *filter;
4398         uint8_t i;
4399         int ret;
4400
4401         filter = rte_zmalloc("e1000_5tuple_filter",
4402                         sizeof(struct e1000_5tuple_filter), 0);
4403         if (filter == NULL)
4404                 return -ENOMEM;
4405
4406         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4407                                             &filter->filter_info);
4408         if (ret < 0) {
4409                 rte_free(filter);
4410                 return ret;
4411         }
4412
4413         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4414                                          &filter->filter_info) != NULL) {
4415                 PMD_DRV_LOG(ERR, "filter exists.");
4416                 rte_free(filter);
4417                 return -EEXIST;
4418         }
4419         filter->queue = ntuple_filter->queue;
4420
4421         /*
4422          * look for an unused 5tuple filter index,
4423          * and insert the filter to list.
4424          */
4425         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4426                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4427                         filter_info->fivetuple_mask |= 1 << i;
4428                         filter->index = i;
4429                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4430                                           filter,
4431                                           entries);
4432                         break;
4433                 }
4434         }
4435         if (i >= E1000_MAX_FTQF_FILTERS) {
4436                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4437                 rte_free(filter);
4438                 return -ENOSYS;
4439         }
4440
4441         igb_inject_5tuple_filter_82576(dev, filter);
4442         return 0;
4443 }
4444
4445 int
4446 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4447                                 struct e1000_5tuple_filter *filter)
4448 {
4449         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4450         struct e1000_filter_info *filter_info =
4451                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4452
4453         filter_info->fivetuple_mask &= ~(1 << filter->index);
4454         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4455         rte_free(filter);
4456
4457         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4458                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4459         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4460         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4461         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4462         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4463         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4464         return 0;
4465 }
4466
4467 /*
4468  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4469  *
4470  * @param
4471  * dev: Pointer to struct rte_eth_dev.
4472  * ntuple_filter: ponter to the filter that will be removed.
4473  *
4474  * @return
4475  *    - On success, zero.
4476  *    - On failure, a negative value.
4477  */
4478 static int
4479 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4480                                 struct rte_eth_ntuple_filter *ntuple_filter)
4481 {
4482         struct e1000_filter_info *filter_info =
4483                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4484         struct e1000_5tuple_filter_info filter_5tuple;
4485         struct e1000_5tuple_filter *filter;
4486         int ret;
4487
4488         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4489         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4490                                             &filter_5tuple);
4491         if (ret < 0)
4492                 return ret;
4493
4494         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4495                                          &filter_5tuple);
4496         if (filter == NULL) {
4497                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4498                 return -ENOENT;
4499         }
4500
4501         igb_delete_5tuple_filter_82576(dev, filter);
4502
4503         return 0;
4504 }
4505
4506 static int
4507 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4508 {
4509         uint32_t rctl;
4510         struct e1000_hw *hw;
4511         struct rte_eth_dev_info dev_info;
4512         uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4513         int ret;
4514
4515         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4516
4517 #ifdef RTE_LIBRTE_82571_SUPPORT
4518         /* XXX: not bigger than max_rx_pktlen */
4519         if (hw->mac.type == e1000_82571)
4520                 return -ENOTSUP;
4521 #endif
4522         ret = eth_igb_infos_get(dev, &dev_info);
4523         if (ret != 0)
4524                 return ret;
4525
4526         /* check that mtu is within the allowed range */
4527         if (mtu < RTE_ETHER_MIN_MTU ||
4528                         frame_size > dev_info.max_rx_pktlen)
4529                 return -EINVAL;
4530
4531         /* refuse mtu that requires the support of scattered packets when this
4532          * feature has not been enabled before. */
4533         if (!dev->data->scattered_rx &&
4534             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4535                 return -EINVAL;
4536
4537         rctl = E1000_READ_REG(hw, E1000_RCTL);
4538
4539         /* switch to jumbo mode if needed */
4540         if (frame_size > RTE_ETHER_MAX_LEN) {
4541                 dev->data->dev_conf.rxmode.offloads |=
4542                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4543                 rctl |= E1000_RCTL_LPE;
4544         } else {
4545                 dev->data->dev_conf.rxmode.offloads &=
4546                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4547                 rctl &= ~E1000_RCTL_LPE;
4548         }
4549         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4550
4551         /* update max frame size */
4552         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4553
4554         E1000_WRITE_REG(hw, E1000_RLPML,
4555                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4556
4557         return 0;
4558 }
4559
4560 /*
4561  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4562  *
4563  * @param
4564  * dev: Pointer to struct rte_eth_dev.
4565  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4566  * add: if true, add filter, if false, remove filter
4567  *
4568  * @return
4569  *    - On success, zero.
4570  *    - On failure, a negative value.
4571  */
4572 int
4573 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4574                         struct rte_eth_ntuple_filter *ntuple_filter,
4575                         bool add)
4576 {
4577         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4578         int ret;
4579
4580         switch (ntuple_filter->flags) {
4581         case RTE_5TUPLE_FLAGS:
4582         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4583                 if (hw->mac.type != e1000_82576)
4584                         return -ENOTSUP;
4585                 if (add)
4586                         ret = igb_add_5tuple_filter_82576(dev,
4587                                                           ntuple_filter);
4588                 else
4589                         ret = igb_remove_5tuple_filter_82576(dev,
4590                                                              ntuple_filter);
4591                 break;
4592         case RTE_2TUPLE_FLAGS:
4593         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4594                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4595                         hw->mac.type != e1000_i210 &&
4596                         hw->mac.type != e1000_i211)
4597                         return -ENOTSUP;
4598                 if (add)
4599                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4600                 else
4601                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4602                 break;
4603         default:
4604                 ret = -EINVAL;
4605                 break;
4606         }
4607
4608         return ret;
4609 }
4610
4611 /*
4612  * igb_get_ntuple_filter - get a ntuple filter
4613  *
4614  * @param
4615  * dev: Pointer to struct rte_eth_dev.
4616  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4617  *
4618  * @return
4619  *    - On success, zero.
4620  *    - On failure, a negative value.
4621  */
4622 static int
4623 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4624                         struct rte_eth_ntuple_filter *ntuple_filter)
4625 {
4626         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4627         struct e1000_filter_info *filter_info =
4628                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4629         struct e1000_5tuple_filter_info filter_5tuple;
4630         struct e1000_2tuple_filter_info filter_2tuple;
4631         struct e1000_5tuple_filter *p_5tuple_filter;
4632         struct e1000_2tuple_filter *p_2tuple_filter;
4633         int ret;
4634
4635         switch (ntuple_filter->flags) {
4636         case RTE_5TUPLE_FLAGS:
4637         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4638                 if (hw->mac.type != e1000_82576)
4639                         return -ENOTSUP;
4640                 memset(&filter_5tuple,
4641                         0,
4642                         sizeof(struct e1000_5tuple_filter_info));
4643                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4644                                                     &filter_5tuple);
4645                 if (ret < 0)
4646                         return ret;
4647                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4648                                         &filter_info->fivetuple_list,
4649                                         &filter_5tuple);
4650                 if (p_5tuple_filter == NULL) {
4651                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4652                         return -ENOENT;
4653                 }
4654                 ntuple_filter->queue = p_5tuple_filter->queue;
4655                 break;
4656         case RTE_2TUPLE_FLAGS:
4657         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4658                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4659                         return -ENOTSUP;
4660                 memset(&filter_2tuple,
4661                         0,
4662                         sizeof(struct e1000_2tuple_filter_info));
4663                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4664                 if (ret < 0)
4665                         return ret;
4666                 p_2tuple_filter = igb_2tuple_filter_lookup(
4667                                         &filter_info->twotuple_list,
4668                                         &filter_2tuple);
4669                 if (p_2tuple_filter == NULL) {
4670                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4671                         return -ENOENT;
4672                 }
4673                 ntuple_filter->queue = p_2tuple_filter->queue;
4674                 break;
4675         default:
4676                 ret = -EINVAL;
4677                 break;
4678         }
4679
4680         return 0;
4681 }
4682
4683 /*
4684  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4685  * @dev: pointer to rte_eth_dev structure
4686  * @filter_op:operation will be taken.
4687  * @arg: a pointer to specific structure corresponding to the filter_op
4688  */
4689 static int
4690 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4691                                 enum rte_filter_op filter_op,
4692                                 void *arg)
4693 {
4694         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4695         int ret;
4696
4697         MAC_TYPE_FILTER_SUP(hw->mac.type);
4698
4699         if (filter_op == RTE_ETH_FILTER_NOP)
4700                 return 0;
4701
4702         if (arg == NULL) {
4703                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4704                             filter_op);
4705                 return -EINVAL;
4706         }
4707
4708         switch (filter_op) {
4709         case RTE_ETH_FILTER_ADD:
4710                 ret = igb_add_del_ntuple_filter(dev,
4711                         (struct rte_eth_ntuple_filter *)arg,
4712                         TRUE);
4713                 break;
4714         case RTE_ETH_FILTER_DELETE:
4715                 ret = igb_add_del_ntuple_filter(dev,
4716                         (struct rte_eth_ntuple_filter *)arg,
4717                         FALSE);
4718                 break;
4719         case RTE_ETH_FILTER_GET:
4720                 ret = igb_get_ntuple_filter(dev,
4721                         (struct rte_eth_ntuple_filter *)arg);
4722                 break;
4723         default:
4724                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4725                 ret = -EINVAL;
4726                 break;
4727         }
4728         return ret;
4729 }
4730
4731 static inline int
4732 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4733                         uint16_t ethertype)
4734 {
4735         int i;
4736
4737         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4738                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4739                     (filter_info->ethertype_mask & (1 << i)))
4740                         return i;
4741         }
4742         return -1;
4743 }
4744
4745 static inline int
4746 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4747                         uint16_t ethertype, uint32_t etqf)
4748 {
4749         int i;
4750
4751         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4752                 if (!(filter_info->ethertype_mask & (1 << i))) {
4753                         filter_info->ethertype_mask |= 1 << i;
4754                         filter_info->ethertype_filters[i].ethertype = ethertype;
4755                         filter_info->ethertype_filters[i].etqf = etqf;
4756                         return i;
4757                 }
4758         }
4759         return -1;
4760 }
4761
4762 int
4763 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4764                         uint8_t idx)
4765 {
4766         if (idx >= E1000_MAX_ETQF_FILTERS)
4767                 return -1;
4768         filter_info->ethertype_mask &= ~(1 << idx);
4769         filter_info->ethertype_filters[idx].ethertype = 0;
4770         filter_info->ethertype_filters[idx].etqf = 0;
4771         return idx;
4772 }
4773
4774
4775 int
4776 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4777                         struct rte_eth_ethertype_filter *filter,
4778                         bool add)
4779 {
4780         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4781         struct e1000_filter_info *filter_info =
4782                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4783         uint32_t etqf = 0;
4784         int ret;
4785
4786         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4787                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4788                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4789                         " ethertype filter.", filter->ether_type);
4790                 return -EINVAL;
4791         }
4792
4793         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4794                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4795                 return -EINVAL;
4796         }
4797         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4798                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4799                 return -EINVAL;
4800         }
4801
4802         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4803         if (ret >= 0 && add) {
4804                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4805                             filter->ether_type);
4806                 return -EEXIST;
4807         }
4808         if (ret < 0 && !add) {
4809                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4810                             filter->ether_type);
4811                 return -ENOENT;
4812         }
4813
4814         if (add) {
4815                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4816                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4817                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4818                 ret = igb_ethertype_filter_insert(filter_info,
4819                                 filter->ether_type, etqf);
4820                 if (ret < 0) {
4821                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4822                         return -ENOSYS;
4823                 }
4824         } else {
4825                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4826                 if (ret < 0)
4827                         return -ENOSYS;
4828         }
4829         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4830         E1000_WRITE_FLUSH(hw);
4831
4832         return 0;
4833 }
4834
4835 static int
4836 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4837                         struct rte_eth_ethertype_filter *filter)
4838 {
4839         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4840         struct e1000_filter_info *filter_info =
4841                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4842         uint32_t etqf;
4843         int ret;
4844
4845         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4846         if (ret < 0) {
4847                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4848                             filter->ether_type);
4849                 return -ENOENT;
4850         }
4851
4852         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4853         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4854                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4855                 filter->flags = 0;
4856                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4857                                 E1000_ETQF_QUEUE_SHIFT;
4858                 return 0;
4859         }
4860
4861         return -ENOENT;
4862 }
4863
4864 /*
4865  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4866  * @dev: pointer to rte_eth_dev structure
4867  * @filter_op:operation will be taken.
4868  * @arg: a pointer to specific structure corresponding to the filter_op
4869  */
4870 static int
4871 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4872                                 enum rte_filter_op filter_op,
4873                                 void *arg)
4874 {
4875         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4876         int ret;
4877
4878         MAC_TYPE_FILTER_SUP(hw->mac.type);
4879
4880         if (filter_op == RTE_ETH_FILTER_NOP)
4881                 return 0;
4882
4883         if (arg == NULL) {
4884                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4885                             filter_op);
4886                 return -EINVAL;
4887         }
4888
4889         switch (filter_op) {
4890         case RTE_ETH_FILTER_ADD:
4891                 ret = igb_add_del_ethertype_filter(dev,
4892                         (struct rte_eth_ethertype_filter *)arg,
4893                         TRUE);
4894                 break;
4895         case RTE_ETH_FILTER_DELETE:
4896                 ret = igb_add_del_ethertype_filter(dev,
4897                         (struct rte_eth_ethertype_filter *)arg,
4898                         FALSE);
4899                 break;
4900         case RTE_ETH_FILTER_GET:
4901                 ret = igb_get_ethertype_filter(dev,
4902                         (struct rte_eth_ethertype_filter *)arg);
4903                 break;
4904         default:
4905                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4906                 ret = -EINVAL;
4907                 break;
4908         }
4909         return ret;
4910 }
4911
4912 static int
4913 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4914                      enum rte_filter_type filter_type,
4915                      enum rte_filter_op filter_op,
4916                      void *arg)
4917 {
4918         int ret = 0;
4919
4920         switch (filter_type) {
4921         case RTE_ETH_FILTER_NTUPLE:
4922                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4923                 break;
4924         case RTE_ETH_FILTER_ETHERTYPE:
4925                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4926                 break;
4927         case RTE_ETH_FILTER_SYN:
4928                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4929                 break;
4930         case RTE_ETH_FILTER_FLEXIBLE:
4931                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4932                 break;
4933         case RTE_ETH_FILTER_GENERIC:
4934                 if (filter_op != RTE_ETH_FILTER_GET)
4935                         return -EINVAL;
4936                 *(const void **)arg = &igb_flow_ops;
4937                 break;
4938         default:
4939                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4940                                                         filter_type);
4941                 break;
4942         }
4943
4944         return ret;
4945 }
4946
4947 static int
4948 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4949                          struct rte_ether_addr *mc_addr_set,
4950                          uint32_t nb_mc_addr)
4951 {
4952         struct e1000_hw *hw;
4953
4954         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4955         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4956         return 0;
4957 }
4958
4959 static uint64_t
4960 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4961 {
4962         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4963         uint64_t systime_cycles;
4964
4965         switch (hw->mac.type) {
4966         case e1000_i210:
4967         case e1000_i211:
4968                 /*
4969                  * Need to read System Time Residue Register to be able
4970                  * to read the other two registers.
4971                  */
4972                 E1000_READ_REG(hw, E1000_SYSTIMR);
4973                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4974                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4975                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4976                                 * NSEC_PER_SEC;
4977                 break;
4978         case e1000_82580:
4979         case e1000_i350:
4980         case e1000_i354:
4981                 /*
4982                  * Need to read System Time Residue Register to be able
4983                  * to read the other two registers.
4984                  */
4985                 E1000_READ_REG(hw, E1000_SYSTIMR);
4986                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4987                 /* Only the 8 LSB are valid. */
4988                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4989                                 & 0xff) << 32;
4990                 break;
4991         default:
4992                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4993                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4994                                 << 32;
4995                 break;
4996         }
4997
4998         return systime_cycles;
4999 }
5000
5001 static uint64_t
5002 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5003 {
5004         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5005         uint64_t rx_tstamp_cycles;
5006
5007         switch (hw->mac.type) {
5008         case e1000_i210:
5009         case e1000_i211:
5010                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5011                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5012                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5013                                 * NSEC_PER_SEC;
5014                 break;
5015         case e1000_82580:
5016         case e1000_i350:
5017         case e1000_i354:
5018                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5019                 /* Only the 8 LSB are valid. */
5020                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
5021                                 & 0xff) << 32;
5022                 break;
5023         default:
5024                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5025                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5026                                 << 32;
5027                 break;
5028         }
5029
5030         return rx_tstamp_cycles;
5031 }
5032
5033 static uint64_t
5034 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5035 {
5036         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5037         uint64_t tx_tstamp_cycles;
5038
5039         switch (hw->mac.type) {
5040         case e1000_i210:
5041         case e1000_i211:
5042                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5043                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5044                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5045                                 * NSEC_PER_SEC;
5046                 break;
5047         case e1000_82580:
5048         case e1000_i350:
5049         case e1000_i354:
5050                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5051                 /* Only the 8 LSB are valid. */
5052                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5053                                 & 0xff) << 32;
5054                 break;
5055         default:
5056                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5057                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5058                                 << 32;
5059                 break;
5060         }
5061
5062         return tx_tstamp_cycles;
5063 }
5064
5065 static void
5066 igb_start_timecounters(struct rte_eth_dev *dev)
5067 {
5068         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5069         struct e1000_adapter *adapter = dev->data->dev_private;
5070         uint32_t incval = 1;
5071         uint32_t shift = 0;
5072         uint64_t mask = E1000_CYCLECOUNTER_MASK;
5073
5074         switch (hw->mac.type) {
5075         case e1000_82580:
5076         case e1000_i350:
5077         case e1000_i354:
5078                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5079                 mask = (1ULL << 40) - 1;
5080                 /* fall-through */
5081         case e1000_i210:
5082         case e1000_i211:
5083                 /*
5084                  * Start incrementing the register
5085                  * used to timestamp PTP packets.
5086                  */
5087                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5088                 break;
5089         case e1000_82576:
5090                 incval = E1000_INCVALUE_82576;
5091                 shift = IGB_82576_TSYNC_SHIFT;
5092                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5093                                 E1000_INCPERIOD_82576 | incval);
5094                 break;
5095         default:
5096                 /* Not supported */
5097                 return;
5098         }
5099
5100         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5101         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5102         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5103
5104         adapter->systime_tc.cc_mask = mask;
5105         adapter->systime_tc.cc_shift = shift;
5106         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5107
5108         adapter->rx_tstamp_tc.cc_mask = mask;
5109         adapter->rx_tstamp_tc.cc_shift = shift;
5110         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5111
5112         adapter->tx_tstamp_tc.cc_mask = mask;
5113         adapter->tx_tstamp_tc.cc_shift = shift;
5114         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5115 }
5116
5117 static int
5118 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5119 {
5120         struct e1000_adapter *adapter = dev->data->dev_private;
5121
5122         adapter->systime_tc.nsec += delta;
5123         adapter->rx_tstamp_tc.nsec += delta;
5124         adapter->tx_tstamp_tc.nsec += delta;
5125
5126         return 0;
5127 }
5128
5129 static int
5130 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5131 {
5132         uint64_t ns;
5133         struct e1000_adapter *adapter = dev->data->dev_private;
5134
5135         ns = rte_timespec_to_ns(ts);
5136
5137         /* Set the timecounters to a new value. */
5138         adapter->systime_tc.nsec = ns;
5139         adapter->rx_tstamp_tc.nsec = ns;
5140         adapter->tx_tstamp_tc.nsec = ns;
5141
5142         return 0;
5143 }
5144
5145 static int
5146 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5147 {
5148         uint64_t ns, systime_cycles;
5149         struct e1000_adapter *adapter = dev->data->dev_private;
5150
5151         systime_cycles = igb_read_systime_cyclecounter(dev);
5152         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5153         *ts = rte_ns_to_timespec(ns);
5154
5155         return 0;
5156 }
5157
5158 static int
5159 igb_timesync_enable(struct rte_eth_dev *dev)
5160 {
5161         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5162         uint32_t tsync_ctl;
5163         uint32_t tsauxc;
5164
5165         /* Stop the timesync system time. */
5166         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5167         /* Reset the timesync system time value. */
5168         switch (hw->mac.type) {
5169         case e1000_82580:
5170         case e1000_i350:
5171         case e1000_i354:
5172         case e1000_i210:
5173         case e1000_i211:
5174                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5175                 /* fall-through */
5176         case e1000_82576:
5177                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5178                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5179                 break;
5180         default:
5181                 /* Not supported. */
5182                 return -ENOTSUP;
5183         }
5184
5185         /* Enable system time for it isn't on by default. */
5186         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5187         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5188         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5189
5190         igb_start_timecounters(dev);
5191
5192         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5193         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5194                         (RTE_ETHER_TYPE_1588 |
5195                          E1000_ETQF_FILTER_ENABLE |
5196                          E1000_ETQF_1588));
5197
5198         /* Enable timestamping of received PTP packets. */
5199         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5200         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5201         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5202
5203         /* Enable Timestamping of transmitted PTP packets. */
5204         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5205         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5206         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5207
5208         return 0;
5209 }
5210
5211 static int
5212 igb_timesync_disable(struct rte_eth_dev *dev)
5213 {
5214         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5215         uint32_t tsync_ctl;
5216
5217         /* Disable timestamping of transmitted PTP packets. */
5218         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5219         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5220         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5221
5222         /* Disable timestamping of received PTP packets. */
5223         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5224         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5225         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5226
5227         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5228         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5229
5230         /* Stop incrementating the System Time registers. */
5231         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5232
5233         return 0;
5234 }
5235
5236 static int
5237 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5238                                struct timespec *timestamp,
5239                                uint32_t flags __rte_unused)
5240 {
5241         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5242         struct e1000_adapter *adapter = dev->data->dev_private;
5243         uint32_t tsync_rxctl;
5244         uint64_t rx_tstamp_cycles;
5245         uint64_t ns;
5246
5247         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5248         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5249                 return -EINVAL;
5250
5251         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5252         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5253         *timestamp = rte_ns_to_timespec(ns);
5254
5255         return  0;
5256 }
5257
5258 static int
5259 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5260                                struct timespec *timestamp)
5261 {
5262         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5263         struct e1000_adapter *adapter = dev->data->dev_private;
5264         uint32_t tsync_txctl;
5265         uint64_t tx_tstamp_cycles;
5266         uint64_t ns;
5267
5268         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5269         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5270                 return -EINVAL;
5271
5272         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5273         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5274         *timestamp = rte_ns_to_timespec(ns);
5275
5276         return  0;
5277 }
5278
5279 static int
5280 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5281 {
5282         int count = 0;
5283         int g_ind = 0;
5284         const struct reg_info *reg_group;
5285
5286         while ((reg_group = igb_regs[g_ind++]))
5287                 count += igb_reg_group_count(reg_group);
5288
5289         return count;
5290 }
5291
5292 static int
5293 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5294 {
5295         int count = 0;
5296         int g_ind = 0;
5297         const struct reg_info *reg_group;
5298
5299         while ((reg_group = igbvf_regs[g_ind++]))
5300                 count += igb_reg_group_count(reg_group);
5301
5302         return count;
5303 }
5304
5305 static int
5306 eth_igb_get_regs(struct rte_eth_dev *dev,
5307         struct rte_dev_reg_info *regs)
5308 {
5309         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5310         uint32_t *data = regs->data;
5311         int g_ind = 0;
5312         int count = 0;
5313         const struct reg_info *reg_group;
5314
5315         if (data == NULL) {
5316                 regs->length = eth_igb_get_reg_length(dev);
5317                 regs->width = sizeof(uint32_t);
5318                 return 0;
5319         }
5320
5321         /* Support only full register dump */
5322         if ((regs->length == 0) ||
5323             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5324                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5325                         hw->device_id;
5326                 while ((reg_group = igb_regs[g_ind++]))
5327                         count += igb_read_regs_group(dev, &data[count],
5328                                                         reg_group);
5329                 return 0;
5330         }
5331
5332         return -ENOTSUP;
5333 }
5334
5335 static int
5336 igbvf_get_regs(struct rte_eth_dev *dev,
5337         struct rte_dev_reg_info *regs)
5338 {
5339         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5340         uint32_t *data = regs->data;
5341         int g_ind = 0;
5342         int count = 0;
5343         const struct reg_info *reg_group;
5344
5345         if (data == NULL) {
5346                 regs->length = igbvf_get_reg_length(dev);
5347                 regs->width = sizeof(uint32_t);
5348                 return 0;
5349         }
5350
5351         /* Support only full register dump */
5352         if ((regs->length == 0) ||
5353             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5354                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5355                         hw->device_id;
5356                 while ((reg_group = igbvf_regs[g_ind++]))
5357                         count += igb_read_regs_group(dev, &data[count],
5358                                                         reg_group);
5359                 return 0;
5360         }
5361
5362         return -ENOTSUP;
5363 }
5364
5365 static int
5366 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5367 {
5368         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5369
5370         /* Return unit is byte count */
5371         return hw->nvm.word_size * 2;
5372 }
5373
5374 static int
5375 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5376         struct rte_dev_eeprom_info *in_eeprom)
5377 {
5378         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5379         struct e1000_nvm_info *nvm = &hw->nvm;
5380         uint16_t *data = in_eeprom->data;
5381         int first, length;
5382
5383         first = in_eeprom->offset >> 1;
5384         length = in_eeprom->length >> 1;
5385         if ((first >= hw->nvm.word_size) ||
5386             ((first + length) >= hw->nvm.word_size))
5387                 return -EINVAL;
5388
5389         in_eeprom->magic = hw->vendor_id |
5390                 ((uint32_t)hw->device_id << 16);
5391
5392         if ((nvm->ops.read) == NULL)
5393                 return -ENOTSUP;
5394
5395         return nvm->ops.read(hw, first, length, data);
5396 }
5397
5398 static int
5399 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5400         struct rte_dev_eeprom_info *in_eeprom)
5401 {
5402         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5403         struct e1000_nvm_info *nvm = &hw->nvm;
5404         uint16_t *data = in_eeprom->data;
5405         int first, length;
5406
5407         first = in_eeprom->offset >> 1;
5408         length = in_eeprom->length >> 1;
5409         if ((first >= hw->nvm.word_size) ||
5410             ((first + length) >= hw->nvm.word_size))
5411                 return -EINVAL;
5412
5413         in_eeprom->magic = (uint32_t)hw->vendor_id |
5414                 ((uint32_t)hw->device_id << 16);
5415
5416         if ((nvm->ops.write) == NULL)
5417                 return -ENOTSUP;
5418         return nvm->ops.write(hw,  first, length, data);
5419 }
5420
5421 static int
5422 eth_igb_get_module_info(struct rte_eth_dev *dev,
5423                         struct rte_eth_dev_module_info *modinfo)
5424 {
5425         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5426
5427         uint32_t status = 0;
5428         uint16_t sff8472_rev, addr_mode;
5429         bool page_swap = false;
5430
5431         if (hw->phy.media_type == e1000_media_type_copper ||
5432             hw->phy.media_type == e1000_media_type_unknown)
5433                 return -EOPNOTSUPP;
5434
5435         /* Check whether we support SFF-8472 or not */
5436         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5437         if (status)
5438                 return -EIO;
5439
5440         /* addressing mode is not supported */
5441         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5442         if (status)
5443                 return -EIO;
5444
5445         /* addressing mode is not supported */
5446         if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5447                 PMD_DRV_LOG(ERR,
5448                             "Address change required to access page 0xA2, "
5449                             "but not supported. Please report the module "
5450                             "type to the driver maintainers.\n");
5451                 page_swap = true;
5452         }
5453
5454         if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5455                 /* We have an SFP, but it does not support SFF-8472 */
5456                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5457                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5458         } else {
5459                 /* We have an SFP which supports a revision of SFF-8472 */
5460                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5461                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5462         }
5463
5464         return 0;
5465 }
5466
5467 static int
5468 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5469                           struct rte_dev_eeprom_info *info)
5470 {
5471         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5472
5473         uint32_t status = 0;
5474         uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5475         u16 first_word, last_word;
5476         int i = 0;
5477
5478         if (info->length == 0)
5479                 return -EINVAL;
5480
5481         first_word = info->offset >> 1;
5482         last_word = (info->offset + info->length - 1) >> 1;
5483
5484         /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5485         for (i = 0; i < last_word - first_word + 1; i++) {
5486                 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5487                                                 &dataword[i]);
5488                 if (status) {
5489                         /* Error occurred while reading module */
5490                         return -EIO;
5491                 }
5492
5493                 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5494         }
5495
5496         memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5497
5498         return 0;
5499 }
5500
5501 static int
5502 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5503 {
5504         struct e1000_hw *hw =
5505                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5506         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5507         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5508         uint32_t vec = E1000_MISC_VEC_ID;
5509
5510         if (rte_intr_allow_others(intr_handle))
5511                 vec = E1000_RX_VEC_START;
5512
5513         uint32_t mask = 1 << (queue_id + vec);
5514
5515         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5516         E1000_WRITE_FLUSH(hw);
5517
5518         return 0;
5519 }
5520
5521 static int
5522 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5523 {
5524         struct e1000_hw *hw =
5525                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5526         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5527         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5528         uint32_t vec = E1000_MISC_VEC_ID;
5529
5530         if (rte_intr_allow_others(intr_handle))
5531                 vec = E1000_RX_VEC_START;
5532
5533         uint32_t mask = 1 << (queue_id + vec);
5534         uint32_t regval;
5535
5536         regval = E1000_READ_REG(hw, E1000_EIMS);
5537         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5538         E1000_WRITE_FLUSH(hw);
5539
5540         rte_intr_ack(intr_handle);
5541
5542         return 0;
5543 }
5544
5545 static void
5546 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5547                    uint8_t index, uint8_t offset)
5548 {
5549         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5550
5551         /* clear bits */
5552         val &= ~((uint32_t)0xFF << offset);
5553
5554         /* write vector and valid bit */
5555         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5556
5557         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5558 }
5559
5560 static void
5561 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5562                            uint8_t queue, uint8_t msix_vector)
5563 {
5564         uint32_t tmp = 0;
5565
5566         if (hw->mac.type == e1000_82575) {
5567                 if (direction == 0)
5568                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5569                 else if (direction == 1)
5570                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5571                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5572         } else if (hw->mac.type == e1000_82576) {
5573                 if ((direction == 0) || (direction == 1))
5574                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5575                                            ((queue & 0x8) << 1) +
5576                                            8 * direction);
5577         } else if ((hw->mac.type == e1000_82580) ||
5578                         (hw->mac.type == e1000_i350) ||
5579                         (hw->mac.type == e1000_i354) ||
5580                         (hw->mac.type == e1000_i210) ||
5581                         (hw->mac.type == e1000_i211)) {
5582                 if ((direction == 0) || (direction == 1))
5583                         eth_igb_write_ivar(hw, msix_vector,
5584                                            queue >> 1,
5585                                            ((queue & 0x1) << 4) +
5586                                            8 * direction);
5587         }
5588 }
5589
5590 /* Sets up the hardware to generate MSI-X interrupts properly
5591  * @hw
5592  *  board private structure
5593  */
5594 static void
5595 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5596 {
5597         int queue_id;
5598         uint32_t tmpval, regval, intr_mask;
5599         struct e1000_hw *hw =
5600                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5601         uint32_t vec = E1000_MISC_VEC_ID;
5602         uint32_t base = E1000_MISC_VEC_ID;
5603         uint32_t misc_shift = 0;
5604         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5605         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5606
5607         /* won't configure msix register if no mapping is done
5608          * between intr vector and event fd
5609          */
5610         if (!rte_intr_dp_is_en(intr_handle))
5611                 return;
5612
5613         if (rte_intr_allow_others(intr_handle)) {
5614                 vec = base = E1000_RX_VEC_START;
5615                 misc_shift = 1;
5616         }
5617
5618         /* set interrupt vector for other causes */
5619         if (hw->mac.type == e1000_82575) {
5620                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5621                 /* enable MSI-X PBA support */
5622                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5623
5624                 /* Auto-Mask interrupts upon ICR read */
5625                 tmpval |= E1000_CTRL_EXT_EIAME;
5626                 tmpval |= E1000_CTRL_EXT_IRCA;
5627
5628                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5629
5630                 /* enable msix_other interrupt */
5631                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5632                 regval = E1000_READ_REG(hw, E1000_EIAC);
5633                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5634                 regval = E1000_READ_REG(hw, E1000_EIAM);
5635                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5636         } else if ((hw->mac.type == e1000_82576) ||
5637                         (hw->mac.type == e1000_82580) ||
5638                         (hw->mac.type == e1000_i350) ||
5639                         (hw->mac.type == e1000_i354) ||
5640                         (hw->mac.type == e1000_i210) ||
5641                         (hw->mac.type == e1000_i211)) {
5642                 /* turn on MSI-X capability first */
5643                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5644                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5645                                         E1000_GPIE_NSICR);
5646                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5647                         misc_shift;
5648
5649                 if (dev->data->dev_conf.intr_conf.lsc != 0)
5650                         intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5651
5652                 regval = E1000_READ_REG(hw, E1000_EIAC);
5653                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5654
5655                 /* enable msix_other interrupt */
5656                 regval = E1000_READ_REG(hw, E1000_EIMS);
5657                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5658                 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5659                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5660         }
5661
5662         /* use EIAM to auto-mask when MSI-X interrupt
5663          * is asserted, this saves a register write for every interrupt
5664          */
5665         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5666                 misc_shift;
5667
5668         if (dev->data->dev_conf.intr_conf.lsc != 0)
5669                 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5670
5671         regval = E1000_READ_REG(hw, E1000_EIAM);
5672         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5673
5674         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5675                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5676                 intr_handle->intr_vec[queue_id] = vec;
5677                 if (vec < base + intr_handle->nb_efd - 1)
5678                         vec++;
5679         }
5680
5681         E1000_WRITE_FLUSH(hw);
5682 }
5683
5684 /* restore n-tuple filter */
5685 static inline void
5686 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5687 {
5688         struct e1000_filter_info *filter_info =
5689                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5690         struct e1000_5tuple_filter *p_5tuple;
5691         struct e1000_2tuple_filter *p_2tuple;
5692
5693         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5694                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5695         }
5696
5697         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5698                 igb_inject_2uple_filter(dev, p_2tuple);
5699         }
5700 }
5701
5702 /* restore SYN filter */
5703 static inline void
5704 igb_syn_filter_restore(struct rte_eth_dev *dev)
5705 {
5706         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5707         struct e1000_filter_info *filter_info =
5708                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5709         uint32_t synqf;
5710
5711         synqf = filter_info->syn_info;
5712
5713         if (synqf & E1000_SYN_FILTER_ENABLE) {
5714                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5715                 E1000_WRITE_FLUSH(hw);
5716         }
5717 }
5718
5719 /* restore ethernet type filter */
5720 static inline void
5721 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5722 {
5723         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5724         struct e1000_filter_info *filter_info =
5725                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5726         int i;
5727
5728         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5729                 if (filter_info->ethertype_mask & (1 << i)) {
5730                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5731                                 filter_info->ethertype_filters[i].etqf);
5732                         E1000_WRITE_FLUSH(hw);
5733                 }
5734         }
5735 }
5736
5737 /* restore flex byte filter */
5738 static inline void
5739 igb_flex_filter_restore(struct rte_eth_dev *dev)
5740 {
5741         struct e1000_filter_info *filter_info =
5742                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5743         struct e1000_flex_filter *flex_filter;
5744
5745         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5746                 igb_inject_flex_filter(dev, flex_filter);
5747         }
5748 }
5749
5750 /* restore rss filter */
5751 static inline void
5752 igb_rss_filter_restore(struct rte_eth_dev *dev)
5753 {
5754         struct e1000_filter_info *filter_info =
5755                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5756
5757         if (filter_info->rss_info.conf.queue_num)
5758                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5759 }
5760
5761 /* restore all types filter */
5762 static int
5763 igb_filter_restore(struct rte_eth_dev *dev)
5764 {
5765         igb_ntuple_filter_restore(dev);
5766         igb_ethertype_filter_restore(dev);
5767         igb_syn_filter_restore(dev);
5768         igb_flex_filter_restore(dev);
5769         igb_rss_filter_restore(dev);
5770
5771         return 0;
5772 }
5773
5774 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5775 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5776 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5777 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5778 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5779 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5780
5781 /* see e1000_logs.c */
5782 RTE_INIT(e1000_init_log)
5783 {
5784         e1000_igb_init_log();
5785 }