drivers/net/ena/base/ena_com.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include "ena_com.h"
   7
   8 /*****************************************************************************/
   9 /*****************************************************************************/
  10
  11 /* Timeout in micro-sec */
  12 #define ADMIN_CMD_TIMEOUT_US (3000000)
  13
  14 #define ENA_ASYNC_QUEUE_DEPTH 16
  15 #define ENA_ADMIN_QUEUE_DEPTH 32
  16
  17 #define ENA_CTRL_MAJOR          0
  18 #define ENA_CTRL_MINOR          0
  19 #define ENA_CTRL_SUB_MINOR      1
  20
  21 #define MIN_ENA_CTRL_VER \
  22         (((ENA_CTRL_MAJOR) << \
  23         (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
  24         ((ENA_CTRL_MINOR) << \
  25         (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
  26         (ENA_CTRL_SUB_MINOR))
  27
  28 #define ENA_DMA_ADDR_TO_UINT32_LOW(x)   ((u32)((u64)(x)))
  29 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x)  ((u32)(((u64)(x)) >> 32))
  30
  31 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
  32
  33 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4
  34
  35 #define ENA_REGS_ADMIN_INTR_MASK 1
  36
  37 #define ENA_POLL_MS     5
  38
  39 /*****************************************************************************/
  40 /*****************************************************************************/
  41 /*****************************************************************************/
  42
  43 enum ena_cmd_status {
  44         ENA_CMD_SUBMITTED,
  45         ENA_CMD_COMPLETED,
  46         /* Abort - canceled by the driver */
  47         ENA_CMD_ABORTED,
  48 };
  49
  50 struct ena_comp_ctx {
  51         ena_wait_event_t wait_event;
  52         struct ena_admin_acq_entry *user_cqe;
  53         u32 comp_size;
  54         enum ena_cmd_status status;
  55         /* status from the device */
  56         u8 comp_status;
  57         u8 cmd_opcode;
  58         bool occupied;
  59 };
  60
  61 struct ena_com_stats_ctx {
  62         struct ena_admin_aq_get_stats_cmd get_cmd;
  63         struct ena_admin_acq_get_stats_resp get_resp;
  64 };
  65
  66 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
  67                                        struct ena_common_mem_addr *ena_addr,
  68                                        dma_addr_t addr)
  69 {
  70         if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
  71                 ena_trc_err("dma address has more bits that the device supports\n");
  72                 return ENA_COM_INVAL;
  73         }
  74
  75         ena_addr->mem_addr_low = lower_32_bits(addr);
  76         ena_addr->mem_addr_high = upper_32_bits(addr);
  77
  78         return 0;
  79 }
  80
  81 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)
  82 {
  83         struct ena_com_admin_sq *sq = &queue->sq;
  84         u16 size = ADMIN_SQ_SIZE(queue->q_depth);
  85
  86         ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, sq->entries, sq->dma_addr,
  87                                sq->mem_handle);
  88
  89         if (!sq->entries) {
  90                 ena_trc_err("memory allocation failed\n");
  91                 return ENA_COM_NO_MEM;
  92         }
  93
  94         sq->head = 0;
  95         sq->tail = 0;
  96         sq->phase = 1;
  97
  98         sq->db_addr = NULL;
  99
 100         return 0;
 101 }
 102
 103 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)
 104 {
 105         struct ena_com_admin_cq *cq = &queue->cq;
 106         u16 size = ADMIN_CQ_SIZE(queue->q_depth);
 107
 108         ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, cq->entries, cq->dma_addr,
 109                                cq->mem_handle);
 110
 111         if (!cq->entries)  {
 112                 ena_trc_err("memory allocation failed\n");
 113                 return ENA_COM_NO_MEM;
 114         }
 115
 116         cq->head = 0;
 117         cq->phase = 1;
 118
 119         return 0;
 120 }
 121
 122 static int ena_com_admin_init_aenq(struct ena_com_dev *dev,
 123                                    struct ena_aenq_handlers *aenq_handlers)
 124 {
 125         struct ena_com_aenq *aenq = &dev->aenq;
 126         u32 addr_low, addr_high, aenq_caps;
 127         u16 size;
 128
 129         dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
 130         size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
 131         ENA_MEM_ALLOC_COHERENT(dev->dmadev, size,
 132                         aenq->entries,
 133                         aenq->dma_addr,
 134                         aenq->mem_handle);
 135
 136         if (!aenq->entries) {
 137                 ena_trc_err("memory allocation failed\n");
 138                 return ENA_COM_NO_MEM;
 139         }
 140
 141         aenq->head = aenq->q_depth;
 142         aenq->phase = 1;
 143
 144         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
 145         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
 146
 147         ENA_REG_WRITE32(dev->bus, addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
 148         ENA_REG_WRITE32(dev->bus, addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
 149
 150         aenq_caps = 0;
 151         aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
 152         aenq_caps |= (sizeof(struct ena_admin_aenq_entry) <<
 153                 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
 154                 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
 155         ENA_REG_WRITE32(dev->bus, aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
 156
 157         if (unlikely(!aenq_handlers)) {
 158                 ena_trc_err("aenq handlers pointer is NULL\n");
 159                 return ENA_COM_INVAL;
 160         }
 161
 162         aenq->aenq_handlers = aenq_handlers;
 163
 164         return 0;
 165 }
 166
 167 static void comp_ctxt_release(struct ena_com_admin_queue *queue,
 168                                      struct ena_comp_ctx *comp_ctx)
 169 {
 170         comp_ctx->occupied = false;
 171         ATOMIC32_DEC(&queue->outstanding_cmds);
 172 }
 173
 174 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
 175                                           u16 command_id, bool capture)
 176 {
 177         if (unlikely(command_id >= queue->q_depth)) {
 178                 ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
 179                             command_id, queue->q_depth);
 180                 return NULL;
 181         }
 182
 183         if (unlikely(!queue->comp_ctx)) {
 184                 ena_trc_err("Completion context is NULL\n");
 185                 return NULL;
 186         }
 187
 188         if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
 189                 ena_trc_err("Completion context is occupied\n");
 190                 return NULL;
 191         }
 192
 193         if (capture) {
 194                 ATOMIC32_INC(&queue->outstanding_cmds);
 195                 queue->comp_ctx[command_id].occupied = true;
 196         }
 197
 198         return &queue->comp_ctx[command_id];
 199 }
 200
 201 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 202                                                        struct ena_admin_aq_entry *cmd,
 203                                                        size_t cmd_size_in_bytes,
 204                                                        struct ena_admin_acq_entry *comp,
 205                                                        size_t comp_size_in_bytes)
 206 {
 207         struct ena_comp_ctx *comp_ctx;
 208         u16 tail_masked, cmd_id;
 209         u16 queue_size_mask;
 210         u16 cnt;
 211
 212         queue_size_mask = admin_queue->q_depth - 1;
 213
 214         tail_masked = admin_queue->sq.tail & queue_size_mask;
 215
 216         /* In case of queue FULL */
 217         cnt = (u16)ATOMIC32_READ(&admin_queue->outstanding_cmds);
 218         if (cnt >= admin_queue->q_depth) {
 219                 ena_trc_dbg("admin queue is full.\n");
 220                 admin_queue->stats.out_of_space++;
 221                 return ERR_PTR(ENA_COM_NO_SPACE);
 222         }
 223
 224         cmd_id = admin_queue->curr_cmd_id;
 225
 226         cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
 227                 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
 228
 229         cmd->aq_common_descriptor.command_id |= cmd_id &
 230                 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
 231
 232         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
 233         if (unlikely(!comp_ctx))
 234                 return ERR_PTR(ENA_COM_INVAL);
 235
 236         comp_ctx->status = ENA_CMD_SUBMITTED;
 237         comp_ctx->comp_size = (u32)comp_size_in_bytes;
 238         comp_ctx->user_cqe = comp;
 239         comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
 240
 241         ENA_WAIT_EVENT_CLEAR(comp_ctx->wait_event);
 242
 243         memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
 244
 245         admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
 246                 queue_size_mask;
 247
 248         admin_queue->sq.tail++;
 249         admin_queue->stats.submitted_cmd++;
 250
 251         if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
 252                 admin_queue->sq.phase = !admin_queue->sq.phase;
 253
 254         ENA_DB_SYNC(&admin_queue->sq.mem_handle);
 255         ENA_REG_WRITE32(admin_queue->bus, admin_queue->sq.tail,
 256                         admin_queue->sq.db_addr);
 257
 258         return comp_ctx;
 259 }
 260
 261 static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
 262 {
 263         size_t size = queue->q_depth * sizeof(struct ena_comp_ctx);
 264         struct ena_comp_ctx *comp_ctx;
 265         u16 i;
 266
 267         queue->comp_ctx = ENA_MEM_ALLOC(queue->q_dmadev, size);
 268         if (unlikely(!queue->comp_ctx)) {
 269                 ena_trc_err("memory allocation failed\n");
 270                 return ENA_COM_NO_MEM;
 271         }
 272
 273         for (i = 0; i < queue->q_depth; i++) {
 274                 comp_ctx = get_comp_ctxt(queue, i, false);
 275                 if (comp_ctx)
 276                         ENA_WAIT_EVENT_INIT(comp_ctx->wait_event);
 277         }
 278
 279         return 0;
 280 }
 281
 282 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 283                                                      struct ena_admin_aq_entry *cmd,
 284                                                      size_t cmd_size_in_bytes,
 285                                                      struct ena_admin_acq_entry *comp,
 286                                                      size_t comp_size_in_bytes)
 287 {
 288         unsigned long flags = 0;
 289         struct ena_comp_ctx *comp_ctx;
 290
 291         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 292         if (unlikely(!admin_queue->running_state)) {
 293                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 294                 return ERR_PTR(ENA_COM_NO_DEVICE);
 295         }
 296         comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
 297                                               cmd_size_in_bytes,
 298                                               comp,
 299                                               comp_size_in_bytes);
 300         if (IS_ERR(comp_ctx))
 301                 admin_queue->running_state = false;
 302         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 303
 304         return comp_ctx;
 305 }
 306
 307 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
 308                               struct ena_com_create_io_ctx *ctx,
 309                               struct ena_com_io_sq *io_sq)
 310 {
 311         size_t size;
 312         int dev_node = 0;
 313
 314         memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
 315
 316         io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits;
 317         io_sq->desc_entry_size =
 318                 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 319                 sizeof(struct ena_eth_io_tx_desc) :
 320                 sizeof(struct ena_eth_io_rx_desc);
 321
 322         size = io_sq->desc_entry_size * io_sq->q_depth;
 323         io_sq->bus = ena_dev->bus;
 324
 325         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
 326                 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
 327                                             size,
 328                                             io_sq->desc_addr.virt_addr,
 329                                             io_sq->desc_addr.phys_addr,
 330                                             io_sq->desc_addr.mem_handle,
 331                                             ctx->numa_node,
 332                                             dev_node);
 333                 if (!io_sq->desc_addr.virt_addr) {
 334                         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
 335                                                size,
 336                                                io_sq->desc_addr.virt_addr,
 337                                                io_sq->desc_addr.phys_addr,
 338                                                io_sq->desc_addr.mem_handle);
 339                 }
 340
 341                 if (!io_sq->desc_addr.virt_addr) {
 342                         ena_trc_err("memory allocation failed\n");
 343                         return ENA_COM_NO_MEM;
 344                 }
 345         }
 346
 347         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 348                 /* Allocate bounce buffers */
 349                 io_sq->bounce_buf_ctrl.buffer_size =
 350                         ena_dev->llq_info.desc_list_entry_size;
 351                 io_sq->bounce_buf_ctrl.buffers_num =
 352                         ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
 353                 io_sq->bounce_buf_ctrl.next_to_use = 0;
 354
 355                 size = io_sq->bounce_buf_ctrl.buffer_size *
 356                         io_sq->bounce_buf_ctrl.buffers_num;
 357
 358                 ENA_MEM_ALLOC_NODE(ena_dev->dmadev,
 359                                    size,
 360                                    io_sq->bounce_buf_ctrl.base_buffer,
 361                                    ctx->numa_node,
 362                                    dev_node);
 363                 if (!io_sq->bounce_buf_ctrl.base_buffer)
 364                         io_sq->bounce_buf_ctrl.base_buffer = ENA_MEM_ALLOC(ena_dev->dmadev, size);
 365
 366                 if (!io_sq->bounce_buf_ctrl.base_buffer) {
 367                         ena_trc_err("bounce buffer memory allocation failed\n");
 368                         return ENA_COM_NO_MEM;
 369                 }
 370
 371                 memcpy(&io_sq->llq_info, &ena_dev->llq_info,
 372                        sizeof(io_sq->llq_info));
 373
 374                 /* Initiate the first bounce buffer */
 375                 io_sq->llq_buf_ctrl.curr_bounce_buf =
 376                         ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
 377                 memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
 378                        0x0, io_sq->llq_info.desc_list_entry_size);
 379                 io_sq->llq_buf_ctrl.descs_left_in_line =
 380                         io_sq->llq_info.descs_num_before_header;
 381
 382                 if (io_sq->llq_info.max_entries_in_tx_burst > 0)
 383                         io_sq->entries_in_tx_burst_left =
 384                                 io_sq->llq_info.max_entries_in_tx_burst;
 385         }
 386
 387         io_sq->tail = 0;
 388         io_sq->next_to_comp = 0;
 389         io_sq->phase = 1;
 390
 391         return 0;
 392 }
 393
 394 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
 395                               struct ena_com_create_io_ctx *ctx,
 396                               struct ena_com_io_cq *io_cq)
 397 {
 398         size_t size;
 399         int prev_node = 0;
 400
 401         memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
 402
 403         /* Use the basic completion descriptor for Rx */
 404         io_cq->cdesc_entry_size_in_bytes =
 405                 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 406                 sizeof(struct ena_eth_io_tx_cdesc) :
 407                 sizeof(struct ena_eth_io_rx_cdesc_base);
 408
 409         size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 410         io_cq->bus = ena_dev->bus;
 411
 412         ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
 413                         size,
 414                         io_cq->cdesc_addr.virt_addr,
 415                         io_cq->cdesc_addr.phys_addr,
 416                         io_cq->cdesc_addr.mem_handle,
 417                         ctx->numa_node,
 418                         prev_node);
 419         if (!io_cq->cdesc_addr.virt_addr) {
 420                 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
 421                                        size,
 422                                        io_cq->cdesc_addr.virt_addr,
 423                                        io_cq->cdesc_addr.phys_addr,
 424                                        io_cq->cdesc_addr.mem_handle);
 425         }
 426
 427         if (!io_cq->cdesc_addr.virt_addr) {
 428                 ena_trc_err("memory allocation failed\n");
 429                 return ENA_COM_NO_MEM;
 430         }
 431
 432         io_cq->phase = 1;
 433         io_cq->head = 0;
 434
 435         return 0;
 436 }
 437
 438 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
 439                                                    struct ena_admin_acq_entry *cqe)
 440 {
 441         struct ena_comp_ctx *comp_ctx;
 442         u16 cmd_id;
 443
 444         cmd_id = cqe->acq_common_descriptor.command &
 445                 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
 446
 447         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
 448         if (unlikely(!comp_ctx)) {
 449                 ena_trc_err("comp_ctx is NULL. Changing the admin queue running state\n");
 450                 admin_queue->running_state = false;
 451                 return;
 452         }
 453
 454         comp_ctx->status = ENA_CMD_COMPLETED;
 455         comp_ctx->comp_status = cqe->acq_common_descriptor.status;
 456
 457         if (comp_ctx->user_cqe)
 458                 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
 459
 460         if (!admin_queue->polling)
 461                 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
 462 }
 463
 464 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
 465 {
 466         struct ena_admin_acq_entry *cqe = NULL;
 467         u16 comp_num = 0;
 468         u16 head_masked;
 469         u8 phase;
 470
 471         head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
 472         phase = admin_queue->cq.phase;
 473
 474         cqe = &admin_queue->cq.entries[head_masked];
 475
 476         /* Go over all the completions */
 477         while ((READ_ONCE8(cqe->acq_common_descriptor.flags) &
 478                         ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
 479                 /* Do not read the rest of the completion entry before the
 480                  * phase bit was validated
 481                  */
 482                 dma_rmb();
 483                 ena_com_handle_single_admin_completion(admin_queue, cqe);
 484
 485                 head_masked++;
 486                 comp_num++;
 487                 if (unlikely(head_masked == admin_queue->q_depth)) {
 488                         head_masked = 0;
 489                         phase = !phase;
 490                 }
 491
 492                 cqe = &admin_queue->cq.entries[head_masked];
 493         }
 494
 495         admin_queue->cq.head += comp_num;
 496         admin_queue->cq.phase = phase;
 497         admin_queue->sq.head += comp_num;
 498         admin_queue->stats.completed_cmd += comp_num;
 499 }
 500
 501 static int ena_com_comp_status_to_errno(u8 comp_status)
 502 {
 503         if (unlikely(comp_status != 0))
 504                 ena_trc_err("admin command failed[%u]\n", comp_status);
 505
 506         switch (comp_status) {
 507         case ENA_ADMIN_SUCCESS:
 508                 return ENA_COM_OK;
 509         case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
 510                 return ENA_COM_NO_MEM;
 511         case ENA_ADMIN_UNSUPPORTED_OPCODE:
 512                 return ENA_COM_UNSUPPORTED;
 513         case ENA_ADMIN_BAD_OPCODE:
 514         case ENA_ADMIN_MALFORMED_REQUEST:
 515         case ENA_ADMIN_ILLEGAL_PARAMETER:
 516         case ENA_ADMIN_UNKNOWN_ERROR:
 517                 return ENA_COM_INVAL;
 518         }
 519
 520         return ENA_COM_INVAL;
 521 }
 522
 523 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
 524                                                      struct ena_com_admin_queue *admin_queue)
 525 {
 526         unsigned long flags = 0;
 527         ena_time_t timeout;
 528         int ret;
 529
 530         timeout = ENA_GET_SYSTEM_TIMEOUT(admin_queue->completion_timeout);
 531
 532         while (1) {
 533                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 534                 ena_com_handle_admin_completion(admin_queue);
 535                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 536
 537                 if (comp_ctx->status != ENA_CMD_SUBMITTED)
 538                         break;
 539
 540                 if (ENA_TIME_EXPIRE(timeout)) {
 541                         ena_trc_err("Wait for completion (polling) timeout\n");
 542                         /* ENA didn't have any completion */
 543                         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 544                         admin_queue->stats.no_completion++;
 545                         admin_queue->running_state = false;
 546                         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 547
 548                         ret = ENA_COM_TIMER_EXPIRED;
 549                         goto err;
 550                 }
 551
 552                 ENA_MSLEEP(ENA_POLL_MS);
 553         }
 554
 555         if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
 556                 ena_trc_err("Command was aborted\n");
 557                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 558                 admin_queue->stats.aborted_cmd++;
 559                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 560                 ret = ENA_COM_NO_DEVICE;
 561                 goto err;
 562         }
 563
 564         ENA_WARN(comp_ctx->status != ENA_CMD_COMPLETED,
 565                  "Invalid comp status %d\n", comp_ctx->status);
 566
 567         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 568 err:
 569         comp_ctxt_release(admin_queue, comp_ctx);
 570         return ret;
 571 }
 572
 573 /**
 574  * Set the LLQ configurations of the firmware
 575  *
 576  * The driver provides only the enabled feature values to the device,
 577  * which in turn, checks if they are supported.
 578  */
 579 static int ena_com_set_llq(struct ena_com_dev *ena_dev)
 580 {
 581         struct ena_com_admin_queue *admin_queue;
 582         struct ena_admin_set_feat_cmd cmd;
 583         struct ena_admin_set_feat_resp resp;
 584         struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
 585         int ret;
 586
 587         memset(&cmd, 0x0, sizeof(cmd));
 588         admin_queue = &ena_dev->admin_queue;
 589
 590         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
 591         cmd.feat_common.feature_id = ENA_ADMIN_LLQ;
 592
 593         cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl;
 594         cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl;
 595         cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header;
 596         cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl;
 597
 598         ret = ena_com_execute_admin_command(admin_queue,
 599                                             (struct ena_admin_aq_entry *)&cmd,
 600                                             sizeof(cmd),
 601                                             (struct ena_admin_acq_entry *)&resp,
 602                                             sizeof(resp));
 603
 604         if (unlikely(ret))
 605                 ena_trc_err("Failed to set LLQ configurations: %d\n", ret);
 606
 607         return ret;
 608 }
 609
 610 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
 611                                    struct ena_admin_feature_llq_desc *llq_features,
 612                                    struct ena_llq_configurations *llq_default_cfg)
 613 {
 614         struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
 615         u16 supported_feat;
 616         int rc;
 617
 618         memset(llq_info, 0, sizeof(*llq_info));
 619
 620         supported_feat = llq_features->header_location_ctrl_supported;
 621
 622         if (likely(supported_feat & llq_default_cfg->llq_header_location)) {
 623                 llq_info->header_location_ctrl =
 624                         llq_default_cfg->llq_header_location;
 625         } else {
 626                 ena_trc_err("Invalid header location control, supported: 0x%x\n",
 627                             supported_feat);
 628                 return -EINVAL;
 629         }
 630
 631         if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) {
 632                 supported_feat = llq_features->descriptors_stride_ctrl_supported;
 633                 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) {
 634                         llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl;
 635                 } else  {
 636                         if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) {
 637                                 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
 638                         } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) {
 639                                 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY;
 640                         } else {
 641                                 ena_trc_err("Invalid desc_stride_ctrl, supported: 0x%x\n",
 642                                             supported_feat);
 643                                 return -EINVAL;
 644                         }
 645
 646                         ena_trc_err("Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 647                                     llq_default_cfg->llq_stride_ctrl,
 648                                     supported_feat,
 649                                     llq_info->desc_stride_ctrl);
 650                 }
 651         } else {
 652                 llq_info->desc_stride_ctrl = 0;
 653         }
 654
 655         supported_feat = llq_features->entry_size_ctrl_supported;
 656         if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) {
 657                 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size;
 658                 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value;
 659         } else {
 660                 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) {
 661                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
 662                         llq_info->desc_list_entry_size = 128;
 663                 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) {
 664                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B;
 665                         llq_info->desc_list_entry_size = 192;
 666                 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) {
 667                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B;
 668                         llq_info->desc_list_entry_size = 256;
 669                 } else {
 670                         ena_trc_err("Invalid entry_size_ctrl, supported: 0x%x\n", supported_feat);
 671                         return -EINVAL;
 672                 }
 673
 674                 ena_trc_err("Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 675                             llq_default_cfg->llq_ring_entry_size,
 676                             supported_feat,
 677                             llq_info->desc_list_entry_size);
 678         }
 679         if (unlikely(llq_info->desc_list_entry_size & 0x7)) {
 680                 /* The desc list entry size should be whole multiply of 8
 681                  * This requirement comes from __iowrite64_copy()
 682                  */
 683                 ena_trc_err("illegal entry size %d\n",
 684                             llq_info->desc_list_entry_size);
 685                 return -EINVAL;
 686         }
 687
 688         if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)
 689                 llq_info->descs_per_entry = llq_info->desc_list_entry_size /
 690                         sizeof(struct ena_eth_io_tx_desc);
 691         else
 692                 llq_info->descs_per_entry = 1;
 693
 694         supported_feat = llq_features->desc_num_before_header_supported;
 695         if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) {
 696                 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header;
 697         } else {
 698                 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) {
 699                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
 700                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) {
 701                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1;
 702                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) {
 703                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4;
 704                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) {
 705                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8;
 706                 } else {
 707                         ena_trc_err("Invalid descs_num_before_header, supported: 0x%x\n",
 708                                     supported_feat);
 709                         return -EINVAL;
 710                 }
 711
 712                 ena_trc_err("Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 713                             llq_default_cfg->llq_num_decs_before_header,
 714                             supported_feat,
 715                             llq_info->descs_num_before_header);
 716         }
 717
 718         llq_info->max_entries_in_tx_burst =
 719                 (u16)(llq_features->max_tx_burst_size / llq_default_cfg->llq_ring_entry_size_value);
 720
 721         rc = ena_com_set_llq(ena_dev);
 722         if (rc)
 723                 ena_trc_err("Cannot set LLQ configuration: %d\n", rc);
 724
 725         return rc;
 726 }
 727
 728 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
 729                                                         struct ena_com_admin_queue *admin_queue)
 730 {
 731         unsigned long flags = 0;
 732         int ret;
 733
 734         ENA_WAIT_EVENT_WAIT(comp_ctx->wait_event,
 735                             admin_queue->completion_timeout);
 736
 737         /* In case the command wasn't completed find out the root cause.
 738          * There might be 2 kinds of errors
 739          * 1) No completion (timeout reached)
 740          * 2) There is completion but the device didn't get any msi-x interrupt.
 741          */
 742         if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
 743                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 744                 ena_com_handle_admin_completion(admin_queue);
 745                 admin_queue->stats.no_completion++;
 746                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 747
 748                 if (comp_ctx->status == ENA_CMD_COMPLETED) {
 749                         ena_trc_err("The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n",
 750                                     comp_ctx->cmd_opcode, admin_queue->auto_polling ? "ON" : "OFF");
 751                         /* Check if fallback to polling is enabled */
 752                         if (admin_queue->auto_polling)
 753                                 admin_queue->polling = true;
 754                 } else {
 755                         ena_trc_err("The ena device didn't send a completion for the admin cmd %d status %d\n",
 756                                     comp_ctx->cmd_opcode, comp_ctx->status);
 757                 }
 758                 /* Check if shifted to polling mode.
 759                  * This will happen if there is a completion without an interrupt
 760                  * and autopolling mode is enabled. Continuing normal execution in such case
 761                  */
 762                 if (!admin_queue->polling) {
 763                         admin_queue->running_state = false;
 764                         ret = ENA_COM_TIMER_EXPIRED;
 765                         goto err;
 766                 }
 767         }
 768
 769         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 770 err:
 771         comp_ctxt_release(admin_queue, comp_ctx);
 772         return ret;
 773 }
 774
 775 /* This method read the hardware device register through posting writes
 776  * and waiting for response
 777  * On timeout the function will return ENA_MMIO_READ_TIMEOUT
 778  */
 779 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
 780 {
 781         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
 782         volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
 783                 mmio_read->read_resp;
 784         u32 mmio_read_reg, ret, i;
 785         unsigned long flags = 0;
 786         u32 timeout = mmio_read->reg_read_to;
 787
 788         ENA_MIGHT_SLEEP();
 789
 790         if (timeout == 0)
 791                 timeout = ENA_REG_READ_TIMEOUT;
 792
 793         /* If readless is disabled, perform regular read */
 794         if (!mmio_read->readless_supported)
 795                 return ENA_REG_READ32(ena_dev->bus, ena_dev->reg_bar + offset);
 796
 797         ENA_SPINLOCK_LOCK(mmio_read->lock, flags);
 798         mmio_read->seq_num++;
 799
 800         read_resp->req_id = mmio_read->seq_num + 0xDEAD;
 801         mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
 802                         ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
 803         mmio_read_reg |= mmio_read->seq_num &
 804                         ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
 805
 806         ENA_REG_WRITE32(ena_dev->bus, mmio_read_reg,
 807                         ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
 808
 809         for (i = 0; i < timeout; i++) {
 810                 if (READ_ONCE16(read_resp->req_id) == mmio_read->seq_num)
 811                         break;
 812
 813                 ENA_UDELAY(1);
 814         }
 815
 816         if (unlikely(i == timeout)) {
 817                 ena_trc_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n",
 818                             mmio_read->seq_num,
 819                             offset,
 820                             read_resp->req_id,
 821                             read_resp->reg_off);
 822                 ret = ENA_MMIO_READ_TIMEOUT;
 823                 goto err;
 824         }
 825
 826         if (read_resp->reg_off != offset) {
 827                 ena_trc_err("Read failure: wrong offset provided\n");
 828                 ret = ENA_MMIO_READ_TIMEOUT;
 829         } else {
 830                 ret = read_resp->reg_val;
 831         }
 832 err:
 833         ENA_SPINLOCK_UNLOCK(mmio_read->lock, flags);
 834
 835         return ret;
 836 }
 837
 838 /* There are two types to wait for completion.
 839  * Polling mode - wait until the completion is available.
 840  * Async mode - wait on wait queue until the completion is ready
 841  * (or the timeout expired).
 842  * It is expected that the IRQ called ena_com_handle_admin_completion
 843  * to mark the completions.
 844  */
 845 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
 846                                              struct ena_com_admin_queue *admin_queue)
 847 {
 848         if (admin_queue->polling)
 849                 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
 850                                                                  admin_queue);
 851
 852         return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
 853                                                             admin_queue);
 854 }
 855
 856 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
 857                                  struct ena_com_io_sq *io_sq)
 858 {
 859         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
 860         struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
 861         struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
 862         u8 direction;
 863         int ret;
 864
 865         memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
 866
 867         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
 868                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
 869         else
 870                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
 871
 872         destroy_cmd.sq.sq_identity |= (direction <<
 873                 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
 874                 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
 875
 876         destroy_cmd.sq.sq_idx = io_sq->idx;
 877         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
 878
 879         ret = ena_com_execute_admin_command(admin_queue,
 880                                             (struct ena_admin_aq_entry *)&destroy_cmd,
 881                                             sizeof(destroy_cmd),
 882                                             (struct ena_admin_acq_entry *)&destroy_resp,
 883                                             sizeof(destroy_resp));
 884
 885         if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
 886                 ena_trc_err("failed to destroy io sq error: %d\n", ret);
 887
 888         return ret;
 889 }
 890
 891 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
 892                                   struct ena_com_io_sq *io_sq,
 893                                   struct ena_com_io_cq *io_cq)
 894 {
 895         size_t size;
 896
 897         if (io_cq->cdesc_addr.virt_addr) {
 898                 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 899
 900                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
 901                                       size,
 902                                       io_cq->cdesc_addr.virt_addr,
 903                                       io_cq->cdesc_addr.phys_addr,
 904                                       io_cq->cdesc_addr.mem_handle);
 905
 906                 io_cq->cdesc_addr.virt_addr = NULL;
 907         }
 908
 909         if (io_sq->desc_addr.virt_addr) {
 910                 size = io_sq->desc_entry_size * io_sq->q_depth;
 911
 912                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
 913                                       size,
 914                                       io_sq->desc_addr.virt_addr,
 915                                       io_sq->desc_addr.phys_addr,
 916                                       io_sq->desc_addr.mem_handle);
 917
 918                 io_sq->desc_addr.virt_addr = NULL;
 919         }
 920
 921         if (io_sq->bounce_buf_ctrl.base_buffer) {
 922                 ENA_MEM_FREE(ena_dev->dmadev,
 923                              io_sq->bounce_buf_ctrl.base_buffer,
 924                              (io_sq->llq_info.desc_list_entry_size * ENA_COM_BOUNCE_BUFFER_CNTRL_CNT));
 925                 io_sq->bounce_buf_ctrl.base_buffer = NULL;
 926         }
 927 }
 928
 929 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
 930                                 u16 exp_state)
 931 {
 932         u32 val, i;
 933
 934         /* Convert timeout from resolution of 100ms to ENA_POLL_MS */
 935         timeout = (timeout * 100) / ENA_POLL_MS;
 936
 937         for (i = 0; i < timeout; i++) {
 938                 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
 939
 940                 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
 941                         ena_trc_err("Reg read timeout occurred\n");
 942                         return ENA_COM_TIMER_EXPIRED;
 943                 }
 944
 945                 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
 946                         exp_state)
 947                         return 0;
 948
 949                 ENA_MSLEEP(ENA_POLL_MS);
 950         }
 951
 952         return ENA_COM_TIMER_EXPIRED;
 953 }
 954
 955 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
 956                                                enum ena_admin_aq_feature_id feature_id)
 957 {
 958         u32 feature_mask = 1 << feature_id;
 959
 960         /* Device attributes is always supported */
 961         if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
 962             !(ena_dev->supported_features & feature_mask))
 963                 return false;
 964
 965         return true;
 966 }
 967
 968 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
 969                                   struct ena_admin_get_feat_resp *get_resp,
 970                                   enum ena_admin_aq_feature_id feature_id,
 971                                   dma_addr_t control_buf_dma_addr,
 972                                   u32 control_buff_size,
 973                                   u8 feature_ver)
 974 {
 975         struct ena_com_admin_queue *admin_queue;
 976         struct ena_admin_get_feat_cmd get_cmd;
 977         int ret;
 978
 979         if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
 980                 ena_trc_dbg("Feature %d isn't supported\n", feature_id);
 981                 return ENA_COM_UNSUPPORTED;
 982         }
 983
 984         memset(&get_cmd, 0x0, sizeof(get_cmd));
 985         admin_queue = &ena_dev->admin_queue;
 986
 987         get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
 988
 989         if (control_buff_size)
 990                 get_cmd.aq_common_descriptor.flags =
 991                         ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
 992         else
 993                 get_cmd.aq_common_descriptor.flags = 0;
 994
 995         ret = ena_com_mem_addr_set(ena_dev,
 996                                    &get_cmd.control_buffer.address,
 997                                    control_buf_dma_addr);
 998         if (unlikely(ret)) {
 999                 ena_trc_err("memory address set failed\n");
1000                 return ret;
1001         }
1002
1003         get_cmd.control_buffer.length = control_buff_size;
1004         get_cmd.feat_common.feature_version = feature_ver;
1005         get_cmd.feat_common.feature_id = feature_id;
1006
1007         ret = ena_com_execute_admin_command(admin_queue,
1008                                             (struct ena_admin_aq_entry *)
1009                                             &get_cmd,
1010                                             sizeof(get_cmd),
1011                                             (struct ena_admin_acq_entry *)
1012                                             get_resp,
1013                                             sizeof(*get_resp));
1014
1015         if (unlikely(ret))
1016                 ena_trc_err("Failed to submit get_feature command %d error: %d\n",
1017                             feature_id, ret);
1018
1019         return ret;
1020 }
1021
1022 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
1023                                struct ena_admin_get_feat_resp *get_resp,
1024                                enum ena_admin_aq_feature_id feature_id,
1025                                u8 feature_ver)
1026 {
1027         return ena_com_get_feature_ex(ena_dev,
1028                                       get_resp,
1029                                       feature_id,
1030                                       0,
1031                                       0,
1032                                       feature_ver);
1033 }
1034
1035 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev)
1036 {
1037         struct ena_admin_feature_rss_flow_hash_control *hash_key =
1038                 (ena_dev->rss).hash_key;
1039
1040         ENA_RSS_FILL_KEY(&hash_key->key, sizeof(hash_key->key));
1041         /* The key is stored in the device in uint32_t array
1042          * as well as the API requires the key to be passed in this
1043          * format. Thus the size of our array should be divided by 4
1044          */
1045         hash_key->keys_num = sizeof(hash_key->key) / sizeof(uint32_t);
1046 }
1047
1048 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
1049 {
1050         struct ena_rss *rss = &ena_dev->rss;
1051
1052         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1053                                sizeof(*rss->hash_key),
1054                                rss->hash_key,
1055                                rss->hash_key_dma_addr,
1056                                rss->hash_key_mem_handle);
1057
1058         if (unlikely(!rss->hash_key))
1059                 return ENA_COM_NO_MEM;
1060
1061         return 0;
1062 }
1063
1064 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
1065 {
1066         struct ena_rss *rss = &ena_dev->rss;
1067
1068         if (rss->hash_key)
1069                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1070                                       sizeof(*rss->hash_key),
1071                                       rss->hash_key,
1072                                       rss->hash_key_dma_addr,
1073                                       rss->hash_key_mem_handle);
1074         rss->hash_key = NULL;
1075 }
1076
1077 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
1078 {
1079         struct ena_rss *rss = &ena_dev->rss;
1080
1081         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1082                                sizeof(*rss->hash_ctrl),
1083                                rss->hash_ctrl,
1084                                rss->hash_ctrl_dma_addr,
1085                                rss->hash_ctrl_mem_handle);
1086
1087         if (unlikely(!rss->hash_ctrl))
1088                 return ENA_COM_NO_MEM;
1089
1090         return 0;
1091 }
1092
1093 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
1094 {
1095         struct ena_rss *rss = &ena_dev->rss;
1096
1097         if (rss->hash_ctrl)
1098                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1099                                       sizeof(*rss->hash_ctrl),
1100                                       rss->hash_ctrl,
1101                                       rss->hash_ctrl_dma_addr,
1102                                       rss->hash_ctrl_mem_handle);
1103         rss->hash_ctrl = NULL;
1104 }
1105
1106 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
1107                                            u16 log_size)
1108 {
1109         struct ena_rss *rss = &ena_dev->rss;
1110         struct ena_admin_get_feat_resp get_resp;
1111         size_t tbl_size;
1112         int ret;
1113
1114         ret = ena_com_get_feature(ena_dev, &get_resp,
1115                                   ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
1116         if (unlikely(ret))
1117                 return ret;
1118
1119         if ((get_resp.u.ind_table.min_size > log_size) ||
1120             (get_resp.u.ind_table.max_size < log_size)) {
1121                 ena_trc_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
1122                             1 << log_size,
1123                             1 << get_resp.u.ind_table.min_size,
1124                             1 << get_resp.u.ind_table.max_size);
1125                 return ENA_COM_INVAL;
1126         }
1127
1128         tbl_size = (1ULL << log_size) *
1129                 sizeof(struct ena_admin_rss_ind_table_entry);
1130
1131         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1132                              tbl_size,
1133                              rss->rss_ind_tbl,
1134                              rss->rss_ind_tbl_dma_addr,
1135                              rss->rss_ind_tbl_mem_handle);
1136         if (unlikely(!rss->rss_ind_tbl))
1137                 goto mem_err1;
1138
1139         tbl_size = (1ULL << log_size) * sizeof(u16);
1140         rss->host_rss_ind_tbl =
1141                 ENA_MEM_ALLOC(ena_dev->dmadev, tbl_size);
1142         if (unlikely(!rss->host_rss_ind_tbl))
1143                 goto mem_err2;
1144
1145         rss->tbl_log_size = log_size;
1146
1147         return 0;
1148
1149 mem_err2:
1150         tbl_size = (1ULL << log_size) *
1151                 sizeof(struct ena_admin_rss_ind_table_entry);
1152
1153         ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1154                               tbl_size,
1155                               rss->rss_ind_tbl,
1156                               rss->rss_ind_tbl_dma_addr,
1157                               rss->rss_ind_tbl_mem_handle);
1158         rss->rss_ind_tbl = NULL;
1159 mem_err1:
1160         rss->tbl_log_size = 0;
1161         return ENA_COM_NO_MEM;
1162 }
1163
1164 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
1165 {
1166         struct ena_rss *rss = &ena_dev->rss;
1167         size_t tbl_size = (1ULL << rss->tbl_log_size) *
1168                 sizeof(struct ena_admin_rss_ind_table_entry);
1169
1170         if (rss->rss_ind_tbl)
1171                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1172                                       tbl_size,
1173                                       rss->rss_ind_tbl,
1174                                       rss->rss_ind_tbl_dma_addr,
1175                                       rss->rss_ind_tbl_mem_handle);
1176         rss->rss_ind_tbl = NULL;
1177
1178         if (rss->host_rss_ind_tbl)
1179                 ENA_MEM_FREE(ena_dev->dmadev,
1180                              rss->host_rss_ind_tbl,
1181                              ((1ULL << rss->tbl_log_size) * sizeof(u16)));
1182         rss->host_rss_ind_tbl = NULL;
1183 }
1184
1185 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
1186                                 struct ena_com_io_sq *io_sq, u16 cq_idx)
1187 {
1188         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1189         struct ena_admin_aq_create_sq_cmd create_cmd;
1190         struct ena_admin_acq_create_sq_resp_desc cmd_completion;
1191         u8 direction;
1192         int ret;
1193
1194         memset(&create_cmd, 0x0, sizeof(create_cmd));
1195
1196         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
1197
1198         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1199                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
1200         else
1201                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
1202
1203         create_cmd.sq_identity |= (direction <<
1204                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1205                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1206
1207         create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1208                 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1209
1210         create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1211                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1212                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1213
1214         create_cmd.sq_caps_3 |=
1215                 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1216
1217         create_cmd.cq_idx = cq_idx;
1218         create_cmd.sq_depth = io_sq->q_depth;
1219
1220         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1221                 ret = ena_com_mem_addr_set(ena_dev,
1222                                            &create_cmd.sq_ba,
1223                                            io_sq->desc_addr.phys_addr);
1224                 if (unlikely(ret)) {
1225                         ena_trc_err("memory address set failed\n");
1226                         return ret;
1227                 }
1228         }
1229
1230         ret = ena_com_execute_admin_command(admin_queue,
1231                                             (struct ena_admin_aq_entry *)&create_cmd,
1232                                             sizeof(create_cmd),
1233                                             (struct ena_admin_acq_entry *)&cmd_completion,
1234                                             sizeof(cmd_completion));
1235         if (unlikely(ret)) {
1236                 ena_trc_err("Failed to create IO SQ. error: %d\n", ret);
1237                 return ret;
1238         }
1239
1240         io_sq->idx = cmd_completion.sq_idx;
1241
1242         io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1243                 (uintptr_t)cmd_completion.sq_doorbell_offset);
1244
1245         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1246                 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1247                                 + cmd_completion.llq_headers_offset);
1248
1249                 io_sq->desc_addr.pbuf_dev_addr =
1250                         (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1251                         cmd_completion.llq_descriptors_offset);
1252         }
1253
1254         ena_trc_dbg("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1255
1256         return ret;
1257 }
1258
1259 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1260 {
1261         struct ena_rss *rss = &ena_dev->rss;
1262         struct ena_com_io_sq *io_sq;
1263         u16 qid;
1264         int i;
1265
1266         for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1267                 qid = rss->host_rss_ind_tbl[i];
1268                 if (qid >= ENA_TOTAL_NUM_QUEUES)
1269                         return ENA_COM_INVAL;
1270
1271                 io_sq = &ena_dev->io_sq_queues[qid];
1272
1273                 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1274                         return ENA_COM_INVAL;
1275
1276                 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1277         }
1278
1279         return 0;
1280 }
1281
1282 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1283                                                  u16 intr_delay_resolution)
1284 {
1285         u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution;
1286
1287         if (unlikely(!intr_delay_resolution)) {
1288                 ena_trc_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1289                 intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION;
1290         }
1291
1292         /* update Rx */
1293         ena_dev->intr_moder_rx_interval =
1294                 ena_dev->intr_moder_rx_interval *
1295                 prev_intr_delay_resolution /
1296                 intr_delay_resolution;
1297
1298         /* update Tx */
1299         ena_dev->intr_moder_tx_interval =
1300                 ena_dev->intr_moder_tx_interval *
1301                 prev_intr_delay_resolution /
1302                 intr_delay_resolution;
1303
1304         ena_dev->intr_delay_resolution = intr_delay_resolution;
1305 }
1306
1307 /*****************************************************************************/
1308 /*******************************      API       ******************************/
1309 /*****************************************************************************/
1310
1311 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1312                                   struct ena_admin_aq_entry *cmd,
1313                                   size_t cmd_size,
1314                                   struct ena_admin_acq_entry *comp,
1315                                   size_t comp_size)
1316 {
1317         struct ena_comp_ctx *comp_ctx;
1318         int ret;
1319
1320         comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1321                                             comp, comp_size);
1322         if (IS_ERR(comp_ctx)) {
1323                 if (comp_ctx == ERR_PTR(ENA_COM_NO_DEVICE))
1324                         ena_trc_dbg("Failed to submit command [%ld]\n",
1325                                     PTR_ERR(comp_ctx));
1326                 else
1327                         ena_trc_err("Failed to submit command [%ld]\n",
1328                                     PTR_ERR(comp_ctx));
1329
1330                 return PTR_ERR(comp_ctx);
1331         }
1332
1333         ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1334         if (unlikely(ret)) {
1335                 if (admin_queue->running_state)
1336                         ena_trc_err("Failed to process command. ret = %d\n",
1337                                     ret);
1338                 else
1339                         ena_trc_dbg("Failed to process command. ret = %d\n",
1340                                     ret);
1341         }
1342         return ret;
1343 }
1344
1345 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1346                          struct ena_com_io_cq *io_cq)
1347 {
1348         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1349         struct ena_admin_aq_create_cq_cmd create_cmd;
1350         struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1351         int ret;
1352
1353         memset(&create_cmd, 0x0, sizeof(create_cmd));
1354
1355         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1356
1357         create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1358                 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1359         create_cmd.cq_caps_1 |=
1360                 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1361
1362         create_cmd.msix_vector = io_cq->msix_vector;
1363         create_cmd.cq_depth = io_cq->q_depth;
1364
1365         ret = ena_com_mem_addr_set(ena_dev,
1366                                    &create_cmd.cq_ba,
1367                                    io_cq->cdesc_addr.phys_addr);
1368         if (unlikely(ret)) {
1369                 ena_trc_err("memory address set failed\n");
1370                 return ret;
1371         }
1372
1373         ret = ena_com_execute_admin_command(admin_queue,
1374                                             (struct ena_admin_aq_entry *)&create_cmd,
1375                                             sizeof(create_cmd),
1376                                             (struct ena_admin_acq_entry *)&cmd_completion,
1377                                             sizeof(cmd_completion));
1378         if (unlikely(ret)) {
1379                 ena_trc_err("Failed to create IO CQ. error: %d\n", ret);
1380                 return ret;
1381         }
1382
1383         io_cq->idx = cmd_completion.cq_idx;
1384
1385         io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1386                 cmd_completion.cq_interrupt_unmask_register_offset);
1387
1388         if (cmd_completion.cq_head_db_register_offset)
1389                 io_cq->cq_head_db_reg =
1390                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1391                         cmd_completion.cq_head_db_register_offset);
1392
1393         if (cmd_completion.numa_node_register_offset)
1394                 io_cq->numa_node_cfg_reg =
1395                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1396                         cmd_completion.numa_node_register_offset);
1397
1398         ena_trc_dbg("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1399
1400         return ret;
1401 }
1402
1403 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1404                             struct ena_com_io_sq **io_sq,
1405                             struct ena_com_io_cq **io_cq)
1406 {
1407         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1408                 ena_trc_err("Invalid queue number %d but the max is %d\n",
1409                             qid, ENA_TOTAL_NUM_QUEUES);
1410                 return ENA_COM_INVAL;
1411         }
1412
1413         *io_sq = &ena_dev->io_sq_queues[qid];
1414         *io_cq = &ena_dev->io_cq_queues[qid];
1415
1416         return 0;
1417 }
1418
1419 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1420 {
1421         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1422         struct ena_comp_ctx *comp_ctx;
1423         u16 i;
1424
1425         if (!admin_queue->comp_ctx)
1426                 return;
1427
1428         for (i = 0; i < admin_queue->q_depth; i++) {
1429                 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1430                 if (unlikely(!comp_ctx))
1431                         break;
1432
1433                 comp_ctx->status = ENA_CMD_ABORTED;
1434
1435                 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
1436         }
1437 }
1438
1439 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1440 {
1441         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1442         unsigned long flags = 0;
1443
1444         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1445         while (ATOMIC32_READ(&admin_queue->outstanding_cmds) != 0) {
1446                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1447                 ENA_MSLEEP(ENA_POLL_MS);
1448                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1449         }
1450         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1451 }
1452
1453 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1454                           struct ena_com_io_cq *io_cq)
1455 {
1456         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1457         struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1458         struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1459         int ret;
1460
1461         memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1462
1463         destroy_cmd.cq_idx = io_cq->idx;
1464         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1465
1466         ret = ena_com_execute_admin_command(admin_queue,
1467                                             (struct ena_admin_aq_entry *)&destroy_cmd,
1468                                             sizeof(destroy_cmd),
1469                                             (struct ena_admin_acq_entry *)&destroy_resp,
1470                                             sizeof(destroy_resp));
1471
1472         if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
1473                 ena_trc_err("Failed to destroy IO CQ. error: %d\n", ret);
1474
1475         return ret;
1476 }
1477
1478 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1479 {
1480         return ena_dev->admin_queue.running_state;
1481 }
1482
1483 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1484 {
1485         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1486         unsigned long flags = 0;
1487
1488         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1489         ena_dev->admin_queue.running_state = state;
1490         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1491 }
1492
1493 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1494 {
1495         u16 depth = ena_dev->aenq.q_depth;
1496
1497         ENA_WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1498
1499         /* Init head_db to mark that all entries in the queue
1500          * are initially available
1501          */
1502         ENA_REG_WRITE32(ena_dev->bus, depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1503 }
1504
1505 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1506 {
1507         struct ena_com_admin_queue *admin_queue;
1508         struct ena_admin_set_feat_cmd cmd;
1509         struct ena_admin_set_feat_resp resp;
1510         struct ena_admin_get_feat_resp get_resp;
1511         int ret;
1512
1513         ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0);
1514         if (ret) {
1515                 ena_trc_info("Can't get aenq configuration\n");
1516                 return ret;
1517         }
1518
1519         if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1520                 ena_trc_warn("Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n",
1521                              get_resp.u.aenq.supported_groups,
1522                              groups_flag);
1523                 return ENA_COM_UNSUPPORTED;
1524         }
1525
1526         memset(&cmd, 0x0, sizeof(cmd));
1527         admin_queue = &ena_dev->admin_queue;
1528
1529         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1530         cmd.aq_common_descriptor.flags = 0;
1531         cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1532         cmd.u.aenq.enabled_groups = groups_flag;
1533
1534         ret = ena_com_execute_admin_command(admin_queue,
1535                                             (struct ena_admin_aq_entry *)&cmd,
1536                                             sizeof(cmd),
1537                                             (struct ena_admin_acq_entry *)&resp,
1538                                             sizeof(resp));
1539
1540         if (unlikely(ret))
1541                 ena_trc_err("Failed to config AENQ ret: %d\n", ret);
1542
1543         return ret;
1544 }
1545
1546 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1547 {
1548         u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1549         int width;
1550
1551         if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1552                 ena_trc_err("Reg read timeout occurred\n");
1553                 return ENA_COM_TIMER_EXPIRED;
1554         }
1555
1556         width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1557                 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1558
1559         ena_trc_dbg("ENA dma width: %d\n", width);
1560
1561         if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1562                 ena_trc_err("DMA width illegal value: %d\n", width);
1563                 return ENA_COM_INVAL;
1564         }
1565
1566         ena_dev->dma_addr_bits = width;
1567
1568         return width;
1569 }
1570
1571 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1572 {
1573         u32 ver;
1574         u32 ctrl_ver;
1575         u32 ctrl_ver_masked;
1576
1577         /* Make sure the ENA version and the controller version are at least
1578          * as the driver expects
1579          */
1580         ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1581         ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1582                                           ENA_REGS_CONTROLLER_VERSION_OFF);
1583
1584         if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1585                      (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1586                 ena_trc_err("Reg read timeout occurred\n");
1587                 return ENA_COM_TIMER_EXPIRED;
1588         }
1589
1590         ena_trc_info("ena device version: %d.%d\n",
1591                      (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1592                      ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1593                      ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1594
1595         ena_trc_info("ena controller version: %d.%d.%d implementation version %d\n",
1596                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK)
1597                      >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1598                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK)
1599                      >> ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1600                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1601                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1602                      ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1603
1604         ctrl_ver_masked =
1605                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1606                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1607                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1608
1609         /* Validate the ctrl version without the implementation ID */
1610         if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1611                 ena_trc_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1612                 return -1;
1613         }
1614
1615         return 0;
1616 }
1617
1618 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1619 {
1620         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1621         struct ena_com_admin_cq *cq = &admin_queue->cq;
1622         struct ena_com_admin_sq *sq = &admin_queue->sq;
1623         struct ena_com_aenq *aenq = &ena_dev->aenq;
1624         u16 size;
1625
1626         ENA_WAIT_EVENT_DESTROY(admin_queue->comp_ctx->wait_event);
1627         if (admin_queue->comp_ctx)
1628                 ENA_MEM_FREE(ena_dev->dmadev,
1629                              admin_queue->comp_ctx,
1630                              (admin_queue->q_depth * sizeof(struct ena_comp_ctx)));
1631         admin_queue->comp_ctx = NULL;
1632         size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1633         if (sq->entries)
1634                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries,
1635                                       sq->dma_addr, sq->mem_handle);
1636         sq->entries = NULL;
1637
1638         size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1639         if (cq->entries)
1640                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, cq->entries,
1641                                       cq->dma_addr, cq->mem_handle);
1642         cq->entries = NULL;
1643
1644         size = ADMIN_AENQ_SIZE(aenq->q_depth);
1645         if (ena_dev->aenq.entries)
1646                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, aenq->entries,
1647                                       aenq->dma_addr, aenq->mem_handle);
1648         aenq->entries = NULL;
1649         ENA_SPINLOCK_DESTROY(admin_queue->q_lock);
1650 }
1651
1652 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1653 {
1654         u32 mask_value = 0;
1655
1656         if (polling)
1657                 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1658
1659         ENA_REG_WRITE32(ena_dev->bus, mask_value,
1660                         ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1661         ena_dev->admin_queue.polling = polling;
1662 }
1663
1664 bool ena_com_get_admin_polling_mode(struct ena_com_dev * ena_dev)
1665 {
1666         return ena_dev->admin_queue.polling;
1667 }
1668
1669 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
1670                                          bool polling)
1671 {
1672         ena_dev->admin_queue.auto_polling = polling;
1673 }
1674
1675 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1676 {
1677         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1678
1679         ENA_SPINLOCK_INIT(mmio_read->lock);
1680         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1681                                sizeof(*mmio_read->read_resp),
1682                                mmio_read->read_resp,
1683                                mmio_read->read_resp_dma_addr,
1684                                mmio_read->read_resp_mem_handle);
1685         if (unlikely(!mmio_read->read_resp))
1686                 goto err;
1687
1688         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1689
1690         mmio_read->read_resp->req_id = 0x0;
1691         mmio_read->seq_num = 0x0;
1692         mmio_read->readless_supported = true;
1693
1694         return 0;
1695
1696 err:
1697                 ENA_SPINLOCK_DESTROY(mmio_read->lock);
1698                 return ENA_COM_NO_MEM;
1699 }
1700
1701 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1702 {
1703         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1704
1705         mmio_read->readless_supported = readless_supported;
1706 }
1707
1708 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1709 {
1710         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1711
1712         ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1713         ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1714
1715         ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1716                               sizeof(*mmio_read->read_resp),
1717                               mmio_read->read_resp,
1718                               mmio_read->read_resp_dma_addr,
1719                               mmio_read->read_resp_mem_handle);
1720
1721         mmio_read->read_resp = NULL;
1722         ENA_SPINLOCK_DESTROY(mmio_read->lock);
1723 }
1724
1725 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1726 {
1727         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1728         u32 addr_low, addr_high;
1729
1730         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1731         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1732
1733         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1734         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1735 }
1736
1737 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1738                        struct ena_aenq_handlers *aenq_handlers)
1739 {
1740         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1741         u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1742         int ret;
1743
1744         dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1745
1746         if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1747                 ena_trc_err("Reg read timeout occurred\n");
1748                 return ENA_COM_TIMER_EXPIRED;
1749         }
1750
1751         if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1752                 ena_trc_err("Device isn't ready, abort com init\n");
1753                 return ENA_COM_NO_DEVICE;
1754         }
1755
1756         admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1757
1758         admin_queue->bus = ena_dev->bus;
1759         admin_queue->q_dmadev = ena_dev->dmadev;
1760         admin_queue->polling = false;
1761         admin_queue->curr_cmd_id = 0;
1762
1763         ATOMIC32_SET(&admin_queue->outstanding_cmds, 0);
1764
1765         ENA_SPINLOCK_INIT(admin_queue->q_lock);
1766
1767         ret = ena_com_init_comp_ctxt(admin_queue);
1768         if (ret)
1769                 goto error;
1770
1771         ret = ena_com_admin_init_sq(admin_queue);
1772         if (ret)
1773                 goto error;
1774
1775         ret = ena_com_admin_init_cq(admin_queue);
1776         if (ret)
1777                 goto error;
1778
1779         admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1780                 ENA_REGS_AQ_DB_OFF);
1781
1782         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1783         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1784
1785         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1786         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1787
1788         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1789         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1790
1791         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1792         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1793
1794         aq_caps = 0;
1795         aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1796         aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1797                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1798                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1799
1800         acq_caps = 0;
1801         acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1802         acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1803                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1804                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1805
1806         ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1807         ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1808         ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1809         if (ret)
1810                 goto error;
1811
1812         admin_queue->running_state = true;
1813
1814         return 0;
1815 error:
1816         ena_com_admin_destroy(ena_dev);
1817
1818         return ret;
1819 }
1820
1821 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1822                             struct ena_com_create_io_ctx *ctx)
1823 {
1824         struct ena_com_io_sq *io_sq;
1825         struct ena_com_io_cq *io_cq;
1826         int ret;
1827
1828         if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1829                 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1830                             ctx->qid, ENA_TOTAL_NUM_QUEUES);
1831                 return ENA_COM_INVAL;
1832         }
1833
1834         io_sq = &ena_dev->io_sq_queues[ctx->qid];
1835         io_cq = &ena_dev->io_cq_queues[ctx->qid];
1836
1837         memset(io_sq, 0x0, sizeof(*io_sq));
1838         memset(io_cq, 0x0, sizeof(*io_cq));
1839
1840         /* Init CQ */
1841         io_cq->q_depth = ctx->queue_size;
1842         io_cq->direction = ctx->direction;
1843         io_cq->qid = ctx->qid;
1844
1845         io_cq->msix_vector = ctx->msix_vector;
1846
1847         io_sq->q_depth = ctx->queue_size;
1848         io_sq->direction = ctx->direction;
1849         io_sq->qid = ctx->qid;
1850
1851         io_sq->mem_queue_type = ctx->mem_queue_type;
1852
1853         if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1854                 /* header length is limited to 8 bits */
1855                 io_sq->tx_max_header_size =
1856                         ENA_MIN32(ena_dev->tx_max_header_size, SZ_256);
1857
1858         ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1859         if (ret)
1860                 goto error;
1861         ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1862         if (ret)
1863                 goto error;
1864
1865         ret = ena_com_create_io_cq(ena_dev, io_cq);
1866         if (ret)
1867                 goto error;
1868
1869         ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1870         if (ret)
1871                 goto destroy_io_cq;
1872
1873         return 0;
1874
1875 destroy_io_cq:
1876         ena_com_destroy_io_cq(ena_dev, io_cq);
1877 error:
1878         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1879         return ret;
1880 }
1881
1882 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1883 {
1884         struct ena_com_io_sq *io_sq;
1885         struct ena_com_io_cq *io_cq;
1886
1887         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1888                 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1889                             qid, ENA_TOTAL_NUM_QUEUES);
1890                 return;
1891         }
1892
1893         io_sq = &ena_dev->io_sq_queues[qid];
1894         io_cq = &ena_dev->io_cq_queues[qid];
1895
1896         ena_com_destroy_io_sq(ena_dev, io_sq);
1897         ena_com_destroy_io_cq(ena_dev, io_cq);
1898
1899         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1900 }
1901
1902 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1903                             struct ena_admin_get_feat_resp *resp)
1904 {
1905         return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0);
1906 }
1907
1908 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1909                               struct ena_com_dev_get_features_ctx *get_feat_ctx)
1910 {
1911         struct ena_admin_get_feat_resp get_resp;
1912         int rc;
1913
1914         rc = ena_com_get_feature(ena_dev, &get_resp,
1915                                  ENA_ADMIN_DEVICE_ATTRIBUTES, 0);
1916         if (rc)
1917                 return rc;
1918
1919         memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1920                sizeof(get_resp.u.dev_attr));
1921         ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1922
1923         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1924                 rc = ena_com_get_feature(ena_dev, &get_resp,
1925                                          ENA_ADMIN_MAX_QUEUES_EXT,
1926                                          ENA_FEATURE_MAX_QUEUE_EXT_VER);
1927                 if (rc)
1928                         return rc;
1929
1930                 if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER)
1931                         return -EINVAL;
1932
1933                 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext,
1934                        sizeof(get_resp.u.max_queue_ext));
1935                 ena_dev->tx_max_header_size =
1936                         get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size;
1937         } else {
1938                 rc = ena_com_get_feature(ena_dev, &get_resp,
1939                                          ENA_ADMIN_MAX_QUEUES_NUM, 0);
1940                 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1941                        sizeof(get_resp.u.max_queue));
1942                 ena_dev->tx_max_header_size =
1943                         get_resp.u.max_queue.max_header_size;
1944
1945                 if (rc)
1946                         return rc;
1947         }
1948
1949         rc = ena_com_get_feature(ena_dev, &get_resp,
1950                                  ENA_ADMIN_AENQ_CONFIG, 0);
1951         if (rc)
1952                 return rc;
1953
1954         memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1955                sizeof(get_resp.u.aenq));
1956
1957         rc = ena_com_get_feature(ena_dev, &get_resp,
1958                                  ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
1959         if (rc)
1960                 return rc;
1961
1962         memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
1963                sizeof(get_resp.u.offload));
1964
1965         /* Driver hints isn't mandatory admin command. So in case the
1966          * command isn't supported set driver hints to 0
1967          */
1968         rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0);
1969
1970         if (!rc)
1971                 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints,
1972                        sizeof(get_resp.u.hw_hints));
1973         else if (rc == ENA_COM_UNSUPPORTED)
1974                 memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints));
1975         else
1976                 return rc;
1977
1978         rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0);
1979         if (!rc)
1980                 memcpy(&get_feat_ctx->llq, &get_resp.u.llq,
1981                        sizeof(get_resp.u.llq));
1982         else if (rc == ENA_COM_UNSUPPORTED)
1983                 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq));
1984         else
1985                 return rc;
1986
1987         rc = ena_com_get_feature(ena_dev, &get_resp,
1988                                  ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
1989         if (!rc)
1990                 memcpy(&get_feat_ctx->ind_table, &get_resp.u.ind_table,
1991                        sizeof(get_resp.u.ind_table));
1992         else if (rc == ENA_COM_UNSUPPORTED)
1993                 memset(&get_feat_ctx->ind_table, 0x0,
1994                        sizeof(get_feat_ctx->ind_table));
1995         else
1996                 return rc;
1997
1998         return 0;
1999 }
2000
2001 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
2002 {
2003         ena_com_handle_admin_completion(&ena_dev->admin_queue);
2004 }
2005
2006 /* ena_handle_specific_aenq_event:
2007  * return the handler that is relevant to the specific event group
2008  */
2009 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,
2010                                                      u16 group)
2011 {
2012         struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
2013
2014         if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
2015                 return aenq_handlers->handlers[group];
2016
2017         return aenq_handlers->unimplemented_handler;
2018 }
2019
2020 /* ena_aenq_intr_handler:
2021  * handles the aenq incoming events.
2022  * pop events from the queue and apply the specific handler
2023  */
2024 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
2025 {
2026         struct ena_admin_aenq_entry *aenq_e;
2027         struct ena_admin_aenq_common_desc *aenq_common;
2028         struct ena_com_aenq *aenq  = &dev->aenq;
2029         u64 timestamp;
2030         ena_aenq_handler handler_cb;
2031         u16 masked_head, processed = 0;
2032         u8 phase;
2033
2034         masked_head = aenq->head & (aenq->q_depth - 1);
2035         phase = aenq->phase;
2036         aenq_e = &aenq->entries[masked_head]; /* Get first entry */
2037         aenq_common = &aenq_e->aenq_common_desc;
2038
2039         /* Go over all the events */
2040         while ((READ_ONCE8(aenq_common->flags) &
2041                 ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
2042                 /* Make sure the phase bit (ownership) is as expected before
2043                  * reading the rest of the descriptor.
2044                  */
2045                 dma_rmb();
2046
2047                 timestamp = (u64)aenq_common->timestamp_low |
2048                         ((u64)aenq_common->timestamp_high << 32);
2049                 ENA_TOUCH(timestamp); /* In case debug is disabled */
2050                 ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%"PRIu64"]\n",
2051                             aenq_common->group,
2052                             aenq_common->syndrom,
2053                             timestamp);
2054
2055                 /* Handle specific event*/
2056                 handler_cb = ena_com_get_specific_aenq_cb(dev,
2057                                                           aenq_common->group);
2058                 handler_cb(data, aenq_e); /* call the actual event handler*/
2059
2060                 /* Get next event entry */
2061                 masked_head++;
2062                 processed++;
2063
2064                 if (unlikely(masked_head == aenq->q_depth)) {
2065                         masked_head = 0;
2066                         phase = !phase;
2067                 }
2068                 aenq_e = &aenq->entries[masked_head];
2069                 aenq_common = &aenq_e->aenq_common_desc;
2070         }
2071
2072         aenq->head += processed;
2073         aenq->phase = phase;
2074
2075         /* Don't update aenq doorbell if there weren't any processed events */
2076         if (!processed)
2077                 return;
2078
2079         /* write the aenq doorbell after all AENQ descriptors were read */
2080         mb();
2081         ENA_REG_WRITE32_RELAXED(dev->bus, (u32)aenq->head,
2082                                 dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
2083 #ifndef MMIOWB_NOT_DEFINED
2084         mmiowb();
2085 #endif
2086 }
2087
2088 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
2089                       enum ena_regs_reset_reason_types reset_reason)
2090 {
2091         u32 stat, timeout, cap, reset_val;
2092         int rc;
2093
2094         stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
2095         cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
2096
2097         if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
2098                      (cap == ENA_MMIO_READ_TIMEOUT))) {
2099                 ena_trc_err("Reg read32 timeout occurred\n");
2100                 return ENA_COM_TIMER_EXPIRED;
2101         }
2102
2103         if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
2104                 ena_trc_err("Device isn't ready, can't reset device\n");
2105                 return ENA_COM_INVAL;
2106         }
2107
2108         timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
2109                         ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
2110         if (timeout == 0) {
2111                 ena_trc_err("Invalid timeout value\n");
2112                 return ENA_COM_INVAL;
2113         }
2114
2115         /* start reset */
2116         reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
2117         reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
2118                         ENA_REGS_DEV_CTL_RESET_REASON_MASK;
2119         ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2120
2121         /* Write again the MMIO read request address */
2122         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
2123
2124         rc = wait_for_reset_state(ena_dev, timeout,
2125                                   ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
2126         if (rc != 0) {
2127                 ena_trc_err("Reset indication didn't turn on\n");
2128                 return rc;
2129         }
2130
2131         /* reset done */
2132         ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2133         rc = wait_for_reset_state(ena_dev, timeout, 0);
2134         if (rc != 0) {
2135                 ena_trc_err("Reset indication didn't turn off\n");
2136                 return rc;
2137         }
2138
2139         timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
2140                 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
2141         if (timeout)
2142                 /* the resolution of timeout reg is 100ms */
2143                 ena_dev->admin_queue.completion_timeout = timeout * 100000;
2144         else
2145                 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
2146
2147         return 0;
2148 }
2149
2150 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
2151                              struct ena_com_stats_ctx *ctx,
2152                              enum ena_admin_get_stats_type type)
2153 {
2154         struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
2155         struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
2156         struct ena_com_admin_queue *admin_queue;
2157         int ret;
2158
2159         admin_queue = &ena_dev->admin_queue;
2160
2161         get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
2162         get_cmd->aq_common_descriptor.flags = 0;
2163         get_cmd->type = type;
2164
2165         ret =  ena_com_execute_admin_command(admin_queue,
2166                                              (struct ena_admin_aq_entry *)get_cmd,
2167                                              sizeof(*get_cmd),
2168                                              (struct ena_admin_acq_entry *)get_resp,
2169                                              sizeof(*get_resp));
2170
2171         if (unlikely(ret))
2172                 ena_trc_err("Failed to get stats. error: %d\n", ret);
2173
2174         return ret;
2175 }
2176
2177 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
2178                                 struct ena_admin_basic_stats *stats)
2179 {
2180         struct ena_com_stats_ctx ctx;
2181         int ret;
2182
2183         memset(&ctx, 0x0, sizeof(ctx));
2184         ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
2185         if (likely(ret == 0))
2186                 memcpy(stats, &ctx.get_resp.basic_stats,
2187                        sizeof(ctx.get_resp.basic_stats));
2188
2189         return ret;
2190 }
2191
2192 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)
2193 {
2194         struct ena_com_admin_queue *admin_queue;
2195         struct ena_admin_set_feat_cmd cmd;
2196         struct ena_admin_set_feat_resp resp;
2197         int ret;
2198
2199         if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
2200                 ena_trc_dbg("Feature %d isn't supported\n", ENA_ADMIN_MTU);
2201                 return ENA_COM_UNSUPPORTED;
2202         }
2203
2204         memset(&cmd, 0x0, sizeof(cmd));
2205         admin_queue = &ena_dev->admin_queue;
2206
2207         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2208         cmd.aq_common_descriptor.flags = 0;
2209         cmd.feat_common.feature_id = ENA_ADMIN_MTU;
2210         cmd.u.mtu.mtu = mtu;
2211
2212         ret = ena_com_execute_admin_command(admin_queue,
2213                                             (struct ena_admin_aq_entry *)&cmd,
2214                                             sizeof(cmd),
2215                                             (struct ena_admin_acq_entry *)&resp,
2216                                             sizeof(resp));
2217
2218         if (unlikely(ret))
2219                 ena_trc_err("Failed to set mtu %d. error: %d\n", mtu, ret);
2220
2221         return ret;
2222 }
2223
2224 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
2225                                  struct ena_admin_feature_offload_desc *offload)
2226 {
2227         int ret;
2228         struct ena_admin_get_feat_resp resp;
2229
2230         ret = ena_com_get_feature(ena_dev, &resp,
2231                                   ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
2232         if (unlikely(ret)) {
2233                 ena_trc_err("Failed to get offload capabilities %d\n", ret);
2234                 return ret;
2235         }
2236
2237         memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
2238
2239         return 0;
2240 }
2241
2242 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2243 {
2244         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2245         struct ena_rss *rss = &ena_dev->rss;
2246         struct ena_admin_set_feat_cmd cmd;
2247         struct ena_admin_set_feat_resp resp;
2248         struct ena_admin_get_feat_resp get_resp;
2249         int ret;
2250
2251         if (!ena_com_check_supported_feature_id(ena_dev,
2252                                                 ENA_ADMIN_RSS_HASH_FUNCTION)) {
2253                 ena_trc_dbg("Feature %d isn't supported\n",
2254                             ENA_ADMIN_RSS_HASH_FUNCTION);
2255                 return ENA_COM_UNSUPPORTED;
2256         }
2257
2258         /* Validate hash function is supported */
2259         ret = ena_com_get_feature(ena_dev, &get_resp,
2260                                   ENA_ADMIN_RSS_HASH_FUNCTION, 0);
2261         if (unlikely(ret))
2262                 return ret;
2263
2264         if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) {
2265                 ena_trc_err("Func hash %d isn't supported by device, abort\n",
2266                             rss->hash_func);
2267                 return ENA_COM_UNSUPPORTED;
2268         }
2269
2270         memset(&cmd, 0x0, sizeof(cmd));
2271
2272         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2273         cmd.aq_common_descriptor.flags =
2274                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2275         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2276         cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2277         cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2278
2279         ret = ena_com_mem_addr_set(ena_dev,
2280                                    &cmd.control_buffer.address,
2281                                    rss->hash_key_dma_addr);
2282         if (unlikely(ret)) {
2283                 ena_trc_err("memory address set failed\n");
2284                 return ret;
2285         }
2286
2287         cmd.control_buffer.length = sizeof(*rss->hash_key);
2288
2289         ret = ena_com_execute_admin_command(admin_queue,
2290                                             (struct ena_admin_aq_entry *)&cmd,
2291                                             sizeof(cmd),
2292                                             (struct ena_admin_acq_entry *)&resp,
2293                                             sizeof(resp));
2294         if (unlikely(ret)) {
2295                 ena_trc_err("Failed to set hash function %d. error: %d\n",
2296                             rss->hash_func, ret);
2297                 return ENA_COM_INVAL;
2298         }
2299
2300         return 0;
2301 }
2302
2303 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2304                                enum ena_admin_hash_functions func,
2305                                const u8 *key, u16 key_len, u32 init_val)
2306 {
2307         struct ena_admin_feature_rss_flow_hash_control *hash_key;
2308         struct ena_admin_get_feat_resp get_resp;
2309         enum ena_admin_hash_functions old_func;
2310         struct ena_rss *rss = &ena_dev->rss;
2311         int rc;
2312
2313         hash_key = rss->hash_key;
2314
2315         /* Make sure size is a mult of DWs */
2316         if (unlikely(key_len & 0x3))
2317                 return ENA_COM_INVAL;
2318
2319         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2320                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2321                                     rss->hash_key_dma_addr,
2322                                     sizeof(*rss->hash_key), 0);
2323         if (unlikely(rc))
2324                 return rc;
2325
2326         if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) {
2327                 ena_trc_err("Flow hash function %d isn't supported\n", func);
2328                 return ENA_COM_UNSUPPORTED;
2329         }
2330
2331         switch (func) {
2332         case ENA_ADMIN_TOEPLITZ:
2333                 if (key) {
2334                         if (key_len != sizeof(hash_key->key)) {
2335                                 ena_trc_err("key len (%hu) doesn't equal the supported size (%zu)\n",
2336                                              key_len, sizeof(hash_key->key));
2337                                 return ENA_COM_INVAL;
2338                         }
2339                         memcpy(hash_key->key, key, key_len);
2340                         rss->hash_init_val = init_val;
2341                         hash_key->keys_num = key_len / sizeof(u32);
2342                 }
2343                 break;
2344         case ENA_ADMIN_CRC32:
2345                 rss->hash_init_val = init_val;
2346                 break;
2347         default:
2348                 ena_trc_err("Invalid hash function (%d)\n", func);
2349                 return ENA_COM_INVAL;
2350         }
2351
2352         old_func = rss->hash_func;
2353         rss->hash_func = func;
2354         rc = ena_com_set_hash_function(ena_dev);
2355
2356         /* Restore the old function */
2357         if (unlikely(rc))
2358                 rss->hash_func = old_func;
2359
2360         return rc;
2361 }
2362
2363 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2364                               enum ena_admin_hash_functions *func,
2365                               u8 *key)
2366 {
2367         struct ena_rss *rss = &ena_dev->rss;
2368         struct ena_admin_get_feat_resp get_resp;
2369         struct ena_admin_feature_rss_flow_hash_control *hash_key =
2370                 rss->hash_key;
2371         int rc;
2372
2373         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2374                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2375                                     rss->hash_key_dma_addr,
2376                                     sizeof(*rss->hash_key), 0);
2377         if (unlikely(rc))
2378                 return rc;
2379
2380         /* ENA_FFS returns 1 in case the lsb is set */
2381         rss->hash_func = ENA_FFS(get_resp.u.flow_hash_func.selected_func);
2382         if (rss->hash_func)
2383                 rss->hash_func--;
2384
2385         if (func)
2386                 *func = rss->hash_func;
2387
2388         if (key)
2389                 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
2390
2391         return 0;
2392 }
2393
2394 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2395                           enum ena_admin_flow_hash_proto proto,
2396                           u16 *fields)
2397 {
2398         struct ena_rss *rss = &ena_dev->rss;
2399         struct ena_admin_get_feat_resp get_resp;
2400         int rc;
2401
2402         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2403                                     ENA_ADMIN_RSS_HASH_INPUT,
2404                                     rss->hash_ctrl_dma_addr,
2405                                     sizeof(*rss->hash_ctrl), 0);
2406         if (unlikely(rc))
2407                 return rc;
2408
2409         if (fields)
2410                 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2411
2412         return 0;
2413 }
2414
2415 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2416 {
2417         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2418         struct ena_rss *rss = &ena_dev->rss;
2419         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2420         struct ena_admin_set_feat_cmd cmd;
2421         struct ena_admin_set_feat_resp resp;
2422         int ret;
2423
2424         if (!ena_com_check_supported_feature_id(ena_dev,
2425                                                 ENA_ADMIN_RSS_HASH_INPUT)) {
2426                 ena_trc_dbg("Feature %d isn't supported\n",
2427                             ENA_ADMIN_RSS_HASH_INPUT);
2428                 return ENA_COM_UNSUPPORTED;
2429         }
2430
2431         memset(&cmd, 0x0, sizeof(cmd));
2432
2433         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2434         cmd.aq_common_descriptor.flags =
2435                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2436         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2437         cmd.u.flow_hash_input.enabled_input_sort =
2438                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2439                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2440
2441         ret = ena_com_mem_addr_set(ena_dev,
2442                                    &cmd.control_buffer.address,
2443                                    rss->hash_ctrl_dma_addr);
2444         if (unlikely(ret)) {
2445                 ena_trc_err("memory address set failed\n");
2446                 return ret;
2447         }
2448         cmd.control_buffer.length = sizeof(*hash_ctrl);
2449
2450         ret = ena_com_execute_admin_command(admin_queue,
2451                                             (struct ena_admin_aq_entry *)&cmd,
2452                                             sizeof(cmd),
2453                                             (struct ena_admin_acq_entry *)&resp,
2454                                             sizeof(resp));
2455         if (unlikely(ret))
2456                 ena_trc_err("Failed to set hash input. error: %d\n", ret);
2457
2458         return ret;
2459 }
2460
2461 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2462 {
2463         struct ena_rss *rss = &ena_dev->rss;
2464         struct ena_admin_feature_rss_hash_control *hash_ctrl =
2465                 rss->hash_ctrl;
2466         u16 available_fields = 0;
2467         int rc, i;
2468
2469         /* Get the supported hash input */
2470         rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2471         if (unlikely(rc))
2472                 return rc;
2473
2474         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2475                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2476                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2477
2478         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2479                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2480                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2481
2482         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2483                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2484                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2485
2486         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2487                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2488                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2489
2490         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2491                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2492
2493         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2494                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2495
2496         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2497                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2498
2499         hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2500                 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2501
2502         for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2503                 available_fields = hash_ctrl->selected_fields[i].fields &
2504                                 hash_ctrl->supported_fields[i].fields;
2505                 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2506                         ena_trc_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2507                                     i, hash_ctrl->supported_fields[i].fields,
2508                                     hash_ctrl->selected_fields[i].fields);
2509                         return ENA_COM_UNSUPPORTED;
2510                 }
2511         }
2512
2513         rc = ena_com_set_hash_ctrl(ena_dev);
2514
2515         /* In case of failure, restore the old hash ctrl */
2516         if (unlikely(rc))
2517                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2518
2519         return rc;
2520 }
2521
2522 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2523                            enum ena_admin_flow_hash_proto proto,
2524                            u16 hash_fields)
2525 {
2526         struct ena_rss *rss = &ena_dev->rss;
2527         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2528         u16 supported_fields;
2529         int rc;
2530
2531         if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2532                 ena_trc_err("Invalid proto num (%u)\n", proto);
2533                 return ENA_COM_INVAL;
2534         }
2535
2536         /* Get the ctrl table */
2537         rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2538         if (unlikely(rc))
2539                 return rc;
2540
2541         /* Make sure all the fields are supported */
2542         supported_fields = hash_ctrl->supported_fields[proto].fields;
2543         if ((hash_fields & supported_fields) != hash_fields) {
2544                 ena_trc_err("proto %d doesn't support the required fields %x. supports only: %x\n",
2545                             proto, hash_fields, supported_fields);
2546         }
2547
2548         hash_ctrl->selected_fields[proto].fields = hash_fields;
2549
2550         rc = ena_com_set_hash_ctrl(ena_dev);
2551
2552         /* In case of failure, restore the old hash ctrl */
2553         if (unlikely(rc))
2554                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2555
2556         return 0;
2557 }
2558
2559 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2560                                       u16 entry_idx, u16 entry_value)
2561 {
2562         struct ena_rss *rss = &ena_dev->rss;
2563
2564         if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2565                 return ENA_COM_INVAL;
2566
2567         if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2568                 return ENA_COM_INVAL;
2569
2570         rss->host_rss_ind_tbl[entry_idx] = entry_value;
2571
2572         return 0;
2573 }
2574
2575 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2576 {
2577         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2578         struct ena_rss *rss = &ena_dev->rss;
2579         struct ena_admin_set_feat_cmd cmd;
2580         struct ena_admin_set_feat_resp resp;
2581         int ret;
2582
2583         if (!ena_com_check_supported_feature_id(ena_dev,
2584                                                 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {
2585                 ena_trc_dbg("Feature %d isn't supported\n",
2586                             ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
2587                 return ENA_COM_UNSUPPORTED;
2588         }
2589
2590         ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2591         if (ret) {
2592                 ena_trc_err("Failed to convert host indirection table to device table\n");
2593                 return ret;
2594         }
2595
2596         memset(&cmd, 0x0, sizeof(cmd));
2597
2598         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2599         cmd.aq_common_descriptor.flags =
2600                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2601         cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG;
2602         cmd.u.ind_table.size = rss->tbl_log_size;
2603         cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2604
2605         ret = ena_com_mem_addr_set(ena_dev,
2606                                    &cmd.control_buffer.address,
2607                                    rss->rss_ind_tbl_dma_addr);
2608         if (unlikely(ret)) {
2609                 ena_trc_err("memory address set failed\n");
2610                 return ret;
2611         }
2612
2613         cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2614                 sizeof(struct ena_admin_rss_ind_table_entry);
2615
2616         ret = ena_com_execute_admin_command(admin_queue,
2617                                             (struct ena_admin_aq_entry *)&cmd,
2618                                             sizeof(cmd),
2619                                             (struct ena_admin_acq_entry *)&resp,
2620                                             sizeof(resp));
2621
2622         if (unlikely(ret))
2623                 ena_trc_err("Failed to set indirect table. error: %d\n", ret);
2624
2625         return ret;
2626 }
2627
2628 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2629 {
2630         struct ena_rss *rss = &ena_dev->rss;
2631         struct ena_admin_get_feat_resp get_resp;
2632         u32 tbl_size;
2633         int i, rc;
2634
2635         tbl_size = (1ULL << rss->tbl_log_size) *
2636                 sizeof(struct ena_admin_rss_ind_table_entry);
2637
2638         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2639                                     ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
2640                                     rss->rss_ind_tbl_dma_addr,
2641                                     tbl_size, 0);
2642         if (unlikely(rc))
2643                 return rc;
2644
2645         if (!ind_tbl)
2646                 return 0;
2647
2648         for (i = 0; i < (1 << rss->tbl_log_size); i++)
2649                 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2650
2651         return 0;
2652 }
2653
2654 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2655 {
2656         int rc;
2657
2658         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2659
2660         rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2661         if (unlikely(rc))
2662                 goto err_indr_tbl;
2663
2664         rc = ena_com_hash_key_allocate(ena_dev);
2665         if (unlikely(rc))
2666                 goto err_hash_key;
2667
2668         ena_com_hash_key_fill_default_key(ena_dev);
2669
2670         rc = ena_com_hash_ctrl_init(ena_dev);
2671         if (unlikely(rc))
2672                 goto err_hash_ctrl;
2673
2674         return 0;
2675
2676 err_hash_ctrl:
2677         ena_com_hash_key_destroy(ena_dev);
2678 err_hash_key:
2679         ena_com_indirect_table_destroy(ena_dev);
2680 err_indr_tbl:
2681
2682         return rc;
2683 }
2684
2685 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2686 {
2687         ena_com_indirect_table_destroy(ena_dev);
2688         ena_com_hash_key_destroy(ena_dev);
2689         ena_com_hash_ctrl_destroy(ena_dev);
2690
2691         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2692 }
2693
2694 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2695 {
2696         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2697
2698         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2699                                SZ_4K,
2700                                host_attr->host_info,
2701                                host_attr->host_info_dma_addr,
2702                                host_attr->host_info_dma_handle);
2703         if (unlikely(!host_attr->host_info))
2704                 return ENA_COM_NO_MEM;
2705
2706         host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR <<
2707                 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) |
2708                 (ENA_COMMON_SPEC_VERSION_MINOR));
2709
2710         return 0;
2711 }
2712
2713 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2714                                 u32 debug_area_size)
2715 {
2716         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2717
2718         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2719                                debug_area_size,
2720                                host_attr->debug_area_virt_addr,
2721                                host_attr->debug_area_dma_addr,
2722                                host_attr->debug_area_dma_handle);
2723         if (unlikely(!host_attr->debug_area_virt_addr)) {
2724                 host_attr->debug_area_size = 0;
2725                 return ENA_COM_NO_MEM;
2726         }
2727
2728         host_attr->debug_area_size = debug_area_size;
2729
2730         return 0;
2731 }
2732
2733 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2734 {
2735         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2736
2737         if (host_attr->host_info) {
2738                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2739                                       SZ_4K,
2740                                       host_attr->host_info,
2741                                       host_attr->host_info_dma_addr,
2742                                       host_attr->host_info_dma_handle);
2743                 host_attr->host_info = NULL;
2744         }
2745 }
2746
2747 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2748 {
2749         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2750
2751         if (host_attr->debug_area_virt_addr) {
2752                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2753                                       host_attr->debug_area_size,
2754                                       host_attr->debug_area_virt_addr,
2755                                       host_attr->debug_area_dma_addr,
2756                                       host_attr->debug_area_dma_handle);
2757                 host_attr->debug_area_virt_addr = NULL;
2758         }
2759 }
2760
2761 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2762 {
2763         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2764         struct ena_com_admin_queue *admin_queue;
2765         struct ena_admin_set_feat_cmd cmd;
2766         struct ena_admin_set_feat_resp resp;
2767
2768         int ret;
2769
2770         /* Host attribute config is called before ena_com_get_dev_attr_feat
2771          * so ena_com can't check if the feature is supported.
2772          */
2773
2774         memset(&cmd, 0x0, sizeof(cmd));
2775         admin_queue = &ena_dev->admin_queue;
2776
2777         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2778         cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2779
2780         ret = ena_com_mem_addr_set(ena_dev,
2781                                    &cmd.u.host_attr.debug_ba,
2782                                    host_attr->debug_area_dma_addr);
2783         if (unlikely(ret)) {
2784                 ena_trc_err("memory address set failed\n");
2785                 return ret;
2786         }
2787
2788         ret = ena_com_mem_addr_set(ena_dev,
2789                                    &cmd.u.host_attr.os_info_ba,
2790                                    host_attr->host_info_dma_addr);
2791         if (unlikely(ret)) {
2792                 ena_trc_err("memory address set failed\n");
2793                 return ret;
2794         }
2795
2796         cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2797
2798         ret = ena_com_execute_admin_command(admin_queue,
2799                                             (struct ena_admin_aq_entry *)&cmd,
2800                                             sizeof(cmd),
2801                                             (struct ena_admin_acq_entry *)&resp,
2802                                             sizeof(resp));
2803
2804         if (unlikely(ret))
2805                 ena_trc_err("Failed to set host attributes: %d\n", ret);
2806
2807         return ret;
2808 }
2809
2810 /* Interrupt moderation */
2811 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2812 {
2813         return ena_com_check_supported_feature_id(ena_dev,
2814                                                   ENA_ADMIN_INTERRUPT_MODERATION);
2815 }
2816
2817 static int ena_com_update_nonadaptive_moderation_interval(u32 coalesce_usecs,
2818                                                           u32 intr_delay_resolution,
2819                                                           u32 *intr_moder_interval)
2820 {
2821         if (!intr_delay_resolution) {
2822                 ena_trc_err("Illegal interrupt delay granularity value\n");
2823                 return ENA_COM_FAULT;
2824         }
2825
2826         *intr_moder_interval = coalesce_usecs / intr_delay_resolution;
2827
2828         return 0;
2829 }
2830
2831
2832 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2833                                                       u32 tx_coalesce_usecs)
2834 {
2835         return ena_com_update_nonadaptive_moderation_interval(tx_coalesce_usecs,
2836                                                               ena_dev->intr_delay_resolution,
2837                                                               &ena_dev->intr_moder_tx_interval);
2838 }
2839
2840 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2841                                                       u32 rx_coalesce_usecs)
2842 {
2843         return ena_com_update_nonadaptive_moderation_interval(rx_coalesce_usecs,
2844                                                               ena_dev->intr_delay_resolution,
2845                                                               &ena_dev->intr_moder_rx_interval);
2846 }
2847
2848 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2849 {
2850         struct ena_admin_get_feat_resp get_resp;
2851         u16 delay_resolution;
2852         int rc;
2853
2854         rc = ena_com_get_feature(ena_dev, &get_resp,
2855                                  ENA_ADMIN_INTERRUPT_MODERATION, 0);
2856
2857         if (rc) {
2858                 if (rc == ENA_COM_UNSUPPORTED) {
2859                         ena_trc_dbg("Feature %d isn't supported\n",
2860                                     ENA_ADMIN_INTERRUPT_MODERATION);
2861                         rc = 0;
2862                 } else {
2863                         ena_trc_err("Failed to get interrupt moderation admin cmd. rc: %d\n",
2864                                     rc);
2865                 }
2866
2867                 /* no moderation supported, disable adaptive support */
2868                 ena_com_disable_adaptive_moderation(ena_dev);
2869                 return rc;
2870         }
2871
2872         /* if moderation is supported by device we set adaptive moderation */
2873         delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2874         ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2875
2876         /* Disable adaptive moderation by default - can be enabled later */
2877         ena_com_disable_adaptive_moderation(ena_dev);
2878
2879         return 0;
2880 }
2881
2882 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2883 {
2884         return ena_dev->intr_moder_tx_interval;
2885 }
2886
2887 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2888 {
2889         return ena_dev->intr_moder_rx_interval;
2890 }
2891
2892 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
2893                             struct ena_admin_feature_llq_desc *llq_features,
2894                             struct ena_llq_configurations *llq_default_cfg)
2895 {
2896         int rc;
2897         struct ena_com_llq_info *llq_info = &(ena_dev->llq_info);;
2898
2899         if (!llq_features->max_llq_num) {
2900                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
2901                 return 0;
2902         }
2903
2904         rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg);
2905         if (rc)
2906                 return rc;
2907
2908         ena_dev->tx_max_header_size = llq_info->desc_list_entry_size -
2909                 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc));
2910
2911         if (ena_dev->tx_max_header_size == 0) {
2912                 ena_trc_err("the size of the LLQ entry is smaller than needed\n");
2913                 return -EINVAL;
2914         }
2915
2916         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
2917
2918         return 0;
2919 }