drivers/net/ena/base/ena_com.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include "ena_com.h"
   7
   8 /*****************************************************************************/
   9 /*****************************************************************************/
  10
  11 /* Timeout in micro-sec */
  12 #define ADMIN_CMD_TIMEOUT_US (3000000)
  13
  14 #define ENA_ASYNC_QUEUE_DEPTH 16
  15 #define ENA_ADMIN_QUEUE_DEPTH 32
  16
  17 #define ENA_CTRL_MAJOR          0
  18 #define ENA_CTRL_MINOR          0
  19 #define ENA_CTRL_SUB_MINOR      1
  20
  21 #define MIN_ENA_CTRL_VER \
  22         (((ENA_CTRL_MAJOR) << \
  23         (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
  24         ((ENA_CTRL_MINOR) << \
  25         (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
  26         (ENA_CTRL_SUB_MINOR))
  27
  28 #define ENA_DMA_ADDR_TO_UINT32_LOW(x)   ((u32)((u64)(x)))
  29 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x)  ((u32)(((u64)(x)) >> 32))
  30
  31 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
  32
  33 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4
  34
  35 #define ENA_REGS_ADMIN_INTR_MASK 1
  36
  37 #define ENA_MIN_ADMIN_POLL_US 100
  38
  39 #define ENA_MAX_ADMIN_POLL_US 5000
  40
  41 /*****************************************************************************/
  42 /*****************************************************************************/
  43 /*****************************************************************************/
  44
  45 enum ena_cmd_status {
  46         ENA_CMD_SUBMITTED,
  47         ENA_CMD_COMPLETED,
  48         /* Abort - canceled by the driver */
  49         ENA_CMD_ABORTED,
  50 };
  51
  52 struct ena_comp_ctx {
  53         ena_wait_event_t wait_event;
  54         struct ena_admin_acq_entry *user_cqe;
  55         u32 comp_size;
  56         enum ena_cmd_status status;
  57         /* status from the device */
  58         u8 comp_status;
  59         u8 cmd_opcode;
  60         bool occupied;
  61 };
  62
  63 struct ena_com_stats_ctx {
  64         struct ena_admin_aq_get_stats_cmd get_cmd;
  65         struct ena_admin_acq_get_stats_resp get_resp;
  66 };
  67
  68 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
  69                                        struct ena_common_mem_addr *ena_addr,
  70                                        dma_addr_t addr)
  71 {
  72         if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
  73                 ena_trc_err("dma address has more bits that the device supports\n");
  74                 return ENA_COM_INVAL;
  75         }
  76
  77         ena_addr->mem_addr_low = lower_32_bits(addr);
  78         ena_addr->mem_addr_high = (u16)upper_32_bits(addr);
  79
  80         return 0;
  81 }
  82
  83 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)
  84 {
  85         struct ena_com_admin_sq *sq = &queue->sq;
  86         u16 size = ADMIN_SQ_SIZE(queue->q_depth);
  87
  88         ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, sq->entries, sq->dma_addr,
  89                                sq->mem_handle);
  90
  91         if (!sq->entries) {
  92                 ena_trc_err("memory allocation failed\n");
  93                 return ENA_COM_NO_MEM;
  94         }
  95
  96         sq->head = 0;
  97         sq->tail = 0;
  98         sq->phase = 1;
  99
 100         sq->db_addr = NULL;
 101
 102         return 0;
 103 }
 104
 105 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)
 106 {
 107         struct ena_com_admin_cq *cq = &queue->cq;
 108         u16 size = ADMIN_CQ_SIZE(queue->q_depth);
 109
 110         ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, cq->entries, cq->dma_addr,
 111                                cq->mem_handle);
 112
 113         if (!cq->entries)  {
 114                 ena_trc_err("memory allocation failed\n");
 115                 return ENA_COM_NO_MEM;
 116         }
 117
 118         cq->head = 0;
 119         cq->phase = 1;
 120
 121         return 0;
 122 }
 123
 124 static int ena_com_admin_init_aenq(struct ena_com_dev *dev,
 125                                    struct ena_aenq_handlers *aenq_handlers)
 126 {
 127         struct ena_com_aenq *aenq = &dev->aenq;
 128         u32 addr_low, addr_high, aenq_caps;
 129         u16 size;
 130
 131         dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
 132         size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
 133         ENA_MEM_ALLOC_COHERENT(dev->dmadev, size,
 134                         aenq->entries,
 135                         aenq->dma_addr,
 136                         aenq->mem_handle);
 137
 138         if (!aenq->entries) {
 139                 ena_trc_err("memory allocation failed\n");
 140                 return ENA_COM_NO_MEM;
 141         }
 142
 143         aenq->head = aenq->q_depth;
 144         aenq->phase = 1;
 145
 146         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
 147         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
 148
 149         ENA_REG_WRITE32(dev->bus, addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
 150         ENA_REG_WRITE32(dev->bus, addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
 151
 152         aenq_caps = 0;
 153         aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
 154         aenq_caps |= (sizeof(struct ena_admin_aenq_entry) <<
 155                 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
 156                 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
 157         ENA_REG_WRITE32(dev->bus, aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
 158
 159         if (unlikely(!aenq_handlers)) {
 160                 ena_trc_err("aenq handlers pointer is NULL\n");
 161                 return ENA_COM_INVAL;
 162         }
 163
 164         aenq->aenq_handlers = aenq_handlers;
 165
 166         return 0;
 167 }
 168
 169 static void comp_ctxt_release(struct ena_com_admin_queue *queue,
 170                                      struct ena_comp_ctx *comp_ctx)
 171 {
 172         comp_ctx->occupied = false;
 173         ATOMIC32_DEC(&queue->outstanding_cmds);
 174 }
 175
 176 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
 177                                           u16 command_id, bool capture)
 178 {
 179         if (unlikely(command_id >= queue->q_depth)) {
 180                 ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
 181                             command_id, queue->q_depth);
 182                 return NULL;
 183         }
 184
 185         if (unlikely(!queue->comp_ctx)) {
 186                 ena_trc_err("Completion context is NULL\n");
 187                 return NULL;
 188         }
 189
 190         if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
 191                 ena_trc_err("Completion context is occupied\n");
 192                 return NULL;
 193         }
 194
 195         if (capture) {
 196                 ATOMIC32_INC(&queue->outstanding_cmds);
 197                 queue->comp_ctx[command_id].occupied = true;
 198         }
 199
 200         return &queue->comp_ctx[command_id];
 201 }
 202
 203 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 204                                                        struct ena_admin_aq_entry *cmd,
 205                                                        size_t cmd_size_in_bytes,
 206                                                        struct ena_admin_acq_entry *comp,
 207                                                        size_t comp_size_in_bytes)
 208 {
 209         struct ena_comp_ctx *comp_ctx;
 210         u16 tail_masked, cmd_id;
 211         u16 queue_size_mask;
 212         u16 cnt;
 213
 214         queue_size_mask = admin_queue->q_depth - 1;
 215
 216         tail_masked = admin_queue->sq.tail & queue_size_mask;
 217
 218         /* In case of queue FULL */
 219         cnt = (u16)ATOMIC32_READ(&admin_queue->outstanding_cmds);
 220         if (cnt >= admin_queue->q_depth) {
 221                 ena_trc_dbg("admin queue is full.\n");
 222                 admin_queue->stats.out_of_space++;
 223                 return ERR_PTR(ENA_COM_NO_SPACE);
 224         }
 225
 226         cmd_id = admin_queue->curr_cmd_id;
 227
 228         cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
 229                 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
 230
 231         cmd->aq_common_descriptor.command_id |= cmd_id &
 232                 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
 233
 234         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
 235         if (unlikely(!comp_ctx))
 236                 return ERR_PTR(ENA_COM_INVAL);
 237
 238         comp_ctx->status = ENA_CMD_SUBMITTED;
 239         comp_ctx->comp_size = (u32)comp_size_in_bytes;
 240         comp_ctx->user_cqe = comp;
 241         comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
 242
 243         ENA_WAIT_EVENT_CLEAR(comp_ctx->wait_event);
 244
 245         memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
 246
 247         admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
 248                 queue_size_mask;
 249
 250         admin_queue->sq.tail++;
 251         admin_queue->stats.submitted_cmd++;
 252
 253         if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
 254                 admin_queue->sq.phase = !admin_queue->sq.phase;
 255
 256         ENA_DB_SYNC(&admin_queue->sq.mem_handle);
 257         ENA_REG_WRITE32(admin_queue->bus, admin_queue->sq.tail,
 258                         admin_queue->sq.db_addr);
 259
 260         return comp_ctx;
 261 }
 262
 263 static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
 264 {
 265         size_t size = queue->q_depth * sizeof(struct ena_comp_ctx);
 266         struct ena_comp_ctx *comp_ctx;
 267         u16 i;
 268
 269         queue->comp_ctx = ENA_MEM_ALLOC(queue->q_dmadev, size);
 270         if (unlikely(!queue->comp_ctx)) {
 271                 ena_trc_err("memory allocation failed\n");
 272                 return ENA_COM_NO_MEM;
 273         }
 274
 275         for (i = 0; i < queue->q_depth; i++) {
 276                 comp_ctx = get_comp_ctxt(queue, i, false);
 277                 if (comp_ctx)
 278                         ENA_WAIT_EVENT_INIT(comp_ctx->wait_event);
 279         }
 280
 281         return 0;
 282 }
 283
 284 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 285                                                      struct ena_admin_aq_entry *cmd,
 286                                                      size_t cmd_size_in_bytes,
 287                                                      struct ena_admin_acq_entry *comp,
 288                                                      size_t comp_size_in_bytes)
 289 {
 290         unsigned long flags = 0;
 291         struct ena_comp_ctx *comp_ctx;
 292
 293         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 294         if (unlikely(!admin_queue->running_state)) {
 295                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 296                 return ERR_PTR(ENA_COM_NO_DEVICE);
 297         }
 298         comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
 299                                               cmd_size_in_bytes,
 300                                               comp,
 301                                               comp_size_in_bytes);
 302         if (IS_ERR(comp_ctx))
 303                 admin_queue->running_state = false;
 304         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 305
 306         return comp_ctx;
 307 }
 308
 309 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
 310                               struct ena_com_create_io_ctx *ctx,
 311                               struct ena_com_io_sq *io_sq)
 312 {
 313         size_t size;
 314         int dev_node = 0;
 315
 316         memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
 317
 318         io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits;
 319         io_sq->desc_entry_size =
 320                 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 321                 sizeof(struct ena_eth_io_tx_desc) :
 322                 sizeof(struct ena_eth_io_rx_desc);
 323
 324         size = io_sq->desc_entry_size * io_sq->q_depth;
 325         io_sq->bus = ena_dev->bus;
 326
 327         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
 328                 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
 329                                             size,
 330                                             io_sq->desc_addr.virt_addr,
 331                                             io_sq->desc_addr.phys_addr,
 332                                             io_sq->desc_addr.mem_handle,
 333                                             ctx->numa_node,
 334                                             dev_node);
 335                 if (!io_sq->desc_addr.virt_addr) {
 336                         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
 337                                                size,
 338                                                io_sq->desc_addr.virt_addr,
 339                                                io_sq->desc_addr.phys_addr,
 340                                                io_sq->desc_addr.mem_handle);
 341                 }
 342
 343                 if (!io_sq->desc_addr.virt_addr) {
 344                         ena_trc_err("memory allocation failed\n");
 345                         return ENA_COM_NO_MEM;
 346                 }
 347         }
 348
 349         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 350                 /* Allocate bounce buffers */
 351                 io_sq->bounce_buf_ctrl.buffer_size =
 352                         ena_dev->llq_info.desc_list_entry_size;
 353                 io_sq->bounce_buf_ctrl.buffers_num =
 354                         ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
 355                 io_sq->bounce_buf_ctrl.next_to_use = 0;
 356
 357                 size = io_sq->bounce_buf_ctrl.buffer_size *
 358                         io_sq->bounce_buf_ctrl.buffers_num;
 359
 360                 ENA_MEM_ALLOC_NODE(ena_dev->dmadev,
 361                                    size,
 362                                    io_sq->bounce_buf_ctrl.base_buffer,
 363                                    ctx->numa_node,
 364                                    dev_node);
 365                 if (!io_sq->bounce_buf_ctrl.base_buffer)
 366                         io_sq->bounce_buf_ctrl.base_buffer = ENA_MEM_ALLOC(ena_dev->dmadev, size);
 367
 368                 if (!io_sq->bounce_buf_ctrl.base_buffer) {
 369                         ena_trc_err("bounce buffer memory allocation failed\n");
 370                         return ENA_COM_NO_MEM;
 371                 }
 372
 373                 memcpy(&io_sq->llq_info, &ena_dev->llq_info,
 374                        sizeof(io_sq->llq_info));
 375
 376                 /* Initiate the first bounce buffer */
 377                 io_sq->llq_buf_ctrl.curr_bounce_buf =
 378                         ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
 379                 memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
 380                        0x0, io_sq->llq_info.desc_list_entry_size);
 381                 io_sq->llq_buf_ctrl.descs_left_in_line =
 382                         io_sq->llq_info.descs_num_before_header;
 383                 io_sq->disable_meta_caching =
 384                         io_sq->llq_info.disable_meta_caching;
 385
 386                 if (io_sq->llq_info.max_entries_in_tx_burst > 0)
 387                         io_sq->entries_in_tx_burst_left =
 388                                 io_sq->llq_info.max_entries_in_tx_burst;
 389         }
 390
 391         io_sq->tail = 0;
 392         io_sq->next_to_comp = 0;
 393         io_sq->phase = 1;
 394
 395         return 0;
 396 }
 397
 398 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
 399                               struct ena_com_create_io_ctx *ctx,
 400                               struct ena_com_io_cq *io_cq)
 401 {
 402         size_t size;
 403         int prev_node = 0;
 404
 405         memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
 406
 407         /* Use the basic completion descriptor for Rx */
 408         io_cq->cdesc_entry_size_in_bytes =
 409                 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 410                 sizeof(struct ena_eth_io_tx_cdesc) :
 411                 sizeof(struct ena_eth_io_rx_cdesc_base);
 412
 413         size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 414         io_cq->bus = ena_dev->bus;
 415
 416         ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
 417                         size,
 418                         io_cq->cdesc_addr.virt_addr,
 419                         io_cq->cdesc_addr.phys_addr,
 420                         io_cq->cdesc_addr.mem_handle,
 421                         ctx->numa_node,
 422                         prev_node);
 423         if (!io_cq->cdesc_addr.virt_addr) {
 424                 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
 425                                        size,
 426                                        io_cq->cdesc_addr.virt_addr,
 427                                        io_cq->cdesc_addr.phys_addr,
 428                                        io_cq->cdesc_addr.mem_handle);
 429         }
 430
 431         if (!io_cq->cdesc_addr.virt_addr) {
 432                 ena_trc_err("memory allocation failed\n");
 433                 return ENA_COM_NO_MEM;
 434         }
 435
 436         io_cq->phase = 1;
 437         io_cq->head = 0;
 438
 439         return 0;
 440 }
 441
 442 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
 443                                                    struct ena_admin_acq_entry *cqe)
 444 {
 445         struct ena_comp_ctx *comp_ctx;
 446         u16 cmd_id;
 447
 448         cmd_id = cqe->acq_common_descriptor.command &
 449                 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
 450
 451         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
 452         if (unlikely(!comp_ctx)) {
 453                 ena_trc_err("comp_ctx is NULL. Changing the admin queue running state\n");
 454                 admin_queue->running_state = false;
 455                 return;
 456         }
 457
 458         comp_ctx->status = ENA_CMD_COMPLETED;
 459         comp_ctx->comp_status = cqe->acq_common_descriptor.status;
 460
 461         if (comp_ctx->user_cqe)
 462                 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
 463
 464         if (!admin_queue->polling)
 465                 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
 466 }
 467
 468 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
 469 {
 470         struct ena_admin_acq_entry *cqe = NULL;
 471         u16 comp_num = 0;
 472         u16 head_masked;
 473         u8 phase;
 474
 475         head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
 476         phase = admin_queue->cq.phase;
 477
 478         cqe = &admin_queue->cq.entries[head_masked];
 479
 480         /* Go over all the completions */
 481         while ((READ_ONCE8(cqe->acq_common_descriptor.flags) &
 482                         ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
 483                 /* Do not read the rest of the completion entry before the
 484                  * phase bit was validated
 485                  */
 486                 dma_rmb();
 487                 ena_com_handle_single_admin_completion(admin_queue, cqe);
 488
 489                 head_masked++;
 490                 comp_num++;
 491                 if (unlikely(head_masked == admin_queue->q_depth)) {
 492                         head_masked = 0;
 493                         phase = !phase;
 494                 }
 495
 496                 cqe = &admin_queue->cq.entries[head_masked];
 497         }
 498
 499         admin_queue->cq.head += comp_num;
 500         admin_queue->cq.phase = phase;
 501         admin_queue->sq.head += comp_num;
 502         admin_queue->stats.completed_cmd += comp_num;
 503 }
 504
 505 static int ena_com_comp_status_to_errno(u8 comp_status)
 506 {
 507         if (unlikely(comp_status != 0))
 508                 ena_trc_err("admin command failed[%u]\n", comp_status);
 509
 510         switch (comp_status) {
 511         case ENA_ADMIN_SUCCESS:
 512                 return ENA_COM_OK;
 513         case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
 514                 return ENA_COM_NO_MEM;
 515         case ENA_ADMIN_UNSUPPORTED_OPCODE:
 516                 return ENA_COM_UNSUPPORTED;
 517         case ENA_ADMIN_BAD_OPCODE:
 518         case ENA_ADMIN_MALFORMED_REQUEST:
 519         case ENA_ADMIN_ILLEGAL_PARAMETER:
 520         case ENA_ADMIN_UNKNOWN_ERROR:
 521                 return ENA_COM_INVAL;
 522         case ENA_ADMIN_RESOURCE_BUSY:
 523                 return ENA_COM_TRY_AGAIN;
 524         }
 525
 526         return ENA_COM_INVAL;
 527 }
 528
 529 static void ena_delay_exponential_backoff_us(u32 exp, u32 delay_us)
 530 {
 531         delay_us = ENA_MAX32(ENA_MIN_ADMIN_POLL_US, delay_us);
 532         delay_us = ENA_MIN32(delay_us * (1U << exp), ENA_MAX_ADMIN_POLL_US);
 533         ENA_USLEEP(delay_us);
 534 }
 535
 536 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
 537                                                      struct ena_com_admin_queue *admin_queue)
 538 {
 539         unsigned long flags = 0;
 540         ena_time_t timeout;
 541         int ret;
 542         u32 exp = 0;
 543
 544         timeout = ENA_GET_SYSTEM_TIMEOUT(admin_queue->completion_timeout);
 545
 546         while (1) {
 547                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 548                 ena_com_handle_admin_completion(admin_queue);
 549                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 550
 551                 if (comp_ctx->status != ENA_CMD_SUBMITTED)
 552                         break;
 553
 554                 if (ENA_TIME_EXPIRE(timeout)) {
 555                         ena_trc_err("Wait for completion (polling) timeout\n");
 556                         /* ENA didn't have any completion */
 557                         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 558                         admin_queue->stats.no_completion++;
 559                         admin_queue->running_state = false;
 560                         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 561
 562                         ret = ENA_COM_TIMER_EXPIRED;
 563                         goto err;
 564                 }
 565
 566                 ena_delay_exponential_backoff_us(exp++,
 567                                                  admin_queue->ena_dev->ena_min_poll_delay_us);
 568         }
 569
 570         if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
 571                 ena_trc_err("Command was aborted\n");
 572                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 573                 admin_queue->stats.aborted_cmd++;
 574                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 575                 ret = ENA_COM_NO_DEVICE;
 576                 goto err;
 577         }
 578
 579         ENA_WARN(comp_ctx->status != ENA_CMD_COMPLETED,
 580                  "Invalid comp status %d\n", comp_ctx->status);
 581
 582         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 583 err:
 584         comp_ctxt_release(admin_queue, comp_ctx);
 585         return ret;
 586 }
 587
 588 /**
 589  * Set the LLQ configurations of the firmware
 590  *
 591  * The driver provides only the enabled feature values to the device,
 592  * which in turn, checks if they are supported.
 593  */
 594 static int ena_com_set_llq(struct ena_com_dev *ena_dev)
 595 {
 596         struct ena_com_admin_queue *admin_queue;
 597         struct ena_admin_set_feat_cmd cmd;
 598         struct ena_admin_set_feat_resp resp;
 599         struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
 600         int ret;
 601
 602         memset(&cmd, 0x0, sizeof(cmd));
 603         admin_queue = &ena_dev->admin_queue;
 604
 605         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
 606         cmd.feat_common.feature_id = ENA_ADMIN_LLQ;
 607
 608         cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl;
 609         cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl;
 610         cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header;
 611         cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl;
 612
 613         if (llq_info->disable_meta_caching)
 614                 cmd.u.llq.accel_mode.u.set.enabled_flags |=
 615                         BIT(ENA_ADMIN_DISABLE_META_CACHING);
 616
 617         if (llq_info->max_entries_in_tx_burst)
 618                 cmd.u.llq.accel_mode.u.set.enabled_flags |=
 619                         BIT(ENA_ADMIN_LIMIT_TX_BURST);
 620
 621         ret = ena_com_execute_admin_command(admin_queue,
 622                                             (struct ena_admin_aq_entry *)&cmd,
 623                                             sizeof(cmd),
 624                                             (struct ena_admin_acq_entry *)&resp,
 625                                             sizeof(resp));
 626
 627         if (unlikely(ret))
 628                 ena_trc_err("Failed to set LLQ configurations: %d\n", ret);
 629
 630         return ret;
 631 }
 632
 633 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
 634                                    struct ena_admin_feature_llq_desc *llq_features,
 635                                    struct ena_llq_configurations *llq_default_cfg)
 636 {
 637         struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
 638         u16 supported_feat;
 639         int rc;
 640
 641         memset(llq_info, 0, sizeof(*llq_info));
 642
 643         supported_feat = llq_features->header_location_ctrl_supported;
 644
 645         if (likely(supported_feat & llq_default_cfg->llq_header_location)) {
 646                 llq_info->header_location_ctrl =
 647                         llq_default_cfg->llq_header_location;
 648         } else {
 649                 ena_trc_err("Invalid header location control, supported: 0x%x\n",
 650                             supported_feat);
 651                 return -EINVAL;
 652         }
 653
 654         if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) {
 655                 supported_feat = llq_features->descriptors_stride_ctrl_supported;
 656                 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) {
 657                         llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl;
 658                 } else  {
 659                         if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) {
 660                                 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
 661                         } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) {
 662                                 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY;
 663                         } else {
 664                                 ena_trc_err("Invalid desc_stride_ctrl, supported: 0x%x\n",
 665                                             supported_feat);
 666                                 return -EINVAL;
 667                         }
 668
 669                         ena_trc_err("Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 670                                     llq_default_cfg->llq_stride_ctrl,
 671                                     supported_feat,
 672                                     llq_info->desc_stride_ctrl);
 673                 }
 674         } else {
 675                 llq_info->desc_stride_ctrl = 0;
 676         }
 677
 678         supported_feat = llq_features->entry_size_ctrl_supported;
 679         if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) {
 680                 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size;
 681                 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value;
 682         } else {
 683                 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) {
 684                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
 685                         llq_info->desc_list_entry_size = 128;
 686                 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) {
 687                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B;
 688                         llq_info->desc_list_entry_size = 192;
 689                 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) {
 690                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B;
 691                         llq_info->desc_list_entry_size = 256;
 692                 } else {
 693                         ena_trc_err("Invalid entry_size_ctrl, supported: 0x%x\n", supported_feat);
 694                         return -EINVAL;
 695                 }
 696
 697                 ena_trc_err("Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 698                             llq_default_cfg->llq_ring_entry_size,
 699                             supported_feat,
 700                             llq_info->desc_list_entry_size);
 701         }
 702         if (unlikely(llq_info->desc_list_entry_size & 0x7)) {
 703                 /* The desc list entry size should be whole multiply of 8
 704                  * This requirement comes from __iowrite64_copy()
 705                  */
 706                 ena_trc_err("illegal entry size %d\n",
 707                             llq_info->desc_list_entry_size);
 708                 return -EINVAL;
 709         }
 710
 711         if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)
 712                 llq_info->descs_per_entry = llq_info->desc_list_entry_size /
 713                         sizeof(struct ena_eth_io_tx_desc);
 714         else
 715                 llq_info->descs_per_entry = 1;
 716
 717         supported_feat = llq_features->desc_num_before_header_supported;
 718         if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) {
 719                 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header;
 720         } else {
 721                 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) {
 722                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
 723                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) {
 724                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1;
 725                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) {
 726                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4;
 727                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) {
 728                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8;
 729                 } else {
 730                         ena_trc_err("Invalid descs_num_before_header, supported: 0x%x\n",
 731                                     supported_feat);
 732                         return -EINVAL;
 733                 }
 734
 735                 ena_trc_err("Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 736                             llq_default_cfg->llq_num_decs_before_header,
 737                             supported_feat,
 738                             llq_info->descs_num_before_header);
 739         }
 740         /* Check for accelerated queue supported */
 741         llq_info->disable_meta_caching =
 742                 llq_features->accel_mode.u.get.supported_flags &
 743                 BIT(ENA_ADMIN_DISABLE_META_CACHING);
 744
 745         if (llq_features->accel_mode.u.get.supported_flags & BIT(ENA_ADMIN_LIMIT_TX_BURST))
 746                 llq_info->max_entries_in_tx_burst =
 747                         llq_features->accel_mode.u.get.max_tx_burst_size /
 748                         llq_default_cfg->llq_ring_entry_size_value;
 749
 750         rc = ena_com_set_llq(ena_dev);
 751         if (rc)
 752                 ena_trc_err("Cannot set LLQ configuration: %d\n", rc);
 753
 754         return rc;
 755 }
 756
 757 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
 758                                                         struct ena_com_admin_queue *admin_queue)
 759 {
 760         unsigned long flags = 0;
 761         int ret;
 762
 763         ENA_WAIT_EVENT_WAIT(comp_ctx->wait_event,
 764                             admin_queue->completion_timeout);
 765
 766         /* In case the command wasn't completed find out the root cause.
 767          * There might be 2 kinds of errors
 768          * 1) No completion (timeout reached)
 769          * 2) There is completion but the device didn't get any msi-x interrupt.
 770          */
 771         if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
 772                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 773                 ena_com_handle_admin_completion(admin_queue);
 774                 admin_queue->stats.no_completion++;
 775                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 776
 777                 if (comp_ctx->status == ENA_CMD_COMPLETED) {
 778                         ena_trc_err("The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n",
 779                                     comp_ctx->cmd_opcode, admin_queue->auto_polling ? "ON" : "OFF");
 780                         /* Check if fallback to polling is enabled */
 781                         if (admin_queue->auto_polling)
 782                                 admin_queue->polling = true;
 783                 } else {
 784                         ena_trc_err("The ena device didn't send a completion for the admin cmd %d status %d\n",
 785                                     comp_ctx->cmd_opcode, comp_ctx->status);
 786                 }
 787                 /* Check if shifted to polling mode.
 788                  * This will happen if there is a completion without an interrupt
 789                  * and autopolling mode is enabled. Continuing normal execution in such case
 790                  */
 791                 if (!admin_queue->polling) {
 792                         admin_queue->running_state = false;
 793                         ret = ENA_COM_TIMER_EXPIRED;
 794                         goto err;
 795                 }
 796         }
 797
 798         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 799 err:
 800         comp_ctxt_release(admin_queue, comp_ctx);
 801         return ret;
 802 }
 803
 804 /* This method read the hardware device register through posting writes
 805  * and waiting for response
 806  * On timeout the function will return ENA_MMIO_READ_TIMEOUT
 807  */
 808 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
 809 {
 810         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
 811         volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
 812                 mmio_read->read_resp;
 813         u32 mmio_read_reg, ret, i;
 814         unsigned long flags = 0;
 815         u32 timeout = mmio_read->reg_read_to;
 816
 817         ENA_MIGHT_SLEEP();
 818
 819         if (timeout == 0)
 820                 timeout = ENA_REG_READ_TIMEOUT;
 821
 822         /* If readless is disabled, perform regular read */
 823         if (!mmio_read->readless_supported)
 824                 return ENA_REG_READ32(ena_dev->bus, ena_dev->reg_bar + offset);
 825
 826         ENA_SPINLOCK_LOCK(mmio_read->lock, flags);
 827         mmio_read->seq_num++;
 828
 829         read_resp->req_id = mmio_read->seq_num + 0xDEAD;
 830         mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
 831                         ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
 832         mmio_read_reg |= mmio_read->seq_num &
 833                         ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
 834
 835         ENA_REG_WRITE32(ena_dev->bus, mmio_read_reg,
 836                         ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
 837
 838         for (i = 0; i < timeout; i++) {
 839                 if (READ_ONCE16(read_resp->req_id) == mmio_read->seq_num)
 840                         break;
 841
 842                 ENA_UDELAY(1);
 843         }
 844
 845         if (unlikely(i == timeout)) {
 846                 ena_trc_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n",
 847                             mmio_read->seq_num,
 848                             offset,
 849                             read_resp->req_id,
 850                             read_resp->reg_off);
 851                 ret = ENA_MMIO_READ_TIMEOUT;
 852                 goto err;
 853         }
 854
 855         if (read_resp->reg_off != offset) {
 856                 ena_trc_err("Read failure: wrong offset provided\n");
 857                 ret = ENA_MMIO_READ_TIMEOUT;
 858         } else {
 859                 ret = read_resp->reg_val;
 860         }
 861 err:
 862         ENA_SPINLOCK_UNLOCK(mmio_read->lock, flags);
 863
 864         return ret;
 865 }
 866
 867 /* There are two types to wait for completion.
 868  * Polling mode - wait until the completion is available.
 869  * Async mode - wait on wait queue until the completion is ready
 870  * (or the timeout expired).
 871  * It is expected that the IRQ called ena_com_handle_admin_completion
 872  * to mark the completions.
 873  */
 874 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
 875                                              struct ena_com_admin_queue *admin_queue)
 876 {
 877         if (admin_queue->polling)
 878                 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
 879                                                                  admin_queue);
 880
 881         return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
 882                                                             admin_queue);
 883 }
 884
 885 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
 886                                  struct ena_com_io_sq *io_sq)
 887 {
 888         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
 889         struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
 890         struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
 891         u8 direction;
 892         int ret;
 893
 894         memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
 895
 896         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
 897                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
 898         else
 899                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
 900
 901         destroy_cmd.sq.sq_identity |= (direction <<
 902                 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
 903                 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
 904
 905         destroy_cmd.sq.sq_idx = io_sq->idx;
 906         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
 907
 908         ret = ena_com_execute_admin_command(admin_queue,
 909                                             (struct ena_admin_aq_entry *)&destroy_cmd,
 910                                             sizeof(destroy_cmd),
 911                                             (struct ena_admin_acq_entry *)&destroy_resp,
 912                                             sizeof(destroy_resp));
 913
 914         if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
 915                 ena_trc_err("failed to destroy io sq error: %d\n", ret);
 916
 917         return ret;
 918 }
 919
 920 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
 921                                   struct ena_com_io_sq *io_sq,
 922                                   struct ena_com_io_cq *io_cq)
 923 {
 924         size_t size;
 925
 926         if (io_cq->cdesc_addr.virt_addr) {
 927                 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 928
 929                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
 930                                       size,
 931                                       io_cq->cdesc_addr.virt_addr,
 932                                       io_cq->cdesc_addr.phys_addr,
 933                                       io_cq->cdesc_addr.mem_handle);
 934
 935                 io_cq->cdesc_addr.virt_addr = NULL;
 936         }
 937
 938         if (io_sq->desc_addr.virt_addr) {
 939                 size = io_sq->desc_entry_size * io_sq->q_depth;
 940
 941                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
 942                                       size,
 943                                       io_sq->desc_addr.virt_addr,
 944                                       io_sq->desc_addr.phys_addr,
 945                                       io_sq->desc_addr.mem_handle);
 946
 947                 io_sq->desc_addr.virt_addr = NULL;
 948         }
 949
 950         if (io_sq->bounce_buf_ctrl.base_buffer) {
 951                 ENA_MEM_FREE(ena_dev->dmadev,
 952                              io_sq->bounce_buf_ctrl.base_buffer,
 953                              (io_sq->llq_info.desc_list_entry_size * ENA_COM_BOUNCE_BUFFER_CNTRL_CNT));
 954                 io_sq->bounce_buf_ctrl.base_buffer = NULL;
 955         }
 956 }
 957
 958 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
 959                                 u16 exp_state)
 960 {
 961         u32 val, exp = 0;
 962         ena_time_t timeout_stamp;
 963
 964         /* Convert timeout from resolution of 100ms to us resolution. */
 965         timeout_stamp = ENA_GET_SYSTEM_TIMEOUT(100 * 1000 * timeout);
 966
 967         while (1) {
 968                 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
 969
 970                 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
 971                         ena_trc_err("Reg read timeout occurred\n");
 972                         return ENA_COM_TIMER_EXPIRED;
 973                 }
 974
 975                 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
 976                         exp_state)
 977                         return 0;
 978
 979                 if (ENA_TIME_EXPIRE(timeout_stamp))
 980                         return ENA_COM_TIMER_EXPIRED;
 981
 982                 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
 983         }
 984 }
 985
 986 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
 987                                                enum ena_admin_aq_feature_id feature_id)
 988 {
 989         u32 feature_mask = 1 << feature_id;
 990
 991         /* Device attributes is always supported */
 992         if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
 993             !(ena_dev->supported_features & feature_mask))
 994                 return false;
 995
 996         return true;
 997 }
 998
 999 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
1000                                   struct ena_admin_get_feat_resp *get_resp,
1001                                   enum ena_admin_aq_feature_id feature_id,
1002                                   dma_addr_t control_buf_dma_addr,
1003                                   u32 control_buff_size,
1004                                   u8 feature_ver)
1005 {
1006         struct ena_com_admin_queue *admin_queue;
1007         struct ena_admin_get_feat_cmd get_cmd;
1008         int ret;
1009
1010         if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
1011                 ena_trc_dbg("Feature %d isn't supported\n", feature_id);
1012                 return ENA_COM_UNSUPPORTED;
1013         }
1014
1015         memset(&get_cmd, 0x0, sizeof(get_cmd));
1016         admin_queue = &ena_dev->admin_queue;
1017
1018         get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
1019
1020         if (control_buff_size)
1021                 get_cmd.aq_common_descriptor.flags =
1022                         ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1023         else
1024                 get_cmd.aq_common_descriptor.flags = 0;
1025
1026         ret = ena_com_mem_addr_set(ena_dev,
1027                                    &get_cmd.control_buffer.address,
1028                                    control_buf_dma_addr);
1029         if (unlikely(ret)) {
1030                 ena_trc_err("memory address set failed\n");
1031                 return ret;
1032         }
1033
1034         get_cmd.control_buffer.length = control_buff_size;
1035         get_cmd.feat_common.feature_version = feature_ver;
1036         get_cmd.feat_common.feature_id = feature_id;
1037
1038         ret = ena_com_execute_admin_command(admin_queue,
1039                                             (struct ena_admin_aq_entry *)
1040                                             &get_cmd,
1041                                             sizeof(get_cmd),
1042                                             (struct ena_admin_acq_entry *)
1043                                             get_resp,
1044                                             sizeof(*get_resp));
1045
1046         if (unlikely(ret))
1047                 ena_trc_err("Failed to submit get_feature command %d error: %d\n",
1048                             feature_id, ret);
1049
1050         return ret;
1051 }
1052
1053 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
1054                                struct ena_admin_get_feat_resp *get_resp,
1055                                enum ena_admin_aq_feature_id feature_id,
1056                                u8 feature_ver)
1057 {
1058         return ena_com_get_feature_ex(ena_dev,
1059                                       get_resp,
1060                                       feature_id,
1061                                       0,
1062                                       0,
1063                                       feature_ver);
1064 }
1065
1066 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev)
1067 {
1068         struct ena_admin_feature_rss_flow_hash_control *hash_key =
1069                 (ena_dev->rss).hash_key;
1070
1071         ENA_RSS_FILL_KEY(&hash_key->key, sizeof(hash_key->key));
1072         /* The key is stored in the device in uint32_t array
1073          * as well as the API requires the key to be passed in this
1074          * format. Thus the size of our array should be divided by 4
1075          */
1076         hash_key->keys_num = sizeof(hash_key->key) / sizeof(uint32_t);
1077 }
1078
1079 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
1080 {
1081         struct ena_rss *rss = &ena_dev->rss;
1082
1083         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1084                                sizeof(*rss->hash_key),
1085                                rss->hash_key,
1086                                rss->hash_key_dma_addr,
1087                                rss->hash_key_mem_handle);
1088
1089         if (unlikely(!rss->hash_key))
1090                 return ENA_COM_NO_MEM;
1091
1092         return 0;
1093 }
1094
1095 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
1096 {
1097         struct ena_rss *rss = &ena_dev->rss;
1098
1099         if (rss->hash_key)
1100                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1101                                       sizeof(*rss->hash_key),
1102                                       rss->hash_key,
1103                                       rss->hash_key_dma_addr,
1104                                       rss->hash_key_mem_handle);
1105         rss->hash_key = NULL;
1106 }
1107
1108 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
1109 {
1110         struct ena_rss *rss = &ena_dev->rss;
1111
1112         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1113                                sizeof(*rss->hash_ctrl),
1114                                rss->hash_ctrl,
1115                                rss->hash_ctrl_dma_addr,
1116                                rss->hash_ctrl_mem_handle);
1117
1118         if (unlikely(!rss->hash_ctrl))
1119                 return ENA_COM_NO_MEM;
1120
1121         return 0;
1122 }
1123
1124 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
1125 {
1126         struct ena_rss *rss = &ena_dev->rss;
1127
1128         if (rss->hash_ctrl)
1129                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1130                                       sizeof(*rss->hash_ctrl),
1131                                       rss->hash_ctrl,
1132                                       rss->hash_ctrl_dma_addr,
1133                                       rss->hash_ctrl_mem_handle);
1134         rss->hash_ctrl = NULL;
1135 }
1136
1137 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
1138                                            u16 log_size)
1139 {
1140         struct ena_rss *rss = &ena_dev->rss;
1141         struct ena_admin_get_feat_resp get_resp;
1142         size_t tbl_size;
1143         int ret;
1144
1145         ret = ena_com_get_feature(ena_dev, &get_resp,
1146                                   ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
1147         if (unlikely(ret))
1148                 return ret;
1149
1150         if ((get_resp.u.ind_table.min_size > log_size) ||
1151             (get_resp.u.ind_table.max_size < log_size)) {
1152                 ena_trc_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
1153                             1 << log_size,
1154                             1 << get_resp.u.ind_table.min_size,
1155                             1 << get_resp.u.ind_table.max_size);
1156                 return ENA_COM_INVAL;
1157         }
1158
1159         tbl_size = (1ULL << log_size) *
1160                 sizeof(struct ena_admin_rss_ind_table_entry);
1161
1162         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1163                              tbl_size,
1164                              rss->rss_ind_tbl,
1165                              rss->rss_ind_tbl_dma_addr,
1166                              rss->rss_ind_tbl_mem_handle);
1167         if (unlikely(!rss->rss_ind_tbl))
1168                 goto mem_err1;
1169
1170         tbl_size = (1ULL << log_size) * sizeof(u16);
1171         rss->host_rss_ind_tbl =
1172                 ENA_MEM_ALLOC(ena_dev->dmadev, tbl_size);
1173         if (unlikely(!rss->host_rss_ind_tbl))
1174                 goto mem_err2;
1175
1176         rss->tbl_log_size = log_size;
1177
1178         return 0;
1179
1180 mem_err2:
1181         tbl_size = (1ULL << log_size) *
1182                 sizeof(struct ena_admin_rss_ind_table_entry);
1183
1184         ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1185                               tbl_size,
1186                               rss->rss_ind_tbl,
1187                               rss->rss_ind_tbl_dma_addr,
1188                               rss->rss_ind_tbl_mem_handle);
1189         rss->rss_ind_tbl = NULL;
1190 mem_err1:
1191         rss->tbl_log_size = 0;
1192         return ENA_COM_NO_MEM;
1193 }
1194
1195 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
1196 {
1197         struct ena_rss *rss = &ena_dev->rss;
1198         size_t tbl_size = (1ULL << rss->tbl_log_size) *
1199                 sizeof(struct ena_admin_rss_ind_table_entry);
1200
1201         if (rss->rss_ind_tbl)
1202                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1203                                       tbl_size,
1204                                       rss->rss_ind_tbl,
1205                                       rss->rss_ind_tbl_dma_addr,
1206                                       rss->rss_ind_tbl_mem_handle);
1207         rss->rss_ind_tbl = NULL;
1208
1209         if (rss->host_rss_ind_tbl)
1210                 ENA_MEM_FREE(ena_dev->dmadev,
1211                              rss->host_rss_ind_tbl,
1212                              ((1ULL << rss->tbl_log_size) * sizeof(u16)));
1213         rss->host_rss_ind_tbl = NULL;
1214 }
1215
1216 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
1217                                 struct ena_com_io_sq *io_sq, u16 cq_idx)
1218 {
1219         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1220         struct ena_admin_aq_create_sq_cmd create_cmd;
1221         struct ena_admin_acq_create_sq_resp_desc cmd_completion;
1222         u8 direction;
1223         int ret;
1224
1225         memset(&create_cmd, 0x0, sizeof(create_cmd));
1226
1227         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
1228
1229         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1230                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
1231         else
1232                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
1233
1234         create_cmd.sq_identity |= (direction <<
1235                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1236                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1237
1238         create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1239                 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1240
1241         create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1242                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1243                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1244
1245         create_cmd.sq_caps_3 |=
1246                 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1247
1248         create_cmd.cq_idx = cq_idx;
1249         create_cmd.sq_depth = io_sq->q_depth;
1250
1251         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1252                 ret = ena_com_mem_addr_set(ena_dev,
1253                                            &create_cmd.sq_ba,
1254                                            io_sq->desc_addr.phys_addr);
1255                 if (unlikely(ret)) {
1256                         ena_trc_err("memory address set failed\n");
1257                         return ret;
1258                 }
1259         }
1260
1261         ret = ena_com_execute_admin_command(admin_queue,
1262                                             (struct ena_admin_aq_entry *)&create_cmd,
1263                                             sizeof(create_cmd),
1264                                             (struct ena_admin_acq_entry *)&cmd_completion,
1265                                             sizeof(cmd_completion));
1266         if (unlikely(ret)) {
1267                 ena_trc_err("Failed to create IO SQ. error: %d\n", ret);
1268                 return ret;
1269         }
1270
1271         io_sq->idx = cmd_completion.sq_idx;
1272
1273         io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1274                 (uintptr_t)cmd_completion.sq_doorbell_offset);
1275
1276         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1277                 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1278                                 + cmd_completion.llq_headers_offset);
1279
1280                 io_sq->desc_addr.pbuf_dev_addr =
1281                         (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1282                         cmd_completion.llq_descriptors_offset);
1283         }
1284
1285         ena_trc_dbg("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1286
1287         return ret;
1288 }
1289
1290 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1291 {
1292         struct ena_rss *rss = &ena_dev->rss;
1293         struct ena_com_io_sq *io_sq;
1294         u16 qid;
1295         int i;
1296
1297         for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1298                 qid = rss->host_rss_ind_tbl[i];
1299                 if (qid >= ENA_TOTAL_NUM_QUEUES)
1300                         return ENA_COM_INVAL;
1301
1302                 io_sq = &ena_dev->io_sq_queues[qid];
1303
1304                 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1305                         return ENA_COM_INVAL;
1306
1307                 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1308         }
1309
1310         return 0;
1311 }
1312
1313 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1314                                                  u16 intr_delay_resolution)
1315 {
1316         u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution;
1317
1318         if (unlikely(!intr_delay_resolution)) {
1319                 ena_trc_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1320                 intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION;
1321         }
1322
1323         /* update Rx */
1324         ena_dev->intr_moder_rx_interval =
1325                 ena_dev->intr_moder_rx_interval *
1326                 prev_intr_delay_resolution /
1327                 intr_delay_resolution;
1328
1329         /* update Tx */
1330         ena_dev->intr_moder_tx_interval =
1331                 ena_dev->intr_moder_tx_interval *
1332                 prev_intr_delay_resolution /
1333                 intr_delay_resolution;
1334
1335         ena_dev->intr_delay_resolution = intr_delay_resolution;
1336 }
1337
1338 /*****************************************************************************/
1339 /*******************************      API       ******************************/
1340 /*****************************************************************************/
1341
1342 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1343                                   struct ena_admin_aq_entry *cmd,
1344                                   size_t cmd_size,
1345                                   struct ena_admin_acq_entry *comp,
1346                                   size_t comp_size)
1347 {
1348         struct ena_comp_ctx *comp_ctx;
1349         int ret;
1350
1351         comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1352                                             comp, comp_size);
1353         if (IS_ERR(comp_ctx)) {
1354                 if (comp_ctx == ERR_PTR(ENA_COM_NO_DEVICE))
1355                         ena_trc_dbg("Failed to submit command [%ld]\n",
1356                                     PTR_ERR(comp_ctx));
1357                 else
1358                         ena_trc_err("Failed to submit command [%ld]\n",
1359                                     PTR_ERR(comp_ctx));
1360
1361                 return PTR_ERR(comp_ctx);
1362         }
1363
1364         ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1365         if (unlikely(ret)) {
1366                 if (admin_queue->running_state)
1367                         ena_trc_err("Failed to process command. ret = %d\n",
1368                                     ret);
1369                 else
1370                         ena_trc_dbg("Failed to process command. ret = %d\n",
1371                                     ret);
1372         }
1373         return ret;
1374 }
1375
1376 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1377                          struct ena_com_io_cq *io_cq)
1378 {
1379         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1380         struct ena_admin_aq_create_cq_cmd create_cmd;
1381         struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1382         int ret;
1383
1384         memset(&create_cmd, 0x0, sizeof(create_cmd));
1385
1386         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1387
1388         create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1389                 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1390         create_cmd.cq_caps_1 |=
1391                 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1392
1393         create_cmd.msix_vector = io_cq->msix_vector;
1394         create_cmd.cq_depth = io_cq->q_depth;
1395
1396         ret = ena_com_mem_addr_set(ena_dev,
1397                                    &create_cmd.cq_ba,
1398                                    io_cq->cdesc_addr.phys_addr);
1399         if (unlikely(ret)) {
1400                 ena_trc_err("memory address set failed\n");
1401                 return ret;
1402         }
1403
1404         ret = ena_com_execute_admin_command(admin_queue,
1405                                             (struct ena_admin_aq_entry *)&create_cmd,
1406                                             sizeof(create_cmd),
1407                                             (struct ena_admin_acq_entry *)&cmd_completion,
1408                                             sizeof(cmd_completion));
1409         if (unlikely(ret)) {
1410                 ena_trc_err("Failed to create IO CQ. error: %d\n", ret);
1411                 return ret;
1412         }
1413
1414         io_cq->idx = cmd_completion.cq_idx;
1415
1416         io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1417                 cmd_completion.cq_interrupt_unmask_register_offset);
1418
1419         if (cmd_completion.cq_head_db_register_offset)
1420                 io_cq->cq_head_db_reg =
1421                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1422                         cmd_completion.cq_head_db_register_offset);
1423
1424         if (cmd_completion.numa_node_register_offset)
1425                 io_cq->numa_node_cfg_reg =
1426                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1427                         cmd_completion.numa_node_register_offset);
1428
1429         ena_trc_dbg("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1430
1431         return ret;
1432 }
1433
1434 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1435                             struct ena_com_io_sq **io_sq,
1436                             struct ena_com_io_cq **io_cq)
1437 {
1438         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1439                 ena_trc_err("Invalid queue number %d but the max is %d\n",
1440                             qid, ENA_TOTAL_NUM_QUEUES);
1441                 return ENA_COM_INVAL;
1442         }
1443
1444         *io_sq = &ena_dev->io_sq_queues[qid];
1445         *io_cq = &ena_dev->io_cq_queues[qid];
1446
1447         return 0;
1448 }
1449
1450 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1451 {
1452         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1453         struct ena_comp_ctx *comp_ctx;
1454         u16 i;
1455
1456         if (!admin_queue->comp_ctx)
1457                 return;
1458
1459         for (i = 0; i < admin_queue->q_depth; i++) {
1460                 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1461                 if (unlikely(!comp_ctx))
1462                         break;
1463
1464                 comp_ctx->status = ENA_CMD_ABORTED;
1465
1466                 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
1467         }
1468 }
1469
1470 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1471 {
1472         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1473         unsigned long flags = 0;
1474         u32 exp = 0;
1475
1476         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1477         while (ATOMIC32_READ(&admin_queue->outstanding_cmds) != 0) {
1478                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1479                 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
1480                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1481         }
1482         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1483 }
1484
1485 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1486                           struct ena_com_io_cq *io_cq)
1487 {
1488         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1489         struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1490         struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1491         int ret;
1492
1493         memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1494
1495         destroy_cmd.cq_idx = io_cq->idx;
1496         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1497
1498         ret = ena_com_execute_admin_command(admin_queue,
1499                                             (struct ena_admin_aq_entry *)&destroy_cmd,
1500                                             sizeof(destroy_cmd),
1501                                             (struct ena_admin_acq_entry *)&destroy_resp,
1502                                             sizeof(destroy_resp));
1503
1504         if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
1505                 ena_trc_err("Failed to destroy IO CQ. error: %d\n", ret);
1506
1507         return ret;
1508 }
1509
1510 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1511 {
1512         return ena_dev->admin_queue.running_state;
1513 }
1514
1515 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1516 {
1517         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1518         unsigned long flags = 0;
1519
1520         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1521         ena_dev->admin_queue.running_state = state;
1522         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1523 }
1524
1525 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1526 {
1527         u16 depth = ena_dev->aenq.q_depth;
1528
1529         ENA_WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1530
1531         /* Init head_db to mark that all entries in the queue
1532          * are initially available
1533          */
1534         ENA_REG_WRITE32(ena_dev->bus, depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1535 }
1536
1537 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1538 {
1539         struct ena_com_admin_queue *admin_queue;
1540         struct ena_admin_set_feat_cmd cmd;
1541         struct ena_admin_set_feat_resp resp;
1542         struct ena_admin_get_feat_resp get_resp;
1543         int ret;
1544
1545         ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0);
1546         if (ret) {
1547                 ena_trc_info("Can't get aenq configuration\n");
1548                 return ret;
1549         }
1550
1551         if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1552                 ena_trc_warn("Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n",
1553                              get_resp.u.aenq.supported_groups,
1554                              groups_flag);
1555                 return ENA_COM_UNSUPPORTED;
1556         }
1557
1558         memset(&cmd, 0x0, sizeof(cmd));
1559         admin_queue = &ena_dev->admin_queue;
1560
1561         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1562         cmd.aq_common_descriptor.flags = 0;
1563         cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1564         cmd.u.aenq.enabled_groups = groups_flag;
1565
1566         ret = ena_com_execute_admin_command(admin_queue,
1567                                             (struct ena_admin_aq_entry *)&cmd,
1568                                             sizeof(cmd),
1569                                             (struct ena_admin_acq_entry *)&resp,
1570                                             sizeof(resp));
1571
1572         if (unlikely(ret))
1573                 ena_trc_err("Failed to config AENQ ret: %d\n", ret);
1574
1575         return ret;
1576 }
1577
1578 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1579 {
1580         u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1581         int width;
1582
1583         if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1584                 ena_trc_err("Reg read timeout occurred\n");
1585                 return ENA_COM_TIMER_EXPIRED;
1586         }
1587
1588         width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1589                 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1590
1591         ena_trc_dbg("ENA dma width: %d\n", width);
1592
1593         if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1594                 ena_trc_err("DMA width illegal value: %d\n", width);
1595                 return ENA_COM_INVAL;
1596         }
1597
1598         ena_dev->dma_addr_bits = width;
1599
1600         return width;
1601 }
1602
1603 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1604 {
1605         u32 ver;
1606         u32 ctrl_ver;
1607         u32 ctrl_ver_masked;
1608
1609         /* Make sure the ENA version and the controller version are at least
1610          * as the driver expects
1611          */
1612         ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1613         ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1614                                           ENA_REGS_CONTROLLER_VERSION_OFF);
1615
1616         if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1617                      (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1618                 ena_trc_err("Reg read timeout occurred\n");
1619                 return ENA_COM_TIMER_EXPIRED;
1620         }
1621
1622         ena_trc_info("ena device version: %d.%d\n",
1623                      (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1624                      ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1625                      ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1626
1627         ena_trc_info("ena controller version: %d.%d.%d implementation version %d\n",
1628                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK)
1629                      >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1630                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK)
1631                      >> ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1632                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1633                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1634                      ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1635
1636         ctrl_ver_masked =
1637                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1638                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1639                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1640
1641         /* Validate the ctrl version without the implementation ID */
1642         if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1643                 ena_trc_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1644                 return -1;
1645         }
1646
1647         return 0;
1648 }
1649
1650 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1651 {
1652         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1653         struct ena_com_admin_cq *cq = &admin_queue->cq;
1654         struct ena_com_admin_sq *sq = &admin_queue->sq;
1655         struct ena_com_aenq *aenq = &ena_dev->aenq;
1656         u16 size;
1657
1658         if (admin_queue->comp_ctx) {
1659                 ENA_WAIT_EVENT_DESTROY(admin_queue->comp_ctx->wait_event);
1660                 ENA_MEM_FREE(ena_dev->dmadev,
1661                              admin_queue->comp_ctx,
1662                              (admin_queue->q_depth * sizeof(struct ena_comp_ctx)));
1663         }
1664
1665         admin_queue->comp_ctx = NULL;
1666         size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1667         if (sq->entries)
1668                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries,
1669                                       sq->dma_addr, sq->mem_handle);
1670         sq->entries = NULL;
1671
1672         size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1673         if (cq->entries)
1674                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, cq->entries,
1675                                       cq->dma_addr, cq->mem_handle);
1676         cq->entries = NULL;
1677
1678         size = ADMIN_AENQ_SIZE(aenq->q_depth);
1679         if (ena_dev->aenq.entries)
1680                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, aenq->entries,
1681                                       aenq->dma_addr, aenq->mem_handle);
1682         aenq->entries = NULL;
1683         ENA_SPINLOCK_DESTROY(admin_queue->q_lock);
1684 }
1685
1686 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1687 {
1688         u32 mask_value = 0;
1689
1690         if (polling)
1691                 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1692
1693         ENA_REG_WRITE32(ena_dev->bus, mask_value,
1694                         ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1695         ena_dev->admin_queue.polling = polling;
1696 }
1697
1698 bool ena_com_get_admin_polling_mode(struct ena_com_dev * ena_dev)
1699 {
1700         return ena_dev->admin_queue.polling;
1701 }
1702
1703 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
1704                                          bool polling)
1705 {
1706         ena_dev->admin_queue.auto_polling = polling;
1707 }
1708
1709 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1710 {
1711         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1712
1713         ENA_SPINLOCK_INIT(mmio_read->lock);
1714         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1715                                sizeof(*mmio_read->read_resp),
1716                                mmio_read->read_resp,
1717                                mmio_read->read_resp_dma_addr,
1718                                mmio_read->read_resp_mem_handle);
1719         if (unlikely(!mmio_read->read_resp))
1720                 goto err;
1721
1722         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1723
1724         mmio_read->read_resp->req_id = 0x0;
1725         mmio_read->seq_num = 0x0;
1726         mmio_read->readless_supported = true;
1727
1728         return 0;
1729
1730 err:
1731                 ENA_SPINLOCK_DESTROY(mmio_read->lock);
1732                 return ENA_COM_NO_MEM;
1733 }
1734
1735 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1736 {
1737         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1738
1739         mmio_read->readless_supported = readless_supported;
1740 }
1741
1742 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1743 {
1744         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1745
1746         ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1747         ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1748
1749         ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1750                               sizeof(*mmio_read->read_resp),
1751                               mmio_read->read_resp,
1752                               mmio_read->read_resp_dma_addr,
1753                               mmio_read->read_resp_mem_handle);
1754
1755         mmio_read->read_resp = NULL;
1756         ENA_SPINLOCK_DESTROY(mmio_read->lock);
1757 }
1758
1759 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1760 {
1761         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1762         u32 addr_low, addr_high;
1763
1764         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1765         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1766
1767         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1768         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1769 }
1770
1771 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1772                        struct ena_aenq_handlers *aenq_handlers)
1773 {
1774         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1775         u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1776         int ret;
1777
1778         dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1779
1780         if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1781                 ena_trc_err("Reg read timeout occurred\n");
1782                 return ENA_COM_TIMER_EXPIRED;
1783         }
1784
1785         if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1786                 ena_trc_err("Device isn't ready, abort com init\n");
1787                 return ENA_COM_NO_DEVICE;
1788         }
1789
1790         admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1791
1792         admin_queue->bus = ena_dev->bus;
1793         admin_queue->q_dmadev = ena_dev->dmadev;
1794         admin_queue->polling = false;
1795         admin_queue->curr_cmd_id = 0;
1796
1797         ATOMIC32_SET(&admin_queue->outstanding_cmds, 0);
1798
1799         ENA_SPINLOCK_INIT(admin_queue->q_lock);
1800
1801         ret = ena_com_init_comp_ctxt(admin_queue);
1802         if (ret)
1803                 goto error;
1804
1805         ret = ena_com_admin_init_sq(admin_queue);
1806         if (ret)
1807                 goto error;
1808
1809         ret = ena_com_admin_init_cq(admin_queue);
1810         if (ret)
1811                 goto error;
1812
1813         admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1814                 ENA_REGS_AQ_DB_OFF);
1815
1816         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1817         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1818
1819         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1820         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1821
1822         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1823         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1824
1825         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1826         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1827
1828         aq_caps = 0;
1829         aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1830         aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1831                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1832                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1833
1834         acq_caps = 0;
1835         acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1836         acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1837                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1838                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1839
1840         ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1841         ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1842         ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1843         if (ret)
1844                 goto error;
1845
1846         admin_queue->ena_dev = ena_dev;
1847         admin_queue->running_state = true;
1848
1849         return 0;
1850 error:
1851         ena_com_admin_destroy(ena_dev);
1852
1853         return ret;
1854 }
1855
1856 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1857                             struct ena_com_create_io_ctx *ctx)
1858 {
1859         struct ena_com_io_sq *io_sq;
1860         struct ena_com_io_cq *io_cq;
1861         int ret;
1862
1863         if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1864                 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1865                             ctx->qid, ENA_TOTAL_NUM_QUEUES);
1866                 return ENA_COM_INVAL;
1867         }
1868
1869         io_sq = &ena_dev->io_sq_queues[ctx->qid];
1870         io_cq = &ena_dev->io_cq_queues[ctx->qid];
1871
1872         memset(io_sq, 0x0, sizeof(*io_sq));
1873         memset(io_cq, 0x0, sizeof(*io_cq));
1874
1875         /* Init CQ */
1876         io_cq->q_depth = ctx->queue_size;
1877         io_cq->direction = ctx->direction;
1878         io_cq->qid = ctx->qid;
1879
1880         io_cq->msix_vector = ctx->msix_vector;
1881
1882         io_sq->q_depth = ctx->queue_size;
1883         io_sq->direction = ctx->direction;
1884         io_sq->qid = ctx->qid;
1885
1886         io_sq->mem_queue_type = ctx->mem_queue_type;
1887
1888         if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1889                 /* header length is limited to 8 bits */
1890                 io_sq->tx_max_header_size =
1891                         ENA_MIN32(ena_dev->tx_max_header_size, SZ_256);
1892
1893         ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1894         if (ret)
1895                 goto error;
1896         ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1897         if (ret)
1898                 goto error;
1899
1900         ret = ena_com_create_io_cq(ena_dev, io_cq);
1901         if (ret)
1902                 goto error;
1903
1904         ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1905         if (ret)
1906                 goto destroy_io_cq;
1907
1908         return 0;
1909
1910 destroy_io_cq:
1911         ena_com_destroy_io_cq(ena_dev, io_cq);
1912 error:
1913         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1914         return ret;
1915 }
1916
1917 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1918 {
1919         struct ena_com_io_sq *io_sq;
1920         struct ena_com_io_cq *io_cq;
1921
1922         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1923                 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1924                             qid, ENA_TOTAL_NUM_QUEUES);
1925                 return;
1926         }
1927
1928         io_sq = &ena_dev->io_sq_queues[qid];
1929         io_cq = &ena_dev->io_cq_queues[qid];
1930
1931         ena_com_destroy_io_sq(ena_dev, io_sq);
1932         ena_com_destroy_io_cq(ena_dev, io_cq);
1933
1934         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1935 }
1936
1937 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1938                             struct ena_admin_get_feat_resp *resp)
1939 {
1940         return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0);
1941 }
1942
1943 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1944                               struct ena_com_dev_get_features_ctx *get_feat_ctx)
1945 {
1946         struct ena_admin_get_feat_resp get_resp;
1947         int rc;
1948
1949         rc = ena_com_get_feature(ena_dev, &get_resp,
1950                                  ENA_ADMIN_DEVICE_ATTRIBUTES, 0);
1951         if (rc)
1952                 return rc;
1953
1954         memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1955                sizeof(get_resp.u.dev_attr));
1956         ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1957
1958         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1959                 rc = ena_com_get_feature(ena_dev, &get_resp,
1960                                          ENA_ADMIN_MAX_QUEUES_EXT,
1961                                          ENA_FEATURE_MAX_QUEUE_EXT_VER);
1962                 if (rc)
1963                         return rc;
1964
1965                 if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER)
1966                         return -EINVAL;
1967
1968                 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext,
1969                        sizeof(get_resp.u.max_queue_ext));
1970                 ena_dev->tx_max_header_size =
1971                         get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size;
1972         } else {
1973                 rc = ena_com_get_feature(ena_dev, &get_resp,
1974                                          ENA_ADMIN_MAX_QUEUES_NUM, 0);
1975                 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1976                        sizeof(get_resp.u.max_queue));
1977                 ena_dev->tx_max_header_size =
1978                         get_resp.u.max_queue.max_header_size;
1979
1980                 if (rc)
1981                         return rc;
1982         }
1983
1984         rc = ena_com_get_feature(ena_dev, &get_resp,
1985                                  ENA_ADMIN_AENQ_CONFIG, 0);
1986         if (rc)
1987                 return rc;
1988
1989         memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1990                sizeof(get_resp.u.aenq));
1991
1992         rc = ena_com_get_feature(ena_dev, &get_resp,
1993                                  ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
1994         if (rc)
1995                 return rc;
1996
1997         memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
1998                sizeof(get_resp.u.offload));
1999
2000         /* Driver hints isn't mandatory admin command. So in case the
2001          * command isn't supported set driver hints to 0
2002          */
2003         rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0);
2004
2005         if (!rc)
2006                 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints,
2007                        sizeof(get_resp.u.hw_hints));
2008         else if (rc == ENA_COM_UNSUPPORTED)
2009                 memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints));
2010         else
2011                 return rc;
2012
2013         rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0);
2014         if (!rc)
2015                 memcpy(&get_feat_ctx->llq, &get_resp.u.llq,
2016                        sizeof(get_resp.u.llq));
2017         else if (rc == ENA_COM_UNSUPPORTED)
2018                 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq));
2019         else
2020                 return rc;
2021
2022         rc = ena_com_get_feature(ena_dev, &get_resp,
2023                                  ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
2024         if (!rc)
2025                 memcpy(&get_feat_ctx->ind_table, &get_resp.u.ind_table,
2026                        sizeof(get_resp.u.ind_table));
2027         else if (rc == ENA_COM_UNSUPPORTED)
2028                 memset(&get_feat_ctx->ind_table, 0x0,
2029                        sizeof(get_feat_ctx->ind_table));
2030         else
2031                 return rc;
2032
2033         return 0;
2034 }
2035
2036 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
2037 {
2038         ena_com_handle_admin_completion(&ena_dev->admin_queue);
2039 }
2040
2041 /* ena_handle_specific_aenq_event:
2042  * return the handler that is relevant to the specific event group
2043  */
2044 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,
2045                                                      u16 group)
2046 {
2047         struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
2048
2049         if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
2050                 return aenq_handlers->handlers[group];
2051
2052         return aenq_handlers->unimplemented_handler;
2053 }
2054
2055 /* ena_aenq_intr_handler:
2056  * handles the aenq incoming events.
2057  * pop events from the queue and apply the specific handler
2058  */
2059 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
2060 {
2061         struct ena_admin_aenq_entry *aenq_e;
2062         struct ena_admin_aenq_common_desc *aenq_common;
2063         struct ena_com_aenq *aenq  = &dev->aenq;
2064         u64 timestamp;
2065         ena_aenq_handler handler_cb;
2066         u16 masked_head, processed = 0;
2067         u8 phase;
2068
2069         masked_head = aenq->head & (aenq->q_depth - 1);
2070         phase = aenq->phase;
2071         aenq_e = &aenq->entries[masked_head]; /* Get first entry */
2072         aenq_common = &aenq_e->aenq_common_desc;
2073
2074         /* Go over all the events */
2075         while ((READ_ONCE8(aenq_common->flags) &
2076                 ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
2077                 /* Make sure the phase bit (ownership) is as expected before
2078                  * reading the rest of the descriptor.
2079                  */
2080                 dma_rmb();
2081
2082                 timestamp = (u64)aenq_common->timestamp_low |
2083                         ((u64)aenq_common->timestamp_high << 32);
2084                 ENA_TOUCH(timestamp); /* In case debug is disabled */
2085                 ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%" ENA_PRIu64 "s]\n",
2086                             aenq_common->group,
2087                             aenq_common->syndrom,
2088                             timestamp);
2089
2090                 /* Handle specific event*/
2091                 handler_cb = ena_com_get_specific_aenq_cb(dev,
2092                                                           aenq_common->group);
2093                 handler_cb(data, aenq_e); /* call the actual event handler*/
2094
2095                 /* Get next event entry */
2096                 masked_head++;
2097                 processed++;
2098
2099                 if (unlikely(masked_head == aenq->q_depth)) {
2100                         masked_head = 0;
2101                         phase = !phase;
2102                 }
2103                 aenq_e = &aenq->entries[masked_head];
2104                 aenq_common = &aenq_e->aenq_common_desc;
2105         }
2106
2107         aenq->head += processed;
2108         aenq->phase = phase;
2109
2110         /* Don't update aenq doorbell if there weren't any processed events */
2111         if (!processed)
2112                 return;
2113
2114         /* write the aenq doorbell after all AENQ descriptors were read */
2115         mb();
2116         ENA_REG_WRITE32_RELAXED(dev->bus, (u32)aenq->head,
2117                                 dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
2118         mmiowb();
2119 }
2120
2121 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
2122                       enum ena_regs_reset_reason_types reset_reason)
2123 {
2124         u32 stat, timeout, cap, reset_val;
2125         int rc;
2126
2127         stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
2128         cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
2129
2130         if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
2131                      (cap == ENA_MMIO_READ_TIMEOUT))) {
2132                 ena_trc_err("Reg read32 timeout occurred\n");
2133                 return ENA_COM_TIMER_EXPIRED;
2134         }
2135
2136         if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
2137                 ena_trc_err("Device isn't ready, can't reset device\n");
2138                 return ENA_COM_INVAL;
2139         }
2140
2141         timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
2142                         ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
2143         if (timeout == 0) {
2144                 ena_trc_err("Invalid timeout value\n");
2145                 return ENA_COM_INVAL;
2146         }
2147
2148         /* start reset */
2149         reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
2150         reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
2151                         ENA_REGS_DEV_CTL_RESET_REASON_MASK;
2152         ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2153
2154         /* Write again the MMIO read request address */
2155         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
2156
2157         rc = wait_for_reset_state(ena_dev, timeout,
2158                                   ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
2159         if (rc != 0) {
2160                 ena_trc_err("Reset indication didn't turn on\n");
2161                 return rc;
2162         }
2163
2164         /* reset done */
2165         ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2166         rc = wait_for_reset_state(ena_dev, timeout, 0);
2167         if (rc != 0) {
2168                 ena_trc_err("Reset indication didn't turn off\n");
2169                 return rc;
2170         }
2171
2172         timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
2173                 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
2174         if (timeout)
2175                 /* the resolution of timeout reg is 100ms */
2176                 ena_dev->admin_queue.completion_timeout = timeout * 100000;
2177         else
2178                 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
2179
2180         return 0;
2181 }
2182
2183 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
2184                              struct ena_com_stats_ctx *ctx,
2185                              enum ena_admin_get_stats_type type)
2186 {
2187         struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
2188         struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
2189         struct ena_com_admin_queue *admin_queue;
2190         int ret;
2191
2192         admin_queue = &ena_dev->admin_queue;
2193
2194         get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
2195         get_cmd->aq_common_descriptor.flags = 0;
2196         get_cmd->type = type;
2197
2198         ret =  ena_com_execute_admin_command(admin_queue,
2199                                              (struct ena_admin_aq_entry *)get_cmd,
2200                                              sizeof(*get_cmd),
2201                                              (struct ena_admin_acq_entry *)get_resp,
2202                                              sizeof(*get_resp));
2203
2204         if (unlikely(ret))
2205                 ena_trc_err("Failed to get stats. error: %d\n", ret);
2206
2207         return ret;
2208 }
2209
2210 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
2211                                 struct ena_admin_basic_stats *stats)
2212 {
2213         struct ena_com_stats_ctx ctx;
2214         int ret;
2215
2216         memset(&ctx, 0x0, sizeof(ctx));
2217         ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
2218         if (likely(ret == 0))
2219                 memcpy(stats, &ctx.get_resp.basic_stats,
2220                        sizeof(ctx.get_resp.basic_stats));
2221
2222         return ret;
2223 }
2224
2225 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)
2226 {
2227         struct ena_com_admin_queue *admin_queue;
2228         struct ena_admin_set_feat_cmd cmd;
2229         struct ena_admin_set_feat_resp resp;
2230         int ret;
2231
2232         if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
2233                 ena_trc_dbg("Feature %d isn't supported\n", ENA_ADMIN_MTU);
2234                 return ENA_COM_UNSUPPORTED;
2235         }
2236
2237         memset(&cmd, 0x0, sizeof(cmd));
2238         admin_queue = &ena_dev->admin_queue;
2239
2240         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2241         cmd.aq_common_descriptor.flags = 0;
2242         cmd.feat_common.feature_id = ENA_ADMIN_MTU;
2243         cmd.u.mtu.mtu = mtu;
2244
2245         ret = ena_com_execute_admin_command(admin_queue,
2246                                             (struct ena_admin_aq_entry *)&cmd,
2247                                             sizeof(cmd),
2248                                             (struct ena_admin_acq_entry *)&resp,
2249                                             sizeof(resp));
2250
2251         if (unlikely(ret))
2252                 ena_trc_err("Failed to set mtu %d. error: %d\n", mtu, ret);
2253
2254         return ret;
2255 }
2256
2257 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
2258                                  struct ena_admin_feature_offload_desc *offload)
2259 {
2260         int ret;
2261         struct ena_admin_get_feat_resp resp;
2262
2263         ret = ena_com_get_feature(ena_dev, &resp,
2264                                   ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
2265         if (unlikely(ret)) {
2266                 ena_trc_err("Failed to get offload capabilities %d\n", ret);
2267                 return ret;
2268         }
2269
2270         memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
2271
2272         return 0;
2273 }
2274
2275 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2276 {
2277         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2278         struct ena_rss *rss = &ena_dev->rss;
2279         struct ena_admin_set_feat_cmd cmd;
2280         struct ena_admin_set_feat_resp resp;
2281         struct ena_admin_get_feat_resp get_resp;
2282         int ret;
2283
2284         if (!ena_com_check_supported_feature_id(ena_dev,
2285                                                 ENA_ADMIN_RSS_HASH_FUNCTION)) {
2286                 ena_trc_dbg("Feature %d isn't supported\n",
2287                             ENA_ADMIN_RSS_HASH_FUNCTION);
2288                 return ENA_COM_UNSUPPORTED;
2289         }
2290
2291         /* Validate hash function is supported */
2292         ret = ena_com_get_feature(ena_dev, &get_resp,
2293                                   ENA_ADMIN_RSS_HASH_FUNCTION, 0);
2294         if (unlikely(ret))
2295                 return ret;
2296
2297         if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) {
2298                 ena_trc_err("Func hash %d isn't supported by device, abort\n",
2299                             rss->hash_func);
2300                 return ENA_COM_UNSUPPORTED;
2301         }
2302
2303         memset(&cmd, 0x0, sizeof(cmd));
2304
2305         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2306         cmd.aq_common_descriptor.flags =
2307                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2308         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2309         cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2310         cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2311
2312         ret = ena_com_mem_addr_set(ena_dev,
2313                                    &cmd.control_buffer.address,
2314                                    rss->hash_key_dma_addr);
2315         if (unlikely(ret)) {
2316                 ena_trc_err("memory address set failed\n");
2317                 return ret;
2318         }
2319
2320         cmd.control_buffer.length = sizeof(*rss->hash_key);
2321
2322         ret = ena_com_execute_admin_command(admin_queue,
2323                                             (struct ena_admin_aq_entry *)&cmd,
2324                                             sizeof(cmd),
2325                                             (struct ena_admin_acq_entry *)&resp,
2326                                             sizeof(resp));
2327         if (unlikely(ret)) {
2328                 ena_trc_err("Failed to set hash function %d. error: %d\n",
2329                             rss->hash_func, ret);
2330                 return ENA_COM_INVAL;
2331         }
2332
2333         return 0;
2334 }
2335
2336 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2337                                enum ena_admin_hash_functions func,
2338                                const u8 *key, u16 key_len, u32 init_val)
2339 {
2340         struct ena_admin_feature_rss_flow_hash_control *hash_key;
2341         struct ena_admin_get_feat_resp get_resp;
2342         enum ena_admin_hash_functions old_func;
2343         struct ena_rss *rss = &ena_dev->rss;
2344         int rc;
2345
2346         hash_key = rss->hash_key;
2347
2348         /* Make sure size is a mult of DWs */
2349         if (unlikely(key_len & 0x3))
2350                 return ENA_COM_INVAL;
2351
2352         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2353                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2354                                     rss->hash_key_dma_addr,
2355                                     sizeof(*rss->hash_key), 0);
2356         if (unlikely(rc))
2357                 return rc;
2358
2359         if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) {
2360                 ena_trc_err("Flow hash function %d isn't supported\n", func);
2361                 return ENA_COM_UNSUPPORTED;
2362         }
2363
2364         switch (func) {
2365         case ENA_ADMIN_TOEPLITZ:
2366                 if (key) {
2367                         if (key_len != sizeof(hash_key->key)) {
2368                                 ena_trc_err("key len (%hu) doesn't equal the supported size (%zu)\n",
2369                                              key_len, sizeof(hash_key->key));
2370                                 return ENA_COM_INVAL;
2371                         }
2372                         memcpy(hash_key->key, key, key_len);
2373                         rss->hash_init_val = init_val;
2374                         hash_key->keys_num = key_len / sizeof(u32);
2375                 }
2376                 break;
2377         case ENA_ADMIN_CRC32:
2378                 rss->hash_init_val = init_val;
2379                 break;
2380         default:
2381                 ena_trc_err("Invalid hash function (%d)\n", func);
2382                 return ENA_COM_INVAL;
2383         }
2384
2385         old_func = rss->hash_func;
2386         rss->hash_func = func;
2387         rc = ena_com_set_hash_function(ena_dev);
2388
2389         /* Restore the old function */
2390         if (unlikely(rc))
2391                 rss->hash_func = old_func;
2392
2393         return rc;
2394 }
2395
2396 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2397                               enum ena_admin_hash_functions *func,
2398                               u8 *key)
2399 {
2400         struct ena_rss *rss = &ena_dev->rss;
2401         struct ena_admin_get_feat_resp get_resp;
2402         struct ena_admin_feature_rss_flow_hash_control *hash_key =
2403                 rss->hash_key;
2404         int rc;
2405
2406         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2407                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2408                                     rss->hash_key_dma_addr,
2409                                     sizeof(*rss->hash_key), 0);
2410         if (unlikely(rc))
2411                 return rc;
2412
2413         /* ENA_FFS returns 1 in case the lsb is set */
2414         rss->hash_func = ENA_FFS(get_resp.u.flow_hash_func.selected_func);
2415         if (rss->hash_func)
2416                 rss->hash_func--;
2417
2418         if (func)
2419                 *func = rss->hash_func;
2420
2421         if (key)
2422                 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
2423
2424         return 0;
2425 }
2426
2427 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2428                           enum ena_admin_flow_hash_proto proto,
2429                           u16 *fields)
2430 {
2431         struct ena_rss *rss = &ena_dev->rss;
2432         struct ena_admin_get_feat_resp get_resp;
2433         int rc;
2434
2435         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2436                                     ENA_ADMIN_RSS_HASH_INPUT,
2437                                     rss->hash_ctrl_dma_addr,
2438                                     sizeof(*rss->hash_ctrl), 0);
2439         if (unlikely(rc))
2440                 return rc;
2441
2442         if (fields)
2443                 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2444
2445         return 0;
2446 }
2447
2448 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2449 {
2450         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2451         struct ena_rss *rss = &ena_dev->rss;
2452         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2453         struct ena_admin_set_feat_cmd cmd;
2454         struct ena_admin_set_feat_resp resp;
2455         int ret;
2456
2457         if (!ena_com_check_supported_feature_id(ena_dev,
2458                                                 ENA_ADMIN_RSS_HASH_INPUT)) {
2459                 ena_trc_dbg("Feature %d isn't supported\n",
2460                             ENA_ADMIN_RSS_HASH_INPUT);
2461                 return ENA_COM_UNSUPPORTED;
2462         }
2463
2464         memset(&cmd, 0x0, sizeof(cmd));
2465
2466         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2467         cmd.aq_common_descriptor.flags =
2468                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2469         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2470         cmd.u.flow_hash_input.enabled_input_sort =
2471                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2472                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2473
2474         ret = ena_com_mem_addr_set(ena_dev,
2475                                    &cmd.control_buffer.address,
2476                                    rss->hash_ctrl_dma_addr);
2477         if (unlikely(ret)) {
2478                 ena_trc_err("memory address set failed\n");
2479                 return ret;
2480         }
2481         cmd.control_buffer.length = sizeof(*hash_ctrl);
2482
2483         ret = ena_com_execute_admin_command(admin_queue,
2484                                             (struct ena_admin_aq_entry *)&cmd,
2485                                             sizeof(cmd),
2486                                             (struct ena_admin_acq_entry *)&resp,
2487                                             sizeof(resp));
2488         if (unlikely(ret))
2489                 ena_trc_err("Failed to set hash input. error: %d\n", ret);
2490
2491         return ret;
2492 }
2493
2494 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2495 {
2496         struct ena_rss *rss = &ena_dev->rss;
2497         struct ena_admin_feature_rss_hash_control *hash_ctrl =
2498                 rss->hash_ctrl;
2499         u16 available_fields = 0;
2500         int rc, i;
2501
2502         /* Get the supported hash input */
2503         rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2504         if (unlikely(rc))
2505                 return rc;
2506
2507         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2508                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2509                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2510
2511         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2512                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2513                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2514
2515         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2516                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2517                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2518
2519         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2520                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2521                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2522
2523         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2524                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2525
2526         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2527                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2528
2529         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2530                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2531
2532         hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2533                 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2534
2535         for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2536                 available_fields = hash_ctrl->selected_fields[i].fields &
2537                                 hash_ctrl->supported_fields[i].fields;
2538                 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2539                         ena_trc_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2540                                     i, hash_ctrl->supported_fields[i].fields,
2541                                     hash_ctrl->selected_fields[i].fields);
2542                         return ENA_COM_UNSUPPORTED;
2543                 }
2544         }
2545
2546         rc = ena_com_set_hash_ctrl(ena_dev);
2547
2548         /* In case of failure, restore the old hash ctrl */
2549         if (unlikely(rc))
2550                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2551
2552         return rc;
2553 }
2554
2555 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2556                            enum ena_admin_flow_hash_proto proto,
2557                            u16 hash_fields)
2558 {
2559         struct ena_rss *rss = &ena_dev->rss;
2560         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2561         u16 supported_fields;
2562         int rc;
2563
2564         if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2565                 ena_trc_err("Invalid proto num (%u)\n", proto);
2566                 return ENA_COM_INVAL;
2567         }
2568
2569         /* Get the ctrl table */
2570         rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2571         if (unlikely(rc))
2572                 return rc;
2573
2574         /* Make sure all the fields are supported */
2575         supported_fields = hash_ctrl->supported_fields[proto].fields;
2576         if ((hash_fields & supported_fields) != hash_fields) {
2577                 ena_trc_err("proto %d doesn't support the required fields %x. supports only: %x\n",
2578                             proto, hash_fields, supported_fields);
2579         }
2580
2581         hash_ctrl->selected_fields[proto].fields = hash_fields;
2582
2583         rc = ena_com_set_hash_ctrl(ena_dev);
2584
2585         /* In case of failure, restore the old hash ctrl */
2586         if (unlikely(rc))
2587                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2588
2589         return 0;
2590 }
2591
2592 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2593                                       u16 entry_idx, u16 entry_value)
2594 {
2595         struct ena_rss *rss = &ena_dev->rss;
2596
2597         if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2598                 return ENA_COM_INVAL;
2599
2600         if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2601                 return ENA_COM_INVAL;
2602
2603         rss->host_rss_ind_tbl[entry_idx] = entry_value;
2604
2605         return 0;
2606 }
2607
2608 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2609 {
2610         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2611         struct ena_rss *rss = &ena_dev->rss;
2612         struct ena_admin_set_feat_cmd cmd;
2613         struct ena_admin_set_feat_resp resp;
2614         int ret;
2615
2616         if (!ena_com_check_supported_feature_id(ena_dev,
2617                                                 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {
2618                 ena_trc_dbg("Feature %d isn't supported\n",
2619                             ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
2620                 return ENA_COM_UNSUPPORTED;
2621         }
2622
2623         ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2624         if (ret) {
2625                 ena_trc_err("Failed to convert host indirection table to device table\n");
2626                 return ret;
2627         }
2628
2629         memset(&cmd, 0x0, sizeof(cmd));
2630
2631         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2632         cmd.aq_common_descriptor.flags =
2633                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2634         cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG;
2635         cmd.u.ind_table.size = rss->tbl_log_size;
2636         cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2637
2638         ret = ena_com_mem_addr_set(ena_dev,
2639                                    &cmd.control_buffer.address,
2640                                    rss->rss_ind_tbl_dma_addr);
2641         if (unlikely(ret)) {
2642                 ena_trc_err("memory address set failed\n");
2643                 return ret;
2644         }
2645
2646         cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2647                 sizeof(struct ena_admin_rss_ind_table_entry);
2648
2649         ret = ena_com_execute_admin_command(admin_queue,
2650                                             (struct ena_admin_aq_entry *)&cmd,
2651                                             sizeof(cmd),
2652                                             (struct ena_admin_acq_entry *)&resp,
2653                                             sizeof(resp));
2654
2655         if (unlikely(ret))
2656                 ena_trc_err("Failed to set indirect table. error: %d\n", ret);
2657
2658         return ret;
2659 }
2660
2661 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2662 {
2663         struct ena_rss *rss = &ena_dev->rss;
2664         struct ena_admin_get_feat_resp get_resp;
2665         u32 tbl_size;
2666         int i, rc;
2667
2668         tbl_size = (1ULL << rss->tbl_log_size) *
2669                 sizeof(struct ena_admin_rss_ind_table_entry);
2670
2671         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2672                                     ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
2673                                     rss->rss_ind_tbl_dma_addr,
2674                                     tbl_size, 0);
2675         if (unlikely(rc))
2676                 return rc;
2677
2678         if (!ind_tbl)
2679                 return 0;
2680
2681         for (i = 0; i < (1 << rss->tbl_log_size); i++)
2682                 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2683
2684         return 0;
2685 }
2686
2687 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2688 {
2689         int rc;
2690
2691         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2692
2693         rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2694         if (unlikely(rc))
2695                 goto err_indr_tbl;
2696
2697         rc = ena_com_hash_key_allocate(ena_dev);
2698         if (unlikely(rc))
2699                 goto err_hash_key;
2700
2701         ena_com_hash_key_fill_default_key(ena_dev);
2702
2703         rc = ena_com_hash_ctrl_init(ena_dev);
2704         if (unlikely(rc))
2705                 goto err_hash_ctrl;
2706
2707         return 0;
2708
2709 err_hash_ctrl:
2710         ena_com_hash_key_destroy(ena_dev);
2711 err_hash_key:
2712         ena_com_indirect_table_destroy(ena_dev);
2713 err_indr_tbl:
2714
2715         return rc;
2716 }
2717
2718 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2719 {
2720         ena_com_indirect_table_destroy(ena_dev);
2721         ena_com_hash_key_destroy(ena_dev);
2722         ena_com_hash_ctrl_destroy(ena_dev);
2723
2724         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2725 }
2726
2727 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2728 {
2729         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2730
2731         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2732                                SZ_4K,
2733                                host_attr->host_info,
2734                                host_attr->host_info_dma_addr,
2735                                host_attr->host_info_dma_handle);
2736         if (unlikely(!host_attr->host_info))
2737                 return ENA_COM_NO_MEM;
2738
2739         host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR <<
2740                 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) |
2741                 (ENA_COMMON_SPEC_VERSION_MINOR));
2742
2743         return 0;
2744 }
2745
2746 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2747                                 u32 debug_area_size)
2748 {
2749         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2750
2751         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2752                                debug_area_size,
2753                                host_attr->debug_area_virt_addr,
2754                                host_attr->debug_area_dma_addr,
2755                                host_attr->debug_area_dma_handle);
2756         if (unlikely(!host_attr->debug_area_virt_addr)) {
2757                 host_attr->debug_area_size = 0;
2758                 return ENA_COM_NO_MEM;
2759         }
2760
2761         host_attr->debug_area_size = debug_area_size;
2762
2763         return 0;
2764 }
2765
2766 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2767 {
2768         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2769
2770         if (host_attr->host_info) {
2771                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2772                                       SZ_4K,
2773                                       host_attr->host_info,
2774                                       host_attr->host_info_dma_addr,
2775                                       host_attr->host_info_dma_handle);
2776                 host_attr->host_info = NULL;
2777         }
2778 }
2779
2780 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2781 {
2782         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2783
2784         if (host_attr->debug_area_virt_addr) {
2785                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2786                                       host_attr->debug_area_size,
2787                                       host_attr->debug_area_virt_addr,
2788                                       host_attr->debug_area_dma_addr,
2789                                       host_attr->debug_area_dma_handle);
2790                 host_attr->debug_area_virt_addr = NULL;
2791         }
2792 }
2793
2794 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2795 {
2796         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2797         struct ena_com_admin_queue *admin_queue;
2798         struct ena_admin_set_feat_cmd cmd;
2799         struct ena_admin_set_feat_resp resp;
2800
2801         int ret;
2802
2803         /* Host attribute config is called before ena_com_get_dev_attr_feat
2804          * so ena_com can't check if the feature is supported.
2805          */
2806
2807         memset(&cmd, 0x0, sizeof(cmd));
2808         admin_queue = &ena_dev->admin_queue;
2809
2810         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2811         cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2812
2813         ret = ena_com_mem_addr_set(ena_dev,
2814                                    &cmd.u.host_attr.debug_ba,
2815                                    host_attr->debug_area_dma_addr);
2816         if (unlikely(ret)) {
2817                 ena_trc_err("memory address set failed\n");
2818                 return ret;
2819         }
2820
2821         ret = ena_com_mem_addr_set(ena_dev,
2822                                    &cmd.u.host_attr.os_info_ba,
2823                                    host_attr->host_info_dma_addr);
2824         if (unlikely(ret)) {
2825                 ena_trc_err("memory address set failed\n");
2826                 return ret;
2827         }
2828
2829         cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2830
2831         ret = ena_com_execute_admin_command(admin_queue,
2832                                             (struct ena_admin_aq_entry *)&cmd,
2833                                             sizeof(cmd),
2834                                             (struct ena_admin_acq_entry *)&resp,
2835                                             sizeof(resp));
2836
2837         if (unlikely(ret))
2838                 ena_trc_err("Failed to set host attributes: %d\n", ret);
2839
2840         return ret;
2841 }
2842
2843 /* Interrupt moderation */
2844 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2845 {
2846         return ena_com_check_supported_feature_id(ena_dev,
2847                                                   ENA_ADMIN_INTERRUPT_MODERATION);
2848 }
2849
2850 static int ena_com_update_nonadaptive_moderation_interval(u32 coalesce_usecs,
2851                                                           u32 intr_delay_resolution,
2852                                                           u32 *intr_moder_interval)
2853 {
2854         if (!intr_delay_resolution) {
2855                 ena_trc_err("Illegal interrupt delay granularity value\n");
2856                 return ENA_COM_FAULT;
2857         }
2858
2859         *intr_moder_interval = coalesce_usecs / intr_delay_resolution;
2860
2861         return 0;
2862 }
2863
2864
2865 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2866                                                       u32 tx_coalesce_usecs)
2867 {
2868         return ena_com_update_nonadaptive_moderation_interval(tx_coalesce_usecs,
2869                                                               ena_dev->intr_delay_resolution,
2870                                                               &ena_dev->intr_moder_tx_interval);
2871 }
2872
2873 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2874                                                       u32 rx_coalesce_usecs)
2875 {
2876         return ena_com_update_nonadaptive_moderation_interval(rx_coalesce_usecs,
2877                                                               ena_dev->intr_delay_resolution,
2878                                                               &ena_dev->intr_moder_rx_interval);
2879 }
2880
2881 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2882 {
2883         struct ena_admin_get_feat_resp get_resp;
2884         u16 delay_resolution;
2885         int rc;
2886
2887         rc = ena_com_get_feature(ena_dev, &get_resp,
2888                                  ENA_ADMIN_INTERRUPT_MODERATION, 0);
2889
2890         if (rc) {
2891                 if (rc == ENA_COM_UNSUPPORTED) {
2892                         ena_trc_dbg("Feature %d isn't supported\n",
2893                                     ENA_ADMIN_INTERRUPT_MODERATION);
2894                         rc = 0;
2895                 } else {
2896                         ena_trc_err("Failed to get interrupt moderation admin cmd. rc: %d\n",
2897                                     rc);
2898                 }
2899
2900                 /* no moderation supported, disable adaptive support */
2901                 ena_com_disable_adaptive_moderation(ena_dev);
2902                 return rc;
2903         }
2904
2905         /* if moderation is supported by device we set adaptive moderation */
2906         delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2907         ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2908
2909         /* Disable adaptive moderation by default - can be enabled later */
2910         ena_com_disable_adaptive_moderation(ena_dev);
2911
2912         return 0;
2913 }
2914
2915 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2916 {
2917         return ena_dev->intr_moder_tx_interval;
2918 }
2919
2920 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2921 {
2922         return ena_dev->intr_moder_rx_interval;
2923 }
2924
2925 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
2926                             struct ena_admin_feature_llq_desc *llq_features,
2927                             struct ena_llq_configurations *llq_default_cfg)
2928 {
2929         int rc;
2930         struct ena_com_llq_info *llq_info = &(ena_dev->llq_info);;
2931
2932         if (!llq_features->max_llq_num) {
2933                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
2934                 return 0;
2935         }
2936
2937         rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg);
2938         if (rc)
2939                 return rc;
2940
2941         ena_dev->tx_max_header_size = llq_info->desc_list_entry_size -
2942                 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc));
2943
2944         if (ena_dev->tx_max_header_size == 0) {
2945                 ena_trc_err("the size of the LLQ entry is smaller than needed\n");
2946                 return -EINVAL;
2947         }
2948
2949         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
2950
2951         return 0;
2952 }