drivers/net/ena/base/ena_defs/ena_admin_defs.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _ENA_ADMIN_H_
   7 #define _ENA_ADMIN_H_
   8
   9 #define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32
  10 #define ENA_ADMIN_EXTRA_PROPERTIES_COUNT     32
  11
  12 enum ena_admin_aq_opcode {
  13         ENA_ADMIN_CREATE_SQ                         = 1,
  14         ENA_ADMIN_DESTROY_SQ                        = 2,
  15         ENA_ADMIN_CREATE_CQ                         = 3,
  16         ENA_ADMIN_DESTROY_CQ                        = 4,
  17         ENA_ADMIN_GET_FEATURE                       = 8,
  18         ENA_ADMIN_SET_FEATURE                       = 9,
  19         ENA_ADMIN_GET_STATS                         = 11,
  20 };
  21
  22 enum ena_admin_aq_completion_status {
  23         ENA_ADMIN_SUCCESS                           = 0,
  24         ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE       = 1,
  25         ENA_ADMIN_BAD_OPCODE                        = 2,
  26         ENA_ADMIN_UNSUPPORTED_OPCODE                = 3,
  27         ENA_ADMIN_MALFORMED_REQUEST                 = 4,
  28         /* Additional status is provided in ACQ entry extended_status */
  29         ENA_ADMIN_ILLEGAL_PARAMETER                 = 5,
  30         ENA_ADMIN_UNKNOWN_ERROR                     = 6,
  31         ENA_ADMIN_RESOURCE_BUSY                     = 7,
  32 };
  33
  34 enum ena_admin_aq_feature_id {
  35         ENA_ADMIN_DEVICE_ATTRIBUTES                 = 1,
  36         ENA_ADMIN_MAX_QUEUES_NUM                    = 2,
  37         ENA_ADMIN_HW_HINTS                          = 3,
  38         ENA_ADMIN_LLQ                               = 4,
  39         ENA_ADMIN_EXTRA_PROPERTIES_STRINGS          = 5,
  40         ENA_ADMIN_EXTRA_PROPERTIES_FLAGS            = 6,
  41         ENA_ADMIN_MAX_QUEUES_EXT                    = 7,
  42         ENA_ADMIN_RSS_HASH_FUNCTION                 = 10,
  43         ENA_ADMIN_STATELESS_OFFLOAD_CONFIG          = 11,
  44         ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG      = 12,
  45         ENA_ADMIN_MTU                               = 14,
  46         ENA_ADMIN_RSS_HASH_INPUT                    = 18,
  47         ENA_ADMIN_INTERRUPT_MODERATION              = 20,
  48         ENA_ADMIN_AENQ_CONFIG                       = 26,
  49         ENA_ADMIN_LINK_CONFIG                       = 27,
  50         ENA_ADMIN_HOST_ATTR_CONFIG                  = 28,
  51         ENA_ADMIN_FEATURES_OPCODE_NUM               = 32,
  52 };
  53
  54 enum ena_admin_placement_policy_type {
  55         /* descriptors and headers are in host memory */
  56         ENA_ADMIN_PLACEMENT_POLICY_HOST             = 1,
  57         /* descriptors and headers are in device memory (a.k.a Low Latency
  58          * Queue)
  59          */
  60         ENA_ADMIN_PLACEMENT_POLICY_DEV              = 3,
  61 };
  62
  63 enum ena_admin_link_types {
  64         ENA_ADMIN_LINK_SPEED_1G                     = 0x1,
  65         ENA_ADMIN_LINK_SPEED_2_HALF_G               = 0x2,
  66         ENA_ADMIN_LINK_SPEED_5G                     = 0x4,
  67         ENA_ADMIN_LINK_SPEED_10G                    = 0x8,
  68         ENA_ADMIN_LINK_SPEED_25G                    = 0x10,
  69         ENA_ADMIN_LINK_SPEED_40G                    = 0x20,
  70         ENA_ADMIN_LINK_SPEED_50G                    = 0x40,
  71         ENA_ADMIN_LINK_SPEED_100G                   = 0x80,
  72         ENA_ADMIN_LINK_SPEED_200G                   = 0x100,
  73         ENA_ADMIN_LINK_SPEED_400G                   = 0x200,
  74 };
  75
  76 enum ena_admin_completion_policy_type {
  77         /* completion queue entry for each sq descriptor */
  78         ENA_ADMIN_COMPLETION_POLICY_DESC            = 0,
  79         /* completion queue entry upon request in sq descriptor */
  80         ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND  = 1,
  81         /* current queue head pointer is updated in OS memory upon sq
  82          * descriptor request
  83          */
  84         ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND  = 2,
  85         /* current queue head pointer is updated in OS memory for each sq
  86          * descriptor
  87          */
  88         ENA_ADMIN_COMPLETION_POLICY_HEAD            = 3,
  89 };
  90
  91 /* basic stats return ena_admin_basic_stats while extanded stats return a
  92  * buffer (string format) with additional statistics per queue and per
  93  * device id
  94  */
  95 enum ena_admin_get_stats_type {
  96         ENA_ADMIN_GET_STATS_TYPE_BASIC              = 0,
  97         ENA_ADMIN_GET_STATS_TYPE_EXTENDED           = 1,
  98 };
  99
 100 enum ena_admin_get_stats_scope {
 101         ENA_ADMIN_SPECIFIC_QUEUE                    = 0,
 102         ENA_ADMIN_ETH_TRAFFIC                       = 1,
 103 };
 104
 105 struct ena_admin_aq_common_desc {
 106         /* 11:0 : command_id
 107          * 15:12 : reserved12
 108          */
 109         uint16_t command_id;
 110
 111         /* as appears in ena_admin_aq_opcode */
 112         uint8_t opcode;
 113
 114         /* 0 : phase
 115          * 1 : ctrl_data - control buffer address valid
 116          * 2 : ctrl_data_indirect - control buffer address
 117          *    points to list of pages with addresses of control
 118          *    buffers
 119          * 7:3 : reserved3
 120          */
 121         uint8_t flags;
 122 };
 123
 124 /* used in ena_admin_aq_entry. Can point directly to control data, or to a
 125  * page list chunk. Used also at the end of indirect mode page list chunks,
 126  * for chaining.
 127  */
 128 struct ena_admin_ctrl_buff_info {
 129         uint32_t length;
 130
 131         struct ena_common_mem_addr address;
 132 };
 133
 134 struct ena_admin_sq {
 135         uint16_t sq_idx;
 136
 137         /* 4:0 : reserved
 138          * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
 139          */
 140         uint8_t sq_identity;
 141
 142         uint8_t reserved1;
 143 };
 144
 145 struct ena_admin_aq_entry {
 146         struct ena_admin_aq_common_desc aq_common_descriptor;
 147
 148         union {
 149                 uint32_t inline_data_w1[3];
 150
 151                 struct ena_admin_ctrl_buff_info control_buffer;
 152         } u;
 153
 154         uint32_t inline_data_w4[12];
 155 };
 156
 157 struct ena_admin_acq_common_desc {
 158         /* command identifier to associate it with the aq descriptor
 159          * 11:0 : command_id
 160          * 15:12 : reserved12
 161          */
 162         uint16_t command;
 163
 164         uint8_t status;
 165
 166         /* 0 : phase
 167          * 7:1 : reserved1
 168          */
 169         uint8_t flags;
 170
 171         uint16_t extended_status;
 172
 173         /* indicates to the driver which AQ entry has been consumed by the
 174          *    device and could be reused
 175          */
 176         uint16_t sq_head_indx;
 177 };
 178
 179 struct ena_admin_acq_entry {
 180         struct ena_admin_acq_common_desc acq_common_descriptor;
 181
 182         uint32_t response_specific_data[14];
 183 };
 184
 185 struct ena_admin_aq_create_sq_cmd {
 186         struct ena_admin_aq_common_desc aq_common_descriptor;
 187
 188         /* 4:0 : reserved0_w1
 189          * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
 190          */
 191         uint8_t sq_identity;
 192
 193         uint8_t reserved8_w1;
 194
 195         /* 3:0 : placement_policy - Describing where the SQ
 196          *    descriptor ring and the SQ packet headers reside:
 197          *    0x1 - descriptors and headers are in OS memory,
 198          *    0x3 - descriptors and headers in device memory
 199          *    (a.k.a Low Latency Queue)
 200          * 6:4 : completion_policy - Describing what policy
 201          *    to use for generation completion entry (cqe) in
 202          *    the CQ associated with this SQ: 0x0 - cqe for each
 203          *    sq descriptor, 0x1 - cqe upon request in sq
 204          *    descriptor, 0x2 - current queue head pointer is
 205          *    updated in OS memory upon sq descriptor request
 206          *    0x3 - current queue head pointer is updated in OS
 207          *    memory for each sq descriptor
 208          * 7 : reserved15_w1
 209          */
 210         uint8_t sq_caps_2;
 211
 212         /* 0 : is_physically_contiguous - Described if the
 213          *    queue ring memory is allocated in physical
 214          *    contiguous pages or split.
 215          * 7:1 : reserved17_w1
 216          */
 217         uint8_t sq_caps_3;
 218
 219         /* associated completion queue id. This CQ must be created prior to
 220          *    SQ creation
 221          */
 222         uint16_t cq_idx;
 223
 224         /* submission queue depth in entries */
 225         uint16_t sq_depth;
 226
 227         /* SQ physical base address in OS memory. This field should not be
 228          * used for Low Latency queues. Has to be page aligned.
 229          */
 230         struct ena_common_mem_addr sq_ba;
 231
 232         /* specifies queue head writeback location in OS memory. Valid if
 233          * completion_policy is set to completion_policy_head_on_demand or
 234          * completion_policy_head. Has to be cache aligned
 235          */
 236         struct ena_common_mem_addr sq_head_writeback;
 237
 238         uint32_t reserved0_w7;
 239
 240         uint32_t reserved0_w8;
 241 };
 242
 243 enum ena_admin_sq_direction {
 244         ENA_ADMIN_SQ_DIRECTION_TX                   = 1,
 245         ENA_ADMIN_SQ_DIRECTION_RX                   = 2,
 246 };
 247
 248 struct ena_admin_acq_create_sq_resp_desc {
 249         struct ena_admin_acq_common_desc acq_common_desc;
 250
 251         uint16_t sq_idx;
 252
 253         uint16_t reserved;
 254
 255         /* queue doorbell address as an offset to PCIe MMIO REG BAR */
 256         uint32_t sq_doorbell_offset;
 257
 258         /* low latency queue ring base address as an offset to PCIe MMIO
 259          * LLQ_MEM BAR
 260          */
 261         uint32_t llq_descriptors_offset;
 262
 263         /* low latency queue headers' memory as an offset to PCIe MMIO
 264          * LLQ_MEM BAR
 265          */
 266         uint32_t llq_headers_offset;
 267 };
 268
 269 struct ena_admin_aq_destroy_sq_cmd {
 270         struct ena_admin_aq_common_desc aq_common_descriptor;
 271
 272         struct ena_admin_sq sq;
 273 };
 274
 275 struct ena_admin_acq_destroy_sq_resp_desc {
 276         struct ena_admin_acq_common_desc acq_common_desc;
 277 };
 278
 279 struct ena_admin_aq_create_cq_cmd {
 280         struct ena_admin_aq_common_desc aq_common_descriptor;
 281
 282         /* 4:0 : reserved5
 283          * 5 : interrupt_mode_enabled - if set, cq operates
 284          *    in interrupt mode, otherwise - polling
 285          * 7:6 : reserved6
 286          */
 287         uint8_t cq_caps_1;
 288
 289         /* 4:0 : cq_entry_size_words - size of CQ entry in
 290          *    32-bit words, valid values: 4, 8.
 291          * 7:5 : reserved7
 292          */
 293         uint8_t cq_caps_2;
 294
 295         /* completion queue depth in # of entries. must be power of 2 */
 296         uint16_t cq_depth;
 297
 298         /* msix vector assigned to this cq */
 299         uint32_t msix_vector;
 300
 301         /* cq physical base address in OS memory. CQ must be physically
 302          * contiguous
 303          */
 304         struct ena_common_mem_addr cq_ba;
 305 };
 306
 307 struct ena_admin_acq_create_cq_resp_desc {
 308         struct ena_admin_acq_common_desc acq_common_desc;
 309
 310         uint16_t cq_idx;
 311
 312         /* actual cq depth in number of entries */
 313         uint16_t cq_actual_depth;
 314
 315         uint32_t numa_node_register_offset;
 316
 317         uint32_t cq_head_db_register_offset;
 318
 319         uint32_t cq_interrupt_unmask_register_offset;
 320 };
 321
 322 struct ena_admin_aq_destroy_cq_cmd {
 323         struct ena_admin_aq_common_desc aq_common_descriptor;
 324
 325         uint16_t cq_idx;
 326
 327         uint16_t reserved1;
 328 };
 329
 330 struct ena_admin_acq_destroy_cq_resp_desc {
 331         struct ena_admin_acq_common_desc acq_common_desc;
 332 };
 333
 334 /* ENA AQ Get Statistics command. Extended statistics are placed in control
 335  * buffer pointed by AQ entry
 336  */
 337 struct ena_admin_aq_get_stats_cmd {
 338         struct ena_admin_aq_common_desc aq_common_descriptor;
 339
 340         union {
 341                 /* command specific inline data */
 342                 uint32_t inline_data_w1[3];
 343
 344                 struct ena_admin_ctrl_buff_info control_buffer;
 345         } u;
 346
 347         /* stats type as defined in enum ena_admin_get_stats_type */
 348         uint8_t type;
 349
 350         /* stats scope defined in enum ena_admin_get_stats_scope */
 351         uint8_t scope;
 352
 353         uint16_t reserved3;
 354
 355         /* queue id. used when scope is specific_queue */
 356         uint16_t queue_idx;
 357
 358         /* device id, value 0xFFFF means mine. only privileged device can get
 359          *    stats of other device
 360          */
 361         uint16_t device_id;
 362 };
 363
 364 /* Basic Statistics Command. */
 365 struct ena_admin_basic_stats {
 366         uint32_t tx_bytes_low;
 367
 368         uint32_t tx_bytes_high;
 369
 370         uint32_t tx_pkts_low;
 371
 372         uint32_t tx_pkts_high;
 373
 374         uint32_t rx_bytes_low;
 375
 376         uint32_t rx_bytes_high;
 377
 378         uint32_t rx_pkts_low;
 379
 380         uint32_t rx_pkts_high;
 381
 382         uint32_t rx_drops_low;
 383
 384         uint32_t rx_drops_high;
 385 };
 386
 387 struct ena_admin_acq_get_stats_resp {
 388         struct ena_admin_acq_common_desc acq_common_desc;
 389
 390         struct ena_admin_basic_stats basic_stats;
 391 };
 392
 393 struct ena_admin_get_set_feature_common_desc {
 394         /* 1:0 : select - 0x1 - current value; 0x3 - default
 395          *    value
 396          * 7:3 : reserved3
 397          */
 398         uint8_t flags;
 399
 400         /* as appears in ena_admin_aq_feature_id */
 401         uint8_t feature_id;
 402
 403         /* The driver specifies the max feature version it supports and the
 404          *    device responds with the currently supported feature version. The
 405          *    field is zero based
 406          */
 407         uint8_t feature_version;
 408
 409         uint8_t reserved8;
 410 };
 411
 412 struct ena_admin_device_attr_feature_desc {
 413         uint32_t impl_id;
 414
 415         uint32_t device_version;
 416
 417         /* bitmap of ena_admin_aq_feature_id */
 418         uint32_t supported_features;
 419
 420         uint32_t reserved3;
 421
 422         /* Indicates how many bits are used physical address access. */
 423         uint32_t phys_addr_width;
 424
 425         /* Indicates how many bits are used virtual address access. */
 426         uint32_t virt_addr_width;
 427
 428         /* unicast MAC address (in Network byte order) */
 429         uint8_t mac_addr[6];
 430
 431         uint8_t reserved7[2];
 432
 433         uint32_t max_mtu;
 434 };
 435
 436 enum ena_admin_llq_header_location {
 437         /* header is in descriptor list */
 438         ENA_ADMIN_INLINE_HEADER                     = 1,
 439         /* header in a separate ring, implies 16B descriptor list entry */
 440         ENA_ADMIN_HEADER_RING                       = 2,
 441 };
 442
 443 enum ena_admin_llq_ring_entry_size {
 444         ENA_ADMIN_LIST_ENTRY_SIZE_128B              = 1,
 445         ENA_ADMIN_LIST_ENTRY_SIZE_192B              = 2,
 446         ENA_ADMIN_LIST_ENTRY_SIZE_256B              = 4,
 447 };
 448
 449 enum ena_admin_llq_num_descs_before_header {
 450         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0     = 0,
 451         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1     = 1,
 452         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2     = 2,
 453         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4     = 4,
 454         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8     = 8,
 455 };
 456
 457 /* packet descriptor list entry always starts with one or more descriptors,
 458  * followed by a header. The rest of the descriptors are located in the
 459  * beginning of the subsequent entry. Stride refers to how the rest of the
 460  * descriptors are placed. This field is relevant only for inline header
 461  * mode
 462  */
 463 enum ena_admin_llq_stride_ctrl {
 464         ENA_ADMIN_SINGLE_DESC_PER_ENTRY             = 1,
 465         ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY          = 2,
 466 };
 467
 468 struct ena_admin_feature_llq_desc {
 469         uint32_t max_llq_num;
 470
 471         uint32_t max_llq_depth;
 472
 473         /*  specify the header locations the device supports. bitfield of
 474          *    enum ena_admin_llq_header_location.
 475          */
 476         uint16_t header_location_ctrl_supported;
 477
 478         /* the header location the driver selected to use. */
 479         uint16_t header_location_ctrl_enabled;
 480
 481         /* if inline header is specified - this is the size of descriptor
 482          *    list entry. If header in a separate ring is specified - this is
 483          *    the size of header ring entry. bitfield of enum
 484          *    ena_admin_llq_ring_entry_size. specify the entry sizes the device
 485          *    supports
 486          */
 487         uint16_t entry_size_ctrl_supported;
 488
 489         /* the entry size the driver selected to use. */
 490         uint16_t entry_size_ctrl_enabled;
 491
 492         /* valid only if inline header is specified. First entry associated
 493          *    with the packet includes descriptors and header. Rest of the
 494          *    entries occupied by descriptors. This parameter defines the max
 495          *    number of descriptors precedding the header in the first entry.
 496          *    The field is bitfield of enum
 497          *    ena_admin_llq_num_descs_before_header and specify the values the
 498          *    device supports
 499          */
 500         uint16_t desc_num_before_header_supported;
 501
 502         /* the desire field the driver selected to use */
 503         uint16_t desc_num_before_header_enabled;
 504
 505         /* valid only if inline was chosen. bitfield of enum
 506          *    ena_admin_llq_stride_ctrl
 507          */
 508         uint16_t descriptors_stride_ctrl_supported;
 509
 510         /* the stride control the driver selected to use */
 511         uint16_t descriptors_stride_ctrl_enabled;
 512
 513         /* Maximum size in bytes taken by llq entries in a single tx burst.
 514          * Set to 0 when there is no such limit.
 515          */
 516         uint32_t max_tx_burst_size;
 517 };
 518
 519 struct ena_admin_queue_ext_feature_fields {
 520         uint32_t max_tx_sq_num;
 521
 522         uint32_t max_tx_cq_num;
 523
 524         uint32_t max_rx_sq_num;
 525
 526         uint32_t max_rx_cq_num;
 527
 528         uint32_t max_tx_sq_depth;
 529
 530         uint32_t max_tx_cq_depth;
 531
 532         uint32_t max_rx_sq_depth;
 533
 534         uint32_t max_rx_cq_depth;
 535
 536         uint32_t max_tx_header_size;
 537
 538         /* Maximum Descriptors number, including meta descriptor, allowed for
 539          *    a single Tx packet
 540          */
 541         uint16_t max_per_packet_tx_descs;
 542
 543         /* Maximum Descriptors number allowed for a single Rx packet */
 544         uint16_t max_per_packet_rx_descs;
 545 };
 546
 547 struct ena_admin_queue_feature_desc {
 548         uint32_t max_sq_num;
 549
 550         uint32_t max_sq_depth;
 551
 552         uint32_t max_cq_num;
 553
 554         uint32_t max_cq_depth;
 555
 556         uint32_t max_legacy_llq_num;
 557
 558         uint32_t max_legacy_llq_depth;
 559
 560         uint32_t max_header_size;
 561
 562         /* Maximum Descriptors number, including meta descriptor, allowed for
 563          *    a single Tx packet
 564          */
 565         uint16_t max_packet_tx_descs;
 566
 567         /* Maximum Descriptors number allowed for a single Rx packet */
 568         uint16_t max_packet_rx_descs;
 569 };
 570
 571 struct ena_admin_set_feature_mtu_desc {
 572         /* exclude L2 */
 573         uint32_t mtu;
 574 };
 575
 576 struct ena_admin_get_extra_properties_strings_desc {
 577         uint32_t count;
 578 };
 579
 580 struct ena_admin_get_extra_properties_flags_desc {
 581         uint32_t flags;
 582 };
 583
 584 struct ena_admin_set_feature_host_attr_desc {
 585         /* host OS info base address in OS memory. host info is 4KB of
 586          * physically contiguous
 587          */
 588         struct ena_common_mem_addr os_info_ba;
 589
 590         /* host debug area base address in OS memory. debug area must be
 591          * physically contiguous
 592          */
 593         struct ena_common_mem_addr debug_ba;
 594
 595         /* debug area size */
 596         uint32_t debug_area_size;
 597 };
 598
 599 struct ena_admin_feature_intr_moder_desc {
 600         /* interrupt delay granularity in usec */
 601         uint16_t intr_delay_resolution;
 602
 603         uint16_t reserved;
 604 };
 605
 606 struct ena_admin_get_feature_link_desc {
 607         /* Link speed in Mb */
 608         uint32_t speed;
 609
 610         /* bit field of enum ena_admin_link types */
 611         uint32_t supported;
 612
 613         /* 0 : autoneg
 614          * 1 : duplex - Full Duplex
 615          * 31:2 : reserved2
 616          */
 617         uint32_t flags;
 618 };
 619
 620 struct ena_admin_feature_aenq_desc {
 621         /* bitmask for AENQ groups the device can report */
 622         uint32_t supported_groups;
 623
 624         /* bitmask for AENQ groups to report */
 625         uint32_t enabled_groups;
 626 };
 627
 628 struct ena_admin_feature_offload_desc {
 629         /* 0 : TX_L3_csum_ipv4
 630          * 1 : TX_L4_ipv4_csum_part - The checksum field
 631          *    should be initialized with pseudo header checksum
 632          * 2 : TX_L4_ipv4_csum_full
 633          * 3 : TX_L4_ipv6_csum_part - The checksum field
 634          *    should be initialized with pseudo header checksum
 635          * 4 : TX_L4_ipv6_csum_full
 636          * 5 : tso_ipv4
 637          * 6 : tso_ipv6
 638          * 7 : tso_ecn
 639          */
 640         uint32_t tx;
 641
 642         /* Receive side supported stateless offload
 643          * 0 : RX_L3_csum_ipv4 - IPv4 checksum
 644          * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
 645          * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
 646          * 3 : RX_hash - Hash calculation
 647          */
 648         uint32_t rx_supported;
 649
 650         uint32_t rx_enabled;
 651 };
 652
 653 enum ena_admin_hash_functions {
 654         ENA_ADMIN_TOEPLITZ                          = 1,
 655         ENA_ADMIN_CRC32                             = 2,
 656 };
 657
 658 struct ena_admin_feature_rss_flow_hash_control {
 659         uint32_t keys_num;
 660
 661         uint32_t reserved;
 662
 663         uint32_t key[10];
 664 };
 665
 666 struct ena_admin_feature_rss_flow_hash_function {
 667         /* 7:0 : funcs - bitmask of ena_admin_hash_functions */
 668         uint32_t supported_func;
 669
 670         /* 7:0 : selected_func - bitmask of
 671          *    ena_admin_hash_functions
 672          */
 673         uint32_t selected_func;
 674
 675         /* initial value */
 676         uint32_t init_val;
 677 };
 678
 679 /* RSS flow hash protocols */
 680 enum ena_admin_flow_hash_proto {
 681         ENA_ADMIN_RSS_TCP4                          = 0,
 682         ENA_ADMIN_RSS_UDP4                          = 1,
 683         ENA_ADMIN_RSS_TCP6                          = 2,
 684         ENA_ADMIN_RSS_UDP6                          = 3,
 685         ENA_ADMIN_RSS_IP4                           = 4,
 686         ENA_ADMIN_RSS_IP6                           = 5,
 687         ENA_ADMIN_RSS_IP4_FRAG                      = 6,
 688         ENA_ADMIN_RSS_NOT_IP                        = 7,
 689         /* TCPv6 with extension header */
 690         ENA_ADMIN_RSS_TCP6_EX                       = 8,
 691         /* IPv6 with extension header */
 692         ENA_ADMIN_RSS_IP6_EX                        = 9,
 693         ENA_ADMIN_RSS_PROTO_NUM                     = 16,
 694 };
 695
 696 /* RSS flow hash fields */
 697 enum ena_admin_flow_hash_fields {
 698         /* Ethernet Dest Addr */
 699         ENA_ADMIN_RSS_L2_DA                         = BIT(0),
 700         /* Ethernet Src Addr */
 701         ENA_ADMIN_RSS_L2_SA                         = BIT(1),
 702         /* ipv4/6 Dest Addr */
 703         ENA_ADMIN_RSS_L3_DA                         = BIT(2),
 704         /* ipv4/6 Src Addr */
 705         ENA_ADMIN_RSS_L3_SA                         = BIT(3),
 706         /* tcp/udp Dest Port */
 707         ENA_ADMIN_RSS_L4_DP                         = BIT(4),
 708         /* tcp/udp Src Port */
 709         ENA_ADMIN_RSS_L4_SP                         = BIT(5),
 710 };
 711
 712 struct ena_admin_proto_input {
 713         /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
 714         uint16_t fields;
 715
 716         uint16_t reserved2;
 717 };
 718
 719 struct ena_admin_feature_rss_hash_control {
 720         struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
 721
 722         struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
 723
 724         struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
 725
 726         struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
 727 };
 728
 729 struct ena_admin_feature_rss_flow_hash_input {
 730         /* supported hash input sorting
 731          * 1 : L3_sort - support swap L3 addresses if DA is
 732          *    smaller than SA
 733          * 2 : L4_sort - support swap L4 ports if DP smaller
 734          *    SP
 735          */
 736         uint16_t supported_input_sort;
 737
 738         /* enabled hash input sorting
 739          * 1 : enable_L3_sort - enable swap L3 addresses if
 740          *    DA smaller than SA
 741          * 2 : enable_L4_sort - enable swap L4 ports if DP
 742          *    smaller than SP
 743          */
 744         uint16_t enabled_input_sort;
 745 };
 746
 747 enum ena_admin_os_type {
 748         ENA_ADMIN_OS_LINUX                          = 1,
 749         ENA_ADMIN_OS_WIN                            = 2,
 750         ENA_ADMIN_OS_DPDK                           = 3,
 751         ENA_ADMIN_OS_FREEBSD                        = 4,
 752         ENA_ADMIN_OS_IPXE                           = 5,
 753         ENA_ADMIN_OS_ESXI                           = 6,
 754         ENA_ADMIN_OS_GROUPS_NUM                     = 6,
 755 };
 756
 757 struct ena_admin_host_info {
 758         /* defined in enum ena_admin_os_type */
 759         uint32_t os_type;
 760
 761         /* os distribution string format */
 762         uint8_t os_dist_str[128];
 763
 764         /* OS distribution numeric format */
 765         uint32_t os_dist;
 766
 767         /* kernel version string format */
 768         uint8_t kernel_ver_str[32];
 769
 770         /* Kernel version numeric format */
 771         uint32_t kernel_ver;
 772
 773         /* 7:0 : major
 774          * 15:8 : minor
 775          * 23:16 : sub_minor
 776          * 31:24 : module_type
 777          */
 778         uint32_t driver_version;
 779
 780         /* features bitmap */
 781         uint32_t supported_network_features[2];
 782
 783         /* ENA spec version of driver */
 784         uint16_t ena_spec_version;
 785
 786         /* ENA device's Bus, Device and Function
 787          * 2:0 : function
 788          * 7:3 : device
 789          * 15:8 : bus
 790          */
 791         uint16_t bdf;
 792
 793         /* Number of CPUs */
 794         uint16_t num_cpus;
 795
 796         uint16_t reserved;
 797 };
 798
 799 struct ena_admin_rss_ind_table_entry {
 800         uint16_t cq_idx;
 801
 802         uint16_t reserved;
 803 };
 804
 805 struct ena_admin_feature_rss_ind_table {
 806         /* min supported table size (2^min_size) */
 807         uint16_t min_size;
 808
 809         /* max supported table size (2^max_size) */
 810         uint16_t max_size;
 811
 812         /* table size (2^size) */
 813         uint16_t size;
 814
 815         /* 0 : one_entry_update - The FW supports setting a
 816          *    single RSS table entry
 817          */
 818         uint8_t flags;
 819
 820         uint8_t reserved;
 821
 822         /* index of the inline entry. 0xFFFFFFFF means invalid */
 823         uint32_t inline_index;
 824
 825         /* used for updating single entry, ignored when setting the entire
 826          * table through the control buffer.
 827          */
 828         struct ena_admin_rss_ind_table_entry inline_entry;
 829 };
 830
 831 /* When hint value is 0, driver should use it's own predefined value */
 832 struct ena_admin_ena_hw_hints {
 833         /* value in ms */
 834         uint16_t mmio_read_timeout;
 835
 836         /* value in ms */
 837         uint16_t driver_watchdog_timeout;
 838
 839         /* Per packet tx completion timeout. value in ms */
 840         uint16_t missing_tx_completion_timeout;
 841
 842         uint16_t missed_tx_completion_count_threshold_to_reset;
 843
 844         /* value in ms */
 845         uint16_t admin_completion_tx_timeout;
 846
 847         uint16_t netdev_wd_timeout;
 848
 849         uint16_t max_tx_sgl_size;
 850
 851         uint16_t max_rx_sgl_size;
 852
 853         uint16_t reserved[8];
 854 };
 855
 856 struct ena_admin_get_feat_cmd {
 857         struct ena_admin_aq_common_desc aq_common_descriptor;
 858
 859         struct ena_admin_ctrl_buff_info control_buffer;
 860
 861         struct ena_admin_get_set_feature_common_desc feat_common;
 862
 863         uint32_t raw[11];
 864 };
 865
 866 struct ena_admin_queue_ext_feature_desc {
 867         /* version */
 868         uint8_t version;
 869
 870         uint8_t reserved1[3];
 871
 872         union {
 873                 struct ena_admin_queue_ext_feature_fields max_queue_ext;
 874
 875                 uint32_t raw[10];
 876         } ;
 877 };
 878
 879 struct ena_admin_get_feat_resp {
 880         struct ena_admin_acq_common_desc acq_common_desc;
 881
 882         union {
 883                 uint32_t raw[14];
 884
 885                 struct ena_admin_device_attr_feature_desc dev_attr;
 886
 887                 struct ena_admin_feature_llq_desc llq;
 888
 889                 struct ena_admin_queue_feature_desc max_queue;
 890
 891                 struct ena_admin_queue_ext_feature_desc max_queue_ext;
 892
 893                 struct ena_admin_feature_aenq_desc aenq;
 894
 895                 struct ena_admin_get_feature_link_desc link;
 896
 897                 struct ena_admin_feature_offload_desc offload;
 898
 899                 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
 900
 901                 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
 902
 903                 struct ena_admin_feature_rss_ind_table ind_table;
 904
 905                 struct ena_admin_feature_intr_moder_desc intr_moderation;
 906
 907                 struct ena_admin_ena_hw_hints hw_hints;
 908
 909                 struct ena_admin_get_extra_properties_strings_desc extra_properties_strings;
 910
 911                 struct ena_admin_get_extra_properties_flags_desc extra_properties_flags;
 912         } u;
 913 };
 914
 915 struct ena_admin_set_feat_cmd {
 916         struct ena_admin_aq_common_desc aq_common_descriptor;
 917
 918         struct ena_admin_ctrl_buff_info control_buffer;
 919
 920         struct ena_admin_get_set_feature_common_desc feat_common;
 921
 922         union {
 923                 uint32_t raw[11];
 924
 925                 /* mtu size */
 926                 struct ena_admin_set_feature_mtu_desc mtu;
 927
 928                 /* host attributes */
 929                 struct ena_admin_set_feature_host_attr_desc host_attr;
 930
 931                 /* AENQ configuration */
 932                 struct ena_admin_feature_aenq_desc aenq;
 933
 934                 /* rss flow hash function */
 935                 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
 936
 937                 /* rss flow hash input */
 938                 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
 939
 940                 /* rss indirection table */
 941                 struct ena_admin_feature_rss_ind_table ind_table;
 942
 943                 /* LLQ configuration */
 944                 struct ena_admin_feature_llq_desc llq;
 945         } u;
 946 };
 947
 948 struct ena_admin_set_feat_resp {
 949         struct ena_admin_acq_common_desc acq_common_desc;
 950
 951         union {
 952                 uint32_t raw[14];
 953         } u;
 954 };
 955
 956 struct ena_admin_aenq_common_desc {
 957         uint16_t group;
 958
 959         uint16_t syndrom;
 960
 961         /* 0 : phase
 962          * 7:1 : reserved - MBZ
 963          */
 964         uint8_t flags;
 965
 966         uint8_t reserved1[3];
 967
 968         uint32_t timestamp_low;
 969
 970         uint32_t timestamp_high;
 971 };
 972
 973 /* asynchronous event notification groups */
 974 enum ena_admin_aenq_group {
 975         ENA_ADMIN_LINK_CHANGE                       = 0,
 976         ENA_ADMIN_FATAL_ERROR                       = 1,
 977         ENA_ADMIN_WARNING                           = 2,
 978         ENA_ADMIN_NOTIFICATION                      = 3,
 979         ENA_ADMIN_KEEP_ALIVE                        = 4,
 980         ENA_ADMIN_AENQ_GROUPS_NUM                   = 5,
 981 };
 982
 983 enum ena_admin_aenq_notification_syndrom {
 984         ENA_ADMIN_SUSPEND                           = 0,
 985         ENA_ADMIN_RESUME                            = 1,
 986         ENA_ADMIN_UPDATE_HINTS                      = 2,
 987 };
 988
 989 struct ena_admin_aenq_entry {
 990         struct ena_admin_aenq_common_desc aenq_common_desc;
 991
 992         /* command specific inline data */
 993         uint32_t inline_data_w4[12];
 994 };
 995
 996 struct ena_admin_aenq_link_change_desc {
 997         struct ena_admin_aenq_common_desc aenq_common_desc;
 998
 999         /* 0 : link_status */
1000         uint32_t flags;
1001 };
1002
1003 struct ena_admin_aenq_keep_alive_desc {
1004         struct ena_admin_aenq_common_desc aenq_common_desc;
1005
1006         uint32_t rx_drops_low;
1007
1008         uint32_t rx_drops_high;
1009 };
1010
1011 struct ena_admin_ena_mmio_req_read_less_resp {
1012         uint16_t req_id;
1013
1014         uint16_t reg_off;
1015
1016         /* value is valid when poll is cleared */
1017         uint32_t reg_val;
1018 };
1019
1020 /* aq_common_desc */
1021 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK            GENMASK(11, 0)
1022 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK                 BIT(0)
1023 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT            1
1024 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK             BIT(1)
1025 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT   2
1026 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK    BIT(2)
1027
1028 /* sq */
1029 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT                     5
1030 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK                      GENMASK(7, 5)
1031
1032 /* acq_common_desc */
1033 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK           GENMASK(11, 0)
1034 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK                BIT(0)
1035
1036 /* aq_create_sq_cmd */
1037 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT       5
1038 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK        GENMASK(7, 5)
1039 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK    GENMASK(3, 0)
1040 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT  4
1041 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK   GENMASK(6, 4)
1042 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1043
1044 /* aq_create_cq_cmd */
1045 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
1046 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
1047 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1048
1049 /* get_set_feature_common_desc */
1050 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK   GENMASK(1, 0)
1051
1052 /* get_feature_link_desc */
1053 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK        BIT(0)
1054 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT        1
1055 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK         BIT(1)
1056
1057 /* feature_offload_desc */
1058 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
1059 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
1060 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1061 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
1062 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1063 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
1064 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1065 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1066 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1067 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT       5
1068 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK        BIT(5)
1069 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT       6
1070 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK        BIT(6)
1071 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT        7
1072 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK         BIT(7)
1073 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1074 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1075 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1076 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1077 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1078 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT        3
1079 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK         BIT(3)
1080
1081 /* feature_rss_flow_hash_function */
1082 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1083 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
1084
1085 /* feature_rss_flow_hash_input */
1086 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1087 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK  BIT(1)
1088 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1089 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK  BIT(2)
1090 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1091 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1092 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1093 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1094
1095 /* host_info */
1096 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK                      GENMASK(7, 0)
1097 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT                     8
1098 #define ENA_ADMIN_HOST_INFO_MINOR_MASK                      GENMASK(15, 8)
1099 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT                 16
1100 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK                  GENMASK(23, 16)
1101 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT               24
1102 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK                GENMASK(31, 24)
1103 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK                   GENMASK(2, 0)
1104 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT                    3
1105 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK                     GENMASK(7, 3)
1106 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT                       8
1107 #define ENA_ADMIN_HOST_INFO_BUS_MASK                        GENMASK(15, 8)
1108
1109 /* feature_rss_ind_table */
1110 #define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0)
1111
1112 /* aenq_common_desc */
1113 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK               BIT(0)
1114
1115 /* aenq_link_change_desc */
1116 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK    BIT(0)
1117
1118 #if !defined(DEFS_LINUX_MAINLINE)
1119 static inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p)
1120 {
1121         return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1122 }
1123
1124 static inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val)
1125 {
1126         p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1127 }
1128
1129 static inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p)
1130 {
1131         return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1132 }
1133
1134 static inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val)
1135 {
1136         p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1137 }
1138
1139 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p)
1140 {
1141         return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT;
1142 }
1143
1144 static inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val)
1145 {
1146         p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK;
1147 }
1148
1149 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p)
1150 {
1151         return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT;
1152 }
1153
1154 static inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val)
1155 {
1156         p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1157 }
1158
1159 static inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p)
1160 {
1161         return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT;
1162 }
1163
1164 static inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val)
1165 {
1166         p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
1167 }
1168
1169 static inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p)
1170 {
1171         return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1172 }
1173
1174 static inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val)
1175 {
1176         p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1177 }
1178
1179 static inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p)
1180 {
1181         return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1182 }
1183
1184 static inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val)
1185 {
1186         p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1187 }
1188
1189 static inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p)
1190 {
1191         return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT;
1192 }
1193
1194 static inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1195 {
1196         p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1197 }
1198
1199 static inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p)
1200 {
1201         return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1202 }
1203
1204 static inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1205 {
1206         p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1207 }
1208
1209 static inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p)
1210 {
1211         return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT;
1212 }
1213
1214 static inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1215 {
1216         p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1217 }
1218
1219 static inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p)
1220 {
1221         return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1222 }
1223
1224 static inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1225 {
1226         p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1227 }
1228
1229 static inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p)
1230 {
1231         return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT;
1232 }
1233
1234 static inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1235 {
1236         p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1237 }
1238
1239 static inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p)
1240 {
1241         return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1242 }
1243
1244 static inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1245 {
1246         p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1247 }
1248
1249 static inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p)
1250 {
1251         return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1252 }
1253
1254 static inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val)
1255 {
1256         p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1257 }
1258
1259 static inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p)
1260 {
1261         return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1262 }
1263
1264 static inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1265 {
1266         p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1267 }
1268
1269 static inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p)
1270 {
1271         return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT;
1272 }
1273
1274 static inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1275 {
1276         p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK;
1277 }
1278
1279 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1280 {
1281         return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1282 }
1283
1284 static inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1285 {
1286         p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1287 }
1288
1289 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p)
1290 {
1291         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT;
1292 }
1293
1294 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1295 {
1296         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK;
1297 }
1298
1299 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p)
1300 {
1301         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT;
1302 }
1303
1304 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1305 {
1306         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK;
1307 }
1308
1309 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p)
1310 {
1311         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT;
1312 }
1313
1314 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1315 {
1316         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK;
1317 }
1318
1319 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p)
1320 {
1321         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT;
1322 }
1323
1324 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1325 {
1326         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK;
1327 }
1328
1329 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p)
1330 {
1331         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT;
1332 }
1333
1334 static inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1335 {
1336         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1337 }
1338
1339 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p)
1340 {
1341         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT;
1342 }
1343
1344 static inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val)
1345 {
1346         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK;
1347 }
1348
1349 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p)
1350 {
1351         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT;
1352 }
1353
1354 static inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val)
1355 {
1356         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK;
1357 }
1358
1359 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1360 {
1361         return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1362 }
1363
1364 static inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1365 {
1366         p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1367 }
1368
1369 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p)
1370 {
1371         return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT;
1372 }
1373
1374 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1375 {
1376         p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK;
1377 }
1378
1379 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p)
1380 {
1381         return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT;
1382 }
1383
1384 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1385 {
1386         p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK;
1387 }
1388
1389 static inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p)
1390 {
1391         return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT;
1392 }
1393
1394 static inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val)
1395 {
1396         p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK;
1397 }
1398
1399 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p)
1400 {
1401         return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1402 }
1403
1404 static inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1405 {
1406         p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1407 }
1408
1409 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p)
1410 {
1411         return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1412 }
1413
1414 static inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1415 {
1416         p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1417 }
1418
1419 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1420 {
1421         return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT;
1422 }
1423
1424 static inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1425 {
1426         p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;
1427 }
1428
1429 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1430 {
1431         return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT;
1432 }
1433
1434 static inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1435 {
1436         p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
1437 }
1438
1439 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1440 {
1441         return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT;
1442 }
1443
1444 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1445 {
1446         p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK;
1447 }
1448
1449 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1450 {
1451         return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT;
1452 }
1453
1454 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1455 {
1456         p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK;
1457 }
1458
1459 static inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p)
1460 {
1461         return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1462 }
1463
1464 static inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val)
1465 {
1466         p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1467 }
1468
1469 static inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p)
1470 {
1471         return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT;
1472 }
1473
1474 static inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val)
1475 {
1476         p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK;
1477 }
1478
1479 static inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p)
1480 {
1481         return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT;
1482 }
1483
1484 static inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val)
1485 {
1486         p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK;
1487 }
1488
1489 static inline uint32_t get_ena_admin_host_info_module_type(const struct ena_admin_host_info *p)
1490 {
1491         return (p->driver_version & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK) >> ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT;
1492 }
1493
1494 static inline void set_ena_admin_host_info_module_type(struct ena_admin_host_info *p, uint32_t val)
1495 {
1496         p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT) & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK;
1497 }
1498
1499 static inline uint16_t get_ena_admin_host_info_function(const struct ena_admin_host_info *p)
1500 {
1501         return p->bdf & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1502 }
1503
1504 static inline void set_ena_admin_host_info_function(struct ena_admin_host_info *p, uint16_t val)
1505 {
1506         p->bdf |= val & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1507 }
1508
1509 static inline uint16_t get_ena_admin_host_info_device(const struct ena_admin_host_info *p)
1510 {
1511         return (p->bdf & ENA_ADMIN_HOST_INFO_DEVICE_MASK) >> ENA_ADMIN_HOST_INFO_DEVICE_SHIFT;
1512 }
1513
1514 static inline void set_ena_admin_host_info_device(struct ena_admin_host_info *p, uint16_t val)
1515 {
1516         p->bdf |= (val << ENA_ADMIN_HOST_INFO_DEVICE_SHIFT) & ENA_ADMIN_HOST_INFO_DEVICE_MASK;
1517 }
1518
1519 static inline uint16_t get_ena_admin_host_info_bus(const struct ena_admin_host_info *p)
1520 {
1521         return (p->bdf & ENA_ADMIN_HOST_INFO_BUS_MASK) >> ENA_ADMIN_HOST_INFO_BUS_SHIFT;
1522 }
1523
1524 static inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, uint16_t val)
1525 {
1526         p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK;
1527 }
1528
1529 static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p)
1530 {
1531         return p->flags & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1532 }
1533
1534 static inline void set_ena_admin_feature_rss_ind_table_one_entry_update(struct ena_admin_feature_rss_ind_table *p, uint8_t val)
1535 {
1536         p->flags |= val & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1537 }
1538
1539 static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p)
1540 {
1541         return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1542 }
1543
1544 static inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val)
1545 {
1546         p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1547 }
1548
1549 static inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p)
1550 {
1551         return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1552 }
1553
1554 static inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val)
1555 {
1556         p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1557 }
1558
1559 #endif /* !defined(DEFS_LINUX_MAINLINE) */
1560 #endif /*_ENA_ADMIN_H_ */