drivers/net/ena/base/ena_defs/ena_admin_defs.h

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33 #ifndef _ENA_ADMIN_H_
  34 #define _ENA_ADMIN_H_
  35
  36 #define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32
  37 #define ENA_ADMIN_EXTRA_PROPERTIES_COUNT     32
  38
  39 enum ena_admin_aq_opcode {
  40         ENA_ADMIN_CREATE_SQ                         = 1,
  41         ENA_ADMIN_DESTROY_SQ                        = 2,
  42         ENA_ADMIN_CREATE_CQ                         = 3,
  43         ENA_ADMIN_DESTROY_CQ                        = 4,
  44         ENA_ADMIN_GET_FEATURE                       = 8,
  45         ENA_ADMIN_SET_FEATURE                       = 9,
  46         ENA_ADMIN_GET_STATS                         = 11,
  47 };
  48
  49 enum ena_admin_aq_completion_status {
  50         ENA_ADMIN_SUCCESS                           = 0,
  51         ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE       = 1,
  52         ENA_ADMIN_BAD_OPCODE                        = 2,
  53         ENA_ADMIN_UNSUPPORTED_OPCODE                = 3,
  54         ENA_ADMIN_MALFORMED_REQUEST                 = 4,
  55         /* Additional status is provided in ACQ entry extended_status */
  56         ENA_ADMIN_ILLEGAL_PARAMETER                 = 5,
  57         ENA_ADMIN_UNKNOWN_ERROR                     = 6,
  58         ENA_ADMIN_RESOURCE_BUSY                     = 7,
  59 };
  60
  61 enum ena_admin_aq_feature_id {
  62         ENA_ADMIN_DEVICE_ATTRIBUTES                 = 1,
  63         ENA_ADMIN_MAX_QUEUES_NUM                    = 2,
  64         ENA_ADMIN_HW_HINTS                          = 3,
  65         ENA_ADMIN_LLQ                               = 4,
  66         ENA_ADMIN_EXTRA_PROPERTIES_STRINGS          = 5,
  67         ENA_ADMIN_EXTRA_PROPERTIES_FLAGS            = 6,
  68         ENA_ADMIN_MAX_QUEUES_EXT                    = 7,
  69         ENA_ADMIN_RSS_HASH_FUNCTION                 = 10,
  70         ENA_ADMIN_STATELESS_OFFLOAD_CONFIG          = 11,
  71         ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG      = 12,
  72         ENA_ADMIN_MTU                               = 14,
  73         ENA_ADMIN_RSS_HASH_INPUT                    = 18,
  74         ENA_ADMIN_INTERRUPT_MODERATION              = 20,
  75         ENA_ADMIN_AENQ_CONFIG                       = 26,
  76         ENA_ADMIN_LINK_CONFIG                       = 27,
  77         ENA_ADMIN_HOST_ATTR_CONFIG                  = 28,
  78         ENA_ADMIN_FEATURES_OPCODE_NUM               = 32,
  79 };
  80
  81 enum ena_admin_placement_policy_type {
  82         /* descriptors and headers are in host memory */
  83         ENA_ADMIN_PLACEMENT_POLICY_HOST             = 1,
  84         /* descriptors and headers are in device memory (a.k.a Low Latency
  85          * Queue)
  86          */
  87         ENA_ADMIN_PLACEMENT_POLICY_DEV              = 3,
  88 };
  89
  90 enum ena_admin_link_types {
  91         ENA_ADMIN_LINK_SPEED_1G                     = 0x1,
  92         ENA_ADMIN_LINK_SPEED_2_HALF_G               = 0x2,
  93         ENA_ADMIN_LINK_SPEED_5G                     = 0x4,
  94         ENA_ADMIN_LINK_SPEED_10G                    = 0x8,
  95         ENA_ADMIN_LINK_SPEED_25G                    = 0x10,
  96         ENA_ADMIN_LINK_SPEED_40G                    = 0x20,
  97         ENA_ADMIN_LINK_SPEED_50G                    = 0x40,
  98         ENA_ADMIN_LINK_SPEED_100G                   = 0x80,
  99         ENA_ADMIN_LINK_SPEED_200G                   = 0x100,
 100         ENA_ADMIN_LINK_SPEED_400G                   = 0x200,
 101 };
 102
 103 enum ena_admin_completion_policy_type {
 104         /* completion queue entry for each sq descriptor */
 105         ENA_ADMIN_COMPLETION_POLICY_DESC            = 0,
 106         /* completion queue entry upon request in sq descriptor */
 107         ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND  = 1,
 108         /* current queue head pointer is updated in OS memory upon sq
 109          * descriptor request
 110          */
 111         ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND  = 2,
 112         /* current queue head pointer is updated in OS memory for each sq
 113          * descriptor
 114          */
 115         ENA_ADMIN_COMPLETION_POLICY_HEAD            = 3,
 116 };
 117
 118 /* basic stats return ena_admin_basic_stats while extanded stats return a
 119  * buffer (string format) with additional statistics per queue and per
 120  * device id
 121  */
 122 enum ena_admin_get_stats_type {
 123         ENA_ADMIN_GET_STATS_TYPE_BASIC              = 0,
 124         ENA_ADMIN_GET_STATS_TYPE_EXTENDED           = 1,
 125 };
 126
 127 enum ena_admin_get_stats_scope {
 128         ENA_ADMIN_SPECIFIC_QUEUE                    = 0,
 129         ENA_ADMIN_ETH_TRAFFIC                       = 1,
 130 };
 131
 132 struct ena_admin_aq_common_desc {
 133         /* 11:0 : command_id
 134          * 15:12 : reserved12
 135          */
 136         uint16_t command_id;
 137
 138         /* as appears in ena_admin_aq_opcode */
 139         uint8_t opcode;
 140
 141         /* 0 : phase
 142          * 1 : ctrl_data - control buffer address valid
 143          * 2 : ctrl_data_indirect - control buffer address
 144          *    points to list of pages with addresses of control
 145          *    buffers
 146          * 7:3 : reserved3
 147          */
 148         uint8_t flags;
 149 };
 150
 151 /* used in ena_admin_aq_entry. Can point directly to control data, or to a
 152  * page list chunk. Used also at the end of indirect mode page list chunks,
 153  * for chaining.
 154  */
 155 struct ena_admin_ctrl_buff_info {
 156         uint32_t length;
 157
 158         struct ena_common_mem_addr address;
 159 };
 160
 161 struct ena_admin_sq {
 162         uint16_t sq_idx;
 163
 164         /* 4:0 : reserved
 165          * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
 166          */
 167         uint8_t sq_identity;
 168
 169         uint8_t reserved1;
 170 };
 171
 172 struct ena_admin_aq_entry {
 173         struct ena_admin_aq_common_desc aq_common_descriptor;
 174
 175         union {
 176                 uint32_t inline_data_w1[3];
 177
 178                 struct ena_admin_ctrl_buff_info control_buffer;
 179         } u;
 180
 181         uint32_t inline_data_w4[12];
 182 };
 183
 184 struct ena_admin_acq_common_desc {
 185         /* command identifier to associate it with the aq descriptor
 186          * 11:0 : command_id
 187          * 15:12 : reserved12
 188          */
 189         uint16_t command;
 190
 191         uint8_t status;
 192
 193         /* 0 : phase
 194          * 7:1 : reserved1
 195          */
 196         uint8_t flags;
 197
 198         uint16_t extended_status;
 199
 200         /* indicates to the driver which AQ entry has been consumed by the
 201          *    device and could be reused
 202          */
 203         uint16_t sq_head_indx;
 204 };
 205
 206 struct ena_admin_acq_entry {
 207         struct ena_admin_acq_common_desc acq_common_descriptor;
 208
 209         uint32_t response_specific_data[14];
 210 };
 211
 212 struct ena_admin_aq_create_sq_cmd {
 213         struct ena_admin_aq_common_desc aq_common_descriptor;
 214
 215         /* 4:0 : reserved0_w1
 216          * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
 217          */
 218         uint8_t sq_identity;
 219
 220         uint8_t reserved8_w1;
 221
 222         /* 3:0 : placement_policy - Describing where the SQ
 223          *    descriptor ring and the SQ packet headers reside:
 224          *    0x1 - descriptors and headers are in OS memory,
 225          *    0x3 - descriptors and headers in device memory
 226          *    (a.k.a Low Latency Queue)
 227          * 6:4 : completion_policy - Describing what policy
 228          *    to use for generation completion entry (cqe) in
 229          *    the CQ associated with this SQ: 0x0 - cqe for each
 230          *    sq descriptor, 0x1 - cqe upon request in sq
 231          *    descriptor, 0x2 - current queue head pointer is
 232          *    updated in OS memory upon sq descriptor request
 233          *    0x3 - current queue head pointer is updated in OS
 234          *    memory for each sq descriptor
 235          * 7 : reserved15_w1
 236          */
 237         uint8_t sq_caps_2;
 238
 239         /* 0 : is_physically_contiguous - Described if the
 240          *    queue ring memory is allocated in physical
 241          *    contiguous pages or split.
 242          * 7:1 : reserved17_w1
 243          */
 244         uint8_t sq_caps_3;
 245
 246         /* associated completion queue id. This CQ must be created prior to
 247          *    SQ creation
 248          */
 249         uint16_t cq_idx;
 250
 251         /* submission queue depth in entries */
 252         uint16_t sq_depth;
 253
 254         /* SQ physical base address in OS memory. This field should not be
 255          * used for Low Latency queues. Has to be page aligned.
 256          */
 257         struct ena_common_mem_addr sq_ba;
 258
 259         /* specifies queue head writeback location in OS memory. Valid if
 260          * completion_policy is set to completion_policy_head_on_demand or
 261          * completion_policy_head. Has to be cache aligned
 262          */
 263         struct ena_common_mem_addr sq_head_writeback;
 264
 265         uint32_t reserved0_w7;
 266
 267         uint32_t reserved0_w8;
 268 };
 269
 270 enum ena_admin_sq_direction {
 271         ENA_ADMIN_SQ_DIRECTION_TX                   = 1,
 272         ENA_ADMIN_SQ_DIRECTION_RX                   = 2,
 273 };
 274
 275 struct ena_admin_acq_create_sq_resp_desc {
 276         struct ena_admin_acq_common_desc acq_common_desc;
 277
 278         uint16_t sq_idx;
 279
 280         uint16_t reserved;
 281
 282         /* queue doorbell address as an offset to PCIe MMIO REG BAR */
 283         uint32_t sq_doorbell_offset;
 284
 285         /* low latency queue ring base address as an offset to PCIe MMIO
 286          * LLQ_MEM BAR
 287          */
 288         uint32_t llq_descriptors_offset;
 289
 290         /* low latency queue headers' memory as an offset to PCIe MMIO
 291          * LLQ_MEM BAR
 292          */
 293         uint32_t llq_headers_offset;
 294 };
 295
 296 struct ena_admin_aq_destroy_sq_cmd {
 297         struct ena_admin_aq_common_desc aq_common_descriptor;
 298
 299         struct ena_admin_sq sq;
 300 };
 301
 302 struct ena_admin_acq_destroy_sq_resp_desc {
 303         struct ena_admin_acq_common_desc acq_common_desc;
 304 };
 305
 306 struct ena_admin_aq_create_cq_cmd {
 307         struct ena_admin_aq_common_desc aq_common_descriptor;
 308
 309         /* 4:0 : reserved5
 310          * 5 : interrupt_mode_enabled - if set, cq operates
 311          *    in interrupt mode, otherwise - polling
 312          * 7:6 : reserved6
 313          */
 314         uint8_t cq_caps_1;
 315
 316         /* 4:0 : cq_entry_size_words - size of CQ entry in
 317          *    32-bit words, valid values: 4, 8.
 318          * 7:5 : reserved7
 319          */
 320         uint8_t cq_caps_2;
 321
 322         /* completion queue depth in # of entries. must be power of 2 */
 323         uint16_t cq_depth;
 324
 325         /* msix vector assigned to this cq */
 326         uint32_t msix_vector;
 327
 328         /* cq physical base address in OS memory. CQ must be physically
 329          * contiguous
 330          */
 331         struct ena_common_mem_addr cq_ba;
 332 };
 333
 334 struct ena_admin_acq_create_cq_resp_desc {
 335         struct ena_admin_acq_common_desc acq_common_desc;
 336
 337         uint16_t cq_idx;
 338
 339         /* actual cq depth in number of entries */
 340         uint16_t cq_actual_depth;
 341
 342         uint32_t numa_node_register_offset;
 343
 344         uint32_t cq_head_db_register_offset;
 345
 346         uint32_t cq_interrupt_unmask_register_offset;
 347 };
 348
 349 struct ena_admin_aq_destroy_cq_cmd {
 350         struct ena_admin_aq_common_desc aq_common_descriptor;
 351
 352         uint16_t cq_idx;
 353
 354         uint16_t reserved1;
 355 };
 356
 357 struct ena_admin_acq_destroy_cq_resp_desc {
 358         struct ena_admin_acq_common_desc acq_common_desc;
 359 };
 360
 361 /* ENA AQ Get Statistics command. Extended statistics are placed in control
 362  * buffer pointed by AQ entry
 363  */
 364 struct ena_admin_aq_get_stats_cmd {
 365         struct ena_admin_aq_common_desc aq_common_descriptor;
 366
 367         union {
 368                 /* command specific inline data */
 369                 uint32_t inline_data_w1[3];
 370
 371                 struct ena_admin_ctrl_buff_info control_buffer;
 372         } u;
 373
 374         /* stats type as defined in enum ena_admin_get_stats_type */
 375         uint8_t type;
 376
 377         /* stats scope defined in enum ena_admin_get_stats_scope */
 378         uint8_t scope;
 379
 380         uint16_t reserved3;
 381
 382         /* queue id. used when scope is specific_queue */
 383         uint16_t queue_idx;
 384
 385         /* device id, value 0xFFFF means mine. only privileged device can get
 386          *    stats of other device
 387          */
 388         uint16_t device_id;
 389 };
 390
 391 /* Basic Statistics Command. */
 392 struct ena_admin_basic_stats {
 393         uint32_t tx_bytes_low;
 394
 395         uint32_t tx_bytes_high;
 396
 397         uint32_t tx_pkts_low;
 398
 399         uint32_t tx_pkts_high;
 400
 401         uint32_t rx_bytes_low;
 402
 403         uint32_t rx_bytes_high;
 404
 405         uint32_t rx_pkts_low;
 406
 407         uint32_t rx_pkts_high;
 408
 409         uint32_t rx_drops_low;
 410
 411         uint32_t rx_drops_high;
 412 };
 413
 414 struct ena_admin_acq_get_stats_resp {
 415         struct ena_admin_acq_common_desc acq_common_desc;
 416
 417         struct ena_admin_basic_stats basic_stats;
 418 };
 419
 420 struct ena_admin_get_set_feature_common_desc {
 421         /* 1:0 : select - 0x1 - current value; 0x3 - default
 422          *    value
 423          * 7:3 : reserved3
 424          */
 425         uint8_t flags;
 426
 427         /* as appears in ena_admin_aq_feature_id */
 428         uint8_t feature_id;
 429
 430         /* The driver specifies the max feature version it supports and the
 431          *    device responds with the currently supported feature version. The
 432          *    field is zero based
 433          */
 434         uint8_t feature_version;
 435
 436         uint8_t reserved8;
 437 };
 438
 439 struct ena_admin_device_attr_feature_desc {
 440         uint32_t impl_id;
 441
 442         uint32_t device_version;
 443
 444         /* bitmap of ena_admin_aq_feature_id */
 445         uint32_t supported_features;
 446
 447         uint32_t reserved3;
 448
 449         /* Indicates how many bits are used physical address access. */
 450         uint32_t phys_addr_width;
 451
 452         /* Indicates how many bits are used virtual address access. */
 453         uint32_t virt_addr_width;
 454
 455         /* unicast MAC address (in Network byte order) */
 456         uint8_t mac_addr[6];
 457
 458         uint8_t reserved7[2];
 459
 460         uint32_t max_mtu;
 461 };
 462
 463 enum ena_admin_llq_header_location {
 464         /* header is in descriptor list */
 465         ENA_ADMIN_INLINE_HEADER                     = 1,
 466         /* header in a separate ring, implies 16B descriptor list entry */
 467         ENA_ADMIN_HEADER_RING                       = 2,
 468 };
 469
 470 enum ena_admin_llq_ring_entry_size {
 471         ENA_ADMIN_LIST_ENTRY_SIZE_128B              = 1,
 472         ENA_ADMIN_LIST_ENTRY_SIZE_192B              = 2,
 473         ENA_ADMIN_LIST_ENTRY_SIZE_256B              = 4,
 474 };
 475
 476 enum ena_admin_llq_num_descs_before_header {
 477         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0     = 0,
 478         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1     = 1,
 479         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2     = 2,
 480         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4     = 4,
 481         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8     = 8,
 482 };
 483
 484 /* packet descriptor list entry always starts with one or more descriptors,
 485  * followed by a header. The rest of the descriptors are located in the
 486  * beginning of the subsequent entry. Stride refers to how the rest of the
 487  * descriptors are placed. This field is relevant only for inline header
 488  * mode
 489  */
 490 enum ena_admin_llq_stride_ctrl {
 491         ENA_ADMIN_SINGLE_DESC_PER_ENTRY             = 1,
 492         ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY          = 2,
 493 };
 494
 495 struct ena_admin_feature_llq_desc {
 496         uint32_t max_llq_num;
 497
 498         uint32_t max_llq_depth;
 499
 500         /*  specify the header locations the device supports. bitfield of
 501          *    enum ena_admin_llq_header_location.
 502          */
 503         uint16_t header_location_ctrl_supported;
 504
 505         /* the header location the driver selected to use. */
 506         uint16_t header_location_ctrl_enabled;
 507
 508         /* if inline header is specified - this is the size of descriptor
 509          *    list entry. If header in a separate ring is specified - this is
 510          *    the size of header ring entry. bitfield of enum
 511          *    ena_admin_llq_ring_entry_size. specify the entry sizes the device
 512          *    supports
 513          */
 514         uint16_t entry_size_ctrl_supported;
 515
 516         /* the entry size the driver selected to use. */
 517         uint16_t entry_size_ctrl_enabled;
 518
 519         /* valid only if inline header is specified. First entry associated
 520          *    with the packet includes descriptors and header. Rest of the
 521          *    entries occupied by descriptors. This parameter defines the max
 522          *    number of descriptors precedding the header in the first entry.
 523          *    The field is bitfield of enum
 524          *    ena_admin_llq_num_descs_before_header and specify the values the
 525          *    device supports
 526          */
 527         uint16_t desc_num_before_header_supported;
 528
 529         /* the desire field the driver selected to use */
 530         uint16_t desc_num_before_header_enabled;
 531
 532         /* valid only if inline was chosen. bitfield of enum
 533          *    ena_admin_llq_stride_ctrl
 534          */
 535         uint16_t descriptors_stride_ctrl_supported;
 536
 537         /* the stride control the driver selected to use */
 538         uint16_t descriptors_stride_ctrl_enabled;
 539
 540         /* Maximum size in bytes taken by llq entries in a single tx burst.
 541          * Set to 0 when there is no such limit.
 542          */
 543         uint32_t max_tx_burst_size;
 544 };
 545
 546 struct ena_admin_queue_ext_feature_fields {
 547         uint32_t max_tx_sq_num;
 548
 549         uint32_t max_tx_cq_num;
 550
 551         uint32_t max_rx_sq_num;
 552
 553         uint32_t max_rx_cq_num;
 554
 555         uint32_t max_tx_sq_depth;
 556
 557         uint32_t max_tx_cq_depth;
 558
 559         uint32_t max_rx_sq_depth;
 560
 561         uint32_t max_rx_cq_depth;
 562
 563         uint32_t max_tx_header_size;
 564
 565         /* Maximum Descriptors number, including meta descriptor, allowed for
 566          *    a single Tx packet
 567          */
 568         uint16_t max_per_packet_tx_descs;
 569
 570         /* Maximum Descriptors number allowed for a single Rx packet */
 571         uint16_t max_per_packet_rx_descs;
 572 };
 573
 574 struct ena_admin_queue_feature_desc {
 575         uint32_t max_sq_num;
 576
 577         uint32_t max_sq_depth;
 578
 579         uint32_t max_cq_num;
 580
 581         uint32_t max_cq_depth;
 582
 583         uint32_t max_legacy_llq_num;
 584
 585         uint32_t max_legacy_llq_depth;
 586
 587         uint32_t max_header_size;
 588
 589         /* Maximum Descriptors number, including meta descriptor, allowed for
 590          *    a single Tx packet
 591          */
 592         uint16_t max_packet_tx_descs;
 593
 594         /* Maximum Descriptors number allowed for a single Rx packet */
 595         uint16_t max_packet_rx_descs;
 596 };
 597
 598 struct ena_admin_set_feature_mtu_desc {
 599         /* exclude L2 */
 600         uint32_t mtu;
 601 };
 602
 603 struct ena_admin_get_extra_properties_strings_desc {
 604         uint32_t count;
 605 };
 606
 607 struct ena_admin_get_extra_properties_flags_desc {
 608         uint32_t flags;
 609 };
 610
 611 struct ena_admin_set_feature_host_attr_desc {
 612         /* host OS info base address in OS memory. host info is 4KB of
 613          * physically contiguous
 614          */
 615         struct ena_common_mem_addr os_info_ba;
 616
 617         /* host debug area base address in OS memory. debug area must be
 618          * physically contiguous
 619          */
 620         struct ena_common_mem_addr debug_ba;
 621
 622         /* debug area size */
 623         uint32_t debug_area_size;
 624 };
 625
 626 struct ena_admin_feature_intr_moder_desc {
 627         /* interrupt delay granularity in usec */
 628         uint16_t intr_delay_resolution;
 629
 630         uint16_t reserved;
 631 };
 632
 633 struct ena_admin_get_feature_link_desc {
 634         /* Link speed in Mb */
 635         uint32_t speed;
 636
 637         /* bit field of enum ena_admin_link types */
 638         uint32_t supported;
 639
 640         /* 0 : autoneg
 641          * 1 : duplex - Full Duplex
 642          * 31:2 : reserved2
 643          */
 644         uint32_t flags;
 645 };
 646
 647 struct ena_admin_feature_aenq_desc {
 648         /* bitmask for AENQ groups the device can report */
 649         uint32_t supported_groups;
 650
 651         /* bitmask for AENQ groups to report */
 652         uint32_t enabled_groups;
 653 };
 654
 655 struct ena_admin_feature_offload_desc {
 656         /* 0 : TX_L3_csum_ipv4
 657          * 1 : TX_L4_ipv4_csum_part - The checksum field
 658          *    should be initialized with pseudo header checksum
 659          * 2 : TX_L4_ipv4_csum_full
 660          * 3 : TX_L4_ipv6_csum_part - The checksum field
 661          *    should be initialized with pseudo header checksum
 662          * 4 : TX_L4_ipv6_csum_full
 663          * 5 : tso_ipv4
 664          * 6 : tso_ipv6
 665          * 7 : tso_ecn
 666          */
 667         uint32_t tx;
 668
 669         /* Receive side supported stateless offload
 670          * 0 : RX_L3_csum_ipv4 - IPv4 checksum
 671          * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
 672          * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
 673          * 3 : RX_hash - Hash calculation
 674          */
 675         uint32_t rx_supported;
 676
 677         uint32_t rx_enabled;
 678 };
 679
 680 enum ena_admin_hash_functions {
 681         ENA_ADMIN_TOEPLITZ                          = 1,
 682         ENA_ADMIN_CRC32                             = 2,
 683 };
 684
 685 struct ena_admin_feature_rss_flow_hash_control {
 686         uint32_t keys_num;
 687
 688         uint32_t reserved;
 689
 690         uint32_t key[10];
 691 };
 692
 693 struct ena_admin_feature_rss_flow_hash_function {
 694         /* 7:0 : funcs - bitmask of ena_admin_hash_functions */
 695         uint32_t supported_func;
 696
 697         /* 7:0 : selected_func - bitmask of
 698          *    ena_admin_hash_functions
 699          */
 700         uint32_t selected_func;
 701
 702         /* initial value */
 703         uint32_t init_val;
 704 };
 705
 706 /* RSS flow hash protocols */
 707 enum ena_admin_flow_hash_proto {
 708         ENA_ADMIN_RSS_TCP4                          = 0,
 709         ENA_ADMIN_RSS_UDP4                          = 1,
 710         ENA_ADMIN_RSS_TCP6                          = 2,
 711         ENA_ADMIN_RSS_UDP6                          = 3,
 712         ENA_ADMIN_RSS_IP4                           = 4,
 713         ENA_ADMIN_RSS_IP6                           = 5,
 714         ENA_ADMIN_RSS_IP4_FRAG                      = 6,
 715         ENA_ADMIN_RSS_NOT_IP                        = 7,
 716         /* TCPv6 with extension header */
 717         ENA_ADMIN_RSS_TCP6_EX                       = 8,
 718         /* IPv6 with extension header */
 719         ENA_ADMIN_RSS_IP6_EX                        = 9,
 720         ENA_ADMIN_RSS_PROTO_NUM                     = 16,
 721 };
 722
 723 /* RSS flow hash fields */
 724 enum ena_admin_flow_hash_fields {
 725         /* Ethernet Dest Addr */
 726         ENA_ADMIN_RSS_L2_DA                         = BIT(0),
 727         /* Ethernet Src Addr */
 728         ENA_ADMIN_RSS_L2_SA                         = BIT(1),
 729         /* ipv4/6 Dest Addr */
 730         ENA_ADMIN_RSS_L3_DA                         = BIT(2),
 731         /* ipv4/6 Src Addr */
 732         ENA_ADMIN_RSS_L3_SA                         = BIT(3),
 733         /* tcp/udp Dest Port */
 734         ENA_ADMIN_RSS_L4_DP                         = BIT(4),
 735         /* tcp/udp Src Port */
 736         ENA_ADMIN_RSS_L4_SP                         = BIT(5),
 737 };
 738
 739 struct ena_admin_proto_input {
 740         /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
 741         uint16_t fields;
 742
 743         uint16_t reserved2;
 744 };
 745
 746 struct ena_admin_feature_rss_hash_control {
 747         struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
 748
 749         struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
 750
 751         struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
 752
 753         struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
 754 };
 755
 756 struct ena_admin_feature_rss_flow_hash_input {
 757         /* supported hash input sorting
 758          * 1 : L3_sort - support swap L3 addresses if DA is
 759          *    smaller than SA
 760          * 2 : L4_sort - support swap L4 ports if DP smaller
 761          *    SP
 762          */
 763         uint16_t supported_input_sort;
 764
 765         /* enabled hash input sorting
 766          * 1 : enable_L3_sort - enable swap L3 addresses if
 767          *    DA smaller than SA
 768          * 2 : enable_L4_sort - enable swap L4 ports if DP
 769          *    smaller than SP
 770          */
 771         uint16_t enabled_input_sort;
 772 };
 773
 774 enum ena_admin_os_type {
 775         ENA_ADMIN_OS_LINUX                          = 1,
 776         ENA_ADMIN_OS_WIN                            = 2,
 777         ENA_ADMIN_OS_DPDK                           = 3,
 778         ENA_ADMIN_OS_FREEBSD                        = 4,
 779         ENA_ADMIN_OS_IPXE                           = 5,
 780         ENA_ADMIN_OS_ESXI                           = 6,
 781         ENA_ADMIN_OS_GROUPS_NUM                     = 6,
 782 };
 783
 784 struct ena_admin_host_info {
 785         /* defined in enum ena_admin_os_type */
 786         uint32_t os_type;
 787
 788         /* os distribution string format */
 789         uint8_t os_dist_str[128];
 790
 791         /* OS distribution numeric format */
 792         uint32_t os_dist;
 793
 794         /* kernel version string format */
 795         uint8_t kernel_ver_str[32];
 796
 797         /* Kernel version numeric format */
 798         uint32_t kernel_ver;
 799
 800         /* 7:0 : major
 801          * 15:8 : minor
 802          * 23:16 : sub_minor
 803          * 31:24 : module_type
 804          */
 805         uint32_t driver_version;
 806
 807         /* features bitmap */
 808         uint32_t supported_network_features[2];
 809
 810         /* ENA spec version of driver */
 811         uint16_t ena_spec_version;
 812
 813         /* ENA device's Bus, Device and Function
 814          * 2:0 : function
 815          * 7:3 : device
 816          * 15:8 : bus
 817          */
 818         uint16_t bdf;
 819
 820         /* Number of CPUs */
 821         uint16_t num_cpus;
 822
 823         uint16_t reserved;
 824 };
 825
 826 struct ena_admin_rss_ind_table_entry {
 827         uint16_t cq_idx;
 828
 829         uint16_t reserved;
 830 };
 831
 832 struct ena_admin_feature_rss_ind_table {
 833         /* min supported table size (2^min_size) */
 834         uint16_t min_size;
 835
 836         /* max supported table size (2^max_size) */
 837         uint16_t max_size;
 838
 839         /* table size (2^size) */
 840         uint16_t size;
 841
 842         /* 0 : one_entry_update - The FW supports setting a
 843          *    single RSS table entry
 844          */
 845         uint8_t flags;
 846
 847         uint8_t reserved;
 848
 849         /* index of the inline entry. 0xFFFFFFFF means invalid */
 850         uint32_t inline_index;
 851
 852         /* used for updating single entry, ignored when setting the entire
 853          * table through the control buffer.
 854          */
 855         struct ena_admin_rss_ind_table_entry inline_entry;
 856 };
 857
 858 /* When hint value is 0, driver should use it's own predefined value */
 859 struct ena_admin_ena_hw_hints {
 860         /* value in ms */
 861         uint16_t mmio_read_timeout;
 862
 863         /* value in ms */
 864         uint16_t driver_watchdog_timeout;
 865
 866         /* Per packet tx completion timeout. value in ms */
 867         uint16_t missing_tx_completion_timeout;
 868
 869         uint16_t missed_tx_completion_count_threshold_to_reset;
 870
 871         /* value in ms */
 872         uint16_t admin_completion_tx_timeout;
 873
 874         uint16_t netdev_wd_timeout;
 875
 876         uint16_t max_tx_sgl_size;
 877
 878         uint16_t max_rx_sgl_size;
 879
 880         uint16_t reserved[8];
 881 };
 882
 883 struct ena_admin_get_feat_cmd {
 884         struct ena_admin_aq_common_desc aq_common_descriptor;
 885
 886         struct ena_admin_ctrl_buff_info control_buffer;
 887
 888         struct ena_admin_get_set_feature_common_desc feat_common;
 889
 890         uint32_t raw[11];
 891 };
 892
 893 struct ena_admin_queue_ext_feature_desc {
 894         /* version */
 895         uint8_t version;
 896
 897         uint8_t reserved1[3];
 898
 899         union {
 900                 struct ena_admin_queue_ext_feature_fields max_queue_ext;
 901
 902                 uint32_t raw[10];
 903         } ;
 904 };
 905
 906 struct ena_admin_get_feat_resp {
 907         struct ena_admin_acq_common_desc acq_common_desc;
 908
 909         union {
 910                 uint32_t raw[14];
 911
 912                 struct ena_admin_device_attr_feature_desc dev_attr;
 913
 914                 struct ena_admin_feature_llq_desc llq;
 915
 916                 struct ena_admin_queue_feature_desc max_queue;
 917
 918                 struct ena_admin_queue_ext_feature_desc max_queue_ext;
 919
 920                 struct ena_admin_feature_aenq_desc aenq;
 921
 922                 struct ena_admin_get_feature_link_desc link;
 923
 924                 struct ena_admin_feature_offload_desc offload;
 925
 926                 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
 927
 928                 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
 929
 930                 struct ena_admin_feature_rss_ind_table ind_table;
 931
 932                 struct ena_admin_feature_intr_moder_desc intr_moderation;
 933
 934                 struct ena_admin_ena_hw_hints hw_hints;
 935
 936                 struct ena_admin_get_extra_properties_strings_desc extra_properties_strings;
 937
 938                 struct ena_admin_get_extra_properties_flags_desc extra_properties_flags;
 939         } u;
 940 };
 941
 942 struct ena_admin_set_feat_cmd {
 943         struct ena_admin_aq_common_desc aq_common_descriptor;
 944
 945         struct ena_admin_ctrl_buff_info control_buffer;
 946
 947         struct ena_admin_get_set_feature_common_desc feat_common;
 948
 949         union {
 950                 uint32_t raw[11];
 951
 952                 /* mtu size */
 953                 struct ena_admin_set_feature_mtu_desc mtu;
 954
 955                 /* host attributes */
 956                 struct ena_admin_set_feature_host_attr_desc host_attr;
 957
 958                 /* AENQ configuration */
 959                 struct ena_admin_feature_aenq_desc aenq;
 960
 961                 /* rss flow hash function */
 962                 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
 963
 964                 /* rss flow hash input */
 965                 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
 966
 967                 /* rss indirection table */
 968                 struct ena_admin_feature_rss_ind_table ind_table;
 969
 970                 /* LLQ configuration */
 971                 struct ena_admin_feature_llq_desc llq;
 972         } u;
 973 };
 974
 975 struct ena_admin_set_feat_resp {
 976         struct ena_admin_acq_common_desc acq_common_desc;
 977
 978         union {
 979                 uint32_t raw[14];
 980         } u;
 981 };
 982
 983 struct ena_admin_aenq_common_desc {
 984         uint16_t group;
 985
 986         uint16_t syndrom;
 987
 988         /* 0 : phase
 989          * 7:1 : reserved - MBZ
 990          */
 991         uint8_t flags;
 992
 993         uint8_t reserved1[3];
 994
 995         uint32_t timestamp_low;
 996
 997         uint32_t timestamp_high;
 998 };
 999
1000 /* asynchronous event notification groups */
1001 enum ena_admin_aenq_group {
1002         ENA_ADMIN_LINK_CHANGE                       = 0,
1003         ENA_ADMIN_FATAL_ERROR                       = 1,
1004         ENA_ADMIN_WARNING                           = 2,
1005         ENA_ADMIN_NOTIFICATION                      = 3,
1006         ENA_ADMIN_KEEP_ALIVE                        = 4,
1007         ENA_ADMIN_AENQ_GROUPS_NUM                   = 5,
1008 };
1009
1010 enum ena_admin_aenq_notification_syndrom {
1011         ENA_ADMIN_SUSPEND                           = 0,
1012         ENA_ADMIN_RESUME                            = 1,
1013         ENA_ADMIN_UPDATE_HINTS                      = 2,
1014 };
1015
1016 struct ena_admin_aenq_entry {
1017         struct ena_admin_aenq_common_desc aenq_common_desc;
1018
1019         /* command specific inline data */
1020         uint32_t inline_data_w4[12];
1021 };
1022
1023 struct ena_admin_aenq_link_change_desc {
1024         struct ena_admin_aenq_common_desc aenq_common_desc;
1025
1026         /* 0 : link_status */
1027         uint32_t flags;
1028 };
1029
1030 struct ena_admin_aenq_keep_alive_desc {
1031         struct ena_admin_aenq_common_desc aenq_common_desc;
1032
1033         uint32_t rx_drops_low;
1034
1035         uint32_t rx_drops_high;
1036 };
1037
1038 struct ena_admin_ena_mmio_req_read_less_resp {
1039         uint16_t req_id;
1040
1041         uint16_t reg_off;
1042
1043         /* value is valid when poll is cleared */
1044         uint32_t reg_val;
1045 };
1046
1047 /* aq_common_desc */
1048 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK            GENMASK(11, 0)
1049 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK                 BIT(0)
1050 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT            1
1051 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK             BIT(1)
1052 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT   2
1053 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK    BIT(2)
1054
1055 /* sq */
1056 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT                     5
1057 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK                      GENMASK(7, 5)
1058
1059 /* acq_common_desc */
1060 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK           GENMASK(11, 0)
1061 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK                BIT(0)
1062
1063 /* aq_create_sq_cmd */
1064 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT       5
1065 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK        GENMASK(7, 5)
1066 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK    GENMASK(3, 0)
1067 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT  4
1068 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK   GENMASK(6, 4)
1069 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1070
1071 /* aq_create_cq_cmd */
1072 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
1073 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
1074 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1075
1076 /* get_set_feature_common_desc */
1077 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK   GENMASK(1, 0)
1078
1079 /* get_feature_link_desc */
1080 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK        BIT(0)
1081 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT        1
1082 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK         BIT(1)
1083
1084 /* feature_offload_desc */
1085 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
1086 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
1087 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1088 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
1089 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1090 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
1091 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1092 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1093 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1094 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT       5
1095 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK        BIT(5)
1096 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT       6
1097 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK        BIT(6)
1098 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT        7
1099 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK         BIT(7)
1100 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1101 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1102 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1103 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1104 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1105 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT        3
1106 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK         BIT(3)
1107
1108 /* feature_rss_flow_hash_function */
1109 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1110 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
1111
1112 /* feature_rss_flow_hash_input */
1113 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1114 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK  BIT(1)
1115 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1116 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK  BIT(2)
1117 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1118 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1119 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1120 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1121
1122 /* host_info */
1123 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK                      GENMASK(7, 0)
1124 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT                     8
1125 #define ENA_ADMIN_HOST_INFO_MINOR_MASK                      GENMASK(15, 8)
1126 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT                 16
1127 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK                  GENMASK(23, 16)
1128 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT               24
1129 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK                GENMASK(31, 24)
1130 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK                   GENMASK(2, 0)
1131 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT                    3
1132 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK                     GENMASK(7, 3)
1133 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT                       8
1134 #define ENA_ADMIN_HOST_INFO_BUS_MASK                        GENMASK(15, 8)
1135
1136 /* feature_rss_ind_table */
1137 #define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0)
1138
1139 /* aenq_common_desc */
1140 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK               BIT(0)
1141
1142 /* aenq_link_change_desc */
1143 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK    BIT(0)
1144
1145 #if !defined(DEFS_LINUX_MAINLINE)
1146 static inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p)
1147 {
1148         return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1149 }
1150
1151 static inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val)
1152 {
1153         p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1154 }
1155
1156 static inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p)
1157 {
1158         return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1159 }
1160
1161 static inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val)
1162 {
1163         p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1164 }
1165
1166 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p)
1167 {
1168         return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT;
1169 }
1170
1171 static inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val)
1172 {
1173         p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK;
1174 }
1175
1176 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p)
1177 {
1178         return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT;
1179 }
1180
1181 static inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val)
1182 {
1183         p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1184 }
1185
1186 static inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p)
1187 {
1188         return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT;
1189 }
1190
1191 static inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val)
1192 {
1193         p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
1194 }
1195
1196 static inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p)
1197 {
1198         return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1199 }
1200
1201 static inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val)
1202 {
1203         p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1204 }
1205
1206 static inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p)
1207 {
1208         return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1209 }
1210
1211 static inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val)
1212 {
1213         p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1214 }
1215
1216 static inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p)
1217 {
1218         return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT;
1219 }
1220
1221 static inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1222 {
1223         p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1224 }
1225
1226 static inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p)
1227 {
1228         return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1229 }
1230
1231 static inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1232 {
1233         p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1234 }
1235
1236 static inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p)
1237 {
1238         return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT;
1239 }
1240
1241 static inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1242 {
1243         p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1244 }
1245
1246 static inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p)
1247 {
1248         return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1249 }
1250
1251 static inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1252 {
1253         p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1254 }
1255
1256 static inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p)
1257 {
1258         return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT;
1259 }
1260
1261 static inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1262 {
1263         p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1264 }
1265
1266 static inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p)
1267 {
1268         return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1269 }
1270
1271 static inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1272 {
1273         p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1274 }
1275
1276 static inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p)
1277 {
1278         return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1279 }
1280
1281 static inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val)
1282 {
1283         p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1284 }
1285
1286 static inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p)
1287 {
1288         return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1289 }
1290
1291 static inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1292 {
1293         p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1294 }
1295
1296 static inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p)
1297 {
1298         return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT;
1299 }
1300
1301 static inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1302 {
1303         p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK;
1304 }
1305
1306 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1307 {
1308         return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1309 }
1310
1311 static inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1312 {
1313         p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1314 }
1315
1316 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p)
1317 {
1318         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT;
1319 }
1320
1321 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1322 {
1323         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK;
1324 }
1325
1326 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p)
1327 {
1328         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT;
1329 }
1330
1331 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1332 {
1333         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK;
1334 }
1335
1336 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p)
1337 {
1338         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT;
1339 }
1340
1341 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1342 {
1343         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK;
1344 }
1345
1346 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p)
1347 {
1348         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT;
1349 }
1350
1351 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1352 {
1353         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK;
1354 }
1355
1356 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p)
1357 {
1358         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT;
1359 }
1360
1361 static inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1362 {
1363         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1364 }
1365
1366 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p)
1367 {
1368         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT;
1369 }
1370
1371 static inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val)
1372 {
1373         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK;
1374 }
1375
1376 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p)
1377 {
1378         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT;
1379 }
1380
1381 static inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val)
1382 {
1383         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK;
1384 }
1385
1386 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1387 {
1388         return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1389 }
1390
1391 static inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1392 {
1393         p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1394 }
1395
1396 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p)
1397 {
1398         return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT;
1399 }
1400
1401 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1402 {
1403         p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK;
1404 }
1405
1406 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p)
1407 {
1408         return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT;
1409 }
1410
1411 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1412 {
1413         p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK;
1414 }
1415
1416 static inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p)
1417 {
1418         return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT;
1419 }
1420
1421 static inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val)
1422 {
1423         p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK;
1424 }
1425
1426 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p)
1427 {
1428         return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1429 }
1430
1431 static inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1432 {
1433         p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1434 }
1435
1436 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p)
1437 {
1438         return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1439 }
1440
1441 static inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1442 {
1443         p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1444 }
1445
1446 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1447 {
1448         return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT;
1449 }
1450
1451 static inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1452 {
1453         p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;
1454 }
1455
1456 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1457 {
1458         return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT;
1459 }
1460
1461 static inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1462 {
1463         p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
1464 }
1465
1466 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1467 {
1468         return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT;
1469 }
1470
1471 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1472 {
1473         p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK;
1474 }
1475
1476 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1477 {
1478         return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT;
1479 }
1480
1481 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1482 {
1483         p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK;
1484 }
1485
1486 static inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p)
1487 {
1488         return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1489 }
1490
1491 static inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val)
1492 {
1493         p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1494 }
1495
1496 static inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p)
1497 {
1498         return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT;
1499 }
1500
1501 static inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val)
1502 {
1503         p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK;
1504 }
1505
1506 static inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p)
1507 {
1508         return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT;
1509 }
1510
1511 static inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val)
1512 {
1513         p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK;
1514 }
1515
1516 static inline uint32_t get_ena_admin_host_info_module_type(const struct ena_admin_host_info *p)
1517 {
1518         return (p->driver_version & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK) >> ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT;
1519 }
1520
1521 static inline void set_ena_admin_host_info_module_type(struct ena_admin_host_info *p, uint32_t val)
1522 {
1523         p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT) & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK;
1524 }
1525
1526 static inline uint16_t get_ena_admin_host_info_function(const struct ena_admin_host_info *p)
1527 {
1528         return p->bdf & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1529 }
1530
1531 static inline void set_ena_admin_host_info_function(struct ena_admin_host_info *p, uint16_t val)
1532 {
1533         p->bdf |= val & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1534 }
1535
1536 static inline uint16_t get_ena_admin_host_info_device(const struct ena_admin_host_info *p)
1537 {
1538         return (p->bdf & ENA_ADMIN_HOST_INFO_DEVICE_MASK) >> ENA_ADMIN_HOST_INFO_DEVICE_SHIFT;
1539 }
1540
1541 static inline void set_ena_admin_host_info_device(struct ena_admin_host_info *p, uint16_t val)
1542 {
1543         p->bdf |= (val << ENA_ADMIN_HOST_INFO_DEVICE_SHIFT) & ENA_ADMIN_HOST_INFO_DEVICE_MASK;
1544 }
1545
1546 static inline uint16_t get_ena_admin_host_info_bus(const struct ena_admin_host_info *p)
1547 {
1548         return (p->bdf & ENA_ADMIN_HOST_INFO_BUS_MASK) >> ENA_ADMIN_HOST_INFO_BUS_SHIFT;
1549 }
1550
1551 static inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, uint16_t val)
1552 {
1553         p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK;
1554 }
1555
1556 static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p)
1557 {
1558         return p->flags & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1559 }
1560
1561 static inline void set_ena_admin_feature_rss_ind_table_one_entry_update(struct ena_admin_feature_rss_ind_table *p, uint8_t val)
1562 {
1563         p->flags |= val & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1564 }
1565
1566 static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p)
1567 {
1568         return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1569 }
1570
1571 static inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val)
1572 {
1573         p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1574 }
1575
1576 static inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p)
1577 {
1578         return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1579 }
1580
1581 static inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val)
1582 {
1583         p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1584 }
1585
1586 #endif /* !defined(DEFS_LINUX_MAINLINE) */
1587 #endif /*_ENA_ADMIN_H_ */