drivers/net/ena/base/ena_plat_dpdk.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #ifndef DPDK_ENA_COM_ENA_PLAT_DPDK_H_
   7 #define DPDK_ENA_COM_ENA_PLAT_DPDK_H_
   8
   9 #include <stdbool.h>
  10 #include <stdlib.h>
  11 #include <pthread.h>
  12 #include <stdint.h>
  13 #include <inttypes.h>
  14 #include <string.h>
  15 #include <errno.h>
  16
  17 #include <rte_atomic.h>
  18 #include <rte_branch_prediction.h>
  19 #include <rte_cycles.h>
  20 #include <rte_io.h>
  21 #include <rte_log.h>
  22 #include <rte_malloc.h>
  23 #include <rte_memzone.h>
  24 #include <rte_prefetch.h>
  25 #include <rte_spinlock.h>
  26
  27 #include <sys/time.h>
  28 #include <rte_memcpy.h>
  29
  30 typedef uint64_t u64;
  31 typedef uint32_t u32;
  32 typedef uint16_t u16;
  33 typedef uint8_t u8;
  34
  35 typedef struct rte_eth_dev ena_netdev;
  36 typedef uint64_t dma_addr_t;
  37 #ifndef ETIME
  38 #define ETIME ETIMEDOUT
  39 #endif
  40
  41 #define ena_atomic32_t rte_atomic32_t
  42 #define ena_mem_handle_t const struct rte_memzone *
  43
  44 #define SZ_256 (256U)
  45 #define SZ_4K (4096U)
  46
  47 #define ENA_COM_OK      0
  48 #define ENA_COM_NO_MEM  -ENOMEM
  49 #define ENA_COM_INVAL   -EINVAL
  50 #define ENA_COM_NO_SPACE        -ENOSPC
  51 #define ENA_COM_NO_DEVICE       -ENODEV
  52 #define ENA_COM_TIMER_EXPIRED   -ETIME
  53 #define ENA_COM_FAULT   -EFAULT
  54 #define ENA_COM_TRY_AGAIN       -EAGAIN
  55 #define ENA_COM_UNSUPPORTED    -EOPNOTSUPP
  56 #define ENA_COM_EIO    -EIO
  57
  58 #define ____cacheline_aligned __rte_cache_aligned
  59
  60 #define ENA_ABORT() abort()
  61
  62 #define ENA_MSLEEP(x) rte_delay_us_sleep(x * 1000)
  63 #define ENA_USLEEP(x) rte_delay_us_sleep(x)
  64 #define ENA_UDELAY(x) rte_delay_us_block(x)
  65
  66 #define ENA_TOUCH(x) ((void)(x))
  67 /* Avoid nested declaration on arm64, as it may define rte_memcpy as memcpy. */
  68 #if defined(RTE_ARCH_X86)
  69 #undef memcpy
  70 #define memcpy rte_memcpy
  71 #endif
  72 #define wmb rte_wmb
  73 #define rmb rte_rmb
  74 #define mb rte_mb
  75 #define mmiowb rte_io_wmb
  76 #define __iomem
  77
  78 #define US_PER_S 1000000
  79 #define ENA_GET_SYSTEM_USECS()                                          \
  80         (rte_get_timer_cycles() * US_PER_S / rte_get_timer_hz())
  81
  82 extern int ena_logtype_com;
  83
  84 #define ENA_MAX_T(type, x, y) RTE_MAX((type)(x), (type)(y))
  85 #define ENA_MAX32(x, y) ENA_MAX_T(uint32_t, (x), (y))
  86 #define ENA_MAX16(x, y) ENA_MAX_T(uint16_t, (x), (y))
  87 #define ENA_MAX8(x, y) ENA_MAX_T(uint8_t, (x), (y))
  88 #define ENA_MIN_T(type, x, y) RTE_MIN((type)(x), (type)(y))
  89 #define ENA_MIN32(x, y) ENA_MIN_T(uint32_t, (x), (y))
  90 #define ENA_MIN16(x, y) ENA_MIN_T(uint16_t, (x), (y))
  91 #define ENA_MIN8(x, y) ENA_MIN_T(uint8_t, (x), (y))
  92
  93 #define BITS_PER_LONG_LONG (__SIZEOF_LONG_LONG__ * 8)
  94 #define U64_C(x) x ## ULL
  95 #define BIT(nr)         (1UL << (nr))
  96 #define BITS_PER_LONG   (__SIZEOF_LONG__ * 8)
  97 #define GENMASK(h, l)   (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
  98 #define GENMASK_ULL(h, l) (((~0ULL) - (1ULL << (l)) + 1) & \
  99                           (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
 100
 101 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
 102 #define ena_trc_log(dev, level, fmt, arg...)                            \
 103         (                                                               \
 104                 ENA_TOUCH(dev),                                         \
 105                 rte_log(RTE_LOG_ ## level, ena_logtype_com,             \
 106                         "[ENA_COM: %s]" fmt, __func__, ##arg)           \
 107         )
 108
 109 #define ena_trc_dbg(dev, format, arg...) ena_trc_log(dev, DEBUG, format, ##arg)
 110 #define ena_trc_info(dev, format, arg...) ena_trc_log(dev, INFO, format, ##arg)
 111 #define ena_trc_warn(dev, format, arg...)                               \
 112         ena_trc_log(dev, WARNING, format, ##arg)
 113 #define ena_trc_err(dev, format, arg...) ena_trc_log(dev, ERR, format, ##arg)
 114 #else
 115 #define ena_trc_dbg(dev, format, arg...) ENA_TOUCH(dev)
 116 #define ena_trc_info(dev, format, arg...) ENA_TOUCH(dev)
 117 #define ena_trc_warn(dev, format, arg...) ENA_TOUCH(dev)
 118 #define ena_trc_err(dev, format, arg...) ENA_TOUCH(dev)
 119 #endif /* RTE_LIBRTE_ENA_COM_DEBUG */
 120
 121 #define ENA_WARN(cond, dev, format, arg...)                             \
 122         do {                                                            \
 123                 if (unlikely(cond)) {                                   \
 124                         ena_trc_err(dev,                                \
 125                                 "Warn failed on %s:%s:%d:" format,      \
 126                                 __FILE__, __func__, __LINE__, ##arg);   \
 127                 }                                                       \
 128         } while (0)
 129
 130 /* Spinlock related methods */
 131 #define ena_spinlock_t rte_spinlock_t
 132 #define ENA_SPINLOCK_INIT(spinlock) rte_spinlock_init(&spinlock)
 133 #define ENA_SPINLOCK_LOCK(spinlock, flags)                              \
 134         ({(void)flags; rte_spinlock_lock(&spinlock); })
 135 #define ENA_SPINLOCK_UNLOCK(spinlock, flags)                            \
 136         ({(void)flags; rte_spinlock_unlock(&(spinlock)); })
 137 #define ENA_SPINLOCK_DESTROY(spinlock) ((void)spinlock)
 138
 139 #define q_waitqueue_t                   \
 140         struct {                        \
 141                 pthread_cond_t cond;    \
 142                 pthread_mutex_t mutex;  \
 143         }
 144
 145 #define ena_wait_queue_t q_waitqueue_t
 146
 147 #define ENA_WAIT_EVENT_INIT(waitqueue)                                  \
 148         do {                                                            \
 149                 pthread_mutex_init(&(waitqueue).mutex, NULL);           \
 150                 pthread_cond_init(&(waitqueue).cond, NULL);             \
 151         } while (0)
 152
 153 #define ENA_WAIT_EVENT_WAIT(waitevent, timeout)                         \
 154         do {                                                            \
 155                 struct timespec wait;                                   \
 156                 struct timeval now;                                     \
 157                 unsigned long timeout_us;                               \
 158                 gettimeofday(&now, NULL);                               \
 159                 wait.tv_sec = now.tv_sec + timeout / 1000000UL;         \
 160                 timeout_us = timeout % 1000000UL;                       \
 161                 wait.tv_nsec = (now.tv_usec + timeout_us) * 1000UL;     \
 162                 pthread_mutex_lock(&waitevent.mutex);                   \
 163                 pthread_cond_timedwait(&waitevent.cond,                 \
 164                                 &waitevent.mutex, &wait);               \
 165                 pthread_mutex_unlock(&waitevent.mutex);                 \
 166         } while (0)
 167 #define ENA_WAIT_EVENT_SIGNAL(waitevent) pthread_cond_signal(&waitevent.cond)
 168 /* pthread condition doesn't need to be rearmed after usage */
 169 #define ENA_WAIT_EVENT_CLEAR(...)
 170 #define ENA_WAIT_EVENT_DESTROY(waitqueue) ((void)(waitqueue))
 171
 172 #define ena_wait_event_t ena_wait_queue_t
 173 #define ENA_MIGHT_SLEEP()
 174
 175 #define ena_time_t uint64_t
 176 #define ENA_TIME_EXPIRE(timeout)  (timeout < rte_get_timer_cycles())
 177 #define ENA_GET_SYSTEM_TIMEOUT(timeout_us)                             \
 178        (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles())
 179
 180 /*
 181  * Each rte_memzone should have unique name.
 182  * To satisfy it, count number of allocations and add it to name.
 183  */
 184 extern rte_atomic32_t ena_alloc_cnt;
 185
 186 #define ENA_MEM_ALLOC_COHERENT_ALIGNED(                                 \
 187         dmadev, size, virt, phys, handle, alignment)                    \
 188         do {                                                            \
 189                 const struct rte_memzone *mz = NULL;                    \
 190                 ENA_TOUCH(dmadev); ENA_TOUCH(handle);                   \
 191                 if (size > 0) {                                         \
 192                         char z_name[RTE_MEMZONE_NAMESIZE];              \
 193                         snprintf(z_name, sizeof(z_name),                \
 194                          "ena_alloc_%d",                                \
 195                          rte_atomic32_add_return(&ena_alloc_cnt, 1));   \
 196                         mz = rte_memzone_reserve_aligned(z_name, size,  \
 197                                         SOCKET_ID_ANY,                  \
 198                                         RTE_MEMZONE_IOVA_CONTIG,        \
 199                                         alignment);                     \
 200                         handle = mz;                                    \
 201                 }                                                       \
 202                 if (mz == NULL) {                                       \
 203                         virt = NULL;                                    \
 204                         phys = 0;                                       \
 205                 } else {                                                \
 206                         memset(mz->addr, 0, size);                      \
 207                         virt = mz->addr;                                \
 208                         phys = mz->iova;                                \
 209                 }                                                       \
 210         } while (0)
 211 #define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, handle)        \
 212                 ENA_MEM_ALLOC_COHERENT_ALIGNED(                         \
 213                         dmadev,                                         \
 214                         size,                                           \
 215                         virt,                                           \
 216                         phys,                                           \
 217                         handle,                                         \
 218                         RTE_CACHE_LINE_SIZE)
 219 #define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, handle)         \
 220                 ({ ENA_TOUCH(size); ENA_TOUCH(phys);                    \
 221                    ENA_TOUCH(dmadev);                                   \
 222                    rte_memzone_free(handle); })
 223
 224 #define ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(                            \
 225         dmadev, size, virt, phys, mem_handle, node, dev_node, alignment) \
 226         do {                                                            \
 227                 const struct rte_memzone *mz = NULL;                    \
 228                 ENA_TOUCH(dmadev); ENA_TOUCH(dev_node);                 \
 229                 if (size > 0) {                                         \
 230                         char z_name[RTE_MEMZONE_NAMESIZE];              \
 231                         snprintf(z_name, sizeof(z_name),                \
 232                          "ena_alloc_%d",                                \
 233                          rte_atomic32_add_return(&ena_alloc_cnt, 1));   \
 234                         mz = rte_memzone_reserve_aligned(z_name, size, node, \
 235                                 RTE_MEMZONE_IOVA_CONTIG, alignment);    \
 236                         mem_handle = mz;                                \
 237                 }                                                       \
 238                 if (mz == NULL) {                                       \
 239                         virt = NULL;                                    \
 240                         phys = 0;                                       \
 241                 } else {                                                \
 242                         memset(mz->addr, 0, size);                      \
 243                         virt = mz->addr;                                \
 244                         phys = mz->iova;                                \
 245                 }                                                       \
 246         } while (0)
 247 #define ENA_MEM_ALLOC_COHERENT_NODE(                                    \
 248         dmadev, size, virt, phys, mem_handle, node, dev_node)           \
 249                 ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(                    \
 250                         dmadev,                                         \
 251                         size,                                           \
 252                         virt,                                           \
 253                         phys,                                           \
 254                         mem_handle,                                     \
 255                         node,                                           \
 256                         dev_node,                                       \
 257                         RTE_CACHE_LINE_SIZE)
 258 #define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) \
 259         do {                                                            \
 260                 ENA_TOUCH(dmadev); ENA_TOUCH(dev_node);                 \
 261                 virt = rte_zmalloc_socket(NULL, size, 0, node);         \
 262         } while (0)
 263
 264 #define ENA_MEM_ALLOC(dmadev, size) rte_zmalloc(NULL, size, 1)
 265 #define ENA_MEM_FREE(dmadev, ptr, size)                                 \
 266         ({ ENA_TOUCH(dmadev); ENA_TOUCH(size); rte_free(ptr); })
 267
 268 #define ENA_DB_SYNC(mem_handle) ((void)mem_handle)
 269
 270 #define ENA_REG_WRITE32(bus, value, reg)                                \
 271         ({ (void)(bus); rte_write32((value), (reg)); })
 272 #define ENA_REG_WRITE32_RELAXED(bus, value, reg)                        \
 273         ({ (void)(bus); rte_write32_relaxed((value), (reg)); })
 274 #define ENA_REG_READ32(bus, reg)                                        \
 275         ({ (void)(bus); rte_read32_relaxed((reg)); })
 276
 277 #define ATOMIC32_INC(i32_ptr) rte_atomic32_inc(i32_ptr)
 278 #define ATOMIC32_DEC(i32_ptr) rte_atomic32_dec(i32_ptr)
 279 #define ATOMIC32_SET(i32_ptr, val) rte_atomic32_set(i32_ptr, val)
 280 #define ATOMIC32_READ(i32_ptr) rte_atomic32_read(i32_ptr)
 281
 282 #define msleep(x) rte_delay_us(x * 1000)
 283 #define udelay(x) rte_delay_us(x)
 284
 285 #define dma_rmb() rmb()
 286
 287 #define MAX_ERRNO       4095
 288 #define IS_ERR(x) (((unsigned long)x) >= (unsigned long)-MAX_ERRNO)
 289 #define ERR_PTR(error) ((void *)(long)error)
 290 #define PTR_ERR(error) ((long)(void *)error)
 291 #define might_sleep()
 292
 293 #define prefetch(x) rte_prefetch0(x)
 294 #define prefetchw(x) prefetch(x)
 295
 296 #define lower_32_bits(x) ((uint32_t)(x))
 297 #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
 298
 299 #define ENA_TIME_EXPIRE(timeout)  (timeout < rte_get_timer_cycles())
 300 #define ENA_GET_SYSTEM_TIMEOUT(timeout_us)                              \
 301     (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles())
 302 #define ENA_WAIT_EVENTS_DESTROY(admin_queue) ((void)(admin_queue))
 303
 304 #ifndef READ_ONCE
 305 #define READ_ONCE(var) (*((volatile typeof(var) *)(&(var))))
 306 #endif
 307
 308 #define READ_ONCE8(var) READ_ONCE(var)
 309 #define READ_ONCE16(var) READ_ONCE(var)
 310 #define READ_ONCE32(var) READ_ONCE(var)
 311
 312 /* The size must be 8 byte align */
 313 #define ENA_MEMCPY_TO_DEVICE_64(dst, src, size)                         \
 314         do {                                                            \
 315                 int count, i;                                           \
 316                 uint64_t *to = (uint64_t *)(dst);                       \
 317                 const uint64_t *from = (const uint64_t *)(src);         \
 318                 count = (size) / 8;                                     \
 319                 for (i = 0; i < count; i++, from++, to++)               \
 320                         rte_write64_relaxed(*from, to);                 \
 321         } while(0)
 322
 323 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
 324
 325 #define ENA_FFS(x) ffs(x)
 326
 327 void ena_rss_key_fill(void *key, size_t size);
 328
 329 #define ENA_RSS_FILL_KEY(key, size) ena_rss_key_fill(key, size)
 330
 331 #define ENA_INTR_INITIAL_TX_INTERVAL_USECS_PLAT 0
 332
 333 #define ENA_PRIu64 PRIu64
 334
 335 #include "ena_includes.h"
 336 #endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */