drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev.h>
  36 #include <rte_tcp.h>
  37 #include <rte_atomic.h>
  38 #include <rte_dev.h>
  39 #include <rte_errno.h>
  40 #include <rte_version.h>
  41
  42 #include "ena_ethdev.h"
  43 #include "ena_logs.h"
  44 #include "ena_platform.h"
  45 #include "ena_com.h"
  46 #include "ena_eth_com.h"
  47
  48 #include <ena_common_defs.h>
  49 #include <ena_regs_defs.h>
  50 #include <ena_admin_defs.h>
  51 #include <ena_eth_io_defs.h>
  52
  53 #define DRV_MODULE_VER_MAJOR    1
  54 #define DRV_MODULE_VER_MINOR    0
  55 #define DRV_MODULE_VER_SUBMINOR 0
  56
  57 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  58 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  59 /*reverse version of ENA_IO_RXQ_IDX*/
  60 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  61
  62 /* While processing submitted and completed descriptors (rx and tx path
  63  * respectively) in a loop it is desired to:
  64  *  - perform batch submissions while populating sumbissmion queue
  65  *  - avoid blocking transmission of other packets during cleanup phase
  66  * Hence the utilization ratio of 1/8 of a queue size.
  67  */
  68 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  69
  70 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  71 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  72
  73 #define GET_L4_HDR_LEN(mbuf)                                    \
  74         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  75                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  76
  77 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  78 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  79 #define ENA_HASH_KEY_SIZE       40
  80 #define ENA_ETH_SS_STATS        0xFF
  81 #define ETH_GSTRING_LEN 32
  82
  83 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  84
  85 enum ethtool_stringset {
  86         ETH_SS_TEST             = 0,
  87         ETH_SS_STATS,
  88 };
  89
  90 struct ena_stats {
  91         char name[ETH_GSTRING_LEN];
  92         int stat_offset;
  93 };
  94
  95 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
  96         .name = #stat, \
  97         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
  98 }
  99
 100 #define ENA_STAT_ENTRY(stat, stat_type) { \
 101         .name = #stat, \
 102         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 103 }
 104
 105 #define ENA_STAT_RX_ENTRY(stat) \
 106         ENA_STAT_ENTRY(stat, rx)
 107
 108 #define ENA_STAT_TX_ENTRY(stat) \
 109         ENA_STAT_ENTRY(stat, tx)
 110
 111 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, dev)
 113
 114 static const struct ena_stats ena_stats_global_strings[] = {
 115         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 116         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 117         ENA_STAT_GLOBAL_ENTRY(io_resume),
 118         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 119         ENA_STAT_GLOBAL_ENTRY(interface_up),
 120         ENA_STAT_GLOBAL_ENTRY(interface_down),
 121         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 122 };
 123
 124 static const struct ena_stats ena_stats_tx_strings[] = {
 125         ENA_STAT_TX_ENTRY(cnt),
 126         ENA_STAT_TX_ENTRY(bytes),
 127         ENA_STAT_TX_ENTRY(queue_stop),
 128         ENA_STAT_TX_ENTRY(queue_wakeup),
 129         ENA_STAT_TX_ENTRY(dma_mapping_err),
 130         ENA_STAT_TX_ENTRY(linearize),
 131         ENA_STAT_TX_ENTRY(linearize_failed),
 132         ENA_STAT_TX_ENTRY(tx_poll),
 133         ENA_STAT_TX_ENTRY(doorbells),
 134         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 135         ENA_STAT_TX_ENTRY(missing_tx_comp),
 136         ENA_STAT_TX_ENTRY(bad_req_id),
 137 };
 138
 139 static const struct ena_stats ena_stats_rx_strings[] = {
 140         ENA_STAT_RX_ENTRY(cnt),
 141         ENA_STAT_RX_ENTRY(bytes),
 142         ENA_STAT_RX_ENTRY(refil_partial),
 143         ENA_STAT_RX_ENTRY(bad_csum),
 144         ENA_STAT_RX_ENTRY(page_alloc_fail),
 145         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 146         ENA_STAT_RX_ENTRY(dma_mapping_err),
 147         ENA_STAT_RX_ENTRY(bad_desc_num),
 148         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 149 };
 150
 151 static const struct ena_stats ena_stats_ena_com_strings[] = {
 152         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 153         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 154         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 155         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 156         ENA_STAT_ENA_COM_ENTRY(no_completion),
 157 };
 158
 159 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 160 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 161 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 162 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 163
 164 /** Vendor ID used by Amazon devices */
 165 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 166 /** Amazon devices */
 167 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 168 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 169
 170 static struct rte_pci_id pci_id_ena_map[] = {
 171 #define RTE_PCI_DEV_ID_DECL_ENA(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 172         RTE_PCI_DEV_ID_DECL_ENA(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF)
 173         RTE_PCI_DEV_ID_DECL_ENA(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF)
 174         {.device_id = 0},
 175 };
 176
 177 static int ena_device_init(struct ena_com_dev *ena_dev,
 178                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 179 static int ena_dev_configure(struct rte_eth_dev *dev);
 180 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 181                                   uint16_t nb_pkts);
 182 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 183                               uint16_t nb_desc, unsigned int socket_id,
 184                               const struct rte_eth_txconf *tx_conf);
 185 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 186                               uint16_t nb_desc, unsigned int socket_id,
 187                               const struct rte_eth_rxconf *rx_conf,
 188                               struct rte_mempool *mp);
 189 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 190                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 191 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 192 static void ena_init_rings(struct ena_adapter *adapter);
 193 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 194 static int ena_start(struct rte_eth_dev *dev);
 195 static void ena_close(struct rte_eth_dev *dev);
 196 static void ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 197 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 198 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 199 static void ena_rx_queue_release(void *queue);
 200 static void ena_tx_queue_release(void *queue);
 201 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 202 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 203 static int ena_link_update(struct rte_eth_dev *dev,
 204                            __rte_unused int wait_to_complete);
 205 static int ena_queue_restart(struct ena_ring *ring);
 206 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 207                                  enum ena_ring_type ring_type);
 208 static void ena_stats_restart(struct rte_eth_dev *dev);
 209 static void ena_infos_get(__rte_unused struct rte_eth_dev *dev,
 210                           struct rte_eth_dev_info *dev_info);
 211 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 212                                struct rte_eth_rss_reta_entry64 *reta_conf,
 213                                uint16_t reta_size);
 214 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 215                               struct rte_eth_rss_reta_entry64 *reta_conf,
 216                               uint16_t reta_size);
 217 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 218
 219 static struct eth_dev_ops ena_dev_ops = {
 220         .dev_configure        = ena_dev_configure,
 221         .dev_infos_get        = ena_infos_get,
 222         .rx_queue_setup       = ena_rx_queue_setup,
 223         .tx_queue_setup       = ena_tx_queue_setup,
 224         .dev_start            = ena_start,
 225         .link_update          = ena_link_update,
 226         .stats_get            = ena_stats_get,
 227         .mtu_set              = ena_mtu_set,
 228         .rx_queue_release     = ena_rx_queue_release,
 229         .tx_queue_release     = ena_tx_queue_release,
 230         .dev_close            = ena_close,
 231         .reta_update          = ena_rss_reta_update,
 232         .reta_query           = ena_rss_reta_query,
 233 };
 234
 235 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 236                                        struct ena_com_rx_ctx *ena_rx_ctx)
 237 {
 238         uint64_t ol_flags = 0;
 239
 240         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 241                 ol_flags |= PKT_TX_TCP_CKSUM;
 242         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 243                 ol_flags |= PKT_TX_UDP_CKSUM;
 244
 245         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 246                 ol_flags |= PKT_TX_IPV4;
 247         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 248                 ol_flags |= PKT_TX_IPV6;
 249
 250         if (unlikely(ena_rx_ctx->l4_csum_err))
 251                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 252         if (unlikely(ena_rx_ctx->l3_csum_err))
 253                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 254
 255         mbuf->ol_flags = ol_flags;
 256 }
 257
 258 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 259                                        struct ena_com_tx_ctx *ena_tx_ctx)
 260 {
 261         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 262
 263         if (mbuf->ol_flags &
 264             (PKT_TX_L4_MASK | PKT_TX_IP_CKSUM | PKT_TX_TCP_SEG)) {
 265                 /* check if TSO is required */
 266                 if (mbuf->ol_flags & PKT_TX_TCP_SEG) {
 267                         ena_tx_ctx->tso_enable = true;
 268
 269                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 270                 }
 271
 272                 /* check if L3 checksum is needed */
 273                 if (mbuf->ol_flags & PKT_TX_IP_CKSUM)
 274                         ena_tx_ctx->l3_csum_enable = true;
 275
 276                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 277                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 278                 } else {
 279                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 280
 281                         /* set don't fragment (DF) flag */
 282                         if (mbuf->packet_type &
 283                                 (RTE_PTYPE_L4_NONFRAG
 284                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 285                                 ena_tx_ctx->df = true;
 286                 }
 287
 288                 /* check if L4 checksum is needed */
 289                 switch (mbuf->ol_flags & PKT_TX_L4_MASK) {
 290                 case PKT_TX_TCP_CKSUM:
 291                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 292                         ena_tx_ctx->l4_csum_enable = true;
 293                         break;
 294                 case PKT_TX_UDP_CKSUM:
 295                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 296                         ena_tx_ctx->l4_csum_enable = true;
 297                         break;
 298                 default:
 299                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 300                         ena_tx_ctx->l4_csum_enable = false;
 301                         break;
 302                 }
 303
 304                 ena_meta->mss = mbuf->tso_segsz;
 305                 ena_meta->l3_hdr_len = mbuf->l3_len;
 306                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 307                 /* this param needed only for TSO */
 308                 ena_meta->l3_outer_hdr_len = 0;
 309                 ena_meta->l3_outer_hdr_offset = 0;
 310
 311                 ena_tx_ctx->meta_valid = true;
 312         } else {
 313                 ena_tx_ctx->meta_valid = false;
 314         }
 315 }
 316
 317 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 318 {
 319         struct ena_admin_host_info *host_info;
 320         int rc;
 321
 322         /* Allocate only the host info */
 323         rc = ena_com_allocate_host_info(ena_dev);
 324         if (rc) {
 325                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 326                 return;
 327         }
 328
 329         host_info = ena_dev->host_attr.host_info;
 330
 331         host_info->os_type = ENA_ADMIN_OS_DPDK;
 332         host_info->kernel_ver = RTE_VERSION;
 333         strncpy((char *)host_info->kernel_ver_str, rte_version(),
 334                 strlen(rte_version()));
 335         host_info->os_dist = RTE_VERSION;
 336         strncpy((char *)host_info->os_dist_str, rte_version(),
 337                 strlen(rte_version()));
 338         host_info->driver_version =
 339                 (DRV_MODULE_VER_MAJOR) |
 340                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 341                 (DRV_MODULE_VER_SUBMINOR <<
 342                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 343
 344         rc = ena_com_set_host_attributes(ena_dev);
 345         if (rc) {
 346                 if (rc == -EPERM)
 347                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 348                 else
 349                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 350
 351                 goto err;
 352         }
 353
 354         return;
 355
 356 err:
 357         ena_com_delete_host_info(ena_dev);
 358 }
 359
 360 static int
 361 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 362 {
 363         if (sset != ETH_SS_STATS)
 364                 return -EOPNOTSUPP;
 365
 366          /* Workaround for clang:
 367          * touch internal structures to prevent
 368          * compiler error
 369          */
 370         ENA_TOUCH(ena_stats_global_strings);
 371         ENA_TOUCH(ena_stats_tx_strings);
 372         ENA_TOUCH(ena_stats_rx_strings);
 373         ENA_TOUCH(ena_stats_ena_com_strings);
 374
 375         return  dev->data->nb_tx_queues *
 376                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 377                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 378 }
 379
 380 static void ena_config_debug_area(struct ena_adapter *adapter)
 381 {
 382         u32 debug_area_size;
 383         int rc, ss_count;
 384
 385         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 386         if (ss_count <= 0) {
 387                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 388                 return;
 389         }
 390
 391         /* allocate 32 bytes for each string and 64bit for the value */
 392         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 393
 394         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 395         if (rc) {
 396                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 397                 return;
 398         }
 399
 400         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 401         if (rc) {
 402                 if (rc == -EPERM)
 403                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 404                 else
 405                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 406                 goto err;
 407         }
 408
 409         return;
 410 err:
 411         ena_com_delete_debug_area(&adapter->ena_dev);
 412 }
 413
 414 static void ena_close(struct rte_eth_dev *dev)
 415 {
 416         struct ena_adapter *adapter =
 417                 (struct ena_adapter *)(dev->data->dev_private);
 418
 419         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 420
 421         ena_rx_queue_release_all(dev);
 422         ena_tx_queue_release_all(dev);
 423 }
 424
 425 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 426                                struct rte_eth_rss_reta_entry64 *reta_conf,
 427                                uint16_t reta_size)
 428 {
 429         struct ena_adapter *adapter =
 430                 (struct ena_adapter *)(dev->data->dev_private);
 431         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 432         int ret, i;
 433         u16 entry_value;
 434         int conf_idx;
 435         int idx;
 436
 437         if ((reta_size == 0) || (reta_conf == NULL))
 438                 return -EINVAL;
 439
 440         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 441                 RTE_LOG(WARNING, PMD,
 442                         "indirection table %d is bigger than supported (%d)\n",
 443                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 444                 ret = -EINVAL;
 445                 goto err;
 446         }
 447
 448         for (i = 0 ; i < reta_size ; i++) {
 449                 /* each reta_conf is for 64 entries.
 450                  * to support 128 we use 2 conf of 64
 451                  */
 452                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 453                 idx = i % RTE_RETA_GROUP_SIZE;
 454                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 455                         entry_value =
 456                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 457                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 458                                                                 i,
 459                                                                 entry_value);
 460                         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 461                                 RTE_LOG(ERR, PMD,
 462                                         "Cannot fill indirect table\n");
 463                                 ret = -ENOTSUP;
 464                                 goto err;
 465                         }
 466                 }
 467         }
 468
 469         ret = ena_com_indirect_table_set(ena_dev);
 470         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 471                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 472                 ret = -ENOTSUP;
 473                 goto err;
 474         }
 475
 476         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 477                 __func__, reta_size, adapter->rte_dev->data->port_id);
 478 err:
 479         return ret;
 480 }
 481
 482 /* Query redirection table. */
 483 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 484                               struct rte_eth_rss_reta_entry64 *reta_conf,
 485                               uint16_t reta_size)
 486 {
 487         struct ena_adapter *adapter =
 488                 (struct ena_adapter *)(dev->data->dev_private);
 489         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 490         int ret;
 491         int i;
 492         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 493         int reta_conf_idx;
 494         int reta_idx;
 495
 496         if (reta_size == 0 || reta_conf == NULL ||
 497             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 498                 return -EINVAL;
 499
 500         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 501         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 502                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 503                 ret = -ENOTSUP;
 504                 goto err;
 505         }
 506
 507         for (i = 0 ; i < reta_size ; i++) {
 508                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 509                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 510                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 511                         reta_conf[reta_conf_idx].reta[reta_idx] =
 512                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 513         }
 514 err:
 515         return ret;
 516 }
 517
 518 static int ena_rss_init_default(struct ena_adapter *adapter)
 519 {
 520         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 521         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 522         int rc, i;
 523         u32 val;
 524
 525         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 526         if (unlikely(rc)) {
 527                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 528                 goto err_rss_init;
 529         }
 530
 531         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 532                 val = i % nb_rx_queues;
 533                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 534                                                        ENA_IO_RXQ_IDX(val));
 535                 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 536                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 537                         goto err_fill_indir;
 538                 }
 539         }
 540
 541         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 542                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 543         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 544                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 545                 goto err_fill_indir;
 546         }
 547
 548         rc = ena_com_set_default_hash_ctrl(ena_dev);
 549         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 550                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 551                 goto err_fill_indir;
 552         }
 553
 554         rc = ena_com_indirect_table_set(ena_dev);
 555         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 556                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 557                 goto err_fill_indir;
 558         }
 559         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 560                 adapter->rte_dev->data->port_id);
 561
 562         return 0;
 563
 564 err_fill_indir:
 565         ena_com_rss_destroy(ena_dev);
 566 err_rss_init:
 567
 568         return rc;
 569 }
 570
 571 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 572 {
 573         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 574         int nb_queues = dev->data->nb_rx_queues;
 575         int i;
 576
 577         for (i = 0; i < nb_queues; i++)
 578                 ena_rx_queue_release(queues[i]);
 579 }
 580
 581 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 582 {
 583         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 584         int nb_queues = dev->data->nb_tx_queues;
 585         int i;
 586
 587         for (i = 0; i < nb_queues; i++)
 588                 ena_tx_queue_release(queues[i]);
 589 }
 590
 591 static void ena_rx_queue_release(void *queue)
 592 {
 593         struct ena_ring *ring = (struct ena_ring *)queue;
 594         struct ena_adapter *adapter = ring->adapter;
 595         int ena_qid;
 596
 597         ena_assert_msg(ring->configured,
 598                        "API violation - releasing not configured queue");
 599         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 600                        "API violation");
 601
 602         /* Destroy HW queue */
 603         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 604         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 605
 606         /* Free all bufs */
 607         ena_rx_queue_release_bufs(ring);
 608
 609         /* Free ring resources */
 610         if (ring->rx_buffer_info)
 611                 rte_free(ring->rx_buffer_info);
 612         ring->rx_buffer_info = NULL;
 613
 614         ring->configured = 0;
 615
 616         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 617                 ring->port_id, ring->id);
 618 }
 619
 620 static void ena_tx_queue_release(void *queue)
 621 {
 622         struct ena_ring *ring = (struct ena_ring *)queue;
 623         struct ena_adapter *adapter = ring->adapter;
 624         int ena_qid;
 625
 626         ena_assert_msg(ring->configured,
 627                        "API violation. Releasing not configured queue");
 628         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 629                        "API violation");
 630
 631         /* Destroy HW queue */
 632         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 633         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 634
 635         /* Free all bufs */
 636         ena_tx_queue_release_bufs(ring);
 637
 638         /* Free ring resources */
 639         if (ring->tx_buffer_info)
 640                 rte_free(ring->tx_buffer_info);
 641
 642         if (ring->empty_tx_reqs)
 643                 rte_free(ring->empty_tx_reqs);
 644
 645         ring->empty_tx_reqs = NULL;
 646         ring->tx_buffer_info = NULL;
 647
 648         ring->configured = 0;
 649
 650         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 651                 ring->port_id, ring->id);
 652 }
 653
 654 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 655 {
 656         unsigned int ring_mask = ring->ring_size - 1;
 657
 658         while (ring->next_to_clean != ring->next_to_use) {
 659                 struct rte_mbuf *m =
 660                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 661
 662                 if (m)
 663                         __rte_mbuf_raw_free(m);
 664
 665                 ring->next_to_clean =
 666                         ENA_CIRC_INC(ring->next_to_clean, 1, ring->ring_size);
 667         }
 668 }
 669
 670 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 671 {
 672         unsigned int ring_mask = ring->ring_size - 1;
 673
 674         while (ring->next_to_clean != ring->next_to_use) {
 675                 struct ena_tx_buffer *tx_buf =
 676                         &ring->tx_buffer_info[ring->next_to_clean & ring_mask];
 677
 678                 if (tx_buf->mbuf)
 679                         rte_pktmbuf_free(tx_buf->mbuf);
 680
 681                 ring->next_to_clean =
 682                         ENA_CIRC_INC(ring->next_to_clean, 1, ring->ring_size);
 683         }
 684 }
 685
 686 static int ena_link_update(struct rte_eth_dev *dev,
 687                            __rte_unused int wait_to_complete)
 688 {
 689         struct rte_eth_link *link = &dev->data->dev_link;
 690
 691         link->link_status = 1;
 692         link->link_speed = ETH_SPEED_NUM_10G;
 693         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 694
 695         return 0;
 696 }
 697
 698 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 699                                  enum ena_ring_type ring_type)
 700 {
 701         struct ena_adapter *adapter =
 702                 (struct ena_adapter *)(dev->data->dev_private);
 703         struct ena_ring *queues = NULL;
 704         int i = 0;
 705         int rc = 0;
 706
 707         queues = (ring_type == ENA_RING_TYPE_RX) ?
 708                 adapter->rx_ring : adapter->tx_ring;
 709
 710         for (i = 0; i < adapter->num_queues; i++) {
 711                 if (queues[i].configured) {
 712                         if (ring_type == ENA_RING_TYPE_RX) {
 713                                 ena_assert_msg(
 714                                         dev->data->rx_queues[i] == &queues[i],
 715                                         "Inconsistent state of rx queues\n");
 716                         } else {
 717                                 ena_assert_msg(
 718                                         dev->data->tx_queues[i] == &queues[i],
 719                                         "Inconsistent state of tx queues\n");
 720                         }
 721
 722                         rc = ena_queue_restart(&queues[i]);
 723
 724                         if (rc) {
 725                                 PMD_INIT_LOG(ERR,
 726                                              "failed to restart queue %d type(%d)\n",
 727                                              i, ring_type);
 728                                 return -1;
 729                         }
 730                 }
 731         }
 732
 733         return 0;
 734 }
 735
 736 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 737 {
 738         uint32_t max_frame_len = adapter->max_mtu;
 739
 740         if (adapter->rte_eth_dev_data->dev_conf.rxmode.jumbo_frame == 1)
 741                 max_frame_len =
 742                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 743
 744         return max_frame_len;
 745 }
 746
 747 static int ena_check_valid_conf(struct ena_adapter *adapter)
 748 {
 749         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 750
 751         if (max_frame_len > adapter->max_mtu) {
 752                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d\n", max_frame_len);
 753                 return -1;
 754         }
 755
 756         return 0;
 757 }
 758
 759 static int
 760 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 761                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 762 {
 763         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 764
 765         queue_size = RTE_MIN(queue_size,
 766                              get_feat_ctx->max_queues.max_cq_depth);
 767         queue_size = RTE_MIN(queue_size,
 768                              get_feat_ctx->max_queues.max_sq_depth);
 769
 770         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 771                 queue_size = RTE_MIN(queue_size,
 772                                      get_feat_ctx->max_queues.max_llq_depth);
 773
 774         /* Round down to power of 2 */
 775         if (!rte_is_power_of_2(queue_size))
 776                 queue_size = rte_align32pow2(queue_size >> 1);
 777
 778         if (queue_size == 0) {
 779                 PMD_INIT_LOG(ERR, "Invalid queue size\n");
 780                 return -EFAULT;
 781         }
 782
 783         return queue_size;
 784 }
 785
 786 static void ena_stats_restart(struct rte_eth_dev *dev)
 787 {
 788         struct ena_adapter *adapter =
 789                 (struct ena_adapter *)(dev->data->dev_private);
 790
 791         rte_atomic64_init(&adapter->drv_stats->ierrors);
 792         rte_atomic64_init(&adapter->drv_stats->oerrors);
 793         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 794 }
 795
 796 static void ena_stats_get(struct rte_eth_dev *dev,
 797                           struct rte_eth_stats *stats)
 798 {
 799         struct ena_admin_basic_stats ena_stats;
 800         struct ena_adapter *adapter =
 801                 (struct ena_adapter *)(dev->data->dev_private);
 802         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 803         int rc;
 804
 805         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 806                 return;
 807
 808         memset(&ena_stats, 0, sizeof(ena_stats));
 809         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 810         if (unlikely(rc)) {
 811                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 812                 return;
 813         }
 814
 815         /* Set of basic statistics from ENA */
 816         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 817                                           ena_stats.rx_pkts_low);
 818         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 819                                           ena_stats.tx_pkts_low);
 820         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 821                                         ena_stats.rx_bytes_low);
 822         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 823                                         ena_stats.tx_bytes_low);
 824         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 825                                          ena_stats.rx_drops_low);
 826
 827         /* Driver related stats */
 828         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 829         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 830         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 831 }
 832
 833 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 834 {
 835         struct ena_adapter *adapter;
 836         struct ena_com_dev *ena_dev;
 837         int rc = 0;
 838
 839         ena_assert_msg(dev->data != NULL, "Uninitialized device");
 840         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
 841         adapter = (struct ena_adapter *)(dev->data->dev_private);
 842
 843         ena_dev = &adapter->ena_dev;
 844         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
 845
 846         if (mtu > ena_get_mtu_conf(adapter)) {
 847                 RTE_LOG(ERR, PMD,
 848                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
 849                         mtu, ena_get_mtu_conf(adapter));
 850                 rc = -EINVAL;
 851                 goto err;
 852         }
 853
 854         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 855         if (rc)
 856                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
 857         else
 858                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
 859
 860 err:
 861         return rc;
 862 }
 863
 864 static int ena_start(struct rte_eth_dev *dev)
 865 {
 866         struct ena_adapter *adapter =
 867                 (struct ena_adapter *)(dev->data->dev_private);
 868         int rc = 0;
 869
 870         if (!(adapter->state == ENA_ADAPTER_STATE_CONFIG ||
 871               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
 872                 PMD_INIT_LOG(ERR, "API violation");
 873                 return -1;
 874         }
 875
 876         rc = ena_check_valid_conf(adapter);
 877         if (rc)
 878                 return rc;
 879
 880         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
 881         if (rc)
 882                 return rc;
 883
 884         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
 885         if (rc)
 886                 return rc;
 887
 888         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
 889             ETH_MQ_RX_RSS_FLAG) {
 890                 rc = ena_rss_init_default(adapter);
 891                 if (rc)
 892                         return rc;
 893         }
 894
 895         ena_stats_restart(dev);
 896
 897         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 898
 899         return 0;
 900 }
 901
 902 static int ena_queue_restart(struct ena_ring *ring)
 903 {
 904         int rc;
 905
 906         ena_assert_msg(ring->configured == 1,
 907                        "Trying to restart unconfigured queue\n");
 908
 909         ring->next_to_clean = 0;
 910         ring->next_to_use = 0;
 911
 912         if (ring->type == ENA_RING_TYPE_TX)
 913                 return 0;
 914
 915         rc = ena_populate_rx_queue(ring, ring->ring_size - 1);
 916         if ((unsigned int)rc != ring->ring_size - 1) {
 917                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !\n");
 918                 return (-1);
 919         }
 920
 921         return 0;
 922 }
 923
 924 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
 925                               uint16_t queue_idx,
 926                               uint16_t nb_desc,
 927                               __rte_unused unsigned int socket_id,
 928                               __rte_unused const struct rte_eth_txconf *tx_conf)
 929 {
 930         struct ena_com_create_io_ctx ctx =
 931                 /* policy set to _HOST just to satisfy icc compiler */
 932                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
 933                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
 934         struct ena_ring *txq = NULL;
 935         struct ena_adapter *adapter =
 936                 (struct ena_adapter *)(dev->data->dev_private);
 937         unsigned int i;
 938         int ena_qid;
 939         int rc;
 940         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 941
 942         txq = &adapter->tx_ring[queue_idx];
 943
 944         if (txq->configured) {
 945                 RTE_LOG(CRIT, PMD,
 946                         "API violation. Queue %d is already configured\n",
 947                         queue_idx);
 948                 return -1;
 949         }
 950
 951         if (nb_desc > adapter->tx_ring_size) {
 952                 RTE_LOG(ERR, PMD,
 953                         "Unsupported size of TX queue (max size: %d)\n",
 954                         adapter->tx_ring_size);
 955                 return -EINVAL;
 956         }
 957
 958         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
 959
 960         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
 961         ctx.qid = ena_qid;
 962         ctx.msix_vector = -1; /* admin interrupts not used */
 963         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
 964         ctx.queue_size = adapter->tx_ring_size;
 965
 966         rc = ena_com_create_io_queue(ena_dev, &ctx);
 967         if (rc) {
 968                 RTE_LOG(ERR, PMD,
 969                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
 970                         queue_idx, ena_qid, rc);
 971         }
 972         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
 973         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
 974
 975         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
 976                                      &txq->ena_com_io_sq,
 977                                      &txq->ena_com_io_cq);
 978         if (rc) {
 979                 RTE_LOG(ERR, PMD,
 980                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
 981                         queue_idx, rc);
 982                 ena_com_destroy_io_queue(ena_dev, ena_qid);
 983                 goto err;
 984         }
 985
 986         txq->port_id = dev->data->port_id;
 987         txq->next_to_clean = 0;
 988         txq->next_to_use = 0;
 989         txq->ring_size = nb_desc;
 990
 991         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
 992                                           sizeof(struct ena_tx_buffer) *
 993                                           txq->ring_size,
 994                                           RTE_CACHE_LINE_SIZE);
 995         if (!txq->tx_buffer_info) {
 996                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
 997                 return -ENOMEM;
 998         }
 999
1000         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1001                                          sizeof(u16) * txq->ring_size,
1002                                          RTE_CACHE_LINE_SIZE);
1003         if (!txq->empty_tx_reqs) {
1004                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1005                 rte_free(txq->tx_buffer_info);
1006                 return -ENOMEM;
1007         }
1008         for (i = 0; i < txq->ring_size; i++)
1009                 txq->empty_tx_reqs[i] = i;
1010
1011         /* Store pointer to this queue in upper layer */
1012         txq->configured = 1;
1013         dev->data->tx_queues[queue_idx] = txq;
1014 err:
1015         return rc;
1016 }
1017
1018 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1019                               uint16_t queue_idx,
1020                               uint16_t nb_desc,
1021                               __rte_unused unsigned int socket_id,
1022                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1023                               struct rte_mempool *mp)
1024 {
1025         struct ena_com_create_io_ctx ctx =
1026                 /* policy set to _HOST just to satisfy icc compiler */
1027                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1028                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1029         struct ena_adapter *adapter =
1030                 (struct ena_adapter *)(dev->data->dev_private);
1031         struct ena_ring *rxq = NULL;
1032         uint16_t ena_qid = 0;
1033         int rc = 0;
1034         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1035
1036         rxq = &adapter->rx_ring[queue_idx];
1037         if (rxq->configured) {
1038                 RTE_LOG(CRIT, PMD,
1039                         "API violation. Queue %d is already configured\n",
1040                         queue_idx);
1041                 return -1;
1042         }
1043
1044         if (nb_desc > adapter->rx_ring_size) {
1045                 RTE_LOG(ERR, PMD,
1046                         "Unsupported size of RX queue (max size: %d)\n",
1047                         adapter->rx_ring_size);
1048                 return -EINVAL;
1049         }
1050
1051         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1052
1053         ctx.qid = ena_qid;
1054         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1055         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1056         ctx.msix_vector = -1; /* admin interrupts not used */
1057         ctx.queue_size = adapter->rx_ring_size;
1058
1059         rc = ena_com_create_io_queue(ena_dev, &ctx);
1060         if (rc)
1061                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1062                         queue_idx, rc);
1063
1064         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1065         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1066
1067         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1068                                      &rxq->ena_com_io_sq,
1069                                      &rxq->ena_com_io_cq);
1070         if (rc) {
1071                 RTE_LOG(ERR, PMD,
1072                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1073                         queue_idx, rc);
1074                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1075         }
1076
1077         rxq->port_id = dev->data->port_id;
1078         rxq->next_to_clean = 0;
1079         rxq->next_to_use = 0;
1080         rxq->ring_size = nb_desc;
1081         rxq->mb_pool = mp;
1082
1083         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1084                                           sizeof(struct rte_mbuf *) * nb_desc,
1085                                           RTE_CACHE_LINE_SIZE);
1086         if (!rxq->rx_buffer_info) {
1087                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1088                 return -ENOMEM;
1089         }
1090
1091         /* Store pointer to this queue in upper layer */
1092         rxq->configured = 1;
1093         dev->data->rx_queues[queue_idx] = rxq;
1094
1095         return rc;
1096 }
1097
1098 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1099 {
1100         unsigned int i;
1101         int rc;
1102         unsigned int ring_size = rxq->ring_size;
1103         unsigned int ring_mask = ring_size - 1;
1104         int next_to_use = rxq->next_to_use & ring_mask;
1105         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1106
1107         if (unlikely(!count))
1108                 return 0;
1109
1110         ena_assert_msg((((ENA_CIRC_COUNT(rxq->next_to_use, rxq->next_to_clean,
1111                                          rxq->ring_size)) +
1112                          count) < rxq->ring_size), "bad ring state");
1113
1114         count = RTE_MIN(count, ring_size - next_to_use);
1115
1116         /* get resources for incoming packets */
1117         rc = rte_mempool_get_bulk(rxq->mb_pool,
1118                                   (void **)(&mbufs[next_to_use]), count);
1119         if (unlikely(rc < 0)) {
1120                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1121                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1122                 return 0;
1123         }
1124
1125         for (i = 0; i < count; i++) {
1126                 struct rte_mbuf *mbuf = mbufs[next_to_use];
1127                 struct ena_com_buf ebuf;
1128
1129                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1130                 /* prepare physical address for DMA transaction */
1131                 ebuf.paddr = mbuf->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1132                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1133                 /* pass resource to device */
1134                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1135                                                 &ebuf, next_to_use);
1136                 if (unlikely(rc)) {
1137                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1138                         break;
1139                 }
1140                 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use, ring_size);
1141         }
1142
1143         rte_wmb();
1144         rxq->next_to_use = next_to_use;
1145         /* let HW know that it can fill buffers with data */
1146         ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1147
1148         return i;
1149 }
1150
1151 static int ena_device_init(struct ena_com_dev *ena_dev,
1152                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1153 {
1154         int rc;
1155         bool readless_supported;
1156
1157         /* Initialize mmio registers */
1158         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1159         if (rc) {
1160                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1161                 return rc;
1162         }
1163
1164         /* The PCIe configuration space revision id indicate if mmio reg
1165          * read is disabled.
1166          */
1167         readless_supported =
1168                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1169                                & ENA_MMIO_DISABLE_REG_READ);
1170         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1171
1172         /* reset device */
1173         rc = ena_com_dev_reset(ena_dev);
1174         if (rc) {
1175                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1176                 goto err_mmio_read_less;
1177         }
1178
1179         /* check FW version */
1180         rc = ena_com_validate_version(ena_dev);
1181         if (rc) {
1182                 RTE_LOG(ERR, PMD, "device version is too low\n");
1183                 goto err_mmio_read_less;
1184         }
1185
1186         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1187
1188         /* ENA device administration layer init */
1189         rc = ena_com_admin_init(ena_dev, NULL, true);
1190         if (rc) {
1191                 RTE_LOG(ERR, PMD,
1192                         "cannot initialize ena admin queue with device\n");
1193                 goto err_mmio_read_less;
1194         }
1195
1196         ena_config_host_info(ena_dev);
1197
1198         /* To enable the msix interrupts the driver needs to know the number
1199          * of queues. So the driver uses polling mode to retrieve this
1200          * information.
1201          */
1202         ena_com_set_admin_polling_mode(ena_dev, true);
1203
1204         /* Get Device Attributes and features */
1205         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1206         if (rc) {
1207                 RTE_LOG(ERR, PMD,
1208                         "cannot get attribute for ena device rc= %d\n", rc);
1209                 goto err_admin_init;
1210         }
1211
1212         return 0;
1213
1214 err_admin_init:
1215         ena_com_admin_destroy(ena_dev);
1216
1217 err_mmio_read_less:
1218         ena_com_mmio_reg_read_request_destroy(ena_dev);
1219
1220         return rc;
1221 }
1222
1223 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1224 {
1225         struct rte_pci_device *pci_dev;
1226         struct ena_adapter *adapter =
1227                 (struct ena_adapter *)(eth_dev->data->dev_private);
1228         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1229         struct ena_com_dev_get_features_ctx get_feat_ctx;
1230         int queue_size, rc;
1231
1232         static int adapters_found;
1233
1234         memset(adapter, 0, sizeof(struct ena_adapter));
1235         ena_dev = &adapter->ena_dev;
1236
1237         eth_dev->dev_ops = &ena_dev_ops;
1238         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1239         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1240         adapter->rte_eth_dev_data = eth_dev->data;
1241         adapter->rte_dev = eth_dev;
1242
1243         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1244                 return 0;
1245
1246         pci_dev = eth_dev->pci_dev;
1247         adapter->pdev = pci_dev;
1248
1249         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
1250                      pci_dev->addr.domain,
1251                      pci_dev->addr.bus,
1252                      pci_dev->addr.devid,
1253                      pci_dev->addr.function);
1254
1255         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1256         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1257
1258         /* Present ENA_MEM_BAR indicates available LLQ mode.
1259          * Use corresponding policy
1260          */
1261         if (adapter->dev_mem_base)
1262                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
1263         else if (adapter->regs)
1264                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1265         else
1266                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
1267                              ENA_REGS_BAR);
1268
1269         ena_dev->reg_bar = adapter->regs;
1270         ena_dev->dmadev = adapter->pdev;
1271
1272         adapter->id_number = adapters_found;
1273
1274         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1275                  adapter->id_number);
1276
1277         /* device specific initialization routine */
1278         rc = ena_device_init(ena_dev, &get_feat_ctx);
1279         if (rc) {
1280                 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
1281                 return -1;
1282         }
1283
1284         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1285                 if (get_feat_ctx.max_queues.max_llq_num == 0) {
1286                         PMD_INIT_LOG(ERR,
1287                                      "Trying to use LLQ but llq_num is 0.\n"
1288                                      "Fall back into regular queues.\n");
1289                         ena_dev->tx_mem_queue_type =
1290                                 ENA_ADMIN_PLACEMENT_POLICY_HOST;
1291                         adapter->num_queues =
1292                                 get_feat_ctx.max_queues.max_sq_num;
1293                 } else {
1294                         adapter->num_queues =
1295                                 get_feat_ctx.max_queues.max_llq_num;
1296                 }
1297         } else {
1298                 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1299         }
1300
1301         queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1302         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1303                 return -EFAULT;
1304
1305         adapter->tx_ring_size = queue_size;
1306         adapter->rx_ring_size = queue_size;
1307
1308         /* prepare ring structures */
1309         ena_init_rings(adapter);
1310
1311         ena_config_debug_area(adapter);
1312
1313         /* Set max MTU for this device */
1314         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1315
1316         /* Copy MAC address and point DPDK to it */
1317         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1318         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1319                         (struct ether_addr *)adapter->mac_addr);
1320
1321         adapter->drv_stats = rte_zmalloc("adapter stats",
1322                                          sizeof(*adapter->drv_stats),
1323                                          RTE_CACHE_LINE_SIZE);
1324         if (!adapter->drv_stats) {
1325                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1326                 return -ENOMEM;
1327         }
1328
1329         adapters_found++;
1330         adapter->state = ENA_ADAPTER_STATE_INIT;
1331
1332         return 0;
1333 }
1334
1335 static int ena_dev_configure(struct rte_eth_dev *dev)
1336 {
1337         struct ena_adapter *adapter =
1338                 (struct ena_adapter *)(dev->data->dev_private);
1339
1340         if (!(adapter->state == ENA_ADAPTER_STATE_INIT ||
1341               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
1342                 PMD_INIT_LOG(ERR, "Illegal adapter state: %d\n",
1343                              adapter->state);
1344                 return -1;
1345         }
1346
1347         switch (adapter->state) {
1348         case ENA_ADAPTER_STATE_INIT:
1349         case ENA_ADAPTER_STATE_STOPPED:
1350                 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1351                 break;
1352         case ENA_ADAPTER_STATE_CONFIG:
1353                 RTE_LOG(WARNING, PMD,
1354                         "Ivalid driver state while trying to configure device\n");
1355                 break;
1356         default:
1357                 break;
1358         }
1359
1360         return 0;
1361 }
1362
1363 static void ena_init_rings(struct ena_adapter *adapter)
1364 {
1365         int i;
1366
1367         for (i = 0; i < adapter->num_queues; i++) {
1368                 struct ena_ring *ring = &adapter->tx_ring[i];
1369
1370                 ring->configured = 0;
1371                 ring->type = ENA_RING_TYPE_TX;
1372                 ring->adapter = adapter;
1373                 ring->id = i;
1374                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1375                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1376         }
1377
1378         for (i = 0; i < adapter->num_queues; i++) {
1379                 struct ena_ring *ring = &adapter->rx_ring[i];
1380
1381                 ring->configured = 0;
1382                 ring->type = ENA_RING_TYPE_RX;
1383                 ring->adapter = adapter;
1384                 ring->id = i;
1385         }
1386 }
1387
1388 static void ena_infos_get(struct rte_eth_dev *dev,
1389                           struct rte_eth_dev_info *dev_info)
1390 {
1391         struct ena_adapter *adapter;
1392         struct ena_com_dev *ena_dev;
1393         struct ena_com_dev_get_features_ctx feat;
1394         uint32_t rx_feat = 0, tx_feat = 0;
1395         int rc = 0;
1396
1397         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1398         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1399         adapter = (struct ena_adapter *)(dev->data->dev_private);
1400
1401         ena_dev = &adapter->ena_dev;
1402         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1403
1404         dev_info->speed_capa =
1405                         ETH_LINK_SPEED_1G   |
1406                         ETH_LINK_SPEED_2_5G |
1407                         ETH_LINK_SPEED_5G   |
1408                         ETH_LINK_SPEED_10G  |
1409                         ETH_LINK_SPEED_25G  |
1410                         ETH_LINK_SPEED_40G  |
1411                         ETH_LINK_SPEED_50G  |
1412                         ETH_LINK_SPEED_100G;
1413
1414         /* Get supported features from HW */
1415         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1416         if (unlikely(rc)) {
1417                 RTE_LOG(ERR, PMD,
1418                         "Cannot get attribute for ena device rc= %d\n", rc);
1419                 return;
1420         }
1421
1422         /* Set Tx & Rx features available for device */
1423         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1424                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1425
1426         if (feat.offload.tx &
1427             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1428                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1429                         DEV_TX_OFFLOAD_UDP_CKSUM |
1430                         DEV_TX_OFFLOAD_TCP_CKSUM;
1431
1432         if (feat.offload.tx &
1433             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1434                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1435                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1436                         DEV_RX_OFFLOAD_TCP_CKSUM;
1437
1438         /* Inform framework about available features */
1439         dev_info->rx_offload_capa = rx_feat;
1440         dev_info->tx_offload_capa = tx_feat;
1441
1442         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1443         dev_info->max_rx_pktlen  = adapter->max_mtu;
1444         dev_info->max_mac_addrs = 1;
1445
1446         dev_info->max_rx_queues = adapter->num_queues;
1447         dev_info->max_tx_queues = adapter->num_queues;
1448         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1449 }
1450
1451 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1452                                   uint16_t nb_pkts)
1453 {
1454         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1455         unsigned int ring_size = rx_ring->ring_size;
1456         unsigned int ring_mask = ring_size - 1;
1457         uint16_t next_to_clean = rx_ring->next_to_clean;
1458         int desc_in_use = 0;
1459         unsigned int recv_idx = 0;
1460         struct rte_mbuf *mbuf = NULL;
1461         struct rte_mbuf *mbuf_head = NULL;
1462         struct rte_mbuf *mbuf_prev = NULL;
1463         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1464         unsigned int completed;
1465
1466         struct ena_com_rx_ctx ena_rx_ctx;
1467         int rc = 0;
1468
1469         /* Check adapter state */
1470         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1471                 RTE_LOG(ALERT, PMD,
1472                         "Trying to receive pkts while device is NOT running\n");
1473                 return 0;
1474         }
1475
1476         desc_in_use = ENA_CIRC_COUNT(rx_ring->next_to_use,
1477                                      next_to_clean, ring_size);
1478         if (unlikely(nb_pkts > desc_in_use))
1479                 nb_pkts = desc_in_use;
1480
1481         for (completed = 0; completed < nb_pkts; completed++) {
1482                 int segments = 0;
1483
1484                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1485                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1486                 ena_rx_ctx.descs = 0;
1487                 /* receive packet context */
1488                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1489                                     rx_ring->ena_com_io_sq,
1490                                     &ena_rx_ctx);
1491                 if (unlikely(rc)) {
1492                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1493                         return 0;
1494                 }
1495
1496                 if (unlikely(ena_rx_ctx.descs == 0))
1497                         break;
1498
1499                 while (segments < ena_rx_ctx.descs) {
1500                         mbuf = rx_buff_info[next_to_clean & ring_mask];
1501                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1502                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1503                         mbuf->refcnt = 1;
1504                         mbuf->next = NULL;
1505                         if (segments == 0) {
1506                                 mbuf->nb_segs = ena_rx_ctx.descs;
1507                                 mbuf->port = rx_ring->port_id;
1508                                 mbuf->pkt_len = 0;
1509                                 mbuf_head = mbuf;
1510                         } else {
1511                                 /* for multi-segment pkts create mbuf chain */
1512                                 mbuf_prev->next = mbuf;
1513                         }
1514                         mbuf_head->pkt_len += mbuf->data_len;
1515
1516                         mbuf_prev = mbuf;
1517                         segments++;
1518                         next_to_clean =
1519                                 ENA_RX_RING_IDX_NEXT(next_to_clean, ring_size);
1520                 }
1521
1522                 /* fill mbuf attributes if any */
1523                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1524                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1525
1526                 /* pass to DPDK application head mbuf */
1527                 rx_pkts[recv_idx] = mbuf_head;
1528                 recv_idx++;
1529         }
1530
1531         /* Burst refill to save doorbells, memory barriers, const interval */
1532         if (ring_size - desc_in_use - 1 > ENA_RING_DESCS_RATIO(ring_size))
1533                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use - 1);
1534
1535         rx_ring->next_to_clean = next_to_clean & ring_mask;
1536
1537         return recv_idx;
1538 }
1539
1540 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1541                                   uint16_t nb_pkts)
1542 {
1543         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1544         unsigned int next_to_use = tx_ring->next_to_use;
1545         struct rte_mbuf *mbuf;
1546         unsigned int ring_size = tx_ring->ring_size;
1547         unsigned int ring_mask = ring_size - 1;
1548         struct ena_com_tx_ctx ena_tx_ctx;
1549         struct ena_tx_buffer *tx_info;
1550         struct ena_com_buf *ebuf;
1551         uint16_t rc, req_id, total_tx_descs = 0;
1552         int sent_idx = 0;
1553         int nb_hw_desc;
1554
1555         /* Check adapter state */
1556         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1557                 RTE_LOG(ALERT, PMD,
1558                         "Trying to xmit pkts while device is NOT running\n");
1559                 return 0;
1560         }
1561
1562         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1563                 mbuf = tx_pkts[sent_idx];
1564
1565                 req_id = tx_ring->empty_tx_reqs[next_to_use];
1566                 tx_info = &tx_ring->tx_buffer_info[req_id];
1567                 tx_info->mbuf = mbuf;
1568                 tx_info->num_of_bufs = 0;
1569                 ebuf = tx_info->bufs;
1570
1571                 /* Prepare TX context */
1572                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1573                 memset(&ena_tx_ctx.ena_meta, 0x0,
1574                        sizeof(struct ena_com_tx_meta));
1575                 ena_tx_ctx.ena_bufs = ebuf;
1576                 ena_tx_ctx.req_id = req_id;
1577                 if (tx_ring->tx_mem_queue_type ==
1578                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1579                         /* prepare the push buffer with
1580                          * virtual address of the data
1581                          */
1582                         ena_tx_ctx.header_len =
1583                                 RTE_MIN(mbuf->data_len,
1584                                         tx_ring->tx_max_header_size);
1585                         ena_tx_ctx.push_header =
1586                                 (void *)((char *)mbuf->buf_addr +
1587                                          mbuf->data_off);
1588                 } /* there's no else as we take advantage of memset zeroing */
1589
1590                 /* Set TX offloads flags, if applicable */
1591                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx);
1592
1593                 if (unlikely(mbuf->ol_flags &
1594                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1595                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1596
1597                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1598
1599                 /* Process first segment taking into
1600                  * consideration pushed header
1601                  */
1602                 if (mbuf->data_len > ena_tx_ctx.header_len) {
1603                         ebuf->paddr = mbuf->buf_physaddr +
1604                                       mbuf->data_off +
1605                                       ena_tx_ctx.header_len;
1606                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1607                         ebuf++;
1608                         tx_info->num_of_bufs++;
1609                 }
1610
1611                 while ((mbuf = mbuf->next) != NULL) {
1612                         ebuf->paddr = mbuf->buf_physaddr + mbuf->data_off;
1613                         ebuf->len = mbuf->data_len;
1614                         ebuf++;
1615                         tx_info->num_of_bufs++;
1616                 }
1617
1618                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1619
1620                 /* Write data to device */
1621                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1622                                         &ena_tx_ctx, &nb_hw_desc);
1623                 if (unlikely(rc))
1624                         break;
1625
1626                 tx_info->tx_descs = nb_hw_desc;
1627
1628                 next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use, ring_size);
1629         }
1630
1631         /* Let HW do it's best :-) */
1632         rte_wmb();
1633         ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1634
1635         /* Clear complete packets  */
1636         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1637                 /* Get Tx info & store how many descs were processed  */
1638                 tx_info = &tx_ring->tx_buffer_info[req_id];
1639                 total_tx_descs += tx_info->tx_descs;
1640
1641                 /* Free whole mbuf chain  */
1642                 mbuf = tx_info->mbuf;
1643                 rte_pktmbuf_free(mbuf);
1644
1645                 /* Put back descriptor to the ring for reuse */
1646                 tx_ring->empty_tx_reqs[tx_ring->next_to_clean] = req_id;
1647                 tx_ring->next_to_clean =
1648                         ENA_TX_RING_IDX_NEXT(tx_ring->next_to_clean,
1649                                              tx_ring->ring_size);
1650
1651                 /* If too many descs to clean, leave it for another run */
1652                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1653                         break;
1654         }
1655
1656         /* acknowledge completion of sent packets */
1657         ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1658         tx_ring->next_to_use = next_to_use;
1659         return sent_idx;
1660 }
1661
1662 static struct eth_driver rte_ena_pmd = {
1663         {
1664                 .name = "rte_ena_pmd",
1665                 .id_table = pci_id_ena_map,
1666                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1667         },
1668         .eth_dev_init = eth_ena_dev_init,
1669         .dev_private_size = sizeof(struct ena_adapter),
1670 };
1671
1672 static int
1673 rte_ena_pmd_init(const char *name __rte_unused,
1674                  const char *params __rte_unused)
1675 {
1676         rte_eth_driver_register(&rte_ena_pmd);
1677         return 0;
1678 };
1679
1680 struct rte_driver ena_pmd_drv = {
1681         .type = PMD_PDEV,
1682         .init = rte_ena_pmd_init,
1683 };
1684
1685 PMD_REGISTER_DRIVER(ena_pmd_drv, ena);
1686 DRIVER_REGISTER_PCI_TABLE(ena, pci_id_ena_map);