drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 0
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 enum ethtool_stringset {
  89         ETH_SS_TEST             = 0,
  90         ETH_SS_STATS,
  91 };
  92
  93 struct ena_stats {
  94         char name[ETH_GSTRING_LEN];
  95         int stat_offset;
  96 };
  97
  98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
  99         .name = #stat, \
 100         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 101 }
 102
 103 #define ENA_STAT_ENTRY(stat, stat_type) { \
 104         .name = #stat, \
 105         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 106 }
 107
 108 #define ENA_STAT_RX_ENTRY(stat) \
 109         ENA_STAT_ENTRY(stat, rx)
 110
 111 #define ENA_STAT_TX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, tx)
 113
 114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, dev)
 116
 117 /*
 118  * Each rte_memzone should have unique name.
 119  * To satisfy it, count number of allocation and add it to name.
 120  */
 121 uint32_t ena_alloc_cnt;
 122
 123 static const struct ena_stats ena_stats_global_strings[] = {
 124         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 125         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 126         ENA_STAT_GLOBAL_ENTRY(io_resume),
 127         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 128         ENA_STAT_GLOBAL_ENTRY(interface_up),
 129         ENA_STAT_GLOBAL_ENTRY(interface_down),
 130         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 131 };
 132
 133 static const struct ena_stats ena_stats_tx_strings[] = {
 134         ENA_STAT_TX_ENTRY(cnt),
 135         ENA_STAT_TX_ENTRY(bytes),
 136         ENA_STAT_TX_ENTRY(queue_stop),
 137         ENA_STAT_TX_ENTRY(queue_wakeup),
 138         ENA_STAT_TX_ENTRY(dma_mapping_err),
 139         ENA_STAT_TX_ENTRY(linearize),
 140         ENA_STAT_TX_ENTRY(linearize_failed),
 141         ENA_STAT_TX_ENTRY(tx_poll),
 142         ENA_STAT_TX_ENTRY(doorbells),
 143         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 144         ENA_STAT_TX_ENTRY(missing_tx_comp),
 145         ENA_STAT_TX_ENTRY(bad_req_id),
 146 };
 147
 148 static const struct ena_stats ena_stats_rx_strings[] = {
 149         ENA_STAT_RX_ENTRY(cnt),
 150         ENA_STAT_RX_ENTRY(bytes),
 151         ENA_STAT_RX_ENTRY(refil_partial),
 152         ENA_STAT_RX_ENTRY(bad_csum),
 153         ENA_STAT_RX_ENTRY(page_alloc_fail),
 154         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 155         ENA_STAT_RX_ENTRY(dma_mapping_err),
 156         ENA_STAT_RX_ENTRY(bad_desc_num),
 157         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 158 };
 159
 160 static const struct ena_stats ena_stats_ena_com_strings[] = {
 161         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 162         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 163         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 164         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 165         ENA_STAT_ENA_COM_ENTRY(no_completion),
 166 };
 167
 168 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 169 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 170 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 171 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 172
 173 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 174                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 175                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 176                         DEV_TX_OFFLOAD_TCP_TSO)
 177 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 178                        PKT_TX_IP_CKSUM |\
 179                        PKT_TX_TCP_SEG)
 180
 181 /** Vendor ID used by Amazon devices */
 182 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 183 /** Amazon devices */
 184 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 185 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 186
 187 #define ENA_TX_OFFLOAD_MASK     (\
 188         PKT_TX_L4_MASK |         \
 189         PKT_TX_IP_CKSUM |        \
 190         PKT_TX_TCP_SEG)
 191
 192 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 193         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 194
 195 int ena_logtype_init;
 196 int ena_logtype_driver;
 197
 198 static const struct rte_pci_id pci_id_ena_map[] = {
 199         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 200         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 201         { .device_id = 0 },
 202 };
 203
 204 static struct ena_aenq_handlers empty_aenq_handlers;
 205
 206 static int ena_device_init(struct ena_com_dev *ena_dev,
 207                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 208 static int ena_dev_configure(struct rte_eth_dev *dev);
 209 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 210                                   uint16_t nb_pkts);
 211 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 212                 uint16_t nb_pkts);
 213 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 214                               uint16_t nb_desc, unsigned int socket_id,
 215                               const struct rte_eth_txconf *tx_conf);
 216 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 217                               uint16_t nb_desc, unsigned int socket_id,
 218                               const struct rte_eth_rxconf *rx_conf,
 219                               struct rte_mempool *mp);
 220 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 221                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 222 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 223 static void ena_init_rings(struct ena_adapter *adapter);
 224 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 225 static int ena_start(struct rte_eth_dev *dev);
 226 static void ena_stop(struct rte_eth_dev *dev);
 227 static void ena_close(struct rte_eth_dev *dev);
 228 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 229 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 230 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 231 static void ena_rx_queue_release(void *queue);
 232 static void ena_tx_queue_release(void *queue);
 233 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 234 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 235 static int ena_link_update(struct rte_eth_dev *dev,
 236                            int wait_to_complete);
 237 static int ena_queue_restart(struct ena_ring *ring);
 238 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 239                                  enum ena_ring_type ring_type);
 240 static void ena_stats_restart(struct rte_eth_dev *dev);
 241 static void ena_infos_get(struct rte_eth_dev *dev,
 242                           struct rte_eth_dev_info *dev_info);
 243 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 244                                struct rte_eth_rss_reta_entry64 *reta_conf,
 245                                uint16_t reta_size);
 246 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 247                               struct rte_eth_rss_reta_entry64 *reta_conf,
 248                               uint16_t reta_size);
 249 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 250 static void ena_interrupt_handler_rte(void *cb_arg);
 251
 252 static const struct eth_dev_ops ena_dev_ops = {
 253         .dev_configure        = ena_dev_configure,
 254         .dev_infos_get        = ena_infos_get,
 255         .rx_queue_setup       = ena_rx_queue_setup,
 256         .tx_queue_setup       = ena_tx_queue_setup,
 257         .dev_start            = ena_start,
 258         .dev_stop             = ena_stop,
 259         .link_update          = ena_link_update,
 260         .stats_get            = ena_stats_get,
 261         .mtu_set              = ena_mtu_set,
 262         .rx_queue_release     = ena_rx_queue_release,
 263         .tx_queue_release     = ena_tx_queue_release,
 264         .dev_close            = ena_close,
 265         .reta_update          = ena_rss_reta_update,
 266         .reta_query           = ena_rss_reta_query,
 267 };
 268
 269 #define NUMA_NO_NODE    SOCKET_ID_ANY
 270
 271 static inline int ena_cpu_to_node(int cpu)
 272 {
 273         struct rte_config *config = rte_eal_get_configuration();
 274         struct rte_fbarray *arr = &config->mem_config->memzones;
 275         const struct rte_memzone *mz;
 276
 277         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 278                 return NUMA_NO_NODE;
 279
 280         mz = rte_fbarray_get(arr, cpu);
 281
 282         return mz->socket_id;
 283 }
 284
 285 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 286                                        struct ena_com_rx_ctx *ena_rx_ctx)
 287 {
 288         uint64_t ol_flags = 0;
 289         uint32_t packet_type = 0;
 290
 291         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 292                 packet_type |= RTE_PTYPE_L4_TCP;
 293         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 294                 packet_type |= RTE_PTYPE_L4_UDP;
 295
 296         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 297                 packet_type |= RTE_PTYPE_L3_IPV4;
 298         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 299                 packet_type |= RTE_PTYPE_L3_IPV6;
 300
 301         if (unlikely(ena_rx_ctx->l4_csum_err))
 302                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 303         if (unlikely(ena_rx_ctx->l3_csum_err))
 304                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 305
 306         mbuf->ol_flags = ol_flags;
 307         mbuf->packet_type = packet_type;
 308 }
 309
 310 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 311                                        struct ena_com_tx_ctx *ena_tx_ctx,
 312                                        uint64_t queue_offloads)
 313 {
 314         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 315
 316         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 317             (queue_offloads & QUEUE_OFFLOADS)) {
 318                 /* check if TSO is required */
 319                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 320                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 321                         ena_tx_ctx->tso_enable = true;
 322
 323                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 324                 }
 325
 326                 /* check if L3 checksum is needed */
 327                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 328                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 329                         ena_tx_ctx->l3_csum_enable = true;
 330
 331                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 332                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 333                 } else {
 334                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 335
 336                         /* set don't fragment (DF) flag */
 337                         if (mbuf->packet_type &
 338                                 (RTE_PTYPE_L4_NONFRAG
 339                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 340                                 ena_tx_ctx->df = true;
 341                 }
 342
 343                 /* check if L4 checksum is needed */
 344                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 345                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 346                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 347                         ena_tx_ctx->l4_csum_enable = true;
 348                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 349                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 350                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 351                         ena_tx_ctx->l4_csum_enable = true;
 352                 } else {
 353                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 354                         ena_tx_ctx->l4_csum_enable = false;
 355                 }
 356
 357                 ena_meta->mss = mbuf->tso_segsz;
 358                 ena_meta->l3_hdr_len = mbuf->l3_len;
 359                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 360
 361                 ena_tx_ctx->meta_valid = true;
 362         } else {
 363                 ena_tx_ctx->meta_valid = false;
 364         }
 365 }
 366
 367 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 368 {
 369         struct ena_admin_host_info *host_info;
 370         int rc;
 371
 372         /* Allocate only the host info */
 373         rc = ena_com_allocate_host_info(ena_dev);
 374         if (rc) {
 375                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 376                 return;
 377         }
 378
 379         host_info = ena_dev->host_attr.host_info;
 380
 381         host_info->os_type = ENA_ADMIN_OS_DPDK;
 382         host_info->kernel_ver = RTE_VERSION;
 383         snprintf((char *)host_info->kernel_ver_str,
 384                  sizeof(host_info->kernel_ver_str),
 385                  "%s", rte_version());
 386         host_info->os_dist = RTE_VERSION;
 387         snprintf((char *)host_info->os_dist_str,
 388                  sizeof(host_info->os_dist_str),
 389                  "%s", rte_version());
 390         host_info->driver_version =
 391                 (DRV_MODULE_VER_MAJOR) |
 392                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 393                 (DRV_MODULE_VER_SUBMINOR <<
 394                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 395
 396         rc = ena_com_set_host_attributes(ena_dev);
 397         if (rc) {
 398                 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 399                 if (rc != -ENA_COM_UNSUPPORTED)
 400                         goto err;
 401         }
 402
 403         return;
 404
 405 err:
 406         ena_com_delete_host_info(ena_dev);
 407 }
 408
 409 static int
 410 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 411 {
 412         if (sset != ETH_SS_STATS)
 413                 return -EOPNOTSUPP;
 414
 415          /* Workaround for clang:
 416          * touch internal structures to prevent
 417          * compiler error
 418          */
 419         ENA_TOUCH(ena_stats_global_strings);
 420         ENA_TOUCH(ena_stats_tx_strings);
 421         ENA_TOUCH(ena_stats_rx_strings);
 422         ENA_TOUCH(ena_stats_ena_com_strings);
 423
 424         return  dev->data->nb_tx_queues *
 425                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 426                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 427 }
 428
 429 static void ena_config_debug_area(struct ena_adapter *adapter)
 430 {
 431         u32 debug_area_size;
 432         int rc, ss_count;
 433
 434         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 435         if (ss_count <= 0) {
 436                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 437                 return;
 438         }
 439
 440         /* allocate 32 bytes for each string and 64bit for the value */
 441         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 442
 443         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 444         if (rc) {
 445                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 446                 return;
 447         }
 448
 449         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 450         if (rc) {
 451                 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 452                 if (rc != -ENA_COM_UNSUPPORTED)
 453                         goto err;
 454         }
 455
 456         return;
 457 err:
 458         ena_com_delete_debug_area(&adapter->ena_dev);
 459 }
 460
 461 static void ena_close(struct rte_eth_dev *dev)
 462 {
 463         struct ena_adapter *adapter =
 464                 (struct ena_adapter *)(dev->data->dev_private);
 465
 466         ena_stop(dev);
 467         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 468
 469         ena_rx_queue_release_all(dev);
 470         ena_tx_queue_release_all(dev);
 471 }
 472
 473 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 474                                struct rte_eth_rss_reta_entry64 *reta_conf,
 475                                uint16_t reta_size)
 476 {
 477         struct ena_adapter *adapter =
 478                 (struct ena_adapter *)(dev->data->dev_private);
 479         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 480         int ret, i;
 481         u16 entry_value;
 482         int conf_idx;
 483         int idx;
 484
 485         if ((reta_size == 0) || (reta_conf == NULL))
 486                 return -EINVAL;
 487
 488         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 489                 RTE_LOG(WARNING, PMD,
 490                         "indirection table %d is bigger than supported (%d)\n",
 491                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 492                 ret = -EINVAL;
 493                 goto err;
 494         }
 495
 496         for (i = 0 ; i < reta_size ; i++) {
 497                 /* each reta_conf is for 64 entries.
 498                  * to support 128 we use 2 conf of 64
 499                  */
 500                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 501                 idx = i % RTE_RETA_GROUP_SIZE;
 502                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 503                         entry_value =
 504                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 505                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 506                                                                 i,
 507                                                                 entry_value);
 508                         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 509                                 RTE_LOG(ERR, PMD,
 510                                         "Cannot fill indirect table\n");
 511                                 ret = -ENOTSUP;
 512                                 goto err;
 513                         }
 514                 }
 515         }
 516
 517         ret = ena_com_indirect_table_set(ena_dev);
 518         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 519                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 520                 ret = -ENOTSUP;
 521                 goto err;
 522         }
 523
 524         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 525                 __func__, reta_size, adapter->rte_dev->data->port_id);
 526 err:
 527         return ret;
 528 }
 529
 530 /* Query redirection table. */
 531 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 532                               struct rte_eth_rss_reta_entry64 *reta_conf,
 533                               uint16_t reta_size)
 534 {
 535         struct ena_adapter *adapter =
 536                 (struct ena_adapter *)(dev->data->dev_private);
 537         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 538         int ret;
 539         int i;
 540         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 541         int reta_conf_idx;
 542         int reta_idx;
 543
 544         if (reta_size == 0 || reta_conf == NULL ||
 545             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 546                 return -EINVAL;
 547
 548         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 549         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 550                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 551                 ret = -ENOTSUP;
 552                 goto err;
 553         }
 554
 555         for (i = 0 ; i < reta_size ; i++) {
 556                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 557                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 558                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 559                         reta_conf[reta_conf_idx].reta[reta_idx] =
 560                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 561         }
 562 err:
 563         return ret;
 564 }
 565
 566 static int ena_rss_init_default(struct ena_adapter *adapter)
 567 {
 568         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 569         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 570         int rc, i;
 571         u32 val;
 572
 573         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 574         if (unlikely(rc)) {
 575                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 576                 goto err_rss_init;
 577         }
 578
 579         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 580                 val = i % nb_rx_queues;
 581                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 582                                                        ENA_IO_RXQ_IDX(val));
 583                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 584                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 585                         goto err_fill_indir;
 586                 }
 587         }
 588
 589         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 590                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 591         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 592                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 593                 goto err_fill_indir;
 594         }
 595
 596         rc = ena_com_set_default_hash_ctrl(ena_dev);
 597         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 598                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 599                 goto err_fill_indir;
 600         }
 601
 602         rc = ena_com_indirect_table_set(ena_dev);
 603         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 604                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 605                 goto err_fill_indir;
 606         }
 607         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 608                 adapter->rte_dev->data->port_id);
 609
 610         return 0;
 611
 612 err_fill_indir:
 613         ena_com_rss_destroy(ena_dev);
 614 err_rss_init:
 615
 616         return rc;
 617 }
 618
 619 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 620 {
 621         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 622         int nb_queues = dev->data->nb_rx_queues;
 623         int i;
 624
 625         for (i = 0; i < nb_queues; i++)
 626                 ena_rx_queue_release(queues[i]);
 627 }
 628
 629 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 630 {
 631         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 632         int nb_queues = dev->data->nb_tx_queues;
 633         int i;
 634
 635         for (i = 0; i < nb_queues; i++)
 636                 ena_tx_queue_release(queues[i]);
 637 }
 638
 639 static void ena_rx_queue_release(void *queue)
 640 {
 641         struct ena_ring *ring = (struct ena_ring *)queue;
 642         struct ena_adapter *adapter = ring->adapter;
 643         int ena_qid;
 644
 645         ena_assert_msg(ring->configured,
 646                        "API violation - releasing not configured queue");
 647         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 648                        "API violation");
 649
 650         /* Destroy HW queue */
 651         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 652         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 653
 654         /* Free all bufs */
 655         ena_rx_queue_release_bufs(ring);
 656
 657         /* Free ring resources */
 658         if (ring->rx_buffer_info)
 659                 rte_free(ring->rx_buffer_info);
 660         ring->rx_buffer_info = NULL;
 661
 662         ring->configured = 0;
 663
 664         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 665                 ring->port_id, ring->id);
 666 }
 667
 668 static void ena_tx_queue_release(void *queue)
 669 {
 670         struct ena_ring *ring = (struct ena_ring *)queue;
 671         struct ena_adapter *adapter = ring->adapter;
 672         int ena_qid;
 673
 674         ena_assert_msg(ring->configured,
 675                        "API violation. Releasing not configured queue");
 676         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 677                        "API violation");
 678
 679         /* Destroy HW queue */
 680         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 681         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 682
 683         /* Free all bufs */
 684         ena_tx_queue_release_bufs(ring);
 685
 686         /* Free ring resources */
 687         if (ring->tx_buffer_info)
 688                 rte_free(ring->tx_buffer_info);
 689
 690         if (ring->empty_tx_reqs)
 691                 rte_free(ring->empty_tx_reqs);
 692
 693         ring->empty_tx_reqs = NULL;
 694         ring->tx_buffer_info = NULL;
 695
 696         ring->configured = 0;
 697
 698         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 699                 ring->port_id, ring->id);
 700 }
 701
 702 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 703 {
 704         unsigned int ring_mask = ring->ring_size - 1;
 705
 706         while (ring->next_to_clean != ring->next_to_use) {
 707                 struct rte_mbuf *m =
 708                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 709
 710                 if (m)
 711                         rte_mbuf_raw_free(m);
 712
 713                 ring->next_to_clean++;
 714         }
 715 }
 716
 717 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 718 {
 719         unsigned int i;
 720
 721         for (i = 0; i < ring->ring_size; ++i) {
 722                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 723
 724                 if (tx_buf->mbuf)
 725                         rte_pktmbuf_free(tx_buf->mbuf);
 726
 727                 ring->next_to_clean++;
 728         }
 729 }
 730
 731 static int ena_link_update(struct rte_eth_dev *dev,
 732                            __rte_unused int wait_to_complete)
 733 {
 734         struct rte_eth_link *link = &dev->data->dev_link;
 735
 736         link->link_status = ETH_LINK_UP;
 737         link->link_speed = ETH_SPEED_NUM_10G;
 738         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 739
 740         return 0;
 741 }
 742
 743 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 744                                  enum ena_ring_type ring_type)
 745 {
 746         struct ena_adapter *adapter =
 747                 (struct ena_adapter *)(dev->data->dev_private);
 748         struct ena_ring *queues = NULL;
 749         int i = 0;
 750         int rc = 0;
 751
 752         queues = (ring_type == ENA_RING_TYPE_RX) ?
 753                 adapter->rx_ring : adapter->tx_ring;
 754
 755         for (i = 0; i < adapter->num_queues; i++) {
 756                 if (queues[i].configured) {
 757                         if (ring_type == ENA_RING_TYPE_RX) {
 758                                 ena_assert_msg(
 759                                         dev->data->rx_queues[i] == &queues[i],
 760                                         "Inconsistent state of rx queues\n");
 761                         } else {
 762                                 ena_assert_msg(
 763                                         dev->data->tx_queues[i] == &queues[i],
 764                                         "Inconsistent state of tx queues\n");
 765                         }
 766
 767                         rc = ena_queue_restart(&queues[i]);
 768
 769                         if (rc) {
 770                                 PMD_INIT_LOG(ERR,
 771                                              "failed to restart queue %d type(%d)",
 772                                              i, ring_type);
 773                                 return -1;
 774                         }
 775                 }
 776         }
 777
 778         return 0;
 779 }
 780
 781 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 782 {
 783         uint32_t max_frame_len = adapter->max_mtu;
 784
 785         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 786             DEV_RX_OFFLOAD_JUMBO_FRAME)
 787                 max_frame_len =
 788                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 789
 790         return max_frame_len;
 791 }
 792
 793 static int ena_check_valid_conf(struct ena_adapter *adapter)
 794 {
 795         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 796
 797         if (max_frame_len > adapter->max_mtu) {
 798                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
 799                 return -1;
 800         }
 801
 802         return 0;
 803 }
 804
 805 static int
 806 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 807                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 808 {
 809         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 810
 811         queue_size = RTE_MIN(queue_size,
 812                              get_feat_ctx->max_queues.max_cq_depth);
 813         queue_size = RTE_MIN(queue_size,
 814                              get_feat_ctx->max_queues.max_sq_depth);
 815
 816         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 817                 queue_size = RTE_MIN(queue_size,
 818                                      get_feat_ctx->max_queues.max_llq_depth);
 819
 820         /* Round down to power of 2 */
 821         if (!rte_is_power_of_2(queue_size))
 822                 queue_size = rte_align32pow2(queue_size >> 1);
 823
 824         if (queue_size == 0) {
 825                 PMD_INIT_LOG(ERR, "Invalid queue size");
 826                 return -EFAULT;
 827         }
 828
 829         return queue_size;
 830 }
 831
 832 static void ena_stats_restart(struct rte_eth_dev *dev)
 833 {
 834         struct ena_adapter *adapter =
 835                 (struct ena_adapter *)(dev->data->dev_private);
 836
 837         rte_atomic64_init(&adapter->drv_stats->ierrors);
 838         rte_atomic64_init(&adapter->drv_stats->oerrors);
 839         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 840 }
 841
 842 static int ena_stats_get(struct rte_eth_dev *dev,
 843                           struct rte_eth_stats *stats)
 844 {
 845         struct ena_admin_basic_stats ena_stats;
 846         struct ena_adapter *adapter =
 847                 (struct ena_adapter *)(dev->data->dev_private);
 848         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 849         int rc;
 850
 851         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 852                 return -ENOTSUP;
 853
 854         memset(&ena_stats, 0, sizeof(ena_stats));
 855         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 856         if (unlikely(rc)) {
 857                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 858                 return rc;
 859         }
 860
 861         /* Set of basic statistics from ENA */
 862         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 863                                           ena_stats.rx_pkts_low);
 864         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 865                                           ena_stats.tx_pkts_low);
 866         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 867                                         ena_stats.rx_bytes_low);
 868         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 869                                         ena_stats.tx_bytes_low);
 870         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 871                                          ena_stats.rx_drops_low);
 872
 873         /* Driver related stats */
 874         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 875         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 876         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 877         return 0;
 878 }
 879
 880 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 881 {
 882         struct ena_adapter *adapter;
 883         struct ena_com_dev *ena_dev;
 884         int rc = 0;
 885
 886         ena_assert_msg(dev->data != NULL, "Uninitialized device");
 887         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
 888         adapter = (struct ena_adapter *)(dev->data->dev_private);
 889
 890         ena_dev = &adapter->ena_dev;
 891         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
 892
 893         if (mtu > ena_get_mtu_conf(adapter)) {
 894                 RTE_LOG(ERR, PMD,
 895                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
 896                         mtu, ena_get_mtu_conf(adapter));
 897                 rc = -EINVAL;
 898                 goto err;
 899         }
 900
 901         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 902         if (rc)
 903                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
 904         else
 905                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
 906
 907 err:
 908         return rc;
 909 }
 910
 911 static int ena_start(struct rte_eth_dev *dev)
 912 {
 913         struct ena_adapter *adapter =
 914                 (struct ena_adapter *)(dev->data->dev_private);
 915         int rc = 0;
 916
 917         rc = ena_check_valid_conf(adapter);
 918         if (rc)
 919                 return rc;
 920
 921         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
 922         if (rc)
 923                 return rc;
 924
 925         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
 926         if (rc)
 927                 return rc;
 928
 929         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
 930             ETH_MQ_RX_RSS_FLAG) {
 931                 rc = ena_rss_init_default(adapter);
 932                 if (rc)
 933                         return rc;
 934         }
 935
 936         ena_stats_restart(dev);
 937
 938         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 939
 940         return 0;
 941 }
 942
 943 static void ena_stop(struct rte_eth_dev *dev)
 944 {
 945         struct ena_adapter *adapter =
 946                 (struct ena_adapter *)(dev->data->dev_private);
 947
 948         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 949 }
 950
 951 static int ena_queue_restart(struct ena_ring *ring)
 952 {
 953         int rc, bufs_num;
 954
 955         ena_assert_msg(ring->configured == 1,
 956                        "Trying to restart unconfigured queue\n");
 957
 958         ring->next_to_clean = 0;
 959         ring->next_to_use = 0;
 960
 961         if (ring->type == ENA_RING_TYPE_TX)
 962                 return 0;
 963
 964         bufs_num = ring->ring_size - 1;
 965         rc = ena_populate_rx_queue(ring, bufs_num);
 966         if (rc != bufs_num) {
 967                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
 968                 return (-1);
 969         }
 970
 971         return 0;
 972 }
 973
 974 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
 975                               uint16_t queue_idx,
 976                               uint16_t nb_desc,
 977                               __rte_unused unsigned int socket_id,
 978                               const struct rte_eth_txconf *tx_conf)
 979 {
 980         struct ena_com_create_io_ctx ctx =
 981                 /* policy set to _HOST just to satisfy icc compiler */
 982                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
 983                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
 984         struct ena_ring *txq = NULL;
 985         struct ena_adapter *adapter =
 986                 (struct ena_adapter *)(dev->data->dev_private);
 987         unsigned int i;
 988         int ena_qid;
 989         int rc;
 990         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 991
 992         txq = &adapter->tx_ring[queue_idx];
 993
 994         if (txq->configured) {
 995                 RTE_LOG(CRIT, PMD,
 996                         "API violation. Queue %d is already configured\n",
 997                         queue_idx);
 998                 return -1;
 999         }
1000
1001         if (!rte_is_power_of_2(nb_desc)) {
1002                 RTE_LOG(ERR, PMD,
1003                         "Unsupported size of RX queue: %d is not a power of 2.",
1004                         nb_desc);
1005                 return -EINVAL;
1006         }
1007
1008         if (nb_desc > adapter->tx_ring_size) {
1009                 RTE_LOG(ERR, PMD,
1010                         "Unsupported size of TX queue (max size: %d)\n",
1011                         adapter->tx_ring_size);
1012                 return -EINVAL;
1013         }
1014
1015         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1016
1017         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1018         ctx.qid = ena_qid;
1019         ctx.msix_vector = -1; /* admin interrupts not used */
1020         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1021         ctx.queue_size = adapter->tx_ring_size;
1022         ctx.numa_node = ena_cpu_to_node(queue_idx);
1023
1024         rc = ena_com_create_io_queue(ena_dev, &ctx);
1025         if (rc) {
1026                 RTE_LOG(ERR, PMD,
1027                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1028                         queue_idx, ena_qid, rc);
1029         }
1030         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1031         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1032
1033         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1034                                      &txq->ena_com_io_sq,
1035                                      &txq->ena_com_io_cq);
1036         if (rc) {
1037                 RTE_LOG(ERR, PMD,
1038                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1039                         queue_idx, rc);
1040                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1041                 goto err;
1042         }
1043
1044         txq->port_id = dev->data->port_id;
1045         txq->next_to_clean = 0;
1046         txq->next_to_use = 0;
1047         txq->ring_size = nb_desc;
1048
1049         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1050                                           sizeof(struct ena_tx_buffer) *
1051                                           txq->ring_size,
1052                                           RTE_CACHE_LINE_SIZE);
1053         if (!txq->tx_buffer_info) {
1054                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1055                 return -ENOMEM;
1056         }
1057
1058         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1059                                          sizeof(u16) * txq->ring_size,
1060                                          RTE_CACHE_LINE_SIZE);
1061         if (!txq->empty_tx_reqs) {
1062                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1063                 rte_free(txq->tx_buffer_info);
1064                 return -ENOMEM;
1065         }
1066         for (i = 0; i < txq->ring_size; i++)
1067                 txq->empty_tx_reqs[i] = i;
1068
1069         txq->offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1070
1071         /* Store pointer to this queue in upper layer */
1072         txq->configured = 1;
1073         dev->data->tx_queues[queue_idx] = txq;
1074 err:
1075         return rc;
1076 }
1077
1078 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1079                               uint16_t queue_idx,
1080                               uint16_t nb_desc,
1081                               __rte_unused unsigned int socket_id,
1082                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1083                               struct rte_mempool *mp)
1084 {
1085         struct ena_com_create_io_ctx ctx =
1086                 /* policy set to _HOST just to satisfy icc compiler */
1087                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1088                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1089         struct ena_adapter *adapter =
1090                 (struct ena_adapter *)(dev->data->dev_private);
1091         struct ena_ring *rxq = NULL;
1092         uint16_t ena_qid = 0;
1093         int rc = 0;
1094         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1095
1096         rxq = &adapter->rx_ring[queue_idx];
1097         if (rxq->configured) {
1098                 RTE_LOG(CRIT, PMD,
1099                         "API violation. Queue %d is already configured\n",
1100                         queue_idx);
1101                 return -1;
1102         }
1103
1104         if (!rte_is_power_of_2(nb_desc)) {
1105                 RTE_LOG(ERR, PMD,
1106                         "Unsupported size of TX queue: %d is not a power of 2.",
1107                         nb_desc);
1108                 return -EINVAL;
1109         }
1110
1111         if (nb_desc > adapter->rx_ring_size) {
1112                 RTE_LOG(ERR, PMD,
1113                         "Unsupported size of RX queue (max size: %d)\n",
1114                         adapter->rx_ring_size);
1115                 return -EINVAL;
1116         }
1117
1118         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1119
1120         ctx.qid = ena_qid;
1121         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1122         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1123         ctx.msix_vector = -1; /* admin interrupts not used */
1124         ctx.queue_size = adapter->rx_ring_size;
1125         ctx.numa_node = ena_cpu_to_node(queue_idx);
1126
1127         rc = ena_com_create_io_queue(ena_dev, &ctx);
1128         if (rc)
1129                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1130                         queue_idx, rc);
1131
1132         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1133         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1134
1135         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1136                                      &rxq->ena_com_io_sq,
1137                                      &rxq->ena_com_io_cq);
1138         if (rc) {
1139                 RTE_LOG(ERR, PMD,
1140                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1141                         queue_idx, rc);
1142                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1143         }
1144
1145         rxq->port_id = dev->data->port_id;
1146         rxq->next_to_clean = 0;
1147         rxq->next_to_use = 0;
1148         rxq->ring_size = nb_desc;
1149         rxq->mb_pool = mp;
1150
1151         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1152                                           sizeof(struct rte_mbuf *) * nb_desc,
1153                                           RTE_CACHE_LINE_SIZE);
1154         if (!rxq->rx_buffer_info) {
1155                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1156                 return -ENOMEM;
1157         }
1158
1159         /* Store pointer to this queue in upper layer */
1160         rxq->configured = 1;
1161         dev->data->rx_queues[queue_idx] = rxq;
1162
1163         return rc;
1164 }
1165
1166 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1167 {
1168         unsigned int i;
1169         int rc;
1170         uint16_t ring_size = rxq->ring_size;
1171         uint16_t ring_mask = ring_size - 1;
1172         uint16_t next_to_use = rxq->next_to_use;
1173         uint16_t in_use;
1174         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1175
1176         if (unlikely(!count))
1177                 return 0;
1178
1179         in_use = rxq->next_to_use - rxq->next_to_clean;
1180         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1181
1182         count = RTE_MIN(count,
1183                         (uint16_t)(ring_size - (next_to_use & ring_mask)));
1184
1185         /* get resources for incoming packets */
1186         rc = rte_mempool_get_bulk(rxq->mb_pool,
1187                                   (void **)(&mbufs[next_to_use & ring_mask]),
1188                                   count);
1189         if (unlikely(rc < 0)) {
1190                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1191                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1192                 return 0;
1193         }
1194
1195         for (i = 0; i < count; i++) {
1196                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1197                 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1198                 struct ena_com_buf ebuf;
1199
1200                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1201                 /* prepare physical address for DMA transaction */
1202                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1203                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1204                 /* pass resource to device */
1205                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1206                                                 &ebuf, next_to_use_masked);
1207                 if (unlikely(rc)) {
1208                         rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1209                                              count - i);
1210                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1211                         break;
1212                 }
1213                 next_to_use++;
1214         }
1215
1216         /* When we submitted free recources to device... */
1217         if (i > 0) {
1218                 /* ...let HW know that it can fill buffers with data */
1219                 rte_wmb();
1220                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1221
1222                 rxq->next_to_use = next_to_use;
1223         }
1224
1225         return i;
1226 }
1227
1228 static int ena_device_init(struct ena_com_dev *ena_dev,
1229                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1230 {
1231         int rc;
1232         bool readless_supported;
1233
1234         /* Initialize mmio registers */
1235         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1236         if (rc) {
1237                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1238                 return rc;
1239         }
1240
1241         /* The PCIe configuration space revision id indicate if mmio reg
1242          * read is disabled.
1243          */
1244         readless_supported =
1245                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1246                                & ENA_MMIO_DISABLE_REG_READ);
1247         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1248
1249         /* reset device */
1250         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1251         if (rc) {
1252                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1253                 goto err_mmio_read_less;
1254         }
1255
1256         /* check FW version */
1257         rc = ena_com_validate_version(ena_dev);
1258         if (rc) {
1259                 RTE_LOG(ERR, PMD, "device version is too low\n");
1260                 goto err_mmio_read_less;
1261         }
1262
1263         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1264
1265         /* ENA device administration layer init */
1266         rc = ena_com_admin_init(ena_dev, &empty_aenq_handlers, true);
1267         if (rc) {
1268                 RTE_LOG(ERR, PMD,
1269                         "cannot initialize ena admin queue with device\n");
1270                 goto err_mmio_read_less;
1271         }
1272
1273         /* To enable the msix interrupts the driver needs to know the number
1274          * of queues. So the driver uses polling mode to retrieve this
1275          * information.
1276          */
1277         ena_com_set_admin_polling_mode(ena_dev, true);
1278
1279         ena_config_host_info(ena_dev);
1280
1281         /* Get Device Attributes and features */
1282         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1283         if (rc) {
1284                 RTE_LOG(ERR, PMD,
1285                         "cannot get attribute for ena device rc= %d\n", rc);
1286                 goto err_admin_init;
1287         }
1288
1289         return 0;
1290
1291 err_admin_init:
1292         ena_com_admin_destroy(ena_dev);
1293
1294 err_mmio_read_less:
1295         ena_com_mmio_reg_read_request_destroy(ena_dev);
1296
1297         return rc;
1298 }
1299
1300 static void ena_interrupt_handler_rte(__rte_unused void *cb_arg)
1301 {
1302         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1303         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1304
1305         ena_com_admin_q_comp_intr_handler(ena_dev);
1306 }
1307
1308 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1309 {
1310         struct rte_pci_device *pci_dev;
1311         struct rte_intr_handle *intr_handle;
1312         struct ena_adapter *adapter =
1313                 (struct ena_adapter *)(eth_dev->data->dev_private);
1314         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1315         struct ena_com_dev_get_features_ctx get_feat_ctx;
1316         int queue_size, rc;
1317
1318         static int adapters_found;
1319
1320         memset(adapter, 0, sizeof(struct ena_adapter));
1321         ena_dev = &adapter->ena_dev;
1322
1323         eth_dev->dev_ops = &ena_dev_ops;
1324         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1325         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1326         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1327         adapter->rte_eth_dev_data = eth_dev->data;
1328         adapter->rte_dev = eth_dev;
1329
1330         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1331                 return 0;
1332
1333         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1334         adapter->pdev = pci_dev;
1335
1336         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1337                      pci_dev->addr.domain,
1338                      pci_dev->addr.bus,
1339                      pci_dev->addr.devid,
1340                      pci_dev->addr.function);
1341
1342         intr_handle = &pci_dev->intr_handle;
1343
1344         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1345         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1346
1347         if (!adapter->regs) {
1348                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1349                              ENA_REGS_BAR);
1350                 return -ENXIO;
1351         }
1352
1353         ena_dev->reg_bar = adapter->regs;
1354         ena_dev->dmadev = adapter->pdev;
1355
1356         adapter->id_number = adapters_found;
1357
1358         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1359                  adapter->id_number);
1360
1361         /* device specific initialization routine */
1362         rc = ena_device_init(ena_dev, &get_feat_ctx);
1363         if (rc) {
1364                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1365                 return -1;
1366         }
1367
1368         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1369         adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1370
1371         queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1372         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1373                 return -EFAULT;
1374
1375         adapter->tx_ring_size = queue_size;
1376         adapter->rx_ring_size = queue_size;
1377
1378         /* prepare ring structures */
1379         ena_init_rings(adapter);
1380
1381         ena_config_debug_area(adapter);
1382
1383         /* Set max MTU for this device */
1384         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1385
1386         /* set device support for TSO */
1387         adapter->tso4_supported = get_feat_ctx.offload.tx &
1388                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1389
1390         /* Copy MAC address and point DPDK to it */
1391         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1392         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1393                         (struct ether_addr *)adapter->mac_addr);
1394
1395         adapter->drv_stats = rte_zmalloc("adapter stats",
1396                                          sizeof(*adapter->drv_stats),
1397                                          RTE_CACHE_LINE_SIZE);
1398         if (!adapter->drv_stats) {
1399                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1400                 return -ENOMEM;
1401         }
1402
1403         rte_intr_callback_register(intr_handle,
1404                                    ena_interrupt_handler_rte,
1405                                    adapter);
1406         rte_intr_enable(intr_handle);
1407         ena_com_set_admin_polling_mode(ena_dev, false);
1408
1409         adapters_found++;
1410         adapter->state = ENA_ADAPTER_STATE_INIT;
1411
1412         return 0;
1413 }
1414
1415 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1416 {
1417         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1418         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1419         struct ena_adapter *adapter =
1420                 (struct ena_adapter *)(eth_dev->data->dev_private);
1421
1422         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1423                 return -EPERM;
1424
1425         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1426                 ena_close(eth_dev);
1427
1428         eth_dev->dev_ops = NULL;
1429         eth_dev->rx_pkt_burst = NULL;
1430         eth_dev->tx_pkt_burst = NULL;
1431         eth_dev->tx_pkt_prepare = NULL;
1432
1433         rte_free(adapter->drv_stats);
1434         adapter->drv_stats = NULL;
1435
1436         rte_intr_disable(intr_handle);
1437         rte_intr_callback_unregister(intr_handle,
1438                                      ena_interrupt_handler_rte,
1439                                      adapter);
1440
1441         adapter->state = ENA_ADAPTER_STATE_FREE;
1442
1443         return 0;
1444 }
1445
1446 static int ena_dev_configure(struct rte_eth_dev *dev)
1447 {
1448         struct ena_adapter *adapter =
1449                 (struct ena_adapter *)(dev->data->dev_private);
1450
1451         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1452
1453         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1454         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1455         return 0;
1456 }
1457
1458 static void ena_init_rings(struct ena_adapter *adapter)
1459 {
1460         int i;
1461
1462         for (i = 0; i < adapter->num_queues; i++) {
1463                 struct ena_ring *ring = &adapter->tx_ring[i];
1464
1465                 ring->configured = 0;
1466                 ring->type = ENA_RING_TYPE_TX;
1467                 ring->adapter = adapter;
1468                 ring->id = i;
1469                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1470                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1471         }
1472
1473         for (i = 0; i < adapter->num_queues; i++) {
1474                 struct ena_ring *ring = &adapter->rx_ring[i];
1475
1476                 ring->configured = 0;
1477                 ring->type = ENA_RING_TYPE_RX;
1478                 ring->adapter = adapter;
1479                 ring->id = i;
1480         }
1481 }
1482
1483 static void ena_infos_get(struct rte_eth_dev *dev,
1484                           struct rte_eth_dev_info *dev_info)
1485 {
1486         struct ena_adapter *adapter;
1487         struct ena_com_dev *ena_dev;
1488         struct ena_com_dev_get_features_ctx feat;
1489         uint64_t rx_feat = 0, tx_feat = 0;
1490         int rc = 0;
1491
1492         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1493         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1494         adapter = (struct ena_adapter *)(dev->data->dev_private);
1495
1496         ena_dev = &adapter->ena_dev;
1497         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1498
1499         dev_info->speed_capa =
1500                         ETH_LINK_SPEED_1G   |
1501                         ETH_LINK_SPEED_2_5G |
1502                         ETH_LINK_SPEED_5G   |
1503                         ETH_LINK_SPEED_10G  |
1504                         ETH_LINK_SPEED_25G  |
1505                         ETH_LINK_SPEED_40G  |
1506                         ETH_LINK_SPEED_50G  |
1507                         ETH_LINK_SPEED_100G;
1508
1509         /* Get supported features from HW */
1510         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1511         if (unlikely(rc)) {
1512                 RTE_LOG(ERR, PMD,
1513                         "Cannot get attribute for ena device rc= %d\n", rc);
1514                 return;
1515         }
1516
1517         /* Set Tx & Rx features available for device */
1518         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1519                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1520
1521         if (feat.offload.tx &
1522             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1523                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1524                         DEV_TX_OFFLOAD_UDP_CKSUM |
1525                         DEV_TX_OFFLOAD_TCP_CKSUM;
1526
1527         if (feat.offload.rx_supported &
1528             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1529                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1530                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1531                         DEV_RX_OFFLOAD_TCP_CKSUM;
1532
1533         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1534
1535         /* Inform framework about available features */
1536         dev_info->rx_offload_capa = rx_feat;
1537         dev_info->rx_queue_offload_capa = rx_feat;
1538         dev_info->tx_offload_capa = tx_feat;
1539         dev_info->tx_queue_offload_capa = tx_feat;
1540
1541         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1542         dev_info->max_rx_pktlen  = adapter->max_mtu;
1543         dev_info->max_mac_addrs = 1;
1544
1545         dev_info->max_rx_queues = adapter->num_queues;
1546         dev_info->max_tx_queues = adapter->num_queues;
1547         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1548
1549         adapter->tx_supported_offloads = tx_feat;
1550         adapter->rx_supported_offloads = rx_feat;
1551 }
1552
1553 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1554                                   uint16_t nb_pkts)
1555 {
1556         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1557         unsigned int ring_size = rx_ring->ring_size;
1558         unsigned int ring_mask = ring_size - 1;
1559         uint16_t next_to_clean = rx_ring->next_to_clean;
1560         uint16_t desc_in_use = 0;
1561         unsigned int recv_idx = 0;
1562         struct rte_mbuf *mbuf = NULL;
1563         struct rte_mbuf *mbuf_head = NULL;
1564         struct rte_mbuf *mbuf_prev = NULL;
1565         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1566         unsigned int completed;
1567
1568         struct ena_com_rx_ctx ena_rx_ctx;
1569         int rc = 0;
1570
1571         /* Check adapter state */
1572         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1573                 RTE_LOG(ALERT, PMD,
1574                         "Trying to receive pkts while device is NOT running\n");
1575                 return 0;
1576         }
1577
1578         desc_in_use = rx_ring->next_to_use - next_to_clean;
1579         if (unlikely(nb_pkts > desc_in_use))
1580                 nb_pkts = desc_in_use;
1581
1582         for (completed = 0; completed < nb_pkts; completed++) {
1583                 int segments = 0;
1584
1585                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1586                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1587                 ena_rx_ctx.descs = 0;
1588                 /* receive packet context */
1589                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1590                                     rx_ring->ena_com_io_sq,
1591                                     &ena_rx_ctx);
1592                 if (unlikely(rc)) {
1593                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1594                         return 0;
1595                 }
1596
1597                 if (unlikely(ena_rx_ctx.descs == 0))
1598                         break;
1599
1600                 while (segments < ena_rx_ctx.descs) {
1601                         mbuf = rx_buff_info[next_to_clean & ring_mask];
1602                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1603                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1604                         mbuf->refcnt = 1;
1605                         mbuf->next = NULL;
1606                         if (segments == 0) {
1607                                 mbuf->nb_segs = ena_rx_ctx.descs;
1608                                 mbuf->port = rx_ring->port_id;
1609                                 mbuf->pkt_len = 0;
1610                                 mbuf_head = mbuf;
1611                         } else {
1612                                 /* for multi-segment pkts create mbuf chain */
1613                                 mbuf_prev->next = mbuf;
1614                         }
1615                         mbuf_head->pkt_len += mbuf->data_len;
1616
1617                         mbuf_prev = mbuf;
1618                         segments++;
1619                         next_to_clean++;
1620                 }
1621
1622                 /* fill mbuf attributes if any */
1623                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1624                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1625
1626                 /* pass to DPDK application head mbuf */
1627                 rx_pkts[recv_idx] = mbuf_head;
1628                 recv_idx++;
1629         }
1630
1631         rx_ring->next_to_clean = next_to_clean;
1632
1633         desc_in_use = desc_in_use - completed + 1;
1634         /* Burst refill to save doorbells, memory barriers, const interval */
1635         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1636                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1637
1638         return recv_idx;
1639 }
1640
1641 static uint16_t
1642 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1643                 uint16_t nb_pkts)
1644 {
1645         int32_t ret;
1646         uint32_t i;
1647         struct rte_mbuf *m;
1648         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1649         struct ipv4_hdr *ip_hdr;
1650         uint64_t ol_flags;
1651         uint16_t frag_field;
1652
1653         for (i = 0; i != nb_pkts; i++) {
1654                 m = tx_pkts[i];
1655                 ol_flags = m->ol_flags;
1656
1657                 if (!(ol_flags & PKT_TX_IPV4))
1658                         continue;
1659
1660                 /* If there was not L2 header length specified, assume it is
1661                  * length of the ethernet header.
1662                  */
1663                 if (unlikely(m->l2_len == 0))
1664                         m->l2_len = sizeof(struct ether_hdr);
1665
1666                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1667                                                  m->l2_len);
1668                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1669
1670                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1671                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1672
1673                         /* If IPv4 header has DF flag enabled and TSO support is
1674                          * disabled, partial chcecksum should not be calculated.
1675                          */
1676                         if (!tx_ring->adapter->tso4_supported)
1677                                 continue;
1678                 }
1679
1680                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1681                                 (ol_flags & PKT_TX_L4_MASK) ==
1682                                 PKT_TX_SCTP_CKSUM) {
1683                         rte_errno = -ENOTSUP;
1684                         return i;
1685                 }
1686
1687 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1688                 ret = rte_validate_tx_offload(m);
1689                 if (ret != 0) {
1690                         rte_errno = ret;
1691                         return i;
1692                 }
1693 #endif
1694
1695                 /* In case we are supposed to TSO and have DF not set (DF=0)
1696                  * hardware must be provided with partial checksum, otherwise
1697                  * it will take care of necessary calculations.
1698                  */
1699
1700                 ret = rte_net_intel_cksum_flags_prepare(m,
1701                         ol_flags & ~PKT_TX_TCP_SEG);
1702                 if (ret != 0) {
1703                         rte_errno = ret;
1704                         return i;
1705                 }
1706         }
1707
1708         return i;
1709 }
1710
1711 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1712                                   uint16_t nb_pkts)
1713 {
1714         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1715         uint16_t next_to_use = tx_ring->next_to_use;
1716         uint16_t next_to_clean = tx_ring->next_to_clean;
1717         struct rte_mbuf *mbuf;
1718         unsigned int ring_size = tx_ring->ring_size;
1719         unsigned int ring_mask = ring_size - 1;
1720         struct ena_com_tx_ctx ena_tx_ctx;
1721         struct ena_tx_buffer *tx_info;
1722         struct ena_com_buf *ebuf;
1723         uint16_t rc, req_id, total_tx_descs = 0;
1724         uint16_t sent_idx = 0, empty_tx_reqs;
1725         int nb_hw_desc;
1726
1727         /* Check adapter state */
1728         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1729                 RTE_LOG(ALERT, PMD,
1730                         "Trying to xmit pkts while device is NOT running\n");
1731                 return 0;
1732         }
1733
1734         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1735         if (nb_pkts > empty_tx_reqs)
1736                 nb_pkts = empty_tx_reqs;
1737
1738         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1739                 mbuf = tx_pkts[sent_idx];
1740
1741                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1742                 tx_info = &tx_ring->tx_buffer_info[req_id];
1743                 tx_info->mbuf = mbuf;
1744                 tx_info->num_of_bufs = 0;
1745                 ebuf = tx_info->bufs;
1746
1747                 /* Prepare TX context */
1748                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1749                 memset(&ena_tx_ctx.ena_meta, 0x0,
1750                        sizeof(struct ena_com_tx_meta));
1751                 ena_tx_ctx.ena_bufs = ebuf;
1752                 ena_tx_ctx.req_id = req_id;
1753                 if (tx_ring->tx_mem_queue_type ==
1754                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1755                         /* prepare the push buffer with
1756                          * virtual address of the data
1757                          */
1758                         ena_tx_ctx.header_len =
1759                                 RTE_MIN(mbuf->data_len,
1760                                         tx_ring->tx_max_header_size);
1761                         ena_tx_ctx.push_header =
1762                                 (void *)((char *)mbuf->buf_addr +
1763                                          mbuf->data_off);
1764                 } /* there's no else as we take advantage of memset zeroing */
1765
1766                 /* Set TX offloads flags, if applicable */
1767                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
1768
1769                 if (unlikely(mbuf->ol_flags &
1770                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1771                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1772
1773                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1774
1775                 /* Process first segment taking into
1776                  * consideration pushed header
1777                  */
1778                 if (mbuf->data_len > ena_tx_ctx.header_len) {
1779                         ebuf->paddr = mbuf->buf_iova +
1780                                       mbuf->data_off +
1781                                       ena_tx_ctx.header_len;
1782                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1783                         ebuf++;
1784                         tx_info->num_of_bufs++;
1785                 }
1786
1787                 while ((mbuf = mbuf->next) != NULL) {
1788                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
1789                         ebuf->len = mbuf->data_len;
1790                         ebuf++;
1791                         tx_info->num_of_bufs++;
1792                 }
1793
1794                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1795
1796                 /* Write data to device */
1797                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1798                                         &ena_tx_ctx, &nb_hw_desc);
1799                 if (unlikely(rc))
1800                         break;
1801
1802                 tx_info->tx_descs = nb_hw_desc;
1803
1804                 next_to_use++;
1805         }
1806
1807         /* If there are ready packets to be xmitted... */
1808         if (sent_idx > 0) {
1809                 /* ...let HW do its best :-) */
1810                 rte_wmb();
1811                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1812
1813                 tx_ring->next_to_use = next_to_use;
1814         }
1815
1816         /* Clear complete packets  */
1817         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1818                 /* Get Tx info & store how many descs were processed  */
1819                 tx_info = &tx_ring->tx_buffer_info[req_id];
1820                 total_tx_descs += tx_info->tx_descs;
1821
1822                 /* Free whole mbuf chain  */
1823                 mbuf = tx_info->mbuf;
1824                 rte_pktmbuf_free(mbuf);
1825                 tx_info->mbuf = NULL;
1826
1827                 /* Put back descriptor to the ring for reuse */
1828                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
1829                 next_to_clean++;
1830
1831                 /* If too many descs to clean, leave it for another run */
1832                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1833                         break;
1834         }
1835
1836         if (total_tx_descs > 0) {
1837                 /* acknowledge completion of sent packets */
1838                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1839                 tx_ring->next_to_clean = next_to_clean;
1840         }
1841
1842         return sent_idx;
1843 }
1844
1845 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1846         struct rte_pci_device *pci_dev)
1847 {
1848         return rte_eth_dev_pci_generic_probe(pci_dev,
1849                 sizeof(struct ena_adapter), eth_ena_dev_init);
1850 }
1851
1852 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
1853 {
1854         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
1855 }
1856
1857 static struct rte_pci_driver rte_ena_pmd = {
1858         .id_table = pci_id_ena_map,
1859         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1860         .probe = eth_ena_pci_probe,
1861         .remove = eth_ena_pci_remove,
1862 };
1863
1864 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
1865 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
1866 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
1867
1868 RTE_INIT(ena_init_log);
1869 static void
1870 ena_init_log(void)
1871 {
1872         ena_logtype_init = rte_log_register("pmd.net.ena.init");
1873         if (ena_logtype_init >= 0)
1874                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
1875         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
1876         if (ena_logtype_driver >= 0)
1877                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
1878 }
1879
1880 /******************************************************************************
1881  ******************************** AENQ Handlers *******************************
1882  *****************************************************************************/
1883 /**
1884  * This handler will called for unknown event group or unimplemented handlers
1885  **/
1886 static void unimplemented_aenq_handler(__rte_unused void *data,
1887                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
1888 {
1889         // Unimplemented handler
1890 }
1891
1892 static struct ena_aenq_handlers empty_aenq_handlers = {
1893         .handlers = {
1894                 [ENA_ADMIN_LINK_CHANGE] = unimplemented_aenq_handler,
1895                 [ENA_ADMIN_NOTIFICATION] = unimplemented_aenq_handler,
1896                 [ENA_ADMIN_KEEP_ALIVE] = unimplemented_aenq_handler
1897         },
1898         .unimplemented_handler = unimplemented_aenq_handler
1899 };