drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 1
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 #define ENA_MIN_RING_DESC       128
  89
  90 enum ethtool_stringset {
  91         ETH_SS_TEST             = 0,
  92         ETH_SS_STATS,
  93 };
  94
  95 struct ena_stats {
  96         char name[ETH_GSTRING_LEN];
  97         int stat_offset;
  98 };
  99
 100 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
 101         .name = #stat, \
 102         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 103 }
 104
 105 #define ENA_STAT_ENTRY(stat, stat_type) { \
 106         .name = #stat, \
 107         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 108 }
 109
 110 #define ENA_STAT_RX_ENTRY(stat) \
 111         ENA_STAT_ENTRY(stat, rx)
 112
 113 #define ENA_STAT_TX_ENTRY(stat) \
 114         ENA_STAT_ENTRY(stat, tx)
 115
 116 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 117         ENA_STAT_ENTRY(stat, dev)
 118
 119 #define ENA_MAX_RING_SIZE_RX 1024
 120 #define ENA_MAX_RING_SIZE_TX 1024
 121
 122 /*
 123  * Each rte_memzone should have unique name.
 124  * To satisfy it, count number of allocation and add it to name.
 125  */
 126 uint32_t ena_alloc_cnt;
 127
 128 static const struct ena_stats ena_stats_global_strings[] = {
 129         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 130         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 131         ENA_STAT_GLOBAL_ENTRY(io_resume),
 132         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 133         ENA_STAT_GLOBAL_ENTRY(interface_up),
 134         ENA_STAT_GLOBAL_ENTRY(interface_down),
 135         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 136 };
 137
 138 static const struct ena_stats ena_stats_tx_strings[] = {
 139         ENA_STAT_TX_ENTRY(cnt),
 140         ENA_STAT_TX_ENTRY(bytes),
 141         ENA_STAT_TX_ENTRY(queue_stop),
 142         ENA_STAT_TX_ENTRY(queue_wakeup),
 143         ENA_STAT_TX_ENTRY(dma_mapping_err),
 144         ENA_STAT_TX_ENTRY(linearize),
 145         ENA_STAT_TX_ENTRY(linearize_failed),
 146         ENA_STAT_TX_ENTRY(tx_poll),
 147         ENA_STAT_TX_ENTRY(doorbells),
 148         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 149         ENA_STAT_TX_ENTRY(missing_tx_comp),
 150         ENA_STAT_TX_ENTRY(bad_req_id),
 151 };
 152
 153 static const struct ena_stats ena_stats_rx_strings[] = {
 154         ENA_STAT_RX_ENTRY(cnt),
 155         ENA_STAT_RX_ENTRY(bytes),
 156         ENA_STAT_RX_ENTRY(refil_partial),
 157         ENA_STAT_RX_ENTRY(bad_csum),
 158         ENA_STAT_RX_ENTRY(page_alloc_fail),
 159         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 160         ENA_STAT_RX_ENTRY(dma_mapping_err),
 161         ENA_STAT_RX_ENTRY(bad_desc_num),
 162         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 163 };
 164
 165 static const struct ena_stats ena_stats_ena_com_strings[] = {
 166         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 167         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 168         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 169         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 170         ENA_STAT_ENA_COM_ENTRY(no_completion),
 171 };
 172
 173 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 174 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 175 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 176 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 177
 178 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 179                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 180                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 181                         DEV_TX_OFFLOAD_TCP_TSO)
 182 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 183                        PKT_TX_IP_CKSUM |\
 184                        PKT_TX_TCP_SEG)
 185
 186 /** Vendor ID used by Amazon devices */
 187 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 188 /** Amazon devices */
 189 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 190 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 191
 192 #define ENA_TX_OFFLOAD_MASK     (\
 193         PKT_TX_L4_MASK |         \
 194         PKT_TX_IPV6 |            \
 195         PKT_TX_IPV4 |            \
 196         PKT_TX_IP_CKSUM |        \
 197         PKT_TX_TCP_SEG)
 198
 199 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 200         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 201
 202 int ena_logtype_init;
 203 int ena_logtype_driver;
 204
 205 static const struct rte_pci_id pci_id_ena_map[] = {
 206         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 207         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 208         { .device_id = 0 },
 209 };
 210
 211 static struct ena_aenq_handlers aenq_handlers;
 212
 213 static int ena_device_init(struct ena_com_dev *ena_dev,
 214                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 215                            bool *wd_state);
 216 static int ena_dev_configure(struct rte_eth_dev *dev);
 217 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 218                                   uint16_t nb_pkts);
 219 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 220                 uint16_t nb_pkts);
 221 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 222                               uint16_t nb_desc, unsigned int socket_id,
 223                               const struct rte_eth_txconf *tx_conf);
 224 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 225                               uint16_t nb_desc, unsigned int socket_id,
 226                               const struct rte_eth_rxconf *rx_conf,
 227                               struct rte_mempool *mp);
 228 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 229                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 230 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 231 static void ena_init_rings(struct ena_adapter *adapter);
 232 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 233 static int ena_start(struct rte_eth_dev *dev);
 234 static void ena_stop(struct rte_eth_dev *dev);
 235 static void ena_close(struct rte_eth_dev *dev);
 236 static int ena_dev_reset(struct rte_eth_dev *dev);
 237 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 238 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 239 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 240 static void ena_rx_queue_release(void *queue);
 241 static void ena_tx_queue_release(void *queue);
 242 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 243 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 244 static int ena_link_update(struct rte_eth_dev *dev,
 245                            int wait_to_complete);
 246 static int ena_create_io_queue(struct ena_ring *ring);
 247 static void ena_free_io_queues_all(struct ena_adapter *adapter);
 248 static int ena_queue_restart(struct ena_ring *ring);
 249 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 250                                  enum ena_ring_type ring_type);
 251 static void ena_stats_restart(struct rte_eth_dev *dev);
 252 static void ena_infos_get(struct rte_eth_dev *dev,
 253                           struct rte_eth_dev_info *dev_info);
 254 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 255                                struct rte_eth_rss_reta_entry64 *reta_conf,
 256                                uint16_t reta_size);
 257 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 258                               struct rte_eth_rss_reta_entry64 *reta_conf,
 259                               uint16_t reta_size);
 260 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 261 static void ena_interrupt_handler_rte(void *cb_arg);
 262 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 263
 264 static const struct eth_dev_ops ena_dev_ops = {
 265         .dev_configure        = ena_dev_configure,
 266         .dev_infos_get        = ena_infos_get,
 267         .rx_queue_setup       = ena_rx_queue_setup,
 268         .tx_queue_setup       = ena_tx_queue_setup,
 269         .dev_start            = ena_start,
 270         .dev_stop             = ena_stop,
 271         .link_update          = ena_link_update,
 272         .stats_get            = ena_stats_get,
 273         .mtu_set              = ena_mtu_set,
 274         .rx_queue_release     = ena_rx_queue_release,
 275         .tx_queue_release     = ena_tx_queue_release,
 276         .dev_close            = ena_close,
 277         .dev_reset            = ena_dev_reset,
 278         .reta_update          = ena_rss_reta_update,
 279         .reta_query           = ena_rss_reta_query,
 280 };
 281
 282 #define NUMA_NO_NODE    SOCKET_ID_ANY
 283
 284 static inline int ena_cpu_to_node(int cpu)
 285 {
 286         struct rte_config *config = rte_eal_get_configuration();
 287         struct rte_fbarray *arr = &config->mem_config->memzones;
 288         const struct rte_memzone *mz;
 289
 290         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 291                 return NUMA_NO_NODE;
 292
 293         mz = rte_fbarray_get(arr, cpu);
 294
 295         return mz->socket_id;
 296 }
 297
 298 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 299                                        struct ena_com_rx_ctx *ena_rx_ctx)
 300 {
 301         uint64_t ol_flags = 0;
 302         uint32_t packet_type = 0;
 303
 304         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 305                 packet_type |= RTE_PTYPE_L4_TCP;
 306         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 307                 packet_type |= RTE_PTYPE_L4_UDP;
 308
 309         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 310                 packet_type |= RTE_PTYPE_L3_IPV4;
 311         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 312                 packet_type |= RTE_PTYPE_L3_IPV6;
 313
 314         if (unlikely(ena_rx_ctx->l4_csum_err))
 315                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 316         if (unlikely(ena_rx_ctx->l3_csum_err))
 317                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 318
 319         mbuf->ol_flags = ol_flags;
 320         mbuf->packet_type = packet_type;
 321 }
 322
 323 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 324                                        struct ena_com_tx_ctx *ena_tx_ctx,
 325                                        uint64_t queue_offloads)
 326 {
 327         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 328
 329         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 330             (queue_offloads & QUEUE_OFFLOADS)) {
 331                 /* check if TSO is required */
 332                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 333                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 334                         ena_tx_ctx->tso_enable = true;
 335
 336                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 337                 }
 338
 339                 /* check if L3 checksum is needed */
 340                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 341                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 342                         ena_tx_ctx->l3_csum_enable = true;
 343
 344                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 345                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 346                 } else {
 347                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 348
 349                         /* set don't fragment (DF) flag */
 350                         if (mbuf->packet_type &
 351                                 (RTE_PTYPE_L4_NONFRAG
 352                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 353                                 ena_tx_ctx->df = true;
 354                 }
 355
 356                 /* check if L4 checksum is needed */
 357                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 358                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 359                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 360                         ena_tx_ctx->l4_csum_enable = true;
 361                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 362                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 363                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 364                         ena_tx_ctx->l4_csum_enable = true;
 365                 } else {
 366                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 367                         ena_tx_ctx->l4_csum_enable = false;
 368                 }
 369
 370                 ena_meta->mss = mbuf->tso_segsz;
 371                 ena_meta->l3_hdr_len = mbuf->l3_len;
 372                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 373
 374                 ena_tx_ctx->meta_valid = true;
 375         } else {
 376                 ena_tx_ctx->meta_valid = false;
 377         }
 378 }
 379
 380 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 381 {
 382         if (likely(req_id < rx_ring->ring_size))
 383                 return 0;
 384
 385         RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
 386
 387         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 388         rx_ring->adapter->trigger_reset = true;
 389
 390         return -EFAULT;
 391 }
 392
 393 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 394 {
 395         struct ena_tx_buffer *tx_info = NULL;
 396
 397         if (likely(req_id < tx_ring->ring_size)) {
 398                 tx_info = &tx_ring->tx_buffer_info[req_id];
 399                 if (likely(tx_info->mbuf))
 400                         return 0;
 401         }
 402
 403         if (tx_info)
 404                 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n");
 405         else
 406                 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id);
 407
 408         /* Trigger device reset */
 409         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 410         tx_ring->adapter->trigger_reset = true;
 411         return -EFAULT;
 412 }
 413
 414 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 415 {
 416         struct ena_admin_host_info *host_info;
 417         int rc;
 418
 419         /* Allocate only the host info */
 420         rc = ena_com_allocate_host_info(ena_dev);
 421         if (rc) {
 422                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 423                 return;
 424         }
 425
 426         host_info = ena_dev->host_attr.host_info;
 427
 428         host_info->os_type = ENA_ADMIN_OS_DPDK;
 429         host_info->kernel_ver = RTE_VERSION;
 430         snprintf((char *)host_info->kernel_ver_str,
 431                  sizeof(host_info->kernel_ver_str),
 432                  "%s", rte_version());
 433         host_info->os_dist = RTE_VERSION;
 434         snprintf((char *)host_info->os_dist_str,
 435                  sizeof(host_info->os_dist_str),
 436                  "%s", rte_version());
 437         host_info->driver_version =
 438                 (DRV_MODULE_VER_MAJOR) |
 439                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 440                 (DRV_MODULE_VER_SUBMINOR <<
 441                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 442         host_info->num_cpus = rte_lcore_count();
 443
 444         rc = ena_com_set_host_attributes(ena_dev);
 445         if (rc) {
 446                 if (rc == -ENA_COM_UNSUPPORTED)
 447                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 448                 else
 449                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 450
 451                 goto err;
 452         }
 453
 454         return;
 455
 456 err:
 457         ena_com_delete_host_info(ena_dev);
 458 }
 459
 460 static int
 461 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 462 {
 463         if (sset != ETH_SS_STATS)
 464                 return -EOPNOTSUPP;
 465
 466          /* Workaround for clang:
 467          * touch internal structures to prevent
 468          * compiler error
 469          */
 470         ENA_TOUCH(ena_stats_global_strings);
 471         ENA_TOUCH(ena_stats_tx_strings);
 472         ENA_TOUCH(ena_stats_rx_strings);
 473         ENA_TOUCH(ena_stats_ena_com_strings);
 474
 475         return  dev->data->nb_tx_queues *
 476                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 477                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 478 }
 479
 480 static void ena_config_debug_area(struct ena_adapter *adapter)
 481 {
 482         u32 debug_area_size;
 483         int rc, ss_count;
 484
 485         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 486         if (ss_count <= 0) {
 487                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 488                 return;
 489         }
 490
 491         /* allocate 32 bytes for each string and 64bit for the value */
 492         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 493
 494         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 495         if (rc) {
 496                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 497                 return;
 498         }
 499
 500         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 501         if (rc) {
 502                 if (rc == -ENA_COM_UNSUPPORTED)
 503                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 504                 else
 505                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 506
 507                 goto err;
 508         }
 509
 510         return;
 511 err:
 512         ena_com_delete_debug_area(&adapter->ena_dev);
 513 }
 514
 515 static void ena_close(struct rte_eth_dev *dev)
 516 {
 517         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 518         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 519         struct ena_adapter *adapter =
 520                 (struct ena_adapter *)(dev->data->dev_private);
 521
 522         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 523                 ena_stop(dev);
 524         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 525
 526         ena_rx_queue_release_all(dev);
 527         ena_tx_queue_release_all(dev);
 528
 529         rte_free(adapter->drv_stats);
 530         adapter->drv_stats = NULL;
 531
 532         rte_intr_disable(intr_handle);
 533         rte_intr_callback_unregister(intr_handle,
 534                                      ena_interrupt_handler_rte,
 535                                      adapter);
 536
 537         /*
 538          * MAC is not allocated dynamically. Setting NULL should prevent from
 539          * release of the resource in the rte_eth_dev_release_port().
 540          */
 541         dev->data->mac_addrs = NULL;
 542 }
 543
 544 static int
 545 ena_dev_reset(struct rte_eth_dev *dev)
 546 {
 547         struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
 548         struct rte_eth_dev *eth_dev;
 549         struct rte_pci_device *pci_dev;
 550         struct rte_intr_handle *intr_handle;
 551         struct ena_com_dev *ena_dev;
 552         struct ena_com_dev_get_features_ctx get_feat_ctx;
 553         struct ena_adapter *adapter;
 554         int nb_queues;
 555         int rc, i;
 556         bool wd_state;
 557
 558         adapter = (struct ena_adapter *)(dev->data->dev_private);
 559         ena_dev = &adapter->ena_dev;
 560         eth_dev = adapter->rte_dev;
 561         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 562         intr_handle = &pci_dev->intr_handle;
 563         nb_queues = eth_dev->data->nb_rx_queues;
 564
 565         ena_com_set_admin_running_state(ena_dev, false);
 566
 567         rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
 568         if (rc)
 569                 RTE_LOG(ERR, PMD, "Device reset failed\n");
 570
 571         for (i = 0; i < nb_queues; i++)
 572                 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
 573
 574         ena_rx_queue_release_all(eth_dev);
 575         ena_tx_queue_release_all(eth_dev);
 576
 577         rte_intr_disable(intr_handle);
 578
 579         ena_com_abort_admin_commands(ena_dev);
 580         ena_com_wait_for_abort_completion(ena_dev);
 581         ena_com_admin_destroy(ena_dev);
 582         ena_com_mmio_reg_read_request_destroy(ena_dev);
 583
 584         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
 585         if (rc) {
 586                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 587                 return rc;
 588         }
 589         adapter->wd_state = wd_state;
 590
 591         rte_intr_enable(intr_handle);
 592         ena_com_set_admin_polling_mode(ena_dev, false);
 593         ena_com_admin_aenq_enable(ena_dev);
 594
 595         for (i = 0; i < nb_queues; ++i)
 596                 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring[i].ring_size, 0,
 597                         NULL, mb_pool_rx[i]);
 598
 599         for (i = 0; i < nb_queues; ++i)
 600                 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring[i].ring_size, 0,
 601                         NULL);
 602
 603         adapter->trigger_reset = false;
 604
 605         return 0;
 606 }
 607
 608 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 609                                struct rte_eth_rss_reta_entry64 *reta_conf,
 610                                uint16_t reta_size)
 611 {
 612         struct ena_adapter *adapter =
 613                 (struct ena_adapter *)(dev->data->dev_private);
 614         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 615         int rc, i;
 616         u16 entry_value;
 617         int conf_idx;
 618         int idx;
 619
 620         if ((reta_size == 0) || (reta_conf == NULL))
 621                 return -EINVAL;
 622
 623         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 624                 RTE_LOG(WARNING, PMD,
 625                         "indirection table %d is bigger than supported (%d)\n",
 626                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 627                 return -EINVAL;
 628         }
 629
 630         for (i = 0 ; i < reta_size ; i++) {
 631                 /* each reta_conf is for 64 entries.
 632                  * to support 128 we use 2 conf of 64
 633                  */
 634                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 635                 idx = i % RTE_RETA_GROUP_SIZE;
 636                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 637                         entry_value =
 638                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 639
 640                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 641                                                                i,
 642                                                                entry_value);
 643                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 644                                 RTE_LOG(ERR, PMD,
 645                                         "Cannot fill indirect table\n");
 646                                 return rc;
 647                         }
 648                 }
 649         }
 650
 651         rc = ena_com_indirect_table_set(ena_dev);
 652         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 653                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 654                 return rc;
 655         }
 656
 657         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 658                 __func__, reta_size, adapter->rte_dev->data->port_id);
 659
 660         return 0;
 661 }
 662
 663 /* Query redirection table. */
 664 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 665                               struct rte_eth_rss_reta_entry64 *reta_conf,
 666                               uint16_t reta_size)
 667 {
 668         struct ena_adapter *adapter =
 669                 (struct ena_adapter *)(dev->data->dev_private);
 670         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 671         int rc;
 672         int i;
 673         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 674         int reta_conf_idx;
 675         int reta_idx;
 676
 677         if (reta_size == 0 || reta_conf == NULL ||
 678             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 679                 return -EINVAL;
 680
 681         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 682         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 683                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 684                 return -ENOTSUP;
 685         }
 686
 687         for (i = 0 ; i < reta_size ; i++) {
 688                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 689                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 690                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 691                         reta_conf[reta_conf_idx].reta[reta_idx] =
 692                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 693         }
 694
 695         return 0;
 696 }
 697
 698 static int ena_rss_init_default(struct ena_adapter *adapter)
 699 {
 700         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 701         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 702         int rc, i;
 703         u32 val;
 704
 705         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 706         if (unlikely(rc)) {
 707                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 708                 goto err_rss_init;
 709         }
 710
 711         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 712                 val = i % nb_rx_queues;
 713                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 714                                                        ENA_IO_RXQ_IDX(val));
 715                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 716                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 717                         goto err_fill_indir;
 718                 }
 719         }
 720
 721         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 722                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 723         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 724                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 725                 goto err_fill_indir;
 726         }
 727
 728         rc = ena_com_set_default_hash_ctrl(ena_dev);
 729         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 730                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 731                 goto err_fill_indir;
 732         }
 733
 734         rc = ena_com_indirect_table_set(ena_dev);
 735         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 736                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 737                 goto err_fill_indir;
 738         }
 739         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 740                 adapter->rte_dev->data->port_id);
 741
 742         return 0;
 743
 744 err_fill_indir:
 745         ena_com_rss_destroy(ena_dev);
 746 err_rss_init:
 747
 748         return rc;
 749 }
 750
 751 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 752 {
 753         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 754         int nb_queues = dev->data->nb_rx_queues;
 755         int i;
 756
 757         for (i = 0; i < nb_queues; i++)
 758                 ena_rx_queue_release(queues[i]);
 759 }
 760
 761 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 762 {
 763         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 764         int nb_queues = dev->data->nb_tx_queues;
 765         int i;
 766
 767         for (i = 0; i < nb_queues; i++)
 768                 ena_tx_queue_release(queues[i]);
 769 }
 770
 771 static void ena_rx_queue_release(void *queue)
 772 {
 773         struct ena_ring *ring = (struct ena_ring *)queue;
 774
 775         ena_assert_msg(ring->configured,
 776                        "API violation - releasing not configured queue");
 777         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 778                        "API violation");
 779
 780         /* Free ring resources */
 781         if (ring->rx_buffer_info)
 782                 rte_free(ring->rx_buffer_info);
 783         ring->rx_buffer_info = NULL;
 784
 785         if (ring->rx_refill_buffer)
 786                 rte_free(ring->rx_refill_buffer);
 787         ring->rx_refill_buffer = NULL;
 788
 789         if (ring->empty_rx_reqs)
 790                 rte_free(ring->empty_rx_reqs);
 791         ring->empty_rx_reqs = NULL;
 792
 793         ring->configured = 0;
 794
 795         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 796                 ring->port_id, ring->id);
 797 }
 798
 799 static void ena_tx_queue_release(void *queue)
 800 {
 801         struct ena_ring *ring = (struct ena_ring *)queue;
 802
 803         ena_assert_msg(ring->configured,
 804                        "API violation. Releasing not configured queue");
 805         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 806                        "API violation");
 807
 808         /* Free all bufs */
 809         ena_tx_queue_release_bufs(ring);
 810
 811         /* Free ring resources */
 812         if (ring->push_buf_intermediate_buf)
 813                 rte_free(ring->push_buf_intermediate_buf);
 814
 815         if (ring->tx_buffer_info)
 816                 rte_free(ring->tx_buffer_info);
 817
 818         if (ring->empty_tx_reqs)
 819                 rte_free(ring->empty_tx_reqs);
 820
 821         ring->empty_tx_reqs = NULL;
 822         ring->tx_buffer_info = NULL;
 823         ring->push_buf_intermediate_buf = NULL;
 824
 825         ring->configured = 0;
 826
 827         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 828                 ring->port_id, ring->id);
 829 }
 830
 831 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 832 {
 833         unsigned int ring_mask = ring->ring_size - 1;
 834
 835         while (ring->next_to_clean != ring->next_to_use) {
 836                 struct rte_mbuf *m =
 837                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 838
 839                 if (m)
 840                         rte_mbuf_raw_free(m);
 841
 842                 ring->next_to_clean++;
 843         }
 844 }
 845
 846 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 847 {
 848         unsigned int i;
 849
 850         for (i = 0; i < ring->ring_size; ++i) {
 851                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 852
 853                 if (tx_buf->mbuf)
 854                         rte_pktmbuf_free(tx_buf->mbuf);
 855
 856                 ring->next_to_clean++;
 857         }
 858 }
 859
 860 static int ena_link_update(struct rte_eth_dev *dev,
 861                            __rte_unused int wait_to_complete)
 862 {
 863         struct rte_eth_link *link = &dev->data->dev_link;
 864         struct ena_adapter *adapter;
 865
 866         adapter = (struct ena_adapter *)(dev->data->dev_private);
 867
 868         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 869         link->link_speed = ETH_SPEED_NUM_NONE;
 870         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 871
 872         return 0;
 873 }
 874
 875 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 876                                  enum ena_ring_type ring_type)
 877 {
 878         struct ena_adapter *adapter =
 879                 (struct ena_adapter *)(dev->data->dev_private);
 880         struct ena_ring *queues = NULL;
 881         int nb_queues;
 882         int i = 0;
 883         int rc = 0;
 884
 885         if (ring_type == ENA_RING_TYPE_RX) {
 886                 queues = adapter->rx_ring;
 887                 nb_queues = dev->data->nb_rx_queues;
 888         } else {
 889                 queues = adapter->tx_ring;
 890                 nb_queues = dev->data->nb_tx_queues;
 891         }
 892         for (i = 0; i < nb_queues; i++) {
 893                 if (queues[i].configured) {
 894                         if (ring_type == ENA_RING_TYPE_RX) {
 895                                 ena_assert_msg(
 896                                         dev->data->rx_queues[i] == &queues[i],
 897                                         "Inconsistent state of rx queues\n");
 898                         } else {
 899                                 ena_assert_msg(
 900                                         dev->data->tx_queues[i] == &queues[i],
 901                                         "Inconsistent state of tx queues\n");
 902                         }
 903
 904                         rc = ena_queue_restart(&queues[i]);
 905
 906                         if (rc) {
 907                                 PMD_INIT_LOG(ERR,
 908                                              "failed to restart queue %d type(%d)",
 909                                              i, ring_type);
 910                                 return rc;
 911                         }
 912                 }
 913         }
 914
 915         return 0;
 916 }
 917
 918 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 919 {
 920         uint32_t max_frame_len = adapter->max_mtu;
 921
 922         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 923             DEV_RX_OFFLOAD_JUMBO_FRAME)
 924                 max_frame_len =
 925                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 926
 927         return max_frame_len;
 928 }
 929
 930 static int ena_check_valid_conf(struct ena_adapter *adapter)
 931 {
 932         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 933
 934         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 935                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 936                                   "max mtu: %d, min mtu: %d\n",
 937                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 938                 return ENA_COM_UNSUPPORTED;
 939         }
 940
 941         return 0;
 942 }
 943
 944 static int
 945 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)
 946 {
 947         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 948         struct ena_com_dev *ena_dev = ctx->ena_dev;
 949         uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX;
 950         uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX;
 951
 952         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 953                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 954                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 955                 rx_queue_size = RTE_MIN(rx_queue_size,
 956                         max_queue_ext->max_rx_cq_depth);
 957                 rx_queue_size = RTE_MIN(rx_queue_size,
 958                         max_queue_ext->max_rx_sq_depth);
 959                 tx_queue_size = RTE_MIN(tx_queue_size,
 960                         max_queue_ext->max_tx_cq_depth);
 961
 962                 if (ena_dev->tx_mem_queue_type ==
 963                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 964                         tx_queue_size = RTE_MIN(tx_queue_size,
 965                                 llq->max_llq_depth);
 966                 } else {
 967                         tx_queue_size = RTE_MIN(tx_queue_size,
 968                                 max_queue_ext->max_tx_sq_depth);
 969                 }
 970
 971                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 972                         max_queue_ext->max_per_packet_rx_descs);
 973                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 974                         max_queue_ext->max_per_packet_tx_descs);
 975         } else {
 976                 struct ena_admin_queue_feature_desc *max_queues =
 977                         &ctx->get_feat_ctx->max_queues;
 978                 rx_queue_size = RTE_MIN(rx_queue_size,
 979                         max_queues->max_cq_depth);
 980                 rx_queue_size = RTE_MIN(rx_queue_size,
 981                         max_queues->max_sq_depth);
 982                 tx_queue_size = RTE_MIN(tx_queue_size,
 983                         max_queues->max_cq_depth);
 984
 985                 if (ena_dev->tx_mem_queue_type ==
 986                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 987                         tx_queue_size = RTE_MIN(tx_queue_size,
 988                                 llq->max_llq_depth);
 989                 } else {
 990                         tx_queue_size = RTE_MIN(tx_queue_size,
 991                                 max_queues->max_sq_depth);
 992                 }
 993
 994                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 995                         max_queues->max_packet_tx_descs);
 996                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 997                         max_queues->max_packet_rx_descs);
 998         }
 999
1000         /* Round down to the nearest power of 2 */
1001         rx_queue_size = rte_align32prevpow2(rx_queue_size);
1002         tx_queue_size = rte_align32prevpow2(tx_queue_size);
1003
1004         if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) {
1005                 PMD_INIT_LOG(ERR, "Invalid queue size");
1006                 return -EFAULT;
1007         }
1008
1009         ctx->rx_queue_size = rx_queue_size;
1010         ctx->tx_queue_size = tx_queue_size;
1011
1012         return 0;
1013 }
1014
1015 static void ena_stats_restart(struct rte_eth_dev *dev)
1016 {
1017         struct ena_adapter *adapter =
1018                 (struct ena_adapter *)(dev->data->dev_private);
1019
1020         rte_atomic64_init(&adapter->drv_stats->ierrors);
1021         rte_atomic64_init(&adapter->drv_stats->oerrors);
1022         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
1023 }
1024
1025 static int ena_stats_get(struct rte_eth_dev *dev,
1026                           struct rte_eth_stats *stats)
1027 {
1028         struct ena_admin_basic_stats ena_stats;
1029         struct ena_adapter *adapter =
1030                 (struct ena_adapter *)(dev->data->dev_private);
1031         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1032         int rc;
1033
1034         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1035                 return -ENOTSUP;
1036
1037         memset(&ena_stats, 0, sizeof(ena_stats));
1038         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
1039         if (unlikely(rc)) {
1040                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
1041                 return rc;
1042         }
1043
1044         /* Set of basic statistics from ENA */
1045         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
1046                                           ena_stats.rx_pkts_low);
1047         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
1048                                           ena_stats.tx_pkts_low);
1049         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
1050                                         ena_stats.rx_bytes_low);
1051         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
1052                                         ena_stats.tx_bytes_low);
1053         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
1054                                          ena_stats.rx_drops_low);
1055
1056         /* Driver related stats */
1057         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1058         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1059         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1060         return 0;
1061 }
1062
1063 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1064 {
1065         struct ena_adapter *adapter;
1066         struct ena_com_dev *ena_dev;
1067         int rc = 0;
1068
1069         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1070         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1071         adapter = (struct ena_adapter *)(dev->data->dev_private);
1072
1073         ena_dev = &adapter->ena_dev;
1074         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1075
1076         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1077                 RTE_LOG(ERR, PMD,
1078                         "Invalid MTU setting. new_mtu: %d "
1079                         "max mtu: %d min mtu: %d\n",
1080                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1081                 return -EINVAL;
1082         }
1083
1084         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1085         if (rc)
1086                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
1087         else
1088                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1089
1090         return rc;
1091 }
1092
1093 static int ena_start(struct rte_eth_dev *dev)
1094 {
1095         struct ena_adapter *adapter =
1096                 (struct ena_adapter *)(dev->data->dev_private);
1097         uint64_t ticks;
1098         int rc = 0;
1099
1100         rc = ena_check_valid_conf(adapter);
1101         if (rc)
1102                 return rc;
1103
1104         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
1105         if (rc)
1106                 return rc;
1107
1108         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
1109         if (rc)
1110                 return rc;
1111
1112         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1113             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1114                 rc = ena_rss_init_default(adapter);
1115                 if (rc)
1116                         return rc;
1117         }
1118
1119         ena_stats_restart(dev);
1120
1121         adapter->timestamp_wd = rte_get_timer_cycles();
1122         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1123
1124         ticks = rte_get_timer_hz();
1125         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1126                         ena_timer_wd_callback, adapter);
1127
1128         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1129
1130         return 0;
1131 }
1132
1133 static void ena_stop(struct rte_eth_dev *dev)
1134 {
1135         struct ena_adapter *adapter =
1136                 (struct ena_adapter *)(dev->data->dev_private);
1137
1138         rte_timer_stop_sync(&adapter->timer_wd);
1139         ena_free_io_queues_all(adapter);
1140
1141         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1142 }
1143
1144 static int ena_create_io_queue(struct ena_ring *ring)
1145 {
1146         struct ena_adapter *adapter;
1147         struct ena_com_dev *ena_dev;
1148         struct ena_com_create_io_ctx ctx =
1149                 /* policy set to _HOST just to satisfy icc compiler */
1150                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1151                   0, 0, 0, 0, 0 };
1152         uint16_t ena_qid;
1153         unsigned int i;
1154         int rc;
1155
1156         adapter = ring->adapter;
1157         ena_dev = &adapter->ena_dev;
1158
1159         if (ring->type == ENA_RING_TYPE_TX) {
1160                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1161                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1162                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1163                 ctx.queue_size = adapter->tx_ring_size;
1164                 for (i = 0; i < ring->ring_size; i++)
1165                         ring->empty_tx_reqs[i] = i;
1166         } else {
1167                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1168                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1169                 ctx.queue_size = adapter->rx_ring_size;
1170                 for (i = 0; i < ring->ring_size; i++)
1171                         ring->empty_rx_reqs[i] = i;
1172         }
1173         ctx.qid = ena_qid;
1174         ctx.msix_vector = -1; /* interrupts not used */
1175         ctx.numa_node = ena_cpu_to_node(ring->id);
1176
1177         rc = ena_com_create_io_queue(ena_dev, &ctx);
1178         if (rc) {
1179                 RTE_LOG(ERR, PMD,
1180                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1181                         ring->id, ena_qid, rc);
1182                 return rc;
1183         }
1184
1185         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1186                                      &ring->ena_com_io_sq,
1187                                      &ring->ena_com_io_cq);
1188         if (rc) {
1189                 RTE_LOG(ERR, PMD,
1190                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1191                         ring->id, rc);
1192                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1193                 return rc;
1194         }
1195
1196         if (ring->type == ENA_RING_TYPE_TX)
1197                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1198
1199         return 0;
1200 }
1201
1202 static void ena_free_io_queues_all(struct ena_adapter *adapter)
1203 {
1204         struct rte_eth_dev *eth_dev = adapter->rte_dev;
1205         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1206         int i;
1207         uint16_t ena_qid;
1208         uint16_t nb_rxq = eth_dev->data->nb_rx_queues;
1209         uint16_t nb_txq = eth_dev->data->nb_tx_queues;
1210
1211         for (i = 0; i < nb_txq; ++i) {
1212                 ena_qid = ENA_IO_TXQ_IDX(i);
1213                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1214
1215                 ena_tx_queue_release_bufs(&adapter->tx_ring[i]);
1216         }
1217
1218         for (i = 0; i < nb_rxq; ++i) {
1219                 ena_qid = ENA_IO_RXQ_IDX(i);
1220                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1221
1222                 ena_rx_queue_release_bufs(&adapter->rx_ring[i]);
1223         }
1224 }
1225
1226 static int ena_queue_restart(struct ena_ring *ring)
1227 {
1228         int rc, bufs_num;
1229
1230         ena_assert_msg(ring->configured == 1,
1231                        "Trying to restart unconfigured queue\n");
1232
1233         rc = ena_create_io_queue(ring);
1234         if (rc) {
1235                 PMD_INIT_LOG(ERR, "Failed to create IO queue!\n");
1236                 return rc;
1237         }
1238
1239         ring->next_to_clean = 0;
1240         ring->next_to_use = 0;
1241
1242         if (ring->type == ENA_RING_TYPE_TX)
1243                 return 0;
1244
1245         bufs_num = ring->ring_size - 1;
1246         rc = ena_populate_rx_queue(ring, bufs_num);
1247         if (rc != bufs_num) {
1248                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1249                 return ENA_COM_FAULT;
1250         }
1251
1252         return 0;
1253 }
1254
1255 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1256                               uint16_t queue_idx,
1257                               uint16_t nb_desc,
1258                               __rte_unused unsigned int socket_id,
1259                               const struct rte_eth_txconf *tx_conf)
1260 {
1261         struct ena_ring *txq = NULL;
1262         struct ena_adapter *adapter =
1263                 (struct ena_adapter *)(dev->data->dev_private);
1264         unsigned int i;
1265
1266         txq = &adapter->tx_ring[queue_idx];
1267
1268         if (txq->configured) {
1269                 RTE_LOG(CRIT, PMD,
1270                         "API violation. Queue %d is already configured\n",
1271                         queue_idx);
1272                 return ENA_COM_FAULT;
1273         }
1274
1275         if (!rte_is_power_of_2(nb_desc)) {
1276                 RTE_LOG(ERR, PMD,
1277                         "Unsupported size of TX queue: %d is not a power of 2.",
1278                         nb_desc);
1279                 return -EINVAL;
1280         }
1281
1282         if (nb_desc > adapter->tx_ring_size) {
1283                 RTE_LOG(ERR, PMD,
1284                         "Unsupported size of TX queue (max size: %d)\n",
1285                         adapter->tx_ring_size);
1286                 return -EINVAL;
1287         }
1288
1289         if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1290                 nb_desc = adapter->tx_ring_size;
1291
1292         txq->port_id = dev->data->port_id;
1293         txq->next_to_clean = 0;
1294         txq->next_to_use = 0;
1295         txq->ring_size = nb_desc;
1296
1297         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1298                                           sizeof(struct ena_tx_buffer) *
1299                                           txq->ring_size,
1300                                           RTE_CACHE_LINE_SIZE);
1301         if (!txq->tx_buffer_info) {
1302                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1303                 return -ENOMEM;
1304         }
1305
1306         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1307                                          sizeof(u16) * txq->ring_size,
1308                                          RTE_CACHE_LINE_SIZE);
1309         if (!txq->empty_tx_reqs) {
1310                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1311                 rte_free(txq->tx_buffer_info);
1312                 return -ENOMEM;
1313         }
1314
1315         txq->push_buf_intermediate_buf =
1316                 rte_zmalloc("txq->push_buf_intermediate_buf",
1317                             txq->tx_max_header_size,
1318                             RTE_CACHE_LINE_SIZE);
1319         if (!txq->push_buf_intermediate_buf) {
1320                 RTE_LOG(ERR, PMD, "failed to alloc push buff for LLQ\n");
1321                 rte_free(txq->tx_buffer_info);
1322                 rte_free(txq->empty_tx_reqs);
1323                 return -ENOMEM;
1324         }
1325
1326         for (i = 0; i < txq->ring_size; i++)
1327                 txq->empty_tx_reqs[i] = i;
1328
1329         if (tx_conf != NULL) {
1330                 txq->offloads =
1331                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1332         }
1333
1334         /* Store pointer to this queue in upper layer */
1335         txq->configured = 1;
1336         dev->data->tx_queues[queue_idx] = txq;
1337
1338         return 0;
1339 }
1340
1341 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1342                               uint16_t queue_idx,
1343                               uint16_t nb_desc,
1344                               __rte_unused unsigned int socket_id,
1345                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1346                               struct rte_mempool *mp)
1347 {
1348         struct ena_adapter *adapter =
1349                 (struct ena_adapter *)(dev->data->dev_private);
1350         struct ena_ring *rxq = NULL;
1351         int i;
1352
1353         rxq = &adapter->rx_ring[queue_idx];
1354         if (rxq->configured) {
1355                 RTE_LOG(CRIT, PMD,
1356                         "API violation. Queue %d is already configured\n",
1357                         queue_idx);
1358                 return ENA_COM_FAULT;
1359         }
1360
1361         if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1362                 nb_desc = adapter->rx_ring_size;
1363
1364         if (!rte_is_power_of_2(nb_desc)) {
1365                 RTE_LOG(ERR, PMD,
1366                         "Unsupported size of RX queue: %d is not a power of 2.",
1367                         nb_desc);
1368                 return -EINVAL;
1369         }
1370
1371         if (nb_desc > adapter->rx_ring_size) {
1372                 RTE_LOG(ERR, PMD,
1373                         "Unsupported size of RX queue (max size: %d)\n",
1374                         adapter->rx_ring_size);
1375                 return -EINVAL;
1376         }
1377
1378         rxq->port_id = dev->data->port_id;
1379         rxq->next_to_clean = 0;
1380         rxq->next_to_use = 0;
1381         rxq->ring_size = nb_desc;
1382         rxq->mb_pool = mp;
1383
1384         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1385                                           sizeof(struct rte_mbuf *) * nb_desc,
1386                                           RTE_CACHE_LINE_SIZE);
1387         if (!rxq->rx_buffer_info) {
1388                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1389                 return -ENOMEM;
1390         }
1391
1392         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1393                                             sizeof(struct rte_mbuf *) * nb_desc,
1394                                             RTE_CACHE_LINE_SIZE);
1395
1396         if (!rxq->rx_refill_buffer) {
1397                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n");
1398                 rte_free(rxq->rx_buffer_info);
1399                 rxq->rx_buffer_info = NULL;
1400                 return -ENOMEM;
1401         }
1402
1403         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1404                                          sizeof(uint16_t) * nb_desc,
1405                                          RTE_CACHE_LINE_SIZE);
1406         if (!rxq->empty_rx_reqs) {
1407                 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1408                 rte_free(rxq->rx_buffer_info);
1409                 rxq->rx_buffer_info = NULL;
1410                 rte_free(rxq->rx_refill_buffer);
1411                 rxq->rx_refill_buffer = NULL;
1412                 return -ENOMEM;
1413         }
1414
1415         for (i = 0; i < nb_desc; i++)
1416                 rxq->empty_tx_reqs[i] = i;
1417
1418         /* Store pointer to this queue in upper layer */
1419         rxq->configured = 1;
1420         dev->data->rx_queues[queue_idx] = rxq;
1421
1422         return 0;
1423 }
1424
1425 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1426 {
1427         unsigned int i;
1428         int rc;
1429         uint16_t ring_size = rxq->ring_size;
1430         uint16_t ring_mask = ring_size - 1;
1431         uint16_t next_to_use = rxq->next_to_use;
1432         uint16_t in_use, req_id;
1433         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1434
1435         if (unlikely(!count))
1436                 return 0;
1437
1438         in_use = rxq->next_to_use - rxq->next_to_clean;
1439         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1440
1441         /* get resources for incoming packets */
1442         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1443         if (unlikely(rc < 0)) {
1444                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1445                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1446                 return 0;
1447         }
1448
1449         for (i = 0; i < count; i++) {
1450                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1451                 struct rte_mbuf *mbuf = mbufs[i];
1452                 struct ena_com_buf ebuf;
1453
1454                 if (likely((i + 4) < count))
1455                         rte_prefetch0(mbufs[i + 4]);
1456
1457                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1458                 rc = validate_rx_req_id(rxq, req_id);
1459                 if (unlikely(rc < 0))
1460                         break;
1461                 rxq->rx_buffer_info[req_id] = mbuf;
1462
1463                 /* prepare physical address for DMA transaction */
1464                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1465                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1466                 /* pass resource to device */
1467                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1468                                                 &ebuf, req_id);
1469                 if (unlikely(rc)) {
1470                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1471                         rxq->rx_buffer_info[req_id] = NULL;
1472                         break;
1473                 }
1474                 next_to_use++;
1475         }
1476
1477         if (unlikely(i < count)) {
1478                 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d "
1479                         "buffers (from %d)\n", rxq->id, i, count);
1480                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1481                                      count - i);
1482         }
1483
1484         /* When we submitted free recources to device... */
1485         if (likely(i > 0)) {
1486                 /* ...let HW know that it can fill buffers with data
1487                  *
1488                  * Add memory barrier to make sure the desc were written before
1489                  * issue a doorbell
1490                  */
1491                 rte_wmb();
1492                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1493
1494                 rxq->next_to_use = next_to_use;
1495         }
1496
1497         return i;
1498 }
1499
1500 static int ena_device_init(struct ena_com_dev *ena_dev,
1501                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1502                            bool *wd_state)
1503 {
1504         uint32_t aenq_groups;
1505         int rc;
1506         bool readless_supported;
1507
1508         /* Initialize mmio registers */
1509         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1510         if (rc) {
1511                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1512                 return rc;
1513         }
1514
1515         /* The PCIe configuration space revision id indicate if mmio reg
1516          * read is disabled.
1517          */
1518         readless_supported =
1519                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1520                                & ENA_MMIO_DISABLE_REG_READ);
1521         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1522
1523         /* reset device */
1524         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1525         if (rc) {
1526                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1527                 goto err_mmio_read_less;
1528         }
1529
1530         /* check FW version */
1531         rc = ena_com_validate_version(ena_dev);
1532         if (rc) {
1533                 RTE_LOG(ERR, PMD, "device version is too low\n");
1534                 goto err_mmio_read_less;
1535         }
1536
1537         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1538
1539         /* ENA device administration layer init */
1540         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1541         if (rc) {
1542                 RTE_LOG(ERR, PMD,
1543                         "cannot initialize ena admin queue with device\n");
1544                 goto err_mmio_read_less;
1545         }
1546
1547         /* To enable the msix interrupts the driver needs to know the number
1548          * of queues. So the driver uses polling mode to retrieve this
1549          * information.
1550          */
1551         ena_com_set_admin_polling_mode(ena_dev, true);
1552
1553         ena_config_host_info(ena_dev);
1554
1555         /* Get Device Attributes and features */
1556         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1557         if (rc) {
1558                 RTE_LOG(ERR, PMD,
1559                         "cannot get attribute for ena device rc= %d\n", rc);
1560                 goto err_admin_init;
1561         }
1562
1563         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1564                       BIT(ENA_ADMIN_NOTIFICATION) |
1565                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1566                       BIT(ENA_ADMIN_FATAL_ERROR) |
1567                       BIT(ENA_ADMIN_WARNING);
1568
1569         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1570         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1571         if (rc) {
1572                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1573                 goto err_admin_init;
1574         }
1575
1576         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1577
1578         return 0;
1579
1580 err_admin_init:
1581         ena_com_admin_destroy(ena_dev);
1582
1583 err_mmio_read_less:
1584         ena_com_mmio_reg_read_request_destroy(ena_dev);
1585
1586         return rc;
1587 }
1588
1589 static void ena_interrupt_handler_rte(void *cb_arg)
1590 {
1591         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1592         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1593
1594         ena_com_admin_q_comp_intr_handler(ena_dev);
1595         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1596                 ena_com_aenq_intr_handler(ena_dev, adapter);
1597 }
1598
1599 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1600 {
1601         if (!adapter->wd_state)
1602                 return;
1603
1604         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1605                 return;
1606
1607         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1608             adapter->keep_alive_timeout)) {
1609                 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1610                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1611                 adapter->trigger_reset = true;
1612         }
1613 }
1614
1615 /* Check if admin queue is enabled */
1616 static void check_for_admin_com_state(struct ena_adapter *adapter)
1617 {
1618         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1619                 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1620                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1621                 adapter->trigger_reset = true;
1622         }
1623 }
1624
1625 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1626                                   void *arg)
1627 {
1628         struct ena_adapter *adapter = (struct ena_adapter *)arg;
1629         struct rte_eth_dev *dev = adapter->rte_dev;
1630
1631         check_for_missing_keep_alive(adapter);
1632         check_for_admin_com_state(adapter);
1633
1634         if (unlikely(adapter->trigger_reset)) {
1635                 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1636                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1637                         NULL);
1638         }
1639 }
1640
1641 static inline void
1642 set_default_llq_configurations(struct ena_llq_configurations *llq_config)
1643 {
1644         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1645         llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1646         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1647         llq_config->llq_num_decs_before_header =
1648                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1649         llq_config->llq_ring_entry_size_value = 128;
1650 }
1651
1652 static int
1653 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1654                                 struct ena_com_dev *ena_dev,
1655                                 struct ena_admin_feature_llq_desc *llq,
1656                                 struct ena_llq_configurations *llq_default_configurations)
1657 {
1658         int rc;
1659         u32 llq_feature_mask;
1660
1661         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1662         if (!(ena_dev->supported_features & llq_feature_mask)) {
1663                 RTE_LOG(INFO, PMD,
1664                         "LLQ is not supported. Fallback to host mode policy.\n");
1665                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1666                 return 0;
1667         }
1668
1669         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1670         if (unlikely(rc)) {
1671                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1672                         "Fallback to host mode policy.\n");
1673                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1674                 return 0;
1675         }
1676
1677         /* Nothing to config, exit */
1678         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1679                 return 0;
1680
1681         if (!adapter->dev_mem_base) {
1682                 RTE_LOG(ERR, PMD, "Unable to access LLQ bar resource. "
1683                         "Fallback to host mode policy.\n.");
1684                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1685                 return 0;
1686         }
1687
1688         ena_dev->mem_bar = adapter->dev_mem_base;
1689
1690         return 0;
1691 }
1692
1693 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,
1694                                  struct ena_com_dev_get_features_ctx *get_feat_ctx)
1695 {
1696         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num;
1697
1698         /* Regular queues capabilities */
1699         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1700                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1701                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1702                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1703                                     max_queue_ext->max_rx_cq_num);
1704                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1705                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1706         } else {
1707                 struct ena_admin_queue_feature_desc *max_queues =
1708                         &get_feat_ctx->max_queues;
1709                 io_tx_sq_num = max_queues->max_sq_num;
1710                 io_tx_cq_num = max_queues->max_cq_num;
1711                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1712         }
1713
1714         /* In case of LLQ use the llq number in the get feature cmd */
1715         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1716                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1717
1718         io_queue_num = RTE_MIN(rte_lcore_count(), ENA_MAX_NUM_IO_QUEUES);
1719         io_queue_num = RTE_MIN(io_queue_num, io_rx_num);
1720         io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num);
1721         io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num);
1722
1723         if (unlikely(io_queue_num == 0)) {
1724                 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n");
1725                 return -EFAULT;
1726         }
1727
1728         return io_queue_num;
1729 }
1730
1731 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1732 {
1733         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1734         struct rte_pci_device *pci_dev;
1735         struct rte_intr_handle *intr_handle;
1736         struct ena_adapter *adapter =
1737                 (struct ena_adapter *)(eth_dev->data->dev_private);
1738         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1739         struct ena_com_dev_get_features_ctx get_feat_ctx;
1740         struct ena_llq_configurations llq_config;
1741         const char *queue_type_str;
1742         int rc;
1743
1744         static int adapters_found;
1745         bool wd_state;
1746
1747         memset(adapter, 0, sizeof(struct ena_adapter));
1748         ena_dev = &adapter->ena_dev;
1749
1750         eth_dev->dev_ops = &ena_dev_ops;
1751         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1752         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1753         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1754         adapter->rte_eth_dev_data = eth_dev->data;
1755         adapter->rte_dev = eth_dev;
1756
1757         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1758                 return 0;
1759
1760         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1761         adapter->pdev = pci_dev;
1762
1763         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1764                      pci_dev->addr.domain,
1765                      pci_dev->addr.bus,
1766                      pci_dev->addr.devid,
1767                      pci_dev->addr.function);
1768
1769         intr_handle = &pci_dev->intr_handle;
1770
1771         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1772         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1773
1774         if (!adapter->regs) {
1775                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1776                              ENA_REGS_BAR);
1777                 return -ENXIO;
1778         }
1779
1780         ena_dev->reg_bar = adapter->regs;
1781         ena_dev->dmadev = adapter->pdev;
1782
1783         adapter->id_number = adapters_found;
1784
1785         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1786                  adapter->id_number);
1787
1788         /* device specific initialization routine */
1789         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1790         if (rc) {
1791                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1792                 goto err;
1793         }
1794         adapter->wd_state = wd_state;
1795
1796         set_default_llq_configurations(&llq_config);
1797         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1798                                              &get_feat_ctx.llq, &llq_config);
1799         if (unlikely(rc)) {
1800                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1801                 return rc;
1802         }
1803
1804         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1805                 queue_type_str = "Regular";
1806         else
1807                 queue_type_str = "Low latency";
1808         RTE_LOG(INFO, PMD, "Placement policy: %s\n", queue_type_str);
1809
1810         calc_queue_ctx.ena_dev = ena_dev;
1811         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1812         adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1813                                                     &get_feat_ctx);
1814
1815         rc = ena_calc_queue_size(&calc_queue_ctx);
1816         if (unlikely((rc != 0) || (adapter->num_queues <= 0))) {
1817                 rc = -EFAULT;
1818                 goto err_device_destroy;
1819         }
1820
1821         adapter->tx_ring_size = calc_queue_ctx.tx_queue_size;
1822         adapter->rx_ring_size = calc_queue_ctx.rx_queue_size;
1823
1824         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1825         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1826
1827         /* prepare ring structures */
1828         ena_init_rings(adapter);
1829
1830         ena_config_debug_area(adapter);
1831
1832         /* Set max MTU for this device */
1833         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1834
1835         /* set device support for TSO */
1836         adapter->tso4_supported = get_feat_ctx.offload.tx &
1837                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1838
1839         /* Copy MAC address and point DPDK to it */
1840         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1841         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1842                         (struct ether_addr *)adapter->mac_addr);
1843
1844         /*
1845          * Pass the information to the rte_eth_dev_close() that it should also
1846          * release the private port resources.
1847          */
1848         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1849
1850         adapter->drv_stats = rte_zmalloc("adapter stats",
1851                                          sizeof(*adapter->drv_stats),
1852                                          RTE_CACHE_LINE_SIZE);
1853         if (!adapter->drv_stats) {
1854                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1855                 rc = -ENOMEM;
1856                 goto err_delete_debug_area;
1857         }
1858
1859         rte_intr_callback_register(intr_handle,
1860                                    ena_interrupt_handler_rte,
1861                                    adapter);
1862         rte_intr_enable(intr_handle);
1863         ena_com_set_admin_polling_mode(ena_dev, false);
1864         ena_com_admin_aenq_enable(ena_dev);
1865
1866         if (adapters_found == 0)
1867                 rte_timer_subsystem_init();
1868         rte_timer_init(&adapter->timer_wd);
1869
1870         adapters_found++;
1871         adapter->state = ENA_ADAPTER_STATE_INIT;
1872
1873         return 0;
1874
1875 err_delete_debug_area:
1876         ena_com_delete_debug_area(ena_dev);
1877
1878 err_device_destroy:
1879         ena_com_delete_host_info(ena_dev);
1880         ena_com_admin_destroy(ena_dev);
1881
1882 err:
1883         return rc;
1884 }
1885
1886 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1887 {
1888         struct ena_adapter *adapter =
1889                 (struct ena_adapter *)(eth_dev->data->dev_private);
1890
1891         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1892                 return 0;
1893
1894         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1895                 ena_close(eth_dev);
1896
1897         eth_dev->dev_ops = NULL;
1898         eth_dev->rx_pkt_burst = NULL;
1899         eth_dev->tx_pkt_burst = NULL;
1900         eth_dev->tx_pkt_prepare = NULL;
1901
1902         adapter->state = ENA_ADAPTER_STATE_FREE;
1903
1904         return 0;
1905 }
1906
1907 static int ena_dev_configure(struct rte_eth_dev *dev)
1908 {
1909         struct ena_adapter *adapter =
1910                 (struct ena_adapter *)(dev->data->dev_private);
1911
1912         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1913
1914         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1915         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1916         return 0;
1917 }
1918
1919 static void ena_init_rings(struct ena_adapter *adapter)
1920 {
1921         int i;
1922
1923         for (i = 0; i < adapter->num_queues; i++) {
1924                 struct ena_ring *ring = &adapter->tx_ring[i];
1925
1926                 ring->configured = 0;
1927                 ring->type = ENA_RING_TYPE_TX;
1928                 ring->adapter = adapter;
1929                 ring->id = i;
1930                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1931                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1932                 ring->sgl_size = adapter->max_tx_sgl_size;
1933         }
1934
1935         for (i = 0; i < adapter->num_queues; i++) {
1936                 struct ena_ring *ring = &adapter->rx_ring[i];
1937
1938                 ring->configured = 0;
1939                 ring->type = ENA_RING_TYPE_RX;
1940                 ring->adapter = adapter;
1941                 ring->id = i;
1942                 ring->sgl_size = adapter->max_rx_sgl_size;
1943         }
1944 }
1945
1946 static void ena_infos_get(struct rte_eth_dev *dev,
1947                           struct rte_eth_dev_info *dev_info)
1948 {
1949         struct ena_adapter *adapter;
1950         struct ena_com_dev *ena_dev;
1951         struct ena_com_dev_get_features_ctx feat;
1952         uint64_t rx_feat = 0, tx_feat = 0;
1953         int rc = 0;
1954
1955         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1956         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1957         adapter = (struct ena_adapter *)(dev->data->dev_private);
1958
1959         ena_dev = &adapter->ena_dev;
1960         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1961
1962         dev_info->speed_capa =
1963                         ETH_LINK_SPEED_1G   |
1964                         ETH_LINK_SPEED_2_5G |
1965                         ETH_LINK_SPEED_5G   |
1966                         ETH_LINK_SPEED_10G  |
1967                         ETH_LINK_SPEED_25G  |
1968                         ETH_LINK_SPEED_40G  |
1969                         ETH_LINK_SPEED_50G  |
1970                         ETH_LINK_SPEED_100G;
1971
1972         /* Get supported features from HW */
1973         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1974         if (unlikely(rc)) {
1975                 RTE_LOG(ERR, PMD,
1976                         "Cannot get attribute for ena device rc= %d\n", rc);
1977                 return;
1978         }
1979
1980         /* Set Tx & Rx features available for device */
1981         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1982                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1983
1984         if (feat.offload.tx &
1985             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1986                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1987                         DEV_TX_OFFLOAD_UDP_CKSUM |
1988                         DEV_TX_OFFLOAD_TCP_CKSUM;
1989
1990         if (feat.offload.rx_supported &
1991             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1992                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1993                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1994                         DEV_RX_OFFLOAD_TCP_CKSUM;
1995
1996         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1997
1998         /* Inform framework about available features */
1999         dev_info->rx_offload_capa = rx_feat;
2000         dev_info->rx_queue_offload_capa = rx_feat;
2001         dev_info->tx_offload_capa = tx_feat;
2002         dev_info->tx_queue_offload_capa = tx_feat;
2003
2004         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2005         dev_info->max_rx_pktlen  = adapter->max_mtu;
2006         dev_info->max_mac_addrs = 1;
2007
2008         dev_info->max_rx_queues = adapter->num_queues;
2009         dev_info->max_tx_queues = adapter->num_queues;
2010         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2011
2012         adapter->tx_supported_offloads = tx_feat;
2013         adapter->rx_supported_offloads = rx_feat;
2014
2015         dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size;
2016         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2017         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2018                                         adapter->max_rx_sgl_size);
2019         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2020                                         adapter->max_rx_sgl_size);
2021
2022         dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size;
2023         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2024         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2025                                         adapter->max_tx_sgl_size);
2026         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2027                                         adapter->max_tx_sgl_size);
2028 }
2029
2030 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2031                                   uint16_t nb_pkts)
2032 {
2033         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2034         unsigned int ring_size = rx_ring->ring_size;
2035         unsigned int ring_mask = ring_size - 1;
2036         uint16_t next_to_clean = rx_ring->next_to_clean;
2037         uint16_t desc_in_use = 0;
2038         uint16_t req_id;
2039         unsigned int recv_idx = 0;
2040         struct rte_mbuf *mbuf = NULL;
2041         struct rte_mbuf *mbuf_head = NULL;
2042         struct rte_mbuf *mbuf_prev = NULL;
2043         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
2044         unsigned int completed;
2045
2046         struct ena_com_rx_ctx ena_rx_ctx;
2047         int rc = 0;
2048
2049         /* Check adapter state */
2050         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2051                 RTE_LOG(ALERT, PMD,
2052                         "Trying to receive pkts while device is NOT running\n");
2053                 return 0;
2054         }
2055
2056         desc_in_use = rx_ring->next_to_use - next_to_clean;
2057         if (unlikely(nb_pkts > desc_in_use))
2058                 nb_pkts = desc_in_use;
2059
2060         for (completed = 0; completed < nb_pkts; completed++) {
2061                 int segments = 0;
2062
2063                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2064                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2065                 ena_rx_ctx.descs = 0;
2066                 /* receive packet context */
2067                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2068                                     rx_ring->ena_com_io_sq,
2069                                     &ena_rx_ctx);
2070                 if (unlikely(rc)) {
2071                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
2072                         rx_ring->adapter->reset_reason =
2073                                 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2074                         rx_ring->adapter->trigger_reset = true;
2075                         return 0;
2076                 }
2077
2078                 if (unlikely(ena_rx_ctx.descs == 0))
2079                         break;
2080
2081                 while (segments < ena_rx_ctx.descs) {
2082                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
2083                         rc = validate_rx_req_id(rx_ring, req_id);
2084                         if (unlikely(rc))
2085                                 break;
2086
2087                         mbuf = rx_buff_info[req_id];
2088                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
2089                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2090                         mbuf->refcnt = 1;
2091                         mbuf->next = NULL;
2092                         if (unlikely(segments == 0)) {
2093                                 mbuf->nb_segs = ena_rx_ctx.descs;
2094                                 mbuf->port = rx_ring->port_id;
2095                                 mbuf->pkt_len = 0;
2096                                 mbuf_head = mbuf;
2097                         } else {
2098                                 /* for multi-segment pkts create mbuf chain */
2099                                 mbuf_prev->next = mbuf;
2100                         }
2101                         mbuf_head->pkt_len += mbuf->data_len;
2102
2103                         mbuf_prev = mbuf;
2104                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
2105                                 req_id;
2106                         segments++;
2107                         next_to_clean++;
2108                 }
2109                 if (unlikely(rc))
2110                         break;
2111
2112                 /* fill mbuf attributes if any */
2113                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
2114                 mbuf_head->hash.rss = ena_rx_ctx.hash;
2115
2116                 /* pass to DPDK application head mbuf */
2117                 rx_pkts[recv_idx] = mbuf_head;
2118                 recv_idx++;
2119         }
2120
2121         rx_ring->next_to_clean = next_to_clean;
2122
2123         desc_in_use = desc_in_use - completed + 1;
2124         /* Burst refill to save doorbells, memory barriers, const interval */
2125         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
2126                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
2127
2128         return recv_idx;
2129 }
2130
2131 static uint16_t
2132 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2133                 uint16_t nb_pkts)
2134 {
2135         int32_t ret;
2136         uint32_t i;
2137         struct rte_mbuf *m;
2138         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2139         struct ipv4_hdr *ip_hdr;
2140         uint64_t ol_flags;
2141         uint16_t frag_field;
2142
2143         for (i = 0; i != nb_pkts; i++) {
2144                 m = tx_pkts[i];
2145                 ol_flags = m->ol_flags;
2146
2147                 if (!(ol_flags & PKT_TX_IPV4))
2148                         continue;
2149
2150                 /* If there was not L2 header length specified, assume it is
2151                  * length of the ethernet header.
2152                  */
2153                 if (unlikely(m->l2_len == 0))
2154                         m->l2_len = sizeof(struct ether_hdr);
2155
2156                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
2157                                                  m->l2_len);
2158                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2159
2160                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
2161                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2162
2163                         /* If IPv4 header has DF flag enabled and TSO support is
2164                          * disabled, partial chcecksum should not be calculated.
2165                          */
2166                         if (!tx_ring->adapter->tso4_supported)
2167                                 continue;
2168                 }
2169
2170                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2171                                 (ol_flags & PKT_TX_L4_MASK) ==
2172                                 PKT_TX_SCTP_CKSUM) {
2173                         rte_errno = -ENOTSUP;
2174                         return i;
2175                 }
2176
2177 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2178                 ret = rte_validate_tx_offload(m);
2179                 if (ret != 0) {
2180                         rte_errno = ret;
2181                         return i;
2182                 }
2183 #endif
2184
2185                 /* In case we are supposed to TSO and have DF not set (DF=0)
2186                  * hardware must be provided with partial checksum, otherwise
2187                  * it will take care of necessary calculations.
2188                  */
2189
2190                 ret = rte_net_intel_cksum_flags_prepare(m,
2191                         ol_flags & ~PKT_TX_TCP_SEG);
2192                 if (ret != 0) {
2193                         rte_errno = ret;
2194                         return i;
2195                 }
2196         }
2197
2198         return i;
2199 }
2200
2201 static void ena_update_hints(struct ena_adapter *adapter,
2202                              struct ena_admin_ena_hw_hints *hints)
2203 {
2204         if (hints->admin_completion_tx_timeout)
2205                 adapter->ena_dev.admin_queue.completion_timeout =
2206                         hints->admin_completion_tx_timeout * 1000;
2207
2208         if (hints->mmio_read_timeout)
2209                 /* convert to usec */
2210                 adapter->ena_dev.mmio_read.reg_read_to =
2211                         hints->mmio_read_timeout * 1000;
2212
2213         if (hints->driver_watchdog_timeout) {
2214                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2215                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2216                 else
2217                         // Convert msecs to ticks
2218                         adapter->keep_alive_timeout =
2219                                 (hints->driver_watchdog_timeout *
2220                                 rte_get_timer_hz()) / 1000;
2221         }
2222 }
2223
2224 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2225                                         struct rte_mbuf *mbuf)
2226 {
2227         struct ena_com_dev *ena_dev;
2228         int num_segments, header_len, rc;
2229
2230         ena_dev = &tx_ring->adapter->ena_dev;
2231         num_segments = mbuf->nb_segs;
2232         header_len = mbuf->data_len;
2233
2234         if (likely(num_segments < tx_ring->sgl_size))
2235                 return 0;
2236
2237         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2238             (num_segments == tx_ring->sgl_size) &&
2239             (header_len < tx_ring->tx_max_header_size))
2240                 return 0;
2241
2242         rc = rte_pktmbuf_linearize(mbuf);
2243         if (unlikely(rc))
2244                 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
2245
2246         return rc;
2247 }
2248
2249 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2250                                   uint16_t nb_pkts)
2251 {
2252         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2253         uint16_t next_to_use = tx_ring->next_to_use;
2254         uint16_t next_to_clean = tx_ring->next_to_clean;
2255         struct rte_mbuf *mbuf;
2256         uint16_t seg_len;
2257         unsigned int ring_size = tx_ring->ring_size;
2258         unsigned int ring_mask = ring_size - 1;
2259         struct ena_com_tx_ctx ena_tx_ctx;
2260         struct ena_tx_buffer *tx_info;
2261         struct ena_com_buf *ebuf;
2262         uint16_t rc, req_id, total_tx_descs = 0;
2263         uint16_t sent_idx = 0, empty_tx_reqs;
2264         uint16_t push_len = 0;
2265         uint16_t delta = 0;
2266         int nb_hw_desc;
2267
2268         /* Check adapter state */
2269         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2270                 RTE_LOG(ALERT, PMD,
2271                         "Trying to xmit pkts while device is NOT running\n");
2272                 return 0;
2273         }
2274
2275         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2276         if (nb_pkts > empty_tx_reqs)
2277                 nb_pkts = empty_tx_reqs;
2278
2279         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2280                 mbuf = tx_pkts[sent_idx];
2281
2282                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2283                 if (unlikely(rc))
2284                         break;
2285
2286                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2287                 tx_info = &tx_ring->tx_buffer_info[req_id];
2288                 tx_info->mbuf = mbuf;
2289                 tx_info->num_of_bufs = 0;
2290                 ebuf = tx_info->bufs;
2291
2292                 /* Prepare TX context */
2293                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2294                 memset(&ena_tx_ctx.ena_meta, 0x0,
2295                        sizeof(struct ena_com_tx_meta));
2296                 ena_tx_ctx.ena_bufs = ebuf;
2297                 ena_tx_ctx.req_id = req_id;
2298
2299                 delta = 0;
2300                 seg_len = mbuf->data_len;
2301
2302                 if (tx_ring->tx_mem_queue_type ==
2303                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2304                         push_len = RTE_MIN(mbuf->pkt_len,
2305                                            tx_ring->tx_max_header_size);
2306                         ena_tx_ctx.header_len = push_len;
2307
2308                         if (likely(push_len <= seg_len)) {
2309                                 /* If the push header is in the single segment,
2310                                  * then just point it to the 1st mbuf data.
2311                                  */
2312                                 ena_tx_ctx.push_header =
2313                                         rte_pktmbuf_mtod(mbuf, uint8_t *);
2314                         } else {
2315                                 /* If the push header lays in the several
2316                                  * segments, copy it to the intermediate buffer.
2317                                  */
2318                                 rte_pktmbuf_read(mbuf, 0, push_len,
2319                                         tx_ring->push_buf_intermediate_buf);
2320                                 ena_tx_ctx.push_header =
2321                                         tx_ring->push_buf_intermediate_buf;
2322                                 delta = push_len - seg_len;
2323                         }
2324                 } /* there's no else as we take advantage of memset zeroing */
2325
2326                 /* Set TX offloads flags, if applicable */
2327                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2328
2329                 if (unlikely(mbuf->ol_flags &
2330                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2331                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2332
2333                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2334
2335                 /* Process first segment taking into
2336                  * consideration pushed header
2337                  */
2338                 if (seg_len > push_len) {
2339                         ebuf->paddr = mbuf->buf_iova +
2340                                       mbuf->data_off +
2341                                       push_len;
2342                         ebuf->len = seg_len - push_len;
2343                         ebuf++;
2344                         tx_info->num_of_bufs++;
2345                 }
2346
2347                 while ((mbuf = mbuf->next) != NULL) {
2348                         seg_len = mbuf->data_len;
2349
2350                         /* Skip mbufs if whole data is pushed as a header */
2351                         if (unlikely(delta > seg_len)) {
2352                                 delta -= seg_len;
2353                                 continue;
2354                         }
2355
2356                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2357                         ebuf->len = seg_len - delta;
2358                         ebuf++;
2359                         tx_info->num_of_bufs++;
2360
2361                         delta = 0;
2362                 }
2363
2364                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2365
2366                 /* Write data to device */
2367                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2368                                         &ena_tx_ctx, &nb_hw_desc);
2369                 if (unlikely(rc))
2370                         break;
2371
2372                 tx_info->tx_descs = nb_hw_desc;
2373
2374                 next_to_use++;
2375         }
2376
2377         /* If there are ready packets to be xmitted... */
2378         if (sent_idx > 0) {
2379                 /* ...let HW do its best :-) */
2380                 rte_wmb();
2381                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2382
2383                 tx_ring->next_to_use = next_to_use;
2384         }
2385
2386         /* Clear complete packets  */
2387         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2388                 rc = validate_tx_req_id(tx_ring, req_id);
2389                 if (rc)
2390                         break;
2391
2392                 /* Get Tx info & store how many descs were processed  */
2393                 tx_info = &tx_ring->tx_buffer_info[req_id];
2394                 total_tx_descs += tx_info->tx_descs;
2395
2396                 /* Free whole mbuf chain  */
2397                 mbuf = tx_info->mbuf;
2398                 rte_pktmbuf_free(mbuf);
2399                 tx_info->mbuf = NULL;
2400
2401                 /* Put back descriptor to the ring for reuse */
2402                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2403                 next_to_clean++;
2404
2405                 /* If too many descs to clean, leave it for another run */
2406                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2407                         break;
2408         }
2409
2410         if (total_tx_descs > 0) {
2411                 /* acknowledge completion of sent packets */
2412                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2413                 tx_ring->next_to_clean = next_to_clean;
2414         }
2415
2416         return sent_idx;
2417 }
2418
2419 /*********************************************************************
2420  *  PMD configuration
2421  *********************************************************************/
2422 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2423         struct rte_pci_device *pci_dev)
2424 {
2425         return rte_eth_dev_pci_generic_probe(pci_dev,
2426                 sizeof(struct ena_adapter), eth_ena_dev_init);
2427 }
2428
2429 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2430 {
2431         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2432 }
2433
2434 static struct rte_pci_driver rte_ena_pmd = {
2435         .id_table = pci_id_ena_map,
2436         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2437                      RTE_PCI_DRV_WC_ACTIVATE,
2438         .probe = eth_ena_pci_probe,
2439         .remove = eth_ena_pci_remove,
2440 };
2441
2442 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2443 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2444 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2445
2446 RTE_INIT(ena_init_log)
2447 {
2448         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2449         if (ena_logtype_init >= 0)
2450                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2451         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2452         if (ena_logtype_driver >= 0)
2453                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2454 }
2455
2456 /******************************************************************************
2457  ******************************** AENQ Handlers *******************************
2458  *****************************************************************************/
2459 static void ena_update_on_link_change(void *adapter_data,
2460                                       struct ena_admin_aenq_entry *aenq_e)
2461 {
2462         struct rte_eth_dev *eth_dev;
2463         struct ena_adapter *adapter;
2464         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2465         uint32_t status;
2466
2467         adapter = (struct ena_adapter *)adapter_data;
2468         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2469         eth_dev = adapter->rte_dev;
2470
2471         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2472         adapter->link_status = status;
2473
2474         ena_link_update(eth_dev, 0);
2475         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2476 }
2477
2478 static void ena_notification(void *data,
2479                              struct ena_admin_aenq_entry *aenq_e)
2480 {
2481         struct ena_adapter *adapter = (struct ena_adapter *)data;
2482         struct ena_admin_ena_hw_hints *hints;
2483
2484         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2485                 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2486                         aenq_e->aenq_common_desc.group,
2487                         ENA_ADMIN_NOTIFICATION);
2488
2489         switch (aenq_e->aenq_common_desc.syndrom) {
2490         case ENA_ADMIN_UPDATE_HINTS:
2491                 hints = (struct ena_admin_ena_hw_hints *)
2492                         (&aenq_e->inline_data_w4);
2493                 ena_update_hints(adapter, hints);
2494                 break;
2495         default:
2496                 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2497                         aenq_e->aenq_common_desc.syndrom);
2498         }
2499 }
2500
2501 static void ena_keep_alive(void *adapter_data,
2502                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2503 {
2504         struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2505
2506         adapter->timestamp_wd = rte_get_timer_cycles();
2507 }
2508
2509 /**
2510  * This handler will called for unknown event group or unimplemented handlers
2511  **/
2512 static void unimplemented_aenq_handler(__rte_unused void *data,
2513                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2514 {
2515         RTE_LOG(ERR, PMD, "Unknown event was received or event with "
2516                           "unimplemented handler\n");
2517 }
2518
2519 static struct ena_aenq_handlers aenq_handlers = {
2520         .handlers = {
2521                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2522                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2523                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2524         },
2525         .unimplemented_handler = unimplemented_aenq_handler
2526 };