drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_errno.h>
   8 #include <rte_version.h>
   9 #include <rte_net.h>
  10 #include <rte_kvargs.h>
  11
  12 #include "ena_ethdev.h"
  13 #include "ena_logs.h"
  14 #include "ena_platform.h"
  15 #include "ena_com.h"
  16 #include "ena_eth_com.h"
  17
  18 #include <ena_common_defs.h>
  19 #include <ena_regs_defs.h>
  20 #include <ena_admin_defs.h>
  21 #include <ena_eth_io_defs.h>
  22
  23 #define DRV_MODULE_VER_MAJOR    2
  24 #define DRV_MODULE_VER_MINOR    4
  25 #define DRV_MODULE_VER_SUBMINOR 0
  26
  27 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  28
  29 #define GET_L4_HDR_LEN(mbuf)                                    \
  30         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  31                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  32
  33 #define ETH_GSTRING_LEN 32
  34
  35 #define ARRAY_SIZE(x) RTE_DIM(x)
  36
  37 #define ENA_MIN_RING_DESC       128
  38
  39 #define ENA_PTYPE_HAS_HASH      (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP)
  40
  41 enum ethtool_stringset {
  42         ETH_SS_TEST             = 0,
  43         ETH_SS_STATS,
  44 };
  45
  46 struct ena_stats {
  47         char name[ETH_GSTRING_LEN];
  48         int stat_offset;
  49 };
  50
  51 #define ENA_STAT_ENTRY(stat, stat_type) { \
  52         .name = #stat, \
  53         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  54 }
  55
  56 #define ENA_STAT_RX_ENTRY(stat) \
  57         ENA_STAT_ENTRY(stat, rx)
  58
  59 #define ENA_STAT_TX_ENTRY(stat) \
  60         ENA_STAT_ENTRY(stat, tx)
  61
  62 #define ENA_STAT_ENI_ENTRY(stat) \
  63         ENA_STAT_ENTRY(stat, eni)
  64
  65 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  66         ENA_STAT_ENTRY(stat, dev)
  67
  68 /* Device arguments */
  69 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  70
  71 /*
  72  * Each rte_memzone should have unique name.
  73  * To satisfy it, count number of allocation and add it to name.
  74  */
  75 rte_atomic64_t ena_alloc_cnt;
  76
  77 static const struct ena_stats ena_stats_global_strings[] = {
  78         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  79         ENA_STAT_GLOBAL_ENTRY(dev_start),
  80         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  81         ENA_STAT_GLOBAL_ENTRY(tx_drops),
  82 };
  83
  84 static const struct ena_stats ena_stats_eni_strings[] = {
  85         ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
  86         ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
  87         ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
  88         ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
  89         ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
  90 };
  91
  92 static const struct ena_stats ena_stats_tx_strings[] = {
  93         ENA_STAT_TX_ENTRY(cnt),
  94         ENA_STAT_TX_ENTRY(bytes),
  95         ENA_STAT_TX_ENTRY(prepare_ctx_err),
  96         ENA_STAT_TX_ENTRY(linearize),
  97         ENA_STAT_TX_ENTRY(linearize_failed),
  98         ENA_STAT_TX_ENTRY(tx_poll),
  99         ENA_STAT_TX_ENTRY(doorbells),
 100         ENA_STAT_TX_ENTRY(bad_req_id),
 101         ENA_STAT_TX_ENTRY(available_desc),
 102 };
 103
 104 static const struct ena_stats ena_stats_rx_strings[] = {
 105         ENA_STAT_RX_ENTRY(cnt),
 106         ENA_STAT_RX_ENTRY(bytes),
 107         ENA_STAT_RX_ENTRY(refill_partial),
 108         ENA_STAT_RX_ENTRY(bad_csum),
 109         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 110         ENA_STAT_RX_ENTRY(bad_desc_num),
 111         ENA_STAT_RX_ENTRY(bad_req_id),
 112 };
 113
 114 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 115 #define ENA_STATS_ARRAY_ENI     ARRAY_SIZE(ena_stats_eni_strings)
 116 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 117 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 118
 119 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 120                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 121                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 122                         DEV_TX_OFFLOAD_TCP_TSO)
 123 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 124                        PKT_TX_IP_CKSUM |\
 125                        PKT_TX_TCP_SEG)
 126
 127 /** Vendor ID used by Amazon devices */
 128 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 129 /** Amazon devices */
 130 #define PCI_DEVICE_ID_ENA_VF            0xEC20
 131 #define PCI_DEVICE_ID_ENA_VF_RSERV0     0xEC21
 132
 133 #define ENA_TX_OFFLOAD_MASK     (\
 134         PKT_TX_L4_MASK |         \
 135         PKT_TX_IPV6 |            \
 136         PKT_TX_IPV4 |            \
 137         PKT_TX_IP_CKSUM |        \
 138         PKT_TX_TCP_SEG)
 139
 140 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 141         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 142
 143 /** HW specific offloads capabilities. */
 144 /* IPv4 checksum offload. */
 145 #define ENA_L3_IPV4_CSUM                0x0001
 146 /* TCP/UDP checksum offload for IPv4 packets. */
 147 #define ENA_L4_IPV4_CSUM                0x0002
 148 /* TCP/UDP checksum offload for IPv4 packets with pseudo header checksum. */
 149 #define ENA_L4_IPV4_CSUM_PARTIAL        0x0004
 150 /* TCP/UDP checksum offload for IPv6 packets. */
 151 #define ENA_L4_IPV6_CSUM                0x0008
 152 /* TCP/UDP checksum offload for IPv6 packets with pseudo header checksum. */
 153 #define ENA_L4_IPV6_CSUM_PARTIAL        0x0010
 154 /* TSO support for IPv4 packets. */
 155 #define ENA_IPV4_TSO                    0x0020
 156
 157 /* Device supports setting RSS hash. */
 158 #define ENA_RX_RSS_HASH                 0x0040
 159
 160 static const struct rte_pci_id pci_id_ena_map[] = {
 161         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 162         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
 163         { .device_id = 0 },
 164 };
 165
 166 static struct ena_aenq_handlers aenq_handlers;
 167
 168 static int ena_device_init(struct ena_com_dev *ena_dev,
 169                            struct rte_pci_device *pdev,
 170                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 171                            bool *wd_state);
 172 static int ena_dev_configure(struct rte_eth_dev *dev);
 173 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
 174         struct ena_tx_buffer *tx_info,
 175         struct rte_mbuf *mbuf,
 176         void **push_header,
 177         uint16_t *header_len);
 178 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
 179 static void ena_tx_cleanup(struct ena_ring *tx_ring);
 180 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 181                                   uint16_t nb_pkts);
 182 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 183                 uint16_t nb_pkts);
 184 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 185                               uint16_t nb_desc, unsigned int socket_id,
 186                               const struct rte_eth_txconf *tx_conf);
 187 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 188                               uint16_t nb_desc, unsigned int socket_id,
 189                               const struct rte_eth_rxconf *rx_conf,
 190                               struct rte_mempool *mp);
 191 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
 192 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
 193                                     struct ena_com_rx_buf_info *ena_bufs,
 194                                     uint32_t descs,
 195                                     uint16_t *next_to_clean,
 196                                     uint8_t offset);
 197 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 198                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 199 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
 200                                   struct rte_mbuf *mbuf, uint16_t id);
 201 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 202 static void ena_init_rings(struct ena_adapter *adapter,
 203                            bool disable_meta_caching);
 204 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 205 static int ena_start(struct rte_eth_dev *dev);
 206 static int ena_stop(struct rte_eth_dev *dev);
 207 static int ena_close(struct rte_eth_dev *dev);
 208 static int ena_dev_reset(struct rte_eth_dev *dev);
 209 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 210 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 211 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 212 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 213 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 214 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 215 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 216 static int ena_link_update(struct rte_eth_dev *dev,
 217                            int wait_to_complete);
 218 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring);
 219 static void ena_queue_stop(struct ena_ring *ring);
 220 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 221                               enum ena_ring_type ring_type);
 222 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring);
 223 static int ena_queue_start_all(struct rte_eth_dev *dev,
 224                                enum ena_ring_type ring_type);
 225 static void ena_stats_restart(struct rte_eth_dev *dev);
 226 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter);
 227 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter);
 228 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter);
 229 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter);
 230 static int ena_infos_get(struct rte_eth_dev *dev,
 231                          struct rte_eth_dev_info *dev_info);
 232 static void ena_interrupt_handler_rte(void *cb_arg);
 233 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 234 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 235 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 236 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 237                                 struct rte_eth_xstat_name *xstats_names,
 238                                 unsigned int n);
 239 static int ena_xstats_get(struct rte_eth_dev *dev,
 240                           struct rte_eth_xstat *stats,
 241                           unsigned int n);
 242 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 243                                 const uint64_t *ids,
 244                                 uint64_t *values,
 245                                 unsigned int n);
 246 static int ena_process_bool_devarg(const char *key,
 247                                    const char *value,
 248                                    void *opaque);
 249 static int ena_parse_devargs(struct ena_adapter *adapter,
 250                              struct rte_devargs *devargs);
 251 static int ena_copy_eni_stats(struct ena_adapter *adapter);
 252 static int ena_setup_rx_intr(struct rte_eth_dev *dev);
 253 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
 254                                     uint16_t queue_id);
 255 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
 256                                      uint16_t queue_id);
 257
 258 static const struct eth_dev_ops ena_dev_ops = {
 259         .dev_configure        = ena_dev_configure,
 260         .dev_infos_get        = ena_infos_get,
 261         .rx_queue_setup       = ena_rx_queue_setup,
 262         .tx_queue_setup       = ena_tx_queue_setup,
 263         .dev_start            = ena_start,
 264         .dev_stop             = ena_stop,
 265         .link_update          = ena_link_update,
 266         .stats_get            = ena_stats_get,
 267         .xstats_get_names     = ena_xstats_get_names,
 268         .xstats_get           = ena_xstats_get,
 269         .xstats_get_by_id     = ena_xstats_get_by_id,
 270         .mtu_set              = ena_mtu_set,
 271         .rx_queue_release     = ena_rx_queue_release,
 272         .tx_queue_release     = ena_tx_queue_release,
 273         .dev_close            = ena_close,
 274         .dev_reset            = ena_dev_reset,
 275         .reta_update          = ena_rss_reta_update,
 276         .reta_query           = ena_rss_reta_query,
 277         .rx_queue_intr_enable = ena_rx_queue_intr_enable,
 278         .rx_queue_intr_disable = ena_rx_queue_intr_disable,
 279         .rss_hash_update      = ena_rss_hash_update,
 280         .rss_hash_conf_get    = ena_rss_hash_conf_get,
 281 };
 282
 283 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 284                                        struct ena_com_rx_ctx *ena_rx_ctx,
 285                                        bool fill_hash)
 286 {
 287         uint64_t ol_flags = 0;
 288         uint32_t packet_type = 0;
 289
 290         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 291                 packet_type |= RTE_PTYPE_L4_TCP;
 292         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 293                 packet_type |= RTE_PTYPE_L4_UDP;
 294
 295         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
 296                 packet_type |= RTE_PTYPE_L3_IPV4;
 297                 if (unlikely(ena_rx_ctx->l3_csum_err))
 298                         ol_flags |= PKT_RX_IP_CKSUM_BAD;
 299                 else
 300                         ol_flags |= PKT_RX_IP_CKSUM_GOOD;
 301         } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
 302                 packet_type |= RTE_PTYPE_L3_IPV6;
 303         }
 304
 305         if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag)
 306                 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 307         else
 308                 if (unlikely(ena_rx_ctx->l4_csum_err))
 309                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
 310                 else
 311                         ol_flags |= PKT_RX_L4_CKSUM_GOOD;
 312
 313         if (fill_hash &&
 314             likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) {
 315                 ol_flags |= PKT_RX_RSS_HASH;
 316                 mbuf->hash.rss = ena_rx_ctx->hash;
 317         }
 318
 319         mbuf->ol_flags = ol_flags;
 320         mbuf->packet_type = packet_type;
 321 }
 322
 323 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 324                                        struct ena_com_tx_ctx *ena_tx_ctx,
 325                                        uint64_t queue_offloads,
 326                                        bool disable_meta_caching)
 327 {
 328         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 329
 330         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 331             (queue_offloads & QUEUE_OFFLOADS)) {
 332                 /* check if TSO is required */
 333                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 334                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 335                         ena_tx_ctx->tso_enable = true;
 336
 337                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 338                 }
 339
 340                 /* check if L3 checksum is needed */
 341                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 342                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 343                         ena_tx_ctx->l3_csum_enable = true;
 344
 345                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 346                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 347                 } else {
 348                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 349
 350                         /* set don't fragment (DF) flag */
 351                         if (mbuf->packet_type &
 352                                 (RTE_PTYPE_L4_NONFRAG
 353                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 354                                 ena_tx_ctx->df = true;
 355                 }
 356
 357                 /* check if L4 checksum is needed */
 358                 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
 359                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 360                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 361                         ena_tx_ctx->l4_csum_enable = true;
 362                 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
 363                                 PKT_TX_UDP_CKSUM) &&
 364                                 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 365                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 366                         ena_tx_ctx->l4_csum_enable = true;
 367                 } else {
 368                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 369                         ena_tx_ctx->l4_csum_enable = false;
 370                 }
 371
 372                 ena_meta->mss = mbuf->tso_segsz;
 373                 ena_meta->l3_hdr_len = mbuf->l3_len;
 374                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 375
 376                 ena_tx_ctx->meta_valid = true;
 377         } else if (disable_meta_caching) {
 378                 memset(ena_meta, 0, sizeof(*ena_meta));
 379                 ena_tx_ctx->meta_valid = true;
 380         } else {
 381                 ena_tx_ctx->meta_valid = false;
 382         }
 383 }
 384
 385 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 386 {
 387         struct ena_tx_buffer *tx_info = NULL;
 388
 389         if (likely(req_id < tx_ring->ring_size)) {
 390                 tx_info = &tx_ring->tx_buffer_info[req_id];
 391                 if (likely(tx_info->mbuf))
 392                         return 0;
 393         }
 394
 395         if (tx_info)
 396                 PMD_TX_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 397         else
 398                 PMD_TX_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 399
 400         /* Trigger device reset */
 401         ++tx_ring->tx_stats.bad_req_id;
 402         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 403         tx_ring->adapter->trigger_reset = true;
 404         return -EFAULT;
 405 }
 406
 407 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 408 {
 409         struct ena_admin_host_info *host_info;
 410         int rc;
 411
 412         /* Allocate only the host info */
 413         rc = ena_com_allocate_host_info(ena_dev);
 414         if (rc) {
 415                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 416                 return;
 417         }
 418
 419         host_info = ena_dev->host_attr.host_info;
 420
 421         host_info->os_type = ENA_ADMIN_OS_DPDK;
 422         host_info->kernel_ver = RTE_VERSION;
 423         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 424                 sizeof(host_info->kernel_ver_str));
 425         host_info->os_dist = RTE_VERSION;
 426         strlcpy((char *)host_info->os_dist_str, rte_version(),
 427                 sizeof(host_info->os_dist_str));
 428         host_info->driver_version =
 429                 (DRV_MODULE_VER_MAJOR) |
 430                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 431                 (DRV_MODULE_VER_SUBMINOR <<
 432                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 433         host_info->num_cpus = rte_lcore_count();
 434
 435         host_info->driver_supported_features =
 436                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK |
 437                 ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
 438
 439         rc = ena_com_set_host_attributes(ena_dev);
 440         if (rc) {
 441                 if (rc == -ENA_COM_UNSUPPORTED)
 442                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 443                 else
 444                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 445
 446                 goto err;
 447         }
 448
 449         return;
 450
 451 err:
 452         ena_com_delete_host_info(ena_dev);
 453 }
 454
 455 /* This function calculates the number of xstats based on the current config */
 456 static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data)
 457 {
 458         return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
 459                 (data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 460                 (data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 461 }
 462
 463 static void ena_config_debug_area(struct ena_adapter *adapter)
 464 {
 465         u32 debug_area_size;
 466         int rc, ss_count;
 467
 468         ss_count = ena_xstats_calc_num(adapter->edev_data);
 469
 470         /* allocate 32 bytes for each string and 64bit for the value */
 471         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 472
 473         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 474         if (rc) {
 475                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 476                 return;
 477         }
 478
 479         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 480         if (rc) {
 481                 if (rc == -ENA_COM_UNSUPPORTED)
 482                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 483                 else
 484                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 485
 486                 goto err;
 487         }
 488
 489         return;
 490 err:
 491         ena_com_delete_debug_area(&adapter->ena_dev);
 492 }
 493
 494 static int ena_close(struct rte_eth_dev *dev)
 495 {
 496         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 497         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 498         struct ena_adapter *adapter = dev->data->dev_private;
 499         int ret = 0;
 500
 501         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 502                 return 0;
 503
 504         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 505                 ret = ena_stop(dev);
 506         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 507
 508         ena_rx_queue_release_all(dev);
 509         ena_tx_queue_release_all(dev);
 510
 511         rte_free(adapter->drv_stats);
 512         adapter->drv_stats = NULL;
 513
 514         rte_intr_disable(intr_handle);
 515         rte_intr_callback_unregister(intr_handle,
 516                                      ena_interrupt_handler_rte,
 517                                      dev);
 518
 519         /*
 520          * MAC is not allocated dynamically. Setting NULL should prevent from
 521          * release of the resource in the rte_eth_dev_release_port().
 522          */
 523         dev->data->mac_addrs = NULL;
 524
 525         return ret;
 526 }
 527
 528 static int
 529 ena_dev_reset(struct rte_eth_dev *dev)
 530 {
 531         int rc = 0;
 532
 533         /* Cannot release memory in secondary process */
 534         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 535                 PMD_DRV_LOG(WARNING, "dev_reset not supported in secondary.\n");
 536                 return -EPERM;
 537         }
 538
 539         ena_destroy_device(dev);
 540         rc = eth_ena_dev_init(dev);
 541         if (rc)
 542                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 543
 544         return rc;
 545 }
 546
 547 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 548 {
 549         int nb_queues = dev->data->nb_rx_queues;
 550         int i;
 551
 552         for (i = 0; i < nb_queues; i++)
 553                 ena_rx_queue_release(dev, i);
 554 }
 555
 556 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 557 {
 558         int nb_queues = dev->data->nb_tx_queues;
 559         int i;
 560
 561         for (i = 0; i < nb_queues; i++)
 562                 ena_tx_queue_release(dev, i);
 563 }
 564
 565 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 566 {
 567         struct ena_ring *ring = dev->data->rx_queues[qid];
 568
 569         /* Free ring resources */
 570         if (ring->rx_buffer_info)
 571                 rte_free(ring->rx_buffer_info);
 572         ring->rx_buffer_info = NULL;
 573
 574         if (ring->rx_refill_buffer)
 575                 rte_free(ring->rx_refill_buffer);
 576         ring->rx_refill_buffer = NULL;
 577
 578         if (ring->empty_rx_reqs)
 579                 rte_free(ring->empty_rx_reqs);
 580         ring->empty_rx_reqs = NULL;
 581
 582         ring->configured = 0;
 583
 584         PMD_DRV_LOG(NOTICE, "Rx queue %d:%d released\n",
 585                 ring->port_id, ring->id);
 586 }
 587
 588 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 589 {
 590         struct ena_ring *ring = dev->data->tx_queues[qid];
 591
 592         /* Free ring resources */
 593         if (ring->push_buf_intermediate_buf)
 594                 rte_free(ring->push_buf_intermediate_buf);
 595
 596         if (ring->tx_buffer_info)
 597                 rte_free(ring->tx_buffer_info);
 598
 599         if (ring->empty_tx_reqs)
 600                 rte_free(ring->empty_tx_reqs);
 601
 602         ring->empty_tx_reqs = NULL;
 603         ring->tx_buffer_info = NULL;
 604         ring->push_buf_intermediate_buf = NULL;
 605
 606         ring->configured = 0;
 607
 608         PMD_DRV_LOG(NOTICE, "Tx queue %d:%d released\n",
 609                 ring->port_id, ring->id);
 610 }
 611
 612 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 613 {
 614         unsigned int i;
 615
 616         for (i = 0; i < ring->ring_size; ++i) {
 617                 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
 618                 if (rx_info->mbuf) {
 619                         rte_mbuf_raw_free(rx_info->mbuf);
 620                         rx_info->mbuf = NULL;
 621                 }
 622         }
 623 }
 624
 625 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 626 {
 627         unsigned int i;
 628
 629         for (i = 0; i < ring->ring_size; ++i) {
 630                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 631
 632                 if (tx_buf->mbuf) {
 633                         rte_pktmbuf_free(tx_buf->mbuf);
 634                         tx_buf->mbuf = NULL;
 635                 }
 636         }
 637 }
 638
 639 static int ena_link_update(struct rte_eth_dev *dev,
 640                            __rte_unused int wait_to_complete)
 641 {
 642         struct rte_eth_link *link = &dev->data->dev_link;
 643         struct ena_adapter *adapter = dev->data->dev_private;
 644
 645         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 646         link->link_speed = ETH_SPEED_NUM_NONE;
 647         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 648
 649         return 0;
 650 }
 651
 652 static int ena_queue_start_all(struct rte_eth_dev *dev,
 653                                enum ena_ring_type ring_type)
 654 {
 655         struct ena_adapter *adapter = dev->data->dev_private;
 656         struct ena_ring *queues = NULL;
 657         int nb_queues;
 658         int i = 0;
 659         int rc = 0;
 660
 661         if (ring_type == ENA_RING_TYPE_RX) {
 662                 queues = adapter->rx_ring;
 663                 nb_queues = dev->data->nb_rx_queues;
 664         } else {
 665                 queues = adapter->tx_ring;
 666                 nb_queues = dev->data->nb_tx_queues;
 667         }
 668         for (i = 0; i < nb_queues; i++) {
 669                 if (queues[i].configured) {
 670                         if (ring_type == ENA_RING_TYPE_RX) {
 671                                 ena_assert_msg(
 672                                         dev->data->rx_queues[i] == &queues[i],
 673                                         "Inconsistent state of Rx queues\n");
 674                         } else {
 675                                 ena_assert_msg(
 676                                         dev->data->tx_queues[i] == &queues[i],
 677                                         "Inconsistent state of Tx queues\n");
 678                         }
 679
 680                         rc = ena_queue_start(dev, &queues[i]);
 681
 682                         if (rc) {
 683                                 PMD_INIT_LOG(ERR,
 684                                         "Failed to start queue[%d] of type(%d)\n",
 685                                         i, ring_type);
 686                                 goto err;
 687                         }
 688                 }
 689         }
 690
 691         return 0;
 692
 693 err:
 694         while (i--)
 695                 if (queues[i].configured)
 696                         ena_queue_stop(&queues[i]);
 697
 698         return rc;
 699 }
 700
 701 static int ena_check_valid_conf(struct ena_adapter *adapter)
 702 {
 703         uint32_t mtu = adapter->edev_data->mtu;
 704
 705         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
 706                 PMD_INIT_LOG(ERR,
 707                         "Unsupported MTU of %d. Max MTU: %d, min MTU: %d\n",
 708                         mtu, adapter->max_mtu, ENA_MIN_MTU);
 709                 return ENA_COM_UNSUPPORTED;
 710         }
 711
 712         return 0;
 713 }
 714
 715 static int
 716 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 717                        bool use_large_llq_hdr)
 718 {
 719         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 720         struct ena_com_dev *ena_dev = ctx->ena_dev;
 721         uint32_t max_tx_queue_size;
 722         uint32_t max_rx_queue_size;
 723
 724         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 725                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 726                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 727                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 728                         max_queue_ext->max_rx_sq_depth);
 729                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
 730
 731                 if (ena_dev->tx_mem_queue_type ==
 732                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 733                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 734                                 llq->max_llq_depth);
 735                 } else {
 736                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 737                                 max_queue_ext->max_tx_sq_depth);
 738                 }
 739
 740                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 741                         max_queue_ext->max_per_packet_rx_descs);
 742                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 743                         max_queue_ext->max_per_packet_tx_descs);
 744         } else {
 745                 struct ena_admin_queue_feature_desc *max_queues =
 746                         &ctx->get_feat_ctx->max_queues;
 747                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
 748                         max_queues->max_sq_depth);
 749                 max_tx_queue_size = max_queues->max_cq_depth;
 750
 751                 if (ena_dev->tx_mem_queue_type ==
 752                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 753                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 754                                 llq->max_llq_depth);
 755                 } else {
 756                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 757                                 max_queues->max_sq_depth);
 758                 }
 759
 760                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 761                         max_queues->max_packet_rx_descs);
 762                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 763                         max_queues->max_packet_tx_descs);
 764         }
 765
 766         /* Round down to the nearest power of 2 */
 767         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
 768         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
 769
 770         if (use_large_llq_hdr) {
 771                 if ((llq->entry_size_ctrl_supported &
 772                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
 773                     (ena_dev->tx_mem_queue_type ==
 774                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
 775                         max_tx_queue_size /= 2;
 776                         PMD_INIT_LOG(INFO,
 777                                 "Forcing large headers and decreasing maximum Tx queue size to %d\n",
 778                                 max_tx_queue_size);
 779                 } else {
 780                         PMD_INIT_LOG(ERR,
 781                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
 782                 }
 783         }
 784
 785         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
 786                 PMD_INIT_LOG(ERR, "Invalid queue size\n");
 787                 return -EFAULT;
 788         }
 789
 790         ctx->max_tx_queue_size = max_tx_queue_size;
 791         ctx->max_rx_queue_size = max_rx_queue_size;
 792
 793         return 0;
 794 }
 795
 796 static void ena_stats_restart(struct rte_eth_dev *dev)
 797 {
 798         struct ena_adapter *adapter = dev->data->dev_private;
 799
 800         rte_atomic64_init(&adapter->drv_stats->ierrors);
 801         rte_atomic64_init(&adapter->drv_stats->oerrors);
 802         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 803         adapter->drv_stats->rx_drops = 0;
 804 }
 805
 806 static int ena_stats_get(struct rte_eth_dev *dev,
 807                           struct rte_eth_stats *stats)
 808 {
 809         struct ena_admin_basic_stats ena_stats;
 810         struct ena_adapter *adapter = dev->data->dev_private;
 811         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 812         int rc;
 813         int i;
 814         int max_rings_stats;
 815
 816         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 817                 return -ENOTSUP;
 818
 819         memset(&ena_stats, 0, sizeof(ena_stats));
 820
 821         rte_spinlock_lock(&adapter->admin_lock);
 822         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 823         rte_spinlock_unlock(&adapter->admin_lock);
 824         if (unlikely(rc)) {
 825                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 826                 return rc;
 827         }
 828
 829         /* Set of basic statistics from ENA */
 830         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 831                                           ena_stats.rx_pkts_low);
 832         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 833                                           ena_stats.tx_pkts_low);
 834         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 835                                         ena_stats.rx_bytes_low);
 836         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 837                                         ena_stats.tx_bytes_low);
 838
 839         /* Driver related stats */
 840         stats->imissed = adapter->drv_stats->rx_drops;
 841         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 842         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 843         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 844
 845         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
 846                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 847         for (i = 0; i < max_rings_stats; ++i) {
 848                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
 849
 850                 stats->q_ibytes[i] = rx_stats->bytes;
 851                 stats->q_ipackets[i] = rx_stats->cnt;
 852                 stats->q_errors[i] = rx_stats->bad_desc_num +
 853                         rx_stats->bad_req_id;
 854         }
 855
 856         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
 857                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 858         for (i = 0; i < max_rings_stats; ++i) {
 859                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
 860
 861                 stats->q_obytes[i] = tx_stats->bytes;
 862                 stats->q_opackets[i] = tx_stats->cnt;
 863         }
 864
 865         return 0;
 866 }
 867
 868 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 869 {
 870         struct ena_adapter *adapter;
 871         struct ena_com_dev *ena_dev;
 872         int rc = 0;
 873
 874         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
 875         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
 876         adapter = dev->data->dev_private;
 877
 878         ena_dev = &adapter->ena_dev;
 879         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
 880
 881         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
 882                 PMD_DRV_LOG(ERR,
 883                         "Invalid MTU setting. New MTU: %d, max MTU: %d, min MTU: %d\n",
 884                         mtu, adapter->max_mtu, ENA_MIN_MTU);
 885                 return -EINVAL;
 886         }
 887
 888         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 889         if (rc)
 890                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
 891         else
 892                 PMD_DRV_LOG(NOTICE, "MTU set to: %d\n", mtu);
 893
 894         return rc;
 895 }
 896
 897 static int ena_start(struct rte_eth_dev *dev)
 898 {
 899         struct ena_adapter *adapter = dev->data->dev_private;
 900         uint64_t ticks;
 901         int rc = 0;
 902
 903         /* Cannot allocate memory in secondary process */
 904         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 905                 PMD_DRV_LOG(WARNING, "dev_start not supported in secondary.\n");
 906                 return -EPERM;
 907         }
 908
 909         rc = ena_check_valid_conf(adapter);
 910         if (rc)
 911                 return rc;
 912
 913         rc = ena_setup_rx_intr(dev);
 914         if (rc)
 915                 return rc;
 916
 917         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
 918         if (rc)
 919                 return rc;
 920
 921         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
 922         if (rc)
 923                 goto err_start_tx;
 924
 925         if (adapter->edev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
 926                 rc = ena_rss_configure(adapter);
 927                 if (rc)
 928                         goto err_rss_init;
 929         }
 930
 931         ena_stats_restart(dev);
 932
 933         adapter->timestamp_wd = rte_get_timer_cycles();
 934         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
 935
 936         ticks = rte_get_timer_hz();
 937         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
 938                         ena_timer_wd_callback, dev);
 939
 940         ++adapter->dev_stats.dev_start;
 941         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 942
 943         return 0;
 944
 945 err_rss_init:
 946         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
 947 err_start_tx:
 948         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
 949         return rc;
 950 }
 951
 952 static int ena_stop(struct rte_eth_dev *dev)
 953 {
 954         struct ena_adapter *adapter = dev->data->dev_private;
 955         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 956         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 957         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 958         int rc;
 959
 960         /* Cannot free memory in secondary process */
 961         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 962                 PMD_DRV_LOG(WARNING, "dev_stop not supported in secondary.\n");
 963                 return -EPERM;
 964         }
 965
 966         rte_timer_stop_sync(&adapter->timer_wd);
 967         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
 968         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
 969
 970         if (adapter->trigger_reset) {
 971                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
 972                 if (rc)
 973                         PMD_DRV_LOG(ERR, "Device reset failed, rc: %d\n", rc);
 974         }
 975
 976         rte_intr_disable(intr_handle);
 977
 978         rte_intr_efd_disable(intr_handle);
 979         if (intr_handle->intr_vec != NULL) {
 980                 rte_free(intr_handle->intr_vec);
 981                 intr_handle->intr_vec = NULL;
 982         }
 983
 984         rte_intr_enable(intr_handle);
 985
 986         ++adapter->dev_stats.dev_stop;
 987         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 988         dev->data->dev_started = 0;
 989
 990         return 0;
 991 }
 992
 993 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring)
 994 {
 995         struct ena_adapter *adapter = ring->adapter;
 996         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 997         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 998         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 999         struct ena_com_create_io_ctx ctx =
1000                 /* policy set to _HOST just to satisfy icc compiler */
1001                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1002                   0, 0, 0, 0, 0 };
1003         uint16_t ena_qid;
1004         unsigned int i;
1005         int rc;
1006
1007         ctx.msix_vector = -1;
1008         if (ring->type == ENA_RING_TYPE_TX) {
1009                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1010                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1011                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1012                 for (i = 0; i < ring->ring_size; i++)
1013                         ring->empty_tx_reqs[i] = i;
1014         } else {
1015                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1016                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1017                 if (rte_intr_dp_is_en(intr_handle))
1018                         ctx.msix_vector = intr_handle->intr_vec[ring->id];
1019                 for (i = 0; i < ring->ring_size; i++)
1020                         ring->empty_rx_reqs[i] = i;
1021         }
1022         ctx.queue_size = ring->ring_size;
1023         ctx.qid = ena_qid;
1024         ctx.numa_node = ring->numa_socket_id;
1025
1026         rc = ena_com_create_io_queue(ena_dev, &ctx);
1027         if (rc) {
1028                 PMD_DRV_LOG(ERR,
1029                         "Failed to create IO queue[%d] (qid:%d), rc: %d\n",
1030                         ring->id, ena_qid, rc);
1031                 return rc;
1032         }
1033
1034         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1035                                      &ring->ena_com_io_sq,
1036                                      &ring->ena_com_io_cq);
1037         if (rc) {
1038                 PMD_DRV_LOG(ERR,
1039                         "Failed to get IO queue[%d] handlers, rc: %d\n",
1040                         ring->id, rc);
1041                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1042                 return rc;
1043         }
1044
1045         if (ring->type == ENA_RING_TYPE_TX)
1046                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1047
1048         /* Start with Rx interrupts being masked. */
1049         if (ring->type == ENA_RING_TYPE_RX && rte_intr_dp_is_en(intr_handle))
1050                 ena_rx_queue_intr_disable(dev, ring->id);
1051
1052         return 0;
1053 }
1054
1055 static void ena_queue_stop(struct ena_ring *ring)
1056 {
1057         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1058
1059         if (ring->type == ENA_RING_TYPE_RX) {
1060                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1061                 ena_rx_queue_release_bufs(ring);
1062         } else {
1063                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1064                 ena_tx_queue_release_bufs(ring);
1065         }
1066 }
1067
1068 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1069                               enum ena_ring_type ring_type)
1070 {
1071         struct ena_adapter *adapter = dev->data->dev_private;
1072         struct ena_ring *queues = NULL;
1073         uint16_t nb_queues, i;
1074
1075         if (ring_type == ENA_RING_TYPE_RX) {
1076                 queues = adapter->rx_ring;
1077                 nb_queues = dev->data->nb_rx_queues;
1078         } else {
1079                 queues = adapter->tx_ring;
1080                 nb_queues = dev->data->nb_tx_queues;
1081         }
1082
1083         for (i = 0; i < nb_queues; ++i)
1084                 if (queues[i].configured)
1085                         ena_queue_stop(&queues[i]);
1086 }
1087
1088 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring)
1089 {
1090         int rc, bufs_num;
1091
1092         ena_assert_msg(ring->configured == 1,
1093                        "Trying to start unconfigured queue\n");
1094
1095         rc = ena_create_io_queue(dev, ring);
1096         if (rc) {
1097                 PMD_INIT_LOG(ERR, "Failed to create IO queue\n");
1098                 return rc;
1099         }
1100
1101         ring->next_to_clean = 0;
1102         ring->next_to_use = 0;
1103
1104         if (ring->type == ENA_RING_TYPE_TX) {
1105                 ring->tx_stats.available_desc =
1106                         ena_com_free_q_entries(ring->ena_com_io_sq);
1107                 return 0;
1108         }
1109
1110         bufs_num = ring->ring_size - 1;
1111         rc = ena_populate_rx_queue(ring, bufs_num);
1112         if (rc != bufs_num) {
1113                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1114                                          ENA_IO_RXQ_IDX(ring->id));
1115                 PMD_INIT_LOG(ERR, "Failed to populate Rx ring\n");
1116                 return ENA_COM_FAULT;
1117         }
1118         /* Flush per-core RX buffers pools cache as they can be used on other
1119          * cores as well.
1120          */
1121         rte_mempool_cache_flush(NULL, ring->mb_pool);
1122
1123         return 0;
1124 }
1125
1126 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1127                               uint16_t queue_idx,
1128                               uint16_t nb_desc,
1129                               unsigned int socket_id,
1130                               const struct rte_eth_txconf *tx_conf)
1131 {
1132         struct ena_ring *txq = NULL;
1133         struct ena_adapter *adapter = dev->data->dev_private;
1134         unsigned int i;
1135         uint16_t dyn_thresh;
1136
1137         txq = &adapter->tx_ring[queue_idx];
1138
1139         if (txq->configured) {
1140                 PMD_DRV_LOG(CRIT,
1141                         "API violation. Queue[%d] is already configured\n",
1142                         queue_idx);
1143                 return ENA_COM_FAULT;
1144         }
1145
1146         if (!rte_is_power_of_2(nb_desc)) {
1147                 PMD_DRV_LOG(ERR,
1148                         "Unsupported size of Tx queue: %d is not a power of 2.\n",
1149                         nb_desc);
1150                 return -EINVAL;
1151         }
1152
1153         if (nb_desc > adapter->max_tx_ring_size) {
1154                 PMD_DRV_LOG(ERR,
1155                         "Unsupported size of Tx queue (max size: %d)\n",
1156                         adapter->max_tx_ring_size);
1157                 return -EINVAL;
1158         }
1159
1160         txq->port_id = dev->data->port_id;
1161         txq->next_to_clean = 0;
1162         txq->next_to_use = 0;
1163         txq->ring_size = nb_desc;
1164         txq->size_mask = nb_desc - 1;
1165         txq->numa_socket_id = socket_id;
1166         txq->pkts_without_db = false;
1167
1168         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1169                                           sizeof(struct ena_tx_buffer) *
1170                                           txq->ring_size,
1171                                           RTE_CACHE_LINE_SIZE);
1172         if (!txq->tx_buffer_info) {
1173                 PMD_DRV_LOG(ERR,
1174                         "Failed to allocate memory for Tx buffer info\n");
1175                 return -ENOMEM;
1176         }
1177
1178         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1179                                          sizeof(u16) * txq->ring_size,
1180                                          RTE_CACHE_LINE_SIZE);
1181         if (!txq->empty_tx_reqs) {
1182                 PMD_DRV_LOG(ERR,
1183                         "Failed to allocate memory for empty Tx requests\n");
1184                 rte_free(txq->tx_buffer_info);
1185                 return -ENOMEM;
1186         }
1187
1188         txq->push_buf_intermediate_buf =
1189                 rte_zmalloc("txq->push_buf_intermediate_buf",
1190                             txq->tx_max_header_size,
1191                             RTE_CACHE_LINE_SIZE);
1192         if (!txq->push_buf_intermediate_buf) {
1193                 PMD_DRV_LOG(ERR, "Failed to alloc push buffer for LLQ\n");
1194                 rte_free(txq->tx_buffer_info);
1195                 rte_free(txq->empty_tx_reqs);
1196                 return -ENOMEM;
1197         }
1198
1199         for (i = 0; i < txq->ring_size; i++)
1200                 txq->empty_tx_reqs[i] = i;
1201
1202         txq->offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1203
1204         /* Check if caller provided the Tx cleanup threshold value. */
1205         if (tx_conf->tx_free_thresh != 0) {
1206                 txq->tx_free_thresh = tx_conf->tx_free_thresh;
1207         } else {
1208                 dyn_thresh = txq->ring_size -
1209                         txq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1210                 txq->tx_free_thresh = RTE_MAX(dyn_thresh,
1211                         txq->ring_size - ENA_REFILL_THRESH_PACKET);
1212         }
1213
1214         /* Store pointer to this queue in upper layer */
1215         txq->configured = 1;
1216         dev->data->tx_queues[queue_idx] = txq;
1217
1218         return 0;
1219 }
1220
1221 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1222                               uint16_t queue_idx,
1223                               uint16_t nb_desc,
1224                               unsigned int socket_id,
1225                               const struct rte_eth_rxconf *rx_conf,
1226                               struct rte_mempool *mp)
1227 {
1228         struct ena_adapter *adapter = dev->data->dev_private;
1229         struct ena_ring *rxq = NULL;
1230         size_t buffer_size;
1231         int i;
1232         uint16_t dyn_thresh;
1233
1234         rxq = &adapter->rx_ring[queue_idx];
1235         if (rxq->configured) {
1236                 PMD_DRV_LOG(CRIT,
1237                         "API violation. Queue[%d] is already configured\n",
1238                         queue_idx);
1239                 return ENA_COM_FAULT;
1240         }
1241
1242         if (!rte_is_power_of_2(nb_desc)) {
1243                 PMD_DRV_LOG(ERR,
1244                         "Unsupported size of Rx queue: %d is not a power of 2.\n",
1245                         nb_desc);
1246                 return -EINVAL;
1247         }
1248
1249         if (nb_desc > adapter->max_rx_ring_size) {
1250                 PMD_DRV_LOG(ERR,
1251                         "Unsupported size of Rx queue (max size: %d)\n",
1252                         adapter->max_rx_ring_size);
1253                 return -EINVAL;
1254         }
1255
1256         /* ENA isn't supporting buffers smaller than 1400 bytes */
1257         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1258         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1259                 PMD_DRV_LOG(ERR,
1260                         "Unsupported size of Rx buffer: %zu (min size: %d)\n",
1261                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1262                 return -EINVAL;
1263         }
1264
1265         rxq->port_id = dev->data->port_id;
1266         rxq->next_to_clean = 0;
1267         rxq->next_to_use = 0;
1268         rxq->ring_size = nb_desc;
1269         rxq->size_mask = nb_desc - 1;
1270         rxq->numa_socket_id = socket_id;
1271         rxq->mb_pool = mp;
1272
1273         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1274                 sizeof(struct ena_rx_buffer) * nb_desc,
1275                 RTE_CACHE_LINE_SIZE);
1276         if (!rxq->rx_buffer_info) {
1277                 PMD_DRV_LOG(ERR,
1278                         "Failed to allocate memory for Rx buffer info\n");
1279                 return -ENOMEM;
1280         }
1281
1282         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1283                                             sizeof(struct rte_mbuf *) * nb_desc,
1284                                             RTE_CACHE_LINE_SIZE);
1285
1286         if (!rxq->rx_refill_buffer) {
1287                 PMD_DRV_LOG(ERR,
1288                         "Failed to allocate memory for Rx refill buffer\n");
1289                 rte_free(rxq->rx_buffer_info);
1290                 rxq->rx_buffer_info = NULL;
1291                 return -ENOMEM;
1292         }
1293
1294         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1295                                          sizeof(uint16_t) * nb_desc,
1296                                          RTE_CACHE_LINE_SIZE);
1297         if (!rxq->empty_rx_reqs) {
1298                 PMD_DRV_LOG(ERR,
1299                         "Failed to allocate memory for empty Rx requests\n");
1300                 rte_free(rxq->rx_buffer_info);
1301                 rxq->rx_buffer_info = NULL;
1302                 rte_free(rxq->rx_refill_buffer);
1303                 rxq->rx_refill_buffer = NULL;
1304                 return -ENOMEM;
1305         }
1306
1307         for (i = 0; i < nb_desc; i++)
1308                 rxq->empty_rx_reqs[i] = i;
1309
1310         rxq->offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1311
1312         if (rx_conf->rx_free_thresh != 0) {
1313                 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1314         } else {
1315                 dyn_thresh = rxq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1316                 rxq->rx_free_thresh = RTE_MIN(dyn_thresh,
1317                         (uint16_t)(ENA_REFILL_THRESH_PACKET));
1318         }
1319
1320         /* Store pointer to this queue in upper layer */
1321         rxq->configured = 1;
1322         dev->data->rx_queues[queue_idx] = rxq;
1323
1324         return 0;
1325 }
1326
1327 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1328                                   struct rte_mbuf *mbuf, uint16_t id)
1329 {
1330         struct ena_com_buf ebuf;
1331         int rc;
1332
1333         /* prepare physical address for DMA transaction */
1334         ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1335         ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1336
1337         /* pass resource to device */
1338         rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1339         if (unlikely(rc != 0))
1340                 PMD_RX_LOG(WARNING, "Failed adding Rx desc\n");
1341
1342         return rc;
1343 }
1344
1345 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1346 {
1347         unsigned int i;
1348         int rc;
1349         uint16_t next_to_use = rxq->next_to_use;
1350         uint16_t req_id;
1351 #ifdef RTE_ETHDEV_DEBUG_RX
1352         uint16_t in_use;
1353 #endif
1354         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1355
1356         if (unlikely(!count))
1357                 return 0;
1358
1359 #ifdef RTE_ETHDEV_DEBUG_RX
1360         in_use = rxq->ring_size - 1 -
1361                 ena_com_free_q_entries(rxq->ena_com_io_sq);
1362         if (unlikely((in_use + count) >= rxq->ring_size))
1363                 PMD_RX_LOG(ERR, "Bad Rx ring state\n");
1364 #endif
1365
1366         /* get resources for incoming packets */
1367         rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count);
1368         if (unlikely(rc < 0)) {
1369                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1370                 ++rxq->rx_stats.mbuf_alloc_fail;
1371                 PMD_RX_LOG(DEBUG, "There are not enough free buffers\n");
1372                 return 0;
1373         }
1374
1375         for (i = 0; i < count; i++) {
1376                 struct rte_mbuf *mbuf = mbufs[i];
1377                 struct ena_rx_buffer *rx_info;
1378
1379                 if (likely((i + 4) < count))
1380                         rte_prefetch0(mbufs[i + 4]);
1381
1382                 req_id = rxq->empty_rx_reqs[next_to_use];
1383                 rx_info = &rxq->rx_buffer_info[req_id];
1384
1385                 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1386                 if (unlikely(rc != 0))
1387                         break;
1388
1389                 rx_info->mbuf = mbuf;
1390                 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1391         }
1392
1393         if (unlikely(i < count)) {
1394                 PMD_RX_LOG(WARNING,
1395                         "Refilled Rx queue[%d] with only %d/%d buffers\n",
1396                         rxq->id, i, count);
1397                 rte_pktmbuf_free_bulk(&mbufs[i], count - i);
1398                 ++rxq->rx_stats.refill_partial;
1399         }
1400
1401         /* When we submitted free recources to device... */
1402         if (likely(i > 0)) {
1403                 /* ...let HW know that it can fill buffers with data. */
1404                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1405
1406                 rxq->next_to_use = next_to_use;
1407         }
1408
1409         return i;
1410 }
1411
1412 static int ena_device_init(struct ena_com_dev *ena_dev,
1413                            struct rte_pci_device *pdev,
1414                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1415                            bool *wd_state)
1416 {
1417         uint32_t aenq_groups;
1418         int rc;
1419         bool readless_supported;
1420
1421         /* Initialize mmio registers */
1422         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1423         if (rc) {
1424                 PMD_DRV_LOG(ERR, "Failed to init MMIO read less\n");
1425                 return rc;
1426         }
1427
1428         /* The PCIe configuration space revision id indicate if mmio reg
1429          * read is disabled.
1430          */
1431         readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ);
1432         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1433
1434         /* reset device */
1435         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1436         if (rc) {
1437                 PMD_DRV_LOG(ERR, "Cannot reset device\n");
1438                 goto err_mmio_read_less;
1439         }
1440
1441         /* check FW version */
1442         rc = ena_com_validate_version(ena_dev);
1443         if (rc) {
1444                 PMD_DRV_LOG(ERR, "Device version is too low\n");
1445                 goto err_mmio_read_less;
1446         }
1447
1448         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1449
1450         /* ENA device administration layer init */
1451         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1452         if (rc) {
1453                 PMD_DRV_LOG(ERR,
1454                         "Cannot initialize ENA admin queue\n");
1455                 goto err_mmio_read_less;
1456         }
1457
1458         /* To enable the msix interrupts the driver needs to know the number
1459          * of queues. So the driver uses polling mode to retrieve this
1460          * information.
1461          */
1462         ena_com_set_admin_polling_mode(ena_dev, true);
1463
1464         ena_config_host_info(ena_dev);
1465
1466         /* Get Device Attributes and features */
1467         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1468         if (rc) {
1469                 PMD_DRV_LOG(ERR,
1470                         "Cannot get attribute for ENA device, rc: %d\n", rc);
1471                 goto err_admin_init;
1472         }
1473
1474         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1475                       BIT(ENA_ADMIN_NOTIFICATION) |
1476                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1477                       BIT(ENA_ADMIN_FATAL_ERROR) |
1478                       BIT(ENA_ADMIN_WARNING);
1479
1480         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1481         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1482         if (rc) {
1483                 PMD_DRV_LOG(ERR, "Cannot configure AENQ groups, rc: %d\n", rc);
1484                 goto err_admin_init;
1485         }
1486
1487         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1488
1489         return 0;
1490
1491 err_admin_init:
1492         ena_com_admin_destroy(ena_dev);
1493
1494 err_mmio_read_less:
1495         ena_com_mmio_reg_read_request_destroy(ena_dev);
1496
1497         return rc;
1498 }
1499
1500 static void ena_interrupt_handler_rte(void *cb_arg)
1501 {
1502         struct rte_eth_dev *dev = cb_arg;
1503         struct ena_adapter *adapter = dev->data->dev_private;
1504         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1505
1506         ena_com_admin_q_comp_intr_handler(ena_dev);
1507         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1508                 ena_com_aenq_intr_handler(ena_dev, dev);
1509 }
1510
1511 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1512 {
1513         if (!adapter->wd_state)
1514                 return;
1515
1516         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1517                 return;
1518
1519         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1520             adapter->keep_alive_timeout)) {
1521                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1522                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1523                 adapter->trigger_reset = true;
1524                 ++adapter->dev_stats.wd_expired;
1525         }
1526 }
1527
1528 /* Check if admin queue is enabled */
1529 static void check_for_admin_com_state(struct ena_adapter *adapter)
1530 {
1531         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1532                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state\n");
1533                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1534                 adapter->trigger_reset = true;
1535         }
1536 }
1537
1538 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1539                                   void *arg)
1540 {
1541         struct rte_eth_dev *dev = arg;
1542         struct ena_adapter *adapter = dev->data->dev_private;
1543
1544         check_for_missing_keep_alive(adapter);
1545         check_for_admin_com_state(adapter);
1546
1547         if (unlikely(adapter->trigger_reset)) {
1548                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1549                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1550                         NULL);
1551         }
1552 }
1553
1554 static inline void
1555 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1556                                struct ena_admin_feature_llq_desc *llq,
1557                                bool use_large_llq_hdr)
1558 {
1559         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1560         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1561         llq_config->llq_num_decs_before_header =
1562                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1563
1564         if (use_large_llq_hdr &&
1565             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1566                 llq_config->llq_ring_entry_size =
1567                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1568                 llq_config->llq_ring_entry_size_value = 256;
1569         } else {
1570                 llq_config->llq_ring_entry_size =
1571                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1572                 llq_config->llq_ring_entry_size_value = 128;
1573         }
1574 }
1575
1576 static int
1577 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1578                                 struct ena_com_dev *ena_dev,
1579                                 struct ena_admin_feature_llq_desc *llq,
1580                                 struct ena_llq_configurations *llq_default_configurations)
1581 {
1582         int rc;
1583         u32 llq_feature_mask;
1584
1585         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1586         if (!(ena_dev->supported_features & llq_feature_mask)) {
1587                 PMD_DRV_LOG(INFO,
1588                         "LLQ is not supported. Fallback to host mode policy.\n");
1589                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1590                 return 0;
1591         }
1592
1593         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1594         if (unlikely(rc)) {
1595                 PMD_INIT_LOG(WARNING,
1596                         "Failed to config dev mode. Fallback to host mode policy.\n");
1597                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1598                 return 0;
1599         }
1600
1601         /* Nothing to config, exit */
1602         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1603                 return 0;
1604
1605         if (!adapter->dev_mem_base) {
1606                 PMD_DRV_LOG(ERR,
1607                         "Unable to access LLQ BAR resource. Fallback to host mode policy.\n");
1608                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1609                 return 0;
1610         }
1611
1612         ena_dev->mem_bar = adapter->dev_mem_base;
1613
1614         return 0;
1615 }
1616
1617 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1618         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1619 {
1620         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1621
1622         /* Regular queues capabilities */
1623         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1624                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1625                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1626                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1627                                     max_queue_ext->max_rx_cq_num);
1628                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1629                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1630         } else {
1631                 struct ena_admin_queue_feature_desc *max_queues =
1632                         &get_feat_ctx->max_queues;
1633                 io_tx_sq_num = max_queues->max_sq_num;
1634                 io_tx_cq_num = max_queues->max_cq_num;
1635                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1636         }
1637
1638         /* In case of LLQ use the llq number in the get feature cmd */
1639         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1640                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1641
1642         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1643         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1644         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1645
1646         if (unlikely(max_num_io_queues == 0)) {
1647                 PMD_DRV_LOG(ERR, "Number of IO queues cannot not be 0\n");
1648                 return -EFAULT;
1649         }
1650
1651         return max_num_io_queues;
1652 }
1653
1654 static void
1655 ena_set_offloads(struct ena_offloads *offloads,
1656                  struct ena_admin_feature_offload_desc *offload_desc)
1657 {
1658         if (offload_desc->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1659                 offloads->tx_offloads |= ENA_IPV4_TSO;
1660
1661         /* Tx IPv4 checksum offloads */
1662         if (offload_desc->tx &
1663             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)
1664                 offloads->tx_offloads |= ENA_L3_IPV4_CSUM;
1665         if (offload_desc->tx &
1666             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK)
1667                 offloads->tx_offloads |= ENA_L4_IPV4_CSUM;
1668         if (offload_desc->tx &
1669             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1670                 offloads->tx_offloads |= ENA_L4_IPV4_CSUM_PARTIAL;
1671
1672         /* Tx IPv6 checksum offloads */
1673         if (offload_desc->tx &
1674             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK)
1675                 offloads->tx_offloads |= ENA_L4_IPV6_CSUM;
1676         if (offload_desc->tx &
1677              ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
1678                 offloads->tx_offloads |= ENA_L4_IPV6_CSUM_PARTIAL;
1679
1680         /* Rx IPv4 checksum offloads */
1681         if (offload_desc->rx_supported &
1682             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)
1683                 offloads->rx_offloads |= ENA_L3_IPV4_CSUM;
1684         if (offload_desc->rx_supported &
1685             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1686                 offloads->rx_offloads |= ENA_L4_IPV4_CSUM;
1687
1688         /* Rx IPv6 checksum offloads */
1689         if (offload_desc->rx_supported &
1690             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
1691                 offloads->rx_offloads |= ENA_L4_IPV6_CSUM;
1692
1693         if (offload_desc->rx_supported &
1694             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK)
1695                 offloads->rx_offloads |= ENA_RX_RSS_HASH;
1696 }
1697
1698 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1699 {
1700         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1701         struct rte_pci_device *pci_dev;
1702         struct rte_intr_handle *intr_handle;
1703         struct ena_adapter *adapter = eth_dev->data->dev_private;
1704         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1705         struct ena_com_dev_get_features_ctx get_feat_ctx;
1706         struct ena_llq_configurations llq_config;
1707         const char *queue_type_str;
1708         uint32_t max_num_io_queues;
1709         int rc;
1710         static int adapters_found;
1711         bool disable_meta_caching;
1712         bool wd_state = false;
1713
1714         eth_dev->dev_ops = &ena_dev_ops;
1715         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1716         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1717         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1718
1719         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1720                 return 0;
1721
1722         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1723
1724         memset(adapter, 0, sizeof(struct ena_adapter));
1725         ena_dev = &adapter->ena_dev;
1726
1727         adapter->edev_data = eth_dev->data;
1728
1729         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1730
1731         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
1732                      pci_dev->addr.domain,
1733                      pci_dev->addr.bus,
1734                      pci_dev->addr.devid,
1735                      pci_dev->addr.function);
1736
1737         intr_handle = &pci_dev->intr_handle;
1738
1739         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1740         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1741
1742         if (!adapter->regs) {
1743                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
1744                              ENA_REGS_BAR);
1745                 return -ENXIO;
1746         }
1747
1748         ena_dev->reg_bar = adapter->regs;
1749         /* This is a dummy pointer for ena_com functions. */
1750         ena_dev->dmadev = adapter;
1751
1752         adapter->id_number = adapters_found;
1753
1754         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1755                  adapter->id_number);
1756
1757         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1758         if (rc != 0) {
1759                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1760                 goto err;
1761         }
1762
1763         /* device specific initialization routine */
1764         rc = ena_device_init(ena_dev, pci_dev, &get_feat_ctx, &wd_state);
1765         if (rc) {
1766                 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
1767                 goto err;
1768         }
1769         adapter->wd_state = wd_state;
1770
1771         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1772                 adapter->use_large_llq_hdr);
1773         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1774                                              &get_feat_ctx.llq, &llq_config);
1775         if (unlikely(rc)) {
1776                 PMD_INIT_LOG(CRIT, "Failed to set placement policy\n");
1777                 return rc;
1778         }
1779
1780         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1781                 queue_type_str = "Regular";
1782         else
1783                 queue_type_str = "Low latency";
1784         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1785
1786         calc_queue_ctx.ena_dev = ena_dev;
1787         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1788
1789         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1790         rc = ena_calc_io_queue_size(&calc_queue_ctx,
1791                 adapter->use_large_llq_hdr);
1792         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1793                 rc = -EFAULT;
1794                 goto err_device_destroy;
1795         }
1796
1797         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1798         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1799         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1800         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1801         adapter->max_num_io_queues = max_num_io_queues;
1802
1803         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1804                 disable_meta_caching =
1805                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1806                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
1807         } else {
1808                 disable_meta_caching = false;
1809         }
1810
1811         /* prepare ring structures */
1812         ena_init_rings(adapter, disable_meta_caching);
1813
1814         ena_config_debug_area(adapter);
1815
1816         /* Set max MTU for this device */
1817         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1818
1819         ena_set_offloads(&adapter->offloads, &get_feat_ctx.offload);
1820
1821         /* Copy MAC address and point DPDK to it */
1822         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1823         rte_ether_addr_copy((struct rte_ether_addr *)
1824                         get_feat_ctx.dev_attr.mac_addr,
1825                         (struct rte_ether_addr *)adapter->mac_addr);
1826
1827         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
1828         if (unlikely(rc != 0)) {
1829                 PMD_DRV_LOG(ERR, "Failed to initialize RSS in ENA device\n");
1830                 goto err_delete_debug_area;
1831         }
1832
1833         adapter->drv_stats = rte_zmalloc("adapter stats",
1834                                          sizeof(*adapter->drv_stats),
1835                                          RTE_CACHE_LINE_SIZE);
1836         if (!adapter->drv_stats) {
1837                 PMD_DRV_LOG(ERR,
1838                         "Failed to allocate memory for adapter statistics\n");
1839                 rc = -ENOMEM;
1840                 goto err_rss_destroy;
1841         }
1842
1843         rte_spinlock_init(&adapter->admin_lock);
1844
1845         rte_intr_callback_register(intr_handle,
1846                                    ena_interrupt_handler_rte,
1847                                    eth_dev);
1848         rte_intr_enable(intr_handle);
1849         ena_com_set_admin_polling_mode(ena_dev, false);
1850         ena_com_admin_aenq_enable(ena_dev);
1851
1852         if (adapters_found == 0)
1853                 rte_timer_subsystem_init();
1854         rte_timer_init(&adapter->timer_wd);
1855
1856         adapters_found++;
1857         adapter->state = ENA_ADAPTER_STATE_INIT;
1858
1859         return 0;
1860
1861 err_rss_destroy:
1862         ena_com_rss_destroy(ena_dev);
1863 err_delete_debug_area:
1864         ena_com_delete_debug_area(ena_dev);
1865
1866 err_device_destroy:
1867         ena_com_delete_host_info(ena_dev);
1868         ena_com_admin_destroy(ena_dev);
1869
1870 err:
1871         return rc;
1872 }
1873
1874 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1875 {
1876         struct ena_adapter *adapter = eth_dev->data->dev_private;
1877         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1878
1879         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1880                 return;
1881
1882         ena_com_set_admin_running_state(ena_dev, false);
1883
1884         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1885                 ena_close(eth_dev);
1886
1887         ena_com_rss_destroy(ena_dev);
1888
1889         ena_com_delete_debug_area(ena_dev);
1890         ena_com_delete_host_info(ena_dev);
1891
1892         ena_com_abort_admin_commands(ena_dev);
1893         ena_com_wait_for_abort_completion(ena_dev);
1894         ena_com_admin_destroy(ena_dev);
1895         ena_com_mmio_reg_read_request_destroy(ena_dev);
1896
1897         adapter->state = ENA_ADAPTER_STATE_FREE;
1898 }
1899
1900 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1901 {
1902         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1903                 return 0;
1904
1905         ena_destroy_device(eth_dev);
1906
1907         return 0;
1908 }
1909
1910 static int ena_dev_configure(struct rte_eth_dev *dev)
1911 {
1912         struct ena_adapter *adapter = dev->data->dev_private;
1913
1914         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1915
1916         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1917                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1918         dev->data->dev_conf.txmode.offloads |= DEV_TX_OFFLOAD_MULTI_SEGS;
1919
1920         /* Scattered Rx cannot be turned off in the HW, so this capability must
1921          * be forced.
1922          */
1923         dev->data->scattered_rx = 1;
1924
1925         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1926         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1927
1928         return 0;
1929 }
1930
1931 static void ena_init_rings(struct ena_adapter *adapter,
1932                            bool disable_meta_caching)
1933 {
1934         size_t i;
1935
1936         for (i = 0; i < adapter->max_num_io_queues; i++) {
1937                 struct ena_ring *ring = &adapter->tx_ring[i];
1938
1939                 ring->configured = 0;
1940                 ring->type = ENA_RING_TYPE_TX;
1941                 ring->adapter = adapter;
1942                 ring->id = i;
1943                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1944                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1945                 ring->sgl_size = adapter->max_tx_sgl_size;
1946                 ring->disable_meta_caching = disable_meta_caching;
1947         }
1948
1949         for (i = 0; i < adapter->max_num_io_queues; i++) {
1950                 struct ena_ring *ring = &adapter->rx_ring[i];
1951
1952                 ring->configured = 0;
1953                 ring->type = ENA_RING_TYPE_RX;
1954                 ring->adapter = adapter;
1955                 ring->id = i;
1956                 ring->sgl_size = adapter->max_rx_sgl_size;
1957         }
1958 }
1959
1960 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter)
1961 {
1962         uint64_t port_offloads = 0;
1963
1964         if (adapter->offloads.rx_offloads & ENA_L3_IPV4_CSUM)
1965                 port_offloads |= DEV_RX_OFFLOAD_IPV4_CKSUM;
1966
1967         if (adapter->offloads.rx_offloads &
1968             (ENA_L4_IPV4_CSUM | ENA_L4_IPV6_CSUM))
1969                 port_offloads |=
1970                         DEV_RX_OFFLOAD_UDP_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM;
1971
1972         if (adapter->offloads.rx_offloads & ENA_RX_RSS_HASH)
1973                 port_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1974
1975         port_offloads |= DEV_RX_OFFLOAD_SCATTER;
1976
1977         return port_offloads;
1978 }
1979
1980 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter)
1981 {
1982         uint64_t port_offloads = 0;
1983
1984         if (adapter->offloads.tx_offloads & ENA_IPV4_TSO)
1985                 port_offloads |= DEV_TX_OFFLOAD_TCP_TSO;
1986
1987         if (adapter->offloads.tx_offloads & ENA_L3_IPV4_CSUM)
1988                 port_offloads |= DEV_TX_OFFLOAD_IPV4_CKSUM;
1989         if (adapter->offloads.tx_offloads &
1990             (ENA_L4_IPV4_CSUM_PARTIAL | ENA_L4_IPV4_CSUM |
1991              ENA_L4_IPV6_CSUM | ENA_L4_IPV6_CSUM_PARTIAL))
1992                 port_offloads |=
1993                         DEV_TX_OFFLOAD_UDP_CKSUM | DEV_TX_OFFLOAD_TCP_CKSUM;
1994
1995         port_offloads |= DEV_TX_OFFLOAD_MULTI_SEGS;
1996
1997         return port_offloads;
1998 }
1999
2000 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter)
2001 {
2002         RTE_SET_USED(adapter);
2003
2004         return 0;
2005 }
2006
2007 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter)
2008 {
2009         RTE_SET_USED(adapter);
2010
2011         return 0;
2012 }
2013
2014 static int ena_infos_get(struct rte_eth_dev *dev,
2015                           struct rte_eth_dev_info *dev_info)
2016 {
2017         struct ena_adapter *adapter;
2018         struct ena_com_dev *ena_dev;
2019
2020         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
2021         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2022         adapter = dev->data->dev_private;
2023
2024         ena_dev = &adapter->ena_dev;
2025         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2026
2027         dev_info->speed_capa =
2028                         ETH_LINK_SPEED_1G   |
2029                         ETH_LINK_SPEED_2_5G |
2030                         ETH_LINK_SPEED_5G   |
2031                         ETH_LINK_SPEED_10G  |
2032                         ETH_LINK_SPEED_25G  |
2033                         ETH_LINK_SPEED_40G  |
2034                         ETH_LINK_SPEED_50G  |
2035                         ETH_LINK_SPEED_100G;
2036
2037         /* Inform framework about available features */
2038         dev_info->rx_offload_capa = ena_get_rx_port_offloads(adapter);
2039         dev_info->tx_offload_capa = ena_get_tx_port_offloads(adapter);
2040         dev_info->rx_queue_offload_capa = ena_get_rx_queue_offloads(adapter);
2041         dev_info->tx_queue_offload_capa = ena_get_tx_queue_offloads(adapter);
2042
2043         dev_info->flow_type_rss_offloads = ENA_ALL_RSS_HF;
2044         dev_info->hash_key_size = ENA_HASH_KEY_SIZE;
2045
2046         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2047         dev_info->max_rx_pktlen  = adapter->max_mtu + RTE_ETHER_HDR_LEN +
2048                 RTE_ETHER_CRC_LEN;
2049         dev_info->min_mtu = ENA_MIN_MTU;
2050         dev_info->max_mtu = adapter->max_mtu;
2051         dev_info->max_mac_addrs = 1;
2052
2053         dev_info->max_rx_queues = adapter->max_num_io_queues;
2054         dev_info->max_tx_queues = adapter->max_num_io_queues;
2055         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2056
2057         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2058         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2059         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2060                                         adapter->max_rx_sgl_size);
2061         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2062                                         adapter->max_rx_sgl_size);
2063
2064         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2065         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2066         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2067                                         adapter->max_tx_sgl_size);
2068         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2069                                         adapter->max_tx_sgl_size);
2070
2071         dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2072         dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2073
2074         return 0;
2075 }
2076
2077 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2078 {
2079         mbuf->data_len = len;
2080         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2081         mbuf->refcnt = 1;
2082         mbuf->next = NULL;
2083 }
2084
2085 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2086                                     struct ena_com_rx_buf_info *ena_bufs,
2087                                     uint32_t descs,
2088                                     uint16_t *next_to_clean,
2089                                     uint8_t offset)
2090 {
2091         struct rte_mbuf *mbuf;
2092         struct rte_mbuf *mbuf_head;
2093         struct ena_rx_buffer *rx_info;
2094         int rc;
2095         uint16_t ntc, len, req_id, buf = 0;
2096
2097         if (unlikely(descs == 0))
2098                 return NULL;
2099
2100         ntc = *next_to_clean;
2101
2102         len = ena_bufs[buf].len;
2103         req_id = ena_bufs[buf].req_id;
2104
2105         rx_info = &rx_ring->rx_buffer_info[req_id];
2106
2107         mbuf = rx_info->mbuf;
2108         RTE_ASSERT(mbuf != NULL);
2109
2110         ena_init_rx_mbuf(mbuf, len);
2111
2112         /* Fill the mbuf head with the data specific for 1st segment. */
2113         mbuf_head = mbuf;
2114         mbuf_head->nb_segs = descs;
2115         mbuf_head->port = rx_ring->port_id;
2116         mbuf_head->pkt_len = len;
2117         mbuf_head->data_off += offset;
2118
2119         rx_info->mbuf = NULL;
2120         rx_ring->empty_rx_reqs[ntc] = req_id;
2121         ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2122
2123         while (--descs) {
2124                 ++buf;
2125                 len = ena_bufs[buf].len;
2126                 req_id = ena_bufs[buf].req_id;
2127
2128                 rx_info = &rx_ring->rx_buffer_info[req_id];
2129                 RTE_ASSERT(rx_info->mbuf != NULL);
2130
2131                 if (unlikely(len == 0)) {
2132                         /*
2133                          * Some devices can pass descriptor with the length 0.
2134                          * To avoid confusion, the PMD is simply putting the
2135                          * descriptor back, as it was never used. We'll avoid
2136                          * mbuf allocation that way.
2137                          */
2138                         rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2139                                 rx_info->mbuf, req_id);
2140                         if (unlikely(rc != 0)) {
2141                                 /* Free the mbuf in case of an error. */
2142                                 rte_mbuf_raw_free(rx_info->mbuf);
2143                         } else {
2144                                 /*
2145                                  * If there was no error, just exit the loop as
2146                                  * 0 length descriptor is always the last one.
2147                                  */
2148                                 break;
2149                         }
2150                 } else {
2151                         /* Create an mbuf chain. */
2152                         mbuf->next = rx_info->mbuf;
2153                         mbuf = mbuf->next;
2154
2155                         ena_init_rx_mbuf(mbuf, len);
2156                         mbuf_head->pkt_len += len;
2157                 }
2158
2159                 /*
2160                  * Mark the descriptor as depleted and perform necessary
2161                  * cleanup.
2162                  * This code will execute in two cases:
2163                  *  1. Descriptor len was greater than 0 - normal situation.
2164                  *  2. Descriptor len was 0 and we failed to add the descriptor
2165                  *     to the device. In that situation, we should try to add
2166                  *     the mbuf again in the populate routine and mark the
2167                  *     descriptor as used up by the device.
2168                  */
2169                 rx_info->mbuf = NULL;
2170                 rx_ring->empty_rx_reqs[ntc] = req_id;
2171                 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2172         }
2173
2174         *next_to_clean = ntc;
2175
2176         return mbuf_head;
2177 }
2178
2179 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2180                                   uint16_t nb_pkts)
2181 {
2182         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2183         unsigned int free_queue_entries;
2184         uint16_t next_to_clean = rx_ring->next_to_clean;
2185         uint16_t descs_in_use;
2186         struct rte_mbuf *mbuf;
2187         uint16_t completed;
2188         struct ena_com_rx_ctx ena_rx_ctx;
2189         int i, rc = 0;
2190         bool fill_hash;
2191
2192 #ifdef RTE_ETHDEV_DEBUG_RX
2193         /* Check adapter state */
2194         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2195                 PMD_RX_LOG(ALERT,
2196                         "Trying to receive pkts while device is NOT running\n");
2197                 return 0;
2198         }
2199 #endif
2200
2201         fill_hash = rx_ring->offloads & DEV_RX_OFFLOAD_RSS_HASH;
2202
2203         descs_in_use = rx_ring->ring_size -
2204                 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2205         nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2206
2207         for (completed = 0; completed < nb_pkts; completed++) {
2208                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2209                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2210                 ena_rx_ctx.descs = 0;
2211                 ena_rx_ctx.pkt_offset = 0;
2212                 /* receive packet context */
2213                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2214                                     rx_ring->ena_com_io_sq,
2215                                     &ena_rx_ctx);
2216                 if (unlikely(rc)) {
2217                         PMD_RX_LOG(ERR,
2218                                 "Failed to get the packet from the device, rc: %d\n",
2219                                 rc);
2220                         if (rc == ENA_COM_NO_SPACE) {
2221                                 ++rx_ring->rx_stats.bad_desc_num;
2222                                 rx_ring->adapter->reset_reason =
2223                                         ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2224                         } else {
2225                                 ++rx_ring->rx_stats.bad_req_id;
2226                                 rx_ring->adapter->reset_reason =
2227                                         ENA_REGS_RESET_INV_RX_REQ_ID;
2228                         }
2229                         rx_ring->adapter->trigger_reset = true;
2230                         return 0;
2231                 }
2232
2233                 mbuf = ena_rx_mbuf(rx_ring,
2234                         ena_rx_ctx.ena_bufs,
2235                         ena_rx_ctx.descs,
2236                         &next_to_clean,
2237                         ena_rx_ctx.pkt_offset);
2238                 if (unlikely(mbuf == NULL)) {
2239                         for (i = 0; i < ena_rx_ctx.descs; ++i) {
2240                                 rx_ring->empty_rx_reqs[next_to_clean] =
2241                                         rx_ring->ena_bufs[i].req_id;
2242                                 next_to_clean = ENA_IDX_NEXT_MASKED(
2243                                         next_to_clean, rx_ring->size_mask);
2244                         }
2245                         break;
2246                 }
2247
2248                 /* fill mbuf attributes if any */
2249                 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx, fill_hash);
2250
2251                 if (unlikely(mbuf->ol_flags &
2252                                 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2253                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2254                         ++rx_ring->rx_stats.bad_csum;
2255                 }
2256
2257                 rx_pkts[completed] = mbuf;
2258                 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2259         }
2260
2261         rx_ring->rx_stats.cnt += completed;
2262         rx_ring->next_to_clean = next_to_clean;
2263
2264         free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2265
2266         /* Burst refill to save doorbells, memory barriers, const interval */
2267         if (free_queue_entries >= rx_ring->rx_free_thresh) {
2268                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2269                 ena_populate_rx_queue(rx_ring, free_queue_entries);
2270         }
2271
2272         return completed;
2273 }
2274
2275 static uint16_t
2276 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2277                 uint16_t nb_pkts)
2278 {
2279         int32_t ret;
2280         uint32_t i;
2281         struct rte_mbuf *m;
2282         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2283         struct ena_adapter *adapter = tx_ring->adapter;
2284         struct rte_ipv4_hdr *ip_hdr;
2285         uint64_t ol_flags;
2286         uint64_t l4_csum_flag;
2287         uint64_t dev_offload_capa;
2288         uint16_t frag_field;
2289         bool need_pseudo_csum;
2290
2291         dev_offload_capa = adapter->offloads.tx_offloads;
2292         for (i = 0; i != nb_pkts; i++) {
2293                 m = tx_pkts[i];
2294                 ol_flags = m->ol_flags;
2295
2296                 /* Check if any offload flag was set */
2297                 if (ol_flags == 0)
2298                         continue;
2299
2300                 l4_csum_flag = ol_flags & PKT_TX_L4_MASK;
2301                 /* SCTP checksum offload is not supported by the ENA. */
2302                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) ||
2303                     l4_csum_flag == PKT_TX_SCTP_CKSUM) {
2304                         PMD_TX_LOG(DEBUG,
2305                                 "mbuf[%" PRIu32 "] has unsupported offloads flags set: 0x%" PRIu64 "\n",
2306                                 i, ol_flags);
2307                         rte_errno = ENOTSUP;
2308                         return i;
2309                 }
2310
2311 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2312                 /* Check if requested offload is also enabled for the queue */
2313                 if ((ol_flags & PKT_TX_IP_CKSUM &&
2314                      !(tx_ring->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) ||
2315                     (l4_csum_flag == PKT_TX_TCP_CKSUM &&
2316                      !(tx_ring->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) ||
2317                     (l4_csum_flag == PKT_TX_UDP_CKSUM &&
2318                      !(tx_ring->offloads & DEV_TX_OFFLOAD_UDP_CKSUM))) {
2319                         PMD_TX_LOG(DEBUG,
2320                                 "mbuf[%" PRIu32 "]: requested offloads: %" PRIu16 " are not enabled for the queue[%u]\n",
2321                                 i, m->nb_segs, tx_ring->id);
2322                         rte_errno = EINVAL;
2323                         return i;
2324                 }
2325
2326                 /* The caller is obligated to set l2 and l3 len if any cksum
2327                  * offload is enabled.
2328                  */
2329                 if (unlikely(ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK) &&
2330                     (m->l2_len == 0 || m->l3_len == 0))) {
2331                         PMD_TX_LOG(DEBUG,
2332                                 "mbuf[%" PRIu32 "]: l2_len or l3_len values are 0 while the offload was requested\n",
2333                                 i);
2334                         rte_errno = EINVAL;
2335                         return i;
2336                 }
2337                 ret = rte_validate_tx_offload(m);
2338                 if (ret != 0) {
2339                         rte_errno = -ret;
2340                         return i;
2341                 }
2342 #endif
2343
2344                 /* Verify HW support for requested offloads and determine if
2345                  * pseudo header checksum is needed.
2346                  */
2347                 need_pseudo_csum = false;
2348                 if (ol_flags & PKT_TX_IPV4) {
2349                         if (ol_flags & PKT_TX_IP_CKSUM &&
2350                             !(dev_offload_capa & ENA_L3_IPV4_CSUM)) {
2351                                 rte_errno = ENOTSUP;
2352                                 return i;
2353                         }
2354
2355                         if (ol_flags & PKT_TX_TCP_SEG &&
2356                             !(dev_offload_capa & ENA_IPV4_TSO)) {
2357                                 rte_errno = ENOTSUP;
2358                                 return i;
2359                         }
2360
2361                         /* Check HW capabilities and if pseudo csum is needed
2362                          * for L4 offloads.
2363                          */
2364                         if (l4_csum_flag != PKT_TX_L4_NO_CKSUM &&
2365                             !(dev_offload_capa & ENA_L4_IPV4_CSUM)) {
2366                                 if (dev_offload_capa &
2367                                     ENA_L4_IPV4_CSUM_PARTIAL) {
2368                                         need_pseudo_csum = true;
2369                                 } else {
2370                                         rte_errno = ENOTSUP;
2371                                         return i;
2372                                 }
2373                         }
2374
2375                         /* Parse the DF flag */
2376                         ip_hdr = rte_pktmbuf_mtod_offset(m,
2377                                 struct rte_ipv4_hdr *, m->l2_len);
2378                         frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2379                         if (frag_field & RTE_IPV4_HDR_DF_FLAG) {
2380                                 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2381                         } else if (ol_flags & PKT_TX_TCP_SEG) {
2382                                 /* In case we are supposed to TSO and have DF
2383                                  * not set (DF=0) hardware must be provided with
2384                                  * partial checksum.
2385                                  */
2386                                 need_pseudo_csum = true;
2387                         }
2388                 } else if (ol_flags & PKT_TX_IPV6) {
2389                         /* There is no support for IPv6 TSO as for now. */
2390                         if (ol_flags & PKT_TX_TCP_SEG) {
2391                                 rte_errno = ENOTSUP;
2392                                 return i;
2393                         }
2394
2395                         /* Check HW capabilities and if pseudo csum is needed */
2396                         if (l4_csum_flag != PKT_TX_L4_NO_CKSUM &&
2397                             !(dev_offload_capa & ENA_L4_IPV6_CSUM)) {
2398                                 if (dev_offload_capa &
2399                                     ENA_L4_IPV6_CSUM_PARTIAL) {
2400                                         need_pseudo_csum = true;
2401                                 } else {
2402                                         rte_errno = ENOTSUP;
2403                                         return i;
2404                                 }
2405                         }
2406                 }
2407
2408                 if (need_pseudo_csum) {
2409                         ret = rte_net_intel_cksum_flags_prepare(m, ol_flags);
2410                         if (ret != 0) {
2411                                 rte_errno = -ret;
2412                                 return i;
2413                         }
2414                 }
2415         }
2416
2417         return i;
2418 }
2419
2420 static void ena_update_hints(struct ena_adapter *adapter,
2421                              struct ena_admin_ena_hw_hints *hints)
2422 {
2423         if (hints->admin_completion_tx_timeout)
2424                 adapter->ena_dev.admin_queue.completion_timeout =
2425                         hints->admin_completion_tx_timeout * 1000;
2426
2427         if (hints->mmio_read_timeout)
2428                 /* convert to usec */
2429                 adapter->ena_dev.mmio_read.reg_read_to =
2430                         hints->mmio_read_timeout * 1000;
2431
2432         if (hints->driver_watchdog_timeout) {
2433                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2434                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2435                 else
2436                         // Convert msecs to ticks
2437                         adapter->keep_alive_timeout =
2438                                 (hints->driver_watchdog_timeout *
2439                                 rte_get_timer_hz()) / 1000;
2440         }
2441 }
2442
2443 static int ena_check_space_and_linearize_mbuf(struct ena_ring *tx_ring,
2444                                               struct rte_mbuf *mbuf)
2445 {
2446         struct ena_com_dev *ena_dev;
2447         int num_segments, header_len, rc;
2448
2449         ena_dev = &tx_ring->adapter->ena_dev;
2450         num_segments = mbuf->nb_segs;
2451         header_len = mbuf->data_len;
2452
2453         if (likely(num_segments < tx_ring->sgl_size))
2454                 goto checkspace;
2455
2456         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2457             (num_segments == tx_ring->sgl_size) &&
2458             (header_len < tx_ring->tx_max_header_size))
2459                 goto checkspace;
2460
2461         /* Checking for space for 2 additional metadata descriptors due to
2462          * possible header split and metadata descriptor. Linearization will
2463          * be needed so we reduce the segments number from num_segments to 1
2464          */
2465         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 3)) {
2466                 PMD_TX_LOG(DEBUG, "Not enough space in the Tx queue\n");
2467                 return ENA_COM_NO_MEM;
2468         }
2469         ++tx_ring->tx_stats.linearize;
2470         rc = rte_pktmbuf_linearize(mbuf);
2471         if (unlikely(rc)) {
2472                 PMD_TX_LOG(WARNING, "Mbuf linearize failed\n");
2473                 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2474                 ++tx_ring->tx_stats.linearize_failed;
2475                 return rc;
2476         }
2477
2478         return 0;
2479
2480 checkspace:
2481         /* Checking for space for 2 additional metadata descriptors due to
2482          * possible header split and metadata descriptor
2483          */
2484         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2485                                           num_segments + 2)) {
2486                 PMD_TX_LOG(DEBUG, "Not enough space in the Tx queue\n");
2487                 return ENA_COM_NO_MEM;
2488         }
2489
2490         return 0;
2491 }
2492
2493 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2494         struct ena_tx_buffer *tx_info,
2495         struct rte_mbuf *mbuf,
2496         void **push_header,
2497         uint16_t *header_len)
2498 {
2499         struct ena_com_buf *ena_buf;
2500         uint16_t delta, seg_len, push_len;
2501
2502         delta = 0;
2503         seg_len = mbuf->data_len;
2504
2505         tx_info->mbuf = mbuf;
2506         ena_buf = tx_info->bufs;
2507
2508         if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2509                 /*
2510                  * Tx header might be (and will be in most cases) smaller than
2511                  * tx_max_header_size. But it's not an issue to send more data
2512                  * to the device, than actually needed if the mbuf size is
2513                  * greater than tx_max_header_size.
2514                  */
2515                 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2516                 *header_len = push_len;
2517
2518                 if (likely(push_len <= seg_len)) {
2519                         /* If the push header is in the single segment, then
2520                          * just point it to the 1st mbuf data.
2521                          */
2522                         *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2523                 } else {
2524                         /* If the push header lays in the several segments, copy
2525                          * it to the intermediate buffer.
2526                          */
2527                         rte_pktmbuf_read(mbuf, 0, push_len,
2528                                 tx_ring->push_buf_intermediate_buf);
2529                         *push_header = tx_ring->push_buf_intermediate_buf;
2530                         delta = push_len - seg_len;
2531                 }
2532         } else {
2533                 *push_header = NULL;
2534                 *header_len = 0;
2535                 push_len = 0;
2536         }
2537
2538         /* Process first segment taking into consideration pushed header */
2539         if (seg_len > push_len) {
2540                 ena_buf->paddr = mbuf->buf_iova +
2541                                 mbuf->data_off +
2542                                 push_len;
2543                 ena_buf->len = seg_len - push_len;
2544                 ena_buf++;
2545                 tx_info->num_of_bufs++;
2546         }
2547
2548         while ((mbuf = mbuf->next) != NULL) {
2549                 seg_len = mbuf->data_len;
2550
2551                 /* Skip mbufs if whole data is pushed as a header */
2552                 if (unlikely(delta > seg_len)) {
2553                         delta -= seg_len;
2554                         continue;
2555                 }
2556
2557                 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2558                 ena_buf->len = seg_len - delta;
2559                 ena_buf++;
2560                 tx_info->num_of_bufs++;
2561
2562                 delta = 0;
2563         }
2564 }
2565
2566 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2567 {
2568         struct ena_tx_buffer *tx_info;
2569         struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2570         uint16_t next_to_use;
2571         uint16_t header_len;
2572         uint16_t req_id;
2573         void *push_header;
2574         int nb_hw_desc;
2575         int rc;
2576
2577         rc = ena_check_space_and_linearize_mbuf(tx_ring, mbuf);
2578         if (unlikely(rc))
2579                 return rc;
2580
2581         next_to_use = tx_ring->next_to_use;
2582
2583         req_id = tx_ring->empty_tx_reqs[next_to_use];
2584         tx_info = &tx_ring->tx_buffer_info[req_id];
2585         tx_info->num_of_bufs = 0;
2586
2587         ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2588
2589         ena_tx_ctx.ena_bufs = tx_info->bufs;
2590         ena_tx_ctx.push_header = push_header;
2591         ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2592         ena_tx_ctx.req_id = req_id;
2593         ena_tx_ctx.header_len = header_len;
2594
2595         /* Set Tx offloads flags, if applicable */
2596         ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2597                 tx_ring->disable_meta_caching);
2598
2599         if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2600                         &ena_tx_ctx))) {
2601                 PMD_TX_LOG(DEBUG,
2602                         "LLQ Tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2603                         tx_ring->id);
2604                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2605                 tx_ring->tx_stats.doorbells++;
2606                 tx_ring->pkts_without_db = false;
2607         }
2608
2609         /* prepare the packet's descriptors to dma engine */
2610         rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2611                 &nb_hw_desc);
2612         if (unlikely(rc)) {
2613                 PMD_DRV_LOG(ERR, "Failed to prepare Tx buffers, rc: %d\n", rc);
2614                 ++tx_ring->tx_stats.prepare_ctx_err;
2615                 tx_ring->adapter->reset_reason =
2616                     ENA_REGS_RESET_DRIVER_INVALID_STATE;
2617                 tx_ring->adapter->trigger_reset = true;
2618                 return rc;
2619         }
2620
2621         tx_info->tx_descs = nb_hw_desc;
2622
2623         tx_ring->tx_stats.cnt++;
2624         tx_ring->tx_stats.bytes += mbuf->pkt_len;
2625
2626         tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2627                 tx_ring->size_mask);
2628
2629         return 0;
2630 }
2631
2632 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2633 {
2634         unsigned int total_tx_descs = 0;
2635         uint16_t cleanup_budget;
2636         uint16_t next_to_clean = tx_ring->next_to_clean;
2637
2638         /* Attempt to release all Tx descriptors (ring_size - 1 -> size_mask) */
2639         cleanup_budget = tx_ring->size_mask;
2640
2641         while (likely(total_tx_descs < cleanup_budget)) {
2642                 struct rte_mbuf *mbuf;
2643                 struct ena_tx_buffer *tx_info;
2644                 uint16_t req_id;
2645
2646                 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2647                         break;
2648
2649                 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2650                         break;
2651
2652                 /* Get Tx info & store how many descs were processed  */
2653                 tx_info = &tx_ring->tx_buffer_info[req_id];
2654
2655                 mbuf = tx_info->mbuf;
2656                 rte_pktmbuf_free(mbuf);
2657
2658                 tx_info->mbuf = NULL;
2659                 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2660
2661                 total_tx_descs += tx_info->tx_descs;
2662
2663                 /* Put back descriptor to the ring for reuse */
2664                 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2665                         tx_ring->size_mask);
2666         }
2667
2668         if (likely(total_tx_descs > 0)) {
2669                 /* acknowledge completion of sent packets */
2670                 tx_ring->next_to_clean = next_to_clean;
2671                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2672                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2673         }
2674 }
2675
2676 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2677                                   uint16_t nb_pkts)
2678 {
2679         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2680         int available_desc;
2681         uint16_t sent_idx = 0;
2682
2683 #ifdef RTE_ETHDEV_DEBUG_TX
2684         /* Check adapter state */
2685         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2686                 PMD_TX_LOG(ALERT,
2687                         "Trying to xmit pkts while device is NOT running\n");
2688                 return 0;
2689         }
2690 #endif
2691
2692         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2693                 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2694                         break;
2695                 tx_ring->pkts_without_db = true;
2696                 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2697                         tx_ring->size_mask)]);
2698         }
2699
2700         available_desc = ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2701         tx_ring->tx_stats.available_desc = available_desc;
2702
2703         /* If there are ready packets to be xmitted... */
2704         if (likely(tx_ring->pkts_without_db)) {
2705                 /* ...let HW do its best :-) */
2706                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2707                 tx_ring->tx_stats.doorbells++;
2708                 tx_ring->pkts_without_db = false;
2709         }
2710
2711         if (available_desc < tx_ring->tx_free_thresh)
2712                 ena_tx_cleanup(tx_ring);
2713
2714         tx_ring->tx_stats.available_desc =
2715                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2716         tx_ring->tx_stats.tx_poll++;
2717
2718         return sent_idx;
2719 }
2720
2721 int ena_copy_eni_stats(struct ena_adapter *adapter)
2722 {
2723         struct ena_admin_eni_stats admin_eni_stats;
2724         int rc;
2725
2726         rte_spinlock_lock(&adapter->admin_lock);
2727         rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats);
2728         rte_spinlock_unlock(&adapter->admin_lock);
2729         if (rc != 0) {
2730                 if (rc == ENA_COM_UNSUPPORTED) {
2731                         PMD_DRV_LOG(DEBUG,
2732                                 "Retrieving ENI metrics is not supported\n");
2733                 } else {
2734                         PMD_DRV_LOG(WARNING,
2735                                 "Failed to get ENI metrics, rc: %d\n", rc);
2736                 }
2737                 return rc;
2738         }
2739
2740         rte_memcpy(&adapter->eni_stats, &admin_eni_stats,
2741                 sizeof(struct ena_stats_eni));
2742
2743         return 0;
2744 }
2745
2746 /**
2747  * DPDK callback to retrieve names of extended device statistics
2748  *
2749  * @param dev
2750  *   Pointer to Ethernet device structure.
2751  * @param[out] xstats_names
2752  *   Buffer to insert names into.
2753  * @param n
2754  *   Number of names.
2755  *
2756  * @return
2757  *   Number of xstats names.
2758  */
2759 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2760                                 struct rte_eth_xstat_name *xstats_names,
2761                                 unsigned int n)
2762 {
2763         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
2764         unsigned int stat, i, count = 0;
2765
2766         if (n < xstats_count || !xstats_names)
2767                 return xstats_count;
2768
2769         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2770                 strcpy(xstats_names[count].name,
2771                         ena_stats_global_strings[stat].name);
2772
2773         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
2774                 strcpy(xstats_names[count].name,
2775                         ena_stats_eni_strings[stat].name);
2776
2777         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2778                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2779                         snprintf(xstats_names[count].name,
2780                                 sizeof(xstats_names[count].name),
2781                                 "rx_q%d_%s", i,
2782                                 ena_stats_rx_strings[stat].name);
2783
2784         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2785                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2786                         snprintf(xstats_names[count].name,
2787                                 sizeof(xstats_names[count].name),
2788                                 "tx_q%d_%s", i,
2789                                 ena_stats_tx_strings[stat].name);
2790
2791         return xstats_count;
2792 }
2793
2794 /**
2795  * DPDK callback to get extended device statistics.
2796  *
2797  * @param dev
2798  *   Pointer to Ethernet device structure.
2799  * @param[out] stats
2800  *   Stats table output buffer.
2801  * @param n
2802  *   The size of the stats table.
2803  *
2804  * @return
2805  *   Number of xstats on success, negative on failure.
2806  */
2807 static int ena_xstats_get(struct rte_eth_dev *dev,
2808                           struct rte_eth_xstat *xstats,
2809                           unsigned int n)
2810 {
2811         struct ena_adapter *adapter = dev->data->dev_private;
2812         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
2813         unsigned int stat, i, count = 0;
2814         int stat_offset;
2815         void *stats_begin;
2816
2817         if (n < xstats_count)
2818                 return xstats_count;
2819
2820         if (!xstats)
2821                 return 0;
2822
2823         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2824                 stat_offset = ena_stats_global_strings[stat].stat_offset;
2825                 stats_begin = &adapter->dev_stats;
2826
2827                 xstats[count].id = count;
2828                 xstats[count].value = *((uint64_t *)
2829                         ((char *)stats_begin + stat_offset));
2830         }
2831
2832         /* Even if the function below fails, we should copy previous (or initial
2833          * values) to keep structure of rte_eth_xstat consistent.
2834          */
2835         ena_copy_eni_stats(adapter);
2836         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
2837                 stat_offset = ena_stats_eni_strings[stat].stat_offset;
2838                 stats_begin = &adapter->eni_stats;
2839
2840                 xstats[count].id = count;
2841                 xstats[count].value = *((uint64_t *)
2842                     ((char *)stats_begin + stat_offset));
2843         }
2844
2845         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2846                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2847                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2848                         stats_begin = &adapter->rx_ring[i].rx_stats;
2849
2850                         xstats[count].id = count;
2851                         xstats[count].value = *((uint64_t *)
2852                                 ((char *)stats_begin + stat_offset));
2853                 }
2854         }
2855
2856         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2857                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2858                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2859                         stats_begin = &adapter->tx_ring[i].rx_stats;
2860
2861                         xstats[count].id = count;
2862                         xstats[count].value = *((uint64_t *)
2863                                 ((char *)stats_begin + stat_offset));
2864                 }
2865         }
2866
2867         return count;
2868 }
2869
2870 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2871                                 const uint64_t *ids,
2872                                 uint64_t *values,
2873                                 unsigned int n)
2874 {
2875         struct ena_adapter *adapter = dev->data->dev_private;
2876         uint64_t id;
2877         uint64_t rx_entries, tx_entries;
2878         unsigned int i;
2879         int qid;
2880         int valid = 0;
2881         bool was_eni_copied = false;
2882
2883         for (i = 0; i < n; ++i) {
2884                 id = ids[i];
2885                 /* Check if id belongs to global statistics */
2886                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2887                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2888                         ++valid;
2889                         continue;
2890                 }
2891
2892                 /* Check if id belongs to ENI statistics */
2893                 id -= ENA_STATS_ARRAY_GLOBAL;
2894                 if (id < ENA_STATS_ARRAY_ENI) {
2895                         /* Avoid reading ENI stats multiple times in a single
2896                          * function call, as it requires communication with the
2897                          * admin queue.
2898                          */
2899                         if (!was_eni_copied) {
2900                                 was_eni_copied = true;
2901                                 ena_copy_eni_stats(adapter);
2902                         }
2903                         values[i] = *((uint64_t *)&adapter->eni_stats + id);
2904                         ++valid;
2905                         continue;
2906                 }
2907
2908                 /* Check if id belongs to rx queue statistics */
2909                 id -= ENA_STATS_ARRAY_ENI;
2910                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2911                 if (id < rx_entries) {
2912                         qid = id % dev->data->nb_rx_queues;
2913                         id /= dev->data->nb_rx_queues;
2914                         values[i] = *((uint64_t *)
2915                                 &adapter->rx_ring[qid].rx_stats + id);
2916                         ++valid;
2917                         continue;
2918                 }
2919                                 /* Check if id belongs to rx queue statistics */
2920                 id -= rx_entries;
2921                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2922                 if (id < tx_entries) {
2923                         qid = id % dev->data->nb_tx_queues;
2924                         id /= dev->data->nb_tx_queues;
2925                         values[i] = *((uint64_t *)
2926                                 &adapter->tx_ring[qid].tx_stats + id);
2927                         ++valid;
2928                         continue;
2929                 }
2930         }
2931
2932         return valid;
2933 }
2934
2935 static int ena_process_bool_devarg(const char *key,
2936                                    const char *value,
2937                                    void *opaque)
2938 {
2939         struct ena_adapter *adapter = opaque;
2940         bool bool_value;
2941
2942         /* Parse the value. */
2943         if (strcmp(value, "1") == 0) {
2944                 bool_value = true;
2945         } else if (strcmp(value, "0") == 0) {
2946                 bool_value = false;
2947         } else {
2948                 PMD_INIT_LOG(ERR,
2949                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
2950                         value, key);
2951                 return -EINVAL;
2952         }
2953
2954         /* Now, assign it to the proper adapter field. */
2955         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0)
2956                 adapter->use_large_llq_hdr = bool_value;
2957
2958         return 0;
2959 }
2960
2961 static int ena_parse_devargs(struct ena_adapter *adapter,
2962                              struct rte_devargs *devargs)
2963 {
2964         static const char * const allowed_args[] = {
2965                 ENA_DEVARG_LARGE_LLQ_HDR,
2966                 NULL,
2967         };
2968         struct rte_kvargs *kvlist;
2969         int rc;
2970
2971         if (devargs == NULL)
2972                 return 0;
2973
2974         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
2975         if (kvlist == NULL) {
2976                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
2977                         devargs->args);
2978                 return -EINVAL;
2979         }
2980
2981         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
2982                 ena_process_bool_devarg, adapter);
2983
2984         rte_kvargs_free(kvlist);
2985
2986         return rc;
2987 }
2988
2989 static int ena_setup_rx_intr(struct rte_eth_dev *dev)
2990 {
2991         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2992         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2993         int rc;
2994         uint16_t vectors_nb, i;
2995         bool rx_intr_requested = dev->data->dev_conf.intr_conf.rxq;
2996
2997         if (!rx_intr_requested)
2998                 return 0;
2999
3000         if (!rte_intr_cap_multiple(intr_handle)) {
3001                 PMD_DRV_LOG(ERR,
3002                         "Rx interrupt requested, but it isn't supported by the PCI driver\n");
3003                 return -ENOTSUP;
3004         }
3005
3006         /* Disable interrupt mapping before the configuration starts. */
3007         rte_intr_disable(intr_handle);
3008
3009         /* Verify if there are enough vectors available. */
3010         vectors_nb = dev->data->nb_rx_queues;
3011         if (vectors_nb > RTE_MAX_RXTX_INTR_VEC_ID) {
3012                 PMD_DRV_LOG(ERR,
3013                         "Too many Rx interrupts requested, maximum number: %d\n",
3014                         RTE_MAX_RXTX_INTR_VEC_ID);
3015                 rc = -ENOTSUP;
3016                 goto enable_intr;
3017         }
3018
3019         intr_handle->intr_vec = rte_zmalloc("intr_vec",
3020                 dev->data->nb_rx_queues * sizeof(*intr_handle->intr_vec), 0);
3021         if (intr_handle->intr_vec == NULL) {
3022                 PMD_DRV_LOG(ERR,
3023                         "Failed to allocate interrupt vector for %d queues\n",
3024                         dev->data->nb_rx_queues);
3025                 rc = -ENOMEM;
3026                 goto enable_intr;
3027         }
3028
3029         rc = rte_intr_efd_enable(intr_handle, vectors_nb);
3030         if (rc != 0)
3031                 goto free_intr_vec;
3032
3033         if (!rte_intr_allow_others(intr_handle)) {
3034                 PMD_DRV_LOG(ERR,
3035                         "Not enough interrupts available to use both ENA Admin and Rx interrupts\n");
3036                 goto disable_intr_efd;
3037         }
3038
3039         for (i = 0; i < vectors_nb; ++i)
3040                 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + i;
3041
3042         rte_intr_enable(intr_handle);
3043         return 0;
3044
3045 disable_intr_efd:
3046         rte_intr_efd_disable(intr_handle);
3047 free_intr_vec:
3048         rte_free(intr_handle->intr_vec);
3049         intr_handle->intr_vec = NULL;
3050 enable_intr:
3051         rte_intr_enable(intr_handle);
3052         return rc;
3053 }
3054
3055 static void ena_rx_queue_intr_set(struct rte_eth_dev *dev,
3056                                  uint16_t queue_id,
3057                                  bool unmask)
3058 {
3059         struct ena_adapter *adapter = dev->data->dev_private;
3060         struct ena_ring *rxq = &adapter->rx_ring[queue_id];
3061         struct ena_eth_io_intr_reg intr_reg;
3062
3063         ena_com_update_intr_reg(&intr_reg, 0, 0, unmask);
3064         ena_com_unmask_intr(rxq->ena_com_io_cq, &intr_reg);
3065 }
3066
3067 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
3068                                     uint16_t queue_id)
3069 {
3070         ena_rx_queue_intr_set(dev, queue_id, true);
3071
3072         return 0;
3073 }
3074
3075 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
3076                                      uint16_t queue_id)
3077 {
3078         ena_rx_queue_intr_set(dev, queue_id, false);
3079
3080         return 0;
3081 }
3082
3083 /*********************************************************************
3084  *  PMD configuration
3085  *********************************************************************/
3086 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3087         struct rte_pci_device *pci_dev)
3088 {
3089         return rte_eth_dev_pci_generic_probe(pci_dev,
3090                 sizeof(struct ena_adapter), eth_ena_dev_init);
3091 }
3092
3093 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
3094 {
3095         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
3096 }
3097
3098 static struct rte_pci_driver rte_ena_pmd = {
3099         .id_table = pci_id_ena_map,
3100         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3101                      RTE_PCI_DRV_WC_ACTIVATE,
3102         .probe = eth_ena_pci_probe,
3103         .remove = eth_ena_pci_remove,
3104 };
3105
3106 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
3107 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
3108 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
3109 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
3110 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE);
3111 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE);
3112 #ifdef RTE_ETHDEV_DEBUG_RX
3113 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, DEBUG);
3114 #endif
3115 #ifdef RTE_ETHDEV_DEBUG_TX
3116 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, DEBUG);
3117 #endif
3118 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, WARNING);
3119
3120 /******************************************************************************
3121  ******************************** AENQ Handlers *******************************
3122  *****************************************************************************/
3123 static void ena_update_on_link_change(void *adapter_data,
3124                                       struct ena_admin_aenq_entry *aenq_e)
3125 {
3126         struct rte_eth_dev *eth_dev = adapter_data;
3127         struct ena_adapter *adapter = eth_dev->data->dev_private;
3128         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
3129         uint32_t status;
3130
3131         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
3132
3133         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
3134         adapter->link_status = status;
3135
3136         ena_link_update(eth_dev, 0);
3137         rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3138 }
3139
3140 static void ena_notification(void *adapter_data,
3141                              struct ena_admin_aenq_entry *aenq_e)
3142 {
3143         struct rte_eth_dev *eth_dev = adapter_data;
3144         struct ena_adapter *adapter = eth_dev->data->dev_private;
3145         struct ena_admin_ena_hw_hints *hints;
3146
3147         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
3148                 PMD_DRV_LOG(WARNING, "Invalid AENQ group: %x. Expected: %x\n",
3149                         aenq_e->aenq_common_desc.group,
3150                         ENA_ADMIN_NOTIFICATION);
3151
3152         switch (aenq_e->aenq_common_desc.syndrome) {
3153         case ENA_ADMIN_UPDATE_HINTS:
3154                 hints = (struct ena_admin_ena_hw_hints *)
3155                         (&aenq_e->inline_data_w4);
3156                 ena_update_hints(adapter, hints);
3157                 break;
3158         default:
3159                 PMD_DRV_LOG(ERR, "Invalid AENQ notification link state: %d\n",
3160                         aenq_e->aenq_common_desc.syndrome);
3161         }
3162 }
3163
3164 static void ena_keep_alive(void *adapter_data,
3165                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
3166 {
3167         struct rte_eth_dev *eth_dev = adapter_data;
3168         struct ena_adapter *adapter = eth_dev->data->dev_private;
3169         struct ena_admin_aenq_keep_alive_desc *desc;
3170         uint64_t rx_drops;
3171         uint64_t tx_drops;
3172
3173         adapter->timestamp_wd = rte_get_timer_cycles();
3174
3175         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
3176         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
3177         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
3178
3179         adapter->drv_stats->rx_drops = rx_drops;
3180         adapter->dev_stats.tx_drops = tx_drops;
3181 }
3182
3183 /**
3184  * This handler will called for unknown event group or unimplemented handlers
3185  **/
3186 static void unimplemented_aenq_handler(__rte_unused void *data,
3187                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
3188 {
3189         PMD_DRV_LOG(ERR,
3190                 "Unknown event was received or event with unimplemented handler\n");
3191 }
3192
3193 static struct ena_aenq_handlers aenq_handlers = {
3194         .handlers = {
3195                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3196                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3197                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3198         },
3199         .unimplemented_handler = unimplemented_aenq_handler
3200 };