drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_ether.h>
   8 #include <rte_ethdev_driver.h>
   9 #include <rte_ethdev_pci.h>
  10 #include <rte_tcp.h>
  11 #include <rte_atomic.h>
  12 #include <rte_dev.h>
  13 #include <rte_errno.h>
  14 #include <rte_version.h>
  15 #include <rte_net.h>
  16 #include <rte_kvargs.h>
  17
  18 #include "ena_ethdev.h"
  19 #include "ena_logs.h"
  20 #include "ena_platform.h"
  21 #include "ena_com.h"
  22 #include "ena_eth_com.h"
  23
  24 #include <ena_common_defs.h>
  25 #include <ena_regs_defs.h>
  26 #include <ena_admin_defs.h>
  27 #include <ena_eth_io_defs.h>
  28
  29 #define DRV_MODULE_VER_MAJOR    2
  30 #define DRV_MODULE_VER_MINOR    0
  31 #define DRV_MODULE_VER_SUBMINOR 3
  32
  33 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  34 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  35 /*reverse version of ENA_IO_RXQ_IDX*/
  36 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  37
  38 /* While processing submitted and completed descriptors (rx and tx path
  39  * respectively) in a loop it is desired to:
  40  *  - perform batch submissions while populating sumbissmion queue
  41  *  - avoid blocking transmission of other packets during cleanup phase
  42  * Hence the utilization ratio of 1/8 of a queue size.
  43  */
  44 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  45
  46 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  47 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  48
  49 #define GET_L4_HDR_LEN(mbuf)                                    \
  50         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  51                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  52
  53 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  54 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  55 #define ENA_HASH_KEY_SIZE       40
  56 #define ETH_GSTRING_LEN 32
  57
  58 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  59
  60 #define ENA_MIN_RING_DESC       128
  61
  62 enum ethtool_stringset {
  63         ETH_SS_TEST             = 0,
  64         ETH_SS_STATS,
  65 };
  66
  67 struct ena_stats {
  68         char name[ETH_GSTRING_LEN];
  69         int stat_offset;
  70 };
  71
  72 #define ENA_STAT_ENTRY(stat, stat_type) { \
  73         .name = #stat, \
  74         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  75 }
  76
  77 #define ENA_STAT_RX_ENTRY(stat) \
  78         ENA_STAT_ENTRY(stat, rx)
  79
  80 #define ENA_STAT_TX_ENTRY(stat) \
  81         ENA_STAT_ENTRY(stat, tx)
  82
  83 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  84         ENA_STAT_ENTRY(stat, dev)
  85
  86 /* Device arguments */
  87 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  88
  89 /*
  90  * Each rte_memzone should have unique name.
  91  * To satisfy it, count number of allocation and add it to name.
  92  */
  93 rte_atomic32_t ena_alloc_cnt;
  94
  95 static const struct ena_stats ena_stats_global_strings[] = {
  96         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  97         ENA_STAT_GLOBAL_ENTRY(dev_start),
  98         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  99         ENA_STAT_GLOBAL_ENTRY(tx_drops),
 100 };
 101
 102 static const struct ena_stats ena_stats_tx_strings[] = {
 103         ENA_STAT_TX_ENTRY(cnt),
 104         ENA_STAT_TX_ENTRY(bytes),
 105         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 106         ENA_STAT_TX_ENTRY(linearize),
 107         ENA_STAT_TX_ENTRY(linearize_failed),
 108         ENA_STAT_TX_ENTRY(tx_poll),
 109         ENA_STAT_TX_ENTRY(doorbells),
 110         ENA_STAT_TX_ENTRY(bad_req_id),
 111         ENA_STAT_TX_ENTRY(available_desc),
 112 };
 113
 114 static const struct ena_stats ena_stats_rx_strings[] = {
 115         ENA_STAT_RX_ENTRY(cnt),
 116         ENA_STAT_RX_ENTRY(bytes),
 117         ENA_STAT_RX_ENTRY(refill_partial),
 118         ENA_STAT_RX_ENTRY(bad_csum),
 119         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 120         ENA_STAT_RX_ENTRY(bad_desc_num),
 121         ENA_STAT_RX_ENTRY(bad_req_id),
 122 };
 123
 124 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 125 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 126 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 127
 128 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 129                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 130                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 131                         DEV_TX_OFFLOAD_TCP_TSO)
 132 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 133                        PKT_TX_IP_CKSUM |\
 134                        PKT_TX_TCP_SEG)
 135
 136 /** Vendor ID used by Amazon devices */
 137 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 138 /** Amazon devices */
 139 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 140 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 141
 142 #define ENA_TX_OFFLOAD_MASK     (\
 143         PKT_TX_L4_MASK |         \
 144         PKT_TX_IPV6 |            \
 145         PKT_TX_IPV4 |            \
 146         PKT_TX_IP_CKSUM |        \
 147         PKT_TX_TCP_SEG)
 148
 149 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 150         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 151
 152 int ena_logtype_init;
 153 int ena_logtype_driver;
 154
 155 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
 156 int ena_logtype_rx;
 157 #endif
 158 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
 159 int ena_logtype_tx;
 160 #endif
 161 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
 162 int ena_logtype_tx_free;
 163 #endif
 164 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
 165 int ena_logtype_com;
 166 #endif
 167
 168 static const struct rte_pci_id pci_id_ena_map[] = {
 169         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 170         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 171         { .device_id = 0 },
 172 };
 173
 174 static struct ena_aenq_handlers aenq_handlers;
 175
 176 static int ena_device_init(struct ena_com_dev *ena_dev,
 177                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 178                            bool *wd_state);
 179 static int ena_dev_configure(struct rte_eth_dev *dev);
 180 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 181                                   uint16_t nb_pkts);
 182 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 183                 uint16_t nb_pkts);
 184 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 185                               uint16_t nb_desc, unsigned int socket_id,
 186                               const struct rte_eth_txconf *tx_conf);
 187 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 188                               uint16_t nb_desc, unsigned int socket_id,
 189                               const struct rte_eth_rxconf *rx_conf,
 190                               struct rte_mempool *mp);
 191 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 192                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 193 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 194 static void ena_init_rings(struct ena_adapter *adapter,
 195                            bool disable_meta_caching);
 196 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 197 static int ena_start(struct rte_eth_dev *dev);
 198 static void ena_stop(struct rte_eth_dev *dev);
 199 static void ena_close(struct rte_eth_dev *dev);
 200 static int ena_dev_reset(struct rte_eth_dev *dev);
 201 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 202 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 203 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 204 static void ena_rx_queue_release(void *queue);
 205 static void ena_tx_queue_release(void *queue);
 206 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 207 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 208 static int ena_link_update(struct rte_eth_dev *dev,
 209                            int wait_to_complete);
 210 static int ena_create_io_queue(struct ena_ring *ring);
 211 static void ena_queue_stop(struct ena_ring *ring);
 212 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 213                               enum ena_ring_type ring_type);
 214 static int ena_queue_start(struct ena_ring *ring);
 215 static int ena_queue_start_all(struct rte_eth_dev *dev,
 216                                enum ena_ring_type ring_type);
 217 static void ena_stats_restart(struct rte_eth_dev *dev);
 218 static int ena_infos_get(struct rte_eth_dev *dev,
 219                          struct rte_eth_dev_info *dev_info);
 220 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 221                                struct rte_eth_rss_reta_entry64 *reta_conf,
 222                                uint16_t reta_size);
 223 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 224                               struct rte_eth_rss_reta_entry64 *reta_conf,
 225                               uint16_t reta_size);
 226 static void ena_interrupt_handler_rte(void *cb_arg);
 227 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 228 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 229 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 230 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 231                                 struct rte_eth_xstat_name *xstats_names,
 232                                 unsigned int n);
 233 static int ena_xstats_get(struct rte_eth_dev *dev,
 234                           struct rte_eth_xstat *stats,
 235                           unsigned int n);
 236 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 237                                 const uint64_t *ids,
 238                                 uint64_t *values,
 239                                 unsigned int n);
 240 static int ena_process_bool_devarg(const char *key,
 241                                    const char *value,
 242                                    void *opaque);
 243 static int ena_parse_devargs(struct ena_adapter *adapter,
 244                              struct rte_devargs *devargs);
 245
 246 static const struct eth_dev_ops ena_dev_ops = {
 247         .dev_configure        = ena_dev_configure,
 248         .dev_infos_get        = ena_infos_get,
 249         .rx_queue_setup       = ena_rx_queue_setup,
 250         .tx_queue_setup       = ena_tx_queue_setup,
 251         .dev_start            = ena_start,
 252         .dev_stop             = ena_stop,
 253         .link_update          = ena_link_update,
 254         .stats_get            = ena_stats_get,
 255         .xstats_get_names     = ena_xstats_get_names,
 256         .xstats_get           = ena_xstats_get,
 257         .xstats_get_by_id     = ena_xstats_get_by_id,
 258         .mtu_set              = ena_mtu_set,
 259         .rx_queue_release     = ena_rx_queue_release,
 260         .tx_queue_release     = ena_tx_queue_release,
 261         .dev_close            = ena_close,
 262         .dev_reset            = ena_dev_reset,
 263         .reta_update          = ena_rss_reta_update,
 264         .reta_query           = ena_rss_reta_query,
 265 };
 266
 267 void ena_rss_key_fill(void *key, size_t size)
 268 {
 269         static bool key_generated;
 270         static uint8_t default_key[ENA_HASH_KEY_SIZE];
 271         size_t i;
 272
 273         RTE_ASSERT(size <= ENA_HASH_KEY_SIZE);
 274
 275         if (!key_generated) {
 276                 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i)
 277                         default_key[i] = rte_rand() & 0xff;
 278                 key_generated = true;
 279         }
 280
 281         rte_memcpy(key, default_key, size);
 282 }
 283
 284 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 285                                        struct ena_com_rx_ctx *ena_rx_ctx)
 286 {
 287         uint64_t ol_flags = 0;
 288         uint32_t packet_type = 0;
 289
 290         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 291                 packet_type |= RTE_PTYPE_L4_TCP;
 292         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 293                 packet_type |= RTE_PTYPE_L4_UDP;
 294
 295         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 296                 packet_type |= RTE_PTYPE_L3_IPV4;
 297         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 298                 packet_type |= RTE_PTYPE_L3_IPV6;
 299
 300         if (!ena_rx_ctx->l4_csum_checked)
 301                 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 302         else
 303                 if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag)
 304                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
 305                 else
 306                         ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 307
 308         if (unlikely(ena_rx_ctx->l3_csum_err))
 309                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 310
 311         mbuf->ol_flags = ol_flags;
 312         mbuf->packet_type = packet_type;
 313 }
 314
 315 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 316                                        struct ena_com_tx_ctx *ena_tx_ctx,
 317                                        uint64_t queue_offloads,
 318                                        bool disable_meta_caching)
 319 {
 320         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 321
 322         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 323             (queue_offloads & QUEUE_OFFLOADS)) {
 324                 /* check if TSO is required */
 325                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 326                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 327                         ena_tx_ctx->tso_enable = true;
 328
 329                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 330                 }
 331
 332                 /* check if L3 checksum is needed */
 333                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 334                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 335                         ena_tx_ctx->l3_csum_enable = true;
 336
 337                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 338                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 339                 } else {
 340                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 341
 342                         /* set don't fragment (DF) flag */
 343                         if (mbuf->packet_type &
 344                                 (RTE_PTYPE_L4_NONFRAG
 345                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 346                                 ena_tx_ctx->df = true;
 347                 }
 348
 349                 /* check if L4 checksum is needed */
 350                 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
 351                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 352                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 353                         ena_tx_ctx->l4_csum_enable = true;
 354                 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
 355                                 PKT_TX_UDP_CKSUM) &&
 356                                 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 357                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 358                         ena_tx_ctx->l4_csum_enable = true;
 359                 } else {
 360                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 361                         ena_tx_ctx->l4_csum_enable = false;
 362                 }
 363
 364                 ena_meta->mss = mbuf->tso_segsz;
 365                 ena_meta->l3_hdr_len = mbuf->l3_len;
 366                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 367
 368                 ena_tx_ctx->meta_valid = true;
 369         } else if (disable_meta_caching) {
 370                 memset(ena_meta, 0, sizeof(*ena_meta));
 371                 ena_tx_ctx->meta_valid = true;
 372         } else {
 373                 ena_tx_ctx->meta_valid = false;
 374         }
 375 }
 376
 377 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 378 {
 379         if (likely(req_id < rx_ring->ring_size))
 380                 return 0;
 381
 382         PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id);
 383
 384         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 385         rx_ring->adapter->trigger_reset = true;
 386         ++rx_ring->rx_stats.bad_req_id;
 387
 388         return -EFAULT;
 389 }
 390
 391 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 392 {
 393         struct ena_tx_buffer *tx_info = NULL;
 394
 395         if (likely(req_id < tx_ring->ring_size)) {
 396                 tx_info = &tx_ring->tx_buffer_info[req_id];
 397                 if (likely(tx_info->mbuf))
 398                         return 0;
 399         }
 400
 401         if (tx_info)
 402                 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 403         else
 404                 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 405
 406         /* Trigger device reset */
 407         ++tx_ring->tx_stats.bad_req_id;
 408         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 409         tx_ring->adapter->trigger_reset = true;
 410         return -EFAULT;
 411 }
 412
 413 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 414 {
 415         struct ena_admin_host_info *host_info;
 416         int rc;
 417
 418         /* Allocate only the host info */
 419         rc = ena_com_allocate_host_info(ena_dev);
 420         if (rc) {
 421                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 422                 return;
 423         }
 424
 425         host_info = ena_dev->host_attr.host_info;
 426
 427         host_info->os_type = ENA_ADMIN_OS_DPDK;
 428         host_info->kernel_ver = RTE_VERSION;
 429         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 430                 sizeof(host_info->kernel_ver_str));
 431         host_info->os_dist = RTE_VERSION;
 432         strlcpy((char *)host_info->os_dist_str, rte_version(),
 433                 sizeof(host_info->os_dist_str));
 434         host_info->driver_version =
 435                 (DRV_MODULE_VER_MAJOR) |
 436                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 437                 (DRV_MODULE_VER_SUBMINOR <<
 438                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 439         host_info->num_cpus = rte_lcore_count();
 440
 441         host_info->driver_supported_features =
 442                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
 443
 444         rc = ena_com_set_host_attributes(ena_dev);
 445         if (rc) {
 446                 if (rc == -ENA_COM_UNSUPPORTED)
 447                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 448                 else
 449                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 450
 451                 goto err;
 452         }
 453
 454         return;
 455
 456 err:
 457         ena_com_delete_host_info(ena_dev);
 458 }
 459
 460 /* This function calculates the number of xstats based on the current config */
 461 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
 462 {
 463         return ENA_STATS_ARRAY_GLOBAL +
 464                 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 465                 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 466 }
 467
 468 static void ena_config_debug_area(struct ena_adapter *adapter)
 469 {
 470         u32 debug_area_size;
 471         int rc, ss_count;
 472
 473         ss_count = ena_xstats_calc_num(adapter->rte_dev);
 474
 475         /* allocate 32 bytes for each string and 64bit for the value */
 476         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 477
 478         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 479         if (rc) {
 480                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 481                 return;
 482         }
 483
 484         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 485         if (rc) {
 486                 if (rc == -ENA_COM_UNSUPPORTED)
 487                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 488                 else
 489                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 490
 491                 goto err;
 492         }
 493
 494         return;
 495 err:
 496         ena_com_delete_debug_area(&adapter->ena_dev);
 497 }
 498
 499 static void ena_close(struct rte_eth_dev *dev)
 500 {
 501         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 502         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 503         struct ena_adapter *adapter = dev->data->dev_private;
 504
 505         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 506                 ena_stop(dev);
 507         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 508
 509         ena_rx_queue_release_all(dev);
 510         ena_tx_queue_release_all(dev);
 511
 512         rte_free(adapter->drv_stats);
 513         adapter->drv_stats = NULL;
 514
 515         rte_intr_disable(intr_handle);
 516         rte_intr_callback_unregister(intr_handle,
 517                                      ena_interrupt_handler_rte,
 518                                      adapter);
 519
 520         /*
 521          * MAC is not allocated dynamically. Setting NULL should prevent from
 522          * release of the resource in the rte_eth_dev_release_port().
 523          */
 524         dev->data->mac_addrs = NULL;
 525 }
 526
 527 static int
 528 ena_dev_reset(struct rte_eth_dev *dev)
 529 {
 530         int rc = 0;
 531
 532         ena_destroy_device(dev);
 533         rc = eth_ena_dev_init(dev);
 534         if (rc)
 535                 PMD_INIT_LOG(CRIT, "Cannot initialize device");
 536
 537         return rc;
 538 }
 539
 540 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 541                                struct rte_eth_rss_reta_entry64 *reta_conf,
 542                                uint16_t reta_size)
 543 {
 544         struct ena_adapter *adapter = dev->data->dev_private;
 545         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 546         int rc, i;
 547         u16 entry_value;
 548         int conf_idx;
 549         int idx;
 550
 551         if ((reta_size == 0) || (reta_conf == NULL))
 552                 return -EINVAL;
 553
 554         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 555                 PMD_DRV_LOG(WARNING,
 556                         "indirection table %d is bigger than supported (%d)\n",
 557                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 558                 return -EINVAL;
 559         }
 560
 561         for (i = 0 ; i < reta_size ; i++) {
 562                 /* each reta_conf is for 64 entries.
 563                  * to support 128 we use 2 conf of 64
 564                  */
 565                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 566                 idx = i % RTE_RETA_GROUP_SIZE;
 567                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 568                         entry_value =
 569                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 570
 571                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 572                                                                i,
 573                                                                entry_value);
 574                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 575                                 PMD_DRV_LOG(ERR,
 576                                         "Cannot fill indirect table\n");
 577                                 return rc;
 578                         }
 579                 }
 580         }
 581
 582         rc = ena_com_indirect_table_set(ena_dev);
 583         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 584                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 585                 return rc;
 586         }
 587
 588         PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries  for port %d\n",
 589                 __func__, reta_size, adapter->rte_dev->data->port_id);
 590
 591         return 0;
 592 }
 593
 594 /* Query redirection table. */
 595 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 596                               struct rte_eth_rss_reta_entry64 *reta_conf,
 597                               uint16_t reta_size)
 598 {
 599         struct ena_adapter *adapter = dev->data->dev_private;
 600         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 601         int rc;
 602         int i;
 603         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 604         int reta_conf_idx;
 605         int reta_idx;
 606
 607         if (reta_size == 0 || reta_conf == NULL ||
 608             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 609                 return -EINVAL;
 610
 611         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 612         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 613                 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
 614                 return -ENOTSUP;
 615         }
 616
 617         for (i = 0 ; i < reta_size ; i++) {
 618                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 619                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 620                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 621                         reta_conf[reta_conf_idx].reta[reta_idx] =
 622                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 623         }
 624
 625         return 0;
 626 }
 627
 628 static int ena_rss_init_default(struct ena_adapter *adapter)
 629 {
 630         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 631         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 632         int rc, i;
 633         u32 val;
 634
 635         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 636         if (unlikely(rc)) {
 637                 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
 638                 goto err_rss_init;
 639         }
 640
 641         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 642                 val = i % nb_rx_queues;
 643                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 644                                                        ENA_IO_RXQ_IDX(val));
 645                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 646                         PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
 647                         goto err_fill_indir;
 648                 }
 649         }
 650
 651         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 652                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 653         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 654                 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
 655                 goto err_fill_indir;
 656         }
 657
 658         rc = ena_com_set_default_hash_ctrl(ena_dev);
 659         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 660                 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
 661                 goto err_fill_indir;
 662         }
 663
 664         rc = ena_com_indirect_table_set(ena_dev);
 665         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 666                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 667                 goto err_fill_indir;
 668         }
 669         PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
 670                 adapter->rte_dev->data->port_id);
 671
 672         return 0;
 673
 674 err_fill_indir:
 675         ena_com_rss_destroy(ena_dev);
 676 err_rss_init:
 677
 678         return rc;
 679 }
 680
 681 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 682 {
 683         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 684         int nb_queues = dev->data->nb_rx_queues;
 685         int i;
 686
 687         for (i = 0; i < nb_queues; i++)
 688                 ena_rx_queue_release(queues[i]);
 689 }
 690
 691 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 692 {
 693         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 694         int nb_queues = dev->data->nb_tx_queues;
 695         int i;
 696
 697         for (i = 0; i < nb_queues; i++)
 698                 ena_tx_queue_release(queues[i]);
 699 }
 700
 701 static void ena_rx_queue_release(void *queue)
 702 {
 703         struct ena_ring *ring = (struct ena_ring *)queue;
 704
 705         /* Free ring resources */
 706         if (ring->rx_buffer_info)
 707                 rte_free(ring->rx_buffer_info);
 708         ring->rx_buffer_info = NULL;
 709
 710         if (ring->rx_refill_buffer)
 711                 rte_free(ring->rx_refill_buffer);
 712         ring->rx_refill_buffer = NULL;
 713
 714         if (ring->empty_rx_reqs)
 715                 rte_free(ring->empty_rx_reqs);
 716         ring->empty_rx_reqs = NULL;
 717
 718         ring->configured = 0;
 719
 720         PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
 721                 ring->port_id, ring->id);
 722 }
 723
 724 static void ena_tx_queue_release(void *queue)
 725 {
 726         struct ena_ring *ring = (struct ena_ring *)queue;
 727
 728         /* Free ring resources */
 729         if (ring->push_buf_intermediate_buf)
 730                 rte_free(ring->push_buf_intermediate_buf);
 731
 732         if (ring->tx_buffer_info)
 733                 rte_free(ring->tx_buffer_info);
 734
 735         if (ring->empty_tx_reqs)
 736                 rte_free(ring->empty_tx_reqs);
 737
 738         ring->empty_tx_reqs = NULL;
 739         ring->tx_buffer_info = NULL;
 740         ring->push_buf_intermediate_buf = NULL;
 741
 742         ring->configured = 0;
 743
 744         PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
 745                 ring->port_id, ring->id);
 746 }
 747
 748 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 749 {
 750         unsigned int i;
 751
 752         for (i = 0; i < ring->ring_size; ++i)
 753                 if (ring->rx_buffer_info[i]) {
 754                         rte_mbuf_raw_free(ring->rx_buffer_info[i]);
 755                         ring->rx_buffer_info[i] = NULL;
 756                 }
 757 }
 758
 759 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 760 {
 761         unsigned int i;
 762
 763         for (i = 0; i < ring->ring_size; ++i) {
 764                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 765
 766                 if (tx_buf->mbuf)
 767                         rte_pktmbuf_free(tx_buf->mbuf);
 768         }
 769 }
 770
 771 static int ena_link_update(struct rte_eth_dev *dev,
 772                            __rte_unused int wait_to_complete)
 773 {
 774         struct rte_eth_link *link = &dev->data->dev_link;
 775         struct ena_adapter *adapter = dev->data->dev_private;
 776
 777         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 778         link->link_speed = ETH_SPEED_NUM_NONE;
 779         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 780
 781         return 0;
 782 }
 783
 784 static int ena_queue_start_all(struct rte_eth_dev *dev,
 785                                enum ena_ring_type ring_type)
 786 {
 787         struct ena_adapter *adapter = dev->data->dev_private;
 788         struct ena_ring *queues = NULL;
 789         int nb_queues;
 790         int i = 0;
 791         int rc = 0;
 792
 793         if (ring_type == ENA_RING_TYPE_RX) {
 794                 queues = adapter->rx_ring;
 795                 nb_queues = dev->data->nb_rx_queues;
 796         } else {
 797                 queues = adapter->tx_ring;
 798                 nb_queues = dev->data->nb_tx_queues;
 799         }
 800         for (i = 0; i < nb_queues; i++) {
 801                 if (queues[i].configured) {
 802                         if (ring_type == ENA_RING_TYPE_RX) {
 803                                 ena_assert_msg(
 804                                         dev->data->rx_queues[i] == &queues[i],
 805                                         "Inconsistent state of rx queues\n");
 806                         } else {
 807                                 ena_assert_msg(
 808                                         dev->data->tx_queues[i] == &queues[i],
 809                                         "Inconsistent state of tx queues\n");
 810                         }
 811
 812                         rc = ena_queue_start(&queues[i]);
 813
 814                         if (rc) {
 815                                 PMD_INIT_LOG(ERR,
 816                                              "failed to start queue %d type(%d)",
 817                                              i, ring_type);
 818                                 goto err;
 819                         }
 820                 }
 821         }
 822
 823         return 0;
 824
 825 err:
 826         while (i--)
 827                 if (queues[i].configured)
 828                         ena_queue_stop(&queues[i]);
 829
 830         return rc;
 831 }
 832
 833 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 834 {
 835         uint32_t max_frame_len = adapter->max_mtu;
 836
 837         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 838             DEV_RX_OFFLOAD_JUMBO_FRAME)
 839                 max_frame_len =
 840                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 841
 842         return max_frame_len;
 843 }
 844
 845 static int ena_check_valid_conf(struct ena_adapter *adapter)
 846 {
 847         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 848
 849         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 850                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 851                                   "max mtu: %d, min mtu: %d",
 852                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 853                 return ENA_COM_UNSUPPORTED;
 854         }
 855
 856         return 0;
 857 }
 858
 859 static int
 860 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 861                        bool use_large_llq_hdr)
 862 {
 863         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 864         struct ena_com_dev *ena_dev = ctx->ena_dev;
 865         uint32_t max_tx_queue_size;
 866         uint32_t max_rx_queue_size;
 867
 868         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 869                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 870                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 871                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 872                         max_queue_ext->max_rx_sq_depth);
 873                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
 874
 875                 if (ena_dev->tx_mem_queue_type ==
 876                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 877                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 878                                 llq->max_llq_depth);
 879                 } else {
 880                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 881                                 max_queue_ext->max_tx_sq_depth);
 882                 }
 883
 884                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 885                         max_queue_ext->max_per_packet_rx_descs);
 886                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 887                         max_queue_ext->max_per_packet_tx_descs);
 888         } else {
 889                 struct ena_admin_queue_feature_desc *max_queues =
 890                         &ctx->get_feat_ctx->max_queues;
 891                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
 892                         max_queues->max_sq_depth);
 893                 max_tx_queue_size = max_queues->max_cq_depth;
 894
 895                 if (ena_dev->tx_mem_queue_type ==
 896                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 897                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 898                                 llq->max_llq_depth);
 899                 } else {
 900                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 901                                 max_queues->max_sq_depth);
 902                 }
 903
 904                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 905                         max_queues->max_packet_rx_descs);
 906                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 907                         max_queues->max_packet_tx_descs);
 908         }
 909
 910         /* Round down to the nearest power of 2 */
 911         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
 912         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
 913
 914         if (use_large_llq_hdr) {
 915                 if ((llq->entry_size_ctrl_supported &
 916                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
 917                     (ena_dev->tx_mem_queue_type ==
 918                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
 919                         max_tx_queue_size /= 2;
 920                         PMD_INIT_LOG(INFO,
 921                                 "Forcing large headers and decreasing maximum TX queue size to %d\n",
 922                                 max_tx_queue_size);
 923                 } else {
 924                         PMD_INIT_LOG(ERR,
 925                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
 926                 }
 927         }
 928
 929         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
 930                 PMD_INIT_LOG(ERR, "Invalid queue size");
 931                 return -EFAULT;
 932         }
 933
 934         ctx->max_tx_queue_size = max_tx_queue_size;
 935         ctx->max_rx_queue_size = max_rx_queue_size;
 936
 937         return 0;
 938 }
 939
 940 static void ena_stats_restart(struct rte_eth_dev *dev)
 941 {
 942         struct ena_adapter *adapter = dev->data->dev_private;
 943
 944         rte_atomic64_init(&adapter->drv_stats->ierrors);
 945         rte_atomic64_init(&adapter->drv_stats->oerrors);
 946         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 947         adapter->drv_stats->rx_drops = 0;
 948 }
 949
 950 static int ena_stats_get(struct rte_eth_dev *dev,
 951                           struct rte_eth_stats *stats)
 952 {
 953         struct ena_admin_basic_stats ena_stats;
 954         struct ena_adapter *adapter = dev->data->dev_private;
 955         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 956         int rc;
 957         int i;
 958         int max_rings_stats;
 959
 960         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 961                 return -ENOTSUP;
 962
 963         memset(&ena_stats, 0, sizeof(ena_stats));
 964         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 965         if (unlikely(rc)) {
 966                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 967                 return rc;
 968         }
 969
 970         /* Set of basic statistics from ENA */
 971         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 972                                           ena_stats.rx_pkts_low);
 973         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 974                                           ena_stats.tx_pkts_low);
 975         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 976                                         ena_stats.rx_bytes_low);
 977         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 978                                         ena_stats.tx_bytes_low);
 979
 980         /* Driver related stats */
 981         stats->imissed = adapter->drv_stats->rx_drops;
 982         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 983         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 984         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 985
 986         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
 987                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 988         for (i = 0; i < max_rings_stats; ++i) {
 989                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
 990
 991                 stats->q_ibytes[i] = rx_stats->bytes;
 992                 stats->q_ipackets[i] = rx_stats->cnt;
 993                 stats->q_errors[i] = rx_stats->bad_desc_num +
 994                         rx_stats->bad_req_id;
 995         }
 996
 997         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
 998                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 999         for (i = 0; i < max_rings_stats; ++i) {
1000                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1001
1002                 stats->q_obytes[i] = tx_stats->bytes;
1003                 stats->q_opackets[i] = tx_stats->cnt;
1004         }
1005
1006         return 0;
1007 }
1008
1009 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1010 {
1011         struct ena_adapter *adapter;
1012         struct ena_com_dev *ena_dev;
1013         int rc = 0;
1014
1015         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1016         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1017         adapter = dev->data->dev_private;
1018
1019         ena_dev = &adapter->ena_dev;
1020         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1021
1022         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1023                 PMD_DRV_LOG(ERR,
1024                         "Invalid MTU setting. new_mtu: %d "
1025                         "max mtu: %d min mtu: %d\n",
1026                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1027                 return -EINVAL;
1028         }
1029
1030         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1031         if (rc)
1032                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1033         else
1034                 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
1035
1036         return rc;
1037 }
1038
1039 static int ena_start(struct rte_eth_dev *dev)
1040 {
1041         struct ena_adapter *adapter = dev->data->dev_private;
1042         uint64_t ticks;
1043         int rc = 0;
1044
1045         rc = ena_check_valid_conf(adapter);
1046         if (rc)
1047                 return rc;
1048
1049         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1050         if (rc)
1051                 return rc;
1052
1053         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1054         if (rc)
1055                 goto err_start_tx;
1056
1057         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1058             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1059                 rc = ena_rss_init_default(adapter);
1060                 if (rc)
1061                         goto err_rss_init;
1062         }
1063
1064         ena_stats_restart(dev);
1065
1066         adapter->timestamp_wd = rte_get_timer_cycles();
1067         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1068
1069         ticks = rte_get_timer_hz();
1070         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1071                         ena_timer_wd_callback, adapter);
1072
1073         ++adapter->dev_stats.dev_start;
1074         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1075
1076         return 0;
1077
1078 err_rss_init:
1079         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1080 err_start_tx:
1081         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1082         return rc;
1083 }
1084
1085 static void ena_stop(struct rte_eth_dev *dev)
1086 {
1087         struct ena_adapter *adapter = dev->data->dev_private;
1088         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1089         int rc;
1090
1091         rte_timer_stop_sync(&adapter->timer_wd);
1092         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1093         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1094
1095         if (adapter->trigger_reset) {
1096                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1097                 if (rc)
1098                         PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1099         }
1100
1101         ++adapter->dev_stats.dev_stop;
1102         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1103 }
1104
1105 static int ena_create_io_queue(struct ena_ring *ring)
1106 {
1107         struct ena_adapter *adapter;
1108         struct ena_com_dev *ena_dev;
1109         struct ena_com_create_io_ctx ctx =
1110                 /* policy set to _HOST just to satisfy icc compiler */
1111                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1112                   0, 0, 0, 0, 0 };
1113         uint16_t ena_qid;
1114         unsigned int i;
1115         int rc;
1116
1117         adapter = ring->adapter;
1118         ena_dev = &adapter->ena_dev;
1119
1120         if (ring->type == ENA_RING_TYPE_TX) {
1121                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1122                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1123                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1124                 for (i = 0; i < ring->ring_size; i++)
1125                         ring->empty_tx_reqs[i] = i;
1126         } else {
1127                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1128                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1129                 for (i = 0; i < ring->ring_size; i++)
1130                         ring->empty_rx_reqs[i] = i;
1131         }
1132         ctx.queue_size = ring->ring_size;
1133         ctx.qid = ena_qid;
1134         ctx.msix_vector = -1; /* interrupts not used */
1135         ctx.numa_node = ring->numa_socket_id;
1136
1137         rc = ena_com_create_io_queue(ena_dev, &ctx);
1138         if (rc) {
1139                 PMD_DRV_LOG(ERR,
1140                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1141                         ring->id, ena_qid, rc);
1142                 return rc;
1143         }
1144
1145         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1146                                      &ring->ena_com_io_sq,
1147                                      &ring->ena_com_io_cq);
1148         if (rc) {
1149                 PMD_DRV_LOG(ERR,
1150                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1151                         ring->id, rc);
1152                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1153                 return rc;
1154         }
1155
1156         if (ring->type == ENA_RING_TYPE_TX)
1157                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1158
1159         return 0;
1160 }
1161
1162 static void ena_queue_stop(struct ena_ring *ring)
1163 {
1164         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1165
1166         if (ring->type == ENA_RING_TYPE_RX) {
1167                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1168                 ena_rx_queue_release_bufs(ring);
1169         } else {
1170                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1171                 ena_tx_queue_release_bufs(ring);
1172         }
1173 }
1174
1175 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1176                               enum ena_ring_type ring_type)
1177 {
1178         struct ena_adapter *adapter = dev->data->dev_private;
1179         struct ena_ring *queues = NULL;
1180         uint16_t nb_queues, i;
1181
1182         if (ring_type == ENA_RING_TYPE_RX) {
1183                 queues = adapter->rx_ring;
1184                 nb_queues = dev->data->nb_rx_queues;
1185         } else {
1186                 queues = adapter->tx_ring;
1187                 nb_queues = dev->data->nb_tx_queues;
1188         }
1189
1190         for (i = 0; i < nb_queues; ++i)
1191                 if (queues[i].configured)
1192                         ena_queue_stop(&queues[i]);
1193 }
1194
1195 static int ena_queue_start(struct ena_ring *ring)
1196 {
1197         int rc, bufs_num;
1198
1199         ena_assert_msg(ring->configured == 1,
1200                        "Trying to start unconfigured queue\n");
1201
1202         rc = ena_create_io_queue(ring);
1203         if (rc) {
1204                 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1205                 return rc;
1206         }
1207
1208         ring->next_to_clean = 0;
1209         ring->next_to_use = 0;
1210
1211         if (ring->type == ENA_RING_TYPE_TX) {
1212                 ring->tx_stats.available_desc =
1213                         ena_com_free_q_entries(ring->ena_com_io_sq);
1214                 return 0;
1215         }
1216
1217         bufs_num = ring->ring_size - 1;
1218         rc = ena_populate_rx_queue(ring, bufs_num);
1219         if (rc != bufs_num) {
1220                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1221                                          ENA_IO_RXQ_IDX(ring->id));
1222                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1223                 return ENA_COM_FAULT;
1224         }
1225
1226         return 0;
1227 }
1228
1229 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1230                               uint16_t queue_idx,
1231                               uint16_t nb_desc,
1232                               unsigned int socket_id,
1233                               const struct rte_eth_txconf *tx_conf)
1234 {
1235         struct ena_ring *txq = NULL;
1236         struct ena_adapter *adapter = dev->data->dev_private;
1237         unsigned int i;
1238
1239         txq = &adapter->tx_ring[queue_idx];
1240
1241         if (txq->configured) {
1242                 PMD_DRV_LOG(CRIT,
1243                         "API violation. Queue %d is already configured\n",
1244                         queue_idx);
1245                 return ENA_COM_FAULT;
1246         }
1247
1248         if (!rte_is_power_of_2(nb_desc)) {
1249                 PMD_DRV_LOG(ERR,
1250                         "Unsupported size of TX queue: %d is not a power of 2.\n",
1251                         nb_desc);
1252                 return -EINVAL;
1253         }
1254
1255         if (nb_desc > adapter->max_tx_ring_size) {
1256                 PMD_DRV_LOG(ERR,
1257                         "Unsupported size of TX queue (max size: %d)\n",
1258                         adapter->max_tx_ring_size);
1259                 return -EINVAL;
1260         }
1261
1262         if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1263                 nb_desc = adapter->max_tx_ring_size;
1264
1265         txq->port_id = dev->data->port_id;
1266         txq->next_to_clean = 0;
1267         txq->next_to_use = 0;
1268         txq->ring_size = nb_desc;
1269         txq->numa_socket_id = socket_id;
1270
1271         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1272                                           sizeof(struct ena_tx_buffer) *
1273                                           txq->ring_size,
1274                                           RTE_CACHE_LINE_SIZE);
1275         if (!txq->tx_buffer_info) {
1276                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1277                 return -ENOMEM;
1278         }
1279
1280         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1281                                          sizeof(u16) * txq->ring_size,
1282                                          RTE_CACHE_LINE_SIZE);
1283         if (!txq->empty_tx_reqs) {
1284                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1285                 rte_free(txq->tx_buffer_info);
1286                 return -ENOMEM;
1287         }
1288
1289         txq->push_buf_intermediate_buf =
1290                 rte_zmalloc("txq->push_buf_intermediate_buf",
1291                             txq->tx_max_header_size,
1292                             RTE_CACHE_LINE_SIZE);
1293         if (!txq->push_buf_intermediate_buf) {
1294                 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1295                 rte_free(txq->tx_buffer_info);
1296                 rte_free(txq->empty_tx_reqs);
1297                 return -ENOMEM;
1298         }
1299
1300         for (i = 0; i < txq->ring_size; i++)
1301                 txq->empty_tx_reqs[i] = i;
1302
1303         if (tx_conf != NULL) {
1304                 txq->offloads =
1305                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1306         }
1307         /* Store pointer to this queue in upper layer */
1308         txq->configured = 1;
1309         dev->data->tx_queues[queue_idx] = txq;
1310
1311         return 0;
1312 }
1313
1314 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1315                               uint16_t queue_idx,
1316                               uint16_t nb_desc,
1317                               unsigned int socket_id,
1318                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1319                               struct rte_mempool *mp)
1320 {
1321         struct ena_adapter *adapter = dev->data->dev_private;
1322         struct ena_ring *rxq = NULL;
1323         size_t buffer_size;
1324         int i;
1325
1326         rxq = &adapter->rx_ring[queue_idx];
1327         if (rxq->configured) {
1328                 PMD_DRV_LOG(CRIT,
1329                         "API violation. Queue %d is already configured\n",
1330                         queue_idx);
1331                 return ENA_COM_FAULT;
1332         }
1333
1334         if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1335                 nb_desc = adapter->max_rx_ring_size;
1336
1337         if (!rte_is_power_of_2(nb_desc)) {
1338                 PMD_DRV_LOG(ERR,
1339                         "Unsupported size of RX queue: %d is not a power of 2.\n",
1340                         nb_desc);
1341                 return -EINVAL;
1342         }
1343
1344         if (nb_desc > adapter->max_rx_ring_size) {
1345                 PMD_DRV_LOG(ERR,
1346                         "Unsupported size of RX queue (max size: %d)\n",
1347                         adapter->max_rx_ring_size);
1348                 return -EINVAL;
1349         }
1350
1351         /* ENA isn't supporting buffers smaller than 1400 bytes */
1352         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1353         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1354                 PMD_DRV_LOG(ERR,
1355                         "Unsupported size of RX buffer: %zu (min size: %d)\n",
1356                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1357                 return -EINVAL;
1358         }
1359
1360         rxq->port_id = dev->data->port_id;
1361         rxq->next_to_clean = 0;
1362         rxq->next_to_use = 0;
1363         rxq->ring_size = nb_desc;
1364         rxq->numa_socket_id = socket_id;
1365         rxq->mb_pool = mp;
1366
1367         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1368                                           sizeof(struct rte_mbuf *) * nb_desc,
1369                                           RTE_CACHE_LINE_SIZE);
1370         if (!rxq->rx_buffer_info) {
1371                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1372                 return -ENOMEM;
1373         }
1374
1375         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1376                                             sizeof(struct rte_mbuf *) * nb_desc,
1377                                             RTE_CACHE_LINE_SIZE);
1378
1379         if (!rxq->rx_refill_buffer) {
1380                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1381                 rte_free(rxq->rx_buffer_info);
1382                 rxq->rx_buffer_info = NULL;
1383                 return -ENOMEM;
1384         }
1385
1386         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1387                                          sizeof(uint16_t) * nb_desc,
1388                                          RTE_CACHE_LINE_SIZE);
1389         if (!rxq->empty_rx_reqs) {
1390                 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1391                 rte_free(rxq->rx_buffer_info);
1392                 rxq->rx_buffer_info = NULL;
1393                 rte_free(rxq->rx_refill_buffer);
1394                 rxq->rx_refill_buffer = NULL;
1395                 return -ENOMEM;
1396         }
1397
1398         for (i = 0; i < nb_desc; i++)
1399                 rxq->empty_rx_reqs[i] = i;
1400
1401         /* Store pointer to this queue in upper layer */
1402         rxq->configured = 1;
1403         dev->data->rx_queues[queue_idx] = rxq;
1404
1405         return 0;
1406 }
1407
1408 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1409 {
1410         unsigned int i;
1411         int rc;
1412         uint16_t ring_size = rxq->ring_size;
1413         uint16_t ring_mask = ring_size - 1;
1414         uint16_t next_to_use = rxq->next_to_use;
1415         uint16_t in_use, req_id;
1416         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1417
1418         if (unlikely(!count))
1419                 return 0;
1420
1421         in_use = rxq->next_to_use - rxq->next_to_clean;
1422         ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n");
1423
1424         /* get resources for incoming packets */
1425         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1426         if (unlikely(rc < 0)) {
1427                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1428                 ++rxq->rx_stats.mbuf_alloc_fail;
1429                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1430                 return 0;
1431         }
1432
1433         for (i = 0; i < count; i++) {
1434                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1435                 struct rte_mbuf *mbuf = mbufs[i];
1436                 struct ena_com_buf ebuf;
1437
1438                 if (likely((i + 4) < count))
1439                         rte_prefetch0(mbufs[i + 4]);
1440
1441                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1442                 rc = validate_rx_req_id(rxq, req_id);
1443                 if (unlikely(rc < 0))
1444                         break;
1445                 rxq->rx_buffer_info[req_id] = mbuf;
1446
1447                 /* prepare physical address for DMA transaction */
1448                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1449                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1450                 /* pass resource to device */
1451                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1452                                                 &ebuf, req_id);
1453                 if (unlikely(rc)) {
1454                         PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1455                         rxq->rx_buffer_info[req_id] = NULL;
1456                         break;
1457                 }
1458                 next_to_use++;
1459         }
1460
1461         if (unlikely(i < count)) {
1462                 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1463                         "buffers (from %d)\n", rxq->id, i, count);
1464                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1465                                      count - i);
1466                 ++rxq->rx_stats.refill_partial;
1467         }
1468
1469         /* When we submitted free recources to device... */
1470         if (likely(i > 0)) {
1471                 /* ...let HW know that it can fill buffers with data. */
1472                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1473
1474                 rxq->next_to_use = next_to_use;
1475         }
1476
1477         return i;
1478 }
1479
1480 static int ena_device_init(struct ena_com_dev *ena_dev,
1481                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1482                            bool *wd_state)
1483 {
1484         uint32_t aenq_groups;
1485         int rc;
1486         bool readless_supported;
1487
1488         /* Initialize mmio registers */
1489         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1490         if (rc) {
1491                 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1492                 return rc;
1493         }
1494
1495         /* The PCIe configuration space revision id indicate if mmio reg
1496          * read is disabled.
1497          */
1498         readless_supported =
1499                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1500                                & ENA_MMIO_DISABLE_REG_READ);
1501         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1502
1503         /* reset device */
1504         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1505         if (rc) {
1506                 PMD_DRV_LOG(ERR, "cannot reset device\n");
1507                 goto err_mmio_read_less;
1508         }
1509
1510         /* check FW version */
1511         rc = ena_com_validate_version(ena_dev);
1512         if (rc) {
1513                 PMD_DRV_LOG(ERR, "device version is too low\n");
1514                 goto err_mmio_read_less;
1515         }
1516
1517         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1518
1519         /* ENA device administration layer init */
1520         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1521         if (rc) {
1522                 PMD_DRV_LOG(ERR,
1523                         "cannot initialize ena admin queue with device\n");
1524                 goto err_mmio_read_less;
1525         }
1526
1527         /* To enable the msix interrupts the driver needs to know the number
1528          * of queues. So the driver uses polling mode to retrieve this
1529          * information.
1530          */
1531         ena_com_set_admin_polling_mode(ena_dev, true);
1532
1533         ena_config_host_info(ena_dev);
1534
1535         /* Get Device Attributes and features */
1536         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1537         if (rc) {
1538                 PMD_DRV_LOG(ERR,
1539                         "cannot get attribute for ena device rc= %d\n", rc);
1540                 goto err_admin_init;
1541         }
1542
1543         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1544                       BIT(ENA_ADMIN_NOTIFICATION) |
1545                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1546                       BIT(ENA_ADMIN_FATAL_ERROR) |
1547                       BIT(ENA_ADMIN_WARNING);
1548
1549         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1550         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1551         if (rc) {
1552                 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1553                 goto err_admin_init;
1554         }
1555
1556         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1557
1558         return 0;
1559
1560 err_admin_init:
1561         ena_com_admin_destroy(ena_dev);
1562
1563 err_mmio_read_less:
1564         ena_com_mmio_reg_read_request_destroy(ena_dev);
1565
1566         return rc;
1567 }
1568
1569 static void ena_interrupt_handler_rte(void *cb_arg)
1570 {
1571         struct ena_adapter *adapter = cb_arg;
1572         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1573
1574         ena_com_admin_q_comp_intr_handler(ena_dev);
1575         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1576                 ena_com_aenq_intr_handler(ena_dev, adapter);
1577 }
1578
1579 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1580 {
1581         if (!adapter->wd_state)
1582                 return;
1583
1584         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1585                 return;
1586
1587         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1588             adapter->keep_alive_timeout)) {
1589                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1590                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1591                 adapter->trigger_reset = true;
1592                 ++adapter->dev_stats.wd_expired;
1593         }
1594 }
1595
1596 /* Check if admin queue is enabled */
1597 static void check_for_admin_com_state(struct ena_adapter *adapter)
1598 {
1599         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1600                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1601                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1602                 adapter->trigger_reset = true;
1603         }
1604 }
1605
1606 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1607                                   void *arg)
1608 {
1609         struct ena_adapter *adapter = arg;
1610         struct rte_eth_dev *dev = adapter->rte_dev;
1611
1612         check_for_missing_keep_alive(adapter);
1613         check_for_admin_com_state(adapter);
1614
1615         if (unlikely(adapter->trigger_reset)) {
1616                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1617                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1618                         NULL);
1619         }
1620 }
1621
1622 static inline void
1623 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1624                                struct ena_admin_feature_llq_desc *llq,
1625                                bool use_large_llq_hdr)
1626 {
1627         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1628         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1629         llq_config->llq_num_decs_before_header =
1630                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1631
1632         if (use_large_llq_hdr &&
1633             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1634                 llq_config->llq_ring_entry_size =
1635                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1636                 llq_config->llq_ring_entry_size_value = 256;
1637         } else {
1638                 llq_config->llq_ring_entry_size =
1639                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1640                 llq_config->llq_ring_entry_size_value = 128;
1641         }
1642 }
1643
1644 static int
1645 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1646                                 struct ena_com_dev *ena_dev,
1647                                 struct ena_admin_feature_llq_desc *llq,
1648                                 struct ena_llq_configurations *llq_default_configurations)
1649 {
1650         int rc;
1651         u32 llq_feature_mask;
1652
1653         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1654         if (!(ena_dev->supported_features & llq_feature_mask)) {
1655                 PMD_DRV_LOG(INFO,
1656                         "LLQ is not supported. Fallback to host mode policy.\n");
1657                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1658                 return 0;
1659         }
1660
1661         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1662         if (unlikely(rc)) {
1663                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1664                         "Fallback to host mode policy.");
1665                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1666                 return 0;
1667         }
1668
1669         /* Nothing to config, exit */
1670         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1671                 return 0;
1672
1673         if (!adapter->dev_mem_base) {
1674                 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1675                         "Fallback to host mode policy.\n.");
1676                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1677                 return 0;
1678         }
1679
1680         ena_dev->mem_bar = adapter->dev_mem_base;
1681
1682         return 0;
1683 }
1684
1685 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1686         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1687 {
1688         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1689
1690         /* Regular queues capabilities */
1691         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1692                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1693                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1694                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1695                                     max_queue_ext->max_rx_cq_num);
1696                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1697                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1698         } else {
1699                 struct ena_admin_queue_feature_desc *max_queues =
1700                         &get_feat_ctx->max_queues;
1701                 io_tx_sq_num = max_queues->max_sq_num;
1702                 io_tx_cq_num = max_queues->max_cq_num;
1703                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1704         }
1705
1706         /* In case of LLQ use the llq number in the get feature cmd */
1707         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1708                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1709
1710         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1711         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1712         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1713
1714         if (unlikely(max_num_io_queues == 0)) {
1715                 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1716                 return -EFAULT;
1717         }
1718
1719         return max_num_io_queues;
1720 }
1721
1722 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1723 {
1724         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1725         struct rte_pci_device *pci_dev;
1726         struct rte_intr_handle *intr_handle;
1727         struct ena_adapter *adapter = eth_dev->data->dev_private;
1728         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1729         struct ena_com_dev_get_features_ctx get_feat_ctx;
1730         struct ena_llq_configurations llq_config;
1731         const char *queue_type_str;
1732         uint32_t max_num_io_queues;
1733         int rc;
1734         static int adapters_found;
1735         bool disable_meta_caching;
1736         bool wd_state;
1737
1738         eth_dev->dev_ops = &ena_dev_ops;
1739         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1740         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1741         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1742
1743         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1744                 return 0;
1745
1746         memset(adapter, 0, sizeof(struct ena_adapter));
1747         ena_dev = &adapter->ena_dev;
1748
1749         adapter->rte_eth_dev_data = eth_dev->data;
1750         adapter->rte_dev = eth_dev;
1751
1752         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1753         adapter->pdev = pci_dev;
1754
1755         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1756                      pci_dev->addr.domain,
1757                      pci_dev->addr.bus,
1758                      pci_dev->addr.devid,
1759                      pci_dev->addr.function);
1760
1761         intr_handle = &pci_dev->intr_handle;
1762
1763         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1764         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1765
1766         if (!adapter->regs) {
1767                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1768                              ENA_REGS_BAR);
1769                 return -ENXIO;
1770         }
1771
1772         ena_dev->reg_bar = adapter->regs;
1773         ena_dev->dmadev = adapter->pdev;
1774
1775         adapter->id_number = adapters_found;
1776
1777         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1778                  adapter->id_number);
1779
1780         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1781         if (rc != 0) {
1782                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1783                 goto err;
1784         }
1785
1786         /* device specific initialization routine */
1787         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1788         if (rc) {
1789                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1790                 goto err;
1791         }
1792         adapter->wd_state = wd_state;
1793
1794         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1795                 adapter->use_large_llq_hdr);
1796         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1797                                              &get_feat_ctx.llq, &llq_config);
1798         if (unlikely(rc)) {
1799                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1800                 return rc;
1801         }
1802
1803         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1804                 queue_type_str = "Regular";
1805         else
1806                 queue_type_str = "Low latency";
1807         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1808
1809         calc_queue_ctx.ena_dev = ena_dev;
1810         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1811
1812         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1813         rc = ena_calc_io_queue_size(&calc_queue_ctx,
1814                 adapter->use_large_llq_hdr);
1815         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1816                 rc = -EFAULT;
1817                 goto err_device_destroy;
1818         }
1819
1820         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1821         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1822         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1823         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1824         adapter->max_num_io_queues = max_num_io_queues;
1825
1826         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1827                 disable_meta_caching =
1828                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1829                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
1830         } else {
1831                 disable_meta_caching = false;
1832         }
1833
1834         /* prepare ring structures */
1835         ena_init_rings(adapter, disable_meta_caching);
1836
1837         ena_config_debug_area(adapter);
1838
1839         /* Set max MTU for this device */
1840         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1841
1842         /* set device support for offloads */
1843         adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1844                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1845         adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1846                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1847         adapter->offloads.rx_csum_supported =
1848                 (get_feat_ctx.offload.rx_supported &
1849                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1850
1851         /* Copy MAC address and point DPDK to it */
1852         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1853         rte_ether_addr_copy((struct rte_ether_addr *)
1854                         get_feat_ctx.dev_attr.mac_addr,
1855                         (struct rte_ether_addr *)adapter->mac_addr);
1856
1857         /*
1858          * Pass the information to the rte_eth_dev_close() that it should also
1859          * release the private port resources.
1860          */
1861         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1862
1863         adapter->drv_stats = rte_zmalloc("adapter stats",
1864                                          sizeof(*adapter->drv_stats),
1865                                          RTE_CACHE_LINE_SIZE);
1866         if (!adapter->drv_stats) {
1867                 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1868                 rc = -ENOMEM;
1869                 goto err_delete_debug_area;
1870         }
1871
1872         rte_intr_callback_register(intr_handle,
1873                                    ena_interrupt_handler_rte,
1874                                    adapter);
1875         rte_intr_enable(intr_handle);
1876         ena_com_set_admin_polling_mode(ena_dev, false);
1877         ena_com_admin_aenq_enable(ena_dev);
1878
1879         if (adapters_found == 0)
1880                 rte_timer_subsystem_init();
1881         rte_timer_init(&adapter->timer_wd);
1882
1883         adapters_found++;
1884         adapter->state = ENA_ADAPTER_STATE_INIT;
1885
1886         return 0;
1887
1888 err_delete_debug_area:
1889         ena_com_delete_debug_area(ena_dev);
1890
1891 err_device_destroy:
1892         ena_com_delete_host_info(ena_dev);
1893         ena_com_admin_destroy(ena_dev);
1894
1895 err:
1896         return rc;
1897 }
1898
1899 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1900 {
1901         struct ena_adapter *adapter = eth_dev->data->dev_private;
1902         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1903
1904         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1905                 return;
1906
1907         ena_com_set_admin_running_state(ena_dev, false);
1908
1909         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1910                 ena_close(eth_dev);
1911
1912         ena_com_delete_debug_area(ena_dev);
1913         ena_com_delete_host_info(ena_dev);
1914
1915         ena_com_abort_admin_commands(ena_dev);
1916         ena_com_wait_for_abort_completion(ena_dev);
1917         ena_com_admin_destroy(ena_dev);
1918         ena_com_mmio_reg_read_request_destroy(ena_dev);
1919
1920         adapter->state = ENA_ADAPTER_STATE_FREE;
1921 }
1922
1923 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1924 {
1925         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1926                 return 0;
1927
1928         ena_destroy_device(eth_dev);
1929
1930         eth_dev->dev_ops = NULL;
1931         eth_dev->rx_pkt_burst = NULL;
1932         eth_dev->tx_pkt_burst = NULL;
1933         eth_dev->tx_pkt_prepare = NULL;
1934
1935         return 0;
1936 }
1937
1938 static int ena_dev_configure(struct rte_eth_dev *dev)
1939 {
1940         struct ena_adapter *adapter = dev->data->dev_private;
1941
1942         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1943
1944         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1945         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1946         return 0;
1947 }
1948
1949 static void ena_init_rings(struct ena_adapter *adapter,
1950                            bool disable_meta_caching)
1951 {
1952         size_t i;
1953
1954         for (i = 0; i < adapter->max_num_io_queues; i++) {
1955                 struct ena_ring *ring = &adapter->tx_ring[i];
1956
1957                 ring->configured = 0;
1958                 ring->type = ENA_RING_TYPE_TX;
1959                 ring->adapter = adapter;
1960                 ring->id = i;
1961                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1962                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1963                 ring->sgl_size = adapter->max_tx_sgl_size;
1964                 ring->disable_meta_caching = disable_meta_caching;
1965         }
1966
1967         for (i = 0; i < adapter->max_num_io_queues; i++) {
1968                 struct ena_ring *ring = &adapter->rx_ring[i];
1969
1970                 ring->configured = 0;
1971                 ring->type = ENA_RING_TYPE_RX;
1972                 ring->adapter = adapter;
1973                 ring->id = i;
1974                 ring->sgl_size = adapter->max_rx_sgl_size;
1975         }
1976 }
1977
1978 static int ena_infos_get(struct rte_eth_dev *dev,
1979                           struct rte_eth_dev_info *dev_info)
1980 {
1981         struct ena_adapter *adapter;
1982         struct ena_com_dev *ena_dev;
1983         uint64_t rx_feat = 0, tx_feat = 0;
1984
1985         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1986         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1987         adapter = dev->data->dev_private;
1988
1989         ena_dev = &adapter->ena_dev;
1990         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1991
1992         dev_info->speed_capa =
1993                         ETH_LINK_SPEED_1G   |
1994                         ETH_LINK_SPEED_2_5G |
1995                         ETH_LINK_SPEED_5G   |
1996                         ETH_LINK_SPEED_10G  |
1997                         ETH_LINK_SPEED_25G  |
1998                         ETH_LINK_SPEED_40G  |
1999                         ETH_LINK_SPEED_50G  |
2000                         ETH_LINK_SPEED_100G;
2001
2002         /* Set Tx & Rx features available for device */
2003         if (adapter->offloads.tso4_supported)
2004                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
2005
2006         if (adapter->offloads.tx_csum_supported)
2007                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
2008                         DEV_TX_OFFLOAD_UDP_CKSUM |
2009                         DEV_TX_OFFLOAD_TCP_CKSUM;
2010
2011         if (adapter->offloads.rx_csum_supported)
2012                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
2013                         DEV_RX_OFFLOAD_UDP_CKSUM  |
2014                         DEV_RX_OFFLOAD_TCP_CKSUM;
2015
2016         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2017
2018         /* Inform framework about available features */
2019         dev_info->rx_offload_capa = rx_feat;
2020         dev_info->rx_queue_offload_capa = rx_feat;
2021         dev_info->tx_offload_capa = tx_feat;
2022         dev_info->tx_queue_offload_capa = tx_feat;
2023
2024         dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
2025                                            ETH_RSS_UDP;
2026
2027         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2028         dev_info->max_rx_pktlen  = adapter->max_mtu;
2029         dev_info->max_mac_addrs = 1;
2030
2031         dev_info->max_rx_queues = adapter->max_num_io_queues;
2032         dev_info->max_tx_queues = adapter->max_num_io_queues;
2033         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2034
2035         adapter->tx_supported_offloads = tx_feat;
2036         adapter->rx_supported_offloads = rx_feat;
2037
2038         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2039         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2040         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2041                                         adapter->max_rx_sgl_size);
2042         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2043                                         adapter->max_rx_sgl_size);
2044
2045         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2046         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2047         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2048                                         adapter->max_tx_sgl_size);
2049         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2050                                         adapter->max_tx_sgl_size);
2051
2052         return 0;
2053 }
2054
2055 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2056                                   uint16_t nb_pkts)
2057 {
2058         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2059         unsigned int ring_size = rx_ring->ring_size;
2060         unsigned int ring_mask = ring_size - 1;
2061         uint16_t next_to_clean = rx_ring->next_to_clean;
2062         uint16_t desc_in_use = 0;
2063         uint16_t req_id;
2064         unsigned int recv_idx = 0;
2065         struct rte_mbuf *mbuf = NULL;
2066         struct rte_mbuf *mbuf_head = NULL;
2067         struct rte_mbuf *mbuf_prev = NULL;
2068         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
2069         unsigned int completed;
2070
2071         struct ena_com_rx_ctx ena_rx_ctx;
2072         int rc = 0;
2073
2074         /* Check adapter state */
2075         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2076                 PMD_DRV_LOG(ALERT,
2077                         "Trying to receive pkts while device is NOT running\n");
2078                 return 0;
2079         }
2080
2081         desc_in_use = rx_ring->next_to_use - next_to_clean;
2082         if (unlikely(nb_pkts > desc_in_use))
2083                 nb_pkts = desc_in_use;
2084
2085         for (completed = 0; completed < nb_pkts; completed++) {
2086                 int segments = 0;
2087
2088                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2089                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2090                 ena_rx_ctx.descs = 0;
2091                 ena_rx_ctx.pkt_offset = 0;
2092                 /* receive packet context */
2093                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2094                                     rx_ring->ena_com_io_sq,
2095                                     &ena_rx_ctx);
2096                 if (unlikely(rc)) {
2097                         PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2098                         rx_ring->adapter->reset_reason =
2099                                 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2100                         rx_ring->adapter->trigger_reset = true;
2101                         ++rx_ring->rx_stats.bad_desc_num;
2102                         return 0;
2103                 }
2104
2105                 if (unlikely(ena_rx_ctx.descs == 0))
2106                         break;
2107
2108                 while (segments < ena_rx_ctx.descs) {
2109                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
2110                         rc = validate_rx_req_id(rx_ring, req_id);
2111                         if (unlikely(rc)) {
2112                                 if (segments != 0)
2113                                         rte_mbuf_raw_free(mbuf_head);
2114                                 break;
2115                         }
2116
2117                         mbuf = rx_buff_info[req_id];
2118                         rx_buff_info[req_id] = NULL;
2119                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
2120                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2121                         mbuf->refcnt = 1;
2122                         mbuf->next = NULL;
2123                         if (unlikely(segments == 0)) {
2124                                 mbuf->nb_segs = ena_rx_ctx.descs;
2125                                 mbuf->port = rx_ring->port_id;
2126                                 mbuf->pkt_len = 0;
2127                                 mbuf->data_off += ena_rx_ctx.pkt_offset;
2128                                 mbuf_head = mbuf;
2129                         } else {
2130                                 /* for multi-segment pkts create mbuf chain */
2131                                 mbuf_prev->next = mbuf;
2132                         }
2133                         mbuf_head->pkt_len += mbuf->data_len;
2134
2135                         mbuf_prev = mbuf;
2136                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
2137                                 req_id;
2138                         segments++;
2139                         next_to_clean++;
2140                 }
2141                 if (unlikely(rc))
2142                         break;
2143
2144                 /* fill mbuf attributes if any */
2145                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
2146
2147                 if (unlikely(mbuf_head->ol_flags &
2148                                 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2149                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2150                         ++rx_ring->rx_stats.bad_csum;
2151                 }
2152
2153                 mbuf_head->hash.rss = ena_rx_ctx.hash;
2154
2155                 /* pass to DPDK application head mbuf */
2156                 rx_pkts[recv_idx] = mbuf_head;
2157                 recv_idx++;
2158                 rx_ring->rx_stats.bytes += mbuf_head->pkt_len;
2159         }
2160
2161         rx_ring->rx_stats.cnt += recv_idx;
2162         rx_ring->next_to_clean = next_to_clean;
2163
2164         desc_in_use = desc_in_use - completed + 1;
2165         /* Burst refill to save doorbells, memory barriers, const interval */
2166         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size)) {
2167                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2168                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
2169         }
2170
2171         return recv_idx;
2172 }
2173
2174 static uint16_t
2175 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2176                 uint16_t nb_pkts)
2177 {
2178         int32_t ret;
2179         uint32_t i;
2180         struct rte_mbuf *m;
2181         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2182         struct rte_ipv4_hdr *ip_hdr;
2183         uint64_t ol_flags;
2184         uint16_t frag_field;
2185
2186         for (i = 0; i != nb_pkts; i++) {
2187                 m = tx_pkts[i];
2188                 ol_flags = m->ol_flags;
2189
2190                 if (!(ol_flags & PKT_TX_IPV4))
2191                         continue;
2192
2193                 /* If there was not L2 header length specified, assume it is
2194                  * length of the ethernet header.
2195                  */
2196                 if (unlikely(m->l2_len == 0))
2197                         m->l2_len = sizeof(struct rte_ether_hdr);
2198
2199                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2200                                                  m->l2_len);
2201                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2202
2203                 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2204                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2205
2206                         /* If IPv4 header has DF flag enabled and TSO support is
2207                          * disabled, partial chcecksum should not be calculated.
2208                          */
2209                         if (!tx_ring->adapter->offloads.tso4_supported)
2210                                 continue;
2211                 }
2212
2213                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2214                                 (ol_flags & PKT_TX_L4_MASK) ==
2215                                 PKT_TX_SCTP_CKSUM) {
2216                         rte_errno = ENOTSUP;
2217                         return i;
2218                 }
2219
2220 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2221                 ret = rte_validate_tx_offload(m);
2222                 if (ret != 0) {
2223                         rte_errno = -ret;
2224                         return i;
2225                 }
2226 #endif
2227
2228                 /* In case we are supposed to TSO and have DF not set (DF=0)
2229                  * hardware must be provided with partial checksum, otherwise
2230                  * it will take care of necessary calculations.
2231                  */
2232
2233                 ret = rte_net_intel_cksum_flags_prepare(m,
2234                         ol_flags & ~PKT_TX_TCP_SEG);
2235                 if (ret != 0) {
2236                         rte_errno = -ret;
2237                         return i;
2238                 }
2239         }
2240
2241         return i;
2242 }
2243
2244 static void ena_update_hints(struct ena_adapter *adapter,
2245                              struct ena_admin_ena_hw_hints *hints)
2246 {
2247         if (hints->admin_completion_tx_timeout)
2248                 adapter->ena_dev.admin_queue.completion_timeout =
2249                         hints->admin_completion_tx_timeout * 1000;
2250
2251         if (hints->mmio_read_timeout)
2252                 /* convert to usec */
2253                 adapter->ena_dev.mmio_read.reg_read_to =
2254                         hints->mmio_read_timeout * 1000;
2255
2256         if (hints->driver_watchdog_timeout) {
2257                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2258                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2259                 else
2260                         // Convert msecs to ticks
2261                         adapter->keep_alive_timeout =
2262                                 (hints->driver_watchdog_timeout *
2263                                 rte_get_timer_hz()) / 1000;
2264         }
2265 }
2266
2267 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2268                                         struct rte_mbuf *mbuf)
2269 {
2270         struct ena_com_dev *ena_dev;
2271         int num_segments, header_len, rc;
2272
2273         ena_dev = &tx_ring->adapter->ena_dev;
2274         num_segments = mbuf->nb_segs;
2275         header_len = mbuf->data_len;
2276
2277         if (likely(num_segments < tx_ring->sgl_size))
2278                 return 0;
2279
2280         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2281             (num_segments == tx_ring->sgl_size) &&
2282             (header_len < tx_ring->tx_max_header_size))
2283                 return 0;
2284
2285         ++tx_ring->tx_stats.linearize;
2286         rc = rte_pktmbuf_linearize(mbuf);
2287         if (unlikely(rc)) {
2288                 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2289                 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2290                 ++tx_ring->tx_stats.linearize_failed;
2291                 return rc;
2292         }
2293
2294         return rc;
2295 }
2296
2297 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2298                                   uint16_t nb_pkts)
2299 {
2300         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2301         uint16_t next_to_use = tx_ring->next_to_use;
2302         uint16_t next_to_clean = tx_ring->next_to_clean;
2303         struct rte_mbuf *mbuf;
2304         uint16_t seg_len;
2305         unsigned int ring_size = tx_ring->ring_size;
2306         unsigned int ring_mask = ring_size - 1;
2307         struct ena_com_tx_ctx ena_tx_ctx;
2308         struct ena_tx_buffer *tx_info;
2309         struct ena_com_buf *ebuf;
2310         uint16_t rc, req_id, total_tx_descs = 0;
2311         uint16_t sent_idx = 0, empty_tx_reqs;
2312         uint16_t push_len = 0;
2313         uint16_t delta = 0;
2314         int nb_hw_desc;
2315         uint32_t total_length;
2316
2317         /* Check adapter state */
2318         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2319                 PMD_DRV_LOG(ALERT,
2320                         "Trying to xmit pkts while device is NOT running\n");
2321                 return 0;
2322         }
2323
2324         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2325         if (nb_pkts > empty_tx_reqs)
2326                 nb_pkts = empty_tx_reqs;
2327
2328         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2329                 mbuf = tx_pkts[sent_idx];
2330                 total_length = 0;
2331
2332                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2333                 if (unlikely(rc))
2334                         break;
2335
2336                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2337                 tx_info = &tx_ring->tx_buffer_info[req_id];
2338                 tx_info->mbuf = mbuf;
2339                 tx_info->num_of_bufs = 0;
2340                 ebuf = tx_info->bufs;
2341
2342                 /* Prepare TX context */
2343                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2344                 memset(&ena_tx_ctx.ena_meta, 0x0,
2345                        sizeof(struct ena_com_tx_meta));
2346                 ena_tx_ctx.ena_bufs = ebuf;
2347                 ena_tx_ctx.req_id = req_id;
2348
2349                 delta = 0;
2350                 seg_len = mbuf->data_len;
2351
2352                 if (tx_ring->tx_mem_queue_type ==
2353                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2354                         push_len = RTE_MIN(mbuf->pkt_len,
2355                                            tx_ring->tx_max_header_size);
2356                         ena_tx_ctx.header_len = push_len;
2357
2358                         if (likely(push_len <= seg_len)) {
2359                                 /* If the push header is in the single segment,
2360                                  * then just point it to the 1st mbuf data.
2361                                  */
2362                                 ena_tx_ctx.push_header =
2363                                         rte_pktmbuf_mtod(mbuf, uint8_t *);
2364                         } else {
2365                                 /* If the push header lays in the several
2366                                  * segments, copy it to the intermediate buffer.
2367                                  */
2368                                 rte_pktmbuf_read(mbuf, 0, push_len,
2369                                         tx_ring->push_buf_intermediate_buf);
2370                                 ena_tx_ctx.push_header =
2371                                         tx_ring->push_buf_intermediate_buf;
2372                                 delta = push_len - seg_len;
2373                         }
2374                 } /* there's no else as we take advantage of memset zeroing */
2375
2376                 /* Set TX offloads flags, if applicable */
2377                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2378                         tx_ring->disable_meta_caching);
2379
2380                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2381
2382                 /* Process first segment taking into
2383                  * consideration pushed header
2384                  */
2385                 if (seg_len > push_len) {
2386                         ebuf->paddr = mbuf->buf_iova +
2387                                       mbuf->data_off +
2388                                       push_len;
2389                         ebuf->len = seg_len - push_len;
2390                         ebuf++;
2391                         tx_info->num_of_bufs++;
2392                 }
2393                 total_length += mbuf->data_len;
2394
2395                 while ((mbuf = mbuf->next) != NULL) {
2396                         seg_len = mbuf->data_len;
2397
2398                         /* Skip mbufs if whole data is pushed as a header */
2399                         if (unlikely(delta > seg_len)) {
2400                                 delta -= seg_len;
2401                                 continue;
2402                         }
2403
2404                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2405                         ebuf->len = seg_len - delta;
2406                         total_length += ebuf->len;
2407                         ebuf++;
2408                         tx_info->num_of_bufs++;
2409
2410                         delta = 0;
2411                 }
2412
2413                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2414
2415                 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2416                                                &ena_tx_ctx)) {
2417                         PMD_DRV_LOG(DEBUG, "llq tx max burst size of queue %d"
2418                                 " achieved, writing doorbell to send burst\n",
2419                                 tx_ring->id);
2420                         ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2421                 }
2422
2423                 /* prepare the packet's descriptors to dma engine */
2424                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2425                                         &ena_tx_ctx, &nb_hw_desc);
2426                 if (unlikely(rc)) {
2427                         ++tx_ring->tx_stats.prepare_ctx_err;
2428                         break;
2429                 }
2430                 tx_info->tx_descs = nb_hw_desc;
2431
2432                 next_to_use++;
2433                 tx_ring->tx_stats.cnt++;
2434                 tx_ring->tx_stats.bytes += total_length;
2435         }
2436         tx_ring->tx_stats.available_desc =
2437                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2438
2439         /* If there are ready packets to be xmitted... */
2440         if (sent_idx > 0) {
2441                 /* ...let HW do its best :-) */
2442                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2443                 tx_ring->tx_stats.doorbells++;
2444                 tx_ring->next_to_use = next_to_use;
2445         }
2446
2447         /* Clear complete packets  */
2448         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2449                 rc = validate_tx_req_id(tx_ring, req_id);
2450                 if (rc)
2451                         break;
2452
2453                 /* Get Tx info & store how many descs were processed  */
2454                 tx_info = &tx_ring->tx_buffer_info[req_id];
2455                 total_tx_descs += tx_info->tx_descs;
2456
2457                 /* Free whole mbuf chain  */
2458                 mbuf = tx_info->mbuf;
2459                 rte_pktmbuf_free(mbuf);
2460                 tx_info->mbuf = NULL;
2461
2462                 /* Put back descriptor to the ring for reuse */
2463                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2464                 next_to_clean++;
2465
2466                 /* If too many descs to clean, leave it for another run */
2467                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2468                         break;
2469         }
2470         tx_ring->tx_stats.available_desc =
2471                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2472
2473         if (total_tx_descs > 0) {
2474                 /* acknowledge completion of sent packets */
2475                 tx_ring->next_to_clean = next_to_clean;
2476                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2477                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2478         }
2479
2480         tx_ring->tx_stats.tx_poll++;
2481
2482         return sent_idx;
2483 }
2484
2485 /**
2486  * DPDK callback to retrieve names of extended device statistics
2487  *
2488  * @param dev
2489  *   Pointer to Ethernet device structure.
2490  * @param[out] xstats_names
2491  *   Buffer to insert names into.
2492  * @param n
2493  *   Number of names.
2494  *
2495  * @return
2496  *   Number of xstats names.
2497  */
2498 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2499                                 struct rte_eth_xstat_name *xstats_names,
2500                                 unsigned int n)
2501 {
2502         unsigned int xstats_count = ena_xstats_calc_num(dev);
2503         unsigned int stat, i, count = 0;
2504
2505         if (n < xstats_count || !xstats_names)
2506                 return xstats_count;
2507
2508         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2509                 strcpy(xstats_names[count].name,
2510                         ena_stats_global_strings[stat].name);
2511
2512         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2513                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2514                         snprintf(xstats_names[count].name,
2515                                 sizeof(xstats_names[count].name),
2516                                 "rx_q%d_%s", i,
2517                                 ena_stats_rx_strings[stat].name);
2518
2519         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2520                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2521                         snprintf(xstats_names[count].name,
2522                                 sizeof(xstats_names[count].name),
2523                                 "tx_q%d_%s", i,
2524                                 ena_stats_tx_strings[stat].name);
2525
2526         return xstats_count;
2527 }
2528
2529 /**
2530  * DPDK callback to get extended device statistics.
2531  *
2532  * @param dev
2533  *   Pointer to Ethernet device structure.
2534  * @param[out] stats
2535  *   Stats table output buffer.
2536  * @param n
2537  *   The size of the stats table.
2538  *
2539  * @return
2540  *   Number of xstats on success, negative on failure.
2541  */
2542 static int ena_xstats_get(struct rte_eth_dev *dev,
2543                           struct rte_eth_xstat *xstats,
2544                           unsigned int n)
2545 {
2546         struct ena_adapter *adapter = dev->data->dev_private;
2547         unsigned int xstats_count = ena_xstats_calc_num(dev);
2548         unsigned int stat, i, count = 0;
2549         int stat_offset;
2550         void *stats_begin;
2551
2552         if (n < xstats_count)
2553                 return xstats_count;
2554
2555         if (!xstats)
2556                 return 0;
2557
2558         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2559                 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2560                 stats_begin = &adapter->dev_stats;
2561
2562                 xstats[count].id = count;
2563                 xstats[count].value = *((uint64_t *)
2564                         ((char *)stats_begin + stat_offset));
2565         }
2566
2567         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2568                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2569                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2570                         stats_begin = &adapter->rx_ring[i].rx_stats;
2571
2572                         xstats[count].id = count;
2573                         xstats[count].value = *((uint64_t *)
2574                                 ((char *)stats_begin + stat_offset));
2575                 }
2576         }
2577
2578         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2579                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2580                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2581                         stats_begin = &adapter->tx_ring[i].rx_stats;
2582
2583                         xstats[count].id = count;
2584                         xstats[count].value = *((uint64_t *)
2585                                 ((char *)stats_begin + stat_offset));
2586                 }
2587         }
2588
2589         return count;
2590 }
2591
2592 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2593                                 const uint64_t *ids,
2594                                 uint64_t *values,
2595                                 unsigned int n)
2596 {
2597         struct ena_adapter *adapter = dev->data->dev_private;
2598         uint64_t id;
2599         uint64_t rx_entries, tx_entries;
2600         unsigned int i;
2601         int qid;
2602         int valid = 0;
2603         for (i = 0; i < n; ++i) {
2604                 id = ids[i];
2605                 /* Check if id belongs to global statistics */
2606                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2607                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2608                         ++valid;
2609                         continue;
2610                 }
2611
2612                 /* Check if id belongs to rx queue statistics */
2613                 id -= ENA_STATS_ARRAY_GLOBAL;
2614                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2615                 if (id < rx_entries) {
2616                         qid = id % dev->data->nb_rx_queues;
2617                         id /= dev->data->nb_rx_queues;
2618                         values[i] = *((uint64_t *)
2619                                 &adapter->rx_ring[qid].rx_stats + id);
2620                         ++valid;
2621                         continue;
2622                 }
2623                                 /* Check if id belongs to rx queue statistics */
2624                 id -= rx_entries;
2625                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2626                 if (id < tx_entries) {
2627                         qid = id % dev->data->nb_tx_queues;
2628                         id /= dev->data->nb_tx_queues;
2629                         values[i] = *((uint64_t *)
2630                                 &adapter->tx_ring[qid].tx_stats + id);
2631                         ++valid;
2632                         continue;
2633                 }
2634         }
2635
2636         return valid;
2637 }
2638
2639 static int ena_process_bool_devarg(const char *key,
2640                                    const char *value,
2641                                    void *opaque)
2642 {
2643         struct ena_adapter *adapter = opaque;
2644         bool bool_value;
2645
2646         /* Parse the value. */
2647         if (strcmp(value, "1") == 0) {
2648                 bool_value = true;
2649         } else if (strcmp(value, "0") == 0) {
2650                 bool_value = false;
2651         } else {
2652                 PMD_INIT_LOG(ERR,
2653                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
2654                         value, key);
2655                 return -EINVAL;
2656         }
2657
2658         /* Now, assign it to the proper adapter field. */
2659         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR))
2660                 adapter->use_large_llq_hdr = bool_value;
2661
2662         return 0;
2663 }
2664
2665 static int ena_parse_devargs(struct ena_adapter *adapter,
2666                              struct rte_devargs *devargs)
2667 {
2668         static const char * const allowed_args[] = {
2669                 ENA_DEVARG_LARGE_LLQ_HDR,
2670         };
2671         struct rte_kvargs *kvlist;
2672         int rc;
2673
2674         if (devargs == NULL)
2675                 return 0;
2676
2677         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
2678         if (kvlist == NULL) {
2679                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
2680                         devargs->args);
2681                 return -EINVAL;
2682         }
2683
2684         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
2685                 ena_process_bool_devarg, adapter);
2686
2687         rte_kvargs_free(kvlist);
2688
2689         return rc;
2690 }
2691
2692 /*********************************************************************
2693  *  PMD configuration
2694  *********************************************************************/
2695 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2696         struct rte_pci_device *pci_dev)
2697 {
2698         return rte_eth_dev_pci_generic_probe(pci_dev,
2699                 sizeof(struct ena_adapter), eth_ena_dev_init);
2700 }
2701
2702 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2703 {
2704         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2705 }
2706
2707 static struct rte_pci_driver rte_ena_pmd = {
2708         .id_table = pci_id_ena_map,
2709         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2710                      RTE_PCI_DRV_WC_ACTIVATE,
2711         .probe = eth_ena_pci_probe,
2712         .remove = eth_ena_pci_remove,
2713 };
2714
2715 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2716 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2717 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2718 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
2719
2720 RTE_INIT(ena_init_log)
2721 {
2722         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2723         if (ena_logtype_init >= 0)
2724                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2725         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2726         if (ena_logtype_driver >= 0)
2727                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2728
2729 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2730         ena_logtype_rx = rte_log_register("pmd.net.ena.rx");
2731         if (ena_logtype_rx >= 0)
2732                 rte_log_set_level(ena_logtype_rx, RTE_LOG_NOTICE);
2733 #endif
2734
2735 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2736         ena_logtype_tx = rte_log_register("pmd.net.ena.tx");
2737         if (ena_logtype_tx >= 0)
2738                 rte_log_set_level(ena_logtype_tx, RTE_LOG_NOTICE);
2739 #endif
2740
2741 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2742         ena_logtype_tx_free = rte_log_register("pmd.net.ena.tx_free");
2743         if (ena_logtype_tx_free >= 0)
2744                 rte_log_set_level(ena_logtype_tx_free, RTE_LOG_NOTICE);
2745 #endif
2746
2747 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2748         ena_logtype_com = rte_log_register("pmd.net.ena.com");
2749         if (ena_logtype_com >= 0)
2750                 rte_log_set_level(ena_logtype_com, RTE_LOG_NOTICE);
2751 #endif
2752 }
2753
2754 /******************************************************************************
2755  ******************************** AENQ Handlers *******************************
2756  *****************************************************************************/
2757 static void ena_update_on_link_change(void *adapter_data,
2758                                       struct ena_admin_aenq_entry *aenq_e)
2759 {
2760         struct rte_eth_dev *eth_dev;
2761         struct ena_adapter *adapter;
2762         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2763         uint32_t status;
2764
2765         adapter = adapter_data;
2766         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2767         eth_dev = adapter->rte_dev;
2768
2769         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2770         adapter->link_status = status;
2771
2772         ena_link_update(eth_dev, 0);
2773         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2774 }
2775
2776 static void ena_notification(void *data,
2777                              struct ena_admin_aenq_entry *aenq_e)
2778 {
2779         struct ena_adapter *adapter = data;
2780         struct ena_admin_ena_hw_hints *hints;
2781
2782         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2783                 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2784                         aenq_e->aenq_common_desc.group,
2785                         ENA_ADMIN_NOTIFICATION);
2786
2787         switch (aenq_e->aenq_common_desc.syndrom) {
2788         case ENA_ADMIN_UPDATE_HINTS:
2789                 hints = (struct ena_admin_ena_hw_hints *)
2790                         (&aenq_e->inline_data_w4);
2791                 ena_update_hints(adapter, hints);
2792                 break;
2793         default:
2794                 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2795                         aenq_e->aenq_common_desc.syndrom);
2796         }
2797 }
2798
2799 static void ena_keep_alive(void *adapter_data,
2800                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2801 {
2802         struct ena_adapter *adapter = adapter_data;
2803         struct ena_admin_aenq_keep_alive_desc *desc;
2804         uint64_t rx_drops;
2805         uint64_t tx_drops;
2806
2807         adapter->timestamp_wd = rte_get_timer_cycles();
2808
2809         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2810         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2811         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
2812
2813         adapter->drv_stats->rx_drops = rx_drops;
2814         adapter->dev_stats.tx_drops = tx_drops;
2815 }
2816
2817 /**
2818  * This handler will called for unknown event group or unimplemented handlers
2819  **/
2820 static void unimplemented_aenq_handler(__rte_unused void *data,
2821                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2822 {
2823         PMD_DRV_LOG(ERR, "Unknown event was received or event with "
2824                           "unimplemented handler\n");
2825 }
2826
2827 static struct ena_aenq_handlers aenq_handlers = {
2828         .handlers = {
2829                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2830                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2831                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2832         },
2833         .unimplemented_handler = unimplemented_aenq_handler
2834 };