drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_ether.h>
   8 #include <rte_ethdev_driver.h>
   9 #include <rte_ethdev_pci.h>
  10 #include <rte_tcp.h>
  11 #include <rte_atomic.h>
  12 #include <rte_dev.h>
  13 #include <rte_errno.h>
  14 #include <rte_version.h>
  15 #include <rte_net.h>
  16
  17 #include "ena_ethdev.h"
  18 #include "ena_logs.h"
  19 #include "ena_platform.h"
  20 #include "ena_com.h"
  21 #include "ena_eth_com.h"
  22
  23 #include <ena_common_defs.h>
  24 #include <ena_regs_defs.h>
  25 #include <ena_admin_defs.h>
  26 #include <ena_eth_io_defs.h>
  27
  28 #define DRV_MODULE_VER_MAJOR    2
  29 #define DRV_MODULE_VER_MINOR    0
  30 #define DRV_MODULE_VER_SUBMINOR 1
  31
  32 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  33 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  34 /*reverse version of ENA_IO_RXQ_IDX*/
  35 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  36
  37 /* While processing submitted and completed descriptors (rx and tx path
  38  * respectively) in a loop it is desired to:
  39  *  - perform batch submissions while populating sumbissmion queue
  40  *  - avoid blocking transmission of other packets during cleanup phase
  41  * Hence the utilization ratio of 1/8 of a queue size.
  42  */
  43 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  44
  45 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  46 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  47
  48 #define GET_L4_HDR_LEN(mbuf)                                    \
  49         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  50                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  51
  52 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  53 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  54 #define ENA_HASH_KEY_SIZE       40
  55 #define ETH_GSTRING_LEN 32
  56
  57 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  58
  59 #define ENA_MIN_RING_DESC       128
  60
  61 enum ethtool_stringset {
  62         ETH_SS_TEST             = 0,
  63         ETH_SS_STATS,
  64 };
  65
  66 struct ena_stats {
  67         char name[ETH_GSTRING_LEN];
  68         int stat_offset;
  69 };
  70
  71 #define ENA_STAT_ENTRY(stat, stat_type) { \
  72         .name = #stat, \
  73         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  74 }
  75
  76 #define ENA_STAT_RX_ENTRY(stat) \
  77         ENA_STAT_ENTRY(stat, rx)
  78
  79 #define ENA_STAT_TX_ENTRY(stat) \
  80         ENA_STAT_ENTRY(stat, tx)
  81
  82 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  83         ENA_STAT_ENTRY(stat, dev)
  84
  85 #define ENA_MAX_RING_SIZE_RX 8192
  86 #define ENA_MAX_RING_SIZE_TX 1024
  87
  88 /*
  89  * Each rte_memzone should have unique name.
  90  * To satisfy it, count number of allocation and add it to name.
  91  */
  92 uint32_t ena_alloc_cnt;
  93
  94 static const struct ena_stats ena_stats_global_strings[] = {
  95         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  96         ENA_STAT_GLOBAL_ENTRY(dev_start),
  97         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  98 };
  99
 100 static const struct ena_stats ena_stats_tx_strings[] = {
 101         ENA_STAT_TX_ENTRY(cnt),
 102         ENA_STAT_TX_ENTRY(bytes),
 103         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 104         ENA_STAT_TX_ENTRY(linearize),
 105         ENA_STAT_TX_ENTRY(linearize_failed),
 106         ENA_STAT_TX_ENTRY(tx_poll),
 107         ENA_STAT_TX_ENTRY(doorbells),
 108         ENA_STAT_TX_ENTRY(bad_req_id),
 109         ENA_STAT_TX_ENTRY(available_desc),
 110 };
 111
 112 static const struct ena_stats ena_stats_rx_strings[] = {
 113         ENA_STAT_RX_ENTRY(cnt),
 114         ENA_STAT_RX_ENTRY(bytes),
 115         ENA_STAT_RX_ENTRY(refill_partial),
 116         ENA_STAT_RX_ENTRY(bad_csum),
 117         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 118         ENA_STAT_RX_ENTRY(bad_desc_num),
 119         ENA_STAT_RX_ENTRY(bad_req_id),
 120 };
 121
 122 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 123 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 124 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 125
 126 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 127                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 128                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 129                         DEV_TX_OFFLOAD_TCP_TSO)
 130 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 131                        PKT_TX_IP_CKSUM |\
 132                        PKT_TX_TCP_SEG)
 133
 134 /** Vendor ID used by Amazon devices */
 135 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 136 /** Amazon devices */
 137 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 138 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 139
 140 #define ENA_TX_OFFLOAD_MASK     (\
 141         PKT_TX_L4_MASK |         \
 142         PKT_TX_IPV6 |            \
 143         PKT_TX_IPV4 |            \
 144         PKT_TX_IP_CKSUM |        \
 145         PKT_TX_TCP_SEG)
 146
 147 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 148         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 149
 150 int ena_logtype_init;
 151 int ena_logtype_driver;
 152
 153 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
 154 int ena_logtype_rx;
 155 #endif
 156 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
 157 int ena_logtype_tx;
 158 #endif
 159 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
 160 int ena_logtype_tx_free;
 161 #endif
 162 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
 163 int ena_logtype_com;
 164 #endif
 165
 166 static const struct rte_pci_id pci_id_ena_map[] = {
 167         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 168         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 169         { .device_id = 0 },
 170 };
 171
 172 static struct ena_aenq_handlers aenq_handlers;
 173
 174 static int ena_device_init(struct ena_com_dev *ena_dev,
 175                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 176                            bool *wd_state);
 177 static int ena_dev_configure(struct rte_eth_dev *dev);
 178 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 179                                   uint16_t nb_pkts);
 180 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 181                 uint16_t nb_pkts);
 182 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 183                               uint16_t nb_desc, unsigned int socket_id,
 184                               const struct rte_eth_txconf *tx_conf);
 185 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 186                               uint16_t nb_desc, unsigned int socket_id,
 187                               const struct rte_eth_rxconf *rx_conf,
 188                               struct rte_mempool *mp);
 189 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 190                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 191 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 192 static void ena_init_rings(struct ena_adapter *adapter);
 193 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 194 static int ena_start(struct rte_eth_dev *dev);
 195 static void ena_stop(struct rte_eth_dev *dev);
 196 static void ena_close(struct rte_eth_dev *dev);
 197 static int ena_dev_reset(struct rte_eth_dev *dev);
 198 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 199 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 200 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 201 static void ena_rx_queue_release(void *queue);
 202 static void ena_tx_queue_release(void *queue);
 203 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 204 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 205 static int ena_link_update(struct rte_eth_dev *dev,
 206                            int wait_to_complete);
 207 static int ena_create_io_queue(struct ena_ring *ring);
 208 static void ena_queue_stop(struct ena_ring *ring);
 209 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 210                               enum ena_ring_type ring_type);
 211 static int ena_queue_start(struct ena_ring *ring);
 212 static int ena_queue_start_all(struct rte_eth_dev *dev,
 213                                enum ena_ring_type ring_type);
 214 static void ena_stats_restart(struct rte_eth_dev *dev);
 215 static int ena_infos_get(struct rte_eth_dev *dev,
 216                          struct rte_eth_dev_info *dev_info);
 217 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 218                                struct rte_eth_rss_reta_entry64 *reta_conf,
 219                                uint16_t reta_size);
 220 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 221                               struct rte_eth_rss_reta_entry64 *reta_conf,
 222                               uint16_t reta_size);
 223 static void ena_interrupt_handler_rte(void *cb_arg);
 224 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 225 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 226 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 227 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 228                                 struct rte_eth_xstat_name *xstats_names,
 229                                 unsigned int n);
 230 static int ena_xstats_get(struct rte_eth_dev *dev,
 231                           struct rte_eth_xstat *stats,
 232                           unsigned int n);
 233 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 234                                 const uint64_t *ids,
 235                                 uint64_t *values,
 236                                 unsigned int n);
 237
 238 static const struct eth_dev_ops ena_dev_ops = {
 239         .dev_configure        = ena_dev_configure,
 240         .dev_infos_get        = ena_infos_get,
 241         .rx_queue_setup       = ena_rx_queue_setup,
 242         .tx_queue_setup       = ena_tx_queue_setup,
 243         .dev_start            = ena_start,
 244         .dev_stop             = ena_stop,
 245         .link_update          = ena_link_update,
 246         .stats_get            = ena_stats_get,
 247         .xstats_get_names     = ena_xstats_get_names,
 248         .xstats_get           = ena_xstats_get,
 249         .xstats_get_by_id     = ena_xstats_get_by_id,
 250         .mtu_set              = ena_mtu_set,
 251         .rx_queue_release     = ena_rx_queue_release,
 252         .tx_queue_release     = ena_tx_queue_release,
 253         .dev_close            = ena_close,
 254         .dev_reset            = ena_dev_reset,
 255         .reta_update          = ena_rss_reta_update,
 256         .reta_query           = ena_rss_reta_query,
 257 };
 258
 259 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 260                                        struct ena_com_rx_ctx *ena_rx_ctx)
 261 {
 262         uint64_t ol_flags = 0;
 263         uint32_t packet_type = 0;
 264
 265         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 266                 packet_type |= RTE_PTYPE_L4_TCP;
 267         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 268                 packet_type |= RTE_PTYPE_L4_UDP;
 269
 270         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 271                 packet_type |= RTE_PTYPE_L3_IPV4;
 272         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 273                 packet_type |= RTE_PTYPE_L3_IPV6;
 274
 275         if (unlikely(ena_rx_ctx->l4_csum_err))
 276                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 277         if (unlikely(ena_rx_ctx->l3_csum_err))
 278                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 279
 280         mbuf->ol_flags = ol_flags;
 281         mbuf->packet_type = packet_type;
 282 }
 283
 284 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 285                                        struct ena_com_tx_ctx *ena_tx_ctx,
 286                                        uint64_t queue_offloads)
 287 {
 288         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 289
 290         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 291             (queue_offloads & QUEUE_OFFLOADS)) {
 292                 /* check if TSO is required */
 293                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 294                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 295                         ena_tx_ctx->tso_enable = true;
 296
 297                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 298                 }
 299
 300                 /* check if L3 checksum is needed */
 301                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 302                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 303                         ena_tx_ctx->l3_csum_enable = true;
 304
 305                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 306                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 307                 } else {
 308                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 309
 310                         /* set don't fragment (DF) flag */
 311                         if (mbuf->packet_type &
 312                                 (RTE_PTYPE_L4_NONFRAG
 313                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 314                                 ena_tx_ctx->df = true;
 315                 }
 316
 317                 /* check if L4 checksum is needed */
 318                 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
 319                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 320                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 321                         ena_tx_ctx->l4_csum_enable = true;
 322                 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
 323                                 PKT_TX_UDP_CKSUM) &&
 324                                 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 325                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 326                         ena_tx_ctx->l4_csum_enable = true;
 327                 } else {
 328                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 329                         ena_tx_ctx->l4_csum_enable = false;
 330                 }
 331
 332                 ena_meta->mss = mbuf->tso_segsz;
 333                 ena_meta->l3_hdr_len = mbuf->l3_len;
 334                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 335
 336                 ena_tx_ctx->meta_valid = true;
 337         } else {
 338                 ena_tx_ctx->meta_valid = false;
 339         }
 340 }
 341
 342 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 343 {
 344         if (likely(req_id < rx_ring->ring_size))
 345                 return 0;
 346
 347         PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id);
 348
 349         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 350         rx_ring->adapter->trigger_reset = true;
 351         ++rx_ring->rx_stats.bad_req_id;
 352
 353         return -EFAULT;
 354 }
 355
 356 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 357 {
 358         struct ena_tx_buffer *tx_info = NULL;
 359
 360         if (likely(req_id < tx_ring->ring_size)) {
 361                 tx_info = &tx_ring->tx_buffer_info[req_id];
 362                 if (likely(tx_info->mbuf))
 363                         return 0;
 364         }
 365
 366         if (tx_info)
 367                 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 368         else
 369                 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 370
 371         /* Trigger device reset */
 372         ++tx_ring->tx_stats.bad_req_id;
 373         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 374         tx_ring->adapter->trigger_reset = true;
 375         return -EFAULT;
 376 }
 377
 378 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 379 {
 380         struct ena_admin_host_info *host_info;
 381         int rc;
 382
 383         /* Allocate only the host info */
 384         rc = ena_com_allocate_host_info(ena_dev);
 385         if (rc) {
 386                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 387                 return;
 388         }
 389
 390         host_info = ena_dev->host_attr.host_info;
 391
 392         host_info->os_type = ENA_ADMIN_OS_DPDK;
 393         host_info->kernel_ver = RTE_VERSION;
 394         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 395                 sizeof(host_info->kernel_ver_str));
 396         host_info->os_dist = RTE_VERSION;
 397         strlcpy((char *)host_info->os_dist_str, rte_version(),
 398                 sizeof(host_info->os_dist_str));
 399         host_info->driver_version =
 400                 (DRV_MODULE_VER_MAJOR) |
 401                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 402                 (DRV_MODULE_VER_SUBMINOR <<
 403                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 404         host_info->num_cpus = rte_lcore_count();
 405
 406         rc = ena_com_set_host_attributes(ena_dev);
 407         if (rc) {
 408                 if (rc == -ENA_COM_UNSUPPORTED)
 409                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 410                 else
 411                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 412
 413                 goto err;
 414         }
 415
 416         return;
 417
 418 err:
 419         ena_com_delete_host_info(ena_dev);
 420 }
 421
 422 /* This function calculates the number of xstats based on the current config */
 423 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
 424 {
 425         return ENA_STATS_ARRAY_GLOBAL +
 426                 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 427                 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 428 }
 429
 430 static void ena_config_debug_area(struct ena_adapter *adapter)
 431 {
 432         u32 debug_area_size;
 433         int rc, ss_count;
 434
 435         ss_count = ena_xstats_calc_num(adapter->rte_dev);
 436
 437         /* allocate 32 bytes for each string and 64bit for the value */
 438         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 439
 440         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 441         if (rc) {
 442                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 443                 return;
 444         }
 445
 446         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 447         if (rc) {
 448                 if (rc == -ENA_COM_UNSUPPORTED)
 449                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 450                 else
 451                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 452
 453                 goto err;
 454         }
 455
 456         return;
 457 err:
 458         ena_com_delete_debug_area(&adapter->ena_dev);
 459 }
 460
 461 static void ena_close(struct rte_eth_dev *dev)
 462 {
 463         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 464         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 465         struct ena_adapter *adapter = dev->data->dev_private;
 466
 467         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 468                 ena_stop(dev);
 469         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 470
 471         ena_rx_queue_release_all(dev);
 472         ena_tx_queue_release_all(dev);
 473
 474         rte_free(adapter->drv_stats);
 475         adapter->drv_stats = NULL;
 476
 477         rte_intr_disable(intr_handle);
 478         rte_intr_callback_unregister(intr_handle,
 479                                      ena_interrupt_handler_rte,
 480                                      adapter);
 481
 482         /*
 483          * MAC is not allocated dynamically. Setting NULL should prevent from
 484          * release of the resource in the rte_eth_dev_release_port().
 485          */
 486         dev->data->mac_addrs = NULL;
 487 }
 488
 489 static int
 490 ena_dev_reset(struct rte_eth_dev *dev)
 491 {
 492         int rc = 0;
 493
 494         ena_destroy_device(dev);
 495         rc = eth_ena_dev_init(dev);
 496         if (rc)
 497                 PMD_INIT_LOG(CRIT, "Cannot initialize device");
 498
 499         return rc;
 500 }
 501
 502 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 503                                struct rte_eth_rss_reta_entry64 *reta_conf,
 504                                uint16_t reta_size)
 505 {
 506         struct ena_adapter *adapter = dev->data->dev_private;
 507         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 508         int rc, i;
 509         u16 entry_value;
 510         int conf_idx;
 511         int idx;
 512
 513         if ((reta_size == 0) || (reta_conf == NULL))
 514                 return -EINVAL;
 515
 516         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 517                 PMD_DRV_LOG(WARNING,
 518                         "indirection table %d is bigger than supported (%d)\n",
 519                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 520                 return -EINVAL;
 521         }
 522
 523         for (i = 0 ; i < reta_size ; i++) {
 524                 /* each reta_conf is for 64 entries.
 525                  * to support 128 we use 2 conf of 64
 526                  */
 527                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 528                 idx = i % RTE_RETA_GROUP_SIZE;
 529                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 530                         entry_value =
 531                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 532
 533                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 534                                                                i,
 535                                                                entry_value);
 536                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 537                                 PMD_DRV_LOG(ERR,
 538                                         "Cannot fill indirect table\n");
 539                                 return rc;
 540                         }
 541                 }
 542         }
 543
 544         rc = ena_com_indirect_table_set(ena_dev);
 545         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 546                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 547                 return rc;
 548         }
 549
 550         PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries  for port %d\n",
 551                 __func__, reta_size, adapter->rte_dev->data->port_id);
 552
 553         return 0;
 554 }
 555
 556 /* Query redirection table. */
 557 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 558                               struct rte_eth_rss_reta_entry64 *reta_conf,
 559                               uint16_t reta_size)
 560 {
 561         struct ena_adapter *adapter = dev->data->dev_private;
 562         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 563         int rc;
 564         int i;
 565         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 566         int reta_conf_idx;
 567         int reta_idx;
 568
 569         if (reta_size == 0 || reta_conf == NULL ||
 570             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 571                 return -EINVAL;
 572
 573         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 574         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 575                 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
 576                 return -ENOTSUP;
 577         }
 578
 579         for (i = 0 ; i < reta_size ; i++) {
 580                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 581                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 582                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 583                         reta_conf[reta_conf_idx].reta[reta_idx] =
 584                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 585         }
 586
 587         return 0;
 588 }
 589
 590 static int ena_rss_init_default(struct ena_adapter *adapter)
 591 {
 592         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 593         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 594         int rc, i;
 595         u32 val;
 596
 597         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 598         if (unlikely(rc)) {
 599                 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
 600                 goto err_rss_init;
 601         }
 602
 603         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 604                 val = i % nb_rx_queues;
 605                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 606                                                        ENA_IO_RXQ_IDX(val));
 607                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 608                         PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
 609                         goto err_fill_indir;
 610                 }
 611         }
 612
 613         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 614                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 615         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 616                 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
 617                 goto err_fill_indir;
 618         }
 619
 620         rc = ena_com_set_default_hash_ctrl(ena_dev);
 621         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 622                 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
 623                 goto err_fill_indir;
 624         }
 625
 626         rc = ena_com_indirect_table_set(ena_dev);
 627         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 628                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 629                 goto err_fill_indir;
 630         }
 631         PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
 632                 adapter->rte_dev->data->port_id);
 633
 634         return 0;
 635
 636 err_fill_indir:
 637         ena_com_rss_destroy(ena_dev);
 638 err_rss_init:
 639
 640         return rc;
 641 }
 642
 643 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 644 {
 645         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 646         int nb_queues = dev->data->nb_rx_queues;
 647         int i;
 648
 649         for (i = 0; i < nb_queues; i++)
 650                 ena_rx_queue_release(queues[i]);
 651 }
 652
 653 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 654 {
 655         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 656         int nb_queues = dev->data->nb_tx_queues;
 657         int i;
 658
 659         for (i = 0; i < nb_queues; i++)
 660                 ena_tx_queue_release(queues[i]);
 661 }
 662
 663 static void ena_rx_queue_release(void *queue)
 664 {
 665         struct ena_ring *ring = (struct ena_ring *)queue;
 666
 667         /* Free ring resources */
 668         if (ring->rx_buffer_info)
 669                 rte_free(ring->rx_buffer_info);
 670         ring->rx_buffer_info = NULL;
 671
 672         if (ring->rx_refill_buffer)
 673                 rte_free(ring->rx_refill_buffer);
 674         ring->rx_refill_buffer = NULL;
 675
 676         if (ring->empty_rx_reqs)
 677                 rte_free(ring->empty_rx_reqs);
 678         ring->empty_rx_reqs = NULL;
 679
 680         ring->configured = 0;
 681
 682         PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
 683                 ring->port_id, ring->id);
 684 }
 685
 686 static void ena_tx_queue_release(void *queue)
 687 {
 688         struct ena_ring *ring = (struct ena_ring *)queue;
 689
 690         /* Free ring resources */
 691         if (ring->push_buf_intermediate_buf)
 692                 rte_free(ring->push_buf_intermediate_buf);
 693
 694         if (ring->tx_buffer_info)
 695                 rte_free(ring->tx_buffer_info);
 696
 697         if (ring->empty_tx_reqs)
 698                 rte_free(ring->empty_tx_reqs);
 699
 700         ring->empty_tx_reqs = NULL;
 701         ring->tx_buffer_info = NULL;
 702         ring->push_buf_intermediate_buf = NULL;
 703
 704         ring->configured = 0;
 705
 706         PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
 707                 ring->port_id, ring->id);
 708 }
 709
 710 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 711 {
 712         unsigned int i;
 713
 714         for (i = 0; i < ring->ring_size; ++i)
 715                 if (ring->rx_buffer_info[i]) {
 716                         rte_mbuf_raw_free(ring->rx_buffer_info[i]);
 717                         ring->rx_buffer_info[i] = NULL;
 718                 }
 719 }
 720
 721 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 722 {
 723         unsigned int i;
 724
 725         for (i = 0; i < ring->ring_size; ++i) {
 726                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 727
 728                 if (tx_buf->mbuf)
 729                         rte_pktmbuf_free(tx_buf->mbuf);
 730         }
 731 }
 732
 733 static int ena_link_update(struct rte_eth_dev *dev,
 734                            __rte_unused int wait_to_complete)
 735 {
 736         struct rte_eth_link *link = &dev->data->dev_link;
 737         struct ena_adapter *adapter = dev->data->dev_private;
 738
 739         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 740         link->link_speed = ETH_SPEED_NUM_NONE;
 741         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 742
 743         return 0;
 744 }
 745
 746 static int ena_queue_start_all(struct rte_eth_dev *dev,
 747                                enum ena_ring_type ring_type)
 748 {
 749         struct ena_adapter *adapter = dev->data->dev_private;
 750         struct ena_ring *queues = NULL;
 751         int nb_queues;
 752         int i = 0;
 753         int rc = 0;
 754
 755         if (ring_type == ENA_RING_TYPE_RX) {
 756                 queues = adapter->rx_ring;
 757                 nb_queues = dev->data->nb_rx_queues;
 758         } else {
 759                 queues = adapter->tx_ring;
 760                 nb_queues = dev->data->nb_tx_queues;
 761         }
 762         for (i = 0; i < nb_queues; i++) {
 763                 if (queues[i].configured) {
 764                         if (ring_type == ENA_RING_TYPE_RX) {
 765                                 ena_assert_msg(
 766                                         dev->data->rx_queues[i] == &queues[i],
 767                                         "Inconsistent state of rx queues\n");
 768                         } else {
 769                                 ena_assert_msg(
 770                                         dev->data->tx_queues[i] == &queues[i],
 771                                         "Inconsistent state of tx queues\n");
 772                         }
 773
 774                         rc = ena_queue_start(&queues[i]);
 775
 776                         if (rc) {
 777                                 PMD_INIT_LOG(ERR,
 778                                              "failed to start queue %d type(%d)",
 779                                              i, ring_type);
 780                                 goto err;
 781                         }
 782                 }
 783         }
 784
 785         return 0;
 786
 787 err:
 788         while (i--)
 789                 if (queues[i].configured)
 790                         ena_queue_stop(&queues[i]);
 791
 792         return rc;
 793 }
 794
 795 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 796 {
 797         uint32_t max_frame_len = adapter->max_mtu;
 798
 799         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 800             DEV_RX_OFFLOAD_JUMBO_FRAME)
 801                 max_frame_len =
 802                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 803
 804         return max_frame_len;
 805 }
 806
 807 static int ena_check_valid_conf(struct ena_adapter *adapter)
 808 {
 809         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 810
 811         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 812                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 813                                   "max mtu: %d, min mtu: %d",
 814                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 815                 return ENA_COM_UNSUPPORTED;
 816         }
 817
 818         return 0;
 819 }
 820
 821 static int
 822 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)
 823 {
 824         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 825         struct ena_com_dev *ena_dev = ctx->ena_dev;
 826         uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX;
 827         uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX;
 828
 829         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 830                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 831                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 832                 rx_queue_size = RTE_MIN(rx_queue_size,
 833                         max_queue_ext->max_rx_cq_depth);
 834                 rx_queue_size = RTE_MIN(rx_queue_size,
 835                         max_queue_ext->max_rx_sq_depth);
 836                 tx_queue_size = RTE_MIN(tx_queue_size,
 837                         max_queue_ext->max_tx_cq_depth);
 838
 839                 if (ena_dev->tx_mem_queue_type ==
 840                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 841                         tx_queue_size = RTE_MIN(tx_queue_size,
 842                                 llq->max_llq_depth);
 843                 } else {
 844                         tx_queue_size = RTE_MIN(tx_queue_size,
 845                                 max_queue_ext->max_tx_sq_depth);
 846                 }
 847
 848                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 849                         max_queue_ext->max_per_packet_rx_descs);
 850                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 851                         max_queue_ext->max_per_packet_tx_descs);
 852         } else {
 853                 struct ena_admin_queue_feature_desc *max_queues =
 854                         &ctx->get_feat_ctx->max_queues;
 855                 rx_queue_size = RTE_MIN(rx_queue_size,
 856                         max_queues->max_cq_depth);
 857                 rx_queue_size = RTE_MIN(rx_queue_size,
 858                         max_queues->max_sq_depth);
 859                 tx_queue_size = RTE_MIN(tx_queue_size,
 860                         max_queues->max_cq_depth);
 861
 862                 if (ena_dev->tx_mem_queue_type ==
 863                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 864                         tx_queue_size = RTE_MIN(tx_queue_size,
 865                                 llq->max_llq_depth);
 866                 } else {
 867                         tx_queue_size = RTE_MIN(tx_queue_size,
 868                                 max_queues->max_sq_depth);
 869                 }
 870
 871                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 872                         max_queues->max_packet_tx_descs);
 873                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 874                         max_queues->max_packet_rx_descs);
 875         }
 876
 877         /* Round down to the nearest power of 2 */
 878         rx_queue_size = rte_align32prevpow2(rx_queue_size);
 879         tx_queue_size = rte_align32prevpow2(tx_queue_size);
 880
 881         if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) {
 882                 PMD_INIT_LOG(ERR, "Invalid queue size");
 883                 return -EFAULT;
 884         }
 885
 886         ctx->rx_queue_size = rx_queue_size;
 887         ctx->tx_queue_size = tx_queue_size;
 888
 889         return 0;
 890 }
 891
 892 static void ena_stats_restart(struct rte_eth_dev *dev)
 893 {
 894         struct ena_adapter *adapter = dev->data->dev_private;
 895
 896         rte_atomic64_init(&adapter->drv_stats->ierrors);
 897         rte_atomic64_init(&adapter->drv_stats->oerrors);
 898         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 899         rte_atomic64_init(&adapter->drv_stats->rx_drops);
 900 }
 901
 902 static int ena_stats_get(struct rte_eth_dev *dev,
 903                           struct rte_eth_stats *stats)
 904 {
 905         struct ena_admin_basic_stats ena_stats;
 906         struct ena_adapter *adapter = dev->data->dev_private;
 907         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 908         int rc;
 909         int i;
 910         int max_rings_stats;
 911
 912         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 913                 return -ENOTSUP;
 914
 915         memset(&ena_stats, 0, sizeof(ena_stats));
 916         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 917         if (unlikely(rc)) {
 918                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 919                 return rc;
 920         }
 921
 922         /* Set of basic statistics from ENA */
 923         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 924                                           ena_stats.rx_pkts_low);
 925         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 926                                           ena_stats.tx_pkts_low);
 927         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 928                                         ena_stats.rx_bytes_low);
 929         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 930                                         ena_stats.tx_bytes_low);
 931
 932         /* Driver related stats */
 933         stats->imissed = rte_atomic64_read(&adapter->drv_stats->rx_drops);
 934         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 935         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 936         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 937
 938         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
 939                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 940         for (i = 0; i < max_rings_stats; ++i) {
 941                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
 942
 943                 stats->q_ibytes[i] = rx_stats->bytes;
 944                 stats->q_ipackets[i] = rx_stats->cnt;
 945                 stats->q_errors[i] = rx_stats->bad_desc_num +
 946                         rx_stats->bad_req_id;
 947         }
 948
 949         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
 950                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 951         for (i = 0; i < max_rings_stats; ++i) {
 952                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
 953
 954                 stats->q_obytes[i] = tx_stats->bytes;
 955                 stats->q_opackets[i] = tx_stats->cnt;
 956         }
 957
 958         return 0;
 959 }
 960
 961 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 962 {
 963         struct ena_adapter *adapter;
 964         struct ena_com_dev *ena_dev;
 965         int rc = 0;
 966
 967         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
 968         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
 969         adapter = dev->data->dev_private;
 970
 971         ena_dev = &adapter->ena_dev;
 972         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
 973
 974         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
 975                 PMD_DRV_LOG(ERR,
 976                         "Invalid MTU setting. new_mtu: %d "
 977                         "max mtu: %d min mtu: %d\n",
 978                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
 979                 return -EINVAL;
 980         }
 981
 982         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 983         if (rc)
 984                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
 985         else
 986                 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
 987
 988         return rc;
 989 }
 990
 991 static int ena_start(struct rte_eth_dev *dev)
 992 {
 993         struct ena_adapter *adapter = dev->data->dev_private;
 994         uint64_t ticks;
 995         int rc = 0;
 996
 997         rc = ena_check_valid_conf(adapter);
 998         if (rc)
 999                 return rc;
1000
1001         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1002         if (rc)
1003                 return rc;
1004
1005         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1006         if (rc)
1007                 goto err_start_tx;
1008
1009         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1010             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1011                 rc = ena_rss_init_default(adapter);
1012                 if (rc)
1013                         goto err_rss_init;
1014         }
1015
1016         ena_stats_restart(dev);
1017
1018         adapter->timestamp_wd = rte_get_timer_cycles();
1019         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1020
1021         ticks = rte_get_timer_hz();
1022         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1023                         ena_timer_wd_callback, adapter);
1024
1025         ++adapter->dev_stats.dev_start;
1026         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1027
1028         return 0;
1029
1030 err_rss_init:
1031         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1032 err_start_tx:
1033         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1034         return rc;
1035 }
1036
1037 static void ena_stop(struct rte_eth_dev *dev)
1038 {
1039         struct ena_adapter *adapter = dev->data->dev_private;
1040         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1041         int rc;
1042
1043         rte_timer_stop_sync(&adapter->timer_wd);
1044         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1045         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1046
1047         if (adapter->trigger_reset) {
1048                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1049                 if (rc)
1050                         PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1051         }
1052
1053         ++adapter->dev_stats.dev_stop;
1054         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1055 }
1056
1057 static int ena_create_io_queue(struct ena_ring *ring)
1058 {
1059         struct ena_adapter *adapter;
1060         struct ena_com_dev *ena_dev;
1061         struct ena_com_create_io_ctx ctx =
1062                 /* policy set to _HOST just to satisfy icc compiler */
1063                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1064                   0, 0, 0, 0, 0 };
1065         uint16_t ena_qid;
1066         unsigned int i;
1067         int rc;
1068
1069         adapter = ring->adapter;
1070         ena_dev = &adapter->ena_dev;
1071
1072         if (ring->type == ENA_RING_TYPE_TX) {
1073                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1074                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1075                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1076                 ctx.queue_size = adapter->tx_ring_size;
1077                 for (i = 0; i < ring->ring_size; i++)
1078                         ring->empty_tx_reqs[i] = i;
1079         } else {
1080                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1081                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1082                 ctx.queue_size = adapter->rx_ring_size;
1083                 for (i = 0; i < ring->ring_size; i++)
1084                         ring->empty_rx_reqs[i] = i;
1085         }
1086         ctx.qid = ena_qid;
1087         ctx.msix_vector = -1; /* interrupts not used */
1088         ctx.numa_node = ring->numa_socket_id;
1089
1090         rc = ena_com_create_io_queue(ena_dev, &ctx);
1091         if (rc) {
1092                 PMD_DRV_LOG(ERR,
1093                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1094                         ring->id, ena_qid, rc);
1095                 return rc;
1096         }
1097
1098         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1099                                      &ring->ena_com_io_sq,
1100                                      &ring->ena_com_io_cq);
1101         if (rc) {
1102                 PMD_DRV_LOG(ERR,
1103                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1104                         ring->id, rc);
1105                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1106                 return rc;
1107         }
1108
1109         if (ring->type == ENA_RING_TYPE_TX)
1110                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1111
1112         return 0;
1113 }
1114
1115 static void ena_queue_stop(struct ena_ring *ring)
1116 {
1117         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1118
1119         if (ring->type == ENA_RING_TYPE_RX) {
1120                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1121                 ena_rx_queue_release_bufs(ring);
1122         } else {
1123                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1124                 ena_tx_queue_release_bufs(ring);
1125         }
1126 }
1127
1128 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1129                               enum ena_ring_type ring_type)
1130 {
1131         struct ena_adapter *adapter = dev->data->dev_private;
1132         struct ena_ring *queues = NULL;
1133         uint16_t nb_queues, i;
1134
1135         if (ring_type == ENA_RING_TYPE_RX) {
1136                 queues = adapter->rx_ring;
1137                 nb_queues = dev->data->nb_rx_queues;
1138         } else {
1139                 queues = adapter->tx_ring;
1140                 nb_queues = dev->data->nb_tx_queues;
1141         }
1142
1143         for (i = 0; i < nb_queues; ++i)
1144                 if (queues[i].configured)
1145                         ena_queue_stop(&queues[i]);
1146 }
1147
1148 static int ena_queue_start(struct ena_ring *ring)
1149 {
1150         int rc, bufs_num;
1151
1152         ena_assert_msg(ring->configured == 1,
1153                        "Trying to start unconfigured queue\n");
1154
1155         rc = ena_create_io_queue(ring);
1156         if (rc) {
1157                 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1158                 return rc;
1159         }
1160
1161         ring->next_to_clean = 0;
1162         ring->next_to_use = 0;
1163
1164         if (ring->type == ENA_RING_TYPE_TX) {
1165                 ring->tx_stats.available_desc =
1166                         ena_com_free_desc(ring->ena_com_io_sq);
1167                 return 0;
1168         }
1169
1170         bufs_num = ring->ring_size - 1;
1171         rc = ena_populate_rx_queue(ring, bufs_num);
1172         if (rc != bufs_num) {
1173                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1174                                          ENA_IO_RXQ_IDX(ring->id));
1175                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1176                 return ENA_COM_FAULT;
1177         }
1178
1179         return 0;
1180 }
1181
1182 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1183                               uint16_t queue_idx,
1184                               uint16_t nb_desc,
1185                               unsigned int socket_id,
1186                               const struct rte_eth_txconf *tx_conf)
1187 {
1188         struct ena_ring *txq = NULL;
1189         struct ena_adapter *adapter = dev->data->dev_private;
1190         unsigned int i;
1191
1192         txq = &adapter->tx_ring[queue_idx];
1193
1194         if (txq->configured) {
1195                 PMD_DRV_LOG(CRIT,
1196                         "API violation. Queue %d is already configured\n",
1197                         queue_idx);
1198                 return ENA_COM_FAULT;
1199         }
1200
1201         if (!rte_is_power_of_2(nb_desc)) {
1202                 PMD_DRV_LOG(ERR,
1203                         "Unsupported size of TX queue: %d is not a power of 2.\n",
1204                         nb_desc);
1205                 return -EINVAL;
1206         }
1207
1208         if (nb_desc > adapter->tx_ring_size) {
1209                 PMD_DRV_LOG(ERR,
1210                         "Unsupported size of TX queue (max size: %d)\n",
1211                         adapter->tx_ring_size);
1212                 return -EINVAL;
1213         }
1214
1215         if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1216                 nb_desc = adapter->tx_ring_size;
1217
1218         txq->port_id = dev->data->port_id;
1219         txq->next_to_clean = 0;
1220         txq->next_to_use = 0;
1221         txq->ring_size = nb_desc;
1222         txq->numa_socket_id = socket_id;
1223
1224         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1225                                           sizeof(struct ena_tx_buffer) *
1226                                           txq->ring_size,
1227                                           RTE_CACHE_LINE_SIZE);
1228         if (!txq->tx_buffer_info) {
1229                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1230                 return -ENOMEM;
1231         }
1232
1233         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1234                                          sizeof(u16) * txq->ring_size,
1235                                          RTE_CACHE_LINE_SIZE);
1236         if (!txq->empty_tx_reqs) {
1237                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1238                 rte_free(txq->tx_buffer_info);
1239                 return -ENOMEM;
1240         }
1241
1242         txq->push_buf_intermediate_buf =
1243                 rte_zmalloc("txq->push_buf_intermediate_buf",
1244                             txq->tx_max_header_size,
1245                             RTE_CACHE_LINE_SIZE);
1246         if (!txq->push_buf_intermediate_buf) {
1247                 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1248                 rte_free(txq->tx_buffer_info);
1249                 rte_free(txq->empty_tx_reqs);
1250                 return -ENOMEM;
1251         }
1252
1253         for (i = 0; i < txq->ring_size; i++)
1254                 txq->empty_tx_reqs[i] = i;
1255
1256         if (tx_conf != NULL) {
1257                 txq->offloads =
1258                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1259         }
1260         /* Store pointer to this queue in upper layer */
1261         txq->configured = 1;
1262         dev->data->tx_queues[queue_idx] = txq;
1263
1264         return 0;
1265 }
1266
1267 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1268                               uint16_t queue_idx,
1269                               uint16_t nb_desc,
1270                               unsigned int socket_id,
1271                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1272                               struct rte_mempool *mp)
1273 {
1274         struct ena_adapter *adapter = dev->data->dev_private;
1275         struct ena_ring *rxq = NULL;
1276         int i;
1277
1278         rxq = &adapter->rx_ring[queue_idx];
1279         if (rxq->configured) {
1280                 PMD_DRV_LOG(CRIT,
1281                         "API violation. Queue %d is already configured\n",
1282                         queue_idx);
1283                 return ENA_COM_FAULT;
1284         }
1285
1286         if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1287                 nb_desc = adapter->rx_ring_size;
1288
1289         if (!rte_is_power_of_2(nb_desc)) {
1290                 PMD_DRV_LOG(ERR,
1291                         "Unsupported size of RX queue: %d is not a power of 2.\n",
1292                         nb_desc);
1293                 return -EINVAL;
1294         }
1295
1296         if (nb_desc > adapter->rx_ring_size) {
1297                 PMD_DRV_LOG(ERR,
1298                         "Unsupported size of RX queue (max size: %d)\n",
1299                         adapter->rx_ring_size);
1300                 return -EINVAL;
1301         }
1302
1303         rxq->port_id = dev->data->port_id;
1304         rxq->next_to_clean = 0;
1305         rxq->next_to_use = 0;
1306         rxq->ring_size = nb_desc;
1307         rxq->numa_socket_id = socket_id;
1308         rxq->mb_pool = mp;
1309
1310         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1311                                           sizeof(struct rte_mbuf *) * nb_desc,
1312                                           RTE_CACHE_LINE_SIZE);
1313         if (!rxq->rx_buffer_info) {
1314                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1315                 return -ENOMEM;
1316         }
1317
1318         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1319                                             sizeof(struct rte_mbuf *) * nb_desc,
1320                                             RTE_CACHE_LINE_SIZE);
1321
1322         if (!rxq->rx_refill_buffer) {
1323                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1324                 rte_free(rxq->rx_buffer_info);
1325                 rxq->rx_buffer_info = NULL;
1326                 return -ENOMEM;
1327         }
1328
1329         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1330                                          sizeof(uint16_t) * nb_desc,
1331                                          RTE_CACHE_LINE_SIZE);
1332         if (!rxq->empty_rx_reqs) {
1333                 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1334                 rte_free(rxq->rx_buffer_info);
1335                 rxq->rx_buffer_info = NULL;
1336                 rte_free(rxq->rx_refill_buffer);
1337                 rxq->rx_refill_buffer = NULL;
1338                 return -ENOMEM;
1339         }
1340
1341         for (i = 0; i < nb_desc; i++)
1342                 rxq->empty_rx_reqs[i] = i;
1343
1344         /* Store pointer to this queue in upper layer */
1345         rxq->configured = 1;
1346         dev->data->rx_queues[queue_idx] = rxq;
1347
1348         return 0;
1349 }
1350
1351 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1352 {
1353         unsigned int i;
1354         int rc;
1355         uint16_t ring_size = rxq->ring_size;
1356         uint16_t ring_mask = ring_size - 1;
1357         uint16_t next_to_use = rxq->next_to_use;
1358         uint16_t in_use, req_id;
1359         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1360
1361         if (unlikely(!count))
1362                 return 0;
1363
1364         in_use = rxq->next_to_use - rxq->next_to_clean;
1365         ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n");
1366
1367         /* get resources for incoming packets */
1368         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1369         if (unlikely(rc < 0)) {
1370                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1371                 ++rxq->rx_stats.mbuf_alloc_fail;
1372                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1373                 return 0;
1374         }
1375
1376         for (i = 0; i < count; i++) {
1377                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1378                 struct rte_mbuf *mbuf = mbufs[i];
1379                 struct ena_com_buf ebuf;
1380
1381                 if (likely((i + 4) < count))
1382                         rte_prefetch0(mbufs[i + 4]);
1383
1384                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1385                 rc = validate_rx_req_id(rxq, req_id);
1386                 if (unlikely(rc < 0))
1387                         break;
1388                 rxq->rx_buffer_info[req_id] = mbuf;
1389
1390                 /* prepare physical address for DMA transaction */
1391                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1392                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1393                 /* pass resource to device */
1394                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1395                                                 &ebuf, req_id);
1396                 if (unlikely(rc)) {
1397                         PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1398                         rxq->rx_buffer_info[req_id] = NULL;
1399                         break;
1400                 }
1401                 next_to_use++;
1402         }
1403
1404         if (unlikely(i < count)) {
1405                 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1406                         "buffers (from %d)\n", rxq->id, i, count);
1407                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1408                                      count - i);
1409                 ++rxq->rx_stats.refill_partial;
1410         }
1411
1412         /* When we submitted free recources to device... */
1413         if (likely(i > 0)) {
1414                 /* ...let HW know that it can fill buffers with data
1415                  *
1416                  * Add memory barrier to make sure the desc were written before
1417                  * issue a doorbell
1418                  */
1419                 rte_wmb();
1420                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1421
1422                 rxq->next_to_use = next_to_use;
1423         }
1424
1425         return i;
1426 }
1427
1428 static int ena_device_init(struct ena_com_dev *ena_dev,
1429                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1430                            bool *wd_state)
1431 {
1432         uint32_t aenq_groups;
1433         int rc;
1434         bool readless_supported;
1435
1436         /* Initialize mmio registers */
1437         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1438         if (rc) {
1439                 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1440                 return rc;
1441         }
1442
1443         /* The PCIe configuration space revision id indicate if mmio reg
1444          * read is disabled.
1445          */
1446         readless_supported =
1447                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1448                                & ENA_MMIO_DISABLE_REG_READ);
1449         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1450
1451         /* reset device */
1452         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1453         if (rc) {
1454                 PMD_DRV_LOG(ERR, "cannot reset device\n");
1455                 goto err_mmio_read_less;
1456         }
1457
1458         /* check FW version */
1459         rc = ena_com_validate_version(ena_dev);
1460         if (rc) {
1461                 PMD_DRV_LOG(ERR, "device version is too low\n");
1462                 goto err_mmio_read_less;
1463         }
1464
1465         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1466
1467         /* ENA device administration layer init */
1468         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1469         if (rc) {
1470                 PMD_DRV_LOG(ERR,
1471                         "cannot initialize ena admin queue with device\n");
1472                 goto err_mmio_read_less;
1473         }
1474
1475         /* To enable the msix interrupts the driver needs to know the number
1476          * of queues. So the driver uses polling mode to retrieve this
1477          * information.
1478          */
1479         ena_com_set_admin_polling_mode(ena_dev, true);
1480
1481         ena_config_host_info(ena_dev);
1482
1483         /* Get Device Attributes and features */
1484         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1485         if (rc) {
1486                 PMD_DRV_LOG(ERR,
1487                         "cannot get attribute for ena device rc= %d\n", rc);
1488                 goto err_admin_init;
1489         }
1490
1491         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1492                       BIT(ENA_ADMIN_NOTIFICATION) |
1493                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1494                       BIT(ENA_ADMIN_FATAL_ERROR) |
1495                       BIT(ENA_ADMIN_WARNING);
1496
1497         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1498         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1499         if (rc) {
1500                 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1501                 goto err_admin_init;
1502         }
1503
1504         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1505
1506         return 0;
1507
1508 err_admin_init:
1509         ena_com_admin_destroy(ena_dev);
1510
1511 err_mmio_read_less:
1512         ena_com_mmio_reg_read_request_destroy(ena_dev);
1513
1514         return rc;
1515 }
1516
1517 static void ena_interrupt_handler_rte(void *cb_arg)
1518 {
1519         struct ena_adapter *adapter = cb_arg;
1520         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1521
1522         ena_com_admin_q_comp_intr_handler(ena_dev);
1523         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1524                 ena_com_aenq_intr_handler(ena_dev, adapter);
1525 }
1526
1527 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1528 {
1529         if (!adapter->wd_state)
1530                 return;
1531
1532         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1533                 return;
1534
1535         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1536             adapter->keep_alive_timeout)) {
1537                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1538                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1539                 adapter->trigger_reset = true;
1540                 ++adapter->dev_stats.wd_expired;
1541         }
1542 }
1543
1544 /* Check if admin queue is enabled */
1545 static void check_for_admin_com_state(struct ena_adapter *adapter)
1546 {
1547         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1548                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1549                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1550                 adapter->trigger_reset = true;
1551         }
1552 }
1553
1554 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1555                                   void *arg)
1556 {
1557         struct ena_adapter *adapter = arg;
1558         struct rte_eth_dev *dev = adapter->rte_dev;
1559
1560         check_for_missing_keep_alive(adapter);
1561         check_for_admin_com_state(adapter);
1562
1563         if (unlikely(adapter->trigger_reset)) {
1564                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1565                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1566                         NULL);
1567         }
1568 }
1569
1570 static inline void
1571 set_default_llq_configurations(struct ena_llq_configurations *llq_config)
1572 {
1573         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1574         llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1575         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1576         llq_config->llq_num_decs_before_header =
1577                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1578         llq_config->llq_ring_entry_size_value = 128;
1579 }
1580
1581 static int
1582 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1583                                 struct ena_com_dev *ena_dev,
1584                                 struct ena_admin_feature_llq_desc *llq,
1585                                 struct ena_llq_configurations *llq_default_configurations)
1586 {
1587         int rc;
1588         u32 llq_feature_mask;
1589
1590         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1591         if (!(ena_dev->supported_features & llq_feature_mask)) {
1592                 PMD_DRV_LOG(INFO,
1593                         "LLQ is not supported. Fallback to host mode policy.\n");
1594                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1595                 return 0;
1596         }
1597
1598         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1599         if (unlikely(rc)) {
1600                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1601                         "Fallback to host mode policy.");
1602                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1603                 return 0;
1604         }
1605
1606         /* Nothing to config, exit */
1607         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1608                 return 0;
1609
1610         if (!adapter->dev_mem_base) {
1611                 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1612                         "Fallback to host mode policy.\n.");
1613                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1614                 return 0;
1615         }
1616
1617         ena_dev->mem_bar = adapter->dev_mem_base;
1618
1619         return 0;
1620 }
1621
1622 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,
1623                                  struct ena_com_dev_get_features_ctx *get_feat_ctx)
1624 {
1625         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num;
1626
1627         /* Regular queues capabilities */
1628         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1629                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1630                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1631                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1632                                     max_queue_ext->max_rx_cq_num);
1633                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1634                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1635         } else {
1636                 struct ena_admin_queue_feature_desc *max_queues =
1637                         &get_feat_ctx->max_queues;
1638                 io_tx_sq_num = max_queues->max_sq_num;
1639                 io_tx_cq_num = max_queues->max_cq_num;
1640                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1641         }
1642
1643         /* In case of LLQ use the llq number in the get feature cmd */
1644         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1645                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1646
1647         io_queue_num = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1648         io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num);
1649         io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num);
1650
1651         if (unlikely(io_queue_num == 0)) {
1652                 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1653                 return -EFAULT;
1654         }
1655
1656         return io_queue_num;
1657 }
1658
1659 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1660 {
1661         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1662         struct rte_pci_device *pci_dev;
1663         struct rte_intr_handle *intr_handle;
1664         struct ena_adapter *adapter = eth_dev->data->dev_private;
1665         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1666         struct ena_com_dev_get_features_ctx get_feat_ctx;
1667         struct ena_llq_configurations llq_config;
1668         const char *queue_type_str;
1669         int rc;
1670
1671         static int adapters_found;
1672         bool wd_state;
1673
1674         eth_dev->dev_ops = &ena_dev_ops;
1675         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1676         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1677         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1678
1679         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1680                 return 0;
1681
1682         memset(adapter, 0, sizeof(struct ena_adapter));
1683         ena_dev = &adapter->ena_dev;
1684
1685         adapter->rte_eth_dev_data = eth_dev->data;
1686         adapter->rte_dev = eth_dev;
1687
1688         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1689         adapter->pdev = pci_dev;
1690
1691         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1692                      pci_dev->addr.domain,
1693                      pci_dev->addr.bus,
1694                      pci_dev->addr.devid,
1695                      pci_dev->addr.function);
1696
1697         intr_handle = &pci_dev->intr_handle;
1698
1699         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1700         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1701
1702         if (!adapter->regs) {
1703                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1704                              ENA_REGS_BAR);
1705                 return -ENXIO;
1706         }
1707
1708         ena_dev->reg_bar = adapter->regs;
1709         ena_dev->dmadev = adapter->pdev;
1710
1711         adapter->id_number = adapters_found;
1712
1713         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1714                  adapter->id_number);
1715
1716         /* device specific initialization routine */
1717         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1718         if (rc) {
1719                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1720                 goto err;
1721         }
1722         adapter->wd_state = wd_state;
1723
1724         set_default_llq_configurations(&llq_config);
1725         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1726                                              &get_feat_ctx.llq, &llq_config);
1727         if (unlikely(rc)) {
1728                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1729                 return rc;
1730         }
1731
1732         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1733                 queue_type_str = "Regular";
1734         else
1735                 queue_type_str = "Low latency";
1736         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1737
1738         calc_queue_ctx.ena_dev = ena_dev;
1739         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1740         adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1741                                                     &get_feat_ctx);
1742
1743         rc = ena_calc_queue_size(&calc_queue_ctx);
1744         if (unlikely((rc != 0) || (adapter->num_queues <= 0))) {
1745                 rc = -EFAULT;
1746                 goto err_device_destroy;
1747         }
1748
1749         adapter->tx_ring_size = calc_queue_ctx.tx_queue_size;
1750         adapter->rx_ring_size = calc_queue_ctx.rx_queue_size;
1751
1752         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1753         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1754
1755         /* prepare ring structures */
1756         ena_init_rings(adapter);
1757
1758         ena_config_debug_area(adapter);
1759
1760         /* Set max MTU for this device */
1761         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1762
1763         /* set device support for offloads */
1764         adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1765                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1766         adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1767                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1768         adapter->offloads.rx_csum_supported =
1769                 (get_feat_ctx.offload.rx_supported &
1770                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1771
1772         /* Copy MAC address and point DPDK to it */
1773         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1774         rte_ether_addr_copy((struct rte_ether_addr *)
1775                         get_feat_ctx.dev_attr.mac_addr,
1776                         (struct rte_ether_addr *)adapter->mac_addr);
1777
1778         /*
1779          * Pass the information to the rte_eth_dev_close() that it should also
1780          * release the private port resources.
1781          */
1782         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1783
1784         adapter->drv_stats = rte_zmalloc("adapter stats",
1785                                          sizeof(*adapter->drv_stats),
1786                                          RTE_CACHE_LINE_SIZE);
1787         if (!adapter->drv_stats) {
1788                 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1789                 rc = -ENOMEM;
1790                 goto err_delete_debug_area;
1791         }
1792
1793         rte_intr_callback_register(intr_handle,
1794                                    ena_interrupt_handler_rte,
1795                                    adapter);
1796         rte_intr_enable(intr_handle);
1797         ena_com_set_admin_polling_mode(ena_dev, false);
1798         ena_com_admin_aenq_enable(ena_dev);
1799
1800         if (adapters_found == 0)
1801                 rte_timer_subsystem_init();
1802         rte_timer_init(&adapter->timer_wd);
1803
1804         adapters_found++;
1805         adapter->state = ENA_ADAPTER_STATE_INIT;
1806
1807         return 0;
1808
1809 err_delete_debug_area:
1810         ena_com_delete_debug_area(ena_dev);
1811
1812 err_device_destroy:
1813         ena_com_delete_host_info(ena_dev);
1814         ena_com_admin_destroy(ena_dev);
1815
1816 err:
1817         return rc;
1818 }
1819
1820 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1821 {
1822         struct ena_adapter *adapter = eth_dev->data->dev_private;
1823         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1824
1825         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1826                 return;
1827
1828         ena_com_set_admin_running_state(ena_dev, false);
1829
1830         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1831                 ena_close(eth_dev);
1832
1833         ena_com_delete_debug_area(ena_dev);
1834         ena_com_delete_host_info(ena_dev);
1835
1836         ena_com_abort_admin_commands(ena_dev);
1837         ena_com_wait_for_abort_completion(ena_dev);
1838         ena_com_admin_destroy(ena_dev);
1839         ena_com_mmio_reg_read_request_destroy(ena_dev);
1840
1841         adapter->state = ENA_ADAPTER_STATE_FREE;
1842 }
1843
1844 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1845 {
1846         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1847                 return 0;
1848
1849         ena_destroy_device(eth_dev);
1850
1851         eth_dev->dev_ops = NULL;
1852         eth_dev->rx_pkt_burst = NULL;
1853         eth_dev->tx_pkt_burst = NULL;
1854         eth_dev->tx_pkt_prepare = NULL;
1855
1856         return 0;
1857 }
1858
1859 static int ena_dev_configure(struct rte_eth_dev *dev)
1860 {
1861         struct ena_adapter *adapter = dev->data->dev_private;
1862
1863         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1864
1865         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1866         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1867         return 0;
1868 }
1869
1870 static void ena_init_rings(struct ena_adapter *adapter)
1871 {
1872         int i;
1873
1874         for (i = 0; i < adapter->num_queues; i++) {
1875                 struct ena_ring *ring = &adapter->tx_ring[i];
1876
1877                 ring->configured = 0;
1878                 ring->type = ENA_RING_TYPE_TX;
1879                 ring->adapter = adapter;
1880                 ring->id = i;
1881                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1882                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1883                 ring->sgl_size = adapter->max_tx_sgl_size;
1884         }
1885
1886         for (i = 0; i < adapter->num_queues; i++) {
1887                 struct ena_ring *ring = &adapter->rx_ring[i];
1888
1889                 ring->configured = 0;
1890                 ring->type = ENA_RING_TYPE_RX;
1891                 ring->adapter = adapter;
1892                 ring->id = i;
1893                 ring->sgl_size = adapter->max_rx_sgl_size;
1894         }
1895 }
1896
1897 static int ena_infos_get(struct rte_eth_dev *dev,
1898                           struct rte_eth_dev_info *dev_info)
1899 {
1900         struct ena_adapter *adapter;
1901         struct ena_com_dev *ena_dev;
1902         uint64_t rx_feat = 0, tx_feat = 0;
1903
1904         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1905         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1906         adapter = dev->data->dev_private;
1907
1908         ena_dev = &adapter->ena_dev;
1909         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1910
1911         dev_info->speed_capa =
1912                         ETH_LINK_SPEED_1G   |
1913                         ETH_LINK_SPEED_2_5G |
1914                         ETH_LINK_SPEED_5G   |
1915                         ETH_LINK_SPEED_10G  |
1916                         ETH_LINK_SPEED_25G  |
1917                         ETH_LINK_SPEED_40G  |
1918                         ETH_LINK_SPEED_50G  |
1919                         ETH_LINK_SPEED_100G;
1920
1921         /* Set Tx & Rx features available for device */
1922         if (adapter->offloads.tso4_supported)
1923                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1924
1925         if (adapter->offloads.tx_csum_supported)
1926                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1927                         DEV_TX_OFFLOAD_UDP_CKSUM |
1928                         DEV_TX_OFFLOAD_TCP_CKSUM;
1929
1930         if (adapter->offloads.rx_csum_supported)
1931                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1932                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1933                         DEV_RX_OFFLOAD_TCP_CKSUM;
1934
1935         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1936
1937         /* Inform framework about available features */
1938         dev_info->rx_offload_capa = rx_feat;
1939         dev_info->rx_queue_offload_capa = rx_feat;
1940         dev_info->tx_offload_capa = tx_feat;
1941         dev_info->tx_queue_offload_capa = tx_feat;
1942
1943         dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
1944                                            ETH_RSS_UDP;
1945
1946         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1947         dev_info->max_rx_pktlen  = adapter->max_mtu;
1948         dev_info->max_mac_addrs = 1;
1949
1950         dev_info->max_rx_queues = adapter->num_queues;
1951         dev_info->max_tx_queues = adapter->num_queues;
1952         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1953
1954         adapter->tx_supported_offloads = tx_feat;
1955         adapter->rx_supported_offloads = rx_feat;
1956
1957         dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size;
1958         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1959         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1960                                         adapter->max_rx_sgl_size);
1961         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1962                                         adapter->max_rx_sgl_size);
1963
1964         dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size;
1965         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1966         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1967                                         adapter->max_tx_sgl_size);
1968         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1969                                         adapter->max_tx_sgl_size);
1970
1971         return 0;
1972 }
1973
1974 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1975                                   uint16_t nb_pkts)
1976 {
1977         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1978         unsigned int ring_size = rx_ring->ring_size;
1979         unsigned int ring_mask = ring_size - 1;
1980         uint16_t next_to_clean = rx_ring->next_to_clean;
1981         uint16_t desc_in_use = 0;
1982         uint16_t req_id;
1983         unsigned int recv_idx = 0;
1984         struct rte_mbuf *mbuf = NULL;
1985         struct rte_mbuf *mbuf_head = NULL;
1986         struct rte_mbuf *mbuf_prev = NULL;
1987         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1988         unsigned int completed;
1989
1990         struct ena_com_rx_ctx ena_rx_ctx;
1991         int rc = 0;
1992
1993         /* Check adapter state */
1994         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1995                 PMD_DRV_LOG(ALERT,
1996                         "Trying to receive pkts while device is NOT running\n");
1997                 return 0;
1998         }
1999
2000         desc_in_use = rx_ring->next_to_use - next_to_clean;
2001         if (unlikely(nb_pkts > desc_in_use))
2002                 nb_pkts = desc_in_use;
2003
2004         for (completed = 0; completed < nb_pkts; completed++) {
2005                 int segments = 0;
2006
2007                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2008                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2009                 ena_rx_ctx.descs = 0;
2010                 /* receive packet context */
2011                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2012                                     rx_ring->ena_com_io_sq,
2013                                     &ena_rx_ctx);
2014                 if (unlikely(rc)) {
2015                         PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2016                         rx_ring->adapter->reset_reason =
2017                                 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2018                         rx_ring->adapter->trigger_reset = true;
2019                         ++rx_ring->rx_stats.bad_desc_num;
2020                         return 0;
2021                 }
2022
2023                 if (unlikely(ena_rx_ctx.descs == 0))
2024                         break;
2025
2026                 while (segments < ena_rx_ctx.descs) {
2027                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
2028                         rc = validate_rx_req_id(rx_ring, req_id);
2029                         if (unlikely(rc)) {
2030                                 if (segments != 0)
2031                                         rte_mbuf_raw_free(mbuf_head);
2032                                 break;
2033                         }
2034
2035                         mbuf = rx_buff_info[req_id];
2036                         rx_buff_info[req_id] = NULL;
2037                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
2038                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2039                         mbuf->refcnt = 1;
2040                         mbuf->next = NULL;
2041                         if (unlikely(segments == 0)) {
2042                                 mbuf->nb_segs = ena_rx_ctx.descs;
2043                                 mbuf->port = rx_ring->port_id;
2044                                 mbuf->pkt_len = 0;
2045                                 mbuf_head = mbuf;
2046                         } else {
2047                                 /* for multi-segment pkts create mbuf chain */
2048                                 mbuf_prev->next = mbuf;
2049                         }
2050                         mbuf_head->pkt_len += mbuf->data_len;
2051
2052                         mbuf_prev = mbuf;
2053                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
2054                                 req_id;
2055                         segments++;
2056                         next_to_clean++;
2057                 }
2058                 if (unlikely(rc))
2059                         break;
2060
2061                 /* fill mbuf attributes if any */
2062                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
2063
2064                 if (unlikely(mbuf_head->ol_flags &
2065                                 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2066                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2067                         ++rx_ring->rx_stats.bad_csum;
2068                 }
2069
2070                 mbuf_head->hash.rss = ena_rx_ctx.hash;
2071
2072                 /* pass to DPDK application head mbuf */
2073                 rx_pkts[recv_idx] = mbuf_head;
2074                 recv_idx++;
2075                 rx_ring->rx_stats.bytes += mbuf_head->pkt_len;
2076         }
2077
2078         rx_ring->rx_stats.cnt += recv_idx;
2079         rx_ring->next_to_clean = next_to_clean;
2080
2081         desc_in_use = desc_in_use - completed + 1;
2082         /* Burst refill to save doorbells, memory barriers, const interval */
2083         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size)) {
2084                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2085                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
2086         }
2087
2088         return recv_idx;
2089 }
2090
2091 static uint16_t
2092 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2093                 uint16_t nb_pkts)
2094 {
2095         int32_t ret;
2096         uint32_t i;
2097         struct rte_mbuf *m;
2098         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2099         struct rte_ipv4_hdr *ip_hdr;
2100         uint64_t ol_flags;
2101         uint16_t frag_field;
2102
2103         for (i = 0; i != nb_pkts; i++) {
2104                 m = tx_pkts[i];
2105                 ol_flags = m->ol_flags;
2106
2107                 if (!(ol_flags & PKT_TX_IPV4))
2108                         continue;
2109
2110                 /* If there was not L2 header length specified, assume it is
2111                  * length of the ethernet header.
2112                  */
2113                 if (unlikely(m->l2_len == 0))
2114                         m->l2_len = sizeof(struct rte_ether_hdr);
2115
2116                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2117                                                  m->l2_len);
2118                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2119
2120                 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2121                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2122
2123                         /* If IPv4 header has DF flag enabled and TSO support is
2124                          * disabled, partial chcecksum should not be calculated.
2125                          */
2126                         if (!tx_ring->adapter->offloads.tso4_supported)
2127                                 continue;
2128                 }
2129
2130                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2131                                 (ol_flags & PKT_TX_L4_MASK) ==
2132                                 PKT_TX_SCTP_CKSUM) {
2133                         rte_errno = ENOTSUP;
2134                         return i;
2135                 }
2136
2137 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2138                 ret = rte_validate_tx_offload(m);
2139                 if (ret != 0) {
2140                         rte_errno = -ret;
2141                         return i;
2142                 }
2143 #endif
2144
2145                 /* In case we are supposed to TSO and have DF not set (DF=0)
2146                  * hardware must be provided with partial checksum, otherwise
2147                  * it will take care of necessary calculations.
2148                  */
2149
2150                 ret = rte_net_intel_cksum_flags_prepare(m,
2151                         ol_flags & ~PKT_TX_TCP_SEG);
2152                 if (ret != 0) {
2153                         rte_errno = -ret;
2154                         return i;
2155                 }
2156         }
2157
2158         return i;
2159 }
2160
2161 static void ena_update_hints(struct ena_adapter *adapter,
2162                              struct ena_admin_ena_hw_hints *hints)
2163 {
2164         if (hints->admin_completion_tx_timeout)
2165                 adapter->ena_dev.admin_queue.completion_timeout =
2166                         hints->admin_completion_tx_timeout * 1000;
2167
2168         if (hints->mmio_read_timeout)
2169                 /* convert to usec */
2170                 adapter->ena_dev.mmio_read.reg_read_to =
2171                         hints->mmio_read_timeout * 1000;
2172
2173         if (hints->driver_watchdog_timeout) {
2174                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2175                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2176                 else
2177                         // Convert msecs to ticks
2178                         adapter->keep_alive_timeout =
2179                                 (hints->driver_watchdog_timeout *
2180                                 rte_get_timer_hz()) / 1000;
2181         }
2182 }
2183
2184 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2185                                         struct rte_mbuf *mbuf)
2186 {
2187         struct ena_com_dev *ena_dev;
2188         int num_segments, header_len, rc;
2189
2190         ena_dev = &tx_ring->adapter->ena_dev;
2191         num_segments = mbuf->nb_segs;
2192         header_len = mbuf->data_len;
2193
2194         if (likely(num_segments < tx_ring->sgl_size))
2195                 return 0;
2196
2197         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2198             (num_segments == tx_ring->sgl_size) &&
2199             (header_len < tx_ring->tx_max_header_size))
2200                 return 0;
2201
2202         ++tx_ring->tx_stats.linearize;
2203         rc = rte_pktmbuf_linearize(mbuf);
2204         if (unlikely(rc)) {
2205                 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2206                 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2207                 ++tx_ring->tx_stats.linearize_failed;
2208                 return rc;
2209         }
2210
2211         return rc;
2212 }
2213
2214 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2215                                   uint16_t nb_pkts)
2216 {
2217         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2218         uint16_t next_to_use = tx_ring->next_to_use;
2219         uint16_t next_to_clean = tx_ring->next_to_clean;
2220         struct rte_mbuf *mbuf;
2221         uint16_t seg_len;
2222         unsigned int ring_size = tx_ring->ring_size;
2223         unsigned int ring_mask = ring_size - 1;
2224         struct ena_com_tx_ctx ena_tx_ctx;
2225         struct ena_tx_buffer *tx_info;
2226         struct ena_com_buf *ebuf;
2227         uint16_t rc, req_id, total_tx_descs = 0;
2228         uint16_t sent_idx = 0, empty_tx_reqs;
2229         uint16_t push_len = 0;
2230         uint16_t delta = 0;
2231         int nb_hw_desc;
2232         uint32_t total_length;
2233
2234         /* Check adapter state */
2235         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2236                 PMD_DRV_LOG(ALERT,
2237                         "Trying to xmit pkts while device is NOT running\n");
2238                 return 0;
2239         }
2240
2241         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2242         if (nb_pkts > empty_tx_reqs)
2243                 nb_pkts = empty_tx_reqs;
2244
2245         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2246                 mbuf = tx_pkts[sent_idx];
2247                 total_length = 0;
2248
2249                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2250                 if (unlikely(rc))
2251                         break;
2252
2253                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2254                 tx_info = &tx_ring->tx_buffer_info[req_id];
2255                 tx_info->mbuf = mbuf;
2256                 tx_info->num_of_bufs = 0;
2257                 ebuf = tx_info->bufs;
2258
2259                 /* Prepare TX context */
2260                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2261                 memset(&ena_tx_ctx.ena_meta, 0x0,
2262                        sizeof(struct ena_com_tx_meta));
2263                 ena_tx_ctx.ena_bufs = ebuf;
2264                 ena_tx_ctx.req_id = req_id;
2265
2266                 delta = 0;
2267                 seg_len = mbuf->data_len;
2268
2269                 if (tx_ring->tx_mem_queue_type ==
2270                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2271                         push_len = RTE_MIN(mbuf->pkt_len,
2272                                            tx_ring->tx_max_header_size);
2273                         ena_tx_ctx.header_len = push_len;
2274
2275                         if (likely(push_len <= seg_len)) {
2276                                 /* If the push header is in the single segment,
2277                                  * then just point it to the 1st mbuf data.
2278                                  */
2279                                 ena_tx_ctx.push_header =
2280                                         rte_pktmbuf_mtod(mbuf, uint8_t *);
2281                         } else {
2282                                 /* If the push header lays in the several
2283                                  * segments, copy it to the intermediate buffer.
2284                                  */
2285                                 rte_pktmbuf_read(mbuf, 0, push_len,
2286                                         tx_ring->push_buf_intermediate_buf);
2287                                 ena_tx_ctx.push_header =
2288                                         tx_ring->push_buf_intermediate_buf;
2289                                 delta = push_len - seg_len;
2290                         }
2291                 } /* there's no else as we take advantage of memset zeroing */
2292
2293                 /* Set TX offloads flags, if applicable */
2294                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2295
2296                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2297
2298                 /* Process first segment taking into
2299                  * consideration pushed header
2300                  */
2301                 if (seg_len > push_len) {
2302                         ebuf->paddr = mbuf->buf_iova +
2303                                       mbuf->data_off +
2304                                       push_len;
2305                         ebuf->len = seg_len - push_len;
2306                         ebuf++;
2307                         tx_info->num_of_bufs++;
2308                 }
2309                 total_length += mbuf->data_len;
2310
2311                 while ((mbuf = mbuf->next) != NULL) {
2312                         seg_len = mbuf->data_len;
2313
2314                         /* Skip mbufs if whole data is pushed as a header */
2315                         if (unlikely(delta > seg_len)) {
2316                                 delta -= seg_len;
2317                                 continue;
2318                         }
2319
2320                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2321                         ebuf->len = seg_len - delta;
2322                         total_length += ebuf->len;
2323                         ebuf++;
2324                         tx_info->num_of_bufs++;
2325
2326                         delta = 0;
2327                 }
2328
2329                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2330
2331                 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2332                                                &ena_tx_ctx)) {
2333                         PMD_DRV_LOG(DEBUG, "llq tx max burst size of queue %d"
2334                                 " achieved, writing doorbell to send burst\n",
2335                                 tx_ring->id);
2336                         rte_wmb();
2337                         ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2338                 }
2339
2340                 /* prepare the packet's descriptors to dma engine */
2341                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2342                                         &ena_tx_ctx, &nb_hw_desc);
2343                 if (unlikely(rc)) {
2344                         ++tx_ring->tx_stats.prepare_ctx_err;
2345                         break;
2346                 }
2347                 tx_info->tx_descs = nb_hw_desc;
2348
2349                 next_to_use++;
2350                 tx_ring->tx_stats.cnt++;
2351                 tx_ring->tx_stats.bytes += total_length;
2352         }
2353         tx_ring->tx_stats.available_desc =
2354                 ena_com_free_desc(tx_ring->ena_com_io_sq);
2355
2356         /* If there are ready packets to be xmitted... */
2357         if (sent_idx > 0) {
2358                 /* ...let HW do its best :-) */
2359                 rte_wmb();
2360                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2361                 tx_ring->tx_stats.doorbells++;
2362                 tx_ring->next_to_use = next_to_use;
2363         }
2364
2365         /* Clear complete packets  */
2366         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2367                 rc = validate_tx_req_id(tx_ring, req_id);
2368                 if (rc)
2369                         break;
2370
2371                 /* Get Tx info & store how many descs were processed  */
2372                 tx_info = &tx_ring->tx_buffer_info[req_id];
2373                 total_tx_descs += tx_info->tx_descs;
2374
2375                 /* Free whole mbuf chain  */
2376                 mbuf = tx_info->mbuf;
2377                 rte_pktmbuf_free(mbuf);
2378                 tx_info->mbuf = NULL;
2379
2380                 /* Put back descriptor to the ring for reuse */
2381                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2382                 next_to_clean++;
2383
2384                 /* If too many descs to clean, leave it for another run */
2385                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2386                         break;
2387         }
2388         tx_ring->tx_stats.available_desc =
2389                 ena_com_free_desc(tx_ring->ena_com_io_sq);
2390
2391         if (total_tx_descs > 0) {
2392                 /* acknowledge completion of sent packets */
2393                 tx_ring->next_to_clean = next_to_clean;
2394                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2395                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2396         }
2397
2398         tx_ring->tx_stats.tx_poll++;
2399
2400         return sent_idx;
2401 }
2402
2403 /**
2404  * DPDK callback to retrieve names of extended device statistics
2405  *
2406  * @param dev
2407  *   Pointer to Ethernet device structure.
2408  * @param[out] xstats_names
2409  *   Buffer to insert names into.
2410  * @param n
2411  *   Number of names.
2412  *
2413  * @return
2414  *   Number of xstats names.
2415  */
2416 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2417                                 struct rte_eth_xstat_name *xstats_names,
2418                                 unsigned int n)
2419 {
2420         unsigned int xstats_count = ena_xstats_calc_num(dev);
2421         unsigned int stat, i, count = 0;
2422
2423         if (n < xstats_count || !xstats_names)
2424                 return xstats_count;
2425
2426         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2427                 strcpy(xstats_names[count].name,
2428                         ena_stats_global_strings[stat].name);
2429
2430         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2431                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2432                         snprintf(xstats_names[count].name,
2433                                 sizeof(xstats_names[count].name),
2434                                 "rx_q%d_%s", i,
2435                                 ena_stats_rx_strings[stat].name);
2436
2437         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2438                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2439                         snprintf(xstats_names[count].name,
2440                                 sizeof(xstats_names[count].name),
2441                                 "tx_q%d_%s", i,
2442                                 ena_stats_tx_strings[stat].name);
2443
2444         return xstats_count;
2445 }
2446
2447 /**
2448  * DPDK callback to get extended device statistics.
2449  *
2450  * @param dev
2451  *   Pointer to Ethernet device structure.
2452  * @param[out] stats
2453  *   Stats table output buffer.
2454  * @param n
2455  *   The size of the stats table.
2456  *
2457  * @return
2458  *   Number of xstats on success, negative on failure.
2459  */
2460 static int ena_xstats_get(struct rte_eth_dev *dev,
2461                           struct rte_eth_xstat *xstats,
2462                           unsigned int n)
2463 {
2464         struct ena_adapter *adapter = dev->data->dev_private;
2465         unsigned int xstats_count = ena_xstats_calc_num(dev);
2466         unsigned int stat, i, count = 0;
2467         int stat_offset;
2468         void *stats_begin;
2469
2470         if (n < xstats_count)
2471                 return xstats_count;
2472
2473         if (!xstats)
2474                 return 0;
2475
2476         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2477                 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2478                 stats_begin = &adapter->dev_stats;
2479
2480                 xstats[count].id = count;
2481                 xstats[count].value = *((uint64_t *)
2482                         ((char *)stats_begin + stat_offset));
2483         }
2484
2485         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2486                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2487                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2488                         stats_begin = &adapter->rx_ring[i].rx_stats;
2489
2490                         xstats[count].id = count;
2491                         xstats[count].value = *((uint64_t *)
2492                                 ((char *)stats_begin + stat_offset));
2493                 }
2494         }
2495
2496         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2497                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2498                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2499                         stats_begin = &adapter->tx_ring[i].rx_stats;
2500
2501                         xstats[count].id = count;
2502                         xstats[count].value = *((uint64_t *)
2503                                 ((char *)stats_begin + stat_offset));
2504                 }
2505         }
2506
2507         return count;
2508 }
2509
2510 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2511                                 const uint64_t *ids,
2512                                 uint64_t *values,
2513                                 unsigned int n)
2514 {
2515         struct ena_adapter *adapter = dev->data->dev_private;
2516         uint64_t id;
2517         uint64_t rx_entries, tx_entries;
2518         unsigned int i;
2519         int qid;
2520         int valid = 0;
2521         for (i = 0; i < n; ++i) {
2522                 id = ids[i];
2523                 /* Check if id belongs to global statistics */
2524                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2525                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2526                         ++valid;
2527                         continue;
2528                 }
2529
2530                 /* Check if id belongs to rx queue statistics */
2531                 id -= ENA_STATS_ARRAY_GLOBAL;
2532                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2533                 if (id < rx_entries) {
2534                         qid = id % dev->data->nb_rx_queues;
2535                         id /= dev->data->nb_rx_queues;
2536                         values[i] = *((uint64_t *)
2537                                 &adapter->rx_ring[qid].rx_stats + id);
2538                         ++valid;
2539                         continue;
2540                 }
2541                                 /* Check if id belongs to rx queue statistics */
2542                 id -= rx_entries;
2543                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2544                 if (id < tx_entries) {
2545                         qid = id % dev->data->nb_tx_queues;
2546                         id /= dev->data->nb_tx_queues;
2547                         values[i] = *((uint64_t *)
2548                                 &adapter->tx_ring[qid].tx_stats + id);
2549                         ++valid;
2550                         continue;
2551                 }
2552         }
2553
2554         return valid;
2555 }
2556
2557 /*********************************************************************
2558  *  PMD configuration
2559  *********************************************************************/
2560 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2561         struct rte_pci_device *pci_dev)
2562 {
2563         return rte_eth_dev_pci_generic_probe(pci_dev,
2564                 sizeof(struct ena_adapter), eth_ena_dev_init);
2565 }
2566
2567 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2568 {
2569         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2570 }
2571
2572 static struct rte_pci_driver rte_ena_pmd = {
2573         .id_table = pci_id_ena_map,
2574         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2575                      RTE_PCI_DRV_WC_ACTIVATE,
2576         .probe = eth_ena_pci_probe,
2577         .remove = eth_ena_pci_remove,
2578 };
2579
2580 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2581 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2582 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2583
2584 RTE_INIT(ena_init_log)
2585 {
2586         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2587         if (ena_logtype_init >= 0)
2588                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2589         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2590         if (ena_logtype_driver >= 0)
2591                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2592
2593 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2594         ena_logtype_rx = rte_log_register("pmd.net.ena.rx");
2595         if (ena_logtype_rx >= 0)
2596                 rte_log_set_level(ena_logtype_rx, RTE_LOG_NOTICE);
2597 #endif
2598
2599 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2600         ena_logtype_tx = rte_log_register("pmd.net.ena.tx");
2601         if (ena_logtype_tx >= 0)
2602                 rte_log_set_level(ena_logtype_tx, RTE_LOG_NOTICE);
2603 #endif
2604
2605 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2606         ena_logtype_tx_free = rte_log_register("pmd.net.ena.tx_free");
2607         if (ena_logtype_tx_free >= 0)
2608                 rte_log_set_level(ena_logtype_tx_free, RTE_LOG_NOTICE);
2609 #endif
2610
2611 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2612         ena_logtype_com = rte_log_register("pmd.net.ena.com");
2613         if (ena_logtype_com >= 0)
2614                 rte_log_set_level(ena_logtype_com, RTE_LOG_NOTICE);
2615 #endif
2616 }
2617
2618 /******************************************************************************
2619  ******************************** AENQ Handlers *******************************
2620  *****************************************************************************/
2621 static void ena_update_on_link_change(void *adapter_data,
2622                                       struct ena_admin_aenq_entry *aenq_e)
2623 {
2624         struct rte_eth_dev *eth_dev;
2625         struct ena_adapter *adapter;
2626         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2627         uint32_t status;
2628
2629         adapter = adapter_data;
2630         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2631         eth_dev = adapter->rte_dev;
2632
2633         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2634         adapter->link_status = status;
2635
2636         ena_link_update(eth_dev, 0);
2637         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2638 }
2639
2640 static void ena_notification(void *data,
2641                              struct ena_admin_aenq_entry *aenq_e)
2642 {
2643         struct ena_adapter *adapter = data;
2644         struct ena_admin_ena_hw_hints *hints;
2645
2646         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2647                 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2648                         aenq_e->aenq_common_desc.group,
2649                         ENA_ADMIN_NOTIFICATION);
2650
2651         switch (aenq_e->aenq_common_desc.syndrom) {
2652         case ENA_ADMIN_UPDATE_HINTS:
2653                 hints = (struct ena_admin_ena_hw_hints *)
2654                         (&aenq_e->inline_data_w4);
2655                 ena_update_hints(adapter, hints);
2656                 break;
2657         default:
2658                 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2659                         aenq_e->aenq_common_desc.syndrom);
2660         }
2661 }
2662
2663 static void ena_keep_alive(void *adapter_data,
2664                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2665 {
2666         struct ena_adapter *adapter = adapter_data;
2667         struct ena_admin_aenq_keep_alive_desc *desc;
2668         uint64_t rx_drops;
2669
2670         adapter->timestamp_wd = rte_get_timer_cycles();
2671
2672         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2673         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2674         rte_atomic64_set(&adapter->drv_stats->rx_drops, rx_drops);
2675 }
2676
2677 /**
2678  * This handler will called for unknown event group or unimplemented handlers
2679  **/
2680 static void unimplemented_aenq_handler(__rte_unused void *data,
2681                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2682 {
2683         PMD_DRV_LOG(ERR, "Unknown event was received or event with "
2684                           "unimplemented handler\n");
2685 }
2686
2687 static struct ena_aenq_handlers aenq_handlers = {
2688         .handlers = {
2689                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2690                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2691                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2692         },
2693         .unimplemented_handler = unimplemented_aenq_handler
2694 };