drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_string_fns.h>
  35 #include <rte_ether.h>
  36 #include <rte_ethdev_driver.h>
  37 #include <rte_ethdev_pci.h>
  38 #include <rte_tcp.h>
  39 #include <rte_atomic.h>
  40 #include <rte_dev.h>
  41 #include <rte_errno.h>
  42 #include <rte_version.h>
  43 #include <rte_eal_memconfig.h>
  44 #include <rte_net.h>
  45
  46 #include "ena_ethdev.h"
  47 #include "ena_logs.h"
  48 #include "ena_platform.h"
  49 #include "ena_com.h"
  50 #include "ena_eth_com.h"
  51
  52 #include <ena_common_defs.h>
  53 #include <ena_regs_defs.h>
  54 #include <ena_admin_defs.h>
  55 #include <ena_eth_io_defs.h>
  56
  57 #define DRV_MODULE_VER_MAJOR    2
  58 #define DRV_MODULE_VER_MINOR    0
  59 #define DRV_MODULE_VER_SUBMINOR 0
  60
  61 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  62 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  63 /*reverse version of ENA_IO_RXQ_IDX*/
  64 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  65
  66 /* While processing submitted and completed descriptors (rx and tx path
  67  * respectively) in a loop it is desired to:
  68  *  - perform batch submissions while populating sumbissmion queue
  69  *  - avoid blocking transmission of other packets during cleanup phase
  70  * Hence the utilization ratio of 1/8 of a queue size.
  71  */
  72 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  73
  74 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  75 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  76
  77 #define GET_L4_HDR_LEN(mbuf)                                    \
  78         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  79                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  80
  81 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  82 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  83 #define ENA_HASH_KEY_SIZE       40
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 #define ENA_MIN_RING_DESC       128
  89
  90 enum ethtool_stringset {
  91         ETH_SS_TEST             = 0,
  92         ETH_SS_STATS,
  93 };
  94
  95 struct ena_stats {
  96         char name[ETH_GSTRING_LEN];
  97         int stat_offset;
  98 };
  99
 100 #define ENA_STAT_ENTRY(stat, stat_type) { \
 101         .name = #stat, \
 102         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 103 }
 104
 105 #define ENA_STAT_RX_ENTRY(stat) \
 106         ENA_STAT_ENTRY(stat, rx)
 107
 108 #define ENA_STAT_TX_ENTRY(stat) \
 109         ENA_STAT_ENTRY(stat, tx)
 110
 111 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, dev)
 113
 114 #define ENA_MAX_RING_SIZE_RX 8192
 115 #define ENA_MAX_RING_SIZE_TX 1024
 116
 117 /*
 118  * Each rte_memzone should have unique name.
 119  * To satisfy it, count number of allocation and add it to name.
 120  */
 121 uint32_t ena_alloc_cnt;
 122
 123 static const struct ena_stats ena_stats_global_strings[] = {
 124         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 125         ENA_STAT_GLOBAL_ENTRY(dev_start),
 126         ENA_STAT_GLOBAL_ENTRY(dev_stop),
 127 };
 128
 129 static const struct ena_stats ena_stats_tx_strings[] = {
 130         ENA_STAT_TX_ENTRY(cnt),
 131         ENA_STAT_TX_ENTRY(bytes),
 132         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 133         ENA_STAT_TX_ENTRY(linearize),
 134         ENA_STAT_TX_ENTRY(linearize_failed),
 135         ENA_STAT_TX_ENTRY(tx_poll),
 136         ENA_STAT_TX_ENTRY(doorbells),
 137         ENA_STAT_TX_ENTRY(bad_req_id),
 138         ENA_STAT_TX_ENTRY(available_desc),
 139 };
 140
 141 static const struct ena_stats ena_stats_rx_strings[] = {
 142         ENA_STAT_RX_ENTRY(cnt),
 143         ENA_STAT_RX_ENTRY(bytes),
 144         ENA_STAT_RX_ENTRY(refill_partial),
 145         ENA_STAT_RX_ENTRY(bad_csum),
 146         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 147         ENA_STAT_RX_ENTRY(bad_desc_num),
 148         ENA_STAT_RX_ENTRY(bad_req_id),
 149 };
 150
 151 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 152 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 153 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 154
 155 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 156                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 157                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 158                         DEV_TX_OFFLOAD_TCP_TSO)
 159 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 160                        PKT_TX_IP_CKSUM |\
 161                        PKT_TX_TCP_SEG)
 162
 163 /** Vendor ID used by Amazon devices */
 164 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 165 /** Amazon devices */
 166 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 167 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 168
 169 #define ENA_TX_OFFLOAD_MASK     (\
 170         PKT_TX_L4_MASK |         \
 171         PKT_TX_IPV6 |            \
 172         PKT_TX_IPV4 |            \
 173         PKT_TX_IP_CKSUM |        \
 174         PKT_TX_TCP_SEG)
 175
 176 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 177         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 178
 179 int ena_logtype_init;
 180 int ena_logtype_driver;
 181
 182 static const struct rte_pci_id pci_id_ena_map[] = {
 183         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 184         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 185         { .device_id = 0 },
 186 };
 187
 188 static struct ena_aenq_handlers aenq_handlers;
 189
 190 static int ena_device_init(struct ena_com_dev *ena_dev,
 191                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 192                            bool *wd_state);
 193 static int ena_dev_configure(struct rte_eth_dev *dev);
 194 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 195                                   uint16_t nb_pkts);
 196 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 197                 uint16_t nb_pkts);
 198 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 199                               uint16_t nb_desc, unsigned int socket_id,
 200                               const struct rte_eth_txconf *tx_conf);
 201 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 202                               uint16_t nb_desc, unsigned int socket_id,
 203                               const struct rte_eth_rxconf *rx_conf,
 204                               struct rte_mempool *mp);
 205 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 206                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 207 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 208 static void ena_init_rings(struct ena_adapter *adapter);
 209 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 210 static int ena_start(struct rte_eth_dev *dev);
 211 static void ena_stop(struct rte_eth_dev *dev);
 212 static void ena_close(struct rte_eth_dev *dev);
 213 static int ena_dev_reset(struct rte_eth_dev *dev);
 214 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 215 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 216 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 217 static void ena_rx_queue_release(void *queue);
 218 static void ena_tx_queue_release(void *queue);
 219 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 220 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 221 static int ena_link_update(struct rte_eth_dev *dev,
 222                            int wait_to_complete);
 223 static int ena_create_io_queue(struct ena_ring *ring);
 224 static void ena_queue_stop(struct ena_ring *ring);
 225 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 226                               enum ena_ring_type ring_type);
 227 static int ena_queue_start(struct ena_ring *ring);
 228 static int ena_queue_start_all(struct rte_eth_dev *dev,
 229                                enum ena_ring_type ring_type);
 230 static void ena_stats_restart(struct rte_eth_dev *dev);
 231 static void ena_infos_get(struct rte_eth_dev *dev,
 232                           struct rte_eth_dev_info *dev_info);
 233 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 234                                struct rte_eth_rss_reta_entry64 *reta_conf,
 235                                uint16_t reta_size);
 236 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 237                               struct rte_eth_rss_reta_entry64 *reta_conf,
 238                               uint16_t reta_size);
 239 static void ena_interrupt_handler_rte(void *cb_arg);
 240 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 241 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 242 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 243 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 244                                 struct rte_eth_xstat_name *xstats_names,
 245                                 unsigned int n);
 246 static int ena_xstats_get(struct rte_eth_dev *dev,
 247                           struct rte_eth_xstat *stats,
 248                           unsigned int n);
 249 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 250                                 const uint64_t *ids,
 251                                 uint64_t *values,
 252                                 unsigned int n);
 253
 254 static const struct eth_dev_ops ena_dev_ops = {
 255         .dev_configure        = ena_dev_configure,
 256         .dev_infos_get        = ena_infos_get,
 257         .rx_queue_setup       = ena_rx_queue_setup,
 258         .tx_queue_setup       = ena_tx_queue_setup,
 259         .dev_start            = ena_start,
 260         .dev_stop             = ena_stop,
 261         .link_update          = ena_link_update,
 262         .stats_get            = ena_stats_get,
 263         .xstats_get_names     = ena_xstats_get_names,
 264         .xstats_get           = ena_xstats_get,
 265         .xstats_get_by_id     = ena_xstats_get_by_id,
 266         .mtu_set              = ena_mtu_set,
 267         .rx_queue_release     = ena_rx_queue_release,
 268         .tx_queue_release     = ena_tx_queue_release,
 269         .dev_close            = ena_close,
 270         .dev_reset            = ena_dev_reset,
 271         .reta_update          = ena_rss_reta_update,
 272         .reta_query           = ena_rss_reta_query,
 273 };
 274
 275 #define NUMA_NO_NODE    SOCKET_ID_ANY
 276
 277 static inline int ena_cpu_to_node(int cpu)
 278 {
 279         struct rte_config *config = rte_eal_get_configuration();
 280         struct rte_fbarray *arr = &config->mem_config->memzones;
 281         const struct rte_memzone *mz;
 282
 283         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 284                 return NUMA_NO_NODE;
 285
 286         mz = rte_fbarray_get(arr, cpu);
 287
 288         return mz->socket_id;
 289 }
 290
 291 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 292                                        struct ena_com_rx_ctx *ena_rx_ctx)
 293 {
 294         uint64_t ol_flags = 0;
 295         uint32_t packet_type = 0;
 296
 297         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 298                 packet_type |= RTE_PTYPE_L4_TCP;
 299         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 300                 packet_type |= RTE_PTYPE_L4_UDP;
 301
 302         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 303                 packet_type |= RTE_PTYPE_L3_IPV4;
 304         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 305                 packet_type |= RTE_PTYPE_L3_IPV6;
 306
 307         if (unlikely(ena_rx_ctx->l4_csum_err))
 308                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 309         if (unlikely(ena_rx_ctx->l3_csum_err))
 310                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 311
 312         mbuf->ol_flags = ol_flags;
 313         mbuf->packet_type = packet_type;
 314 }
 315
 316 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 317                                        struct ena_com_tx_ctx *ena_tx_ctx,
 318                                        uint64_t queue_offloads)
 319 {
 320         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 321
 322         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 323             (queue_offloads & QUEUE_OFFLOADS)) {
 324                 /* check if TSO is required */
 325                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 326                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 327                         ena_tx_ctx->tso_enable = true;
 328
 329                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 330                 }
 331
 332                 /* check if L3 checksum is needed */
 333                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 334                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 335                         ena_tx_ctx->l3_csum_enable = true;
 336
 337                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 338                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 339                 } else {
 340                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 341
 342                         /* set don't fragment (DF) flag */
 343                         if (mbuf->packet_type &
 344                                 (RTE_PTYPE_L4_NONFRAG
 345                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 346                                 ena_tx_ctx->df = true;
 347                 }
 348
 349                 /* check if L4 checksum is needed */
 350                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 351                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 352                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 353                         ena_tx_ctx->l4_csum_enable = true;
 354                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 355                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 356                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 357                         ena_tx_ctx->l4_csum_enable = true;
 358                 } else {
 359                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 360                         ena_tx_ctx->l4_csum_enable = false;
 361                 }
 362
 363                 ena_meta->mss = mbuf->tso_segsz;
 364                 ena_meta->l3_hdr_len = mbuf->l3_len;
 365                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 366
 367                 ena_tx_ctx->meta_valid = true;
 368         } else {
 369                 ena_tx_ctx->meta_valid = false;
 370         }
 371 }
 372
 373 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 374 {
 375         if (likely(req_id < rx_ring->ring_size))
 376                 return 0;
 377
 378         RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
 379
 380         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 381         rx_ring->adapter->trigger_reset = true;
 382         ++rx_ring->rx_stats.bad_req_id;
 383
 384         return -EFAULT;
 385 }
 386
 387 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 388 {
 389         struct ena_tx_buffer *tx_info = NULL;
 390
 391         if (likely(req_id < tx_ring->ring_size)) {
 392                 tx_info = &tx_ring->tx_buffer_info[req_id];
 393                 if (likely(tx_info->mbuf))
 394                         return 0;
 395         }
 396
 397         if (tx_info)
 398                 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n");
 399         else
 400                 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id);
 401
 402         /* Trigger device reset */
 403         ++tx_ring->tx_stats.bad_req_id;
 404         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 405         tx_ring->adapter->trigger_reset = true;
 406         return -EFAULT;
 407 }
 408
 409 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 410 {
 411         struct ena_admin_host_info *host_info;
 412         int rc;
 413
 414         /* Allocate only the host info */
 415         rc = ena_com_allocate_host_info(ena_dev);
 416         if (rc) {
 417                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 418                 return;
 419         }
 420
 421         host_info = ena_dev->host_attr.host_info;
 422
 423         host_info->os_type = ENA_ADMIN_OS_DPDK;
 424         host_info->kernel_ver = RTE_VERSION;
 425         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 426                 sizeof(host_info->kernel_ver_str));
 427         host_info->os_dist = RTE_VERSION;
 428         strlcpy((char *)host_info->os_dist_str, rte_version(),
 429                 sizeof(host_info->os_dist_str));
 430         host_info->driver_version =
 431                 (DRV_MODULE_VER_MAJOR) |
 432                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 433                 (DRV_MODULE_VER_SUBMINOR <<
 434                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 435         host_info->num_cpus = rte_lcore_count();
 436
 437         rc = ena_com_set_host_attributes(ena_dev);
 438         if (rc) {
 439                 if (rc == -ENA_COM_UNSUPPORTED)
 440                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 441                 else
 442                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 443
 444                 goto err;
 445         }
 446
 447         return;
 448
 449 err:
 450         ena_com_delete_host_info(ena_dev);
 451 }
 452
 453 /* This function calculates the number of xstats based on the current config */
 454 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
 455 {
 456         return ENA_STATS_ARRAY_GLOBAL +
 457                 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 458                 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 459 }
 460
 461 static void ena_config_debug_area(struct ena_adapter *adapter)
 462 {
 463         u32 debug_area_size;
 464         int rc, ss_count;
 465
 466         ss_count = ena_xstats_calc_num(adapter->rte_dev);
 467
 468         /* allocate 32 bytes for each string and 64bit for the value */
 469         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 470
 471         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 472         if (rc) {
 473                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 474                 return;
 475         }
 476
 477         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 478         if (rc) {
 479                 if (rc == -ENA_COM_UNSUPPORTED)
 480                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 481                 else
 482                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 483
 484                 goto err;
 485         }
 486
 487         return;
 488 err:
 489         ena_com_delete_debug_area(&adapter->ena_dev);
 490 }
 491
 492 static void ena_close(struct rte_eth_dev *dev)
 493 {
 494         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 495         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 496         struct ena_adapter *adapter = dev->data->dev_private;
 497
 498         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 499                 ena_stop(dev);
 500         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 501
 502         ena_rx_queue_release_all(dev);
 503         ena_tx_queue_release_all(dev);
 504
 505         rte_free(adapter->drv_stats);
 506         adapter->drv_stats = NULL;
 507
 508         rte_intr_disable(intr_handle);
 509         rte_intr_callback_unregister(intr_handle,
 510                                      ena_interrupt_handler_rte,
 511                                      adapter);
 512
 513         /*
 514          * MAC is not allocated dynamically. Setting NULL should prevent from
 515          * release of the resource in the rte_eth_dev_release_port().
 516          */
 517         dev->data->mac_addrs = NULL;
 518 }
 519
 520 static int
 521 ena_dev_reset(struct rte_eth_dev *dev)
 522 {
 523         int rc = 0;
 524
 525         ena_destroy_device(dev);
 526         rc = eth_ena_dev_init(dev);
 527         if (rc)
 528                 PMD_INIT_LOG(CRIT, "Cannot initialize device");
 529
 530         return rc;
 531 }
 532
 533 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 534                                struct rte_eth_rss_reta_entry64 *reta_conf,
 535                                uint16_t reta_size)
 536 {
 537         struct ena_adapter *adapter = dev->data->dev_private;
 538         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 539         int rc, i;
 540         u16 entry_value;
 541         int conf_idx;
 542         int idx;
 543
 544         if ((reta_size == 0) || (reta_conf == NULL))
 545                 return -EINVAL;
 546
 547         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 548                 RTE_LOG(WARNING, PMD,
 549                         "indirection table %d is bigger than supported (%d)\n",
 550                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 551                 return -EINVAL;
 552         }
 553
 554         for (i = 0 ; i < reta_size ; i++) {
 555                 /* each reta_conf is for 64 entries.
 556                  * to support 128 we use 2 conf of 64
 557                  */
 558                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 559                 idx = i % RTE_RETA_GROUP_SIZE;
 560                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 561                         entry_value =
 562                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 563
 564                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 565                                                                i,
 566                                                                entry_value);
 567                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 568                                 RTE_LOG(ERR, PMD,
 569                                         "Cannot fill indirect table\n");
 570                                 return rc;
 571                         }
 572                 }
 573         }
 574
 575         rc = ena_com_indirect_table_set(ena_dev);
 576         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 577                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 578                 return rc;
 579         }
 580
 581         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 582                 __func__, reta_size, adapter->rte_dev->data->port_id);
 583
 584         return 0;
 585 }
 586
 587 /* Query redirection table. */
 588 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 589                               struct rte_eth_rss_reta_entry64 *reta_conf,
 590                               uint16_t reta_size)
 591 {
 592         struct ena_adapter *adapter = dev->data->dev_private;
 593         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 594         int rc;
 595         int i;
 596         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 597         int reta_conf_idx;
 598         int reta_idx;
 599
 600         if (reta_size == 0 || reta_conf == NULL ||
 601             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 602                 return -EINVAL;
 603
 604         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 605         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 606                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 607                 return -ENOTSUP;
 608         }
 609
 610         for (i = 0 ; i < reta_size ; i++) {
 611                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 612                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 613                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 614                         reta_conf[reta_conf_idx].reta[reta_idx] =
 615                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 616         }
 617
 618         return 0;
 619 }
 620
 621 static int ena_rss_init_default(struct ena_adapter *adapter)
 622 {
 623         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 624         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 625         int rc, i;
 626         u32 val;
 627
 628         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 629         if (unlikely(rc)) {
 630                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 631                 goto err_rss_init;
 632         }
 633
 634         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 635                 val = i % nb_rx_queues;
 636                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 637                                                        ENA_IO_RXQ_IDX(val));
 638                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 639                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 640                         goto err_fill_indir;
 641                 }
 642         }
 643
 644         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 645                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 646         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 647                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 648                 goto err_fill_indir;
 649         }
 650
 651         rc = ena_com_set_default_hash_ctrl(ena_dev);
 652         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 653                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 654                 goto err_fill_indir;
 655         }
 656
 657         rc = ena_com_indirect_table_set(ena_dev);
 658         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 659                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 660                 goto err_fill_indir;
 661         }
 662         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 663                 adapter->rte_dev->data->port_id);
 664
 665         return 0;
 666
 667 err_fill_indir:
 668         ena_com_rss_destroy(ena_dev);
 669 err_rss_init:
 670
 671         return rc;
 672 }
 673
 674 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 675 {
 676         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 677         int nb_queues = dev->data->nb_rx_queues;
 678         int i;
 679
 680         for (i = 0; i < nb_queues; i++)
 681                 ena_rx_queue_release(queues[i]);
 682 }
 683
 684 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 685 {
 686         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 687         int nb_queues = dev->data->nb_tx_queues;
 688         int i;
 689
 690         for (i = 0; i < nb_queues; i++)
 691                 ena_tx_queue_release(queues[i]);
 692 }
 693
 694 static void ena_rx_queue_release(void *queue)
 695 {
 696         struct ena_ring *ring = (struct ena_ring *)queue;
 697
 698         /* Free ring resources */
 699         if (ring->rx_buffer_info)
 700                 rte_free(ring->rx_buffer_info);
 701         ring->rx_buffer_info = NULL;
 702
 703         if (ring->rx_refill_buffer)
 704                 rte_free(ring->rx_refill_buffer);
 705         ring->rx_refill_buffer = NULL;
 706
 707         if (ring->empty_rx_reqs)
 708                 rte_free(ring->empty_rx_reqs);
 709         ring->empty_rx_reqs = NULL;
 710
 711         ring->configured = 0;
 712
 713         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 714                 ring->port_id, ring->id);
 715 }
 716
 717 static void ena_tx_queue_release(void *queue)
 718 {
 719         struct ena_ring *ring = (struct ena_ring *)queue;
 720
 721         /* Free ring resources */
 722         if (ring->push_buf_intermediate_buf)
 723                 rte_free(ring->push_buf_intermediate_buf);
 724
 725         if (ring->tx_buffer_info)
 726                 rte_free(ring->tx_buffer_info);
 727
 728         if (ring->empty_tx_reqs)
 729                 rte_free(ring->empty_tx_reqs);
 730
 731         ring->empty_tx_reqs = NULL;
 732         ring->tx_buffer_info = NULL;
 733         ring->push_buf_intermediate_buf = NULL;
 734
 735         ring->configured = 0;
 736
 737         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 738                 ring->port_id, ring->id);
 739 }
 740
 741 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 742 {
 743         unsigned int i;
 744
 745         for (i = 0; i < ring->ring_size; ++i)
 746                 if (ring->rx_buffer_info[i]) {
 747                         rte_mbuf_raw_free(ring->rx_buffer_info[i]);
 748                         ring->rx_buffer_info[i] = NULL;
 749                 }
 750 }
 751
 752 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 753 {
 754         unsigned int i;
 755
 756         for (i = 0; i < ring->ring_size; ++i) {
 757                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 758
 759                 if (tx_buf->mbuf)
 760                         rte_pktmbuf_free(tx_buf->mbuf);
 761         }
 762 }
 763
 764 static int ena_link_update(struct rte_eth_dev *dev,
 765                            __rte_unused int wait_to_complete)
 766 {
 767         struct rte_eth_link *link = &dev->data->dev_link;
 768         struct ena_adapter *adapter = dev->data->dev_private;
 769
 770         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 771         link->link_speed = ETH_SPEED_NUM_NONE;
 772         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 773
 774         return 0;
 775 }
 776
 777 static int ena_queue_start_all(struct rte_eth_dev *dev,
 778                                enum ena_ring_type ring_type)
 779 {
 780         struct ena_adapter *adapter = dev->data->dev_private;
 781         struct ena_ring *queues = NULL;
 782         int nb_queues;
 783         int i = 0;
 784         int rc = 0;
 785
 786         if (ring_type == ENA_RING_TYPE_RX) {
 787                 queues = adapter->rx_ring;
 788                 nb_queues = dev->data->nb_rx_queues;
 789         } else {
 790                 queues = adapter->tx_ring;
 791                 nb_queues = dev->data->nb_tx_queues;
 792         }
 793         for (i = 0; i < nb_queues; i++) {
 794                 if (queues[i].configured) {
 795                         if (ring_type == ENA_RING_TYPE_RX) {
 796                                 ena_assert_msg(
 797                                         dev->data->rx_queues[i] == &queues[i],
 798                                         "Inconsistent state of rx queues\n");
 799                         } else {
 800                                 ena_assert_msg(
 801                                         dev->data->tx_queues[i] == &queues[i],
 802                                         "Inconsistent state of tx queues\n");
 803                         }
 804
 805                         rc = ena_queue_start(&queues[i]);
 806
 807                         if (rc) {
 808                                 PMD_INIT_LOG(ERR,
 809                                              "failed to start queue %d type(%d)",
 810                                              i, ring_type);
 811                                 goto err;
 812                         }
 813                 }
 814         }
 815
 816         return 0;
 817
 818 err:
 819         while (i--)
 820                 if (queues[i].configured)
 821                         ena_queue_stop(&queues[i]);
 822
 823         return rc;
 824 }
 825
 826 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 827 {
 828         uint32_t max_frame_len = adapter->max_mtu;
 829
 830         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 831             DEV_RX_OFFLOAD_JUMBO_FRAME)
 832                 max_frame_len =
 833                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 834
 835         return max_frame_len;
 836 }
 837
 838 static int ena_check_valid_conf(struct ena_adapter *adapter)
 839 {
 840         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 841
 842         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 843                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 844                                   "max mtu: %d, min mtu: %d",
 845                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 846                 return ENA_COM_UNSUPPORTED;
 847         }
 848
 849         return 0;
 850 }
 851
 852 static int
 853 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)
 854 {
 855         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 856         struct ena_com_dev *ena_dev = ctx->ena_dev;
 857         uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX;
 858         uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX;
 859
 860         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 861                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 862                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 863                 rx_queue_size = RTE_MIN(rx_queue_size,
 864                         max_queue_ext->max_rx_cq_depth);
 865                 rx_queue_size = RTE_MIN(rx_queue_size,
 866                         max_queue_ext->max_rx_sq_depth);
 867                 tx_queue_size = RTE_MIN(tx_queue_size,
 868                         max_queue_ext->max_tx_cq_depth);
 869
 870                 if (ena_dev->tx_mem_queue_type ==
 871                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 872                         tx_queue_size = RTE_MIN(tx_queue_size,
 873                                 llq->max_llq_depth);
 874                 } else {
 875                         tx_queue_size = RTE_MIN(tx_queue_size,
 876                                 max_queue_ext->max_tx_sq_depth);
 877                 }
 878
 879                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 880                         max_queue_ext->max_per_packet_rx_descs);
 881                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 882                         max_queue_ext->max_per_packet_tx_descs);
 883         } else {
 884                 struct ena_admin_queue_feature_desc *max_queues =
 885                         &ctx->get_feat_ctx->max_queues;
 886                 rx_queue_size = RTE_MIN(rx_queue_size,
 887                         max_queues->max_cq_depth);
 888                 rx_queue_size = RTE_MIN(rx_queue_size,
 889                         max_queues->max_sq_depth);
 890                 tx_queue_size = RTE_MIN(tx_queue_size,
 891                         max_queues->max_cq_depth);
 892
 893                 if (ena_dev->tx_mem_queue_type ==
 894                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 895                         tx_queue_size = RTE_MIN(tx_queue_size,
 896                                 llq->max_llq_depth);
 897                 } else {
 898                         tx_queue_size = RTE_MIN(tx_queue_size,
 899                                 max_queues->max_sq_depth);
 900                 }
 901
 902                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 903                         max_queues->max_packet_tx_descs);
 904                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 905                         max_queues->max_packet_rx_descs);
 906         }
 907
 908         /* Round down to the nearest power of 2 */
 909         rx_queue_size = rte_align32prevpow2(rx_queue_size);
 910         tx_queue_size = rte_align32prevpow2(tx_queue_size);
 911
 912         if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) {
 913                 PMD_INIT_LOG(ERR, "Invalid queue size");
 914                 return -EFAULT;
 915         }
 916
 917         ctx->rx_queue_size = rx_queue_size;
 918         ctx->tx_queue_size = tx_queue_size;
 919
 920         return 0;
 921 }
 922
 923 static void ena_stats_restart(struct rte_eth_dev *dev)
 924 {
 925         struct ena_adapter *adapter = dev->data->dev_private;
 926
 927         rte_atomic64_init(&adapter->drv_stats->ierrors);
 928         rte_atomic64_init(&adapter->drv_stats->oerrors);
 929         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 930         rte_atomic64_init(&adapter->drv_stats->rx_drops);
 931 }
 932
 933 static int ena_stats_get(struct rte_eth_dev *dev,
 934                           struct rte_eth_stats *stats)
 935 {
 936         struct ena_admin_basic_stats ena_stats;
 937         struct ena_adapter *adapter = dev->data->dev_private;
 938         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 939         int rc;
 940         int i;
 941         int max_rings_stats;
 942
 943         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 944                 return -ENOTSUP;
 945
 946         memset(&ena_stats, 0, sizeof(ena_stats));
 947         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 948         if (unlikely(rc)) {
 949                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA\n");
 950                 return rc;
 951         }
 952
 953         /* Set of basic statistics from ENA */
 954         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 955                                           ena_stats.rx_pkts_low);
 956         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 957                                           ena_stats.tx_pkts_low);
 958         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 959                                         ena_stats.rx_bytes_low);
 960         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 961                                         ena_stats.tx_bytes_low);
 962
 963         /* Driver related stats */
 964         stats->imissed = rte_atomic64_read(&adapter->drv_stats->rx_drops);
 965         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 966         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 967         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 968
 969         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
 970                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 971         for (i = 0; i < max_rings_stats; ++i) {
 972                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
 973
 974                 stats->q_ibytes[i] = rx_stats->bytes;
 975                 stats->q_ipackets[i] = rx_stats->cnt;
 976                 stats->q_errors[i] = rx_stats->bad_desc_num +
 977                         rx_stats->bad_req_id;
 978         }
 979
 980         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
 981                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 982         for (i = 0; i < max_rings_stats; ++i) {
 983                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
 984
 985                 stats->q_obytes[i] = tx_stats->bytes;
 986                 stats->q_opackets[i] = tx_stats->cnt;
 987         }
 988
 989         return 0;
 990 }
 991
 992 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 993 {
 994         struct ena_adapter *adapter;
 995         struct ena_com_dev *ena_dev;
 996         int rc = 0;
 997
 998         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
 999         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1000         adapter = dev->data->dev_private;
1001
1002         ena_dev = &adapter->ena_dev;
1003         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1004
1005         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1006                 RTE_LOG(ERR, PMD,
1007                         "Invalid MTU setting. new_mtu: %d "
1008                         "max mtu: %d min mtu: %d\n",
1009                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1010                 return -EINVAL;
1011         }
1012
1013         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1014         if (rc)
1015                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
1016         else
1017                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1018
1019         return rc;
1020 }
1021
1022 static int ena_start(struct rte_eth_dev *dev)
1023 {
1024         struct ena_adapter *adapter = dev->data->dev_private;
1025         uint64_t ticks;
1026         int rc = 0;
1027
1028         rc = ena_check_valid_conf(adapter);
1029         if (rc)
1030                 return rc;
1031
1032         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1033         if (rc)
1034                 return rc;
1035
1036         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1037         if (rc)
1038                 goto err_start_tx;
1039
1040         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1041             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1042                 rc = ena_rss_init_default(adapter);
1043                 if (rc)
1044                         goto err_rss_init;
1045         }
1046
1047         ena_stats_restart(dev);
1048
1049         adapter->timestamp_wd = rte_get_timer_cycles();
1050         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1051
1052         ticks = rte_get_timer_hz();
1053         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1054                         ena_timer_wd_callback, adapter);
1055
1056         ++adapter->dev_stats.dev_start;
1057         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1058
1059         return 0;
1060
1061 err_rss_init:
1062         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1063 err_start_tx:
1064         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1065         return rc;
1066 }
1067
1068 static void ena_stop(struct rte_eth_dev *dev)
1069 {
1070         struct ena_adapter *adapter = dev->data->dev_private;
1071         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1072         int rc;
1073
1074         rte_timer_stop_sync(&adapter->timer_wd);
1075         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1076         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1077
1078         if (adapter->trigger_reset) {
1079                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1080                 if (rc)
1081                         RTE_LOG(ERR, PMD, "Device reset failed rc=%d\n", rc);
1082         }
1083
1084         ++adapter->dev_stats.dev_stop;
1085         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1086 }
1087
1088 static int ena_create_io_queue(struct ena_ring *ring)
1089 {
1090         struct ena_adapter *adapter;
1091         struct ena_com_dev *ena_dev;
1092         struct ena_com_create_io_ctx ctx =
1093                 /* policy set to _HOST just to satisfy icc compiler */
1094                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1095                   0, 0, 0, 0, 0 };
1096         uint16_t ena_qid;
1097         unsigned int i;
1098         int rc;
1099
1100         adapter = ring->adapter;
1101         ena_dev = &adapter->ena_dev;
1102
1103         if (ring->type == ENA_RING_TYPE_TX) {
1104                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1105                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1106                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1107                 ctx.queue_size = adapter->tx_ring_size;
1108                 for (i = 0; i < ring->ring_size; i++)
1109                         ring->empty_tx_reqs[i] = i;
1110         } else {
1111                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1112                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1113                 ctx.queue_size = adapter->rx_ring_size;
1114                 for (i = 0; i < ring->ring_size; i++)
1115                         ring->empty_rx_reqs[i] = i;
1116         }
1117         ctx.qid = ena_qid;
1118         ctx.msix_vector = -1; /* interrupts not used */
1119         ctx.numa_node = ena_cpu_to_node(ring->id);
1120
1121         rc = ena_com_create_io_queue(ena_dev, &ctx);
1122         if (rc) {
1123                 RTE_LOG(ERR, PMD,
1124                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1125                         ring->id, ena_qid, rc);
1126                 return rc;
1127         }
1128
1129         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1130                                      &ring->ena_com_io_sq,
1131                                      &ring->ena_com_io_cq);
1132         if (rc) {
1133                 RTE_LOG(ERR, PMD,
1134                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1135                         ring->id, rc);
1136                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1137                 return rc;
1138         }
1139
1140         if (ring->type == ENA_RING_TYPE_TX)
1141                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1142
1143         return 0;
1144 }
1145
1146 static void ena_queue_stop(struct ena_ring *ring)
1147 {
1148         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1149
1150         if (ring->type == ENA_RING_TYPE_RX) {
1151                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1152                 ena_rx_queue_release_bufs(ring);
1153         } else {
1154                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1155                 ena_tx_queue_release_bufs(ring);
1156         }
1157 }
1158
1159 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1160                               enum ena_ring_type ring_type)
1161 {
1162         struct ena_adapter *adapter = dev->data->dev_private;
1163         struct ena_ring *queues = NULL;
1164         uint16_t nb_queues, i;
1165
1166         if (ring_type == ENA_RING_TYPE_RX) {
1167                 queues = adapter->rx_ring;
1168                 nb_queues = dev->data->nb_rx_queues;
1169         } else {
1170                 queues = adapter->tx_ring;
1171                 nb_queues = dev->data->nb_tx_queues;
1172         }
1173
1174         for (i = 0; i < nb_queues; ++i)
1175                 if (queues[i].configured)
1176                         ena_queue_stop(&queues[i]);
1177 }
1178
1179 static int ena_queue_start(struct ena_ring *ring)
1180 {
1181         int rc, bufs_num;
1182
1183         ena_assert_msg(ring->configured == 1,
1184                        "Trying to start unconfigured queue\n");
1185
1186         rc = ena_create_io_queue(ring);
1187         if (rc) {
1188                 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1189                 return rc;
1190         }
1191
1192         ring->next_to_clean = 0;
1193         ring->next_to_use = 0;
1194
1195         if (ring->type == ENA_RING_TYPE_TX) {
1196                 ring->tx_stats.available_desc =
1197                         ena_com_free_desc(ring->ena_com_io_sq);
1198                 return 0;
1199         }
1200
1201         bufs_num = ring->ring_size - 1;
1202         rc = ena_populate_rx_queue(ring, bufs_num);
1203         if (rc != bufs_num) {
1204                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1205                                          ENA_IO_RXQ_IDX(ring->id));
1206                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1207                 return ENA_COM_FAULT;
1208         }
1209
1210         return 0;
1211 }
1212
1213 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1214                               uint16_t queue_idx,
1215                               uint16_t nb_desc,
1216                               __rte_unused unsigned int socket_id,
1217                               const struct rte_eth_txconf *tx_conf)
1218 {
1219         struct ena_ring *txq = NULL;
1220         struct ena_adapter *adapter = dev->data->dev_private;
1221         unsigned int i;
1222
1223         txq = &adapter->tx_ring[queue_idx];
1224
1225         if (txq->configured) {
1226                 RTE_LOG(CRIT, PMD,
1227                         "API violation. Queue %d is already configured\n",
1228                         queue_idx);
1229                 return ENA_COM_FAULT;
1230         }
1231
1232         if (!rte_is_power_of_2(nb_desc)) {
1233                 RTE_LOG(ERR, PMD,
1234                         "Unsupported size of TX queue: %d is not a power of 2.\n",
1235                         nb_desc);
1236                 return -EINVAL;
1237         }
1238
1239         if (nb_desc > adapter->tx_ring_size) {
1240                 RTE_LOG(ERR, PMD,
1241                         "Unsupported size of TX queue (max size: %d)\n",
1242                         adapter->tx_ring_size);
1243                 return -EINVAL;
1244         }
1245
1246         if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1247                 nb_desc = adapter->tx_ring_size;
1248
1249         txq->port_id = dev->data->port_id;
1250         txq->next_to_clean = 0;
1251         txq->next_to_use = 0;
1252         txq->ring_size = nb_desc;
1253
1254         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1255                                           sizeof(struct ena_tx_buffer) *
1256                                           txq->ring_size,
1257                                           RTE_CACHE_LINE_SIZE);
1258         if (!txq->tx_buffer_info) {
1259                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1260                 return -ENOMEM;
1261         }
1262
1263         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1264                                          sizeof(u16) * txq->ring_size,
1265                                          RTE_CACHE_LINE_SIZE);
1266         if (!txq->empty_tx_reqs) {
1267                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1268                 rte_free(txq->tx_buffer_info);
1269                 return -ENOMEM;
1270         }
1271
1272         txq->push_buf_intermediate_buf =
1273                 rte_zmalloc("txq->push_buf_intermediate_buf",
1274                             txq->tx_max_header_size,
1275                             RTE_CACHE_LINE_SIZE);
1276         if (!txq->push_buf_intermediate_buf) {
1277                 RTE_LOG(ERR, PMD, "failed to alloc push buff for LLQ\n");
1278                 rte_free(txq->tx_buffer_info);
1279                 rte_free(txq->empty_tx_reqs);
1280                 return -ENOMEM;
1281         }
1282
1283         for (i = 0; i < txq->ring_size; i++)
1284                 txq->empty_tx_reqs[i] = i;
1285
1286         if (tx_conf != NULL) {
1287                 txq->offloads =
1288                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1289         }
1290         /* Store pointer to this queue in upper layer */
1291         txq->configured = 1;
1292         dev->data->tx_queues[queue_idx] = txq;
1293
1294         return 0;
1295 }
1296
1297 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1298                               uint16_t queue_idx,
1299                               uint16_t nb_desc,
1300                               __rte_unused unsigned int socket_id,
1301                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1302                               struct rte_mempool *mp)
1303 {
1304         struct ena_adapter *adapter = dev->data->dev_private;
1305         struct ena_ring *rxq = NULL;
1306         int i;
1307
1308         rxq = &adapter->rx_ring[queue_idx];
1309         if (rxq->configured) {
1310                 RTE_LOG(CRIT, PMD,
1311                         "API violation. Queue %d is already configured\n",
1312                         queue_idx);
1313                 return ENA_COM_FAULT;
1314         }
1315
1316         if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1317                 nb_desc = adapter->rx_ring_size;
1318
1319         if (!rte_is_power_of_2(nb_desc)) {
1320                 RTE_LOG(ERR, PMD,
1321                         "Unsupported size of RX queue: %d is not a power of 2.\n",
1322                         nb_desc);
1323                 return -EINVAL;
1324         }
1325
1326         if (nb_desc > adapter->rx_ring_size) {
1327                 RTE_LOG(ERR, PMD,
1328                         "Unsupported size of RX queue (max size: %d)\n",
1329                         adapter->rx_ring_size);
1330                 return -EINVAL;
1331         }
1332
1333         rxq->port_id = dev->data->port_id;
1334         rxq->next_to_clean = 0;
1335         rxq->next_to_use = 0;
1336         rxq->ring_size = nb_desc;
1337         rxq->mb_pool = mp;
1338
1339         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1340                                           sizeof(struct rte_mbuf *) * nb_desc,
1341                                           RTE_CACHE_LINE_SIZE);
1342         if (!rxq->rx_buffer_info) {
1343                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1344                 return -ENOMEM;
1345         }
1346
1347         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1348                                             sizeof(struct rte_mbuf *) * nb_desc,
1349                                             RTE_CACHE_LINE_SIZE);
1350
1351         if (!rxq->rx_refill_buffer) {
1352                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n");
1353                 rte_free(rxq->rx_buffer_info);
1354                 rxq->rx_buffer_info = NULL;
1355                 return -ENOMEM;
1356         }
1357
1358         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1359                                          sizeof(uint16_t) * nb_desc,
1360                                          RTE_CACHE_LINE_SIZE);
1361         if (!rxq->empty_rx_reqs) {
1362                 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1363                 rte_free(rxq->rx_buffer_info);
1364                 rxq->rx_buffer_info = NULL;
1365                 rte_free(rxq->rx_refill_buffer);
1366                 rxq->rx_refill_buffer = NULL;
1367                 return -ENOMEM;
1368         }
1369
1370         for (i = 0; i < nb_desc; i++)
1371                 rxq->empty_rx_reqs[i] = i;
1372
1373         /* Store pointer to this queue in upper layer */
1374         rxq->configured = 1;
1375         dev->data->rx_queues[queue_idx] = rxq;
1376
1377         return 0;
1378 }
1379
1380 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1381 {
1382         unsigned int i;
1383         int rc;
1384         uint16_t ring_size = rxq->ring_size;
1385         uint16_t ring_mask = ring_size - 1;
1386         uint16_t next_to_use = rxq->next_to_use;
1387         uint16_t in_use, req_id;
1388         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1389
1390         if (unlikely(!count))
1391                 return 0;
1392
1393         in_use = rxq->next_to_use - rxq->next_to_clean;
1394         ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n");
1395
1396         /* get resources for incoming packets */
1397         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1398         if (unlikely(rc < 0)) {
1399                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1400                 ++rxq->rx_stats.mbuf_alloc_fail;
1401                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1402                 return 0;
1403         }
1404
1405         for (i = 0; i < count; i++) {
1406                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1407                 struct rte_mbuf *mbuf = mbufs[i];
1408                 struct ena_com_buf ebuf;
1409
1410                 if (likely((i + 4) < count))
1411                         rte_prefetch0(mbufs[i + 4]);
1412
1413                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1414                 rc = validate_rx_req_id(rxq, req_id);
1415                 if (unlikely(rc < 0))
1416                         break;
1417                 rxq->rx_buffer_info[req_id] = mbuf;
1418
1419                 /* prepare physical address for DMA transaction */
1420                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1421                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1422                 /* pass resource to device */
1423                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1424                                                 &ebuf, req_id);
1425                 if (unlikely(rc)) {
1426                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1427                         rxq->rx_buffer_info[req_id] = NULL;
1428                         break;
1429                 }
1430                 next_to_use++;
1431         }
1432
1433         if (unlikely(i < count)) {
1434                 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d "
1435                         "buffers (from %d)\n", rxq->id, i, count);
1436                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1437                                      count - i);
1438                 ++rxq->rx_stats.refill_partial;
1439         }
1440
1441         /* When we submitted free recources to device... */
1442         if (likely(i > 0)) {
1443                 /* ...let HW know that it can fill buffers with data
1444                  *
1445                  * Add memory barrier to make sure the desc were written before
1446                  * issue a doorbell
1447                  */
1448                 rte_wmb();
1449                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1450
1451                 rxq->next_to_use = next_to_use;
1452         }
1453
1454         return i;
1455 }
1456
1457 static int ena_device_init(struct ena_com_dev *ena_dev,
1458                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1459                            bool *wd_state)
1460 {
1461         uint32_t aenq_groups;
1462         int rc;
1463         bool readless_supported;
1464
1465         /* Initialize mmio registers */
1466         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1467         if (rc) {
1468                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1469                 return rc;
1470         }
1471
1472         /* The PCIe configuration space revision id indicate if mmio reg
1473          * read is disabled.
1474          */
1475         readless_supported =
1476                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1477                                & ENA_MMIO_DISABLE_REG_READ);
1478         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1479
1480         /* reset device */
1481         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1482         if (rc) {
1483                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1484                 goto err_mmio_read_less;
1485         }
1486
1487         /* check FW version */
1488         rc = ena_com_validate_version(ena_dev);
1489         if (rc) {
1490                 RTE_LOG(ERR, PMD, "device version is too low\n");
1491                 goto err_mmio_read_less;
1492         }
1493
1494         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1495
1496         /* ENA device administration layer init */
1497         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1498         if (rc) {
1499                 RTE_LOG(ERR, PMD,
1500                         "cannot initialize ena admin queue with device\n");
1501                 goto err_mmio_read_less;
1502         }
1503
1504         /* To enable the msix interrupts the driver needs to know the number
1505          * of queues. So the driver uses polling mode to retrieve this
1506          * information.
1507          */
1508         ena_com_set_admin_polling_mode(ena_dev, true);
1509
1510         ena_config_host_info(ena_dev);
1511
1512         /* Get Device Attributes and features */
1513         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1514         if (rc) {
1515                 RTE_LOG(ERR, PMD,
1516                         "cannot get attribute for ena device rc= %d\n", rc);
1517                 goto err_admin_init;
1518         }
1519
1520         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1521                       BIT(ENA_ADMIN_NOTIFICATION) |
1522                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1523                       BIT(ENA_ADMIN_FATAL_ERROR) |
1524                       BIT(ENA_ADMIN_WARNING);
1525
1526         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1527         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1528         if (rc) {
1529                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1530                 goto err_admin_init;
1531         }
1532
1533         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1534
1535         return 0;
1536
1537 err_admin_init:
1538         ena_com_admin_destroy(ena_dev);
1539
1540 err_mmio_read_less:
1541         ena_com_mmio_reg_read_request_destroy(ena_dev);
1542
1543         return rc;
1544 }
1545
1546 static void ena_interrupt_handler_rte(void *cb_arg)
1547 {
1548         struct ena_adapter *adapter = cb_arg;
1549         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1550
1551         ena_com_admin_q_comp_intr_handler(ena_dev);
1552         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1553                 ena_com_aenq_intr_handler(ena_dev, adapter);
1554 }
1555
1556 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1557 {
1558         if (!adapter->wd_state)
1559                 return;
1560
1561         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1562                 return;
1563
1564         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1565             adapter->keep_alive_timeout)) {
1566                 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1567                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1568                 adapter->trigger_reset = true;
1569                 ++adapter->dev_stats.wd_expired;
1570         }
1571 }
1572
1573 /* Check if admin queue is enabled */
1574 static void check_for_admin_com_state(struct ena_adapter *adapter)
1575 {
1576         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1577                 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1578                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1579                 adapter->trigger_reset = true;
1580         }
1581 }
1582
1583 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1584                                   void *arg)
1585 {
1586         struct ena_adapter *adapter = arg;
1587         struct rte_eth_dev *dev = adapter->rte_dev;
1588
1589         check_for_missing_keep_alive(adapter);
1590         check_for_admin_com_state(adapter);
1591
1592         if (unlikely(adapter->trigger_reset)) {
1593                 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1594                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1595                         NULL);
1596         }
1597 }
1598
1599 static inline void
1600 set_default_llq_configurations(struct ena_llq_configurations *llq_config)
1601 {
1602         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1603         llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1604         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1605         llq_config->llq_num_decs_before_header =
1606                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1607         llq_config->llq_ring_entry_size_value = 128;
1608 }
1609
1610 static int
1611 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1612                                 struct ena_com_dev *ena_dev,
1613                                 struct ena_admin_feature_llq_desc *llq,
1614                                 struct ena_llq_configurations *llq_default_configurations)
1615 {
1616         int rc;
1617         u32 llq_feature_mask;
1618
1619         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1620         if (!(ena_dev->supported_features & llq_feature_mask)) {
1621                 RTE_LOG(INFO, PMD,
1622                         "LLQ is not supported. Fallback to host mode policy.\n");
1623                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1624                 return 0;
1625         }
1626
1627         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1628         if (unlikely(rc)) {
1629                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1630                         "Fallback to host mode policy.");
1631                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1632                 return 0;
1633         }
1634
1635         /* Nothing to config, exit */
1636         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1637                 return 0;
1638
1639         if (!adapter->dev_mem_base) {
1640                 RTE_LOG(ERR, PMD, "Unable to access LLQ bar resource. "
1641                         "Fallback to host mode policy.\n.");
1642                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1643                 return 0;
1644         }
1645
1646         ena_dev->mem_bar = adapter->dev_mem_base;
1647
1648         return 0;
1649 }
1650
1651 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,
1652                                  struct ena_com_dev_get_features_ctx *get_feat_ctx)
1653 {
1654         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num;
1655
1656         /* Regular queues capabilities */
1657         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1658                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1659                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1660                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1661                                     max_queue_ext->max_rx_cq_num);
1662                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1663                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1664         } else {
1665                 struct ena_admin_queue_feature_desc *max_queues =
1666                         &get_feat_ctx->max_queues;
1667                 io_tx_sq_num = max_queues->max_sq_num;
1668                 io_tx_cq_num = max_queues->max_cq_num;
1669                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1670         }
1671
1672         /* In case of LLQ use the llq number in the get feature cmd */
1673         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1674                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1675
1676         io_queue_num = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1677         io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num);
1678         io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num);
1679
1680         if (unlikely(io_queue_num == 0)) {
1681                 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n");
1682                 return -EFAULT;
1683         }
1684
1685         return io_queue_num;
1686 }
1687
1688 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1689 {
1690         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1691         struct rte_pci_device *pci_dev;
1692         struct rte_intr_handle *intr_handle;
1693         struct ena_adapter *adapter = eth_dev->data->dev_private;
1694         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1695         struct ena_com_dev_get_features_ctx get_feat_ctx;
1696         struct ena_llq_configurations llq_config;
1697         const char *queue_type_str;
1698         int rc;
1699
1700         static int adapters_found;
1701         bool wd_state;
1702
1703         eth_dev->dev_ops = &ena_dev_ops;
1704         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1705         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1706         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1707
1708         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1709                 return 0;
1710
1711         memset(adapter, 0, sizeof(struct ena_adapter));
1712         ena_dev = &adapter->ena_dev;
1713
1714         adapter->rte_eth_dev_data = eth_dev->data;
1715         adapter->rte_dev = eth_dev;
1716
1717         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1718         adapter->pdev = pci_dev;
1719
1720         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1721                      pci_dev->addr.domain,
1722                      pci_dev->addr.bus,
1723                      pci_dev->addr.devid,
1724                      pci_dev->addr.function);
1725
1726         intr_handle = &pci_dev->intr_handle;
1727
1728         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1729         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1730
1731         if (!adapter->regs) {
1732                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1733                              ENA_REGS_BAR);
1734                 return -ENXIO;
1735         }
1736
1737         ena_dev->reg_bar = adapter->regs;
1738         ena_dev->dmadev = adapter->pdev;
1739
1740         adapter->id_number = adapters_found;
1741
1742         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1743                  adapter->id_number);
1744
1745         /* device specific initialization routine */
1746         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1747         if (rc) {
1748                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1749                 goto err;
1750         }
1751         adapter->wd_state = wd_state;
1752
1753         set_default_llq_configurations(&llq_config);
1754         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1755                                              &get_feat_ctx.llq, &llq_config);
1756         if (unlikely(rc)) {
1757                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1758                 return rc;
1759         }
1760
1761         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1762                 queue_type_str = "Regular";
1763         else
1764                 queue_type_str = "Low latency";
1765         RTE_LOG(INFO, PMD, "Placement policy: %s\n", queue_type_str);
1766
1767         calc_queue_ctx.ena_dev = ena_dev;
1768         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1769         adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1770                                                     &get_feat_ctx);
1771
1772         rc = ena_calc_queue_size(&calc_queue_ctx);
1773         if (unlikely((rc != 0) || (adapter->num_queues <= 0))) {
1774                 rc = -EFAULT;
1775                 goto err_device_destroy;
1776         }
1777
1778         adapter->tx_ring_size = calc_queue_ctx.tx_queue_size;
1779         adapter->rx_ring_size = calc_queue_ctx.rx_queue_size;
1780
1781         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1782         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1783
1784         /* prepare ring structures */
1785         ena_init_rings(adapter);
1786
1787         ena_config_debug_area(adapter);
1788
1789         /* Set max MTU for this device */
1790         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1791
1792         /* set device support for offloads */
1793         adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1794                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1795         adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1796                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1797         adapter->offloads.rx_csum_supported =
1798                 (get_feat_ctx.offload.rx_supported &
1799                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1800
1801         /* Copy MAC address and point DPDK to it */
1802         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1803         rte_ether_addr_copy((struct rte_ether_addr *)
1804                         get_feat_ctx.dev_attr.mac_addr,
1805                         (struct rte_ether_addr *)adapter->mac_addr);
1806
1807         /*
1808          * Pass the information to the rte_eth_dev_close() that it should also
1809          * release the private port resources.
1810          */
1811         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1812
1813         adapter->drv_stats = rte_zmalloc("adapter stats",
1814                                          sizeof(*adapter->drv_stats),
1815                                          RTE_CACHE_LINE_SIZE);
1816         if (!adapter->drv_stats) {
1817                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1818                 rc = -ENOMEM;
1819                 goto err_delete_debug_area;
1820         }
1821
1822         rte_intr_callback_register(intr_handle,
1823                                    ena_interrupt_handler_rte,
1824                                    adapter);
1825         rte_intr_enable(intr_handle);
1826         ena_com_set_admin_polling_mode(ena_dev, false);
1827         ena_com_admin_aenq_enable(ena_dev);
1828
1829         if (adapters_found == 0)
1830                 rte_timer_subsystem_init();
1831         rte_timer_init(&adapter->timer_wd);
1832
1833         adapters_found++;
1834         adapter->state = ENA_ADAPTER_STATE_INIT;
1835
1836         return 0;
1837
1838 err_delete_debug_area:
1839         ena_com_delete_debug_area(ena_dev);
1840
1841 err_device_destroy:
1842         ena_com_delete_host_info(ena_dev);
1843         ena_com_admin_destroy(ena_dev);
1844
1845 err:
1846         return rc;
1847 }
1848
1849 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1850 {
1851         struct ena_adapter *adapter = eth_dev->data->dev_private;
1852         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1853
1854         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1855                 return;
1856
1857         ena_com_set_admin_running_state(ena_dev, false);
1858
1859         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1860                 ena_close(eth_dev);
1861
1862         ena_com_delete_debug_area(ena_dev);
1863         ena_com_delete_host_info(ena_dev);
1864
1865         ena_com_abort_admin_commands(ena_dev);
1866         ena_com_wait_for_abort_completion(ena_dev);
1867         ena_com_admin_destroy(ena_dev);
1868         ena_com_mmio_reg_read_request_destroy(ena_dev);
1869
1870         adapter->state = ENA_ADAPTER_STATE_FREE;
1871 }
1872
1873 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1874 {
1875         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1876                 return 0;
1877
1878         ena_destroy_device(eth_dev);
1879
1880         eth_dev->dev_ops = NULL;
1881         eth_dev->rx_pkt_burst = NULL;
1882         eth_dev->tx_pkt_burst = NULL;
1883         eth_dev->tx_pkt_prepare = NULL;
1884
1885         return 0;
1886 }
1887
1888 static int ena_dev_configure(struct rte_eth_dev *dev)
1889 {
1890         struct ena_adapter *adapter = dev->data->dev_private;
1891
1892         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1893
1894         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1895         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1896         return 0;
1897 }
1898
1899 static void ena_init_rings(struct ena_adapter *adapter)
1900 {
1901         int i;
1902
1903         for (i = 0; i < adapter->num_queues; i++) {
1904                 struct ena_ring *ring = &adapter->tx_ring[i];
1905
1906                 ring->configured = 0;
1907                 ring->type = ENA_RING_TYPE_TX;
1908                 ring->adapter = adapter;
1909                 ring->id = i;
1910                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1911                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1912                 ring->sgl_size = adapter->max_tx_sgl_size;
1913         }
1914
1915         for (i = 0; i < adapter->num_queues; i++) {
1916                 struct ena_ring *ring = &adapter->rx_ring[i];
1917
1918                 ring->configured = 0;
1919                 ring->type = ENA_RING_TYPE_RX;
1920                 ring->adapter = adapter;
1921                 ring->id = i;
1922                 ring->sgl_size = adapter->max_rx_sgl_size;
1923         }
1924 }
1925
1926 static void ena_infos_get(struct rte_eth_dev *dev,
1927                           struct rte_eth_dev_info *dev_info)
1928 {
1929         struct ena_adapter *adapter;
1930         struct ena_com_dev *ena_dev;
1931         uint64_t rx_feat = 0, tx_feat = 0;
1932
1933         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1934         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1935         adapter = dev->data->dev_private;
1936
1937         ena_dev = &adapter->ena_dev;
1938         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1939
1940         dev_info->speed_capa =
1941                         ETH_LINK_SPEED_1G   |
1942                         ETH_LINK_SPEED_2_5G |
1943                         ETH_LINK_SPEED_5G   |
1944                         ETH_LINK_SPEED_10G  |
1945                         ETH_LINK_SPEED_25G  |
1946                         ETH_LINK_SPEED_40G  |
1947                         ETH_LINK_SPEED_50G  |
1948                         ETH_LINK_SPEED_100G;
1949
1950         /* Set Tx & Rx features available for device */
1951         if (adapter->offloads.tso4_supported)
1952                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1953
1954         if (adapter->offloads.tx_csum_supported)
1955                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1956                         DEV_TX_OFFLOAD_UDP_CKSUM |
1957                         DEV_TX_OFFLOAD_TCP_CKSUM;
1958
1959         if (adapter->offloads.rx_csum_supported)
1960                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1961                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1962                         DEV_RX_OFFLOAD_TCP_CKSUM;
1963
1964         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1965
1966         /* Inform framework about available features */
1967         dev_info->rx_offload_capa = rx_feat;
1968         dev_info->rx_queue_offload_capa = rx_feat;
1969         dev_info->tx_offload_capa = tx_feat;
1970         dev_info->tx_queue_offload_capa = tx_feat;
1971
1972         dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
1973                                            ETH_RSS_UDP;
1974
1975         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1976         dev_info->max_rx_pktlen  = adapter->max_mtu;
1977         dev_info->max_mac_addrs = 1;
1978
1979         dev_info->max_rx_queues = adapter->num_queues;
1980         dev_info->max_tx_queues = adapter->num_queues;
1981         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1982
1983         adapter->tx_supported_offloads = tx_feat;
1984         adapter->rx_supported_offloads = rx_feat;
1985
1986         dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size;
1987         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1988         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1989                                         adapter->max_rx_sgl_size);
1990         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1991                                         adapter->max_rx_sgl_size);
1992
1993         dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size;
1994         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1995         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1996                                         adapter->max_tx_sgl_size);
1997         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1998                                         adapter->max_tx_sgl_size);
1999 }
2000
2001 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2002                                   uint16_t nb_pkts)
2003 {
2004         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2005         unsigned int ring_size = rx_ring->ring_size;
2006         unsigned int ring_mask = ring_size - 1;
2007         uint16_t next_to_clean = rx_ring->next_to_clean;
2008         uint16_t desc_in_use = 0;
2009         uint16_t req_id;
2010         unsigned int recv_idx = 0;
2011         struct rte_mbuf *mbuf = NULL;
2012         struct rte_mbuf *mbuf_head = NULL;
2013         struct rte_mbuf *mbuf_prev = NULL;
2014         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
2015         unsigned int completed;
2016
2017         struct ena_com_rx_ctx ena_rx_ctx;
2018         int rc = 0;
2019
2020         /* Check adapter state */
2021         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2022                 RTE_LOG(ALERT, PMD,
2023                         "Trying to receive pkts while device is NOT running\n");
2024                 return 0;
2025         }
2026
2027         desc_in_use = rx_ring->next_to_use - next_to_clean;
2028         if (unlikely(nb_pkts > desc_in_use))
2029                 nb_pkts = desc_in_use;
2030
2031         for (completed = 0; completed < nb_pkts; completed++) {
2032                 int segments = 0;
2033
2034                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2035                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2036                 ena_rx_ctx.descs = 0;
2037                 /* receive packet context */
2038                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2039                                     rx_ring->ena_com_io_sq,
2040                                     &ena_rx_ctx);
2041                 if (unlikely(rc)) {
2042                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
2043                         rx_ring->adapter->reset_reason =
2044                                 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2045                         rx_ring->adapter->trigger_reset = true;
2046                         ++rx_ring->rx_stats.bad_desc_num;
2047                         return 0;
2048                 }
2049
2050                 if (unlikely(ena_rx_ctx.descs == 0))
2051                         break;
2052
2053                 while (segments < ena_rx_ctx.descs) {
2054                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
2055                         rc = validate_rx_req_id(rx_ring, req_id);
2056                         if (unlikely(rc)) {
2057                                 if (segments != 0)
2058                                         rte_mbuf_raw_free(mbuf_head);
2059                                 break;
2060                         }
2061
2062                         mbuf = rx_buff_info[req_id];
2063                         rx_buff_info[req_id] = NULL;
2064                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
2065                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2066                         mbuf->refcnt = 1;
2067                         mbuf->next = NULL;
2068                         if (unlikely(segments == 0)) {
2069                                 mbuf->nb_segs = ena_rx_ctx.descs;
2070                                 mbuf->port = rx_ring->port_id;
2071                                 mbuf->pkt_len = 0;
2072                                 mbuf_head = mbuf;
2073                         } else {
2074                                 /* for multi-segment pkts create mbuf chain */
2075                                 mbuf_prev->next = mbuf;
2076                         }
2077                         mbuf_head->pkt_len += mbuf->data_len;
2078
2079                         mbuf_prev = mbuf;
2080                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
2081                                 req_id;
2082                         segments++;
2083                         next_to_clean++;
2084                 }
2085                 if (unlikely(rc))
2086                         break;
2087
2088                 /* fill mbuf attributes if any */
2089                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
2090
2091                 if (unlikely(mbuf_head->ol_flags &
2092                         (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD)))
2093                         ++rx_ring->rx_stats.bad_csum;
2094
2095                 mbuf_head->hash.rss = ena_rx_ctx.hash;
2096
2097                 /* pass to DPDK application head mbuf */
2098                 rx_pkts[recv_idx] = mbuf_head;
2099                 recv_idx++;
2100                 rx_ring->rx_stats.bytes += mbuf_head->pkt_len;
2101         }
2102
2103         rx_ring->rx_stats.cnt += recv_idx;
2104         rx_ring->next_to_clean = next_to_clean;
2105
2106         desc_in_use = desc_in_use - completed + 1;
2107         /* Burst refill to save doorbells, memory barriers, const interval */
2108         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size)) {
2109                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2110                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
2111         }
2112
2113         return recv_idx;
2114 }
2115
2116 static uint16_t
2117 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2118                 uint16_t nb_pkts)
2119 {
2120         int32_t ret;
2121         uint32_t i;
2122         struct rte_mbuf *m;
2123         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2124         struct rte_ipv4_hdr *ip_hdr;
2125         uint64_t ol_flags;
2126         uint16_t frag_field;
2127
2128         for (i = 0; i != nb_pkts; i++) {
2129                 m = tx_pkts[i];
2130                 ol_flags = m->ol_flags;
2131
2132                 if (!(ol_flags & PKT_TX_IPV4))
2133                         continue;
2134
2135                 /* If there was not L2 header length specified, assume it is
2136                  * length of the ethernet header.
2137                  */
2138                 if (unlikely(m->l2_len == 0))
2139                         m->l2_len = sizeof(struct rte_ether_hdr);
2140
2141                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2142                                                  m->l2_len);
2143                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2144
2145                 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2146                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2147
2148                         /* If IPv4 header has DF flag enabled and TSO support is
2149                          * disabled, partial chcecksum should not be calculated.
2150                          */
2151                         if (!tx_ring->adapter->offloads.tso4_supported)
2152                                 continue;
2153                 }
2154
2155                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2156                                 (ol_flags & PKT_TX_L4_MASK) ==
2157                                 PKT_TX_SCTP_CKSUM) {
2158                         rte_errno = ENOTSUP;
2159                         return i;
2160                 }
2161
2162 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2163                 ret = rte_validate_tx_offload(m);
2164                 if (ret != 0) {
2165                         rte_errno = -ret;
2166                         return i;
2167                 }
2168 #endif
2169
2170                 /* In case we are supposed to TSO and have DF not set (DF=0)
2171                  * hardware must be provided with partial checksum, otherwise
2172                  * it will take care of necessary calculations.
2173                  */
2174
2175                 ret = rte_net_intel_cksum_flags_prepare(m,
2176                         ol_flags & ~PKT_TX_TCP_SEG);
2177                 if (ret != 0) {
2178                         rte_errno = -ret;
2179                         return i;
2180                 }
2181         }
2182
2183         return i;
2184 }
2185
2186 static void ena_update_hints(struct ena_adapter *adapter,
2187                              struct ena_admin_ena_hw_hints *hints)
2188 {
2189         if (hints->admin_completion_tx_timeout)
2190                 adapter->ena_dev.admin_queue.completion_timeout =
2191                         hints->admin_completion_tx_timeout * 1000;
2192
2193         if (hints->mmio_read_timeout)
2194                 /* convert to usec */
2195                 adapter->ena_dev.mmio_read.reg_read_to =
2196                         hints->mmio_read_timeout * 1000;
2197
2198         if (hints->driver_watchdog_timeout) {
2199                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2200                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2201                 else
2202                         // Convert msecs to ticks
2203                         adapter->keep_alive_timeout =
2204                                 (hints->driver_watchdog_timeout *
2205                                 rte_get_timer_hz()) / 1000;
2206         }
2207 }
2208
2209 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2210                                         struct rte_mbuf *mbuf)
2211 {
2212         struct ena_com_dev *ena_dev;
2213         int num_segments, header_len, rc;
2214
2215         ena_dev = &tx_ring->adapter->ena_dev;
2216         num_segments = mbuf->nb_segs;
2217         header_len = mbuf->data_len;
2218
2219         if (likely(num_segments < tx_ring->sgl_size))
2220                 return 0;
2221
2222         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2223             (num_segments == tx_ring->sgl_size) &&
2224             (header_len < tx_ring->tx_max_header_size))
2225                 return 0;
2226
2227         ++tx_ring->tx_stats.linearize;
2228         rc = rte_pktmbuf_linearize(mbuf);
2229         if (unlikely(rc)) {
2230                 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
2231                 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2232                 ++tx_ring->tx_stats.linearize_failed;
2233                 return rc;
2234         }
2235
2236         return rc;
2237 }
2238
2239 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2240                                   uint16_t nb_pkts)
2241 {
2242         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2243         uint16_t next_to_use = tx_ring->next_to_use;
2244         uint16_t next_to_clean = tx_ring->next_to_clean;
2245         struct rte_mbuf *mbuf;
2246         uint16_t seg_len;
2247         unsigned int ring_size = tx_ring->ring_size;
2248         unsigned int ring_mask = ring_size - 1;
2249         struct ena_com_tx_ctx ena_tx_ctx;
2250         struct ena_tx_buffer *tx_info;
2251         struct ena_com_buf *ebuf;
2252         uint16_t rc, req_id, total_tx_descs = 0;
2253         uint16_t sent_idx = 0, empty_tx_reqs;
2254         uint16_t push_len = 0;
2255         uint16_t delta = 0;
2256         int nb_hw_desc;
2257         uint32_t total_length;
2258
2259         /* Check adapter state */
2260         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2261                 RTE_LOG(ALERT, PMD,
2262                         "Trying to xmit pkts while device is NOT running\n");
2263                 return 0;
2264         }
2265
2266         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2267         if (nb_pkts > empty_tx_reqs)
2268                 nb_pkts = empty_tx_reqs;
2269
2270         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2271                 mbuf = tx_pkts[sent_idx];
2272                 total_length = 0;
2273
2274                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2275                 if (unlikely(rc))
2276                         break;
2277
2278                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2279                 tx_info = &tx_ring->tx_buffer_info[req_id];
2280                 tx_info->mbuf = mbuf;
2281                 tx_info->num_of_bufs = 0;
2282                 ebuf = tx_info->bufs;
2283
2284                 /* Prepare TX context */
2285                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2286                 memset(&ena_tx_ctx.ena_meta, 0x0,
2287                        sizeof(struct ena_com_tx_meta));
2288                 ena_tx_ctx.ena_bufs = ebuf;
2289                 ena_tx_ctx.req_id = req_id;
2290
2291                 delta = 0;
2292                 seg_len = mbuf->data_len;
2293
2294                 if (tx_ring->tx_mem_queue_type ==
2295                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2296                         push_len = RTE_MIN(mbuf->pkt_len,
2297                                            tx_ring->tx_max_header_size);
2298                         ena_tx_ctx.header_len = push_len;
2299
2300                         if (likely(push_len <= seg_len)) {
2301                                 /* If the push header is in the single segment,
2302                                  * then just point it to the 1st mbuf data.
2303                                  */
2304                                 ena_tx_ctx.push_header =
2305                                         rte_pktmbuf_mtod(mbuf, uint8_t *);
2306                         } else {
2307                                 /* If the push header lays in the several
2308                                  * segments, copy it to the intermediate buffer.
2309                                  */
2310                                 rte_pktmbuf_read(mbuf, 0, push_len,
2311                                         tx_ring->push_buf_intermediate_buf);
2312                                 ena_tx_ctx.push_header =
2313                                         tx_ring->push_buf_intermediate_buf;
2314                                 delta = push_len - seg_len;
2315                         }
2316                 } /* there's no else as we take advantage of memset zeroing */
2317
2318                 /* Set TX offloads flags, if applicable */
2319                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2320
2321                 if (unlikely(mbuf->ol_flags &
2322                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2323                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2324
2325                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2326
2327                 /* Process first segment taking into
2328                  * consideration pushed header
2329                  */
2330                 if (seg_len > push_len) {
2331                         ebuf->paddr = mbuf->buf_iova +
2332                                       mbuf->data_off +
2333                                       push_len;
2334                         ebuf->len = seg_len - push_len;
2335                         ebuf++;
2336                         tx_info->num_of_bufs++;
2337                 }
2338                 total_length += mbuf->data_len;
2339
2340                 while ((mbuf = mbuf->next) != NULL) {
2341                         seg_len = mbuf->data_len;
2342
2343                         /* Skip mbufs if whole data is pushed as a header */
2344                         if (unlikely(delta > seg_len)) {
2345                                 delta -= seg_len;
2346                                 continue;
2347                         }
2348
2349                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2350                         ebuf->len = seg_len - delta;
2351                         total_length += ebuf->len;
2352                         ebuf++;
2353                         tx_info->num_of_bufs++;
2354
2355                         delta = 0;
2356                 }
2357
2358                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2359
2360                 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2361                                                &ena_tx_ctx)) {
2362                         RTE_LOG(DEBUG, PMD, "llq tx max burst size of queue %d"
2363                                 " achieved, writing doorbell to send burst\n",
2364                                 tx_ring->id);
2365                         rte_wmb();
2366                         ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2367                 }
2368
2369                 /* prepare the packet's descriptors to dma engine */
2370                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2371                                         &ena_tx_ctx, &nb_hw_desc);
2372                 if (unlikely(rc)) {
2373                         ++tx_ring->tx_stats.prepare_ctx_err;
2374                         break;
2375                 }
2376                 tx_info->tx_descs = nb_hw_desc;
2377
2378                 next_to_use++;
2379                 tx_ring->tx_stats.cnt += tx_info->num_of_bufs;
2380                 tx_ring->tx_stats.bytes += total_length;
2381         }
2382         tx_ring->tx_stats.available_desc =
2383                 ena_com_free_desc(tx_ring->ena_com_io_sq);
2384
2385         /* If there are ready packets to be xmitted... */
2386         if (sent_idx > 0) {
2387                 /* ...let HW do its best :-) */
2388                 rte_wmb();
2389                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2390                 tx_ring->tx_stats.doorbells++;
2391                 tx_ring->next_to_use = next_to_use;
2392         }
2393
2394         /* Clear complete packets  */
2395         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2396                 rc = validate_tx_req_id(tx_ring, req_id);
2397                 if (rc)
2398                         break;
2399
2400                 /* Get Tx info & store how many descs were processed  */
2401                 tx_info = &tx_ring->tx_buffer_info[req_id];
2402                 total_tx_descs += tx_info->tx_descs;
2403
2404                 /* Free whole mbuf chain  */
2405                 mbuf = tx_info->mbuf;
2406                 rte_pktmbuf_free(mbuf);
2407                 tx_info->mbuf = NULL;
2408
2409                 /* Put back descriptor to the ring for reuse */
2410                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2411                 next_to_clean++;
2412
2413                 /* If too many descs to clean, leave it for another run */
2414                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2415                         break;
2416         }
2417         tx_ring->tx_stats.available_desc =
2418                 ena_com_free_desc(tx_ring->ena_com_io_sq);
2419
2420         if (total_tx_descs > 0) {
2421                 /* acknowledge completion of sent packets */
2422                 tx_ring->next_to_clean = next_to_clean;
2423                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2424                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2425         }
2426
2427         tx_ring->tx_stats.tx_poll++;
2428
2429         return sent_idx;
2430 }
2431
2432 /**
2433  * DPDK callback to retrieve names of extended device statistics
2434  *
2435  * @param dev
2436  *   Pointer to Ethernet device structure.
2437  * @param[out] xstats_names
2438  *   Buffer to insert names into.
2439  * @param n
2440  *   Number of names.
2441  *
2442  * @return
2443  *   Number of xstats names.
2444  */
2445 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2446                                 struct rte_eth_xstat_name *xstats_names,
2447                                 unsigned int n)
2448 {
2449         unsigned int xstats_count = ena_xstats_calc_num(dev);
2450         unsigned int stat, i, count = 0;
2451
2452         if (n < xstats_count || !xstats_names)
2453                 return xstats_count;
2454
2455         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2456                 strcpy(xstats_names[count].name,
2457                         ena_stats_global_strings[stat].name);
2458
2459         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2460                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2461                         snprintf(xstats_names[count].name,
2462                                 sizeof(xstats_names[count].name),
2463                                 "rx_q%d_%s", i,
2464                                 ena_stats_rx_strings[stat].name);
2465
2466         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2467                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2468                         snprintf(xstats_names[count].name,
2469                                 sizeof(xstats_names[count].name),
2470                                 "tx_q%d_%s", i,
2471                                 ena_stats_tx_strings[stat].name);
2472
2473         return xstats_count;
2474 }
2475
2476 /**
2477  * DPDK callback to get extended device statistics.
2478  *
2479  * @param dev
2480  *   Pointer to Ethernet device structure.
2481  * @param[out] stats
2482  *   Stats table output buffer.
2483  * @param n
2484  *   The size of the stats table.
2485  *
2486  * @return
2487  *   Number of xstats on success, negative on failure.
2488  */
2489 static int ena_xstats_get(struct rte_eth_dev *dev,
2490                           struct rte_eth_xstat *xstats,
2491                           unsigned int n)
2492 {
2493         struct ena_adapter *adapter = dev->data->dev_private;
2494         unsigned int xstats_count = ena_xstats_calc_num(dev);
2495         unsigned int stat, i, count = 0;
2496         int stat_offset;
2497         void *stats_begin;
2498
2499         if (n < xstats_count)
2500                 return xstats_count;
2501
2502         if (!xstats)
2503                 return 0;
2504
2505         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2506                 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2507                 stats_begin = &adapter->dev_stats;
2508
2509                 xstats[count].id = count;
2510                 xstats[count].value = *((uint64_t *)
2511                         ((char *)stats_begin + stat_offset));
2512         }
2513
2514         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2515                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2516                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2517                         stats_begin = &adapter->rx_ring[i].rx_stats;
2518
2519                         xstats[count].id = count;
2520                         xstats[count].value = *((uint64_t *)
2521                                 ((char *)stats_begin + stat_offset));
2522                 }
2523         }
2524
2525         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2526                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2527                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2528                         stats_begin = &adapter->tx_ring[i].rx_stats;
2529
2530                         xstats[count].id = count;
2531                         xstats[count].value = *((uint64_t *)
2532                                 ((char *)stats_begin + stat_offset));
2533                 }
2534         }
2535
2536         return count;
2537 }
2538
2539 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2540                                 const uint64_t *ids,
2541                                 uint64_t *values,
2542                                 unsigned int n)
2543 {
2544         struct ena_adapter *adapter = dev->data->dev_private;
2545         uint64_t id;
2546         uint64_t rx_entries, tx_entries;
2547         unsigned int i;
2548         int qid;
2549         int valid = 0;
2550         for (i = 0; i < n; ++i) {
2551                 id = ids[i];
2552                 /* Check if id belongs to global statistics */
2553                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2554                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2555                         ++valid;
2556                         continue;
2557                 }
2558
2559                 /* Check if id belongs to rx queue statistics */
2560                 id -= ENA_STATS_ARRAY_GLOBAL;
2561                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2562                 if (id < rx_entries) {
2563                         qid = id % dev->data->nb_rx_queues;
2564                         id /= dev->data->nb_rx_queues;
2565                         values[i] = *((uint64_t *)
2566                                 &adapter->rx_ring[qid].rx_stats + id);
2567                         ++valid;
2568                         continue;
2569                 }
2570                                 /* Check if id belongs to rx queue statistics */
2571                 id -= rx_entries;
2572                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2573                 if (id < tx_entries) {
2574                         qid = id % dev->data->nb_tx_queues;
2575                         id /= dev->data->nb_tx_queues;
2576                         values[i] = *((uint64_t *)
2577                                 &adapter->tx_ring[qid].tx_stats + id);
2578                         ++valid;
2579                         continue;
2580                 }
2581         }
2582
2583         return valid;
2584 }
2585
2586 /*********************************************************************
2587  *  PMD configuration
2588  *********************************************************************/
2589 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2590         struct rte_pci_device *pci_dev)
2591 {
2592         return rte_eth_dev_pci_generic_probe(pci_dev,
2593                 sizeof(struct ena_adapter), eth_ena_dev_init);
2594 }
2595
2596 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2597 {
2598         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2599 }
2600
2601 static struct rte_pci_driver rte_ena_pmd = {
2602         .id_table = pci_id_ena_map,
2603         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2604                      RTE_PCI_DRV_WC_ACTIVATE,
2605         .probe = eth_ena_pci_probe,
2606         .remove = eth_ena_pci_remove,
2607 };
2608
2609 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2610 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2611 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2612
2613 RTE_INIT(ena_init_log)
2614 {
2615         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2616         if (ena_logtype_init >= 0)
2617                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2618         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2619         if (ena_logtype_driver >= 0)
2620                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2621 }
2622
2623 /******************************************************************************
2624  ******************************** AENQ Handlers *******************************
2625  *****************************************************************************/
2626 static void ena_update_on_link_change(void *adapter_data,
2627                                       struct ena_admin_aenq_entry *aenq_e)
2628 {
2629         struct rte_eth_dev *eth_dev;
2630         struct ena_adapter *adapter;
2631         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2632         uint32_t status;
2633
2634         adapter = adapter_data;
2635         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2636         eth_dev = adapter->rte_dev;
2637
2638         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2639         adapter->link_status = status;
2640
2641         ena_link_update(eth_dev, 0);
2642         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2643 }
2644
2645 static void ena_notification(void *data,
2646                              struct ena_admin_aenq_entry *aenq_e)
2647 {
2648         struct ena_adapter *adapter = data;
2649         struct ena_admin_ena_hw_hints *hints;
2650
2651         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2652                 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2653                         aenq_e->aenq_common_desc.group,
2654                         ENA_ADMIN_NOTIFICATION);
2655
2656         switch (aenq_e->aenq_common_desc.syndrom) {
2657         case ENA_ADMIN_UPDATE_HINTS:
2658                 hints = (struct ena_admin_ena_hw_hints *)
2659                         (&aenq_e->inline_data_w4);
2660                 ena_update_hints(adapter, hints);
2661                 break;
2662         default:
2663                 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2664                         aenq_e->aenq_common_desc.syndrom);
2665         }
2666 }
2667
2668 static void ena_keep_alive(void *adapter_data,
2669                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2670 {
2671         struct ena_adapter *adapter = adapter_data;
2672         struct ena_admin_aenq_keep_alive_desc *desc;
2673         uint64_t rx_drops;
2674
2675         adapter->timestamp_wd = rte_get_timer_cycles();
2676
2677         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2678         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2679         rte_atomic64_set(&adapter->drv_stats->rx_drops, rx_drops);
2680 }
2681
2682 /**
2683  * This handler will called for unknown event group or unimplemented handlers
2684  **/
2685 static void unimplemented_aenq_handler(__rte_unused void *data,
2686                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2687 {
2688         RTE_LOG(ERR, PMD, "Unknown event was received or event with "
2689                           "unimplemented handler\n");
2690 }
2691
2692 static struct ena_aenq_handlers aenq_handlers = {
2693         .handlers = {
2694                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2695                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2696                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2697         },
2698         .unimplemented_handler = unimplemented_aenq_handler
2699 };