drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 0
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 enum ethtool_stringset {
  89         ETH_SS_TEST             = 0,
  90         ETH_SS_STATS,
  91 };
  92
  93 struct ena_stats {
  94         char name[ETH_GSTRING_LEN];
  95         int stat_offset;
  96 };
  97
  98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
  99         .name = #stat, \
 100         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 101 }
 102
 103 #define ENA_STAT_ENTRY(stat, stat_type) { \
 104         .name = #stat, \
 105         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 106 }
 107
 108 #define ENA_STAT_RX_ENTRY(stat) \
 109         ENA_STAT_ENTRY(stat, rx)
 110
 111 #define ENA_STAT_TX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, tx)
 113
 114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, dev)
 116
 117 /*
 118  * Each rte_memzone should have unique name.
 119  * To satisfy it, count number of allocation and add it to name.
 120  */
 121 uint32_t ena_alloc_cnt;
 122
 123 static const struct ena_stats ena_stats_global_strings[] = {
 124         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 125         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 126         ENA_STAT_GLOBAL_ENTRY(io_resume),
 127         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 128         ENA_STAT_GLOBAL_ENTRY(interface_up),
 129         ENA_STAT_GLOBAL_ENTRY(interface_down),
 130         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 131 };
 132
 133 static const struct ena_stats ena_stats_tx_strings[] = {
 134         ENA_STAT_TX_ENTRY(cnt),
 135         ENA_STAT_TX_ENTRY(bytes),
 136         ENA_STAT_TX_ENTRY(queue_stop),
 137         ENA_STAT_TX_ENTRY(queue_wakeup),
 138         ENA_STAT_TX_ENTRY(dma_mapping_err),
 139         ENA_STAT_TX_ENTRY(linearize),
 140         ENA_STAT_TX_ENTRY(linearize_failed),
 141         ENA_STAT_TX_ENTRY(tx_poll),
 142         ENA_STAT_TX_ENTRY(doorbells),
 143         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 144         ENA_STAT_TX_ENTRY(missing_tx_comp),
 145         ENA_STAT_TX_ENTRY(bad_req_id),
 146 };
 147
 148 static const struct ena_stats ena_stats_rx_strings[] = {
 149         ENA_STAT_RX_ENTRY(cnt),
 150         ENA_STAT_RX_ENTRY(bytes),
 151         ENA_STAT_RX_ENTRY(refil_partial),
 152         ENA_STAT_RX_ENTRY(bad_csum),
 153         ENA_STAT_RX_ENTRY(page_alloc_fail),
 154         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 155         ENA_STAT_RX_ENTRY(dma_mapping_err),
 156         ENA_STAT_RX_ENTRY(bad_desc_num),
 157         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 158 };
 159
 160 static const struct ena_stats ena_stats_ena_com_strings[] = {
 161         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 162         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 163         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 164         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 165         ENA_STAT_ENA_COM_ENTRY(no_completion),
 166 };
 167
 168 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 169 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 170 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 171 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 172
 173 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 174                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 175                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 176                         DEV_TX_OFFLOAD_TCP_TSO)
 177 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 178                        PKT_TX_IP_CKSUM |\
 179                        PKT_TX_TCP_SEG)
 180
 181 /** Vendor ID used by Amazon devices */
 182 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 183 /** Amazon devices */
 184 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 185 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 186
 187 #define ENA_TX_OFFLOAD_MASK     (\
 188         PKT_TX_L4_MASK |         \
 189         PKT_TX_IP_CKSUM |        \
 190         PKT_TX_TCP_SEG)
 191
 192 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 193         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 194
 195 int ena_logtype_init;
 196 int ena_logtype_driver;
 197
 198 static const struct rte_pci_id pci_id_ena_map[] = {
 199         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 200         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 201         { .device_id = 0 },
 202 };
 203
 204 static struct ena_aenq_handlers aenq_handlers;
 205
 206 static int ena_device_init(struct ena_com_dev *ena_dev,
 207                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 208 static int ena_dev_configure(struct rte_eth_dev *dev);
 209 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 210                                   uint16_t nb_pkts);
 211 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 212                 uint16_t nb_pkts);
 213 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 214                               uint16_t nb_desc, unsigned int socket_id,
 215                               const struct rte_eth_txconf *tx_conf);
 216 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 217                               uint16_t nb_desc, unsigned int socket_id,
 218                               const struct rte_eth_rxconf *rx_conf,
 219                               struct rte_mempool *mp);
 220 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 221                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 222 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 223 static void ena_init_rings(struct ena_adapter *adapter);
 224 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 225 static int ena_start(struct rte_eth_dev *dev);
 226 static void ena_stop(struct rte_eth_dev *dev);
 227 static void ena_close(struct rte_eth_dev *dev);
 228 static int ena_dev_reset(struct rte_eth_dev *dev);
 229 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 230 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 231 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 232 static void ena_rx_queue_release(void *queue);
 233 static void ena_tx_queue_release(void *queue);
 234 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 235 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 236 static int ena_link_update(struct rte_eth_dev *dev,
 237                            int wait_to_complete);
 238 static int ena_queue_restart(struct ena_ring *ring);
 239 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 240                                  enum ena_ring_type ring_type);
 241 static void ena_stats_restart(struct rte_eth_dev *dev);
 242 static void ena_infos_get(struct rte_eth_dev *dev,
 243                           struct rte_eth_dev_info *dev_info);
 244 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 245                                struct rte_eth_rss_reta_entry64 *reta_conf,
 246                                uint16_t reta_size);
 247 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 248                               struct rte_eth_rss_reta_entry64 *reta_conf,
 249                               uint16_t reta_size);
 250 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 251 static void ena_interrupt_handler_rte(void *cb_arg);
 252 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 253
 254 static const struct eth_dev_ops ena_dev_ops = {
 255         .dev_configure        = ena_dev_configure,
 256         .dev_infos_get        = ena_infos_get,
 257         .rx_queue_setup       = ena_rx_queue_setup,
 258         .tx_queue_setup       = ena_tx_queue_setup,
 259         .dev_start            = ena_start,
 260         .dev_stop             = ena_stop,
 261         .link_update          = ena_link_update,
 262         .stats_get            = ena_stats_get,
 263         .mtu_set              = ena_mtu_set,
 264         .rx_queue_release     = ena_rx_queue_release,
 265         .tx_queue_release     = ena_tx_queue_release,
 266         .dev_close            = ena_close,
 267         .dev_reset            = ena_dev_reset,
 268         .reta_update          = ena_rss_reta_update,
 269         .reta_query           = ena_rss_reta_query,
 270 };
 271
 272 #define NUMA_NO_NODE    SOCKET_ID_ANY
 273
 274 static inline int ena_cpu_to_node(int cpu)
 275 {
 276         struct rte_config *config = rte_eal_get_configuration();
 277         struct rte_fbarray *arr = &config->mem_config->memzones;
 278         const struct rte_memzone *mz;
 279
 280         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 281                 return NUMA_NO_NODE;
 282
 283         mz = rte_fbarray_get(arr, cpu);
 284
 285         return mz->socket_id;
 286 }
 287
 288 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 289                                        struct ena_com_rx_ctx *ena_rx_ctx)
 290 {
 291         uint64_t ol_flags = 0;
 292         uint32_t packet_type = 0;
 293
 294         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 295                 packet_type |= RTE_PTYPE_L4_TCP;
 296         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 297                 packet_type |= RTE_PTYPE_L4_UDP;
 298
 299         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 300                 packet_type |= RTE_PTYPE_L3_IPV4;
 301         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 302                 packet_type |= RTE_PTYPE_L3_IPV6;
 303
 304         if (unlikely(ena_rx_ctx->l4_csum_err))
 305                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 306         if (unlikely(ena_rx_ctx->l3_csum_err))
 307                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 308
 309         mbuf->ol_flags = ol_flags;
 310         mbuf->packet_type = packet_type;
 311 }
 312
 313 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 314                                        struct ena_com_tx_ctx *ena_tx_ctx,
 315                                        uint64_t queue_offloads)
 316 {
 317         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 318
 319         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 320             (queue_offloads & QUEUE_OFFLOADS)) {
 321                 /* check if TSO is required */
 322                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 323                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 324                         ena_tx_ctx->tso_enable = true;
 325
 326                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 327                 }
 328
 329                 /* check if L3 checksum is needed */
 330                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 331                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 332                         ena_tx_ctx->l3_csum_enable = true;
 333
 334                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 335                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 336                 } else {
 337                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 338
 339                         /* set don't fragment (DF) flag */
 340                         if (mbuf->packet_type &
 341                                 (RTE_PTYPE_L4_NONFRAG
 342                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 343                                 ena_tx_ctx->df = true;
 344                 }
 345
 346                 /* check if L4 checksum is needed */
 347                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 348                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 349                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 350                         ena_tx_ctx->l4_csum_enable = true;
 351                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 352                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 353                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 354                         ena_tx_ctx->l4_csum_enable = true;
 355                 } else {
 356                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 357                         ena_tx_ctx->l4_csum_enable = false;
 358                 }
 359
 360                 ena_meta->mss = mbuf->tso_segsz;
 361                 ena_meta->l3_hdr_len = mbuf->l3_len;
 362                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 363
 364                 ena_tx_ctx->meta_valid = true;
 365         } else {
 366                 ena_tx_ctx->meta_valid = false;
 367         }
 368 }
 369
 370 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 371 {
 372         struct ena_admin_host_info *host_info;
 373         int rc;
 374
 375         /* Allocate only the host info */
 376         rc = ena_com_allocate_host_info(ena_dev);
 377         if (rc) {
 378                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 379                 return;
 380         }
 381
 382         host_info = ena_dev->host_attr.host_info;
 383
 384         host_info->os_type = ENA_ADMIN_OS_DPDK;
 385         host_info->kernel_ver = RTE_VERSION;
 386         snprintf((char *)host_info->kernel_ver_str,
 387                  sizeof(host_info->kernel_ver_str),
 388                  "%s", rte_version());
 389         host_info->os_dist = RTE_VERSION;
 390         snprintf((char *)host_info->os_dist_str,
 391                  sizeof(host_info->os_dist_str),
 392                  "%s", rte_version());
 393         host_info->driver_version =
 394                 (DRV_MODULE_VER_MAJOR) |
 395                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 396                 (DRV_MODULE_VER_SUBMINOR <<
 397                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 398
 399         rc = ena_com_set_host_attributes(ena_dev);
 400         if (rc) {
 401                 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 402                 if (rc != -ENA_COM_UNSUPPORTED)
 403                         goto err;
 404         }
 405
 406         return;
 407
 408 err:
 409         ena_com_delete_host_info(ena_dev);
 410 }
 411
 412 static int
 413 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 414 {
 415         if (sset != ETH_SS_STATS)
 416                 return -EOPNOTSUPP;
 417
 418          /* Workaround for clang:
 419          * touch internal structures to prevent
 420          * compiler error
 421          */
 422         ENA_TOUCH(ena_stats_global_strings);
 423         ENA_TOUCH(ena_stats_tx_strings);
 424         ENA_TOUCH(ena_stats_rx_strings);
 425         ENA_TOUCH(ena_stats_ena_com_strings);
 426
 427         return  dev->data->nb_tx_queues *
 428                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 429                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 430 }
 431
 432 static void ena_config_debug_area(struct ena_adapter *adapter)
 433 {
 434         u32 debug_area_size;
 435         int rc, ss_count;
 436
 437         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 438         if (ss_count <= 0) {
 439                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 440                 return;
 441         }
 442
 443         /* allocate 32 bytes for each string and 64bit for the value */
 444         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 445
 446         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 447         if (rc) {
 448                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 449                 return;
 450         }
 451
 452         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 453         if (rc) {
 454                 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 455                 if (rc != -ENA_COM_UNSUPPORTED)
 456                         goto err;
 457         }
 458
 459         return;
 460 err:
 461         ena_com_delete_debug_area(&adapter->ena_dev);
 462 }
 463
 464 static void ena_close(struct rte_eth_dev *dev)
 465 {
 466         struct ena_adapter *adapter =
 467                 (struct ena_adapter *)(dev->data->dev_private);
 468
 469         ena_stop(dev);
 470         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 471
 472         ena_rx_queue_release_all(dev);
 473         ena_tx_queue_release_all(dev);
 474 }
 475
 476 static int
 477 ena_dev_reset(struct rte_eth_dev *dev)
 478 {
 479         struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
 480         struct rte_eth_dev *eth_dev;
 481         struct rte_pci_device *pci_dev;
 482         struct rte_intr_handle *intr_handle;
 483         struct ena_com_dev *ena_dev;
 484         struct ena_com_dev_get_features_ctx get_feat_ctx;
 485         struct ena_adapter *adapter;
 486         int nb_queues;
 487         int rc, i;
 488
 489         adapter = (struct ena_adapter *)(dev->data->dev_private);
 490         ena_dev = &adapter->ena_dev;
 491         eth_dev = adapter->rte_dev;
 492         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 493         intr_handle = &pci_dev->intr_handle;
 494         nb_queues = eth_dev->data->nb_rx_queues;
 495
 496         ena_com_set_admin_running_state(ena_dev, false);
 497
 498         ena_com_dev_reset(ena_dev, adapter->reset_reason);
 499
 500         for (i = 0; i < nb_queues; i++)
 501                 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
 502
 503         ena_rx_queue_release_all(eth_dev);
 504         ena_tx_queue_release_all(eth_dev);
 505
 506         rte_intr_disable(intr_handle);
 507
 508         ena_com_abort_admin_commands(ena_dev);
 509         ena_com_wait_for_abort_completion(ena_dev);
 510         ena_com_admin_destroy(ena_dev);
 511         ena_com_mmio_reg_read_request_destroy(ena_dev);
 512
 513         rc = ena_device_init(ena_dev, &get_feat_ctx);
 514         if (rc) {
 515                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 516                 return rc;
 517         }
 518
 519         rte_intr_enable(intr_handle);
 520         ena_com_set_admin_polling_mode(ena_dev, false);
 521         ena_com_admin_aenq_enable(ena_dev);
 522
 523         for (i = 0; i < nb_queues; ++i)
 524                 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring_size, 0, NULL,
 525                         mb_pool_rx[i]);
 526
 527         for (i = 0; i < nb_queues; ++i)
 528                 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring_size, 0, NULL);
 529
 530         adapter->trigger_reset = false;
 531
 532         return 0;
 533 }
 534
 535 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 536                                struct rte_eth_rss_reta_entry64 *reta_conf,
 537                                uint16_t reta_size)
 538 {
 539         struct ena_adapter *adapter =
 540                 (struct ena_adapter *)(dev->data->dev_private);
 541         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 542         int ret, i;
 543         u16 entry_value;
 544         int conf_idx;
 545         int idx;
 546
 547         if ((reta_size == 0) || (reta_conf == NULL))
 548                 return -EINVAL;
 549
 550         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 551                 RTE_LOG(WARNING, PMD,
 552                         "indirection table %d is bigger than supported (%d)\n",
 553                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 554                 ret = -EINVAL;
 555                 goto err;
 556         }
 557
 558         for (i = 0 ; i < reta_size ; i++) {
 559                 /* each reta_conf is for 64 entries.
 560                  * to support 128 we use 2 conf of 64
 561                  */
 562                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 563                 idx = i % RTE_RETA_GROUP_SIZE;
 564                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 565                         entry_value =
 566                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 567                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 568                                                                 i,
 569                                                                 entry_value);
 570                         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 571                                 RTE_LOG(ERR, PMD,
 572                                         "Cannot fill indirect table\n");
 573                                 ret = -ENOTSUP;
 574                                 goto err;
 575                         }
 576                 }
 577         }
 578
 579         ret = ena_com_indirect_table_set(ena_dev);
 580         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 581                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 582                 ret = -ENOTSUP;
 583                 goto err;
 584         }
 585
 586         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 587                 __func__, reta_size, adapter->rte_dev->data->port_id);
 588 err:
 589         return ret;
 590 }
 591
 592 /* Query redirection table. */
 593 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 594                               struct rte_eth_rss_reta_entry64 *reta_conf,
 595                               uint16_t reta_size)
 596 {
 597         struct ena_adapter *adapter =
 598                 (struct ena_adapter *)(dev->data->dev_private);
 599         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 600         int ret;
 601         int i;
 602         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 603         int reta_conf_idx;
 604         int reta_idx;
 605
 606         if (reta_size == 0 || reta_conf == NULL ||
 607             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 608                 return -EINVAL;
 609
 610         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 611         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 612                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 613                 ret = -ENOTSUP;
 614                 goto err;
 615         }
 616
 617         for (i = 0 ; i < reta_size ; i++) {
 618                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 619                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 620                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 621                         reta_conf[reta_conf_idx].reta[reta_idx] =
 622                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 623         }
 624 err:
 625         return ret;
 626 }
 627
 628 static int ena_rss_init_default(struct ena_adapter *adapter)
 629 {
 630         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 631         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 632         int rc, i;
 633         u32 val;
 634
 635         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 636         if (unlikely(rc)) {
 637                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 638                 goto err_rss_init;
 639         }
 640
 641         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 642                 val = i % nb_rx_queues;
 643                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 644                                                        ENA_IO_RXQ_IDX(val));
 645                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 646                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 647                         goto err_fill_indir;
 648                 }
 649         }
 650
 651         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 652                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 653         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 654                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 655                 goto err_fill_indir;
 656         }
 657
 658         rc = ena_com_set_default_hash_ctrl(ena_dev);
 659         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 660                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 661                 goto err_fill_indir;
 662         }
 663
 664         rc = ena_com_indirect_table_set(ena_dev);
 665         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 666                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 667                 goto err_fill_indir;
 668         }
 669         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 670                 adapter->rte_dev->data->port_id);
 671
 672         return 0;
 673
 674 err_fill_indir:
 675         ena_com_rss_destroy(ena_dev);
 676 err_rss_init:
 677
 678         return rc;
 679 }
 680
 681 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 682 {
 683         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 684         int nb_queues = dev->data->nb_rx_queues;
 685         int i;
 686
 687         for (i = 0; i < nb_queues; i++)
 688                 ena_rx_queue_release(queues[i]);
 689 }
 690
 691 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 692 {
 693         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 694         int nb_queues = dev->data->nb_tx_queues;
 695         int i;
 696
 697         for (i = 0; i < nb_queues; i++)
 698                 ena_tx_queue_release(queues[i]);
 699 }
 700
 701 static void ena_rx_queue_release(void *queue)
 702 {
 703         struct ena_ring *ring = (struct ena_ring *)queue;
 704         struct ena_adapter *adapter = ring->adapter;
 705         int ena_qid;
 706
 707         ena_assert_msg(ring->configured,
 708                        "API violation - releasing not configured queue");
 709         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 710                        "API violation");
 711
 712         /* Destroy HW queue */
 713         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 714         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 715
 716         /* Free all bufs */
 717         ena_rx_queue_release_bufs(ring);
 718
 719         /* Free ring resources */
 720         if (ring->rx_buffer_info)
 721                 rte_free(ring->rx_buffer_info);
 722         ring->rx_buffer_info = NULL;
 723
 724         ring->configured = 0;
 725
 726         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 727                 ring->port_id, ring->id);
 728 }
 729
 730 static void ena_tx_queue_release(void *queue)
 731 {
 732         struct ena_ring *ring = (struct ena_ring *)queue;
 733         struct ena_adapter *adapter = ring->adapter;
 734         int ena_qid;
 735
 736         ena_assert_msg(ring->configured,
 737                        "API violation. Releasing not configured queue");
 738         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 739                        "API violation");
 740
 741         /* Destroy HW queue */
 742         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 743         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 744
 745         /* Free all bufs */
 746         ena_tx_queue_release_bufs(ring);
 747
 748         /* Free ring resources */
 749         if (ring->tx_buffer_info)
 750                 rte_free(ring->tx_buffer_info);
 751
 752         if (ring->empty_tx_reqs)
 753                 rte_free(ring->empty_tx_reqs);
 754
 755         ring->empty_tx_reqs = NULL;
 756         ring->tx_buffer_info = NULL;
 757
 758         ring->configured = 0;
 759
 760         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 761                 ring->port_id, ring->id);
 762 }
 763
 764 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 765 {
 766         unsigned int ring_mask = ring->ring_size - 1;
 767
 768         while (ring->next_to_clean != ring->next_to_use) {
 769                 struct rte_mbuf *m =
 770                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 771
 772                 if (m)
 773                         rte_mbuf_raw_free(m);
 774
 775                 ring->next_to_clean++;
 776         }
 777 }
 778
 779 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 780 {
 781         unsigned int i;
 782
 783         for (i = 0; i < ring->ring_size; ++i) {
 784                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 785
 786                 if (tx_buf->mbuf)
 787                         rte_pktmbuf_free(tx_buf->mbuf);
 788
 789                 ring->next_to_clean++;
 790         }
 791 }
 792
 793 static int ena_link_update(struct rte_eth_dev *dev,
 794                            __rte_unused int wait_to_complete)
 795 {
 796         struct rte_eth_link *link = &dev->data->dev_link;
 797         struct ena_adapter *adapter;
 798
 799         adapter = (struct ena_adapter *)(dev->data->dev_private);
 800
 801         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 802         link->link_speed = ETH_SPEED_NUM_10G;
 803         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 804
 805         return 0;
 806 }
 807
 808 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 809                                  enum ena_ring_type ring_type)
 810 {
 811         struct ena_adapter *adapter =
 812                 (struct ena_adapter *)(dev->data->dev_private);
 813         struct ena_ring *queues = NULL;
 814         int nb_queues;
 815         int i = 0;
 816         int rc = 0;
 817
 818         if (ring_type == ENA_RING_TYPE_RX) {
 819                 queues = adapter->rx_ring;
 820                 nb_queues = dev->data->nb_rx_queues;
 821         } else {
 822                 queues = adapter->tx_ring;
 823                 nb_queues = dev->data->nb_tx_queues;
 824         }
 825         for (i = 0; i < nb_queues; i++) {
 826                 if (queues[i].configured) {
 827                         if (ring_type == ENA_RING_TYPE_RX) {
 828                                 ena_assert_msg(
 829                                         dev->data->rx_queues[i] == &queues[i],
 830                                         "Inconsistent state of rx queues\n");
 831                         } else {
 832                                 ena_assert_msg(
 833                                         dev->data->tx_queues[i] == &queues[i],
 834                                         "Inconsistent state of tx queues\n");
 835                         }
 836
 837                         rc = ena_queue_restart(&queues[i]);
 838
 839                         if (rc) {
 840                                 PMD_INIT_LOG(ERR,
 841                                              "failed to restart queue %d type(%d)",
 842                                              i, ring_type);
 843                                 return -1;
 844                         }
 845                 }
 846         }
 847
 848         return 0;
 849 }
 850
 851 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 852 {
 853         uint32_t max_frame_len = adapter->max_mtu;
 854
 855         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 856             DEV_RX_OFFLOAD_JUMBO_FRAME)
 857                 max_frame_len =
 858                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 859
 860         return max_frame_len;
 861 }
 862
 863 static int ena_check_valid_conf(struct ena_adapter *adapter)
 864 {
 865         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 866
 867         if (max_frame_len > adapter->max_mtu) {
 868                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
 869                 return -1;
 870         }
 871
 872         return 0;
 873 }
 874
 875 static int
 876 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 877                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 878 {
 879         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 880
 881         queue_size = RTE_MIN(queue_size,
 882                              get_feat_ctx->max_queues.max_cq_depth);
 883         queue_size = RTE_MIN(queue_size,
 884                              get_feat_ctx->max_queues.max_sq_depth);
 885
 886         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 887                 queue_size = RTE_MIN(queue_size,
 888                                      get_feat_ctx->max_queues.max_llq_depth);
 889
 890         /* Round down to power of 2 */
 891         if (!rte_is_power_of_2(queue_size))
 892                 queue_size = rte_align32pow2(queue_size >> 1);
 893
 894         if (queue_size == 0) {
 895                 PMD_INIT_LOG(ERR, "Invalid queue size");
 896                 return -EFAULT;
 897         }
 898
 899         return queue_size;
 900 }
 901
 902 static void ena_stats_restart(struct rte_eth_dev *dev)
 903 {
 904         struct ena_adapter *adapter =
 905                 (struct ena_adapter *)(dev->data->dev_private);
 906
 907         rte_atomic64_init(&adapter->drv_stats->ierrors);
 908         rte_atomic64_init(&adapter->drv_stats->oerrors);
 909         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 910 }
 911
 912 static int ena_stats_get(struct rte_eth_dev *dev,
 913                           struct rte_eth_stats *stats)
 914 {
 915         struct ena_admin_basic_stats ena_stats;
 916         struct ena_adapter *adapter =
 917                 (struct ena_adapter *)(dev->data->dev_private);
 918         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 919         int rc;
 920
 921         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 922                 return -ENOTSUP;
 923
 924         memset(&ena_stats, 0, sizeof(ena_stats));
 925         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 926         if (unlikely(rc)) {
 927                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 928                 return rc;
 929         }
 930
 931         /* Set of basic statistics from ENA */
 932         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 933                                           ena_stats.rx_pkts_low);
 934         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 935                                           ena_stats.tx_pkts_low);
 936         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 937                                         ena_stats.rx_bytes_low);
 938         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 939                                         ena_stats.tx_bytes_low);
 940         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 941                                          ena_stats.rx_drops_low);
 942
 943         /* Driver related stats */
 944         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 945         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 946         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 947         return 0;
 948 }
 949
 950 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 951 {
 952         struct ena_adapter *adapter;
 953         struct ena_com_dev *ena_dev;
 954         int rc = 0;
 955
 956         ena_assert_msg(dev->data != NULL, "Uninitialized device");
 957         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
 958         adapter = (struct ena_adapter *)(dev->data->dev_private);
 959
 960         ena_dev = &adapter->ena_dev;
 961         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
 962
 963         if (mtu > ena_get_mtu_conf(adapter)) {
 964                 RTE_LOG(ERR, PMD,
 965                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
 966                         mtu, ena_get_mtu_conf(adapter));
 967                 rc = -EINVAL;
 968                 goto err;
 969         }
 970
 971         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 972         if (rc)
 973                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
 974         else
 975                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
 976
 977 err:
 978         return rc;
 979 }
 980
 981 static int ena_start(struct rte_eth_dev *dev)
 982 {
 983         struct ena_adapter *adapter =
 984                 (struct ena_adapter *)(dev->data->dev_private);
 985         uint64_t ticks;
 986         int rc = 0;
 987
 988         rc = ena_check_valid_conf(adapter);
 989         if (rc)
 990                 return rc;
 991
 992         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
 993         if (rc)
 994                 return rc;
 995
 996         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
 997         if (rc)
 998                 return rc;
 999
1000         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1001             ETH_MQ_RX_RSS_FLAG) {
1002                 rc = ena_rss_init_default(adapter);
1003                 if (rc)
1004                         return rc;
1005         }
1006
1007         ena_stats_restart(dev);
1008
1009         adapter->timestamp_wd = rte_get_timer_cycles();
1010         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1011
1012         ticks = rte_get_timer_hz();
1013         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1014                         ena_timer_wd_callback, adapter);
1015
1016         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1017
1018         return 0;
1019 }
1020
1021 static void ena_stop(struct rte_eth_dev *dev)
1022 {
1023         struct ena_adapter *adapter =
1024                 (struct ena_adapter *)(dev->data->dev_private);
1025
1026         rte_timer_stop_sync(&adapter->timer_wd);
1027
1028         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1029 }
1030
1031 static int ena_queue_restart(struct ena_ring *ring)
1032 {
1033         int rc, bufs_num;
1034
1035         ena_assert_msg(ring->configured == 1,
1036                        "Trying to restart unconfigured queue\n");
1037
1038         ring->next_to_clean = 0;
1039         ring->next_to_use = 0;
1040
1041         if (ring->type == ENA_RING_TYPE_TX)
1042                 return 0;
1043
1044         bufs_num = ring->ring_size - 1;
1045         rc = ena_populate_rx_queue(ring, bufs_num);
1046         if (rc != bufs_num) {
1047                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1048                 return (-1);
1049         }
1050
1051         return 0;
1052 }
1053
1054 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1055                               uint16_t queue_idx,
1056                               uint16_t nb_desc,
1057                               __rte_unused unsigned int socket_id,
1058                               const struct rte_eth_txconf *tx_conf)
1059 {
1060         struct ena_com_create_io_ctx ctx =
1061                 /* policy set to _HOST just to satisfy icc compiler */
1062                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1063                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
1064         struct ena_ring *txq = NULL;
1065         struct ena_adapter *adapter =
1066                 (struct ena_adapter *)(dev->data->dev_private);
1067         unsigned int i;
1068         int ena_qid;
1069         int rc;
1070         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1071
1072         txq = &adapter->tx_ring[queue_idx];
1073
1074         if (txq->configured) {
1075                 RTE_LOG(CRIT, PMD,
1076                         "API violation. Queue %d is already configured\n",
1077                         queue_idx);
1078                 return -1;
1079         }
1080
1081         if (!rte_is_power_of_2(nb_desc)) {
1082                 RTE_LOG(ERR, PMD,
1083                         "Unsupported size of RX queue: %d is not a power of 2.",
1084                         nb_desc);
1085                 return -EINVAL;
1086         }
1087
1088         if (nb_desc > adapter->tx_ring_size) {
1089                 RTE_LOG(ERR, PMD,
1090                         "Unsupported size of TX queue (max size: %d)\n",
1091                         adapter->tx_ring_size);
1092                 return -EINVAL;
1093         }
1094
1095         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1096
1097         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1098         ctx.qid = ena_qid;
1099         ctx.msix_vector = -1; /* admin interrupts not used */
1100         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1101         ctx.queue_size = adapter->tx_ring_size;
1102         ctx.numa_node = ena_cpu_to_node(queue_idx);
1103
1104         rc = ena_com_create_io_queue(ena_dev, &ctx);
1105         if (rc) {
1106                 RTE_LOG(ERR, PMD,
1107                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1108                         queue_idx, ena_qid, rc);
1109         }
1110         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1111         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1112
1113         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1114                                      &txq->ena_com_io_sq,
1115                                      &txq->ena_com_io_cq);
1116         if (rc) {
1117                 RTE_LOG(ERR, PMD,
1118                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1119                         queue_idx, rc);
1120                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1121                 goto err;
1122         }
1123
1124         txq->port_id = dev->data->port_id;
1125         txq->next_to_clean = 0;
1126         txq->next_to_use = 0;
1127         txq->ring_size = nb_desc;
1128
1129         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1130                                           sizeof(struct ena_tx_buffer) *
1131                                           txq->ring_size,
1132                                           RTE_CACHE_LINE_SIZE);
1133         if (!txq->tx_buffer_info) {
1134                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1135                 return -ENOMEM;
1136         }
1137
1138         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1139                                          sizeof(u16) * txq->ring_size,
1140                                          RTE_CACHE_LINE_SIZE);
1141         if (!txq->empty_tx_reqs) {
1142                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1143                 rte_free(txq->tx_buffer_info);
1144                 return -ENOMEM;
1145         }
1146         for (i = 0; i < txq->ring_size; i++)
1147                 txq->empty_tx_reqs[i] = i;
1148
1149         if (tx_conf != NULL) {
1150                 txq->offloads =
1151                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1152         }
1153
1154         /* Store pointer to this queue in upper layer */
1155         txq->configured = 1;
1156         dev->data->tx_queues[queue_idx] = txq;
1157 err:
1158         return rc;
1159 }
1160
1161 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1162                               uint16_t queue_idx,
1163                               uint16_t nb_desc,
1164                               __rte_unused unsigned int socket_id,
1165                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1166                               struct rte_mempool *mp)
1167 {
1168         struct ena_com_create_io_ctx ctx =
1169                 /* policy set to _HOST just to satisfy icc compiler */
1170                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1171                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1172         struct ena_adapter *adapter =
1173                 (struct ena_adapter *)(dev->data->dev_private);
1174         struct ena_ring *rxq = NULL;
1175         uint16_t ena_qid = 0;
1176         int rc = 0;
1177         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1178
1179         rxq = &adapter->rx_ring[queue_idx];
1180         if (rxq->configured) {
1181                 RTE_LOG(CRIT, PMD,
1182                         "API violation. Queue %d is already configured\n",
1183                         queue_idx);
1184                 return -1;
1185         }
1186
1187         if (!rte_is_power_of_2(nb_desc)) {
1188                 RTE_LOG(ERR, PMD,
1189                         "Unsupported size of TX queue: %d is not a power of 2.",
1190                         nb_desc);
1191                 return -EINVAL;
1192         }
1193
1194         if (nb_desc > adapter->rx_ring_size) {
1195                 RTE_LOG(ERR, PMD,
1196                         "Unsupported size of RX queue (max size: %d)\n",
1197                         adapter->rx_ring_size);
1198                 return -EINVAL;
1199         }
1200
1201         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1202
1203         ctx.qid = ena_qid;
1204         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1205         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1206         ctx.msix_vector = -1; /* admin interrupts not used */
1207         ctx.queue_size = adapter->rx_ring_size;
1208         ctx.numa_node = ena_cpu_to_node(queue_idx);
1209
1210         rc = ena_com_create_io_queue(ena_dev, &ctx);
1211         if (rc)
1212                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1213                         queue_idx, rc);
1214
1215         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1216         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1217
1218         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1219                                      &rxq->ena_com_io_sq,
1220                                      &rxq->ena_com_io_cq);
1221         if (rc) {
1222                 RTE_LOG(ERR, PMD,
1223                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1224                         queue_idx, rc);
1225                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1226         }
1227
1228         rxq->port_id = dev->data->port_id;
1229         rxq->next_to_clean = 0;
1230         rxq->next_to_use = 0;
1231         rxq->ring_size = nb_desc;
1232         rxq->mb_pool = mp;
1233
1234         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1235                                           sizeof(struct rte_mbuf *) * nb_desc,
1236                                           RTE_CACHE_LINE_SIZE);
1237         if (!rxq->rx_buffer_info) {
1238                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1239                 return -ENOMEM;
1240         }
1241
1242         /* Store pointer to this queue in upper layer */
1243         rxq->configured = 1;
1244         dev->data->rx_queues[queue_idx] = rxq;
1245
1246         return rc;
1247 }
1248
1249 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1250 {
1251         unsigned int i;
1252         int rc;
1253         uint16_t ring_size = rxq->ring_size;
1254         uint16_t ring_mask = ring_size - 1;
1255         uint16_t next_to_use = rxq->next_to_use;
1256         uint16_t in_use;
1257         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1258
1259         if (unlikely(!count))
1260                 return 0;
1261
1262         in_use = rxq->next_to_use - rxq->next_to_clean;
1263         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1264
1265         count = RTE_MIN(count,
1266                         (uint16_t)(ring_size - (next_to_use & ring_mask)));
1267
1268         /* get resources for incoming packets */
1269         rc = rte_mempool_get_bulk(rxq->mb_pool,
1270                                   (void **)(&mbufs[next_to_use & ring_mask]),
1271                                   count);
1272         if (unlikely(rc < 0)) {
1273                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1274                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1275                 return 0;
1276         }
1277
1278         for (i = 0; i < count; i++) {
1279                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1280                 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1281                 struct ena_com_buf ebuf;
1282
1283                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1284                 /* prepare physical address for DMA transaction */
1285                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1286                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1287                 /* pass resource to device */
1288                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1289                                                 &ebuf, next_to_use_masked);
1290                 if (unlikely(rc)) {
1291                         rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1292                                              count - i);
1293                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1294                         break;
1295                 }
1296                 next_to_use++;
1297         }
1298
1299         /* When we submitted free recources to device... */
1300         if (i > 0) {
1301                 /* ...let HW know that it can fill buffers with data */
1302                 rte_wmb();
1303                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1304
1305                 rxq->next_to_use = next_to_use;
1306         }
1307
1308         return i;
1309 }
1310
1311 static int ena_device_init(struct ena_com_dev *ena_dev,
1312                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1313 {
1314         uint32_t aenq_groups;
1315         int rc;
1316         bool readless_supported;
1317
1318         /* Initialize mmio registers */
1319         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1320         if (rc) {
1321                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1322                 return rc;
1323         }
1324
1325         /* The PCIe configuration space revision id indicate if mmio reg
1326          * read is disabled.
1327          */
1328         readless_supported =
1329                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1330                                & ENA_MMIO_DISABLE_REG_READ);
1331         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1332
1333         /* reset device */
1334         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1335         if (rc) {
1336                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1337                 goto err_mmio_read_less;
1338         }
1339
1340         /* check FW version */
1341         rc = ena_com_validate_version(ena_dev);
1342         if (rc) {
1343                 RTE_LOG(ERR, PMD, "device version is too low\n");
1344                 goto err_mmio_read_less;
1345         }
1346
1347         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1348
1349         /* ENA device administration layer init */
1350         rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
1351         if (rc) {
1352                 RTE_LOG(ERR, PMD,
1353                         "cannot initialize ena admin queue with device\n");
1354                 goto err_mmio_read_less;
1355         }
1356
1357         /* To enable the msix interrupts the driver needs to know the number
1358          * of queues. So the driver uses polling mode to retrieve this
1359          * information.
1360          */
1361         ena_com_set_admin_polling_mode(ena_dev, true);
1362
1363         ena_config_host_info(ena_dev);
1364
1365         /* Get Device Attributes and features */
1366         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1367         if (rc) {
1368                 RTE_LOG(ERR, PMD,
1369                         "cannot get attribute for ena device rc= %d\n", rc);
1370                 goto err_admin_init;
1371         }
1372
1373         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1374                       BIT(ENA_ADMIN_NOTIFICATION) |
1375                       BIT(ENA_ADMIN_KEEP_ALIVE);
1376
1377         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1378         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1379         if (rc) {
1380                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1381                 goto err_admin_init;
1382         }
1383
1384         return 0;
1385
1386 err_admin_init:
1387         ena_com_admin_destroy(ena_dev);
1388
1389 err_mmio_read_less:
1390         ena_com_mmio_reg_read_request_destroy(ena_dev);
1391
1392         return rc;
1393 }
1394
1395 static void ena_interrupt_handler_rte(void *cb_arg)
1396 {
1397         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1398         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1399
1400         ena_com_admin_q_comp_intr_handler(ena_dev);
1401         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1402                 ena_com_aenq_intr_handler(ena_dev, adapter);
1403 }
1404
1405 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1406 {
1407         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1408                 return;
1409
1410         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1411             adapter->keep_alive_timeout)) {
1412                 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1413                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1414                 adapter->trigger_reset = true;
1415         }
1416 }
1417
1418 /* Check if admin queue is enabled */
1419 static void check_for_admin_com_state(struct ena_adapter *adapter)
1420 {
1421         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1422                 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1423                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1424                 adapter->trigger_reset = true;
1425         }
1426 }
1427
1428 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1429                                   void *arg)
1430 {
1431         struct ena_adapter *adapter = (struct ena_adapter *)arg;
1432         struct rte_eth_dev *dev = adapter->rte_dev;
1433
1434         check_for_missing_keep_alive(adapter);
1435         check_for_admin_com_state(adapter);
1436
1437         if (unlikely(adapter->trigger_reset)) {
1438                 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1439                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1440                         NULL);
1441         }
1442 }
1443
1444 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1445 {
1446         struct rte_pci_device *pci_dev;
1447         struct rte_intr_handle *intr_handle;
1448         struct ena_adapter *adapter =
1449                 (struct ena_adapter *)(eth_dev->data->dev_private);
1450         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1451         struct ena_com_dev_get_features_ctx get_feat_ctx;
1452         int queue_size, rc;
1453
1454         static int adapters_found;
1455
1456         memset(adapter, 0, sizeof(struct ena_adapter));
1457         ena_dev = &adapter->ena_dev;
1458
1459         eth_dev->dev_ops = &ena_dev_ops;
1460         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1461         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1462         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1463         adapter->rte_eth_dev_data = eth_dev->data;
1464         adapter->rte_dev = eth_dev;
1465
1466         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1467                 return 0;
1468
1469         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1470         adapter->pdev = pci_dev;
1471
1472         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1473                      pci_dev->addr.domain,
1474                      pci_dev->addr.bus,
1475                      pci_dev->addr.devid,
1476                      pci_dev->addr.function);
1477
1478         intr_handle = &pci_dev->intr_handle;
1479
1480         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1481         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1482
1483         if (!adapter->regs) {
1484                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1485                              ENA_REGS_BAR);
1486                 return -ENXIO;
1487         }
1488
1489         ena_dev->reg_bar = adapter->regs;
1490         ena_dev->dmadev = adapter->pdev;
1491
1492         adapter->id_number = adapters_found;
1493
1494         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1495                  adapter->id_number);
1496
1497         /* device specific initialization routine */
1498         rc = ena_device_init(ena_dev, &get_feat_ctx);
1499         if (rc) {
1500                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1501                 return -1;
1502         }
1503
1504         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1505         adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1506
1507         queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1508         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1509                 return -EFAULT;
1510
1511         adapter->tx_ring_size = queue_size;
1512         adapter->rx_ring_size = queue_size;
1513
1514         /* prepare ring structures */
1515         ena_init_rings(adapter);
1516
1517         ena_config_debug_area(adapter);
1518
1519         /* Set max MTU for this device */
1520         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1521
1522         /* set device support for TSO */
1523         adapter->tso4_supported = get_feat_ctx.offload.tx &
1524                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1525
1526         /* Copy MAC address and point DPDK to it */
1527         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1528         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1529                         (struct ether_addr *)adapter->mac_addr);
1530
1531         adapter->drv_stats = rte_zmalloc("adapter stats",
1532                                          sizeof(*adapter->drv_stats),
1533                                          RTE_CACHE_LINE_SIZE);
1534         if (!adapter->drv_stats) {
1535                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1536                 return -ENOMEM;
1537         }
1538
1539         rte_intr_callback_register(intr_handle,
1540                                    ena_interrupt_handler_rte,
1541                                    adapter);
1542         rte_intr_enable(intr_handle);
1543         ena_com_set_admin_polling_mode(ena_dev, false);
1544         ena_com_admin_aenq_enable(ena_dev);
1545
1546         if (adapters_found == 0)
1547                 rte_timer_subsystem_init();
1548         rte_timer_init(&adapter->timer_wd);
1549
1550         adapters_found++;
1551         adapter->state = ENA_ADAPTER_STATE_INIT;
1552
1553         return 0;
1554 }
1555
1556 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1557 {
1558         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1559         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1560         struct ena_adapter *adapter =
1561                 (struct ena_adapter *)(eth_dev->data->dev_private);
1562
1563         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1564                 return -EPERM;
1565
1566         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1567                 ena_close(eth_dev);
1568
1569         eth_dev->dev_ops = NULL;
1570         eth_dev->rx_pkt_burst = NULL;
1571         eth_dev->tx_pkt_burst = NULL;
1572         eth_dev->tx_pkt_prepare = NULL;
1573
1574         rte_free(adapter->drv_stats);
1575         adapter->drv_stats = NULL;
1576
1577         rte_intr_disable(intr_handle);
1578         rte_intr_callback_unregister(intr_handle,
1579                                      ena_interrupt_handler_rte,
1580                                      adapter);
1581
1582         adapter->state = ENA_ADAPTER_STATE_FREE;
1583
1584         return 0;
1585 }
1586
1587 static int ena_dev_configure(struct rte_eth_dev *dev)
1588 {
1589         struct ena_adapter *adapter =
1590                 (struct ena_adapter *)(dev->data->dev_private);
1591
1592         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1593
1594         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1595         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1596         return 0;
1597 }
1598
1599 static void ena_init_rings(struct ena_adapter *adapter)
1600 {
1601         int i;
1602
1603         for (i = 0; i < adapter->num_queues; i++) {
1604                 struct ena_ring *ring = &adapter->tx_ring[i];
1605
1606                 ring->configured = 0;
1607                 ring->type = ENA_RING_TYPE_TX;
1608                 ring->adapter = adapter;
1609                 ring->id = i;
1610                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1611                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1612         }
1613
1614         for (i = 0; i < adapter->num_queues; i++) {
1615                 struct ena_ring *ring = &adapter->rx_ring[i];
1616
1617                 ring->configured = 0;
1618                 ring->type = ENA_RING_TYPE_RX;
1619                 ring->adapter = adapter;
1620                 ring->id = i;
1621         }
1622 }
1623
1624 static void ena_infos_get(struct rte_eth_dev *dev,
1625                           struct rte_eth_dev_info *dev_info)
1626 {
1627         struct ena_adapter *adapter;
1628         struct ena_com_dev *ena_dev;
1629         struct ena_com_dev_get_features_ctx feat;
1630         uint64_t rx_feat = 0, tx_feat = 0;
1631         int rc = 0;
1632
1633         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1634         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1635         adapter = (struct ena_adapter *)(dev->data->dev_private);
1636
1637         ena_dev = &adapter->ena_dev;
1638         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1639
1640         dev_info->speed_capa =
1641                         ETH_LINK_SPEED_1G   |
1642                         ETH_LINK_SPEED_2_5G |
1643                         ETH_LINK_SPEED_5G   |
1644                         ETH_LINK_SPEED_10G  |
1645                         ETH_LINK_SPEED_25G  |
1646                         ETH_LINK_SPEED_40G  |
1647                         ETH_LINK_SPEED_50G  |
1648                         ETH_LINK_SPEED_100G;
1649
1650         /* Get supported features from HW */
1651         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1652         if (unlikely(rc)) {
1653                 RTE_LOG(ERR, PMD,
1654                         "Cannot get attribute for ena device rc= %d\n", rc);
1655                 return;
1656         }
1657
1658         /* Set Tx & Rx features available for device */
1659         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1660                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1661
1662         if (feat.offload.tx &
1663             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1664                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1665                         DEV_TX_OFFLOAD_UDP_CKSUM |
1666                         DEV_TX_OFFLOAD_TCP_CKSUM;
1667
1668         if (feat.offload.rx_supported &
1669             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1670                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1671                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1672                         DEV_RX_OFFLOAD_TCP_CKSUM;
1673
1674         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1675
1676         /* Inform framework about available features */
1677         dev_info->rx_offload_capa = rx_feat;
1678         dev_info->rx_queue_offload_capa = rx_feat;
1679         dev_info->tx_offload_capa = tx_feat;
1680         dev_info->tx_queue_offload_capa = tx_feat;
1681
1682         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1683         dev_info->max_rx_pktlen  = adapter->max_mtu;
1684         dev_info->max_mac_addrs = 1;
1685
1686         dev_info->max_rx_queues = adapter->num_queues;
1687         dev_info->max_tx_queues = adapter->num_queues;
1688         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1689
1690         adapter->tx_supported_offloads = tx_feat;
1691         adapter->rx_supported_offloads = rx_feat;
1692 }
1693
1694 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1695                                   uint16_t nb_pkts)
1696 {
1697         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1698         unsigned int ring_size = rx_ring->ring_size;
1699         unsigned int ring_mask = ring_size - 1;
1700         uint16_t next_to_clean = rx_ring->next_to_clean;
1701         uint16_t desc_in_use = 0;
1702         unsigned int recv_idx = 0;
1703         struct rte_mbuf *mbuf = NULL;
1704         struct rte_mbuf *mbuf_head = NULL;
1705         struct rte_mbuf *mbuf_prev = NULL;
1706         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1707         unsigned int completed;
1708
1709         struct ena_com_rx_ctx ena_rx_ctx;
1710         int rc = 0;
1711
1712         /* Check adapter state */
1713         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1714                 RTE_LOG(ALERT, PMD,
1715                         "Trying to receive pkts while device is NOT running\n");
1716                 return 0;
1717         }
1718
1719         desc_in_use = rx_ring->next_to_use - next_to_clean;
1720         if (unlikely(nb_pkts > desc_in_use))
1721                 nb_pkts = desc_in_use;
1722
1723         for (completed = 0; completed < nb_pkts; completed++) {
1724                 int segments = 0;
1725
1726                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1727                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1728                 ena_rx_ctx.descs = 0;
1729                 /* receive packet context */
1730                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1731                                     rx_ring->ena_com_io_sq,
1732                                     &ena_rx_ctx);
1733                 if (unlikely(rc)) {
1734                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1735                         return 0;
1736                 }
1737
1738                 if (unlikely(ena_rx_ctx.descs == 0))
1739                         break;
1740
1741                 while (segments < ena_rx_ctx.descs) {
1742                         mbuf = rx_buff_info[next_to_clean & ring_mask];
1743                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1744                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1745                         mbuf->refcnt = 1;
1746                         mbuf->next = NULL;
1747                         if (segments == 0) {
1748                                 mbuf->nb_segs = ena_rx_ctx.descs;
1749                                 mbuf->port = rx_ring->port_id;
1750                                 mbuf->pkt_len = 0;
1751                                 mbuf_head = mbuf;
1752                         } else {
1753                                 /* for multi-segment pkts create mbuf chain */
1754                                 mbuf_prev->next = mbuf;
1755                         }
1756                         mbuf_head->pkt_len += mbuf->data_len;
1757
1758                         mbuf_prev = mbuf;
1759                         segments++;
1760                         next_to_clean++;
1761                 }
1762
1763                 /* fill mbuf attributes if any */
1764                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1765                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1766
1767                 /* pass to DPDK application head mbuf */
1768                 rx_pkts[recv_idx] = mbuf_head;
1769                 recv_idx++;
1770         }
1771
1772         rx_ring->next_to_clean = next_to_clean;
1773
1774         desc_in_use = desc_in_use - completed + 1;
1775         /* Burst refill to save doorbells, memory barriers, const interval */
1776         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1777                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1778
1779         return recv_idx;
1780 }
1781
1782 static uint16_t
1783 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1784                 uint16_t nb_pkts)
1785 {
1786         int32_t ret;
1787         uint32_t i;
1788         struct rte_mbuf *m;
1789         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1790         struct ipv4_hdr *ip_hdr;
1791         uint64_t ol_flags;
1792         uint16_t frag_field;
1793
1794         for (i = 0; i != nb_pkts; i++) {
1795                 m = tx_pkts[i];
1796                 ol_flags = m->ol_flags;
1797
1798                 if (!(ol_flags & PKT_TX_IPV4))
1799                         continue;
1800
1801                 /* If there was not L2 header length specified, assume it is
1802                  * length of the ethernet header.
1803                  */
1804                 if (unlikely(m->l2_len == 0))
1805                         m->l2_len = sizeof(struct ether_hdr);
1806
1807                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1808                                                  m->l2_len);
1809                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1810
1811                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1812                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1813
1814                         /* If IPv4 header has DF flag enabled and TSO support is
1815                          * disabled, partial chcecksum should not be calculated.
1816                          */
1817                         if (!tx_ring->adapter->tso4_supported)
1818                                 continue;
1819                 }
1820
1821                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1822                                 (ol_flags & PKT_TX_L4_MASK) ==
1823                                 PKT_TX_SCTP_CKSUM) {
1824                         rte_errno = -ENOTSUP;
1825                         return i;
1826                 }
1827
1828 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1829                 ret = rte_validate_tx_offload(m);
1830                 if (ret != 0) {
1831                         rte_errno = ret;
1832                         return i;
1833                 }
1834 #endif
1835
1836                 /* In case we are supposed to TSO and have DF not set (DF=0)
1837                  * hardware must be provided with partial checksum, otherwise
1838                  * it will take care of necessary calculations.
1839                  */
1840
1841                 ret = rte_net_intel_cksum_flags_prepare(m,
1842                         ol_flags & ~PKT_TX_TCP_SEG);
1843                 if (ret != 0) {
1844                         rte_errno = ret;
1845                         return i;
1846                 }
1847         }
1848
1849         return i;
1850 }
1851
1852 static void ena_update_hints(struct ena_adapter *adapter,
1853                              struct ena_admin_ena_hw_hints *hints)
1854 {
1855         if (hints->admin_completion_tx_timeout)
1856                 adapter->ena_dev.admin_queue.completion_timeout =
1857                         hints->admin_completion_tx_timeout * 1000;
1858
1859         if (hints->mmio_read_timeout)
1860                 /* convert to usec */
1861                 adapter->ena_dev.mmio_read.reg_read_to =
1862                         hints->mmio_read_timeout * 1000;
1863
1864         if (hints->driver_watchdog_timeout) {
1865                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1866                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
1867                 else
1868                         // Convert msecs to ticks
1869                         adapter->keep_alive_timeout =
1870                                 (hints->driver_watchdog_timeout *
1871                                 rte_get_timer_hz()) / 1000;
1872         }
1873 }
1874
1875 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1876                                   uint16_t nb_pkts)
1877 {
1878         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1879         uint16_t next_to_use = tx_ring->next_to_use;
1880         uint16_t next_to_clean = tx_ring->next_to_clean;
1881         struct rte_mbuf *mbuf;
1882         unsigned int ring_size = tx_ring->ring_size;
1883         unsigned int ring_mask = ring_size - 1;
1884         struct ena_com_tx_ctx ena_tx_ctx;
1885         struct ena_tx_buffer *tx_info;
1886         struct ena_com_buf *ebuf;
1887         uint16_t rc, req_id, total_tx_descs = 0;
1888         uint16_t sent_idx = 0, empty_tx_reqs;
1889         int nb_hw_desc;
1890
1891         /* Check adapter state */
1892         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1893                 RTE_LOG(ALERT, PMD,
1894                         "Trying to xmit pkts while device is NOT running\n");
1895                 return 0;
1896         }
1897
1898         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1899         if (nb_pkts > empty_tx_reqs)
1900                 nb_pkts = empty_tx_reqs;
1901
1902         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1903                 mbuf = tx_pkts[sent_idx];
1904
1905                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1906                 tx_info = &tx_ring->tx_buffer_info[req_id];
1907                 tx_info->mbuf = mbuf;
1908                 tx_info->num_of_bufs = 0;
1909                 ebuf = tx_info->bufs;
1910
1911                 /* Prepare TX context */
1912                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1913                 memset(&ena_tx_ctx.ena_meta, 0x0,
1914                        sizeof(struct ena_com_tx_meta));
1915                 ena_tx_ctx.ena_bufs = ebuf;
1916                 ena_tx_ctx.req_id = req_id;
1917                 if (tx_ring->tx_mem_queue_type ==
1918                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1919                         /* prepare the push buffer with
1920                          * virtual address of the data
1921                          */
1922                         ena_tx_ctx.header_len =
1923                                 RTE_MIN(mbuf->data_len,
1924                                         tx_ring->tx_max_header_size);
1925                         ena_tx_ctx.push_header =
1926                                 (void *)((char *)mbuf->buf_addr +
1927                                          mbuf->data_off);
1928                 } /* there's no else as we take advantage of memset zeroing */
1929
1930                 /* Set TX offloads flags, if applicable */
1931                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
1932
1933                 if (unlikely(mbuf->ol_flags &
1934                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1935                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1936
1937                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1938
1939                 /* Process first segment taking into
1940                  * consideration pushed header
1941                  */
1942                 if (mbuf->data_len > ena_tx_ctx.header_len) {
1943                         ebuf->paddr = mbuf->buf_iova +
1944                                       mbuf->data_off +
1945                                       ena_tx_ctx.header_len;
1946                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1947                         ebuf++;
1948                         tx_info->num_of_bufs++;
1949                 }
1950
1951                 while ((mbuf = mbuf->next) != NULL) {
1952                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
1953                         ebuf->len = mbuf->data_len;
1954                         ebuf++;
1955                         tx_info->num_of_bufs++;
1956                 }
1957
1958                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1959
1960                 /* Write data to device */
1961                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1962                                         &ena_tx_ctx, &nb_hw_desc);
1963                 if (unlikely(rc))
1964                         break;
1965
1966                 tx_info->tx_descs = nb_hw_desc;
1967
1968                 next_to_use++;
1969         }
1970
1971         /* If there are ready packets to be xmitted... */
1972         if (sent_idx > 0) {
1973                 /* ...let HW do its best :-) */
1974                 rte_wmb();
1975                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1976
1977                 tx_ring->next_to_use = next_to_use;
1978         }
1979
1980         /* Clear complete packets  */
1981         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1982                 /* Get Tx info & store how many descs were processed  */
1983                 tx_info = &tx_ring->tx_buffer_info[req_id];
1984                 total_tx_descs += tx_info->tx_descs;
1985
1986                 /* Free whole mbuf chain  */
1987                 mbuf = tx_info->mbuf;
1988                 rte_pktmbuf_free(mbuf);
1989                 tx_info->mbuf = NULL;
1990
1991                 /* Put back descriptor to the ring for reuse */
1992                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
1993                 next_to_clean++;
1994
1995                 /* If too many descs to clean, leave it for another run */
1996                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1997                         break;
1998         }
1999
2000         if (total_tx_descs > 0) {
2001                 /* acknowledge completion of sent packets */
2002                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2003                 tx_ring->next_to_clean = next_to_clean;
2004         }
2005
2006         return sent_idx;
2007 }
2008
2009 /*********************************************************************
2010  *  PMD configuration
2011  *********************************************************************/
2012 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2013         struct rte_pci_device *pci_dev)
2014 {
2015         return rte_eth_dev_pci_generic_probe(pci_dev,
2016                 sizeof(struct ena_adapter), eth_ena_dev_init);
2017 }
2018
2019 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2020 {
2021         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2022 }
2023
2024 static struct rte_pci_driver rte_ena_pmd = {
2025         .id_table = pci_id_ena_map,
2026         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2027         .probe = eth_ena_pci_probe,
2028         .remove = eth_ena_pci_remove,
2029 };
2030
2031 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2032 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2033 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2034
2035 RTE_INIT(ena_init_log);
2036 static void
2037 ena_init_log(void)
2038 {
2039         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2040         if (ena_logtype_init >= 0)
2041                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2042         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2043         if (ena_logtype_driver >= 0)
2044                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2045 }
2046
2047 /******************************************************************************
2048  ******************************** AENQ Handlers *******************************
2049  *****************************************************************************/
2050 static void ena_update_on_link_change(void *adapter_data,
2051                                       struct ena_admin_aenq_entry *aenq_e)
2052 {
2053         struct rte_eth_dev *eth_dev;
2054         struct ena_adapter *adapter;
2055         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2056         uint32_t status;
2057
2058         adapter = (struct ena_adapter *)adapter_data;
2059         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2060         eth_dev = adapter->rte_dev;
2061
2062         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2063         adapter->link_status = status;
2064
2065         ena_link_update(eth_dev, 0);
2066         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2067 }
2068
2069 static void ena_notification(void *data,
2070                              struct ena_admin_aenq_entry *aenq_e)
2071 {
2072         struct ena_adapter *adapter = (struct ena_adapter *)data;
2073         struct ena_admin_ena_hw_hints *hints;
2074
2075         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2076                 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2077                         aenq_e->aenq_common_desc.group,
2078                         ENA_ADMIN_NOTIFICATION);
2079
2080         switch (aenq_e->aenq_common_desc.syndrom) {
2081         case ENA_ADMIN_UPDATE_HINTS:
2082                 hints = (struct ena_admin_ena_hw_hints *)
2083                         (&aenq_e->inline_data_w4);
2084                 ena_update_hints(adapter, hints);
2085                 break;
2086         default:
2087                 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2088                         aenq_e->aenq_common_desc.syndrom);
2089         }
2090 }
2091
2092 static void ena_keep_alive(void *adapter_data,
2093                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2094 {
2095         struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2096
2097         adapter->timestamp_wd = rte_get_timer_cycles();
2098 }
2099
2100 /**
2101  * This handler will called for unknown event group or unimplemented handlers
2102  **/
2103 static void unimplemented_aenq_handler(__rte_unused void *data,
2104                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2105 {
2106         // Unimplemented handler
2107 }
2108
2109 static struct ena_aenq_handlers aenq_handlers = {
2110         .handlers = {
2111                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2112                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2113                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2114         },
2115         .unimplemented_handler = unimplemented_aenq_handler
2116 };