drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 1
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 #define ENA_MIN_RING_DESC       128
  89
  90 enum ethtool_stringset {
  91         ETH_SS_TEST             = 0,
  92         ETH_SS_STATS,
  93 };
  94
  95 struct ena_stats {
  96         char name[ETH_GSTRING_LEN];
  97         int stat_offset;
  98 };
  99
 100 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
 101         .name = #stat, \
 102         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 103 }
 104
 105 #define ENA_STAT_ENTRY(stat, stat_type) { \
 106         .name = #stat, \
 107         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 108 }
 109
 110 #define ENA_STAT_RX_ENTRY(stat) \
 111         ENA_STAT_ENTRY(stat, rx)
 112
 113 #define ENA_STAT_TX_ENTRY(stat) \
 114         ENA_STAT_ENTRY(stat, tx)
 115
 116 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 117         ENA_STAT_ENTRY(stat, dev)
 118
 119 #define ENA_MAX_RING_SIZE_RX 8192
 120 #define ENA_MAX_RING_SIZE_TX 1024
 121
 122 /*
 123  * Each rte_memzone should have unique name.
 124  * To satisfy it, count number of allocation and add it to name.
 125  */
 126 uint32_t ena_alloc_cnt;
 127
 128 static const struct ena_stats ena_stats_global_strings[] = {
 129         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 130         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 131         ENA_STAT_GLOBAL_ENTRY(io_resume),
 132         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 133         ENA_STAT_GLOBAL_ENTRY(interface_up),
 134         ENA_STAT_GLOBAL_ENTRY(interface_down),
 135         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 136 };
 137
 138 static const struct ena_stats ena_stats_tx_strings[] = {
 139         ENA_STAT_TX_ENTRY(cnt),
 140         ENA_STAT_TX_ENTRY(bytes),
 141         ENA_STAT_TX_ENTRY(queue_stop),
 142         ENA_STAT_TX_ENTRY(queue_wakeup),
 143         ENA_STAT_TX_ENTRY(dma_mapping_err),
 144         ENA_STAT_TX_ENTRY(linearize),
 145         ENA_STAT_TX_ENTRY(linearize_failed),
 146         ENA_STAT_TX_ENTRY(tx_poll),
 147         ENA_STAT_TX_ENTRY(doorbells),
 148         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 149         ENA_STAT_TX_ENTRY(missing_tx_comp),
 150         ENA_STAT_TX_ENTRY(bad_req_id),
 151 };
 152
 153 static const struct ena_stats ena_stats_rx_strings[] = {
 154         ENA_STAT_RX_ENTRY(cnt),
 155         ENA_STAT_RX_ENTRY(bytes),
 156         ENA_STAT_RX_ENTRY(refil_partial),
 157         ENA_STAT_RX_ENTRY(bad_csum),
 158         ENA_STAT_RX_ENTRY(page_alloc_fail),
 159         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 160         ENA_STAT_RX_ENTRY(dma_mapping_err),
 161         ENA_STAT_RX_ENTRY(bad_desc_num),
 162         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 163 };
 164
 165 static const struct ena_stats ena_stats_ena_com_strings[] = {
 166         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 167         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 168         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 169         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 170         ENA_STAT_ENA_COM_ENTRY(no_completion),
 171 };
 172
 173 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 174 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 175 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 176 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 177
 178 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 179                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 180                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 181                         DEV_TX_OFFLOAD_TCP_TSO)
 182 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 183                        PKT_TX_IP_CKSUM |\
 184                        PKT_TX_TCP_SEG)
 185
 186 /** Vendor ID used by Amazon devices */
 187 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 188 /** Amazon devices */
 189 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 190 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 191
 192 #define ENA_TX_OFFLOAD_MASK     (\
 193         PKT_TX_L4_MASK |         \
 194         PKT_TX_IPV6 |            \
 195         PKT_TX_IPV4 |            \
 196         PKT_TX_IP_CKSUM |        \
 197         PKT_TX_TCP_SEG)
 198
 199 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 200         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 201
 202 int ena_logtype_init;
 203 int ena_logtype_driver;
 204
 205 static const struct rte_pci_id pci_id_ena_map[] = {
 206         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 207         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 208         { .device_id = 0 },
 209 };
 210
 211 static struct ena_aenq_handlers aenq_handlers;
 212
 213 static int ena_device_init(struct ena_com_dev *ena_dev,
 214                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 215                            bool *wd_state);
 216 static int ena_dev_configure(struct rte_eth_dev *dev);
 217 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 218                                   uint16_t nb_pkts);
 219 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 220                 uint16_t nb_pkts);
 221 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 222                               uint16_t nb_desc, unsigned int socket_id,
 223                               const struct rte_eth_txconf *tx_conf);
 224 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 225                               uint16_t nb_desc, unsigned int socket_id,
 226                               const struct rte_eth_rxconf *rx_conf,
 227                               struct rte_mempool *mp);
 228 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 229                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 230 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 231 static void ena_init_rings(struct ena_adapter *adapter);
 232 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 233 static int ena_start(struct rte_eth_dev *dev);
 234 static void ena_stop(struct rte_eth_dev *dev);
 235 static void ena_close(struct rte_eth_dev *dev);
 236 static int ena_dev_reset(struct rte_eth_dev *dev);
 237 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 238 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 239 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 240 static void ena_rx_queue_release(void *queue);
 241 static void ena_tx_queue_release(void *queue);
 242 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 243 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 244 static int ena_link_update(struct rte_eth_dev *dev,
 245                            int wait_to_complete);
 246 static int ena_create_io_queue(struct ena_ring *ring);
 247 static void ena_queue_stop(struct ena_ring *ring);
 248 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 249                               enum ena_ring_type ring_type);
 250 static int ena_queue_start(struct ena_ring *ring);
 251 static int ena_queue_start_all(struct rte_eth_dev *dev,
 252                                enum ena_ring_type ring_type);
 253 static void ena_stats_restart(struct rte_eth_dev *dev);
 254 static void ena_infos_get(struct rte_eth_dev *dev,
 255                           struct rte_eth_dev_info *dev_info);
 256 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 257                                struct rte_eth_rss_reta_entry64 *reta_conf,
 258                                uint16_t reta_size);
 259 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 260                               struct rte_eth_rss_reta_entry64 *reta_conf,
 261                               uint16_t reta_size);
 262 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 263 static void ena_interrupt_handler_rte(void *cb_arg);
 264 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 265
 266 static const struct eth_dev_ops ena_dev_ops = {
 267         .dev_configure        = ena_dev_configure,
 268         .dev_infos_get        = ena_infos_get,
 269         .rx_queue_setup       = ena_rx_queue_setup,
 270         .tx_queue_setup       = ena_tx_queue_setup,
 271         .dev_start            = ena_start,
 272         .dev_stop             = ena_stop,
 273         .link_update          = ena_link_update,
 274         .stats_get            = ena_stats_get,
 275         .mtu_set              = ena_mtu_set,
 276         .rx_queue_release     = ena_rx_queue_release,
 277         .tx_queue_release     = ena_tx_queue_release,
 278         .dev_close            = ena_close,
 279         .dev_reset            = ena_dev_reset,
 280         .reta_update          = ena_rss_reta_update,
 281         .reta_query           = ena_rss_reta_query,
 282 };
 283
 284 #define NUMA_NO_NODE    SOCKET_ID_ANY
 285
 286 static inline int ena_cpu_to_node(int cpu)
 287 {
 288         struct rte_config *config = rte_eal_get_configuration();
 289         struct rte_fbarray *arr = &config->mem_config->memzones;
 290         const struct rte_memzone *mz;
 291
 292         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 293                 return NUMA_NO_NODE;
 294
 295         mz = rte_fbarray_get(arr, cpu);
 296
 297         return mz->socket_id;
 298 }
 299
 300 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 301                                        struct ena_com_rx_ctx *ena_rx_ctx)
 302 {
 303         uint64_t ol_flags = 0;
 304         uint32_t packet_type = 0;
 305
 306         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 307                 packet_type |= RTE_PTYPE_L4_TCP;
 308         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 309                 packet_type |= RTE_PTYPE_L4_UDP;
 310
 311         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 312                 packet_type |= RTE_PTYPE_L3_IPV4;
 313         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 314                 packet_type |= RTE_PTYPE_L3_IPV6;
 315
 316         if (unlikely(ena_rx_ctx->l4_csum_err))
 317                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 318         if (unlikely(ena_rx_ctx->l3_csum_err))
 319                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 320
 321         mbuf->ol_flags = ol_flags;
 322         mbuf->packet_type = packet_type;
 323 }
 324
 325 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 326                                        struct ena_com_tx_ctx *ena_tx_ctx,
 327                                        uint64_t queue_offloads)
 328 {
 329         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 330
 331         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 332             (queue_offloads & QUEUE_OFFLOADS)) {
 333                 /* check if TSO is required */
 334                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 335                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 336                         ena_tx_ctx->tso_enable = true;
 337
 338                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 339                 }
 340
 341                 /* check if L3 checksum is needed */
 342                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 343                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 344                         ena_tx_ctx->l3_csum_enable = true;
 345
 346                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 347                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 348                 } else {
 349                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 350
 351                         /* set don't fragment (DF) flag */
 352                         if (mbuf->packet_type &
 353                                 (RTE_PTYPE_L4_NONFRAG
 354                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 355                                 ena_tx_ctx->df = true;
 356                 }
 357
 358                 /* check if L4 checksum is needed */
 359                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 360                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 361                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 362                         ena_tx_ctx->l4_csum_enable = true;
 363                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 364                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 365                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 366                         ena_tx_ctx->l4_csum_enable = true;
 367                 } else {
 368                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 369                         ena_tx_ctx->l4_csum_enable = false;
 370                 }
 371
 372                 ena_meta->mss = mbuf->tso_segsz;
 373                 ena_meta->l3_hdr_len = mbuf->l3_len;
 374                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 375
 376                 ena_tx_ctx->meta_valid = true;
 377         } else {
 378                 ena_tx_ctx->meta_valid = false;
 379         }
 380 }
 381
 382 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 383 {
 384         if (likely(req_id < rx_ring->ring_size))
 385                 return 0;
 386
 387         RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
 388
 389         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 390         rx_ring->adapter->trigger_reset = true;
 391
 392         return -EFAULT;
 393 }
 394
 395 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 396 {
 397         struct ena_tx_buffer *tx_info = NULL;
 398
 399         if (likely(req_id < tx_ring->ring_size)) {
 400                 tx_info = &tx_ring->tx_buffer_info[req_id];
 401                 if (likely(tx_info->mbuf))
 402                         return 0;
 403         }
 404
 405         if (tx_info)
 406                 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n");
 407         else
 408                 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id);
 409
 410         /* Trigger device reset */
 411         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 412         tx_ring->adapter->trigger_reset = true;
 413         return -EFAULT;
 414 }
 415
 416 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 417 {
 418         struct ena_admin_host_info *host_info;
 419         int rc;
 420
 421         /* Allocate only the host info */
 422         rc = ena_com_allocate_host_info(ena_dev);
 423         if (rc) {
 424                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 425                 return;
 426         }
 427
 428         host_info = ena_dev->host_attr.host_info;
 429
 430         host_info->os_type = ENA_ADMIN_OS_DPDK;
 431         host_info->kernel_ver = RTE_VERSION;
 432         snprintf((char *)host_info->kernel_ver_str,
 433                  sizeof(host_info->kernel_ver_str),
 434                  "%s", rte_version());
 435         host_info->os_dist = RTE_VERSION;
 436         snprintf((char *)host_info->os_dist_str,
 437                  sizeof(host_info->os_dist_str),
 438                  "%s", rte_version());
 439         host_info->driver_version =
 440                 (DRV_MODULE_VER_MAJOR) |
 441                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 442                 (DRV_MODULE_VER_SUBMINOR <<
 443                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 444         host_info->num_cpus = rte_lcore_count();
 445
 446         rc = ena_com_set_host_attributes(ena_dev);
 447         if (rc) {
 448                 if (rc == -ENA_COM_UNSUPPORTED)
 449                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 450                 else
 451                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 452
 453                 goto err;
 454         }
 455
 456         return;
 457
 458 err:
 459         ena_com_delete_host_info(ena_dev);
 460 }
 461
 462 static int
 463 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 464 {
 465         if (sset != ETH_SS_STATS)
 466                 return -EOPNOTSUPP;
 467
 468          /* Workaround for clang:
 469          * touch internal structures to prevent
 470          * compiler error
 471          */
 472         ENA_TOUCH(ena_stats_global_strings);
 473         ENA_TOUCH(ena_stats_tx_strings);
 474         ENA_TOUCH(ena_stats_rx_strings);
 475         ENA_TOUCH(ena_stats_ena_com_strings);
 476
 477         return  dev->data->nb_tx_queues *
 478                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 479                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 480 }
 481
 482 static void ena_config_debug_area(struct ena_adapter *adapter)
 483 {
 484         u32 debug_area_size;
 485         int rc, ss_count;
 486
 487         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 488         if (ss_count <= 0) {
 489                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 490                 return;
 491         }
 492
 493         /* allocate 32 bytes for each string and 64bit for the value */
 494         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 495
 496         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 497         if (rc) {
 498                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 499                 return;
 500         }
 501
 502         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 503         if (rc) {
 504                 if (rc == -ENA_COM_UNSUPPORTED)
 505                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 506                 else
 507                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 508
 509                 goto err;
 510         }
 511
 512         return;
 513 err:
 514         ena_com_delete_debug_area(&adapter->ena_dev);
 515 }
 516
 517 static void ena_close(struct rte_eth_dev *dev)
 518 {
 519         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 520         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 521         struct ena_adapter *adapter =
 522                 (struct ena_adapter *)(dev->data->dev_private);
 523
 524         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 525                 ena_stop(dev);
 526         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 527
 528         ena_rx_queue_release_all(dev);
 529         ena_tx_queue_release_all(dev);
 530
 531         rte_free(adapter->drv_stats);
 532         adapter->drv_stats = NULL;
 533
 534         rte_intr_disable(intr_handle);
 535         rte_intr_callback_unregister(intr_handle,
 536                                      ena_interrupt_handler_rte,
 537                                      adapter);
 538
 539         /*
 540          * MAC is not allocated dynamically. Setting NULL should prevent from
 541          * release of the resource in the rte_eth_dev_release_port().
 542          */
 543         dev->data->mac_addrs = NULL;
 544 }
 545
 546 static int
 547 ena_dev_reset(struct rte_eth_dev *dev)
 548 {
 549         struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
 550         struct rte_eth_dev *eth_dev;
 551         struct rte_pci_device *pci_dev;
 552         struct rte_intr_handle *intr_handle;
 553         struct ena_com_dev *ena_dev;
 554         struct ena_com_dev_get_features_ctx get_feat_ctx;
 555         struct ena_adapter *adapter;
 556         int nb_queues;
 557         int rc, i;
 558         bool wd_state;
 559
 560         adapter = (struct ena_adapter *)(dev->data->dev_private);
 561         ena_dev = &adapter->ena_dev;
 562         eth_dev = adapter->rte_dev;
 563         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 564         intr_handle = &pci_dev->intr_handle;
 565         nb_queues = eth_dev->data->nb_rx_queues;
 566
 567         ena_com_set_admin_running_state(ena_dev, false);
 568
 569         rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
 570         if (rc)
 571                 RTE_LOG(ERR, PMD, "Device reset failed\n");
 572
 573         for (i = 0; i < nb_queues; i++)
 574                 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
 575
 576         ena_rx_queue_release_all(eth_dev);
 577         ena_tx_queue_release_all(eth_dev);
 578
 579         rte_intr_disable(intr_handle);
 580
 581         ena_com_abort_admin_commands(ena_dev);
 582         ena_com_wait_for_abort_completion(ena_dev);
 583         ena_com_admin_destroy(ena_dev);
 584         ena_com_mmio_reg_read_request_destroy(ena_dev);
 585
 586         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
 587         if (rc) {
 588                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 589                 return rc;
 590         }
 591         adapter->wd_state = wd_state;
 592
 593         rte_intr_enable(intr_handle);
 594         ena_com_set_admin_polling_mode(ena_dev, false);
 595         ena_com_admin_aenq_enable(ena_dev);
 596
 597         for (i = 0; i < nb_queues; ++i)
 598                 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring[i].ring_size, 0,
 599                         NULL, mb_pool_rx[i]);
 600
 601         for (i = 0; i < nb_queues; ++i)
 602                 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring[i].ring_size, 0,
 603                         NULL);
 604
 605         adapter->trigger_reset = false;
 606
 607         return 0;
 608 }
 609
 610 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 611                                struct rte_eth_rss_reta_entry64 *reta_conf,
 612                                uint16_t reta_size)
 613 {
 614         struct ena_adapter *adapter =
 615                 (struct ena_adapter *)(dev->data->dev_private);
 616         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 617         int rc, i;
 618         u16 entry_value;
 619         int conf_idx;
 620         int idx;
 621
 622         if ((reta_size == 0) || (reta_conf == NULL))
 623                 return -EINVAL;
 624
 625         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 626                 RTE_LOG(WARNING, PMD,
 627                         "indirection table %d is bigger than supported (%d)\n",
 628                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 629                 return -EINVAL;
 630         }
 631
 632         for (i = 0 ; i < reta_size ; i++) {
 633                 /* each reta_conf is for 64 entries.
 634                  * to support 128 we use 2 conf of 64
 635                  */
 636                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 637                 idx = i % RTE_RETA_GROUP_SIZE;
 638                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 639                         entry_value =
 640                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 641
 642                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 643                                                                i,
 644                                                                entry_value);
 645                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 646                                 RTE_LOG(ERR, PMD,
 647                                         "Cannot fill indirect table\n");
 648                                 return rc;
 649                         }
 650                 }
 651         }
 652
 653         rc = ena_com_indirect_table_set(ena_dev);
 654         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 655                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 656                 return rc;
 657         }
 658
 659         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 660                 __func__, reta_size, adapter->rte_dev->data->port_id);
 661
 662         return 0;
 663 }
 664
 665 /* Query redirection table. */
 666 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 667                               struct rte_eth_rss_reta_entry64 *reta_conf,
 668                               uint16_t reta_size)
 669 {
 670         struct ena_adapter *adapter =
 671                 (struct ena_adapter *)(dev->data->dev_private);
 672         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 673         int rc;
 674         int i;
 675         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 676         int reta_conf_idx;
 677         int reta_idx;
 678
 679         if (reta_size == 0 || reta_conf == NULL ||
 680             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 681                 return -EINVAL;
 682
 683         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 684         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 685                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 686                 return -ENOTSUP;
 687         }
 688
 689         for (i = 0 ; i < reta_size ; i++) {
 690                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 691                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 692                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 693                         reta_conf[reta_conf_idx].reta[reta_idx] =
 694                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 695         }
 696
 697         return 0;
 698 }
 699
 700 static int ena_rss_init_default(struct ena_adapter *adapter)
 701 {
 702         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 703         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 704         int rc, i;
 705         u32 val;
 706
 707         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 708         if (unlikely(rc)) {
 709                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 710                 goto err_rss_init;
 711         }
 712
 713         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 714                 val = i % nb_rx_queues;
 715                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 716                                                        ENA_IO_RXQ_IDX(val));
 717                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 718                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 719                         goto err_fill_indir;
 720                 }
 721         }
 722
 723         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 724                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 725         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 726                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 727                 goto err_fill_indir;
 728         }
 729
 730         rc = ena_com_set_default_hash_ctrl(ena_dev);
 731         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 732                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 733                 goto err_fill_indir;
 734         }
 735
 736         rc = ena_com_indirect_table_set(ena_dev);
 737         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 738                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 739                 goto err_fill_indir;
 740         }
 741         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 742                 adapter->rte_dev->data->port_id);
 743
 744         return 0;
 745
 746 err_fill_indir:
 747         ena_com_rss_destroy(ena_dev);
 748 err_rss_init:
 749
 750         return rc;
 751 }
 752
 753 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 754 {
 755         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 756         int nb_queues = dev->data->nb_rx_queues;
 757         int i;
 758
 759         for (i = 0; i < nb_queues; i++)
 760                 ena_rx_queue_release(queues[i]);
 761 }
 762
 763 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 764 {
 765         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 766         int nb_queues = dev->data->nb_tx_queues;
 767         int i;
 768
 769         for (i = 0; i < nb_queues; i++)
 770                 ena_tx_queue_release(queues[i]);
 771 }
 772
 773 static void ena_rx_queue_release(void *queue)
 774 {
 775         struct ena_ring *ring = (struct ena_ring *)queue;
 776
 777         ena_assert_msg(ring->configured,
 778                        "API violation - releasing not configured queue");
 779         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 780                        "API violation");
 781
 782         /* Free ring resources */
 783         if (ring->rx_buffer_info)
 784                 rte_free(ring->rx_buffer_info);
 785         ring->rx_buffer_info = NULL;
 786
 787         if (ring->rx_refill_buffer)
 788                 rte_free(ring->rx_refill_buffer);
 789         ring->rx_refill_buffer = NULL;
 790
 791         if (ring->empty_rx_reqs)
 792                 rte_free(ring->empty_rx_reqs);
 793         ring->empty_rx_reqs = NULL;
 794
 795         ring->configured = 0;
 796
 797         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 798                 ring->port_id, ring->id);
 799 }
 800
 801 static void ena_tx_queue_release(void *queue)
 802 {
 803         struct ena_ring *ring = (struct ena_ring *)queue;
 804
 805         ena_assert_msg(ring->configured,
 806                        "API violation. Releasing not configured queue");
 807         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 808                        "API violation");
 809
 810         /* Free ring resources */
 811         if (ring->push_buf_intermediate_buf)
 812                 rte_free(ring->push_buf_intermediate_buf);
 813
 814         if (ring->tx_buffer_info)
 815                 rte_free(ring->tx_buffer_info);
 816
 817         if (ring->empty_tx_reqs)
 818                 rte_free(ring->empty_tx_reqs);
 819
 820         ring->empty_tx_reqs = NULL;
 821         ring->tx_buffer_info = NULL;
 822         ring->push_buf_intermediate_buf = NULL;
 823
 824         ring->configured = 0;
 825
 826         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 827                 ring->port_id, ring->id);
 828 }
 829
 830 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 831 {
 832         unsigned int ring_mask = ring->ring_size - 1;
 833
 834         while (ring->next_to_clean != ring->next_to_use) {
 835                 struct rte_mbuf *m =
 836                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 837
 838                 if (m)
 839                         rte_mbuf_raw_free(m);
 840
 841                 ring->next_to_clean++;
 842         }
 843 }
 844
 845 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 846 {
 847         unsigned int i;
 848
 849         for (i = 0; i < ring->ring_size; ++i) {
 850                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 851
 852                 if (tx_buf->mbuf)
 853                         rte_pktmbuf_free(tx_buf->mbuf);
 854
 855                 ring->next_to_clean++;
 856         }
 857 }
 858
 859 static int ena_link_update(struct rte_eth_dev *dev,
 860                            __rte_unused int wait_to_complete)
 861 {
 862         struct rte_eth_link *link = &dev->data->dev_link;
 863         struct ena_adapter *adapter;
 864
 865         adapter = (struct ena_adapter *)(dev->data->dev_private);
 866
 867         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 868         link->link_speed = ETH_SPEED_NUM_NONE;
 869         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 870
 871         return 0;
 872 }
 873
 874 static int ena_queue_start_all(struct rte_eth_dev *dev,
 875                                enum ena_ring_type ring_type)
 876 {
 877         struct ena_adapter *adapter =
 878                 (struct ena_adapter *)(dev->data->dev_private);
 879         struct ena_ring *queues = NULL;
 880         int nb_queues;
 881         int i = 0;
 882         int rc = 0;
 883
 884         if (ring_type == ENA_RING_TYPE_RX) {
 885                 queues = adapter->rx_ring;
 886                 nb_queues = dev->data->nb_rx_queues;
 887         } else {
 888                 queues = adapter->tx_ring;
 889                 nb_queues = dev->data->nb_tx_queues;
 890         }
 891         for (i = 0; i < nb_queues; i++) {
 892                 if (queues[i].configured) {
 893                         if (ring_type == ENA_RING_TYPE_RX) {
 894                                 ena_assert_msg(
 895                                         dev->data->rx_queues[i] == &queues[i],
 896                                         "Inconsistent state of rx queues\n");
 897                         } else {
 898                                 ena_assert_msg(
 899                                         dev->data->tx_queues[i] == &queues[i],
 900                                         "Inconsistent state of tx queues\n");
 901                         }
 902
 903                         rc = ena_queue_start(&queues[i]);
 904
 905                         if (rc) {
 906                                 PMD_INIT_LOG(ERR,
 907                                              "failed to start queue %d type(%d)",
 908                                              i, ring_type);
 909                                 goto err;
 910                         }
 911                 }
 912         }
 913
 914         return 0;
 915
 916 err:
 917         while (i--)
 918                 if (queues[i].configured)
 919                         ena_queue_stop(&queues[i]);
 920
 921         return rc;
 922 }
 923
 924 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 925 {
 926         uint32_t max_frame_len = adapter->max_mtu;
 927
 928         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 929             DEV_RX_OFFLOAD_JUMBO_FRAME)
 930                 max_frame_len =
 931                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 932
 933         return max_frame_len;
 934 }
 935
 936 static int ena_check_valid_conf(struct ena_adapter *adapter)
 937 {
 938         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 939
 940         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 941                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 942                                   "max mtu: %d, min mtu: %d\n",
 943                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 944                 return ENA_COM_UNSUPPORTED;
 945         }
 946
 947         return 0;
 948 }
 949
 950 static int
 951 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)
 952 {
 953         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 954         struct ena_com_dev *ena_dev = ctx->ena_dev;
 955         uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX;
 956         uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX;
 957
 958         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 959                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 960                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 961                 rx_queue_size = RTE_MIN(rx_queue_size,
 962                         max_queue_ext->max_rx_cq_depth);
 963                 rx_queue_size = RTE_MIN(rx_queue_size,
 964                         max_queue_ext->max_rx_sq_depth);
 965                 tx_queue_size = RTE_MIN(tx_queue_size,
 966                         max_queue_ext->max_tx_cq_depth);
 967
 968                 if (ena_dev->tx_mem_queue_type ==
 969                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 970                         tx_queue_size = RTE_MIN(tx_queue_size,
 971                                 llq->max_llq_depth);
 972                 } else {
 973                         tx_queue_size = RTE_MIN(tx_queue_size,
 974                                 max_queue_ext->max_tx_sq_depth);
 975                 }
 976
 977                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 978                         max_queue_ext->max_per_packet_rx_descs);
 979                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 980                         max_queue_ext->max_per_packet_tx_descs);
 981         } else {
 982                 struct ena_admin_queue_feature_desc *max_queues =
 983                         &ctx->get_feat_ctx->max_queues;
 984                 rx_queue_size = RTE_MIN(rx_queue_size,
 985                         max_queues->max_cq_depth);
 986                 rx_queue_size = RTE_MIN(rx_queue_size,
 987                         max_queues->max_sq_depth);
 988                 tx_queue_size = RTE_MIN(tx_queue_size,
 989                         max_queues->max_cq_depth);
 990
 991                 if (ena_dev->tx_mem_queue_type ==
 992                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 993                         tx_queue_size = RTE_MIN(tx_queue_size,
 994                                 llq->max_llq_depth);
 995                 } else {
 996                         tx_queue_size = RTE_MIN(tx_queue_size,
 997                                 max_queues->max_sq_depth);
 998                 }
 999
1000                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
1001                         max_queues->max_packet_tx_descs);
1002                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
1003                         max_queues->max_packet_rx_descs);
1004         }
1005
1006         /* Round down to the nearest power of 2 */
1007         rx_queue_size = rte_align32prevpow2(rx_queue_size);
1008         tx_queue_size = rte_align32prevpow2(tx_queue_size);
1009
1010         if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) {
1011                 PMD_INIT_LOG(ERR, "Invalid queue size");
1012                 return -EFAULT;
1013         }
1014
1015         ctx->rx_queue_size = rx_queue_size;
1016         ctx->tx_queue_size = tx_queue_size;
1017
1018         return 0;
1019 }
1020
1021 static void ena_stats_restart(struct rte_eth_dev *dev)
1022 {
1023         struct ena_adapter *adapter =
1024                 (struct ena_adapter *)(dev->data->dev_private);
1025
1026         rte_atomic64_init(&adapter->drv_stats->ierrors);
1027         rte_atomic64_init(&adapter->drv_stats->oerrors);
1028         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
1029 }
1030
1031 static int ena_stats_get(struct rte_eth_dev *dev,
1032                           struct rte_eth_stats *stats)
1033 {
1034         struct ena_admin_basic_stats ena_stats;
1035         struct ena_adapter *adapter =
1036                 (struct ena_adapter *)(dev->data->dev_private);
1037         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1038         int rc;
1039
1040         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1041                 return -ENOTSUP;
1042
1043         memset(&ena_stats, 0, sizeof(ena_stats));
1044         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
1045         if (unlikely(rc)) {
1046                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
1047                 return rc;
1048         }
1049
1050         /* Set of basic statistics from ENA */
1051         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
1052                                           ena_stats.rx_pkts_low);
1053         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
1054                                           ena_stats.tx_pkts_low);
1055         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
1056                                         ena_stats.rx_bytes_low);
1057         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
1058                                         ena_stats.tx_bytes_low);
1059         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
1060                                          ena_stats.rx_drops_low);
1061
1062         /* Driver related stats */
1063         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1064         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1065         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1066         return 0;
1067 }
1068
1069 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1070 {
1071         struct ena_adapter *adapter;
1072         struct ena_com_dev *ena_dev;
1073         int rc = 0;
1074
1075         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1076         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1077         adapter = (struct ena_adapter *)(dev->data->dev_private);
1078
1079         ena_dev = &adapter->ena_dev;
1080         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1081
1082         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1083                 RTE_LOG(ERR, PMD,
1084                         "Invalid MTU setting. new_mtu: %d "
1085                         "max mtu: %d min mtu: %d\n",
1086                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1087                 return -EINVAL;
1088         }
1089
1090         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1091         if (rc)
1092                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
1093         else
1094                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1095
1096         return rc;
1097 }
1098
1099 static int ena_start(struct rte_eth_dev *dev)
1100 {
1101         struct ena_adapter *adapter =
1102                 (struct ena_adapter *)(dev->data->dev_private);
1103         uint64_t ticks;
1104         int rc = 0;
1105
1106         rc = ena_check_valid_conf(adapter);
1107         if (rc)
1108                 return rc;
1109
1110         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1111         if (rc)
1112                 return rc;
1113
1114         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1115         if (rc)
1116                 goto err_start_tx;
1117
1118         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1119             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1120                 rc = ena_rss_init_default(adapter);
1121                 if (rc)
1122                         goto err_rss_init;
1123         }
1124
1125         ena_stats_restart(dev);
1126
1127         adapter->timestamp_wd = rte_get_timer_cycles();
1128         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1129
1130         ticks = rte_get_timer_hz();
1131         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1132                         ena_timer_wd_callback, adapter);
1133
1134         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1135
1136         return 0;
1137
1138 err_rss_init:
1139         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1140 err_start_tx:
1141         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1142         return rc;
1143 }
1144
1145 static void ena_stop(struct rte_eth_dev *dev)
1146 {
1147         struct ena_adapter *adapter =
1148                 (struct ena_adapter *)(dev->data->dev_private);
1149
1150         rte_timer_stop_sync(&adapter->timer_wd);
1151         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1152         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1153
1154         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1155 }
1156
1157 static int ena_create_io_queue(struct ena_ring *ring)
1158 {
1159         struct ena_adapter *adapter;
1160         struct ena_com_dev *ena_dev;
1161         struct ena_com_create_io_ctx ctx =
1162                 /* policy set to _HOST just to satisfy icc compiler */
1163                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1164                   0, 0, 0, 0, 0 };
1165         uint16_t ena_qid;
1166         unsigned int i;
1167         int rc;
1168
1169         adapter = ring->adapter;
1170         ena_dev = &adapter->ena_dev;
1171
1172         if (ring->type == ENA_RING_TYPE_TX) {
1173                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1174                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1175                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1176                 ctx.queue_size = adapter->tx_ring_size;
1177                 for (i = 0; i < ring->ring_size; i++)
1178                         ring->empty_tx_reqs[i] = i;
1179         } else {
1180                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1181                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1182                 ctx.queue_size = adapter->rx_ring_size;
1183                 for (i = 0; i < ring->ring_size; i++)
1184                         ring->empty_rx_reqs[i] = i;
1185         }
1186         ctx.qid = ena_qid;
1187         ctx.msix_vector = -1; /* interrupts not used */
1188         ctx.numa_node = ena_cpu_to_node(ring->id);
1189
1190         rc = ena_com_create_io_queue(ena_dev, &ctx);
1191         if (rc) {
1192                 RTE_LOG(ERR, PMD,
1193                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1194                         ring->id, ena_qid, rc);
1195                 return rc;
1196         }
1197
1198         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1199                                      &ring->ena_com_io_sq,
1200                                      &ring->ena_com_io_cq);
1201         if (rc) {
1202                 RTE_LOG(ERR, PMD,
1203                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1204                         ring->id, rc);
1205                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1206                 return rc;
1207         }
1208
1209         if (ring->type == ENA_RING_TYPE_TX)
1210                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1211
1212         return 0;
1213 }
1214
1215 static void ena_queue_stop(struct ena_ring *ring)
1216 {
1217         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1218
1219         if (ring->type == ENA_RING_TYPE_RX) {
1220                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1221                 ena_rx_queue_release_bufs(ring);
1222         } else {
1223                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1224                 ena_tx_queue_release_bufs(ring);
1225         }
1226 }
1227
1228 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1229                               enum ena_ring_type ring_type)
1230 {
1231         struct ena_adapter *adapter =
1232                 (struct ena_adapter *)(dev->data->dev_private);
1233         struct ena_ring *queues = NULL;
1234         uint16_t nb_queues, i;
1235
1236         if (ring_type == ENA_RING_TYPE_RX) {
1237                 queues = adapter->rx_ring;
1238                 nb_queues = dev->data->nb_rx_queues;
1239         } else {
1240                 queues = adapter->tx_ring;
1241                 nb_queues = dev->data->nb_tx_queues;
1242         }
1243
1244         for (i = 0; i < nb_queues; ++i)
1245                 if (queues[i].configured)
1246                         ena_queue_stop(&queues[i]);
1247 }
1248
1249 static int ena_queue_start(struct ena_ring *ring)
1250 {
1251         int rc, bufs_num;
1252
1253         ena_assert_msg(ring->configured == 1,
1254                        "Trying to start unconfigured queue\n");
1255
1256         rc = ena_create_io_queue(ring);
1257         if (rc) {
1258                 PMD_INIT_LOG(ERR, "Failed to create IO queue!\n");
1259                 return rc;
1260         }
1261
1262         ring->next_to_clean = 0;
1263         ring->next_to_use = 0;
1264
1265         if (ring->type == ENA_RING_TYPE_TX)
1266                 return 0;
1267
1268         bufs_num = ring->ring_size - 1;
1269         rc = ena_populate_rx_queue(ring, bufs_num);
1270         if (rc != bufs_num) {
1271                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1272                                          ENA_IO_RXQ_IDX(ring->id));
1273                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1274                 return ENA_COM_FAULT;
1275         }
1276
1277         return 0;
1278 }
1279
1280 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1281                               uint16_t queue_idx,
1282                               uint16_t nb_desc,
1283                               __rte_unused unsigned int socket_id,
1284                               const struct rte_eth_txconf *tx_conf)
1285 {
1286         struct ena_ring *txq = NULL;
1287         struct ena_adapter *adapter =
1288                 (struct ena_adapter *)(dev->data->dev_private);
1289         unsigned int i;
1290
1291         txq = &adapter->tx_ring[queue_idx];
1292
1293         if (txq->configured) {
1294                 RTE_LOG(CRIT, PMD,
1295                         "API violation. Queue %d is already configured\n",
1296                         queue_idx);
1297                 return ENA_COM_FAULT;
1298         }
1299
1300         if (!rte_is_power_of_2(nb_desc)) {
1301                 RTE_LOG(ERR, PMD,
1302                         "Unsupported size of TX queue: %d is not a power of 2.",
1303                         nb_desc);
1304                 return -EINVAL;
1305         }
1306
1307         if (nb_desc > adapter->tx_ring_size) {
1308                 RTE_LOG(ERR, PMD,
1309                         "Unsupported size of TX queue (max size: %d)\n",
1310                         adapter->tx_ring_size);
1311                 return -EINVAL;
1312         }
1313
1314         if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1315                 nb_desc = adapter->tx_ring_size;
1316
1317         txq->port_id = dev->data->port_id;
1318         txq->next_to_clean = 0;
1319         txq->next_to_use = 0;
1320         txq->ring_size = nb_desc;
1321
1322         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1323                                           sizeof(struct ena_tx_buffer) *
1324                                           txq->ring_size,
1325                                           RTE_CACHE_LINE_SIZE);
1326         if (!txq->tx_buffer_info) {
1327                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1328                 return -ENOMEM;
1329         }
1330
1331         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1332                                          sizeof(u16) * txq->ring_size,
1333                                          RTE_CACHE_LINE_SIZE);
1334         if (!txq->empty_tx_reqs) {
1335                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1336                 rte_free(txq->tx_buffer_info);
1337                 return -ENOMEM;
1338         }
1339
1340         txq->push_buf_intermediate_buf =
1341                 rte_zmalloc("txq->push_buf_intermediate_buf",
1342                             txq->tx_max_header_size,
1343                             RTE_CACHE_LINE_SIZE);
1344         if (!txq->push_buf_intermediate_buf) {
1345                 RTE_LOG(ERR, PMD, "failed to alloc push buff for LLQ\n");
1346                 rte_free(txq->tx_buffer_info);
1347                 rte_free(txq->empty_tx_reqs);
1348                 return -ENOMEM;
1349         }
1350
1351         for (i = 0; i < txq->ring_size; i++)
1352                 txq->empty_tx_reqs[i] = i;
1353
1354         if (tx_conf != NULL) {
1355                 txq->offloads =
1356                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1357         }
1358
1359         /* Store pointer to this queue in upper layer */
1360         txq->configured = 1;
1361         dev->data->tx_queues[queue_idx] = txq;
1362
1363         return 0;
1364 }
1365
1366 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1367                               uint16_t queue_idx,
1368                               uint16_t nb_desc,
1369                               __rte_unused unsigned int socket_id,
1370                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1371                               struct rte_mempool *mp)
1372 {
1373         struct ena_adapter *adapter =
1374                 (struct ena_adapter *)(dev->data->dev_private);
1375         struct ena_ring *rxq = NULL;
1376         int i;
1377
1378         rxq = &adapter->rx_ring[queue_idx];
1379         if (rxq->configured) {
1380                 RTE_LOG(CRIT, PMD,
1381                         "API violation. Queue %d is already configured\n",
1382                         queue_idx);
1383                 return ENA_COM_FAULT;
1384         }
1385
1386         if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1387                 nb_desc = adapter->rx_ring_size;
1388
1389         if (!rte_is_power_of_2(nb_desc)) {
1390                 RTE_LOG(ERR, PMD,
1391                         "Unsupported size of RX queue: %d is not a power of 2.",
1392                         nb_desc);
1393                 return -EINVAL;
1394         }
1395
1396         if (nb_desc > adapter->rx_ring_size) {
1397                 RTE_LOG(ERR, PMD,
1398                         "Unsupported size of RX queue (max size: %d)\n",
1399                         adapter->rx_ring_size);
1400                 return -EINVAL;
1401         }
1402
1403         rxq->port_id = dev->data->port_id;
1404         rxq->next_to_clean = 0;
1405         rxq->next_to_use = 0;
1406         rxq->ring_size = nb_desc;
1407         rxq->mb_pool = mp;
1408
1409         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1410                                           sizeof(struct rte_mbuf *) * nb_desc,
1411                                           RTE_CACHE_LINE_SIZE);
1412         if (!rxq->rx_buffer_info) {
1413                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1414                 return -ENOMEM;
1415         }
1416
1417         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1418                                             sizeof(struct rte_mbuf *) * nb_desc,
1419                                             RTE_CACHE_LINE_SIZE);
1420
1421         if (!rxq->rx_refill_buffer) {
1422                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n");
1423                 rte_free(rxq->rx_buffer_info);
1424                 rxq->rx_buffer_info = NULL;
1425                 return -ENOMEM;
1426         }
1427
1428         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1429                                          sizeof(uint16_t) * nb_desc,
1430                                          RTE_CACHE_LINE_SIZE);
1431         if (!rxq->empty_rx_reqs) {
1432                 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1433                 rte_free(rxq->rx_buffer_info);
1434                 rxq->rx_buffer_info = NULL;
1435                 rte_free(rxq->rx_refill_buffer);
1436                 rxq->rx_refill_buffer = NULL;
1437                 return -ENOMEM;
1438         }
1439
1440         for (i = 0; i < nb_desc; i++)
1441                 rxq->empty_tx_reqs[i] = i;
1442
1443         /* Store pointer to this queue in upper layer */
1444         rxq->configured = 1;
1445         dev->data->rx_queues[queue_idx] = rxq;
1446
1447         return 0;
1448 }
1449
1450 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1451 {
1452         unsigned int i;
1453         int rc;
1454         uint16_t ring_size = rxq->ring_size;
1455         uint16_t ring_mask = ring_size - 1;
1456         uint16_t next_to_use = rxq->next_to_use;
1457         uint16_t in_use, req_id;
1458         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1459
1460         if (unlikely(!count))
1461                 return 0;
1462
1463         in_use = rxq->next_to_use - rxq->next_to_clean;
1464         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1465
1466         /* get resources for incoming packets */
1467         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1468         if (unlikely(rc < 0)) {
1469                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1470                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1471                 return 0;
1472         }
1473
1474         for (i = 0; i < count; i++) {
1475                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1476                 struct rte_mbuf *mbuf = mbufs[i];
1477                 struct ena_com_buf ebuf;
1478
1479                 if (likely((i + 4) < count))
1480                         rte_prefetch0(mbufs[i + 4]);
1481
1482                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1483                 rc = validate_rx_req_id(rxq, req_id);
1484                 if (unlikely(rc < 0))
1485                         break;
1486                 rxq->rx_buffer_info[req_id] = mbuf;
1487
1488                 /* prepare physical address for DMA transaction */
1489                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1490                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1491                 /* pass resource to device */
1492                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1493                                                 &ebuf, req_id);
1494                 if (unlikely(rc)) {
1495                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1496                         rxq->rx_buffer_info[req_id] = NULL;
1497                         break;
1498                 }
1499                 next_to_use++;
1500         }
1501
1502         if (unlikely(i < count)) {
1503                 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d "
1504                         "buffers (from %d)\n", rxq->id, i, count);
1505                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1506                                      count - i);
1507         }
1508
1509         /* When we submitted free recources to device... */
1510         if (likely(i > 0)) {
1511                 /* ...let HW know that it can fill buffers with data
1512                  *
1513                  * Add memory barrier to make sure the desc were written before
1514                  * issue a doorbell
1515                  */
1516                 rte_wmb();
1517                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1518
1519                 rxq->next_to_use = next_to_use;
1520         }
1521
1522         return i;
1523 }
1524
1525 static int ena_device_init(struct ena_com_dev *ena_dev,
1526                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1527                            bool *wd_state)
1528 {
1529         uint32_t aenq_groups;
1530         int rc;
1531         bool readless_supported;
1532
1533         /* Initialize mmio registers */
1534         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1535         if (rc) {
1536                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1537                 return rc;
1538         }
1539
1540         /* The PCIe configuration space revision id indicate if mmio reg
1541          * read is disabled.
1542          */
1543         readless_supported =
1544                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1545                                & ENA_MMIO_DISABLE_REG_READ);
1546         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1547
1548         /* reset device */
1549         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1550         if (rc) {
1551                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1552                 goto err_mmio_read_less;
1553         }
1554
1555         /* check FW version */
1556         rc = ena_com_validate_version(ena_dev);
1557         if (rc) {
1558                 RTE_LOG(ERR, PMD, "device version is too low\n");
1559                 goto err_mmio_read_less;
1560         }
1561
1562         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1563
1564         /* ENA device administration layer init */
1565         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1566         if (rc) {
1567                 RTE_LOG(ERR, PMD,
1568                         "cannot initialize ena admin queue with device\n");
1569                 goto err_mmio_read_less;
1570         }
1571
1572         /* To enable the msix interrupts the driver needs to know the number
1573          * of queues. So the driver uses polling mode to retrieve this
1574          * information.
1575          */
1576         ena_com_set_admin_polling_mode(ena_dev, true);
1577
1578         ena_config_host_info(ena_dev);
1579
1580         /* Get Device Attributes and features */
1581         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1582         if (rc) {
1583                 RTE_LOG(ERR, PMD,
1584                         "cannot get attribute for ena device rc= %d\n", rc);
1585                 goto err_admin_init;
1586         }
1587
1588         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1589                       BIT(ENA_ADMIN_NOTIFICATION) |
1590                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1591                       BIT(ENA_ADMIN_FATAL_ERROR) |
1592                       BIT(ENA_ADMIN_WARNING);
1593
1594         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1595         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1596         if (rc) {
1597                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1598                 goto err_admin_init;
1599         }
1600
1601         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1602
1603         return 0;
1604
1605 err_admin_init:
1606         ena_com_admin_destroy(ena_dev);
1607
1608 err_mmio_read_less:
1609         ena_com_mmio_reg_read_request_destroy(ena_dev);
1610
1611         return rc;
1612 }
1613
1614 static void ena_interrupt_handler_rte(void *cb_arg)
1615 {
1616         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1617         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1618
1619         ena_com_admin_q_comp_intr_handler(ena_dev);
1620         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1621                 ena_com_aenq_intr_handler(ena_dev, adapter);
1622 }
1623
1624 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1625 {
1626         if (!adapter->wd_state)
1627                 return;
1628
1629         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1630                 return;
1631
1632         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1633             adapter->keep_alive_timeout)) {
1634                 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1635                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1636                 adapter->trigger_reset = true;
1637         }
1638 }
1639
1640 /* Check if admin queue is enabled */
1641 static void check_for_admin_com_state(struct ena_adapter *adapter)
1642 {
1643         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1644                 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1645                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1646                 adapter->trigger_reset = true;
1647         }
1648 }
1649
1650 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1651                                   void *arg)
1652 {
1653         struct ena_adapter *adapter = (struct ena_adapter *)arg;
1654         struct rte_eth_dev *dev = adapter->rte_dev;
1655
1656         check_for_missing_keep_alive(adapter);
1657         check_for_admin_com_state(adapter);
1658
1659         if (unlikely(adapter->trigger_reset)) {
1660                 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1661                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1662                         NULL);
1663         }
1664 }
1665
1666 static inline void
1667 set_default_llq_configurations(struct ena_llq_configurations *llq_config)
1668 {
1669         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1670         llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1671         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1672         llq_config->llq_num_decs_before_header =
1673                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1674         llq_config->llq_ring_entry_size_value = 128;
1675 }
1676
1677 static int
1678 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1679                                 struct ena_com_dev *ena_dev,
1680                                 struct ena_admin_feature_llq_desc *llq,
1681                                 struct ena_llq_configurations *llq_default_configurations)
1682 {
1683         int rc;
1684         u32 llq_feature_mask;
1685
1686         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1687         if (!(ena_dev->supported_features & llq_feature_mask)) {
1688                 RTE_LOG(INFO, PMD,
1689                         "LLQ is not supported. Fallback to host mode policy.\n");
1690                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1691                 return 0;
1692         }
1693
1694         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1695         if (unlikely(rc)) {
1696                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1697                         "Fallback to host mode policy.\n");
1698                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1699                 return 0;
1700         }
1701
1702         /* Nothing to config, exit */
1703         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1704                 return 0;
1705
1706         if (!adapter->dev_mem_base) {
1707                 RTE_LOG(ERR, PMD, "Unable to access LLQ bar resource. "
1708                         "Fallback to host mode policy.\n.");
1709                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1710                 return 0;
1711         }
1712
1713         ena_dev->mem_bar = adapter->dev_mem_base;
1714
1715         return 0;
1716 }
1717
1718 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,
1719                                  struct ena_com_dev_get_features_ctx *get_feat_ctx)
1720 {
1721         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num;
1722
1723         /* Regular queues capabilities */
1724         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1725                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1726                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1727                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1728                                     max_queue_ext->max_rx_cq_num);
1729                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1730                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1731         } else {
1732                 struct ena_admin_queue_feature_desc *max_queues =
1733                         &get_feat_ctx->max_queues;
1734                 io_tx_sq_num = max_queues->max_sq_num;
1735                 io_tx_cq_num = max_queues->max_cq_num;
1736                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1737         }
1738
1739         /* In case of LLQ use the llq number in the get feature cmd */
1740         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1741                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1742
1743         io_queue_num = RTE_MIN(rte_lcore_count(), ENA_MAX_NUM_IO_QUEUES);
1744         io_queue_num = RTE_MIN(io_queue_num, io_rx_num);
1745         io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num);
1746         io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num);
1747
1748         if (unlikely(io_queue_num == 0)) {
1749                 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n");
1750                 return -EFAULT;
1751         }
1752
1753         return io_queue_num;
1754 }
1755
1756 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1757 {
1758         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1759         struct rte_pci_device *pci_dev;
1760         struct rte_intr_handle *intr_handle;
1761         struct ena_adapter *adapter =
1762                 (struct ena_adapter *)(eth_dev->data->dev_private);
1763         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1764         struct ena_com_dev_get_features_ctx get_feat_ctx;
1765         struct ena_llq_configurations llq_config;
1766         const char *queue_type_str;
1767         int rc;
1768
1769         static int adapters_found;
1770         bool wd_state;
1771
1772         memset(adapter, 0, sizeof(struct ena_adapter));
1773         ena_dev = &adapter->ena_dev;
1774
1775         eth_dev->dev_ops = &ena_dev_ops;
1776         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1777         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1778         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1779         adapter->rte_eth_dev_data = eth_dev->data;
1780         adapter->rte_dev = eth_dev;
1781
1782         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1783                 return 0;
1784
1785         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1786         adapter->pdev = pci_dev;
1787
1788         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1789                      pci_dev->addr.domain,
1790                      pci_dev->addr.bus,
1791                      pci_dev->addr.devid,
1792                      pci_dev->addr.function);
1793
1794         intr_handle = &pci_dev->intr_handle;
1795
1796         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1797         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1798
1799         if (!adapter->regs) {
1800                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1801                              ENA_REGS_BAR);
1802                 return -ENXIO;
1803         }
1804
1805         ena_dev->reg_bar = adapter->regs;
1806         ena_dev->dmadev = adapter->pdev;
1807
1808         adapter->id_number = adapters_found;
1809
1810         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1811                  adapter->id_number);
1812
1813         /* device specific initialization routine */
1814         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1815         if (rc) {
1816                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1817                 goto err;
1818         }
1819         adapter->wd_state = wd_state;
1820
1821         set_default_llq_configurations(&llq_config);
1822         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1823                                              &get_feat_ctx.llq, &llq_config);
1824         if (unlikely(rc)) {
1825                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1826                 return rc;
1827         }
1828
1829         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1830                 queue_type_str = "Regular";
1831         else
1832                 queue_type_str = "Low latency";
1833         RTE_LOG(INFO, PMD, "Placement policy: %s\n", queue_type_str);
1834
1835         calc_queue_ctx.ena_dev = ena_dev;
1836         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1837         adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1838                                                     &get_feat_ctx);
1839
1840         rc = ena_calc_queue_size(&calc_queue_ctx);
1841         if (unlikely((rc != 0) || (adapter->num_queues <= 0))) {
1842                 rc = -EFAULT;
1843                 goto err_device_destroy;
1844         }
1845
1846         adapter->tx_ring_size = calc_queue_ctx.tx_queue_size;
1847         adapter->rx_ring_size = calc_queue_ctx.rx_queue_size;
1848
1849         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1850         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1851
1852         /* prepare ring structures */
1853         ena_init_rings(adapter);
1854
1855         ena_config_debug_area(adapter);
1856
1857         /* Set max MTU for this device */
1858         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1859
1860         /* set device support for TSO */
1861         adapter->tso4_supported = get_feat_ctx.offload.tx &
1862                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1863
1864         /* Copy MAC address and point DPDK to it */
1865         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1866         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1867                         (struct ether_addr *)adapter->mac_addr);
1868
1869         /*
1870          * Pass the information to the rte_eth_dev_close() that it should also
1871          * release the private port resources.
1872          */
1873         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1874
1875         adapter->drv_stats = rte_zmalloc("adapter stats",
1876                                          sizeof(*adapter->drv_stats),
1877                                          RTE_CACHE_LINE_SIZE);
1878         if (!adapter->drv_stats) {
1879                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1880                 rc = -ENOMEM;
1881                 goto err_delete_debug_area;
1882         }
1883
1884         rte_intr_callback_register(intr_handle,
1885                                    ena_interrupt_handler_rte,
1886                                    adapter);
1887         rte_intr_enable(intr_handle);
1888         ena_com_set_admin_polling_mode(ena_dev, false);
1889         ena_com_admin_aenq_enable(ena_dev);
1890
1891         if (adapters_found == 0)
1892                 rte_timer_subsystem_init();
1893         rte_timer_init(&adapter->timer_wd);
1894
1895         adapters_found++;
1896         adapter->state = ENA_ADAPTER_STATE_INIT;
1897
1898         return 0;
1899
1900 err_delete_debug_area:
1901         ena_com_delete_debug_area(ena_dev);
1902
1903 err_device_destroy:
1904         ena_com_delete_host_info(ena_dev);
1905         ena_com_admin_destroy(ena_dev);
1906
1907 err:
1908         return rc;
1909 }
1910
1911 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1912 {
1913         struct ena_adapter *adapter =
1914                 (struct ena_adapter *)(eth_dev->data->dev_private);
1915
1916         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1917                 return 0;
1918
1919         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1920                 ena_close(eth_dev);
1921
1922         eth_dev->dev_ops = NULL;
1923         eth_dev->rx_pkt_burst = NULL;
1924         eth_dev->tx_pkt_burst = NULL;
1925         eth_dev->tx_pkt_prepare = NULL;
1926
1927         adapter->state = ENA_ADAPTER_STATE_FREE;
1928
1929         return 0;
1930 }
1931
1932 static int ena_dev_configure(struct rte_eth_dev *dev)
1933 {
1934         struct ena_adapter *adapter =
1935                 (struct ena_adapter *)(dev->data->dev_private);
1936
1937         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1938
1939         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1940         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1941         return 0;
1942 }
1943
1944 static void ena_init_rings(struct ena_adapter *adapter)
1945 {
1946         int i;
1947
1948         for (i = 0; i < adapter->num_queues; i++) {
1949                 struct ena_ring *ring = &adapter->tx_ring[i];
1950
1951                 ring->configured = 0;
1952                 ring->type = ENA_RING_TYPE_TX;
1953                 ring->adapter = adapter;
1954                 ring->id = i;
1955                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1956                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1957                 ring->sgl_size = adapter->max_tx_sgl_size;
1958         }
1959
1960         for (i = 0; i < adapter->num_queues; i++) {
1961                 struct ena_ring *ring = &adapter->rx_ring[i];
1962
1963                 ring->configured = 0;
1964                 ring->type = ENA_RING_TYPE_RX;
1965                 ring->adapter = adapter;
1966                 ring->id = i;
1967                 ring->sgl_size = adapter->max_rx_sgl_size;
1968         }
1969 }
1970
1971 static void ena_infos_get(struct rte_eth_dev *dev,
1972                           struct rte_eth_dev_info *dev_info)
1973 {
1974         struct ena_adapter *adapter;
1975         struct ena_com_dev *ena_dev;
1976         struct ena_com_dev_get_features_ctx feat;
1977         uint64_t rx_feat = 0, tx_feat = 0;
1978         int rc = 0;
1979
1980         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1981         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1982         adapter = (struct ena_adapter *)(dev->data->dev_private);
1983
1984         ena_dev = &adapter->ena_dev;
1985         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1986
1987         dev_info->speed_capa =
1988                         ETH_LINK_SPEED_1G   |
1989                         ETH_LINK_SPEED_2_5G |
1990                         ETH_LINK_SPEED_5G   |
1991                         ETH_LINK_SPEED_10G  |
1992                         ETH_LINK_SPEED_25G  |
1993                         ETH_LINK_SPEED_40G  |
1994                         ETH_LINK_SPEED_50G  |
1995                         ETH_LINK_SPEED_100G;
1996
1997         /* Get supported features from HW */
1998         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1999         if (unlikely(rc)) {
2000                 RTE_LOG(ERR, PMD,
2001                         "Cannot get attribute for ena device rc= %d\n", rc);
2002                 return;
2003         }
2004
2005         /* Set Tx & Rx features available for device */
2006         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
2007                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
2008
2009         if (feat.offload.tx &
2010             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
2011                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
2012                         DEV_TX_OFFLOAD_UDP_CKSUM |
2013                         DEV_TX_OFFLOAD_TCP_CKSUM;
2014
2015         if (feat.offload.rx_supported &
2016             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
2017                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
2018                         DEV_RX_OFFLOAD_UDP_CKSUM  |
2019                         DEV_RX_OFFLOAD_TCP_CKSUM;
2020
2021         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2022
2023         /* Inform framework about available features */
2024         dev_info->rx_offload_capa = rx_feat;
2025         dev_info->rx_queue_offload_capa = rx_feat;
2026         dev_info->tx_offload_capa = tx_feat;
2027         dev_info->tx_queue_offload_capa = tx_feat;
2028
2029         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2030         dev_info->max_rx_pktlen  = adapter->max_mtu;
2031         dev_info->max_mac_addrs = 1;
2032
2033         dev_info->max_rx_queues = adapter->num_queues;
2034         dev_info->max_tx_queues = adapter->num_queues;
2035         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2036
2037         adapter->tx_supported_offloads = tx_feat;
2038         adapter->rx_supported_offloads = rx_feat;
2039
2040         dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size;
2041         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2042         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2043                                         adapter->max_rx_sgl_size);
2044         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2045                                         adapter->max_rx_sgl_size);
2046
2047         dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size;
2048         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2049         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2050                                         adapter->max_tx_sgl_size);
2051         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2052                                         adapter->max_tx_sgl_size);
2053 }
2054
2055 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2056                                   uint16_t nb_pkts)
2057 {
2058         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2059         unsigned int ring_size = rx_ring->ring_size;
2060         unsigned int ring_mask = ring_size - 1;
2061         uint16_t next_to_clean = rx_ring->next_to_clean;
2062         uint16_t desc_in_use = 0;
2063         uint16_t req_id;
2064         unsigned int recv_idx = 0;
2065         struct rte_mbuf *mbuf = NULL;
2066         struct rte_mbuf *mbuf_head = NULL;
2067         struct rte_mbuf *mbuf_prev = NULL;
2068         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
2069         unsigned int completed;
2070
2071         struct ena_com_rx_ctx ena_rx_ctx;
2072         int rc = 0;
2073
2074         /* Check adapter state */
2075         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2076                 RTE_LOG(ALERT, PMD,
2077                         "Trying to receive pkts while device is NOT running\n");
2078                 return 0;
2079         }
2080
2081         desc_in_use = rx_ring->next_to_use - next_to_clean;
2082         if (unlikely(nb_pkts > desc_in_use))
2083                 nb_pkts = desc_in_use;
2084
2085         for (completed = 0; completed < nb_pkts; completed++) {
2086                 int segments = 0;
2087
2088                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2089                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2090                 ena_rx_ctx.descs = 0;
2091                 /* receive packet context */
2092                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2093                                     rx_ring->ena_com_io_sq,
2094                                     &ena_rx_ctx);
2095                 if (unlikely(rc)) {
2096                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
2097                         rx_ring->adapter->reset_reason =
2098                                 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2099                         rx_ring->adapter->trigger_reset = true;
2100                         return 0;
2101                 }
2102
2103                 if (unlikely(ena_rx_ctx.descs == 0))
2104                         break;
2105
2106                 while (segments < ena_rx_ctx.descs) {
2107                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
2108                         rc = validate_rx_req_id(rx_ring, req_id);
2109                         if (unlikely(rc))
2110                                 break;
2111
2112                         mbuf = rx_buff_info[req_id];
2113                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
2114                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2115                         mbuf->refcnt = 1;
2116                         mbuf->next = NULL;
2117                         if (unlikely(segments == 0)) {
2118                                 mbuf->nb_segs = ena_rx_ctx.descs;
2119                                 mbuf->port = rx_ring->port_id;
2120                                 mbuf->pkt_len = 0;
2121                                 mbuf_head = mbuf;
2122                         } else {
2123                                 /* for multi-segment pkts create mbuf chain */
2124                                 mbuf_prev->next = mbuf;
2125                         }
2126                         mbuf_head->pkt_len += mbuf->data_len;
2127
2128                         mbuf_prev = mbuf;
2129                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
2130                                 req_id;
2131                         segments++;
2132                         next_to_clean++;
2133                 }
2134                 if (unlikely(rc))
2135                         break;
2136
2137                 /* fill mbuf attributes if any */
2138                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
2139                 mbuf_head->hash.rss = ena_rx_ctx.hash;
2140
2141                 /* pass to DPDK application head mbuf */
2142                 rx_pkts[recv_idx] = mbuf_head;
2143                 recv_idx++;
2144         }
2145
2146         rx_ring->next_to_clean = next_to_clean;
2147
2148         desc_in_use = desc_in_use - completed + 1;
2149         /* Burst refill to save doorbells, memory barriers, const interval */
2150         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
2151                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
2152
2153         return recv_idx;
2154 }
2155
2156 static uint16_t
2157 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2158                 uint16_t nb_pkts)
2159 {
2160         int32_t ret;
2161         uint32_t i;
2162         struct rte_mbuf *m;
2163         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2164         struct ipv4_hdr *ip_hdr;
2165         uint64_t ol_flags;
2166         uint16_t frag_field;
2167
2168         for (i = 0; i != nb_pkts; i++) {
2169                 m = tx_pkts[i];
2170                 ol_flags = m->ol_flags;
2171
2172                 if (!(ol_flags & PKT_TX_IPV4))
2173                         continue;
2174
2175                 /* If there was not L2 header length specified, assume it is
2176                  * length of the ethernet header.
2177                  */
2178                 if (unlikely(m->l2_len == 0))
2179                         m->l2_len = sizeof(struct ether_hdr);
2180
2181                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
2182                                                  m->l2_len);
2183                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2184
2185                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
2186                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2187
2188                         /* If IPv4 header has DF flag enabled and TSO support is
2189                          * disabled, partial chcecksum should not be calculated.
2190                          */
2191                         if (!tx_ring->adapter->tso4_supported)
2192                                 continue;
2193                 }
2194
2195                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2196                                 (ol_flags & PKT_TX_L4_MASK) ==
2197                                 PKT_TX_SCTP_CKSUM) {
2198                         rte_errno = -ENOTSUP;
2199                         return i;
2200                 }
2201
2202 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2203                 ret = rte_validate_tx_offload(m);
2204                 if (ret != 0) {
2205                         rte_errno = ret;
2206                         return i;
2207                 }
2208 #endif
2209
2210                 /* In case we are supposed to TSO and have DF not set (DF=0)
2211                  * hardware must be provided with partial checksum, otherwise
2212                  * it will take care of necessary calculations.
2213                  */
2214
2215                 ret = rte_net_intel_cksum_flags_prepare(m,
2216                         ol_flags & ~PKT_TX_TCP_SEG);
2217                 if (ret != 0) {
2218                         rte_errno = ret;
2219                         return i;
2220                 }
2221         }
2222
2223         return i;
2224 }
2225
2226 static void ena_update_hints(struct ena_adapter *adapter,
2227                              struct ena_admin_ena_hw_hints *hints)
2228 {
2229         if (hints->admin_completion_tx_timeout)
2230                 adapter->ena_dev.admin_queue.completion_timeout =
2231                         hints->admin_completion_tx_timeout * 1000;
2232
2233         if (hints->mmio_read_timeout)
2234                 /* convert to usec */
2235                 adapter->ena_dev.mmio_read.reg_read_to =
2236                         hints->mmio_read_timeout * 1000;
2237
2238         if (hints->driver_watchdog_timeout) {
2239                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2240                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2241                 else
2242                         // Convert msecs to ticks
2243                         adapter->keep_alive_timeout =
2244                                 (hints->driver_watchdog_timeout *
2245                                 rte_get_timer_hz()) / 1000;
2246         }
2247 }
2248
2249 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2250                                         struct rte_mbuf *mbuf)
2251 {
2252         struct ena_com_dev *ena_dev;
2253         int num_segments, header_len, rc;
2254
2255         ena_dev = &tx_ring->adapter->ena_dev;
2256         num_segments = mbuf->nb_segs;
2257         header_len = mbuf->data_len;
2258
2259         if (likely(num_segments < tx_ring->sgl_size))
2260                 return 0;
2261
2262         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2263             (num_segments == tx_ring->sgl_size) &&
2264             (header_len < tx_ring->tx_max_header_size))
2265                 return 0;
2266
2267         rc = rte_pktmbuf_linearize(mbuf);
2268         if (unlikely(rc))
2269                 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
2270
2271         return rc;
2272 }
2273
2274 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2275                                   uint16_t nb_pkts)
2276 {
2277         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2278         uint16_t next_to_use = tx_ring->next_to_use;
2279         uint16_t next_to_clean = tx_ring->next_to_clean;
2280         struct rte_mbuf *mbuf;
2281         uint16_t seg_len;
2282         unsigned int ring_size = tx_ring->ring_size;
2283         unsigned int ring_mask = ring_size - 1;
2284         struct ena_com_tx_ctx ena_tx_ctx;
2285         struct ena_tx_buffer *tx_info;
2286         struct ena_com_buf *ebuf;
2287         uint16_t rc, req_id, total_tx_descs = 0;
2288         uint16_t sent_idx = 0, empty_tx_reqs;
2289         uint16_t push_len = 0;
2290         uint16_t delta = 0;
2291         int nb_hw_desc;
2292
2293         /* Check adapter state */
2294         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2295                 RTE_LOG(ALERT, PMD,
2296                         "Trying to xmit pkts while device is NOT running\n");
2297                 return 0;
2298         }
2299
2300         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2301         if (nb_pkts > empty_tx_reqs)
2302                 nb_pkts = empty_tx_reqs;
2303
2304         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2305                 mbuf = tx_pkts[sent_idx];
2306
2307                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2308                 if (unlikely(rc))
2309                         break;
2310
2311                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2312                 tx_info = &tx_ring->tx_buffer_info[req_id];
2313                 tx_info->mbuf = mbuf;
2314                 tx_info->num_of_bufs = 0;
2315                 ebuf = tx_info->bufs;
2316
2317                 /* Prepare TX context */
2318                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2319                 memset(&ena_tx_ctx.ena_meta, 0x0,
2320                        sizeof(struct ena_com_tx_meta));
2321                 ena_tx_ctx.ena_bufs = ebuf;
2322                 ena_tx_ctx.req_id = req_id;
2323
2324                 delta = 0;
2325                 seg_len = mbuf->data_len;
2326
2327                 if (tx_ring->tx_mem_queue_type ==
2328                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2329                         push_len = RTE_MIN(mbuf->pkt_len,
2330                                            tx_ring->tx_max_header_size);
2331                         ena_tx_ctx.header_len = push_len;
2332
2333                         if (likely(push_len <= seg_len)) {
2334                                 /* If the push header is in the single segment,
2335                                  * then just point it to the 1st mbuf data.
2336                                  */
2337                                 ena_tx_ctx.push_header =
2338                                         rte_pktmbuf_mtod(mbuf, uint8_t *);
2339                         } else {
2340                                 /* If the push header lays in the several
2341                                  * segments, copy it to the intermediate buffer.
2342                                  */
2343                                 rte_pktmbuf_read(mbuf, 0, push_len,
2344                                         tx_ring->push_buf_intermediate_buf);
2345                                 ena_tx_ctx.push_header =
2346                                         tx_ring->push_buf_intermediate_buf;
2347                                 delta = push_len - seg_len;
2348                         }
2349                 } /* there's no else as we take advantage of memset zeroing */
2350
2351                 /* Set TX offloads flags, if applicable */
2352                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2353
2354                 if (unlikely(mbuf->ol_flags &
2355                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2356                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2357
2358                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2359
2360                 /* Process first segment taking into
2361                  * consideration pushed header
2362                  */
2363                 if (seg_len > push_len) {
2364                         ebuf->paddr = mbuf->buf_iova +
2365                                       mbuf->data_off +
2366                                       push_len;
2367                         ebuf->len = seg_len - push_len;
2368                         ebuf++;
2369                         tx_info->num_of_bufs++;
2370                 }
2371
2372                 while ((mbuf = mbuf->next) != NULL) {
2373                         seg_len = mbuf->data_len;
2374
2375                         /* Skip mbufs if whole data is pushed as a header */
2376                         if (unlikely(delta > seg_len)) {
2377                                 delta -= seg_len;
2378                                 continue;
2379                         }
2380
2381                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2382                         ebuf->len = seg_len - delta;
2383                         ebuf++;
2384                         tx_info->num_of_bufs++;
2385
2386                         delta = 0;
2387                 }
2388
2389                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2390
2391                 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2392                                                &ena_tx_ctx)) {
2393                         RTE_LOG(DEBUG, PMD, "llq tx max burst size of queue %d"
2394                                 " achieved, writing doorbell to send burst\n",
2395                                 tx_ring->id);
2396                         rte_wmb();
2397                         ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2398                 }
2399
2400                 /* prepare the packet's descriptors to dma engine */
2401                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2402                                         &ena_tx_ctx, &nb_hw_desc);
2403                 if (unlikely(rc))
2404                         break;
2405
2406                 tx_info->tx_descs = nb_hw_desc;
2407
2408                 next_to_use++;
2409         }
2410
2411         /* If there are ready packets to be xmitted... */
2412         if (sent_idx > 0) {
2413                 /* ...let HW do its best :-) */
2414                 rte_wmb();
2415                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2416
2417                 tx_ring->next_to_use = next_to_use;
2418         }
2419
2420         /* Clear complete packets  */
2421         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2422                 rc = validate_tx_req_id(tx_ring, req_id);
2423                 if (rc)
2424                         break;
2425
2426                 /* Get Tx info & store how many descs were processed  */
2427                 tx_info = &tx_ring->tx_buffer_info[req_id];
2428                 total_tx_descs += tx_info->tx_descs;
2429
2430                 /* Free whole mbuf chain  */
2431                 mbuf = tx_info->mbuf;
2432                 rte_pktmbuf_free(mbuf);
2433                 tx_info->mbuf = NULL;
2434
2435                 /* Put back descriptor to the ring for reuse */
2436                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2437                 next_to_clean++;
2438
2439                 /* If too many descs to clean, leave it for another run */
2440                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2441                         break;
2442         }
2443
2444         if (total_tx_descs > 0) {
2445                 /* acknowledge completion of sent packets */
2446                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2447                 tx_ring->next_to_clean = next_to_clean;
2448         }
2449
2450         return sent_idx;
2451 }
2452
2453 /*********************************************************************
2454  *  PMD configuration
2455  *********************************************************************/
2456 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2457         struct rte_pci_device *pci_dev)
2458 {
2459         return rte_eth_dev_pci_generic_probe(pci_dev,
2460                 sizeof(struct ena_adapter), eth_ena_dev_init);
2461 }
2462
2463 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2464 {
2465         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2466 }
2467
2468 static struct rte_pci_driver rte_ena_pmd = {
2469         .id_table = pci_id_ena_map,
2470         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2471                      RTE_PCI_DRV_WC_ACTIVATE,
2472         .probe = eth_ena_pci_probe,
2473         .remove = eth_ena_pci_remove,
2474 };
2475
2476 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2477 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2478 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2479
2480 RTE_INIT(ena_init_log)
2481 {
2482         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2483         if (ena_logtype_init >= 0)
2484                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2485         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2486         if (ena_logtype_driver >= 0)
2487                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2488 }
2489
2490 /******************************************************************************
2491  ******************************** AENQ Handlers *******************************
2492  *****************************************************************************/
2493 static void ena_update_on_link_change(void *adapter_data,
2494                                       struct ena_admin_aenq_entry *aenq_e)
2495 {
2496         struct rte_eth_dev *eth_dev;
2497         struct ena_adapter *adapter;
2498         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2499         uint32_t status;
2500
2501         adapter = (struct ena_adapter *)adapter_data;
2502         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2503         eth_dev = adapter->rte_dev;
2504
2505         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2506         adapter->link_status = status;
2507
2508         ena_link_update(eth_dev, 0);
2509         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2510 }
2511
2512 static void ena_notification(void *data,
2513                              struct ena_admin_aenq_entry *aenq_e)
2514 {
2515         struct ena_adapter *adapter = (struct ena_adapter *)data;
2516         struct ena_admin_ena_hw_hints *hints;
2517
2518         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2519                 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2520                         aenq_e->aenq_common_desc.group,
2521                         ENA_ADMIN_NOTIFICATION);
2522
2523         switch (aenq_e->aenq_common_desc.syndrom) {
2524         case ENA_ADMIN_UPDATE_HINTS:
2525                 hints = (struct ena_admin_ena_hw_hints *)
2526                         (&aenq_e->inline_data_w4);
2527                 ena_update_hints(adapter, hints);
2528                 break;
2529         default:
2530                 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2531                         aenq_e->aenq_common_desc.syndrom);
2532         }
2533 }
2534
2535 static void ena_keep_alive(void *adapter_data,
2536                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2537 {
2538         struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2539
2540         adapter->timestamp_wd = rte_get_timer_cycles();
2541 }
2542
2543 /**
2544  * This handler will called for unknown event group or unimplemented handlers
2545  **/
2546 static void unimplemented_aenq_handler(__rte_unused void *data,
2547                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2548 {
2549         RTE_LOG(ERR, PMD, "Unknown event was received or event with "
2550                           "unimplemented handler\n");
2551 }
2552
2553 static struct ena_aenq_handlers aenq_handlers = {
2554         .handlers = {
2555                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2556                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2557                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2558         },
2559         .unimplemented_handler = unimplemented_aenq_handler
2560 };