drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 0
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 enum ethtool_stringset {
  89         ETH_SS_TEST             = 0,
  90         ETH_SS_STATS,
  91 };
  92
  93 struct ena_stats {
  94         char name[ETH_GSTRING_LEN];
  95         int stat_offset;
  96 };
  97
  98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
  99         .name = #stat, \
 100         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 101 }
 102
 103 #define ENA_STAT_ENTRY(stat, stat_type) { \
 104         .name = #stat, \
 105         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 106 }
 107
 108 #define ENA_STAT_RX_ENTRY(stat) \
 109         ENA_STAT_ENTRY(stat, rx)
 110
 111 #define ENA_STAT_TX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, tx)
 113
 114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, dev)
 116
 117 /*
 118  * Each rte_memzone should have unique name.
 119  * To satisfy it, count number of allocation and add it to name.
 120  */
 121 uint32_t ena_alloc_cnt;
 122
 123 static const struct ena_stats ena_stats_global_strings[] = {
 124         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 125         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 126         ENA_STAT_GLOBAL_ENTRY(io_resume),
 127         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 128         ENA_STAT_GLOBAL_ENTRY(interface_up),
 129         ENA_STAT_GLOBAL_ENTRY(interface_down),
 130         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 131 };
 132
 133 static const struct ena_stats ena_stats_tx_strings[] = {
 134         ENA_STAT_TX_ENTRY(cnt),
 135         ENA_STAT_TX_ENTRY(bytes),
 136         ENA_STAT_TX_ENTRY(queue_stop),
 137         ENA_STAT_TX_ENTRY(queue_wakeup),
 138         ENA_STAT_TX_ENTRY(dma_mapping_err),
 139         ENA_STAT_TX_ENTRY(linearize),
 140         ENA_STAT_TX_ENTRY(linearize_failed),
 141         ENA_STAT_TX_ENTRY(tx_poll),
 142         ENA_STAT_TX_ENTRY(doorbells),
 143         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 144         ENA_STAT_TX_ENTRY(missing_tx_comp),
 145         ENA_STAT_TX_ENTRY(bad_req_id),
 146 };
 147
 148 static const struct ena_stats ena_stats_rx_strings[] = {
 149         ENA_STAT_RX_ENTRY(cnt),
 150         ENA_STAT_RX_ENTRY(bytes),
 151         ENA_STAT_RX_ENTRY(refil_partial),
 152         ENA_STAT_RX_ENTRY(bad_csum),
 153         ENA_STAT_RX_ENTRY(page_alloc_fail),
 154         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 155         ENA_STAT_RX_ENTRY(dma_mapping_err),
 156         ENA_STAT_RX_ENTRY(bad_desc_num),
 157         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 158 };
 159
 160 static const struct ena_stats ena_stats_ena_com_strings[] = {
 161         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 162         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 163         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 164         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 165         ENA_STAT_ENA_COM_ENTRY(no_completion),
 166 };
 167
 168 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 169 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 170 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 171 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 172
 173 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 174                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 175                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 176                         DEV_TX_OFFLOAD_TCP_TSO)
 177 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 178                        PKT_TX_IP_CKSUM |\
 179                        PKT_TX_TCP_SEG)
 180
 181 /** Vendor ID used by Amazon devices */
 182 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 183 /** Amazon devices */
 184 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 185 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 186
 187 #define ENA_TX_OFFLOAD_MASK     (\
 188         PKT_TX_L4_MASK |         \
 189         PKT_TX_IP_CKSUM |        \
 190         PKT_TX_TCP_SEG)
 191
 192 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 193         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 194
 195 int ena_logtype_init;
 196 int ena_logtype_driver;
 197
 198 static const struct rte_pci_id pci_id_ena_map[] = {
 199         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 200         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 201         { .device_id = 0 },
 202 };
 203
 204 static struct ena_aenq_handlers empty_aenq_handlers;
 205
 206 static int ena_device_init(struct ena_com_dev *ena_dev,
 207                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 208 static int ena_dev_configure(struct rte_eth_dev *dev);
 209 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 210                                   uint16_t nb_pkts);
 211 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 212                 uint16_t nb_pkts);
 213 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 214                               uint16_t nb_desc, unsigned int socket_id,
 215                               const struct rte_eth_txconf *tx_conf);
 216 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 217                               uint16_t nb_desc, unsigned int socket_id,
 218                               const struct rte_eth_rxconf *rx_conf,
 219                               struct rte_mempool *mp);
 220 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 221                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 222 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 223 static void ena_init_rings(struct ena_adapter *adapter);
 224 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 225 static int ena_start(struct rte_eth_dev *dev);
 226 static void ena_close(struct rte_eth_dev *dev);
 227 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 228 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 229 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 230 static void ena_rx_queue_release(void *queue);
 231 static void ena_tx_queue_release(void *queue);
 232 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 233 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 234 static int ena_link_update(struct rte_eth_dev *dev,
 235                            int wait_to_complete);
 236 static int ena_queue_restart(struct ena_ring *ring);
 237 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 238                                  enum ena_ring_type ring_type);
 239 static void ena_stats_restart(struct rte_eth_dev *dev);
 240 static void ena_infos_get(struct rte_eth_dev *dev,
 241                           struct rte_eth_dev_info *dev_info);
 242 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 243                                struct rte_eth_rss_reta_entry64 *reta_conf,
 244                                uint16_t reta_size);
 245 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 246                               struct rte_eth_rss_reta_entry64 *reta_conf,
 247                               uint16_t reta_size);
 248 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 249
 250 static const struct eth_dev_ops ena_dev_ops = {
 251         .dev_configure        = ena_dev_configure,
 252         .dev_infos_get        = ena_infos_get,
 253         .rx_queue_setup       = ena_rx_queue_setup,
 254         .tx_queue_setup       = ena_tx_queue_setup,
 255         .dev_start            = ena_start,
 256         .link_update          = ena_link_update,
 257         .stats_get            = ena_stats_get,
 258         .mtu_set              = ena_mtu_set,
 259         .rx_queue_release     = ena_rx_queue_release,
 260         .tx_queue_release     = ena_tx_queue_release,
 261         .dev_close            = ena_close,
 262         .reta_update          = ena_rss_reta_update,
 263         .reta_query           = ena_rss_reta_query,
 264 };
 265
 266 #define NUMA_NO_NODE    SOCKET_ID_ANY
 267
 268 static inline int ena_cpu_to_node(int cpu)
 269 {
 270         struct rte_config *config = rte_eal_get_configuration();
 271         struct rte_fbarray *arr = &config->mem_config->memzones;
 272         const struct rte_memzone *mz;
 273
 274         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 275                 return NUMA_NO_NODE;
 276
 277         mz = rte_fbarray_get(arr, cpu);
 278
 279         return mz->socket_id;
 280 }
 281
 282 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 283                                        struct ena_com_rx_ctx *ena_rx_ctx)
 284 {
 285         uint64_t ol_flags = 0;
 286         uint32_t packet_type = 0;
 287
 288         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 289                 packet_type |= RTE_PTYPE_L4_TCP;
 290         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 291                 packet_type |= RTE_PTYPE_L4_UDP;
 292
 293         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 294                 packet_type |= RTE_PTYPE_L3_IPV4;
 295         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 296                 packet_type |= RTE_PTYPE_L3_IPV6;
 297
 298         if (unlikely(ena_rx_ctx->l4_csum_err))
 299                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 300         if (unlikely(ena_rx_ctx->l3_csum_err))
 301                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 302
 303         mbuf->ol_flags = ol_flags;
 304         mbuf->packet_type = packet_type;
 305 }
 306
 307 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 308                                        struct ena_com_tx_ctx *ena_tx_ctx,
 309                                        uint64_t queue_offloads)
 310 {
 311         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 312
 313         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 314             (queue_offloads & QUEUE_OFFLOADS)) {
 315                 /* check if TSO is required */
 316                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 317                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 318                         ena_tx_ctx->tso_enable = true;
 319
 320                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 321                 }
 322
 323                 /* check if L3 checksum is needed */
 324                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 325                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 326                         ena_tx_ctx->l3_csum_enable = true;
 327
 328                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 329                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 330                 } else {
 331                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 332
 333                         /* set don't fragment (DF) flag */
 334                         if (mbuf->packet_type &
 335                                 (RTE_PTYPE_L4_NONFRAG
 336                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 337                                 ena_tx_ctx->df = true;
 338                 }
 339
 340                 /* check if L4 checksum is needed */
 341                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 342                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 343                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 344                         ena_tx_ctx->l4_csum_enable = true;
 345                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 346                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 347                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 348                         ena_tx_ctx->l4_csum_enable = true;
 349                 } else {
 350                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 351                         ena_tx_ctx->l4_csum_enable = false;
 352                 }
 353
 354                 ena_meta->mss = mbuf->tso_segsz;
 355                 ena_meta->l3_hdr_len = mbuf->l3_len;
 356                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 357
 358                 ena_tx_ctx->meta_valid = true;
 359         } else {
 360                 ena_tx_ctx->meta_valid = false;
 361         }
 362 }
 363
 364 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 365 {
 366         struct ena_admin_host_info *host_info;
 367         int rc;
 368
 369         /* Allocate only the host info */
 370         rc = ena_com_allocate_host_info(ena_dev);
 371         if (rc) {
 372                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 373                 return;
 374         }
 375
 376         host_info = ena_dev->host_attr.host_info;
 377
 378         host_info->os_type = ENA_ADMIN_OS_DPDK;
 379         host_info->kernel_ver = RTE_VERSION;
 380         snprintf((char *)host_info->kernel_ver_str,
 381                  sizeof(host_info->kernel_ver_str),
 382                  "%s", rte_version());
 383         host_info->os_dist = RTE_VERSION;
 384         snprintf((char *)host_info->os_dist_str,
 385                  sizeof(host_info->os_dist_str),
 386                  "%s", rte_version());
 387         host_info->driver_version =
 388                 (DRV_MODULE_VER_MAJOR) |
 389                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 390                 (DRV_MODULE_VER_SUBMINOR <<
 391                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 392
 393         rc = ena_com_set_host_attributes(ena_dev);
 394         if (rc) {
 395                 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 396                 if (rc != -ENA_COM_UNSUPPORTED)
 397                         goto err;
 398         }
 399
 400         return;
 401
 402 err:
 403         ena_com_delete_host_info(ena_dev);
 404 }
 405
 406 static int
 407 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 408 {
 409         if (sset != ETH_SS_STATS)
 410                 return -EOPNOTSUPP;
 411
 412          /* Workaround for clang:
 413          * touch internal structures to prevent
 414          * compiler error
 415          */
 416         ENA_TOUCH(ena_stats_global_strings);
 417         ENA_TOUCH(ena_stats_tx_strings);
 418         ENA_TOUCH(ena_stats_rx_strings);
 419         ENA_TOUCH(ena_stats_ena_com_strings);
 420
 421         return  dev->data->nb_tx_queues *
 422                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 423                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 424 }
 425
 426 static void ena_config_debug_area(struct ena_adapter *adapter)
 427 {
 428         u32 debug_area_size;
 429         int rc, ss_count;
 430
 431         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 432         if (ss_count <= 0) {
 433                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 434                 return;
 435         }
 436
 437         /* allocate 32 bytes for each string and 64bit for the value */
 438         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 439
 440         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 441         if (rc) {
 442                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 443                 return;
 444         }
 445
 446         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 447         if (rc) {
 448                 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 449                 if (rc != -ENA_COM_UNSUPPORTED)
 450                         goto err;
 451         }
 452
 453         return;
 454 err:
 455         ena_com_delete_debug_area(&adapter->ena_dev);
 456 }
 457
 458 static void ena_close(struct rte_eth_dev *dev)
 459 {
 460         struct ena_adapter *adapter =
 461                 (struct ena_adapter *)(dev->data->dev_private);
 462
 463         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 464
 465         ena_rx_queue_release_all(dev);
 466         ena_tx_queue_release_all(dev);
 467 }
 468
 469 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 470                                struct rte_eth_rss_reta_entry64 *reta_conf,
 471                                uint16_t reta_size)
 472 {
 473         struct ena_adapter *adapter =
 474                 (struct ena_adapter *)(dev->data->dev_private);
 475         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 476         int ret, i;
 477         u16 entry_value;
 478         int conf_idx;
 479         int idx;
 480
 481         if ((reta_size == 0) || (reta_conf == NULL))
 482                 return -EINVAL;
 483
 484         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 485                 RTE_LOG(WARNING, PMD,
 486                         "indirection table %d is bigger than supported (%d)\n",
 487                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 488                 ret = -EINVAL;
 489                 goto err;
 490         }
 491
 492         for (i = 0 ; i < reta_size ; i++) {
 493                 /* each reta_conf is for 64 entries.
 494                  * to support 128 we use 2 conf of 64
 495                  */
 496                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 497                 idx = i % RTE_RETA_GROUP_SIZE;
 498                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 499                         entry_value =
 500                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 501                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 502                                                                 i,
 503                                                                 entry_value);
 504                         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 505                                 RTE_LOG(ERR, PMD,
 506                                         "Cannot fill indirect table\n");
 507                                 ret = -ENOTSUP;
 508                                 goto err;
 509                         }
 510                 }
 511         }
 512
 513         ret = ena_com_indirect_table_set(ena_dev);
 514         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 515                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 516                 ret = -ENOTSUP;
 517                 goto err;
 518         }
 519
 520         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 521                 __func__, reta_size, adapter->rte_dev->data->port_id);
 522 err:
 523         return ret;
 524 }
 525
 526 /* Query redirection table. */
 527 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 528                               struct rte_eth_rss_reta_entry64 *reta_conf,
 529                               uint16_t reta_size)
 530 {
 531         struct ena_adapter *adapter =
 532                 (struct ena_adapter *)(dev->data->dev_private);
 533         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 534         int ret;
 535         int i;
 536         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 537         int reta_conf_idx;
 538         int reta_idx;
 539
 540         if (reta_size == 0 || reta_conf == NULL ||
 541             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 542                 return -EINVAL;
 543
 544         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 545         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 546                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 547                 ret = -ENOTSUP;
 548                 goto err;
 549         }
 550
 551         for (i = 0 ; i < reta_size ; i++) {
 552                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 553                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 554                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 555                         reta_conf[reta_conf_idx].reta[reta_idx] =
 556                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 557         }
 558 err:
 559         return ret;
 560 }
 561
 562 static int ena_rss_init_default(struct ena_adapter *adapter)
 563 {
 564         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 565         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 566         int rc, i;
 567         u32 val;
 568
 569         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 570         if (unlikely(rc)) {
 571                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 572                 goto err_rss_init;
 573         }
 574
 575         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 576                 val = i % nb_rx_queues;
 577                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 578                                                        ENA_IO_RXQ_IDX(val));
 579                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 580                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 581                         goto err_fill_indir;
 582                 }
 583         }
 584
 585         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 586                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 587         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 588                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 589                 goto err_fill_indir;
 590         }
 591
 592         rc = ena_com_set_default_hash_ctrl(ena_dev);
 593         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 594                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 595                 goto err_fill_indir;
 596         }
 597
 598         rc = ena_com_indirect_table_set(ena_dev);
 599         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 600                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 601                 goto err_fill_indir;
 602         }
 603         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 604                 adapter->rte_dev->data->port_id);
 605
 606         return 0;
 607
 608 err_fill_indir:
 609         ena_com_rss_destroy(ena_dev);
 610 err_rss_init:
 611
 612         return rc;
 613 }
 614
 615 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 616 {
 617         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 618         int nb_queues = dev->data->nb_rx_queues;
 619         int i;
 620
 621         for (i = 0; i < nb_queues; i++)
 622                 ena_rx_queue_release(queues[i]);
 623 }
 624
 625 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 626 {
 627         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 628         int nb_queues = dev->data->nb_tx_queues;
 629         int i;
 630
 631         for (i = 0; i < nb_queues; i++)
 632                 ena_tx_queue_release(queues[i]);
 633 }
 634
 635 static void ena_rx_queue_release(void *queue)
 636 {
 637         struct ena_ring *ring = (struct ena_ring *)queue;
 638         struct ena_adapter *adapter = ring->adapter;
 639         int ena_qid;
 640
 641         ena_assert_msg(ring->configured,
 642                        "API violation - releasing not configured queue");
 643         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 644                        "API violation");
 645
 646         /* Destroy HW queue */
 647         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 648         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 649
 650         /* Free all bufs */
 651         ena_rx_queue_release_bufs(ring);
 652
 653         /* Free ring resources */
 654         if (ring->rx_buffer_info)
 655                 rte_free(ring->rx_buffer_info);
 656         ring->rx_buffer_info = NULL;
 657
 658         ring->configured = 0;
 659
 660         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 661                 ring->port_id, ring->id);
 662 }
 663
 664 static void ena_tx_queue_release(void *queue)
 665 {
 666         struct ena_ring *ring = (struct ena_ring *)queue;
 667         struct ena_adapter *adapter = ring->adapter;
 668         int ena_qid;
 669
 670         ena_assert_msg(ring->configured,
 671                        "API violation. Releasing not configured queue");
 672         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 673                        "API violation");
 674
 675         /* Destroy HW queue */
 676         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 677         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 678
 679         /* Free all bufs */
 680         ena_tx_queue_release_bufs(ring);
 681
 682         /* Free ring resources */
 683         if (ring->tx_buffer_info)
 684                 rte_free(ring->tx_buffer_info);
 685
 686         if (ring->empty_tx_reqs)
 687                 rte_free(ring->empty_tx_reqs);
 688
 689         ring->empty_tx_reqs = NULL;
 690         ring->tx_buffer_info = NULL;
 691
 692         ring->configured = 0;
 693
 694         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 695                 ring->port_id, ring->id);
 696 }
 697
 698 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 699 {
 700         unsigned int ring_mask = ring->ring_size - 1;
 701
 702         while (ring->next_to_clean != ring->next_to_use) {
 703                 struct rte_mbuf *m =
 704                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 705
 706                 if (m)
 707                         rte_mbuf_raw_free(m);
 708
 709                 ring->next_to_clean++;
 710         }
 711 }
 712
 713 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 714 {
 715         unsigned int i;
 716
 717         for (i = 0; i < ring->ring_size; ++i) {
 718                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 719
 720                 if (tx_buf->mbuf)
 721                         rte_pktmbuf_free(tx_buf->mbuf);
 722
 723                 ring->next_to_clean++;
 724         }
 725 }
 726
 727 static int ena_link_update(struct rte_eth_dev *dev,
 728                            __rte_unused int wait_to_complete)
 729 {
 730         struct rte_eth_link *link = &dev->data->dev_link;
 731
 732         link->link_status = ETH_LINK_UP;
 733         link->link_speed = ETH_SPEED_NUM_10G;
 734         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 735
 736         return 0;
 737 }
 738
 739 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 740                                  enum ena_ring_type ring_type)
 741 {
 742         struct ena_adapter *adapter =
 743                 (struct ena_adapter *)(dev->data->dev_private);
 744         struct ena_ring *queues = NULL;
 745         int i = 0;
 746         int rc = 0;
 747
 748         queues = (ring_type == ENA_RING_TYPE_RX) ?
 749                 adapter->rx_ring : adapter->tx_ring;
 750
 751         for (i = 0; i < adapter->num_queues; i++) {
 752                 if (queues[i].configured) {
 753                         if (ring_type == ENA_RING_TYPE_RX) {
 754                                 ena_assert_msg(
 755                                         dev->data->rx_queues[i] == &queues[i],
 756                                         "Inconsistent state of rx queues\n");
 757                         } else {
 758                                 ena_assert_msg(
 759                                         dev->data->tx_queues[i] == &queues[i],
 760                                         "Inconsistent state of tx queues\n");
 761                         }
 762
 763                         rc = ena_queue_restart(&queues[i]);
 764
 765                         if (rc) {
 766                                 PMD_INIT_LOG(ERR,
 767                                              "failed to restart queue %d type(%d)",
 768                                              i, ring_type);
 769                                 return -1;
 770                         }
 771                 }
 772         }
 773
 774         return 0;
 775 }
 776
 777 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 778 {
 779         uint32_t max_frame_len = adapter->max_mtu;
 780
 781         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 782             DEV_RX_OFFLOAD_JUMBO_FRAME)
 783                 max_frame_len =
 784                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 785
 786         return max_frame_len;
 787 }
 788
 789 static int ena_check_valid_conf(struct ena_adapter *adapter)
 790 {
 791         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 792
 793         if (max_frame_len > adapter->max_mtu) {
 794                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
 795                 return -1;
 796         }
 797
 798         return 0;
 799 }
 800
 801 static int
 802 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 803                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 804 {
 805         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 806
 807         queue_size = RTE_MIN(queue_size,
 808                              get_feat_ctx->max_queues.max_cq_depth);
 809         queue_size = RTE_MIN(queue_size,
 810                              get_feat_ctx->max_queues.max_sq_depth);
 811
 812         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 813                 queue_size = RTE_MIN(queue_size,
 814                                      get_feat_ctx->max_queues.max_llq_depth);
 815
 816         /* Round down to power of 2 */
 817         if (!rte_is_power_of_2(queue_size))
 818                 queue_size = rte_align32pow2(queue_size >> 1);
 819
 820         if (queue_size == 0) {
 821                 PMD_INIT_LOG(ERR, "Invalid queue size");
 822                 return -EFAULT;
 823         }
 824
 825         return queue_size;
 826 }
 827
 828 static void ena_stats_restart(struct rte_eth_dev *dev)
 829 {
 830         struct ena_adapter *adapter =
 831                 (struct ena_adapter *)(dev->data->dev_private);
 832
 833         rte_atomic64_init(&adapter->drv_stats->ierrors);
 834         rte_atomic64_init(&adapter->drv_stats->oerrors);
 835         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 836 }
 837
 838 static int ena_stats_get(struct rte_eth_dev *dev,
 839                           struct rte_eth_stats *stats)
 840 {
 841         struct ena_admin_basic_stats ena_stats;
 842         struct ena_adapter *adapter =
 843                 (struct ena_adapter *)(dev->data->dev_private);
 844         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 845         int rc;
 846
 847         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 848                 return -ENOTSUP;
 849
 850         memset(&ena_stats, 0, sizeof(ena_stats));
 851         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 852         if (unlikely(rc)) {
 853                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 854                 return rc;
 855         }
 856
 857         /* Set of basic statistics from ENA */
 858         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 859                                           ena_stats.rx_pkts_low);
 860         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 861                                           ena_stats.tx_pkts_low);
 862         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 863                                         ena_stats.rx_bytes_low);
 864         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 865                                         ena_stats.tx_bytes_low);
 866         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 867                                          ena_stats.rx_drops_low);
 868
 869         /* Driver related stats */
 870         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 871         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 872         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 873         return 0;
 874 }
 875
 876 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 877 {
 878         struct ena_adapter *adapter;
 879         struct ena_com_dev *ena_dev;
 880         int rc = 0;
 881
 882         ena_assert_msg(dev->data != NULL, "Uninitialized device");
 883         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
 884         adapter = (struct ena_adapter *)(dev->data->dev_private);
 885
 886         ena_dev = &adapter->ena_dev;
 887         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
 888
 889         if (mtu > ena_get_mtu_conf(adapter)) {
 890                 RTE_LOG(ERR, PMD,
 891                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
 892                         mtu, ena_get_mtu_conf(adapter));
 893                 rc = -EINVAL;
 894                 goto err;
 895         }
 896
 897         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 898         if (rc)
 899                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
 900         else
 901                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
 902
 903 err:
 904         return rc;
 905 }
 906
 907 static int ena_start(struct rte_eth_dev *dev)
 908 {
 909         struct ena_adapter *adapter =
 910                 (struct ena_adapter *)(dev->data->dev_private);
 911         int rc = 0;
 912
 913         if (!(adapter->state == ENA_ADAPTER_STATE_CONFIG ||
 914               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
 915                 PMD_INIT_LOG(ERR, "API violation");
 916                 return -1;
 917         }
 918
 919         rc = ena_check_valid_conf(adapter);
 920         if (rc)
 921                 return rc;
 922
 923         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
 924         if (rc)
 925                 return rc;
 926
 927         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
 928         if (rc)
 929                 return rc;
 930
 931         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
 932             ETH_MQ_RX_RSS_FLAG) {
 933                 rc = ena_rss_init_default(adapter);
 934                 if (rc)
 935                         return rc;
 936         }
 937
 938         ena_stats_restart(dev);
 939
 940         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 941
 942         return 0;
 943 }
 944
 945 static int ena_queue_restart(struct ena_ring *ring)
 946 {
 947         int rc, bufs_num;
 948
 949         ena_assert_msg(ring->configured == 1,
 950                        "Trying to restart unconfigured queue\n");
 951
 952         ring->next_to_clean = 0;
 953         ring->next_to_use = 0;
 954
 955         if (ring->type == ENA_RING_TYPE_TX)
 956                 return 0;
 957
 958         bufs_num = ring->ring_size - 1;
 959         rc = ena_populate_rx_queue(ring, bufs_num);
 960         if (rc != bufs_num) {
 961                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
 962                 return (-1);
 963         }
 964
 965         return 0;
 966 }
 967
 968 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
 969                               uint16_t queue_idx,
 970                               uint16_t nb_desc,
 971                               __rte_unused unsigned int socket_id,
 972                               const struct rte_eth_txconf *tx_conf)
 973 {
 974         struct ena_com_create_io_ctx ctx =
 975                 /* policy set to _HOST just to satisfy icc compiler */
 976                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
 977                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
 978         struct ena_ring *txq = NULL;
 979         struct ena_adapter *adapter =
 980                 (struct ena_adapter *)(dev->data->dev_private);
 981         unsigned int i;
 982         int ena_qid;
 983         int rc;
 984         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 985
 986         txq = &adapter->tx_ring[queue_idx];
 987
 988         if (txq->configured) {
 989                 RTE_LOG(CRIT, PMD,
 990                         "API violation. Queue %d is already configured\n",
 991                         queue_idx);
 992                 return -1;
 993         }
 994
 995         if (!rte_is_power_of_2(nb_desc)) {
 996                 RTE_LOG(ERR, PMD,
 997                         "Unsupported size of RX queue: %d is not a power of 2.",
 998                         nb_desc);
 999                 return -EINVAL;
1000         }
1001
1002         if (nb_desc > adapter->tx_ring_size) {
1003                 RTE_LOG(ERR, PMD,
1004                         "Unsupported size of TX queue (max size: %d)\n",
1005                         adapter->tx_ring_size);
1006                 return -EINVAL;
1007         }
1008
1009         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1010
1011         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1012         ctx.qid = ena_qid;
1013         ctx.msix_vector = -1; /* admin interrupts not used */
1014         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1015         ctx.queue_size = adapter->tx_ring_size;
1016         ctx.numa_node = ena_cpu_to_node(queue_idx);
1017
1018         rc = ena_com_create_io_queue(ena_dev, &ctx);
1019         if (rc) {
1020                 RTE_LOG(ERR, PMD,
1021                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1022                         queue_idx, ena_qid, rc);
1023         }
1024         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1025         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1026
1027         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1028                                      &txq->ena_com_io_sq,
1029                                      &txq->ena_com_io_cq);
1030         if (rc) {
1031                 RTE_LOG(ERR, PMD,
1032                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1033                         queue_idx, rc);
1034                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1035                 goto err;
1036         }
1037
1038         txq->port_id = dev->data->port_id;
1039         txq->next_to_clean = 0;
1040         txq->next_to_use = 0;
1041         txq->ring_size = nb_desc;
1042
1043         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1044                                           sizeof(struct ena_tx_buffer) *
1045                                           txq->ring_size,
1046                                           RTE_CACHE_LINE_SIZE);
1047         if (!txq->tx_buffer_info) {
1048                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1049                 return -ENOMEM;
1050         }
1051
1052         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1053                                          sizeof(u16) * txq->ring_size,
1054                                          RTE_CACHE_LINE_SIZE);
1055         if (!txq->empty_tx_reqs) {
1056                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1057                 rte_free(txq->tx_buffer_info);
1058                 return -ENOMEM;
1059         }
1060         for (i = 0; i < txq->ring_size; i++)
1061                 txq->empty_tx_reqs[i] = i;
1062
1063         txq->offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1064
1065         /* Store pointer to this queue in upper layer */
1066         txq->configured = 1;
1067         dev->data->tx_queues[queue_idx] = txq;
1068 err:
1069         return rc;
1070 }
1071
1072 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1073                               uint16_t queue_idx,
1074                               uint16_t nb_desc,
1075                               __rte_unused unsigned int socket_id,
1076                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1077                               struct rte_mempool *mp)
1078 {
1079         struct ena_com_create_io_ctx ctx =
1080                 /* policy set to _HOST just to satisfy icc compiler */
1081                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1082                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1083         struct ena_adapter *adapter =
1084                 (struct ena_adapter *)(dev->data->dev_private);
1085         struct ena_ring *rxq = NULL;
1086         uint16_t ena_qid = 0;
1087         int rc = 0;
1088         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1089
1090         rxq = &adapter->rx_ring[queue_idx];
1091         if (rxq->configured) {
1092                 RTE_LOG(CRIT, PMD,
1093                         "API violation. Queue %d is already configured\n",
1094                         queue_idx);
1095                 return -1;
1096         }
1097
1098         if (!rte_is_power_of_2(nb_desc)) {
1099                 RTE_LOG(ERR, PMD,
1100                         "Unsupported size of TX queue: %d is not a power of 2.",
1101                         nb_desc);
1102                 return -EINVAL;
1103         }
1104
1105         if (nb_desc > adapter->rx_ring_size) {
1106                 RTE_LOG(ERR, PMD,
1107                         "Unsupported size of RX queue (max size: %d)\n",
1108                         adapter->rx_ring_size);
1109                 return -EINVAL;
1110         }
1111
1112         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1113
1114         ctx.qid = ena_qid;
1115         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1116         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1117         ctx.msix_vector = -1; /* admin interrupts not used */
1118         ctx.queue_size = adapter->rx_ring_size;
1119         ctx.numa_node = ena_cpu_to_node(queue_idx);
1120
1121         rc = ena_com_create_io_queue(ena_dev, &ctx);
1122         if (rc)
1123                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1124                         queue_idx, rc);
1125
1126         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1127         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1128
1129         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1130                                      &rxq->ena_com_io_sq,
1131                                      &rxq->ena_com_io_cq);
1132         if (rc) {
1133                 RTE_LOG(ERR, PMD,
1134                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1135                         queue_idx, rc);
1136                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1137         }
1138
1139         rxq->port_id = dev->data->port_id;
1140         rxq->next_to_clean = 0;
1141         rxq->next_to_use = 0;
1142         rxq->ring_size = nb_desc;
1143         rxq->mb_pool = mp;
1144
1145         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1146                                           sizeof(struct rte_mbuf *) * nb_desc,
1147                                           RTE_CACHE_LINE_SIZE);
1148         if (!rxq->rx_buffer_info) {
1149                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1150                 return -ENOMEM;
1151         }
1152
1153         /* Store pointer to this queue in upper layer */
1154         rxq->configured = 1;
1155         dev->data->rx_queues[queue_idx] = rxq;
1156
1157         return rc;
1158 }
1159
1160 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1161 {
1162         unsigned int i;
1163         int rc;
1164         uint16_t ring_size = rxq->ring_size;
1165         uint16_t ring_mask = ring_size - 1;
1166         uint16_t next_to_use = rxq->next_to_use;
1167         uint16_t in_use;
1168         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1169
1170         if (unlikely(!count))
1171                 return 0;
1172
1173         in_use = rxq->next_to_use - rxq->next_to_clean;
1174         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1175
1176         count = RTE_MIN(count,
1177                         (uint16_t)(ring_size - (next_to_use & ring_mask)));
1178
1179         /* get resources for incoming packets */
1180         rc = rte_mempool_get_bulk(rxq->mb_pool,
1181                                   (void **)(&mbufs[next_to_use & ring_mask]),
1182                                   count);
1183         if (unlikely(rc < 0)) {
1184                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1185                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1186                 return 0;
1187         }
1188
1189         for (i = 0; i < count; i++) {
1190                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1191                 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1192                 struct ena_com_buf ebuf;
1193
1194                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1195                 /* prepare physical address for DMA transaction */
1196                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1197                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1198                 /* pass resource to device */
1199                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1200                                                 &ebuf, next_to_use_masked);
1201                 if (unlikely(rc)) {
1202                         rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1203                                              count - i);
1204                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1205                         break;
1206                 }
1207                 next_to_use++;
1208         }
1209
1210         /* When we submitted free recources to device... */
1211         if (i > 0) {
1212                 /* ...let HW know that it can fill buffers with data */
1213                 rte_wmb();
1214                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1215
1216                 rxq->next_to_use = next_to_use;
1217         }
1218
1219         return i;
1220 }
1221
1222 static int ena_device_init(struct ena_com_dev *ena_dev,
1223                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1224 {
1225         int rc;
1226         bool readless_supported;
1227
1228         /* Initialize mmio registers */
1229         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1230         if (rc) {
1231                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1232                 return rc;
1233         }
1234
1235         /* The PCIe configuration space revision id indicate if mmio reg
1236          * read is disabled.
1237          */
1238         readless_supported =
1239                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1240                                & ENA_MMIO_DISABLE_REG_READ);
1241         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1242
1243         /* reset device */
1244         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1245         if (rc) {
1246                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1247                 goto err_mmio_read_less;
1248         }
1249
1250         /* check FW version */
1251         rc = ena_com_validate_version(ena_dev);
1252         if (rc) {
1253                 RTE_LOG(ERR, PMD, "device version is too low\n");
1254                 goto err_mmio_read_less;
1255         }
1256
1257         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1258
1259         /* ENA device administration layer init */
1260         rc = ena_com_admin_init(ena_dev, &empty_aenq_handlers, true);
1261         if (rc) {
1262                 RTE_LOG(ERR, PMD,
1263                         "cannot initialize ena admin queue with device\n");
1264                 goto err_mmio_read_less;
1265         }
1266
1267         /* To enable the msix interrupts the driver needs to know the number
1268          * of queues. So the driver uses polling mode to retrieve this
1269          * information.
1270          */
1271         ena_com_set_admin_polling_mode(ena_dev, true);
1272
1273         ena_config_host_info(ena_dev);
1274
1275         /* Get Device Attributes and features */
1276         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1277         if (rc) {
1278                 RTE_LOG(ERR, PMD,
1279                         "cannot get attribute for ena device rc= %d\n", rc);
1280                 goto err_admin_init;
1281         }
1282
1283         return 0;
1284
1285 err_admin_init:
1286         ena_com_admin_destroy(ena_dev);
1287
1288 err_mmio_read_less:
1289         ena_com_mmio_reg_read_request_destroy(ena_dev);
1290
1291         return rc;
1292 }
1293
1294 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1295 {
1296         struct rte_pci_device *pci_dev;
1297         struct ena_adapter *adapter =
1298                 (struct ena_adapter *)(eth_dev->data->dev_private);
1299         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1300         struct ena_com_dev_get_features_ctx get_feat_ctx;
1301         int queue_size, rc;
1302
1303         static int adapters_found;
1304
1305         memset(adapter, 0, sizeof(struct ena_adapter));
1306         ena_dev = &adapter->ena_dev;
1307
1308         eth_dev->dev_ops = &ena_dev_ops;
1309         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1310         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1311         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1312         adapter->rte_eth_dev_data = eth_dev->data;
1313         adapter->rte_dev = eth_dev;
1314
1315         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1316                 return 0;
1317
1318         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1319         adapter->pdev = pci_dev;
1320
1321         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1322                      pci_dev->addr.domain,
1323                      pci_dev->addr.bus,
1324                      pci_dev->addr.devid,
1325                      pci_dev->addr.function);
1326
1327         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1328         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1329
1330         if (!adapter->regs) {
1331                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1332                              ENA_REGS_BAR);
1333                 return -ENXIO;
1334         }
1335
1336         ena_dev->reg_bar = adapter->regs;
1337         ena_dev->dmadev = adapter->pdev;
1338
1339         adapter->id_number = adapters_found;
1340
1341         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1342                  adapter->id_number);
1343
1344         /* device specific initialization routine */
1345         rc = ena_device_init(ena_dev, &get_feat_ctx);
1346         if (rc) {
1347                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1348                 return -1;
1349         }
1350
1351         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1352         adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1353
1354         queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1355         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1356                 return -EFAULT;
1357
1358         adapter->tx_ring_size = queue_size;
1359         adapter->rx_ring_size = queue_size;
1360
1361         /* prepare ring structures */
1362         ena_init_rings(adapter);
1363
1364         ena_config_debug_area(adapter);
1365
1366         /* Set max MTU for this device */
1367         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1368
1369         /* set device support for TSO */
1370         adapter->tso4_supported = get_feat_ctx.offload.tx &
1371                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1372
1373         /* Copy MAC address and point DPDK to it */
1374         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1375         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1376                         (struct ether_addr *)adapter->mac_addr);
1377
1378         adapter->drv_stats = rte_zmalloc("adapter stats",
1379                                          sizeof(*adapter->drv_stats),
1380                                          RTE_CACHE_LINE_SIZE);
1381         if (!adapter->drv_stats) {
1382                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1383                 return -ENOMEM;
1384         }
1385
1386         adapters_found++;
1387         adapter->state = ENA_ADAPTER_STATE_INIT;
1388
1389         return 0;
1390 }
1391
1392 static int ena_dev_configure(struct rte_eth_dev *dev)
1393 {
1394         struct ena_adapter *adapter =
1395                 (struct ena_adapter *)(dev->data->dev_private);
1396
1397         if (!(adapter->state == ENA_ADAPTER_STATE_INIT ||
1398               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
1399                 PMD_INIT_LOG(ERR, "Illegal adapter state: %d",
1400                              adapter->state);
1401                 return -1;
1402         }
1403
1404         switch (adapter->state) {
1405         case ENA_ADAPTER_STATE_INIT:
1406         case ENA_ADAPTER_STATE_STOPPED:
1407                 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1408                 break;
1409         case ENA_ADAPTER_STATE_CONFIG:
1410                 RTE_LOG(WARNING, PMD,
1411                         "Ivalid driver state while trying to configure device\n");
1412                 break;
1413         default:
1414                 break;
1415         }
1416
1417         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1418         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1419         return 0;
1420 }
1421
1422 static void ena_init_rings(struct ena_adapter *adapter)
1423 {
1424         int i;
1425
1426         for (i = 0; i < adapter->num_queues; i++) {
1427                 struct ena_ring *ring = &adapter->tx_ring[i];
1428
1429                 ring->configured = 0;
1430                 ring->type = ENA_RING_TYPE_TX;
1431                 ring->adapter = adapter;
1432                 ring->id = i;
1433                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1434                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1435         }
1436
1437         for (i = 0; i < adapter->num_queues; i++) {
1438                 struct ena_ring *ring = &adapter->rx_ring[i];
1439
1440                 ring->configured = 0;
1441                 ring->type = ENA_RING_TYPE_RX;
1442                 ring->adapter = adapter;
1443                 ring->id = i;
1444         }
1445 }
1446
1447 static void ena_infos_get(struct rte_eth_dev *dev,
1448                           struct rte_eth_dev_info *dev_info)
1449 {
1450         struct ena_adapter *adapter;
1451         struct ena_com_dev *ena_dev;
1452         struct ena_com_dev_get_features_ctx feat;
1453         uint64_t rx_feat = 0, tx_feat = 0;
1454         int rc = 0;
1455
1456         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1457         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1458         adapter = (struct ena_adapter *)(dev->data->dev_private);
1459
1460         ena_dev = &adapter->ena_dev;
1461         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1462
1463         dev_info->speed_capa =
1464                         ETH_LINK_SPEED_1G   |
1465                         ETH_LINK_SPEED_2_5G |
1466                         ETH_LINK_SPEED_5G   |
1467                         ETH_LINK_SPEED_10G  |
1468                         ETH_LINK_SPEED_25G  |
1469                         ETH_LINK_SPEED_40G  |
1470                         ETH_LINK_SPEED_50G  |
1471                         ETH_LINK_SPEED_100G;
1472
1473         /* Get supported features from HW */
1474         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1475         if (unlikely(rc)) {
1476                 RTE_LOG(ERR, PMD,
1477                         "Cannot get attribute for ena device rc= %d\n", rc);
1478                 return;
1479         }
1480
1481         /* Set Tx & Rx features available for device */
1482         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1483                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1484
1485         if (feat.offload.tx &
1486             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1487                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1488                         DEV_TX_OFFLOAD_UDP_CKSUM |
1489                         DEV_TX_OFFLOAD_TCP_CKSUM;
1490
1491         if (feat.offload.rx_supported &
1492             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1493                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1494                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1495                         DEV_RX_OFFLOAD_TCP_CKSUM;
1496
1497         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1498
1499         /* Inform framework about available features */
1500         dev_info->rx_offload_capa = rx_feat;
1501         dev_info->rx_queue_offload_capa = rx_feat;
1502         dev_info->tx_offload_capa = tx_feat;
1503         dev_info->tx_queue_offload_capa = tx_feat;
1504
1505         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1506         dev_info->max_rx_pktlen  = adapter->max_mtu;
1507         dev_info->max_mac_addrs = 1;
1508
1509         dev_info->max_rx_queues = adapter->num_queues;
1510         dev_info->max_tx_queues = adapter->num_queues;
1511         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1512
1513         adapter->tx_supported_offloads = tx_feat;
1514         adapter->rx_supported_offloads = rx_feat;
1515 }
1516
1517 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1518                                   uint16_t nb_pkts)
1519 {
1520         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1521         unsigned int ring_size = rx_ring->ring_size;
1522         unsigned int ring_mask = ring_size - 1;
1523         uint16_t next_to_clean = rx_ring->next_to_clean;
1524         uint16_t desc_in_use = 0;
1525         unsigned int recv_idx = 0;
1526         struct rte_mbuf *mbuf = NULL;
1527         struct rte_mbuf *mbuf_head = NULL;
1528         struct rte_mbuf *mbuf_prev = NULL;
1529         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1530         unsigned int completed;
1531
1532         struct ena_com_rx_ctx ena_rx_ctx;
1533         int rc = 0;
1534
1535         /* Check adapter state */
1536         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1537                 RTE_LOG(ALERT, PMD,
1538                         "Trying to receive pkts while device is NOT running\n");
1539                 return 0;
1540         }
1541
1542         desc_in_use = rx_ring->next_to_use - next_to_clean;
1543         if (unlikely(nb_pkts > desc_in_use))
1544                 nb_pkts = desc_in_use;
1545
1546         for (completed = 0; completed < nb_pkts; completed++) {
1547                 int segments = 0;
1548
1549                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1550                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1551                 ena_rx_ctx.descs = 0;
1552                 /* receive packet context */
1553                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1554                                     rx_ring->ena_com_io_sq,
1555                                     &ena_rx_ctx);
1556                 if (unlikely(rc)) {
1557                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1558                         return 0;
1559                 }
1560
1561                 if (unlikely(ena_rx_ctx.descs == 0))
1562                         break;
1563
1564                 while (segments < ena_rx_ctx.descs) {
1565                         mbuf = rx_buff_info[next_to_clean & ring_mask];
1566                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1567                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1568                         mbuf->refcnt = 1;
1569                         mbuf->next = NULL;
1570                         if (segments == 0) {
1571                                 mbuf->nb_segs = ena_rx_ctx.descs;
1572                                 mbuf->port = rx_ring->port_id;
1573                                 mbuf->pkt_len = 0;
1574                                 mbuf_head = mbuf;
1575                         } else {
1576                                 /* for multi-segment pkts create mbuf chain */
1577                                 mbuf_prev->next = mbuf;
1578                         }
1579                         mbuf_head->pkt_len += mbuf->data_len;
1580
1581                         mbuf_prev = mbuf;
1582                         segments++;
1583                         next_to_clean++;
1584                 }
1585
1586                 /* fill mbuf attributes if any */
1587                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1588                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1589
1590                 /* pass to DPDK application head mbuf */
1591                 rx_pkts[recv_idx] = mbuf_head;
1592                 recv_idx++;
1593         }
1594
1595         rx_ring->next_to_clean = next_to_clean;
1596
1597         desc_in_use = desc_in_use - completed + 1;
1598         /* Burst refill to save doorbells, memory barriers, const interval */
1599         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1600                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1601
1602         return recv_idx;
1603 }
1604
1605 static uint16_t
1606 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1607                 uint16_t nb_pkts)
1608 {
1609         int32_t ret;
1610         uint32_t i;
1611         struct rte_mbuf *m;
1612         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1613         struct ipv4_hdr *ip_hdr;
1614         uint64_t ol_flags;
1615         uint16_t frag_field;
1616
1617         for (i = 0; i != nb_pkts; i++) {
1618                 m = tx_pkts[i];
1619                 ol_flags = m->ol_flags;
1620
1621                 if (!(ol_flags & PKT_TX_IPV4))
1622                         continue;
1623
1624                 /* If there was not L2 header length specified, assume it is
1625                  * length of the ethernet header.
1626                  */
1627                 if (unlikely(m->l2_len == 0))
1628                         m->l2_len = sizeof(struct ether_hdr);
1629
1630                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1631                                                  m->l2_len);
1632                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1633
1634                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1635                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1636
1637                         /* If IPv4 header has DF flag enabled and TSO support is
1638                          * disabled, partial chcecksum should not be calculated.
1639                          */
1640                         if (!tx_ring->adapter->tso4_supported)
1641                                 continue;
1642                 }
1643
1644                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1645                                 (ol_flags & PKT_TX_L4_MASK) ==
1646                                 PKT_TX_SCTP_CKSUM) {
1647                         rte_errno = -ENOTSUP;
1648                         return i;
1649                 }
1650
1651 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1652                 ret = rte_validate_tx_offload(m);
1653                 if (ret != 0) {
1654                         rte_errno = ret;
1655                         return i;
1656                 }
1657 #endif
1658
1659                 /* In case we are supposed to TSO and have DF not set (DF=0)
1660                  * hardware must be provided with partial checksum, otherwise
1661                  * it will take care of necessary calculations.
1662                  */
1663
1664                 ret = rte_net_intel_cksum_flags_prepare(m,
1665                         ol_flags & ~PKT_TX_TCP_SEG);
1666                 if (ret != 0) {
1667                         rte_errno = ret;
1668                         return i;
1669                 }
1670         }
1671
1672         return i;
1673 }
1674
1675 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1676                                   uint16_t nb_pkts)
1677 {
1678         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1679         uint16_t next_to_use = tx_ring->next_to_use;
1680         uint16_t next_to_clean = tx_ring->next_to_clean;
1681         struct rte_mbuf *mbuf;
1682         unsigned int ring_size = tx_ring->ring_size;
1683         unsigned int ring_mask = ring_size - 1;
1684         struct ena_com_tx_ctx ena_tx_ctx;
1685         struct ena_tx_buffer *tx_info;
1686         struct ena_com_buf *ebuf;
1687         uint16_t rc, req_id, total_tx_descs = 0;
1688         uint16_t sent_idx = 0, empty_tx_reqs;
1689         int nb_hw_desc;
1690
1691         /* Check adapter state */
1692         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1693                 RTE_LOG(ALERT, PMD,
1694                         "Trying to xmit pkts while device is NOT running\n");
1695                 return 0;
1696         }
1697
1698         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1699         if (nb_pkts > empty_tx_reqs)
1700                 nb_pkts = empty_tx_reqs;
1701
1702         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1703                 mbuf = tx_pkts[sent_idx];
1704
1705                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1706                 tx_info = &tx_ring->tx_buffer_info[req_id];
1707                 tx_info->mbuf = mbuf;
1708                 tx_info->num_of_bufs = 0;
1709                 ebuf = tx_info->bufs;
1710
1711                 /* Prepare TX context */
1712                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1713                 memset(&ena_tx_ctx.ena_meta, 0x0,
1714                        sizeof(struct ena_com_tx_meta));
1715                 ena_tx_ctx.ena_bufs = ebuf;
1716                 ena_tx_ctx.req_id = req_id;
1717                 if (tx_ring->tx_mem_queue_type ==
1718                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1719                         /* prepare the push buffer with
1720                          * virtual address of the data
1721                          */
1722                         ena_tx_ctx.header_len =
1723                                 RTE_MIN(mbuf->data_len,
1724                                         tx_ring->tx_max_header_size);
1725                         ena_tx_ctx.push_header =
1726                                 (void *)((char *)mbuf->buf_addr +
1727                                          mbuf->data_off);
1728                 } /* there's no else as we take advantage of memset zeroing */
1729
1730                 /* Set TX offloads flags, if applicable */
1731                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
1732
1733                 if (unlikely(mbuf->ol_flags &
1734                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1735                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1736
1737                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1738
1739                 /* Process first segment taking into
1740                  * consideration pushed header
1741                  */
1742                 if (mbuf->data_len > ena_tx_ctx.header_len) {
1743                         ebuf->paddr = mbuf->buf_iova +
1744                                       mbuf->data_off +
1745                                       ena_tx_ctx.header_len;
1746                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1747                         ebuf++;
1748                         tx_info->num_of_bufs++;
1749                 }
1750
1751                 while ((mbuf = mbuf->next) != NULL) {
1752                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
1753                         ebuf->len = mbuf->data_len;
1754                         ebuf++;
1755                         tx_info->num_of_bufs++;
1756                 }
1757
1758                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1759
1760                 /* Write data to device */
1761                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1762                                         &ena_tx_ctx, &nb_hw_desc);
1763                 if (unlikely(rc))
1764                         break;
1765
1766                 tx_info->tx_descs = nb_hw_desc;
1767
1768                 next_to_use++;
1769         }
1770
1771         /* If there are ready packets to be xmitted... */
1772         if (sent_idx > 0) {
1773                 /* ...let HW do its best :-) */
1774                 rte_wmb();
1775                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1776
1777                 tx_ring->next_to_use = next_to_use;
1778         }
1779
1780         /* Clear complete packets  */
1781         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1782                 /* Get Tx info & store how many descs were processed  */
1783                 tx_info = &tx_ring->tx_buffer_info[req_id];
1784                 total_tx_descs += tx_info->tx_descs;
1785
1786                 /* Free whole mbuf chain  */
1787                 mbuf = tx_info->mbuf;
1788                 rte_pktmbuf_free(mbuf);
1789                 tx_info->mbuf = NULL;
1790
1791                 /* Put back descriptor to the ring for reuse */
1792                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
1793                 next_to_clean++;
1794
1795                 /* If too many descs to clean, leave it for another run */
1796                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1797                         break;
1798         }
1799
1800         if (total_tx_descs > 0) {
1801                 /* acknowledge completion of sent packets */
1802                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1803                 tx_ring->next_to_clean = next_to_clean;
1804         }
1805
1806         return sent_idx;
1807 }
1808
1809 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1810         struct rte_pci_device *pci_dev)
1811 {
1812         return rte_eth_dev_pci_generic_probe(pci_dev,
1813                 sizeof(struct ena_adapter), eth_ena_dev_init);
1814 }
1815
1816 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
1817 {
1818         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1819 }
1820
1821 static struct rte_pci_driver rte_ena_pmd = {
1822         .id_table = pci_id_ena_map,
1823         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1824         .probe = eth_ena_pci_probe,
1825         .remove = eth_ena_pci_remove,
1826 };
1827
1828 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
1829 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
1830 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
1831
1832 RTE_INIT(ena_init_log);
1833 static void
1834 ena_init_log(void)
1835 {
1836         ena_logtype_init = rte_log_register("pmd.net.ena.init");
1837         if (ena_logtype_init >= 0)
1838                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
1839         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
1840         if (ena_logtype_driver >= 0)
1841                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
1842 }
1843
1844 /******************************************************************************
1845  ******************************** AENQ Handlers *******************************
1846  *****************************************************************************/
1847 /**
1848  * This handler will called for unknown event group or unimplemented handlers
1849  **/
1850 static void unimplemented_aenq_handler(__rte_unused void *data,
1851                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
1852 {
1853         // Unimplemented handler
1854 }
1855
1856 static struct ena_aenq_handlers empty_aenq_handlers = {
1857         .handlers = {
1858                 [ENA_ADMIN_LINK_CHANGE] = unimplemented_aenq_handler,
1859                 [ENA_ADMIN_NOTIFICATION] = unimplemented_aenq_handler,
1860                 [ENA_ADMIN_KEEP_ALIVE] = unimplemented_aenq_handler
1861         },
1862         .unimplemented_handler = unimplemented_aenq_handler
1863 };