drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 0
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 enum ethtool_stringset {
  89         ETH_SS_TEST             = 0,
  90         ETH_SS_STATS,
  91 };
  92
  93 struct ena_stats {
  94         char name[ETH_GSTRING_LEN];
  95         int stat_offset;
  96 };
  97
  98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
  99         .name = #stat, \
 100         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 101 }
 102
 103 #define ENA_STAT_ENTRY(stat, stat_type) { \
 104         .name = #stat, \
 105         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 106 }
 107
 108 #define ENA_STAT_RX_ENTRY(stat) \
 109         ENA_STAT_ENTRY(stat, rx)
 110
 111 #define ENA_STAT_TX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, tx)
 113
 114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, dev)
 116
 117 /*
 118  * Each rte_memzone should have unique name.
 119  * To satisfy it, count number of allocation and add it to name.
 120  */
 121 uint32_t ena_alloc_cnt;
 122
 123 static const struct ena_stats ena_stats_global_strings[] = {
 124         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 125         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 126         ENA_STAT_GLOBAL_ENTRY(io_resume),
 127         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 128         ENA_STAT_GLOBAL_ENTRY(interface_up),
 129         ENA_STAT_GLOBAL_ENTRY(interface_down),
 130         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 131 };
 132
 133 static const struct ena_stats ena_stats_tx_strings[] = {
 134         ENA_STAT_TX_ENTRY(cnt),
 135         ENA_STAT_TX_ENTRY(bytes),
 136         ENA_STAT_TX_ENTRY(queue_stop),
 137         ENA_STAT_TX_ENTRY(queue_wakeup),
 138         ENA_STAT_TX_ENTRY(dma_mapping_err),
 139         ENA_STAT_TX_ENTRY(linearize),
 140         ENA_STAT_TX_ENTRY(linearize_failed),
 141         ENA_STAT_TX_ENTRY(tx_poll),
 142         ENA_STAT_TX_ENTRY(doorbells),
 143         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 144         ENA_STAT_TX_ENTRY(missing_tx_comp),
 145         ENA_STAT_TX_ENTRY(bad_req_id),
 146 };
 147
 148 static const struct ena_stats ena_stats_rx_strings[] = {
 149         ENA_STAT_RX_ENTRY(cnt),
 150         ENA_STAT_RX_ENTRY(bytes),
 151         ENA_STAT_RX_ENTRY(refil_partial),
 152         ENA_STAT_RX_ENTRY(bad_csum),
 153         ENA_STAT_RX_ENTRY(page_alloc_fail),
 154         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 155         ENA_STAT_RX_ENTRY(dma_mapping_err),
 156         ENA_STAT_RX_ENTRY(bad_desc_num),
 157         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 158 };
 159
 160 static const struct ena_stats ena_stats_ena_com_strings[] = {
 161         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 162         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 163         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 164         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 165         ENA_STAT_ENA_COM_ENTRY(no_completion),
 166 };
 167
 168 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 169 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 170 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 171 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 172
 173 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 174                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 175                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 176                         DEV_TX_OFFLOAD_TCP_TSO)
 177 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 178                        PKT_TX_IP_CKSUM |\
 179                        PKT_TX_TCP_SEG)
 180
 181 /** Vendor ID used by Amazon devices */
 182 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 183 /** Amazon devices */
 184 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 185 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 186
 187 #define ENA_TX_OFFLOAD_MASK     (\
 188         PKT_TX_L4_MASK |         \
 189         PKT_TX_IP_CKSUM |        \
 190         PKT_TX_TCP_SEG)
 191
 192 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 193         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 194
 195 int ena_logtype_init;
 196 int ena_logtype_driver;
 197
 198 static const struct rte_pci_id pci_id_ena_map[] = {
 199         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 200         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 201         { .device_id = 0 },
 202 };
 203
 204 static struct ena_aenq_handlers aenq_handlers;
 205
 206 static int ena_device_init(struct ena_com_dev *ena_dev,
 207                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 208                            bool *wd_state);
 209 static int ena_dev_configure(struct rte_eth_dev *dev);
 210 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 211                                   uint16_t nb_pkts);
 212 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 213                 uint16_t nb_pkts);
 214 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 215                               uint16_t nb_desc, unsigned int socket_id,
 216                               const struct rte_eth_txconf *tx_conf);
 217 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 218                               uint16_t nb_desc, unsigned int socket_id,
 219                               const struct rte_eth_rxconf *rx_conf,
 220                               struct rte_mempool *mp);
 221 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 222                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 223 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 224 static void ena_init_rings(struct ena_adapter *adapter);
 225 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 226 static int ena_start(struct rte_eth_dev *dev);
 227 static void ena_stop(struct rte_eth_dev *dev);
 228 static void ena_close(struct rte_eth_dev *dev);
 229 static int ena_dev_reset(struct rte_eth_dev *dev);
 230 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 231 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 232 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 233 static void ena_rx_queue_release(void *queue);
 234 static void ena_tx_queue_release(void *queue);
 235 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 236 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 237 static int ena_link_update(struct rte_eth_dev *dev,
 238                            int wait_to_complete);
 239 static int ena_queue_restart(struct ena_ring *ring);
 240 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 241                                  enum ena_ring_type ring_type);
 242 static void ena_stats_restart(struct rte_eth_dev *dev);
 243 static void ena_infos_get(struct rte_eth_dev *dev,
 244                           struct rte_eth_dev_info *dev_info);
 245 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 246                                struct rte_eth_rss_reta_entry64 *reta_conf,
 247                                uint16_t reta_size);
 248 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 249                               struct rte_eth_rss_reta_entry64 *reta_conf,
 250                               uint16_t reta_size);
 251 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 252 static void ena_interrupt_handler_rte(void *cb_arg);
 253 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 254
 255 static const struct eth_dev_ops ena_dev_ops = {
 256         .dev_configure        = ena_dev_configure,
 257         .dev_infos_get        = ena_infos_get,
 258         .rx_queue_setup       = ena_rx_queue_setup,
 259         .tx_queue_setup       = ena_tx_queue_setup,
 260         .dev_start            = ena_start,
 261         .dev_stop             = ena_stop,
 262         .link_update          = ena_link_update,
 263         .stats_get            = ena_stats_get,
 264         .mtu_set              = ena_mtu_set,
 265         .rx_queue_release     = ena_rx_queue_release,
 266         .tx_queue_release     = ena_tx_queue_release,
 267         .dev_close            = ena_close,
 268         .dev_reset            = ena_dev_reset,
 269         .reta_update          = ena_rss_reta_update,
 270         .reta_query           = ena_rss_reta_query,
 271 };
 272
 273 #define NUMA_NO_NODE    SOCKET_ID_ANY
 274
 275 static inline int ena_cpu_to_node(int cpu)
 276 {
 277         struct rte_config *config = rte_eal_get_configuration();
 278         struct rte_fbarray *arr = &config->mem_config->memzones;
 279         const struct rte_memzone *mz;
 280
 281         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 282                 return NUMA_NO_NODE;
 283
 284         mz = rte_fbarray_get(arr, cpu);
 285
 286         return mz->socket_id;
 287 }
 288
 289 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 290                                        struct ena_com_rx_ctx *ena_rx_ctx)
 291 {
 292         uint64_t ol_flags = 0;
 293         uint32_t packet_type = 0;
 294
 295         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 296                 packet_type |= RTE_PTYPE_L4_TCP;
 297         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 298                 packet_type |= RTE_PTYPE_L4_UDP;
 299
 300         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 301                 packet_type |= RTE_PTYPE_L3_IPV4;
 302         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 303                 packet_type |= RTE_PTYPE_L3_IPV6;
 304
 305         if (unlikely(ena_rx_ctx->l4_csum_err))
 306                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 307         if (unlikely(ena_rx_ctx->l3_csum_err))
 308                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 309
 310         mbuf->ol_flags = ol_flags;
 311         mbuf->packet_type = packet_type;
 312 }
 313
 314 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 315                                        struct ena_com_tx_ctx *ena_tx_ctx,
 316                                        uint64_t queue_offloads)
 317 {
 318         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 319
 320         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 321             (queue_offloads & QUEUE_OFFLOADS)) {
 322                 /* check if TSO is required */
 323                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 324                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 325                         ena_tx_ctx->tso_enable = true;
 326
 327                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 328                 }
 329
 330                 /* check if L3 checksum is needed */
 331                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 332                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 333                         ena_tx_ctx->l3_csum_enable = true;
 334
 335                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 336                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 337                 } else {
 338                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 339
 340                         /* set don't fragment (DF) flag */
 341                         if (mbuf->packet_type &
 342                                 (RTE_PTYPE_L4_NONFRAG
 343                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 344                                 ena_tx_ctx->df = true;
 345                 }
 346
 347                 /* check if L4 checksum is needed */
 348                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 349                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 350                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 351                         ena_tx_ctx->l4_csum_enable = true;
 352                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 353                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 354                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 355                         ena_tx_ctx->l4_csum_enable = true;
 356                 } else {
 357                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 358                         ena_tx_ctx->l4_csum_enable = false;
 359                 }
 360
 361                 ena_meta->mss = mbuf->tso_segsz;
 362                 ena_meta->l3_hdr_len = mbuf->l3_len;
 363                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 364
 365                 ena_tx_ctx->meta_valid = true;
 366         } else {
 367                 ena_tx_ctx->meta_valid = false;
 368         }
 369 }
 370
 371 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 372 {
 373         if (likely(req_id < rx_ring->ring_size))
 374                 return 0;
 375
 376         RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
 377
 378         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 379         rx_ring->adapter->trigger_reset = true;
 380
 381         return -EFAULT;
 382 }
 383
 384 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 385 {
 386         struct ena_admin_host_info *host_info;
 387         int rc;
 388
 389         /* Allocate only the host info */
 390         rc = ena_com_allocate_host_info(ena_dev);
 391         if (rc) {
 392                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 393                 return;
 394         }
 395
 396         host_info = ena_dev->host_attr.host_info;
 397
 398         host_info->os_type = ENA_ADMIN_OS_DPDK;
 399         host_info->kernel_ver = RTE_VERSION;
 400         snprintf((char *)host_info->kernel_ver_str,
 401                  sizeof(host_info->kernel_ver_str),
 402                  "%s", rte_version());
 403         host_info->os_dist = RTE_VERSION;
 404         snprintf((char *)host_info->os_dist_str,
 405                  sizeof(host_info->os_dist_str),
 406                  "%s", rte_version());
 407         host_info->driver_version =
 408                 (DRV_MODULE_VER_MAJOR) |
 409                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 410                 (DRV_MODULE_VER_SUBMINOR <<
 411                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 412
 413         rc = ena_com_set_host_attributes(ena_dev);
 414         if (rc) {
 415                 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 416                 if (rc != -ENA_COM_UNSUPPORTED)
 417                         goto err;
 418         }
 419
 420         return;
 421
 422 err:
 423         ena_com_delete_host_info(ena_dev);
 424 }
 425
 426 static int
 427 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 428 {
 429         if (sset != ETH_SS_STATS)
 430                 return -EOPNOTSUPP;
 431
 432          /* Workaround for clang:
 433          * touch internal structures to prevent
 434          * compiler error
 435          */
 436         ENA_TOUCH(ena_stats_global_strings);
 437         ENA_TOUCH(ena_stats_tx_strings);
 438         ENA_TOUCH(ena_stats_rx_strings);
 439         ENA_TOUCH(ena_stats_ena_com_strings);
 440
 441         return  dev->data->nb_tx_queues *
 442                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 443                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 444 }
 445
 446 static void ena_config_debug_area(struct ena_adapter *adapter)
 447 {
 448         u32 debug_area_size;
 449         int rc, ss_count;
 450
 451         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 452         if (ss_count <= 0) {
 453                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 454                 return;
 455         }
 456
 457         /* allocate 32 bytes for each string and 64bit for the value */
 458         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 459
 460         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 461         if (rc) {
 462                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 463                 return;
 464         }
 465
 466         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 467         if (rc) {
 468                 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 469                 if (rc != -ENA_COM_UNSUPPORTED)
 470                         goto err;
 471         }
 472
 473         return;
 474 err:
 475         ena_com_delete_debug_area(&adapter->ena_dev);
 476 }
 477
 478 static void ena_close(struct rte_eth_dev *dev)
 479 {
 480         struct ena_adapter *adapter =
 481                 (struct ena_adapter *)(dev->data->dev_private);
 482
 483         ena_stop(dev);
 484         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 485
 486         ena_rx_queue_release_all(dev);
 487         ena_tx_queue_release_all(dev);
 488 }
 489
 490 static int
 491 ena_dev_reset(struct rte_eth_dev *dev)
 492 {
 493         struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
 494         struct rte_eth_dev *eth_dev;
 495         struct rte_pci_device *pci_dev;
 496         struct rte_intr_handle *intr_handle;
 497         struct ena_com_dev *ena_dev;
 498         struct ena_com_dev_get_features_ctx get_feat_ctx;
 499         struct ena_adapter *adapter;
 500         int nb_queues;
 501         int rc, i;
 502         bool wd_state;
 503
 504         adapter = (struct ena_adapter *)(dev->data->dev_private);
 505         ena_dev = &adapter->ena_dev;
 506         eth_dev = adapter->rte_dev;
 507         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 508         intr_handle = &pci_dev->intr_handle;
 509         nb_queues = eth_dev->data->nb_rx_queues;
 510
 511         ena_com_set_admin_running_state(ena_dev, false);
 512
 513         ena_com_dev_reset(ena_dev, adapter->reset_reason);
 514
 515         for (i = 0; i < nb_queues; i++)
 516                 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
 517
 518         ena_rx_queue_release_all(eth_dev);
 519         ena_tx_queue_release_all(eth_dev);
 520
 521         rte_intr_disable(intr_handle);
 522
 523         ena_com_abort_admin_commands(ena_dev);
 524         ena_com_wait_for_abort_completion(ena_dev);
 525         ena_com_admin_destroy(ena_dev);
 526         ena_com_mmio_reg_read_request_destroy(ena_dev);
 527
 528         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
 529         if (rc) {
 530                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 531                 return rc;
 532         }
 533         adapter->wd_state = wd_state;
 534
 535         rte_intr_enable(intr_handle);
 536         ena_com_set_admin_polling_mode(ena_dev, false);
 537         ena_com_admin_aenq_enable(ena_dev);
 538
 539         for (i = 0; i < nb_queues; ++i)
 540                 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring_size, 0, NULL,
 541                         mb_pool_rx[i]);
 542
 543         for (i = 0; i < nb_queues; ++i)
 544                 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring_size, 0, NULL);
 545
 546         adapter->trigger_reset = false;
 547
 548         return 0;
 549 }
 550
 551 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 552                                struct rte_eth_rss_reta_entry64 *reta_conf,
 553                                uint16_t reta_size)
 554 {
 555         struct ena_adapter *adapter =
 556                 (struct ena_adapter *)(dev->data->dev_private);
 557         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 558         int ret, i;
 559         u16 entry_value;
 560         int conf_idx;
 561         int idx;
 562
 563         if ((reta_size == 0) || (reta_conf == NULL))
 564                 return -EINVAL;
 565
 566         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 567                 RTE_LOG(WARNING, PMD,
 568                         "indirection table %d is bigger than supported (%d)\n",
 569                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 570                 ret = -EINVAL;
 571                 goto err;
 572         }
 573
 574         for (i = 0 ; i < reta_size ; i++) {
 575                 /* each reta_conf is for 64 entries.
 576                  * to support 128 we use 2 conf of 64
 577                  */
 578                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 579                 idx = i % RTE_RETA_GROUP_SIZE;
 580                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 581                         entry_value =
 582                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 583                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 584                                                                 i,
 585                                                                 entry_value);
 586                         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 587                                 RTE_LOG(ERR, PMD,
 588                                         "Cannot fill indirect table\n");
 589                                 ret = -ENOTSUP;
 590                                 goto err;
 591                         }
 592                 }
 593         }
 594
 595         ret = ena_com_indirect_table_set(ena_dev);
 596         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 597                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 598                 ret = -ENOTSUP;
 599                 goto err;
 600         }
 601
 602         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 603                 __func__, reta_size, adapter->rte_dev->data->port_id);
 604 err:
 605         return ret;
 606 }
 607
 608 /* Query redirection table. */
 609 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 610                               struct rte_eth_rss_reta_entry64 *reta_conf,
 611                               uint16_t reta_size)
 612 {
 613         struct ena_adapter *adapter =
 614                 (struct ena_adapter *)(dev->data->dev_private);
 615         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 616         int ret;
 617         int i;
 618         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 619         int reta_conf_idx;
 620         int reta_idx;
 621
 622         if (reta_size == 0 || reta_conf == NULL ||
 623             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 624                 return -EINVAL;
 625
 626         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 627         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 628                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 629                 ret = -ENOTSUP;
 630                 goto err;
 631         }
 632
 633         for (i = 0 ; i < reta_size ; i++) {
 634                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 635                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 636                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 637                         reta_conf[reta_conf_idx].reta[reta_idx] =
 638                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 639         }
 640 err:
 641         return ret;
 642 }
 643
 644 static int ena_rss_init_default(struct ena_adapter *adapter)
 645 {
 646         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 647         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 648         int rc, i;
 649         u32 val;
 650
 651         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 652         if (unlikely(rc)) {
 653                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 654                 goto err_rss_init;
 655         }
 656
 657         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 658                 val = i % nb_rx_queues;
 659                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 660                                                        ENA_IO_RXQ_IDX(val));
 661                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 662                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 663                         goto err_fill_indir;
 664                 }
 665         }
 666
 667         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 668                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 669         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 670                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 671                 goto err_fill_indir;
 672         }
 673
 674         rc = ena_com_set_default_hash_ctrl(ena_dev);
 675         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 676                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 677                 goto err_fill_indir;
 678         }
 679
 680         rc = ena_com_indirect_table_set(ena_dev);
 681         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 682                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 683                 goto err_fill_indir;
 684         }
 685         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 686                 adapter->rte_dev->data->port_id);
 687
 688         return 0;
 689
 690 err_fill_indir:
 691         ena_com_rss_destroy(ena_dev);
 692 err_rss_init:
 693
 694         return rc;
 695 }
 696
 697 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 698 {
 699         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 700         int nb_queues = dev->data->nb_rx_queues;
 701         int i;
 702
 703         for (i = 0; i < nb_queues; i++)
 704                 ena_rx_queue_release(queues[i]);
 705 }
 706
 707 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 708 {
 709         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 710         int nb_queues = dev->data->nb_tx_queues;
 711         int i;
 712
 713         for (i = 0; i < nb_queues; i++)
 714                 ena_tx_queue_release(queues[i]);
 715 }
 716
 717 static void ena_rx_queue_release(void *queue)
 718 {
 719         struct ena_ring *ring = (struct ena_ring *)queue;
 720         struct ena_adapter *adapter = ring->adapter;
 721         int ena_qid;
 722
 723         ena_assert_msg(ring->configured,
 724                        "API violation - releasing not configured queue");
 725         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 726                        "API violation");
 727
 728         /* Destroy HW queue */
 729         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 730         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 731
 732         /* Free all bufs */
 733         ena_rx_queue_release_bufs(ring);
 734
 735         /* Free ring resources */
 736         if (ring->rx_buffer_info)
 737                 rte_free(ring->rx_buffer_info);
 738         ring->rx_buffer_info = NULL;
 739
 740         if (ring->empty_rx_reqs)
 741                 rte_free(ring->empty_rx_reqs);
 742         ring->empty_rx_reqs = NULL;
 743
 744         ring->configured = 0;
 745
 746         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 747                 ring->port_id, ring->id);
 748 }
 749
 750 static void ena_tx_queue_release(void *queue)
 751 {
 752         struct ena_ring *ring = (struct ena_ring *)queue;
 753         struct ena_adapter *adapter = ring->adapter;
 754         int ena_qid;
 755
 756         ena_assert_msg(ring->configured,
 757                        "API violation. Releasing not configured queue");
 758         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 759                        "API violation");
 760
 761         /* Destroy HW queue */
 762         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 763         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 764
 765         /* Free all bufs */
 766         ena_tx_queue_release_bufs(ring);
 767
 768         /* Free ring resources */
 769         if (ring->tx_buffer_info)
 770                 rte_free(ring->tx_buffer_info);
 771
 772         if (ring->empty_tx_reqs)
 773                 rte_free(ring->empty_tx_reqs);
 774
 775         ring->empty_tx_reqs = NULL;
 776         ring->tx_buffer_info = NULL;
 777
 778         ring->configured = 0;
 779
 780         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 781                 ring->port_id, ring->id);
 782 }
 783
 784 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 785 {
 786         unsigned int ring_mask = ring->ring_size - 1;
 787
 788         while (ring->next_to_clean != ring->next_to_use) {
 789                 struct rte_mbuf *m =
 790                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 791
 792                 if (m)
 793                         rte_mbuf_raw_free(m);
 794
 795                 ring->next_to_clean++;
 796         }
 797 }
 798
 799 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 800 {
 801         unsigned int i;
 802
 803         for (i = 0; i < ring->ring_size; ++i) {
 804                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 805
 806                 if (tx_buf->mbuf)
 807                         rte_pktmbuf_free(tx_buf->mbuf);
 808
 809                 ring->next_to_clean++;
 810         }
 811 }
 812
 813 static int ena_link_update(struct rte_eth_dev *dev,
 814                            __rte_unused int wait_to_complete)
 815 {
 816         struct rte_eth_link *link = &dev->data->dev_link;
 817         struct ena_adapter *adapter;
 818
 819         adapter = (struct ena_adapter *)(dev->data->dev_private);
 820
 821         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 822         link->link_speed = ETH_SPEED_NUM_10G;
 823         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 824
 825         return 0;
 826 }
 827
 828 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 829                                  enum ena_ring_type ring_type)
 830 {
 831         struct ena_adapter *adapter =
 832                 (struct ena_adapter *)(dev->data->dev_private);
 833         struct ena_ring *queues = NULL;
 834         int nb_queues;
 835         int i = 0;
 836         int rc = 0;
 837
 838         if (ring_type == ENA_RING_TYPE_RX) {
 839                 queues = adapter->rx_ring;
 840                 nb_queues = dev->data->nb_rx_queues;
 841         } else {
 842                 queues = adapter->tx_ring;
 843                 nb_queues = dev->data->nb_tx_queues;
 844         }
 845         for (i = 0; i < nb_queues; i++) {
 846                 if (queues[i].configured) {
 847                         if (ring_type == ENA_RING_TYPE_RX) {
 848                                 ena_assert_msg(
 849                                         dev->data->rx_queues[i] == &queues[i],
 850                                         "Inconsistent state of rx queues\n");
 851                         } else {
 852                                 ena_assert_msg(
 853                                         dev->data->tx_queues[i] == &queues[i],
 854                                         "Inconsistent state of tx queues\n");
 855                         }
 856
 857                         rc = ena_queue_restart(&queues[i]);
 858
 859                         if (rc) {
 860                                 PMD_INIT_LOG(ERR,
 861                                              "failed to restart queue %d type(%d)",
 862                                              i, ring_type);
 863                                 return -1;
 864                         }
 865                 }
 866         }
 867
 868         return 0;
 869 }
 870
 871 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 872 {
 873         uint32_t max_frame_len = adapter->max_mtu;
 874
 875         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 876             DEV_RX_OFFLOAD_JUMBO_FRAME)
 877                 max_frame_len =
 878                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 879
 880         return max_frame_len;
 881 }
 882
 883 static int ena_check_valid_conf(struct ena_adapter *adapter)
 884 {
 885         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 886
 887         if (max_frame_len > adapter->max_mtu) {
 888                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
 889                 return -1;
 890         }
 891
 892         return 0;
 893 }
 894
 895 static int
 896 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 897                     u16 *max_tx_sgl_size,
 898                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 899 {
 900         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 901
 902         queue_size = RTE_MIN(queue_size,
 903                              get_feat_ctx->max_queues.max_cq_depth);
 904         queue_size = RTE_MIN(queue_size,
 905                              get_feat_ctx->max_queues.max_sq_depth);
 906
 907         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 908                 queue_size = RTE_MIN(queue_size,
 909                                      get_feat_ctx->max_queues.max_llq_depth);
 910
 911         /* Round down to power of 2 */
 912         if (!rte_is_power_of_2(queue_size))
 913                 queue_size = rte_align32pow2(queue_size >> 1);
 914
 915         if (queue_size == 0) {
 916                 PMD_INIT_LOG(ERR, "Invalid queue size");
 917                 return -EFAULT;
 918         }
 919
 920         *max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 921                 get_feat_ctx->max_queues.max_packet_tx_descs);
 922
 923         return queue_size;
 924 }
 925
 926 static void ena_stats_restart(struct rte_eth_dev *dev)
 927 {
 928         struct ena_adapter *adapter =
 929                 (struct ena_adapter *)(dev->data->dev_private);
 930
 931         rte_atomic64_init(&adapter->drv_stats->ierrors);
 932         rte_atomic64_init(&adapter->drv_stats->oerrors);
 933         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 934 }
 935
 936 static int ena_stats_get(struct rte_eth_dev *dev,
 937                           struct rte_eth_stats *stats)
 938 {
 939         struct ena_admin_basic_stats ena_stats;
 940         struct ena_adapter *adapter =
 941                 (struct ena_adapter *)(dev->data->dev_private);
 942         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 943         int rc;
 944
 945         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 946                 return -ENOTSUP;
 947
 948         memset(&ena_stats, 0, sizeof(ena_stats));
 949         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 950         if (unlikely(rc)) {
 951                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 952                 return rc;
 953         }
 954
 955         /* Set of basic statistics from ENA */
 956         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 957                                           ena_stats.rx_pkts_low);
 958         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 959                                           ena_stats.tx_pkts_low);
 960         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 961                                         ena_stats.rx_bytes_low);
 962         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 963                                         ena_stats.tx_bytes_low);
 964         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 965                                          ena_stats.rx_drops_low);
 966
 967         /* Driver related stats */
 968         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 969         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 970         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 971         return 0;
 972 }
 973
 974 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 975 {
 976         struct ena_adapter *adapter;
 977         struct ena_com_dev *ena_dev;
 978         int rc = 0;
 979
 980         ena_assert_msg(dev->data != NULL, "Uninitialized device");
 981         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
 982         adapter = (struct ena_adapter *)(dev->data->dev_private);
 983
 984         ena_dev = &adapter->ena_dev;
 985         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
 986
 987         if (mtu > ena_get_mtu_conf(adapter)) {
 988                 RTE_LOG(ERR, PMD,
 989                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
 990                         mtu, ena_get_mtu_conf(adapter));
 991                 rc = -EINVAL;
 992                 goto err;
 993         }
 994
 995         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 996         if (rc)
 997                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
 998         else
 999                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1000
1001 err:
1002         return rc;
1003 }
1004
1005 static int ena_start(struct rte_eth_dev *dev)
1006 {
1007         struct ena_adapter *adapter =
1008                 (struct ena_adapter *)(dev->data->dev_private);
1009         uint64_t ticks;
1010         int rc = 0;
1011
1012         rc = ena_check_valid_conf(adapter);
1013         if (rc)
1014                 return rc;
1015
1016         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
1017         if (rc)
1018                 return rc;
1019
1020         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
1021         if (rc)
1022                 return rc;
1023
1024         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1025             ETH_MQ_RX_RSS_FLAG) {
1026                 rc = ena_rss_init_default(adapter);
1027                 if (rc)
1028                         return rc;
1029         }
1030
1031         ena_stats_restart(dev);
1032
1033         adapter->timestamp_wd = rte_get_timer_cycles();
1034         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1035
1036         ticks = rte_get_timer_hz();
1037         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1038                         ena_timer_wd_callback, adapter);
1039
1040         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1041
1042         return 0;
1043 }
1044
1045 static void ena_stop(struct rte_eth_dev *dev)
1046 {
1047         struct ena_adapter *adapter =
1048                 (struct ena_adapter *)(dev->data->dev_private);
1049
1050         rte_timer_stop_sync(&adapter->timer_wd);
1051
1052         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1053 }
1054
1055 static int ena_queue_restart(struct ena_ring *ring)
1056 {
1057         int rc, bufs_num;
1058
1059         ena_assert_msg(ring->configured == 1,
1060                        "Trying to restart unconfigured queue\n");
1061
1062         ring->next_to_clean = 0;
1063         ring->next_to_use = 0;
1064
1065         if (ring->type == ENA_RING_TYPE_TX)
1066                 return 0;
1067
1068         bufs_num = ring->ring_size - 1;
1069         rc = ena_populate_rx_queue(ring, bufs_num);
1070         if (rc != bufs_num) {
1071                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1072                 return (-1);
1073         }
1074
1075         return 0;
1076 }
1077
1078 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1079                               uint16_t queue_idx,
1080                               uint16_t nb_desc,
1081                               __rte_unused unsigned int socket_id,
1082                               const struct rte_eth_txconf *tx_conf)
1083 {
1084         struct ena_com_create_io_ctx ctx =
1085                 /* policy set to _HOST just to satisfy icc compiler */
1086                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1087                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
1088         struct ena_ring *txq = NULL;
1089         struct ena_adapter *adapter =
1090                 (struct ena_adapter *)(dev->data->dev_private);
1091         unsigned int i;
1092         int ena_qid;
1093         int rc;
1094         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1095
1096         txq = &adapter->tx_ring[queue_idx];
1097
1098         if (txq->configured) {
1099                 RTE_LOG(CRIT, PMD,
1100                         "API violation. Queue %d is already configured\n",
1101                         queue_idx);
1102                 return -1;
1103         }
1104
1105         if (!rte_is_power_of_2(nb_desc)) {
1106                 RTE_LOG(ERR, PMD,
1107                         "Unsupported size of RX queue: %d is not a power of 2.",
1108                         nb_desc);
1109                 return -EINVAL;
1110         }
1111
1112         if (nb_desc > adapter->tx_ring_size) {
1113                 RTE_LOG(ERR, PMD,
1114                         "Unsupported size of TX queue (max size: %d)\n",
1115                         adapter->tx_ring_size);
1116                 return -EINVAL;
1117         }
1118
1119         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1120
1121         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1122         ctx.qid = ena_qid;
1123         ctx.msix_vector = -1; /* admin interrupts not used */
1124         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1125         ctx.queue_size = adapter->tx_ring_size;
1126         ctx.numa_node = ena_cpu_to_node(queue_idx);
1127
1128         rc = ena_com_create_io_queue(ena_dev, &ctx);
1129         if (rc) {
1130                 RTE_LOG(ERR, PMD,
1131                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1132                         queue_idx, ena_qid, rc);
1133         }
1134         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1135         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1136
1137         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1138                                      &txq->ena_com_io_sq,
1139                                      &txq->ena_com_io_cq);
1140         if (rc) {
1141                 RTE_LOG(ERR, PMD,
1142                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1143                         queue_idx, rc);
1144                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1145                 goto err;
1146         }
1147
1148         txq->port_id = dev->data->port_id;
1149         txq->next_to_clean = 0;
1150         txq->next_to_use = 0;
1151         txq->ring_size = nb_desc;
1152
1153         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1154                                           sizeof(struct ena_tx_buffer) *
1155                                           txq->ring_size,
1156                                           RTE_CACHE_LINE_SIZE);
1157         if (!txq->tx_buffer_info) {
1158                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1159                 return -ENOMEM;
1160         }
1161
1162         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1163                                          sizeof(u16) * txq->ring_size,
1164                                          RTE_CACHE_LINE_SIZE);
1165         if (!txq->empty_tx_reqs) {
1166                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1167                 rte_free(txq->tx_buffer_info);
1168                 return -ENOMEM;
1169         }
1170         for (i = 0; i < txq->ring_size; i++)
1171                 txq->empty_tx_reqs[i] = i;
1172
1173         if (tx_conf != NULL) {
1174                 txq->offloads =
1175                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1176         }
1177
1178         /* Store pointer to this queue in upper layer */
1179         txq->configured = 1;
1180         dev->data->tx_queues[queue_idx] = txq;
1181 err:
1182         return rc;
1183 }
1184
1185 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1186                               uint16_t queue_idx,
1187                               uint16_t nb_desc,
1188                               __rte_unused unsigned int socket_id,
1189                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1190                               struct rte_mempool *mp)
1191 {
1192         struct ena_com_create_io_ctx ctx =
1193                 /* policy set to _HOST just to satisfy icc compiler */
1194                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1195                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1196         struct ena_adapter *adapter =
1197                 (struct ena_adapter *)(dev->data->dev_private);
1198         struct ena_ring *rxq = NULL;
1199         uint16_t ena_qid = 0;
1200         int i, rc = 0;
1201         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1202
1203         rxq = &adapter->rx_ring[queue_idx];
1204         if (rxq->configured) {
1205                 RTE_LOG(CRIT, PMD,
1206                         "API violation. Queue %d is already configured\n",
1207                         queue_idx);
1208                 return -1;
1209         }
1210
1211         if (!rte_is_power_of_2(nb_desc)) {
1212                 RTE_LOG(ERR, PMD,
1213                         "Unsupported size of TX queue: %d is not a power of 2.",
1214                         nb_desc);
1215                 return -EINVAL;
1216         }
1217
1218         if (nb_desc > adapter->rx_ring_size) {
1219                 RTE_LOG(ERR, PMD,
1220                         "Unsupported size of RX queue (max size: %d)\n",
1221                         adapter->rx_ring_size);
1222                 return -EINVAL;
1223         }
1224
1225         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1226
1227         ctx.qid = ena_qid;
1228         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1229         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1230         ctx.msix_vector = -1; /* admin interrupts not used */
1231         ctx.queue_size = adapter->rx_ring_size;
1232         ctx.numa_node = ena_cpu_to_node(queue_idx);
1233
1234         rc = ena_com_create_io_queue(ena_dev, &ctx);
1235         if (rc)
1236                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1237                         queue_idx, rc);
1238
1239         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1240         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1241
1242         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1243                                      &rxq->ena_com_io_sq,
1244                                      &rxq->ena_com_io_cq);
1245         if (rc) {
1246                 RTE_LOG(ERR, PMD,
1247                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1248                         queue_idx, rc);
1249                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1250         }
1251
1252         rxq->port_id = dev->data->port_id;
1253         rxq->next_to_clean = 0;
1254         rxq->next_to_use = 0;
1255         rxq->ring_size = nb_desc;
1256         rxq->mb_pool = mp;
1257
1258         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1259                                           sizeof(struct rte_mbuf *) * nb_desc,
1260                                           RTE_CACHE_LINE_SIZE);
1261         if (!rxq->rx_buffer_info) {
1262                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1263                 return -ENOMEM;
1264         }
1265
1266         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1267                                          sizeof(uint16_t) * nb_desc,
1268                                          RTE_CACHE_LINE_SIZE);
1269         if (!rxq->empty_rx_reqs) {
1270                 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1271                 rte_free(rxq->rx_buffer_info);
1272                 rxq->rx_buffer_info = NULL;
1273                 return -ENOMEM;
1274         }
1275
1276         for (i = 0; i < nb_desc; i++)
1277                 rxq->empty_tx_reqs[i] = i;
1278
1279         /* Store pointer to this queue in upper layer */
1280         rxq->configured = 1;
1281         dev->data->rx_queues[queue_idx] = rxq;
1282
1283         return rc;
1284 }
1285
1286 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1287 {
1288         unsigned int i;
1289         int rc;
1290         uint16_t ring_size = rxq->ring_size;
1291         uint16_t ring_mask = ring_size - 1;
1292         uint16_t next_to_use = rxq->next_to_use;
1293         uint16_t in_use, req_id;
1294         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1295
1296         if (unlikely(!count))
1297                 return 0;
1298
1299         in_use = rxq->next_to_use - rxq->next_to_clean;
1300         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1301
1302         count = RTE_MIN(count,
1303                         (uint16_t)(ring_size - (next_to_use & ring_mask)));
1304
1305         /* get resources for incoming packets */
1306         rc = rte_mempool_get_bulk(rxq->mb_pool,
1307                                   (void **)(&mbufs[next_to_use & ring_mask]),
1308                                   count);
1309         if (unlikely(rc < 0)) {
1310                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1311                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1312                 return 0;
1313         }
1314
1315         for (i = 0; i < count; i++) {
1316                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1317                 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1318                 struct ena_com_buf ebuf;
1319
1320                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1321
1322                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1323                 /* prepare physical address for DMA transaction */
1324                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1325                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1326                 /* pass resource to device */
1327                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1328                                                 &ebuf, req_id);
1329                 if (unlikely(rc)) {
1330                         rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1331                                              count - i);
1332                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1333                         break;
1334                 }
1335                 next_to_use++;
1336         }
1337
1338         /* When we submitted free recources to device... */
1339         if (i > 0) {
1340                 /* ...let HW know that it can fill buffers with data */
1341                 rte_wmb();
1342                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1343
1344                 rxq->next_to_use = next_to_use;
1345         }
1346
1347         return i;
1348 }
1349
1350 static int ena_device_init(struct ena_com_dev *ena_dev,
1351                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1352                            bool *wd_state)
1353 {
1354         uint32_t aenq_groups;
1355         int rc;
1356         bool readless_supported;
1357
1358         /* Initialize mmio registers */
1359         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1360         if (rc) {
1361                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1362                 return rc;
1363         }
1364
1365         /* The PCIe configuration space revision id indicate if mmio reg
1366          * read is disabled.
1367          */
1368         readless_supported =
1369                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1370                                & ENA_MMIO_DISABLE_REG_READ);
1371         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1372
1373         /* reset device */
1374         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1375         if (rc) {
1376                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1377                 goto err_mmio_read_less;
1378         }
1379
1380         /* check FW version */
1381         rc = ena_com_validate_version(ena_dev);
1382         if (rc) {
1383                 RTE_LOG(ERR, PMD, "device version is too low\n");
1384                 goto err_mmio_read_less;
1385         }
1386
1387         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1388
1389         /* ENA device administration layer init */
1390         rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
1391         if (rc) {
1392                 RTE_LOG(ERR, PMD,
1393                         "cannot initialize ena admin queue with device\n");
1394                 goto err_mmio_read_less;
1395         }
1396
1397         /* To enable the msix interrupts the driver needs to know the number
1398          * of queues. So the driver uses polling mode to retrieve this
1399          * information.
1400          */
1401         ena_com_set_admin_polling_mode(ena_dev, true);
1402
1403         ena_config_host_info(ena_dev);
1404
1405         /* Get Device Attributes and features */
1406         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1407         if (rc) {
1408                 RTE_LOG(ERR, PMD,
1409                         "cannot get attribute for ena device rc= %d\n", rc);
1410                 goto err_admin_init;
1411         }
1412
1413         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1414                       BIT(ENA_ADMIN_NOTIFICATION) |
1415                       BIT(ENA_ADMIN_KEEP_ALIVE);
1416
1417         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1418         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1419         if (rc) {
1420                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1421                 goto err_admin_init;
1422         }
1423
1424         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1425
1426         return 0;
1427
1428 err_admin_init:
1429         ena_com_admin_destroy(ena_dev);
1430
1431 err_mmio_read_less:
1432         ena_com_mmio_reg_read_request_destroy(ena_dev);
1433
1434         return rc;
1435 }
1436
1437 static void ena_interrupt_handler_rte(void *cb_arg)
1438 {
1439         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1440         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1441
1442         ena_com_admin_q_comp_intr_handler(ena_dev);
1443         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1444                 ena_com_aenq_intr_handler(ena_dev, adapter);
1445 }
1446
1447 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1448 {
1449         if (!adapter->wd_state)
1450                 return;
1451
1452         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1453                 return;
1454
1455         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1456             adapter->keep_alive_timeout)) {
1457                 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1458                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1459                 adapter->trigger_reset = true;
1460         }
1461 }
1462
1463 /* Check if admin queue is enabled */
1464 static void check_for_admin_com_state(struct ena_adapter *adapter)
1465 {
1466         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1467                 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1468                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1469                 adapter->trigger_reset = true;
1470         }
1471 }
1472
1473 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1474                                   void *arg)
1475 {
1476         struct ena_adapter *adapter = (struct ena_adapter *)arg;
1477         struct rte_eth_dev *dev = adapter->rte_dev;
1478
1479         check_for_missing_keep_alive(adapter);
1480         check_for_admin_com_state(adapter);
1481
1482         if (unlikely(adapter->trigger_reset)) {
1483                 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1484                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1485                         NULL);
1486         }
1487 }
1488
1489 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1490 {
1491         struct rte_pci_device *pci_dev;
1492         struct rte_intr_handle *intr_handle;
1493         struct ena_adapter *adapter =
1494                 (struct ena_adapter *)(eth_dev->data->dev_private);
1495         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1496         struct ena_com_dev_get_features_ctx get_feat_ctx;
1497         int queue_size, rc;
1498         u16 tx_sgl_size = 0;
1499
1500         static int adapters_found;
1501         bool wd_state;
1502
1503         memset(adapter, 0, sizeof(struct ena_adapter));
1504         ena_dev = &adapter->ena_dev;
1505
1506         eth_dev->dev_ops = &ena_dev_ops;
1507         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1508         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1509         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1510         adapter->rte_eth_dev_data = eth_dev->data;
1511         adapter->rte_dev = eth_dev;
1512
1513         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1514                 return 0;
1515
1516         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1517         adapter->pdev = pci_dev;
1518
1519         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1520                      pci_dev->addr.domain,
1521                      pci_dev->addr.bus,
1522                      pci_dev->addr.devid,
1523                      pci_dev->addr.function);
1524
1525         intr_handle = &pci_dev->intr_handle;
1526
1527         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1528         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1529
1530         if (!adapter->regs) {
1531                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1532                              ENA_REGS_BAR);
1533                 return -ENXIO;
1534         }
1535
1536         ena_dev->reg_bar = adapter->regs;
1537         ena_dev->dmadev = adapter->pdev;
1538
1539         adapter->id_number = adapters_found;
1540
1541         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1542                  adapter->id_number);
1543
1544         /* device specific initialization routine */
1545         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1546         if (rc) {
1547                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1548                 return -1;
1549         }
1550         adapter->wd_state = wd_state;
1551
1552         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1553         adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1554
1555         queue_size = ena_calc_queue_size(ena_dev, &tx_sgl_size, &get_feat_ctx);
1556         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1557                 return -EFAULT;
1558
1559         adapter->tx_ring_size = queue_size;
1560         adapter->rx_ring_size = queue_size;
1561
1562         adapter->max_tx_sgl_size = tx_sgl_size;
1563
1564         /* prepare ring structures */
1565         ena_init_rings(adapter);
1566
1567         ena_config_debug_area(adapter);
1568
1569         /* Set max MTU for this device */
1570         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1571
1572         /* set device support for TSO */
1573         adapter->tso4_supported = get_feat_ctx.offload.tx &
1574                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1575
1576         /* Copy MAC address and point DPDK to it */
1577         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1578         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1579                         (struct ether_addr *)adapter->mac_addr);
1580
1581         adapter->drv_stats = rte_zmalloc("adapter stats",
1582                                          sizeof(*adapter->drv_stats),
1583                                          RTE_CACHE_LINE_SIZE);
1584         if (!adapter->drv_stats) {
1585                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1586                 return -ENOMEM;
1587         }
1588
1589         rte_intr_callback_register(intr_handle,
1590                                    ena_interrupt_handler_rte,
1591                                    adapter);
1592         rte_intr_enable(intr_handle);
1593         ena_com_set_admin_polling_mode(ena_dev, false);
1594         ena_com_admin_aenq_enable(ena_dev);
1595
1596         if (adapters_found == 0)
1597                 rte_timer_subsystem_init();
1598         rte_timer_init(&adapter->timer_wd);
1599
1600         adapters_found++;
1601         adapter->state = ENA_ADAPTER_STATE_INIT;
1602
1603         return 0;
1604 }
1605
1606 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1607 {
1608         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1609         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1610         struct ena_adapter *adapter =
1611                 (struct ena_adapter *)(eth_dev->data->dev_private);
1612
1613         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1614                 return -EPERM;
1615
1616         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1617                 ena_close(eth_dev);
1618
1619         eth_dev->dev_ops = NULL;
1620         eth_dev->rx_pkt_burst = NULL;
1621         eth_dev->tx_pkt_burst = NULL;
1622         eth_dev->tx_pkt_prepare = NULL;
1623
1624         rte_free(adapter->drv_stats);
1625         adapter->drv_stats = NULL;
1626
1627         rte_intr_disable(intr_handle);
1628         rte_intr_callback_unregister(intr_handle,
1629                                      ena_interrupt_handler_rte,
1630                                      adapter);
1631
1632         adapter->state = ENA_ADAPTER_STATE_FREE;
1633
1634         return 0;
1635 }
1636
1637 static int ena_dev_configure(struct rte_eth_dev *dev)
1638 {
1639         struct ena_adapter *adapter =
1640                 (struct ena_adapter *)(dev->data->dev_private);
1641
1642         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1643
1644         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1645         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1646         return 0;
1647 }
1648
1649 static void ena_init_rings(struct ena_adapter *adapter)
1650 {
1651         int i;
1652
1653         for (i = 0; i < adapter->num_queues; i++) {
1654                 struct ena_ring *ring = &adapter->tx_ring[i];
1655
1656                 ring->configured = 0;
1657                 ring->type = ENA_RING_TYPE_TX;
1658                 ring->adapter = adapter;
1659                 ring->id = i;
1660                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1661                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1662                 ring->sgl_size = adapter->max_tx_sgl_size;
1663         }
1664
1665         for (i = 0; i < adapter->num_queues; i++) {
1666                 struct ena_ring *ring = &adapter->rx_ring[i];
1667
1668                 ring->configured = 0;
1669                 ring->type = ENA_RING_TYPE_RX;
1670                 ring->adapter = adapter;
1671                 ring->id = i;
1672         }
1673 }
1674
1675 static void ena_infos_get(struct rte_eth_dev *dev,
1676                           struct rte_eth_dev_info *dev_info)
1677 {
1678         struct ena_adapter *adapter;
1679         struct ena_com_dev *ena_dev;
1680         struct ena_com_dev_get_features_ctx feat;
1681         uint64_t rx_feat = 0, tx_feat = 0;
1682         int rc = 0;
1683
1684         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1685         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1686         adapter = (struct ena_adapter *)(dev->data->dev_private);
1687
1688         ena_dev = &adapter->ena_dev;
1689         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1690
1691         dev_info->speed_capa =
1692                         ETH_LINK_SPEED_1G   |
1693                         ETH_LINK_SPEED_2_5G |
1694                         ETH_LINK_SPEED_5G   |
1695                         ETH_LINK_SPEED_10G  |
1696                         ETH_LINK_SPEED_25G  |
1697                         ETH_LINK_SPEED_40G  |
1698                         ETH_LINK_SPEED_50G  |
1699                         ETH_LINK_SPEED_100G;
1700
1701         /* Get supported features from HW */
1702         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1703         if (unlikely(rc)) {
1704                 RTE_LOG(ERR, PMD,
1705                         "Cannot get attribute for ena device rc= %d\n", rc);
1706                 return;
1707         }
1708
1709         /* Set Tx & Rx features available for device */
1710         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1711                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1712
1713         if (feat.offload.tx &
1714             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1715                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1716                         DEV_TX_OFFLOAD_UDP_CKSUM |
1717                         DEV_TX_OFFLOAD_TCP_CKSUM;
1718
1719         if (feat.offload.rx_supported &
1720             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1721                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1722                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1723                         DEV_RX_OFFLOAD_TCP_CKSUM;
1724
1725         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1726
1727         /* Inform framework about available features */
1728         dev_info->rx_offload_capa = rx_feat;
1729         dev_info->rx_queue_offload_capa = rx_feat;
1730         dev_info->tx_offload_capa = tx_feat;
1731         dev_info->tx_queue_offload_capa = tx_feat;
1732
1733         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1734         dev_info->max_rx_pktlen  = adapter->max_mtu;
1735         dev_info->max_mac_addrs = 1;
1736
1737         dev_info->max_rx_queues = adapter->num_queues;
1738         dev_info->max_tx_queues = adapter->num_queues;
1739         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1740
1741         adapter->tx_supported_offloads = tx_feat;
1742         adapter->rx_supported_offloads = rx_feat;
1743 }
1744
1745 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1746                                   uint16_t nb_pkts)
1747 {
1748         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1749         unsigned int ring_size = rx_ring->ring_size;
1750         unsigned int ring_mask = ring_size - 1;
1751         uint16_t next_to_clean = rx_ring->next_to_clean;
1752         uint16_t desc_in_use = 0;
1753         uint16_t req_id;
1754         unsigned int recv_idx = 0;
1755         struct rte_mbuf *mbuf = NULL;
1756         struct rte_mbuf *mbuf_head = NULL;
1757         struct rte_mbuf *mbuf_prev = NULL;
1758         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1759         unsigned int completed;
1760
1761         struct ena_com_rx_ctx ena_rx_ctx;
1762         int rc = 0;
1763
1764         /* Check adapter state */
1765         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1766                 RTE_LOG(ALERT, PMD,
1767                         "Trying to receive pkts while device is NOT running\n");
1768                 return 0;
1769         }
1770
1771         desc_in_use = rx_ring->next_to_use - next_to_clean;
1772         if (unlikely(nb_pkts > desc_in_use))
1773                 nb_pkts = desc_in_use;
1774
1775         for (completed = 0; completed < nb_pkts; completed++) {
1776                 int segments = 0;
1777
1778                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1779                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1780                 ena_rx_ctx.descs = 0;
1781                 /* receive packet context */
1782                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1783                                     rx_ring->ena_com_io_sq,
1784                                     &ena_rx_ctx);
1785                 if (unlikely(rc)) {
1786                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1787                         return 0;
1788                 }
1789
1790                 if (unlikely(ena_rx_ctx.descs == 0))
1791                         break;
1792
1793                 while (segments < ena_rx_ctx.descs) {
1794                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
1795                         rc = validate_rx_req_id(rx_ring, req_id);
1796                         if (unlikely(rc))
1797                                 break;
1798
1799                         mbuf = rx_buff_info[req_id];
1800                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1801                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1802                         mbuf->refcnt = 1;
1803                         mbuf->next = NULL;
1804                         if (segments == 0) {
1805                                 mbuf->nb_segs = ena_rx_ctx.descs;
1806                                 mbuf->port = rx_ring->port_id;
1807                                 mbuf->pkt_len = 0;
1808                                 mbuf_head = mbuf;
1809                         } else {
1810                                 /* for multi-segment pkts create mbuf chain */
1811                                 mbuf_prev->next = mbuf;
1812                         }
1813                         mbuf_head->pkt_len += mbuf->data_len;
1814
1815                         mbuf_prev = mbuf;
1816                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
1817                                 req_id;
1818                         segments++;
1819                         next_to_clean++;
1820                 }
1821
1822                 /* fill mbuf attributes if any */
1823                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1824                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1825
1826                 /* pass to DPDK application head mbuf */
1827                 rx_pkts[recv_idx] = mbuf_head;
1828                 recv_idx++;
1829         }
1830
1831         rx_ring->next_to_clean = next_to_clean;
1832
1833         desc_in_use = desc_in_use - completed + 1;
1834         /* Burst refill to save doorbells, memory barriers, const interval */
1835         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1836                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1837
1838         return recv_idx;
1839 }
1840
1841 static uint16_t
1842 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1843                 uint16_t nb_pkts)
1844 {
1845         int32_t ret;
1846         uint32_t i;
1847         struct rte_mbuf *m;
1848         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1849         struct ipv4_hdr *ip_hdr;
1850         uint64_t ol_flags;
1851         uint16_t frag_field;
1852
1853         for (i = 0; i != nb_pkts; i++) {
1854                 m = tx_pkts[i];
1855                 ol_flags = m->ol_flags;
1856
1857                 if (!(ol_flags & PKT_TX_IPV4))
1858                         continue;
1859
1860                 /* If there was not L2 header length specified, assume it is
1861                  * length of the ethernet header.
1862                  */
1863                 if (unlikely(m->l2_len == 0))
1864                         m->l2_len = sizeof(struct ether_hdr);
1865
1866                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1867                                                  m->l2_len);
1868                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1869
1870                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1871                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1872
1873                         /* If IPv4 header has DF flag enabled and TSO support is
1874                          * disabled, partial chcecksum should not be calculated.
1875                          */
1876                         if (!tx_ring->adapter->tso4_supported)
1877                                 continue;
1878                 }
1879
1880                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1881                                 (ol_flags & PKT_TX_L4_MASK) ==
1882                                 PKT_TX_SCTP_CKSUM) {
1883                         rte_errno = -ENOTSUP;
1884                         return i;
1885                 }
1886
1887 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1888                 ret = rte_validate_tx_offload(m);
1889                 if (ret != 0) {
1890                         rte_errno = ret;
1891                         return i;
1892                 }
1893 #endif
1894
1895                 /* In case we are supposed to TSO and have DF not set (DF=0)
1896                  * hardware must be provided with partial checksum, otherwise
1897                  * it will take care of necessary calculations.
1898                  */
1899
1900                 ret = rte_net_intel_cksum_flags_prepare(m,
1901                         ol_flags & ~PKT_TX_TCP_SEG);
1902                 if (ret != 0) {
1903                         rte_errno = ret;
1904                         return i;
1905                 }
1906         }
1907
1908         return i;
1909 }
1910
1911 static void ena_update_hints(struct ena_adapter *adapter,
1912                              struct ena_admin_ena_hw_hints *hints)
1913 {
1914         if (hints->admin_completion_tx_timeout)
1915                 adapter->ena_dev.admin_queue.completion_timeout =
1916                         hints->admin_completion_tx_timeout * 1000;
1917
1918         if (hints->mmio_read_timeout)
1919                 /* convert to usec */
1920                 adapter->ena_dev.mmio_read.reg_read_to =
1921                         hints->mmio_read_timeout * 1000;
1922
1923         if (hints->driver_watchdog_timeout) {
1924                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1925                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
1926                 else
1927                         // Convert msecs to ticks
1928                         adapter->keep_alive_timeout =
1929                                 (hints->driver_watchdog_timeout *
1930                                 rte_get_timer_hz()) / 1000;
1931         }
1932 }
1933
1934 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
1935                                         struct rte_mbuf *mbuf)
1936 {
1937         int num_segments, rc;
1938
1939         num_segments = mbuf->nb_segs;
1940
1941         if (likely(num_segments < tx_ring->sgl_size))
1942                 return 0;
1943
1944         rc = rte_pktmbuf_linearize(mbuf);
1945         if (unlikely(rc))
1946                 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
1947
1948         return rc;
1949 }
1950
1951 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1952                                   uint16_t nb_pkts)
1953 {
1954         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1955         uint16_t next_to_use = tx_ring->next_to_use;
1956         uint16_t next_to_clean = tx_ring->next_to_clean;
1957         struct rte_mbuf *mbuf;
1958         unsigned int ring_size = tx_ring->ring_size;
1959         unsigned int ring_mask = ring_size - 1;
1960         struct ena_com_tx_ctx ena_tx_ctx;
1961         struct ena_tx_buffer *tx_info;
1962         struct ena_com_buf *ebuf;
1963         uint16_t rc, req_id, total_tx_descs = 0;
1964         uint16_t sent_idx = 0, empty_tx_reqs;
1965         int nb_hw_desc;
1966
1967         /* Check adapter state */
1968         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1969                 RTE_LOG(ALERT, PMD,
1970                         "Trying to xmit pkts while device is NOT running\n");
1971                 return 0;
1972         }
1973
1974         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1975         if (nb_pkts > empty_tx_reqs)
1976                 nb_pkts = empty_tx_reqs;
1977
1978         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1979                 mbuf = tx_pkts[sent_idx];
1980
1981                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
1982                 if (unlikely(rc))
1983                         break;
1984
1985                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1986                 tx_info = &tx_ring->tx_buffer_info[req_id];
1987                 tx_info->mbuf = mbuf;
1988                 tx_info->num_of_bufs = 0;
1989                 ebuf = tx_info->bufs;
1990
1991                 /* Prepare TX context */
1992                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1993                 memset(&ena_tx_ctx.ena_meta, 0x0,
1994                        sizeof(struct ena_com_tx_meta));
1995                 ena_tx_ctx.ena_bufs = ebuf;
1996                 ena_tx_ctx.req_id = req_id;
1997                 if (tx_ring->tx_mem_queue_type ==
1998                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1999                         /* prepare the push buffer with
2000                          * virtual address of the data
2001                          */
2002                         ena_tx_ctx.header_len =
2003                                 RTE_MIN(mbuf->data_len,
2004                                         tx_ring->tx_max_header_size);
2005                         ena_tx_ctx.push_header =
2006                                 (void *)((char *)mbuf->buf_addr +
2007                                          mbuf->data_off);
2008                 } /* there's no else as we take advantage of memset zeroing */
2009
2010                 /* Set TX offloads flags, if applicable */
2011                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2012
2013                 if (unlikely(mbuf->ol_flags &
2014                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2015                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2016
2017                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2018
2019                 /* Process first segment taking into
2020                  * consideration pushed header
2021                  */
2022                 if (mbuf->data_len > ena_tx_ctx.header_len) {
2023                         ebuf->paddr = mbuf->buf_iova +
2024                                       mbuf->data_off +
2025                                       ena_tx_ctx.header_len;
2026                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
2027                         ebuf++;
2028                         tx_info->num_of_bufs++;
2029                 }
2030
2031                 while ((mbuf = mbuf->next) != NULL) {
2032                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
2033                         ebuf->len = mbuf->data_len;
2034                         ebuf++;
2035                         tx_info->num_of_bufs++;
2036                 }
2037
2038                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2039
2040                 /* Write data to device */
2041                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2042                                         &ena_tx_ctx, &nb_hw_desc);
2043                 if (unlikely(rc))
2044                         break;
2045
2046                 tx_info->tx_descs = nb_hw_desc;
2047
2048                 next_to_use++;
2049         }
2050
2051         /* If there are ready packets to be xmitted... */
2052         if (sent_idx > 0) {
2053                 /* ...let HW do its best :-) */
2054                 rte_wmb();
2055                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2056
2057                 tx_ring->next_to_use = next_to_use;
2058         }
2059
2060         /* Clear complete packets  */
2061         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2062                 /* Get Tx info & store how many descs were processed  */
2063                 tx_info = &tx_ring->tx_buffer_info[req_id];
2064                 total_tx_descs += tx_info->tx_descs;
2065
2066                 /* Free whole mbuf chain  */
2067                 mbuf = tx_info->mbuf;
2068                 rte_pktmbuf_free(mbuf);
2069                 tx_info->mbuf = NULL;
2070
2071                 /* Put back descriptor to the ring for reuse */
2072                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2073                 next_to_clean++;
2074
2075                 /* If too many descs to clean, leave it for another run */
2076                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2077                         break;
2078         }
2079
2080         if (total_tx_descs > 0) {
2081                 /* acknowledge completion of sent packets */
2082                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2083                 tx_ring->next_to_clean = next_to_clean;
2084         }
2085
2086         return sent_idx;
2087 }
2088
2089 /*********************************************************************
2090  *  PMD configuration
2091  *********************************************************************/
2092 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2093         struct rte_pci_device *pci_dev)
2094 {
2095         return rte_eth_dev_pci_generic_probe(pci_dev,
2096                 sizeof(struct ena_adapter), eth_ena_dev_init);
2097 }
2098
2099 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2100 {
2101         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2102 }
2103
2104 static struct rte_pci_driver rte_ena_pmd = {
2105         .id_table = pci_id_ena_map,
2106         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2107         .probe = eth_ena_pci_probe,
2108         .remove = eth_ena_pci_remove,
2109 };
2110
2111 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2112 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2113 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2114
2115 RTE_INIT(ena_init_log);
2116 static void
2117 ena_init_log(void)
2118 {
2119         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2120         if (ena_logtype_init >= 0)
2121                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2122         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2123         if (ena_logtype_driver >= 0)
2124                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2125 }
2126
2127 /******************************************************************************
2128  ******************************** AENQ Handlers *******************************
2129  *****************************************************************************/
2130 static void ena_update_on_link_change(void *adapter_data,
2131                                       struct ena_admin_aenq_entry *aenq_e)
2132 {
2133         struct rte_eth_dev *eth_dev;
2134         struct ena_adapter *adapter;
2135         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2136         uint32_t status;
2137
2138         adapter = (struct ena_adapter *)adapter_data;
2139         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2140         eth_dev = adapter->rte_dev;
2141
2142         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2143         adapter->link_status = status;
2144
2145         ena_link_update(eth_dev, 0);
2146         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2147 }
2148
2149 static void ena_notification(void *data,
2150                              struct ena_admin_aenq_entry *aenq_e)
2151 {
2152         struct ena_adapter *adapter = (struct ena_adapter *)data;
2153         struct ena_admin_ena_hw_hints *hints;
2154
2155         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2156                 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2157                         aenq_e->aenq_common_desc.group,
2158                         ENA_ADMIN_NOTIFICATION);
2159
2160         switch (aenq_e->aenq_common_desc.syndrom) {
2161         case ENA_ADMIN_UPDATE_HINTS:
2162                 hints = (struct ena_admin_ena_hw_hints *)
2163                         (&aenq_e->inline_data_w4);
2164                 ena_update_hints(adapter, hints);
2165                 break;
2166         default:
2167                 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2168                         aenq_e->aenq_common_desc.syndrom);
2169         }
2170 }
2171
2172 static void ena_keep_alive(void *adapter_data,
2173                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2174 {
2175         struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2176
2177         adapter->timestamp_wd = rte_get_timer_cycles();
2178 }
2179
2180 /**
2181  * This handler will called for unknown event group or unimplemented handlers
2182  **/
2183 static void unimplemented_aenq_handler(__rte_unused void *data,
2184                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2185 {
2186         // Unimplemented handler
2187 }
2188
2189 static struct ena_aenq_handlers aenq_handlers = {
2190         .handlers = {
2191                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2192                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2193                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2194         },
2195         .unimplemented_handler = unimplemented_aenq_handler
2196 };