drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_ether.h>
   8 #include <rte_ethdev_driver.h>
   9 #include <rte_ethdev_pci.h>
  10 #include <rte_tcp.h>
  11 #include <rte_atomic.h>
  12 #include <rte_dev.h>
  13 #include <rte_errno.h>
  14 #include <rte_version.h>
  15 #include <rte_net.h>
  16 #include <rte_kvargs.h>
  17
  18 #include "ena_ethdev.h"
  19 #include "ena_logs.h"
  20 #include "ena_platform.h"
  21 #include "ena_com.h"
  22 #include "ena_eth_com.h"
  23
  24 #include <ena_common_defs.h>
  25 #include <ena_regs_defs.h>
  26 #include <ena_admin_defs.h>
  27 #include <ena_eth_io_defs.h>
  28
  29 #define DRV_MODULE_VER_MAJOR    2
  30 #define DRV_MODULE_VER_MINOR    0
  31 #define DRV_MODULE_VER_SUBMINOR 3
  32
  33 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  34 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  35 /*reverse version of ENA_IO_RXQ_IDX*/
  36 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  37
  38 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  39 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  40
  41 #define GET_L4_HDR_LEN(mbuf)                                    \
  42         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  43                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  44
  45 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  46 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  47 #define ENA_HASH_KEY_SIZE       40
  48 #define ETH_GSTRING_LEN 32
  49
  50 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  51
  52 #define ENA_MIN_RING_DESC       128
  53
  54 enum ethtool_stringset {
  55         ETH_SS_TEST             = 0,
  56         ETH_SS_STATS,
  57 };
  58
  59 struct ena_stats {
  60         char name[ETH_GSTRING_LEN];
  61         int stat_offset;
  62 };
  63
  64 #define ENA_STAT_ENTRY(stat, stat_type) { \
  65         .name = #stat, \
  66         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  67 }
  68
  69 #define ENA_STAT_RX_ENTRY(stat) \
  70         ENA_STAT_ENTRY(stat, rx)
  71
  72 #define ENA_STAT_TX_ENTRY(stat) \
  73         ENA_STAT_ENTRY(stat, tx)
  74
  75 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  76         ENA_STAT_ENTRY(stat, dev)
  77
  78 /* Device arguments */
  79 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  80
  81 /*
  82  * Each rte_memzone should have unique name.
  83  * To satisfy it, count number of allocation and add it to name.
  84  */
  85 rte_atomic32_t ena_alloc_cnt;
  86
  87 static const struct ena_stats ena_stats_global_strings[] = {
  88         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  89         ENA_STAT_GLOBAL_ENTRY(dev_start),
  90         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  91         ENA_STAT_GLOBAL_ENTRY(tx_drops),
  92 };
  93
  94 static const struct ena_stats ena_stats_tx_strings[] = {
  95         ENA_STAT_TX_ENTRY(cnt),
  96         ENA_STAT_TX_ENTRY(bytes),
  97         ENA_STAT_TX_ENTRY(prepare_ctx_err),
  98         ENA_STAT_TX_ENTRY(linearize),
  99         ENA_STAT_TX_ENTRY(linearize_failed),
 100         ENA_STAT_TX_ENTRY(tx_poll),
 101         ENA_STAT_TX_ENTRY(doorbells),
 102         ENA_STAT_TX_ENTRY(bad_req_id),
 103         ENA_STAT_TX_ENTRY(available_desc),
 104 };
 105
 106 static const struct ena_stats ena_stats_rx_strings[] = {
 107         ENA_STAT_RX_ENTRY(cnt),
 108         ENA_STAT_RX_ENTRY(bytes),
 109         ENA_STAT_RX_ENTRY(refill_partial),
 110         ENA_STAT_RX_ENTRY(bad_csum),
 111         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 112         ENA_STAT_RX_ENTRY(bad_desc_num),
 113         ENA_STAT_RX_ENTRY(bad_req_id),
 114 };
 115
 116 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 117 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 118 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 119
 120 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 121                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 122                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 123                         DEV_TX_OFFLOAD_TCP_TSO)
 124 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 125                        PKT_TX_IP_CKSUM |\
 126                        PKT_TX_TCP_SEG)
 127
 128 /** Vendor ID used by Amazon devices */
 129 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 130 /** Amazon devices */
 131 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 132 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 133
 134 #define ENA_TX_OFFLOAD_MASK     (\
 135         PKT_TX_L4_MASK |         \
 136         PKT_TX_IPV6 |            \
 137         PKT_TX_IPV4 |            \
 138         PKT_TX_IP_CKSUM |        \
 139         PKT_TX_TCP_SEG)
 140
 141 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 142         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 143
 144 int ena_logtype_init;
 145 int ena_logtype_driver;
 146
 147 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
 148 int ena_logtype_rx;
 149 #endif
 150 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
 151 int ena_logtype_tx;
 152 #endif
 153 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
 154 int ena_logtype_tx_free;
 155 #endif
 156 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
 157 int ena_logtype_com;
 158 #endif
 159
 160 static const struct rte_pci_id pci_id_ena_map[] = {
 161         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 162         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 163         { .device_id = 0 },
 164 };
 165
 166 static struct ena_aenq_handlers aenq_handlers;
 167
 168 static int ena_device_init(struct ena_com_dev *ena_dev,
 169                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 170                            bool *wd_state);
 171 static int ena_dev_configure(struct rte_eth_dev *dev);
 172 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
 173         struct ena_tx_buffer *tx_info,
 174         struct rte_mbuf *mbuf,
 175         void **push_header,
 176         uint16_t *header_len);
 177 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
 178 static void ena_tx_cleanup(struct ena_ring *tx_ring);
 179 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 180                                   uint16_t nb_pkts);
 181 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 182                 uint16_t nb_pkts);
 183 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 184                               uint16_t nb_desc, unsigned int socket_id,
 185                               const struct rte_eth_txconf *tx_conf);
 186 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 187                               uint16_t nb_desc, unsigned int socket_id,
 188                               const struct rte_eth_rxconf *rx_conf,
 189                               struct rte_mempool *mp);
 190 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
 191 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
 192                                     struct ena_com_rx_buf_info *ena_bufs,
 193                                     uint32_t descs,
 194                                     uint16_t *next_to_clean,
 195                                     uint8_t offset);
 196 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 197                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 198 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 199 static void ena_init_rings(struct ena_adapter *adapter,
 200                            bool disable_meta_caching);
 201 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 202 static int ena_start(struct rte_eth_dev *dev);
 203 static void ena_stop(struct rte_eth_dev *dev);
 204 static void ena_close(struct rte_eth_dev *dev);
 205 static int ena_dev_reset(struct rte_eth_dev *dev);
 206 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 207 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 208 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 209 static void ena_rx_queue_release(void *queue);
 210 static void ena_tx_queue_release(void *queue);
 211 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 212 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 213 static int ena_link_update(struct rte_eth_dev *dev,
 214                            int wait_to_complete);
 215 static int ena_create_io_queue(struct ena_ring *ring);
 216 static void ena_queue_stop(struct ena_ring *ring);
 217 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 218                               enum ena_ring_type ring_type);
 219 static int ena_queue_start(struct ena_ring *ring);
 220 static int ena_queue_start_all(struct rte_eth_dev *dev,
 221                                enum ena_ring_type ring_type);
 222 static void ena_stats_restart(struct rte_eth_dev *dev);
 223 static int ena_infos_get(struct rte_eth_dev *dev,
 224                          struct rte_eth_dev_info *dev_info);
 225 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 226                                struct rte_eth_rss_reta_entry64 *reta_conf,
 227                                uint16_t reta_size);
 228 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 229                               struct rte_eth_rss_reta_entry64 *reta_conf,
 230                               uint16_t reta_size);
 231 static void ena_interrupt_handler_rte(void *cb_arg);
 232 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 233 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 234 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 235 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 236                                 struct rte_eth_xstat_name *xstats_names,
 237                                 unsigned int n);
 238 static int ena_xstats_get(struct rte_eth_dev *dev,
 239                           struct rte_eth_xstat *stats,
 240                           unsigned int n);
 241 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 242                                 const uint64_t *ids,
 243                                 uint64_t *values,
 244                                 unsigned int n);
 245 static int ena_process_bool_devarg(const char *key,
 246                                    const char *value,
 247                                    void *opaque);
 248 static int ena_parse_devargs(struct ena_adapter *adapter,
 249                              struct rte_devargs *devargs);
 250
 251 static const struct eth_dev_ops ena_dev_ops = {
 252         .dev_configure        = ena_dev_configure,
 253         .dev_infos_get        = ena_infos_get,
 254         .rx_queue_setup       = ena_rx_queue_setup,
 255         .tx_queue_setup       = ena_tx_queue_setup,
 256         .dev_start            = ena_start,
 257         .dev_stop             = ena_stop,
 258         .link_update          = ena_link_update,
 259         .stats_get            = ena_stats_get,
 260         .xstats_get_names     = ena_xstats_get_names,
 261         .xstats_get           = ena_xstats_get,
 262         .xstats_get_by_id     = ena_xstats_get_by_id,
 263         .mtu_set              = ena_mtu_set,
 264         .rx_queue_release     = ena_rx_queue_release,
 265         .tx_queue_release     = ena_tx_queue_release,
 266         .dev_close            = ena_close,
 267         .dev_reset            = ena_dev_reset,
 268         .reta_update          = ena_rss_reta_update,
 269         .reta_query           = ena_rss_reta_query,
 270 };
 271
 272 void ena_rss_key_fill(void *key, size_t size)
 273 {
 274         static bool key_generated;
 275         static uint8_t default_key[ENA_HASH_KEY_SIZE];
 276         size_t i;
 277
 278         RTE_ASSERT(size <= ENA_HASH_KEY_SIZE);
 279
 280         if (!key_generated) {
 281                 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i)
 282                         default_key[i] = rte_rand() & 0xff;
 283                 key_generated = true;
 284         }
 285
 286         rte_memcpy(key, default_key, size);
 287 }
 288
 289 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 290                                        struct ena_com_rx_ctx *ena_rx_ctx)
 291 {
 292         uint64_t ol_flags = 0;
 293         uint32_t packet_type = 0;
 294
 295         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 296                 packet_type |= RTE_PTYPE_L4_TCP;
 297         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 298                 packet_type |= RTE_PTYPE_L4_UDP;
 299
 300         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 301                 packet_type |= RTE_PTYPE_L3_IPV4;
 302         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 303                 packet_type |= RTE_PTYPE_L3_IPV6;
 304
 305         if (!ena_rx_ctx->l4_csum_checked)
 306                 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 307         else
 308                 if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag)
 309                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
 310                 else
 311                         ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 312
 313         if (unlikely(ena_rx_ctx->l3_csum_err))
 314                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 315
 316         mbuf->ol_flags = ol_flags;
 317         mbuf->packet_type = packet_type;
 318 }
 319
 320 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 321                                        struct ena_com_tx_ctx *ena_tx_ctx,
 322                                        uint64_t queue_offloads,
 323                                        bool disable_meta_caching)
 324 {
 325         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 326
 327         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 328             (queue_offloads & QUEUE_OFFLOADS)) {
 329                 /* check if TSO is required */
 330                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 331                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 332                         ena_tx_ctx->tso_enable = true;
 333
 334                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 335                 }
 336
 337                 /* check if L3 checksum is needed */
 338                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 339                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 340                         ena_tx_ctx->l3_csum_enable = true;
 341
 342                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 343                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 344                 } else {
 345                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 346
 347                         /* set don't fragment (DF) flag */
 348                         if (mbuf->packet_type &
 349                                 (RTE_PTYPE_L4_NONFRAG
 350                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 351                                 ena_tx_ctx->df = true;
 352                 }
 353
 354                 /* check if L4 checksum is needed */
 355                 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
 356                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 357                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 358                         ena_tx_ctx->l4_csum_enable = true;
 359                 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
 360                                 PKT_TX_UDP_CKSUM) &&
 361                                 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 362                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 363                         ena_tx_ctx->l4_csum_enable = true;
 364                 } else {
 365                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 366                         ena_tx_ctx->l4_csum_enable = false;
 367                 }
 368
 369                 ena_meta->mss = mbuf->tso_segsz;
 370                 ena_meta->l3_hdr_len = mbuf->l3_len;
 371                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 372
 373                 ena_tx_ctx->meta_valid = true;
 374         } else if (disable_meta_caching) {
 375                 memset(ena_meta, 0, sizeof(*ena_meta));
 376                 ena_tx_ctx->meta_valid = true;
 377         } else {
 378                 ena_tx_ctx->meta_valid = false;
 379         }
 380 }
 381
 382 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 383 {
 384         if (likely(req_id < rx_ring->ring_size))
 385                 return 0;
 386
 387         PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id);
 388
 389         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 390         rx_ring->adapter->trigger_reset = true;
 391         ++rx_ring->rx_stats.bad_req_id;
 392
 393         return -EFAULT;
 394 }
 395
 396 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 397 {
 398         struct ena_tx_buffer *tx_info = NULL;
 399
 400         if (likely(req_id < tx_ring->ring_size)) {
 401                 tx_info = &tx_ring->tx_buffer_info[req_id];
 402                 if (likely(tx_info->mbuf))
 403                         return 0;
 404         }
 405
 406         if (tx_info)
 407                 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 408         else
 409                 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 410
 411         /* Trigger device reset */
 412         ++tx_ring->tx_stats.bad_req_id;
 413         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 414         tx_ring->adapter->trigger_reset = true;
 415         return -EFAULT;
 416 }
 417
 418 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 419 {
 420         struct ena_admin_host_info *host_info;
 421         int rc;
 422
 423         /* Allocate only the host info */
 424         rc = ena_com_allocate_host_info(ena_dev);
 425         if (rc) {
 426                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 427                 return;
 428         }
 429
 430         host_info = ena_dev->host_attr.host_info;
 431
 432         host_info->os_type = ENA_ADMIN_OS_DPDK;
 433         host_info->kernel_ver = RTE_VERSION;
 434         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 435                 sizeof(host_info->kernel_ver_str));
 436         host_info->os_dist = RTE_VERSION;
 437         strlcpy((char *)host_info->os_dist_str, rte_version(),
 438                 sizeof(host_info->os_dist_str));
 439         host_info->driver_version =
 440                 (DRV_MODULE_VER_MAJOR) |
 441                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 442                 (DRV_MODULE_VER_SUBMINOR <<
 443                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 444         host_info->num_cpus = rte_lcore_count();
 445
 446         host_info->driver_supported_features =
 447                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
 448
 449         rc = ena_com_set_host_attributes(ena_dev);
 450         if (rc) {
 451                 if (rc == -ENA_COM_UNSUPPORTED)
 452                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 453                 else
 454                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 455
 456                 goto err;
 457         }
 458
 459         return;
 460
 461 err:
 462         ena_com_delete_host_info(ena_dev);
 463 }
 464
 465 /* This function calculates the number of xstats based on the current config */
 466 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
 467 {
 468         return ENA_STATS_ARRAY_GLOBAL +
 469                 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 470                 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 471 }
 472
 473 static void ena_config_debug_area(struct ena_adapter *adapter)
 474 {
 475         u32 debug_area_size;
 476         int rc, ss_count;
 477
 478         ss_count = ena_xstats_calc_num(adapter->rte_dev);
 479
 480         /* allocate 32 bytes for each string and 64bit for the value */
 481         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 482
 483         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 484         if (rc) {
 485                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 486                 return;
 487         }
 488
 489         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 490         if (rc) {
 491                 if (rc == -ENA_COM_UNSUPPORTED)
 492                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 493                 else
 494                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 495
 496                 goto err;
 497         }
 498
 499         return;
 500 err:
 501         ena_com_delete_debug_area(&adapter->ena_dev);
 502 }
 503
 504 static void ena_close(struct rte_eth_dev *dev)
 505 {
 506         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 507         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 508         struct ena_adapter *adapter = dev->data->dev_private;
 509
 510         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 511                 ena_stop(dev);
 512         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 513
 514         ena_rx_queue_release_all(dev);
 515         ena_tx_queue_release_all(dev);
 516
 517         rte_free(adapter->drv_stats);
 518         adapter->drv_stats = NULL;
 519
 520         rte_intr_disable(intr_handle);
 521         rte_intr_callback_unregister(intr_handle,
 522                                      ena_interrupt_handler_rte,
 523                                      adapter);
 524
 525         /*
 526          * MAC is not allocated dynamically. Setting NULL should prevent from
 527          * release of the resource in the rte_eth_dev_release_port().
 528          */
 529         dev->data->mac_addrs = NULL;
 530 }
 531
 532 static int
 533 ena_dev_reset(struct rte_eth_dev *dev)
 534 {
 535         int rc = 0;
 536
 537         ena_destroy_device(dev);
 538         rc = eth_ena_dev_init(dev);
 539         if (rc)
 540                 PMD_INIT_LOG(CRIT, "Cannot initialize device");
 541
 542         return rc;
 543 }
 544
 545 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 546                                struct rte_eth_rss_reta_entry64 *reta_conf,
 547                                uint16_t reta_size)
 548 {
 549         struct ena_adapter *adapter = dev->data->dev_private;
 550         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 551         int rc, i;
 552         u16 entry_value;
 553         int conf_idx;
 554         int idx;
 555
 556         if ((reta_size == 0) || (reta_conf == NULL))
 557                 return -EINVAL;
 558
 559         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 560                 PMD_DRV_LOG(WARNING,
 561                         "indirection table %d is bigger than supported (%d)\n",
 562                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 563                 return -EINVAL;
 564         }
 565
 566         for (i = 0 ; i < reta_size ; i++) {
 567                 /* each reta_conf is for 64 entries.
 568                  * to support 128 we use 2 conf of 64
 569                  */
 570                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 571                 idx = i % RTE_RETA_GROUP_SIZE;
 572                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 573                         entry_value =
 574                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 575
 576                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 577                                                                i,
 578                                                                entry_value);
 579                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 580                                 PMD_DRV_LOG(ERR,
 581                                         "Cannot fill indirect table\n");
 582                                 return rc;
 583                         }
 584                 }
 585         }
 586
 587         rc = ena_com_indirect_table_set(ena_dev);
 588         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 589                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 590                 return rc;
 591         }
 592
 593         PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries  for port %d\n",
 594                 __func__, reta_size, adapter->rte_dev->data->port_id);
 595
 596         return 0;
 597 }
 598
 599 /* Query redirection table. */
 600 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 601                               struct rte_eth_rss_reta_entry64 *reta_conf,
 602                               uint16_t reta_size)
 603 {
 604         struct ena_adapter *adapter = dev->data->dev_private;
 605         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 606         int rc;
 607         int i;
 608         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 609         int reta_conf_idx;
 610         int reta_idx;
 611
 612         if (reta_size == 0 || reta_conf == NULL ||
 613             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 614                 return -EINVAL;
 615
 616         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 617         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 618                 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
 619                 return -ENOTSUP;
 620         }
 621
 622         for (i = 0 ; i < reta_size ; i++) {
 623                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 624                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 625                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 626                         reta_conf[reta_conf_idx].reta[reta_idx] =
 627                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 628         }
 629
 630         return 0;
 631 }
 632
 633 static int ena_rss_init_default(struct ena_adapter *adapter)
 634 {
 635         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 636         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 637         int rc, i;
 638         u32 val;
 639
 640         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 641         if (unlikely(rc)) {
 642                 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
 643                 goto err_rss_init;
 644         }
 645
 646         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 647                 val = i % nb_rx_queues;
 648                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 649                                                        ENA_IO_RXQ_IDX(val));
 650                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 651                         PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
 652                         goto err_fill_indir;
 653                 }
 654         }
 655
 656         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 657                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 658         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 659                 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
 660                 goto err_fill_indir;
 661         }
 662
 663         rc = ena_com_set_default_hash_ctrl(ena_dev);
 664         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 665                 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
 666                 goto err_fill_indir;
 667         }
 668
 669         rc = ena_com_indirect_table_set(ena_dev);
 670         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 671                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 672                 goto err_fill_indir;
 673         }
 674         PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
 675                 adapter->rte_dev->data->port_id);
 676
 677         return 0;
 678
 679 err_fill_indir:
 680         ena_com_rss_destroy(ena_dev);
 681 err_rss_init:
 682
 683         return rc;
 684 }
 685
 686 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 687 {
 688         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 689         int nb_queues = dev->data->nb_rx_queues;
 690         int i;
 691
 692         for (i = 0; i < nb_queues; i++)
 693                 ena_rx_queue_release(queues[i]);
 694 }
 695
 696 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 697 {
 698         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 699         int nb_queues = dev->data->nb_tx_queues;
 700         int i;
 701
 702         for (i = 0; i < nb_queues; i++)
 703                 ena_tx_queue_release(queues[i]);
 704 }
 705
 706 static void ena_rx_queue_release(void *queue)
 707 {
 708         struct ena_ring *ring = (struct ena_ring *)queue;
 709
 710         /* Free ring resources */
 711         if (ring->rx_buffer_info)
 712                 rte_free(ring->rx_buffer_info);
 713         ring->rx_buffer_info = NULL;
 714
 715         if (ring->rx_refill_buffer)
 716                 rte_free(ring->rx_refill_buffer);
 717         ring->rx_refill_buffer = NULL;
 718
 719         if (ring->empty_rx_reqs)
 720                 rte_free(ring->empty_rx_reqs);
 721         ring->empty_rx_reqs = NULL;
 722
 723         ring->configured = 0;
 724
 725         PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
 726                 ring->port_id, ring->id);
 727 }
 728
 729 static void ena_tx_queue_release(void *queue)
 730 {
 731         struct ena_ring *ring = (struct ena_ring *)queue;
 732
 733         /* Free ring resources */
 734         if (ring->push_buf_intermediate_buf)
 735                 rte_free(ring->push_buf_intermediate_buf);
 736
 737         if (ring->tx_buffer_info)
 738                 rte_free(ring->tx_buffer_info);
 739
 740         if (ring->empty_tx_reqs)
 741                 rte_free(ring->empty_tx_reqs);
 742
 743         ring->empty_tx_reqs = NULL;
 744         ring->tx_buffer_info = NULL;
 745         ring->push_buf_intermediate_buf = NULL;
 746
 747         ring->configured = 0;
 748
 749         PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
 750                 ring->port_id, ring->id);
 751 }
 752
 753 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 754 {
 755         unsigned int i;
 756
 757         for (i = 0; i < ring->ring_size; ++i) {
 758                 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
 759                 if (rx_info->mbuf) {
 760                         rte_mbuf_raw_free(rx_info->mbuf);
 761                         rx_info->mbuf = NULL;
 762                 }
 763         }
 764 }
 765
 766 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 767 {
 768         unsigned int i;
 769
 770         for (i = 0; i < ring->ring_size; ++i) {
 771                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 772
 773                 if (tx_buf->mbuf)
 774                         rte_pktmbuf_free(tx_buf->mbuf);
 775         }
 776 }
 777
 778 static int ena_link_update(struct rte_eth_dev *dev,
 779                            __rte_unused int wait_to_complete)
 780 {
 781         struct rte_eth_link *link = &dev->data->dev_link;
 782         struct ena_adapter *adapter = dev->data->dev_private;
 783
 784         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 785         link->link_speed = ETH_SPEED_NUM_NONE;
 786         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 787
 788         return 0;
 789 }
 790
 791 static int ena_queue_start_all(struct rte_eth_dev *dev,
 792                                enum ena_ring_type ring_type)
 793 {
 794         struct ena_adapter *adapter = dev->data->dev_private;
 795         struct ena_ring *queues = NULL;
 796         int nb_queues;
 797         int i = 0;
 798         int rc = 0;
 799
 800         if (ring_type == ENA_RING_TYPE_RX) {
 801                 queues = adapter->rx_ring;
 802                 nb_queues = dev->data->nb_rx_queues;
 803         } else {
 804                 queues = adapter->tx_ring;
 805                 nb_queues = dev->data->nb_tx_queues;
 806         }
 807         for (i = 0; i < nb_queues; i++) {
 808                 if (queues[i].configured) {
 809                         if (ring_type == ENA_RING_TYPE_RX) {
 810                                 ena_assert_msg(
 811                                         dev->data->rx_queues[i] == &queues[i],
 812                                         "Inconsistent state of rx queues\n");
 813                         } else {
 814                                 ena_assert_msg(
 815                                         dev->data->tx_queues[i] == &queues[i],
 816                                         "Inconsistent state of tx queues\n");
 817                         }
 818
 819                         rc = ena_queue_start(&queues[i]);
 820
 821                         if (rc) {
 822                                 PMD_INIT_LOG(ERR,
 823                                              "failed to start queue %d type(%d)",
 824                                              i, ring_type);
 825                                 goto err;
 826                         }
 827                 }
 828         }
 829
 830         return 0;
 831
 832 err:
 833         while (i--)
 834                 if (queues[i].configured)
 835                         ena_queue_stop(&queues[i]);
 836
 837         return rc;
 838 }
 839
 840 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 841 {
 842         uint32_t max_frame_len = adapter->max_mtu;
 843
 844         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 845             DEV_RX_OFFLOAD_JUMBO_FRAME)
 846                 max_frame_len =
 847                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 848
 849         return max_frame_len;
 850 }
 851
 852 static int ena_check_valid_conf(struct ena_adapter *adapter)
 853 {
 854         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 855
 856         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 857                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 858                                   "max mtu: %d, min mtu: %d",
 859                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 860                 return ENA_COM_UNSUPPORTED;
 861         }
 862
 863         return 0;
 864 }
 865
 866 static int
 867 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 868                        bool use_large_llq_hdr)
 869 {
 870         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 871         struct ena_com_dev *ena_dev = ctx->ena_dev;
 872         uint32_t max_tx_queue_size;
 873         uint32_t max_rx_queue_size;
 874
 875         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 876                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 877                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 878                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 879                         max_queue_ext->max_rx_sq_depth);
 880                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
 881
 882                 if (ena_dev->tx_mem_queue_type ==
 883                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 884                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 885                                 llq->max_llq_depth);
 886                 } else {
 887                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 888                                 max_queue_ext->max_tx_sq_depth);
 889                 }
 890
 891                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 892                         max_queue_ext->max_per_packet_rx_descs);
 893                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 894                         max_queue_ext->max_per_packet_tx_descs);
 895         } else {
 896                 struct ena_admin_queue_feature_desc *max_queues =
 897                         &ctx->get_feat_ctx->max_queues;
 898                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
 899                         max_queues->max_sq_depth);
 900                 max_tx_queue_size = max_queues->max_cq_depth;
 901
 902                 if (ena_dev->tx_mem_queue_type ==
 903                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 904                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 905                                 llq->max_llq_depth);
 906                 } else {
 907                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 908                                 max_queues->max_sq_depth);
 909                 }
 910
 911                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 912                         max_queues->max_packet_rx_descs);
 913                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 914                         max_queues->max_packet_tx_descs);
 915         }
 916
 917         /* Round down to the nearest power of 2 */
 918         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
 919         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
 920
 921         if (use_large_llq_hdr) {
 922                 if ((llq->entry_size_ctrl_supported &
 923                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
 924                     (ena_dev->tx_mem_queue_type ==
 925                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
 926                         max_tx_queue_size /= 2;
 927                         PMD_INIT_LOG(INFO,
 928                                 "Forcing large headers and decreasing maximum TX queue size to %d\n",
 929                                 max_tx_queue_size);
 930                 } else {
 931                         PMD_INIT_LOG(ERR,
 932                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
 933                 }
 934         }
 935
 936         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
 937                 PMD_INIT_LOG(ERR, "Invalid queue size");
 938                 return -EFAULT;
 939         }
 940
 941         ctx->max_tx_queue_size = max_tx_queue_size;
 942         ctx->max_rx_queue_size = max_rx_queue_size;
 943
 944         return 0;
 945 }
 946
 947 static void ena_stats_restart(struct rte_eth_dev *dev)
 948 {
 949         struct ena_adapter *adapter = dev->data->dev_private;
 950
 951         rte_atomic64_init(&adapter->drv_stats->ierrors);
 952         rte_atomic64_init(&adapter->drv_stats->oerrors);
 953         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 954         adapter->drv_stats->rx_drops = 0;
 955 }
 956
 957 static int ena_stats_get(struct rte_eth_dev *dev,
 958                           struct rte_eth_stats *stats)
 959 {
 960         struct ena_admin_basic_stats ena_stats;
 961         struct ena_adapter *adapter = dev->data->dev_private;
 962         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 963         int rc;
 964         int i;
 965         int max_rings_stats;
 966
 967         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 968                 return -ENOTSUP;
 969
 970         memset(&ena_stats, 0, sizeof(ena_stats));
 971         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 972         if (unlikely(rc)) {
 973                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 974                 return rc;
 975         }
 976
 977         /* Set of basic statistics from ENA */
 978         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 979                                           ena_stats.rx_pkts_low);
 980         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 981                                           ena_stats.tx_pkts_low);
 982         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 983                                         ena_stats.rx_bytes_low);
 984         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 985                                         ena_stats.tx_bytes_low);
 986
 987         /* Driver related stats */
 988         stats->imissed = adapter->drv_stats->rx_drops;
 989         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 990         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 991         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 992
 993         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
 994                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 995         for (i = 0; i < max_rings_stats; ++i) {
 996                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
 997
 998                 stats->q_ibytes[i] = rx_stats->bytes;
 999                 stats->q_ipackets[i] = rx_stats->cnt;
1000                 stats->q_errors[i] = rx_stats->bad_desc_num +
1001                         rx_stats->bad_req_id;
1002         }
1003
1004         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
1005                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1006         for (i = 0; i < max_rings_stats; ++i) {
1007                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1008
1009                 stats->q_obytes[i] = tx_stats->bytes;
1010                 stats->q_opackets[i] = tx_stats->cnt;
1011         }
1012
1013         return 0;
1014 }
1015
1016 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1017 {
1018         struct ena_adapter *adapter;
1019         struct ena_com_dev *ena_dev;
1020         int rc = 0;
1021
1022         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1023         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1024         adapter = dev->data->dev_private;
1025
1026         ena_dev = &adapter->ena_dev;
1027         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1028
1029         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1030                 PMD_DRV_LOG(ERR,
1031                         "Invalid MTU setting. new_mtu: %d "
1032                         "max mtu: %d min mtu: %d\n",
1033                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1034                 return -EINVAL;
1035         }
1036
1037         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1038         if (rc)
1039                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1040         else
1041                 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
1042
1043         return rc;
1044 }
1045
1046 static int ena_start(struct rte_eth_dev *dev)
1047 {
1048         struct ena_adapter *adapter = dev->data->dev_private;
1049         uint64_t ticks;
1050         int rc = 0;
1051
1052         rc = ena_check_valid_conf(adapter);
1053         if (rc)
1054                 return rc;
1055
1056         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1057         if (rc)
1058                 return rc;
1059
1060         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1061         if (rc)
1062                 goto err_start_tx;
1063
1064         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1065             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1066                 rc = ena_rss_init_default(adapter);
1067                 if (rc)
1068                         goto err_rss_init;
1069         }
1070
1071         ena_stats_restart(dev);
1072
1073         adapter->timestamp_wd = rte_get_timer_cycles();
1074         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1075
1076         ticks = rte_get_timer_hz();
1077         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1078                         ena_timer_wd_callback, adapter);
1079
1080         ++adapter->dev_stats.dev_start;
1081         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1082
1083         return 0;
1084
1085 err_rss_init:
1086         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1087 err_start_tx:
1088         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1089         return rc;
1090 }
1091
1092 static void ena_stop(struct rte_eth_dev *dev)
1093 {
1094         struct ena_adapter *adapter = dev->data->dev_private;
1095         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1096         int rc;
1097
1098         rte_timer_stop_sync(&adapter->timer_wd);
1099         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1100         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1101
1102         if (adapter->trigger_reset) {
1103                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1104                 if (rc)
1105                         PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1106         }
1107
1108         ++adapter->dev_stats.dev_stop;
1109         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1110 }
1111
1112 static int ena_create_io_queue(struct ena_ring *ring)
1113 {
1114         struct ena_adapter *adapter;
1115         struct ena_com_dev *ena_dev;
1116         struct ena_com_create_io_ctx ctx =
1117                 /* policy set to _HOST just to satisfy icc compiler */
1118                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1119                   0, 0, 0, 0, 0 };
1120         uint16_t ena_qid;
1121         unsigned int i;
1122         int rc;
1123
1124         adapter = ring->adapter;
1125         ena_dev = &adapter->ena_dev;
1126
1127         if (ring->type == ENA_RING_TYPE_TX) {
1128                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1129                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1130                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1131                 for (i = 0; i < ring->ring_size; i++)
1132                         ring->empty_tx_reqs[i] = i;
1133         } else {
1134                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1135                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1136                 for (i = 0; i < ring->ring_size; i++)
1137                         ring->empty_rx_reqs[i] = i;
1138         }
1139         ctx.queue_size = ring->ring_size;
1140         ctx.qid = ena_qid;
1141         ctx.msix_vector = -1; /* interrupts not used */
1142         ctx.numa_node = ring->numa_socket_id;
1143
1144         rc = ena_com_create_io_queue(ena_dev, &ctx);
1145         if (rc) {
1146                 PMD_DRV_LOG(ERR,
1147                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1148                         ring->id, ena_qid, rc);
1149                 return rc;
1150         }
1151
1152         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1153                                      &ring->ena_com_io_sq,
1154                                      &ring->ena_com_io_cq);
1155         if (rc) {
1156                 PMD_DRV_LOG(ERR,
1157                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1158                         ring->id, rc);
1159                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1160                 return rc;
1161         }
1162
1163         if (ring->type == ENA_RING_TYPE_TX)
1164                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1165
1166         return 0;
1167 }
1168
1169 static void ena_queue_stop(struct ena_ring *ring)
1170 {
1171         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1172
1173         if (ring->type == ENA_RING_TYPE_RX) {
1174                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1175                 ena_rx_queue_release_bufs(ring);
1176         } else {
1177                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1178                 ena_tx_queue_release_bufs(ring);
1179         }
1180 }
1181
1182 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1183                               enum ena_ring_type ring_type)
1184 {
1185         struct ena_adapter *adapter = dev->data->dev_private;
1186         struct ena_ring *queues = NULL;
1187         uint16_t nb_queues, i;
1188
1189         if (ring_type == ENA_RING_TYPE_RX) {
1190                 queues = adapter->rx_ring;
1191                 nb_queues = dev->data->nb_rx_queues;
1192         } else {
1193                 queues = adapter->tx_ring;
1194                 nb_queues = dev->data->nb_tx_queues;
1195         }
1196
1197         for (i = 0; i < nb_queues; ++i)
1198                 if (queues[i].configured)
1199                         ena_queue_stop(&queues[i]);
1200 }
1201
1202 static int ena_queue_start(struct ena_ring *ring)
1203 {
1204         int rc, bufs_num;
1205
1206         ena_assert_msg(ring->configured == 1,
1207                        "Trying to start unconfigured queue\n");
1208
1209         rc = ena_create_io_queue(ring);
1210         if (rc) {
1211                 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1212                 return rc;
1213         }
1214
1215         ring->next_to_clean = 0;
1216         ring->next_to_use = 0;
1217
1218         if (ring->type == ENA_RING_TYPE_TX) {
1219                 ring->tx_stats.available_desc =
1220                         ena_com_free_q_entries(ring->ena_com_io_sq);
1221                 return 0;
1222         }
1223
1224         bufs_num = ring->ring_size - 1;
1225         rc = ena_populate_rx_queue(ring, bufs_num);
1226         if (rc != bufs_num) {
1227                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1228                                          ENA_IO_RXQ_IDX(ring->id));
1229                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1230                 return ENA_COM_FAULT;
1231         }
1232
1233         return 0;
1234 }
1235
1236 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1237                               uint16_t queue_idx,
1238                               uint16_t nb_desc,
1239                               unsigned int socket_id,
1240                               const struct rte_eth_txconf *tx_conf)
1241 {
1242         struct ena_ring *txq = NULL;
1243         struct ena_adapter *adapter = dev->data->dev_private;
1244         unsigned int i;
1245
1246         txq = &adapter->tx_ring[queue_idx];
1247
1248         if (txq->configured) {
1249                 PMD_DRV_LOG(CRIT,
1250                         "API violation. Queue %d is already configured\n",
1251                         queue_idx);
1252                 return ENA_COM_FAULT;
1253         }
1254
1255         if (!rte_is_power_of_2(nb_desc)) {
1256                 PMD_DRV_LOG(ERR,
1257                         "Unsupported size of TX queue: %d is not a power of 2.\n",
1258                         nb_desc);
1259                 return -EINVAL;
1260         }
1261
1262         if (nb_desc > adapter->max_tx_ring_size) {
1263                 PMD_DRV_LOG(ERR,
1264                         "Unsupported size of TX queue (max size: %d)\n",
1265                         adapter->max_tx_ring_size);
1266                 return -EINVAL;
1267         }
1268
1269         if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1270                 nb_desc = adapter->max_tx_ring_size;
1271
1272         txq->port_id = dev->data->port_id;
1273         txq->next_to_clean = 0;
1274         txq->next_to_use = 0;
1275         txq->ring_size = nb_desc;
1276         txq->size_mask = nb_desc - 1;
1277         txq->numa_socket_id = socket_id;
1278
1279         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1280                                           sizeof(struct ena_tx_buffer) *
1281                                           txq->ring_size,
1282                                           RTE_CACHE_LINE_SIZE);
1283         if (!txq->tx_buffer_info) {
1284                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1285                 return -ENOMEM;
1286         }
1287
1288         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1289                                          sizeof(u16) * txq->ring_size,
1290                                          RTE_CACHE_LINE_SIZE);
1291         if (!txq->empty_tx_reqs) {
1292                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1293                 rte_free(txq->tx_buffer_info);
1294                 return -ENOMEM;
1295         }
1296
1297         txq->push_buf_intermediate_buf =
1298                 rte_zmalloc("txq->push_buf_intermediate_buf",
1299                             txq->tx_max_header_size,
1300                             RTE_CACHE_LINE_SIZE);
1301         if (!txq->push_buf_intermediate_buf) {
1302                 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1303                 rte_free(txq->tx_buffer_info);
1304                 rte_free(txq->empty_tx_reqs);
1305                 return -ENOMEM;
1306         }
1307
1308         for (i = 0; i < txq->ring_size; i++)
1309                 txq->empty_tx_reqs[i] = i;
1310
1311         if (tx_conf != NULL) {
1312                 txq->offloads =
1313                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1314         }
1315         /* Store pointer to this queue in upper layer */
1316         txq->configured = 1;
1317         dev->data->tx_queues[queue_idx] = txq;
1318
1319         return 0;
1320 }
1321
1322 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1323                               uint16_t queue_idx,
1324                               uint16_t nb_desc,
1325                               unsigned int socket_id,
1326                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1327                               struct rte_mempool *mp)
1328 {
1329         struct ena_adapter *adapter = dev->data->dev_private;
1330         struct ena_ring *rxq = NULL;
1331         size_t buffer_size;
1332         int i;
1333
1334         rxq = &adapter->rx_ring[queue_idx];
1335         if (rxq->configured) {
1336                 PMD_DRV_LOG(CRIT,
1337                         "API violation. Queue %d is already configured\n",
1338                         queue_idx);
1339                 return ENA_COM_FAULT;
1340         }
1341
1342         if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1343                 nb_desc = adapter->max_rx_ring_size;
1344
1345         if (!rte_is_power_of_2(nb_desc)) {
1346                 PMD_DRV_LOG(ERR,
1347                         "Unsupported size of RX queue: %d is not a power of 2.\n",
1348                         nb_desc);
1349                 return -EINVAL;
1350         }
1351
1352         if (nb_desc > adapter->max_rx_ring_size) {
1353                 PMD_DRV_LOG(ERR,
1354                         "Unsupported size of RX queue (max size: %d)\n",
1355                         adapter->max_rx_ring_size);
1356                 return -EINVAL;
1357         }
1358
1359         /* ENA isn't supporting buffers smaller than 1400 bytes */
1360         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1361         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1362                 PMD_DRV_LOG(ERR,
1363                         "Unsupported size of RX buffer: %zu (min size: %d)\n",
1364                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1365                 return -EINVAL;
1366         }
1367
1368         rxq->port_id = dev->data->port_id;
1369         rxq->next_to_clean = 0;
1370         rxq->next_to_use = 0;
1371         rxq->ring_size = nb_desc;
1372         rxq->size_mask = nb_desc - 1;
1373         rxq->numa_socket_id = socket_id;
1374         rxq->mb_pool = mp;
1375
1376         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1377                 sizeof(struct ena_rx_buffer) * nb_desc,
1378                 RTE_CACHE_LINE_SIZE);
1379         if (!rxq->rx_buffer_info) {
1380                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1381                 return -ENOMEM;
1382         }
1383
1384         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1385                                             sizeof(struct rte_mbuf *) * nb_desc,
1386                                             RTE_CACHE_LINE_SIZE);
1387
1388         if (!rxq->rx_refill_buffer) {
1389                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1390                 rte_free(rxq->rx_buffer_info);
1391                 rxq->rx_buffer_info = NULL;
1392                 return -ENOMEM;
1393         }
1394
1395         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1396                                          sizeof(uint16_t) * nb_desc,
1397                                          RTE_CACHE_LINE_SIZE);
1398         if (!rxq->empty_rx_reqs) {
1399                 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1400                 rte_free(rxq->rx_buffer_info);
1401                 rxq->rx_buffer_info = NULL;
1402                 rte_free(rxq->rx_refill_buffer);
1403                 rxq->rx_refill_buffer = NULL;
1404                 return -ENOMEM;
1405         }
1406
1407         for (i = 0; i < nb_desc; i++)
1408                 rxq->empty_rx_reqs[i] = i;
1409
1410         /* Store pointer to this queue in upper layer */
1411         rxq->configured = 1;
1412         dev->data->rx_queues[queue_idx] = rxq;
1413
1414         return 0;
1415 }
1416
1417 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1418 {
1419         unsigned int i;
1420         int rc;
1421         uint16_t next_to_use = rxq->next_to_use;
1422         uint16_t in_use, req_id;
1423         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1424
1425         if (unlikely(!count))
1426                 return 0;
1427
1428         in_use = rxq->ring_size - 1 -
1429                 ena_com_free_q_entries(rxq->ena_com_io_sq);
1430         ena_assert_msg(((in_use + count) < rxq->ring_size),
1431                 "bad ring state\n");
1432
1433         /* get resources for incoming packets */
1434         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1435         if (unlikely(rc < 0)) {
1436                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1437                 ++rxq->rx_stats.mbuf_alloc_fail;
1438                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1439                 return 0;
1440         }
1441
1442         for (i = 0; i < count; i++) {
1443                 struct rte_mbuf *mbuf = mbufs[i];
1444                 struct ena_com_buf ebuf;
1445                 struct ena_rx_buffer *rx_info;
1446
1447                 if (likely((i + 4) < count))
1448                         rte_prefetch0(mbufs[i + 4]);
1449
1450                 req_id = rxq->empty_rx_reqs[next_to_use];
1451                 rc = validate_rx_req_id(rxq, req_id);
1452                 if (unlikely(rc))
1453                         break;
1454
1455                 rx_info = &rxq->rx_buffer_info[req_id];
1456
1457                 /* prepare physical address for DMA transaction */
1458                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1459                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1460                 /* pass resource to device */
1461                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1462                                                 &ebuf, req_id);
1463                 if (unlikely(rc)) {
1464                         PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1465                         break;
1466                 }
1467                 rx_info->mbuf = mbuf;
1468                 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1469         }
1470
1471         if (unlikely(i < count)) {
1472                 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1473                         "buffers (from %d)\n", rxq->id, i, count);
1474                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1475                                      count - i);
1476                 ++rxq->rx_stats.refill_partial;
1477         }
1478
1479         /* When we submitted free recources to device... */
1480         if (likely(i > 0)) {
1481                 /* ...let HW know that it can fill buffers with data. */
1482                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1483
1484                 rxq->next_to_use = next_to_use;
1485         }
1486
1487         return i;
1488 }
1489
1490 static int ena_device_init(struct ena_com_dev *ena_dev,
1491                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1492                            bool *wd_state)
1493 {
1494         uint32_t aenq_groups;
1495         int rc;
1496         bool readless_supported;
1497
1498         /* Initialize mmio registers */
1499         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1500         if (rc) {
1501                 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1502                 return rc;
1503         }
1504
1505         /* The PCIe configuration space revision id indicate if mmio reg
1506          * read is disabled.
1507          */
1508         readless_supported =
1509                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1510                                & ENA_MMIO_DISABLE_REG_READ);
1511         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1512
1513         /* reset device */
1514         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1515         if (rc) {
1516                 PMD_DRV_LOG(ERR, "cannot reset device\n");
1517                 goto err_mmio_read_less;
1518         }
1519
1520         /* check FW version */
1521         rc = ena_com_validate_version(ena_dev);
1522         if (rc) {
1523                 PMD_DRV_LOG(ERR, "device version is too low\n");
1524                 goto err_mmio_read_less;
1525         }
1526
1527         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1528
1529         /* ENA device administration layer init */
1530         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1531         if (rc) {
1532                 PMD_DRV_LOG(ERR,
1533                         "cannot initialize ena admin queue with device\n");
1534                 goto err_mmio_read_less;
1535         }
1536
1537         /* To enable the msix interrupts the driver needs to know the number
1538          * of queues. So the driver uses polling mode to retrieve this
1539          * information.
1540          */
1541         ena_com_set_admin_polling_mode(ena_dev, true);
1542
1543         ena_config_host_info(ena_dev);
1544
1545         /* Get Device Attributes and features */
1546         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1547         if (rc) {
1548                 PMD_DRV_LOG(ERR,
1549                         "cannot get attribute for ena device rc= %d\n", rc);
1550                 goto err_admin_init;
1551         }
1552
1553         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1554                       BIT(ENA_ADMIN_NOTIFICATION) |
1555                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1556                       BIT(ENA_ADMIN_FATAL_ERROR) |
1557                       BIT(ENA_ADMIN_WARNING);
1558
1559         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1560         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1561         if (rc) {
1562                 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1563                 goto err_admin_init;
1564         }
1565
1566         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1567
1568         return 0;
1569
1570 err_admin_init:
1571         ena_com_admin_destroy(ena_dev);
1572
1573 err_mmio_read_less:
1574         ena_com_mmio_reg_read_request_destroy(ena_dev);
1575
1576         return rc;
1577 }
1578
1579 static void ena_interrupt_handler_rte(void *cb_arg)
1580 {
1581         struct ena_adapter *adapter = cb_arg;
1582         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1583
1584         ena_com_admin_q_comp_intr_handler(ena_dev);
1585         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1586                 ena_com_aenq_intr_handler(ena_dev, adapter);
1587 }
1588
1589 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1590 {
1591         if (!adapter->wd_state)
1592                 return;
1593
1594         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1595                 return;
1596
1597         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1598             adapter->keep_alive_timeout)) {
1599                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1600                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1601                 adapter->trigger_reset = true;
1602                 ++adapter->dev_stats.wd_expired;
1603         }
1604 }
1605
1606 /* Check if admin queue is enabled */
1607 static void check_for_admin_com_state(struct ena_adapter *adapter)
1608 {
1609         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1610                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1611                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1612                 adapter->trigger_reset = true;
1613         }
1614 }
1615
1616 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1617                                   void *arg)
1618 {
1619         struct ena_adapter *adapter = arg;
1620         struct rte_eth_dev *dev = adapter->rte_dev;
1621
1622         check_for_missing_keep_alive(adapter);
1623         check_for_admin_com_state(adapter);
1624
1625         if (unlikely(adapter->trigger_reset)) {
1626                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1627                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1628                         NULL);
1629         }
1630 }
1631
1632 static inline void
1633 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1634                                struct ena_admin_feature_llq_desc *llq,
1635                                bool use_large_llq_hdr)
1636 {
1637         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1638         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1639         llq_config->llq_num_decs_before_header =
1640                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1641
1642         if (use_large_llq_hdr &&
1643             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1644                 llq_config->llq_ring_entry_size =
1645                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1646                 llq_config->llq_ring_entry_size_value = 256;
1647         } else {
1648                 llq_config->llq_ring_entry_size =
1649                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1650                 llq_config->llq_ring_entry_size_value = 128;
1651         }
1652 }
1653
1654 static int
1655 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1656                                 struct ena_com_dev *ena_dev,
1657                                 struct ena_admin_feature_llq_desc *llq,
1658                                 struct ena_llq_configurations *llq_default_configurations)
1659 {
1660         int rc;
1661         u32 llq_feature_mask;
1662
1663         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1664         if (!(ena_dev->supported_features & llq_feature_mask)) {
1665                 PMD_DRV_LOG(INFO,
1666                         "LLQ is not supported. Fallback to host mode policy.\n");
1667                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1668                 return 0;
1669         }
1670
1671         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1672         if (unlikely(rc)) {
1673                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1674                         "Fallback to host mode policy.");
1675                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1676                 return 0;
1677         }
1678
1679         /* Nothing to config, exit */
1680         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1681                 return 0;
1682
1683         if (!adapter->dev_mem_base) {
1684                 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1685                         "Fallback to host mode policy.\n.");
1686                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1687                 return 0;
1688         }
1689
1690         ena_dev->mem_bar = adapter->dev_mem_base;
1691
1692         return 0;
1693 }
1694
1695 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1696         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1697 {
1698         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1699
1700         /* Regular queues capabilities */
1701         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1702                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1703                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1704                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1705                                     max_queue_ext->max_rx_cq_num);
1706                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1707                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1708         } else {
1709                 struct ena_admin_queue_feature_desc *max_queues =
1710                         &get_feat_ctx->max_queues;
1711                 io_tx_sq_num = max_queues->max_sq_num;
1712                 io_tx_cq_num = max_queues->max_cq_num;
1713                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1714         }
1715
1716         /* In case of LLQ use the llq number in the get feature cmd */
1717         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1718                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1719
1720         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1721         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1722         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1723
1724         if (unlikely(max_num_io_queues == 0)) {
1725                 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1726                 return -EFAULT;
1727         }
1728
1729         return max_num_io_queues;
1730 }
1731
1732 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1733 {
1734         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1735         struct rte_pci_device *pci_dev;
1736         struct rte_intr_handle *intr_handle;
1737         struct ena_adapter *adapter = eth_dev->data->dev_private;
1738         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1739         struct ena_com_dev_get_features_ctx get_feat_ctx;
1740         struct ena_llq_configurations llq_config;
1741         const char *queue_type_str;
1742         uint32_t max_num_io_queues;
1743         int rc;
1744         static int adapters_found;
1745         bool disable_meta_caching;
1746         bool wd_state;
1747
1748         eth_dev->dev_ops = &ena_dev_ops;
1749         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1750         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1751         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1752
1753         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1754                 return 0;
1755
1756         memset(adapter, 0, sizeof(struct ena_adapter));
1757         ena_dev = &adapter->ena_dev;
1758
1759         adapter->rte_eth_dev_data = eth_dev->data;
1760         adapter->rte_dev = eth_dev;
1761
1762         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1763         adapter->pdev = pci_dev;
1764
1765         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1766                      pci_dev->addr.domain,
1767                      pci_dev->addr.bus,
1768                      pci_dev->addr.devid,
1769                      pci_dev->addr.function);
1770
1771         intr_handle = &pci_dev->intr_handle;
1772
1773         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1774         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1775
1776         if (!adapter->regs) {
1777                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1778                              ENA_REGS_BAR);
1779                 return -ENXIO;
1780         }
1781
1782         ena_dev->reg_bar = adapter->regs;
1783         ena_dev->dmadev = adapter->pdev;
1784
1785         adapter->id_number = adapters_found;
1786
1787         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1788                  adapter->id_number);
1789
1790         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1791         if (rc != 0) {
1792                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1793                 goto err;
1794         }
1795
1796         /* device specific initialization routine */
1797         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1798         if (rc) {
1799                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1800                 goto err;
1801         }
1802         adapter->wd_state = wd_state;
1803
1804         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1805                 adapter->use_large_llq_hdr);
1806         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1807                                              &get_feat_ctx.llq, &llq_config);
1808         if (unlikely(rc)) {
1809                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1810                 return rc;
1811         }
1812
1813         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1814                 queue_type_str = "Regular";
1815         else
1816                 queue_type_str = "Low latency";
1817         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1818
1819         calc_queue_ctx.ena_dev = ena_dev;
1820         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1821
1822         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1823         rc = ena_calc_io_queue_size(&calc_queue_ctx,
1824                 adapter->use_large_llq_hdr);
1825         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1826                 rc = -EFAULT;
1827                 goto err_device_destroy;
1828         }
1829
1830         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1831         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1832         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1833         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1834         adapter->max_num_io_queues = max_num_io_queues;
1835
1836         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1837                 disable_meta_caching =
1838                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1839                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
1840         } else {
1841                 disable_meta_caching = false;
1842         }
1843
1844         /* prepare ring structures */
1845         ena_init_rings(adapter, disable_meta_caching);
1846
1847         ena_config_debug_area(adapter);
1848
1849         /* Set max MTU for this device */
1850         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1851
1852         /* set device support for offloads */
1853         adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1854                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1855         adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1856                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1857         adapter->offloads.rx_csum_supported =
1858                 (get_feat_ctx.offload.rx_supported &
1859                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1860
1861         /* Copy MAC address and point DPDK to it */
1862         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1863         rte_ether_addr_copy((struct rte_ether_addr *)
1864                         get_feat_ctx.dev_attr.mac_addr,
1865                         (struct rte_ether_addr *)adapter->mac_addr);
1866
1867         /*
1868          * Pass the information to the rte_eth_dev_close() that it should also
1869          * release the private port resources.
1870          */
1871         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1872
1873         adapter->drv_stats = rte_zmalloc("adapter stats",
1874                                          sizeof(*adapter->drv_stats),
1875                                          RTE_CACHE_LINE_SIZE);
1876         if (!adapter->drv_stats) {
1877                 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1878                 rc = -ENOMEM;
1879                 goto err_delete_debug_area;
1880         }
1881
1882         rte_intr_callback_register(intr_handle,
1883                                    ena_interrupt_handler_rte,
1884                                    adapter);
1885         rte_intr_enable(intr_handle);
1886         ena_com_set_admin_polling_mode(ena_dev, false);
1887         ena_com_admin_aenq_enable(ena_dev);
1888
1889         if (adapters_found == 0)
1890                 rte_timer_subsystem_init();
1891         rte_timer_init(&adapter->timer_wd);
1892
1893         adapters_found++;
1894         adapter->state = ENA_ADAPTER_STATE_INIT;
1895
1896         return 0;
1897
1898 err_delete_debug_area:
1899         ena_com_delete_debug_area(ena_dev);
1900
1901 err_device_destroy:
1902         ena_com_delete_host_info(ena_dev);
1903         ena_com_admin_destroy(ena_dev);
1904
1905 err:
1906         return rc;
1907 }
1908
1909 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1910 {
1911         struct ena_adapter *adapter = eth_dev->data->dev_private;
1912         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1913
1914         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1915                 return;
1916
1917         ena_com_set_admin_running_state(ena_dev, false);
1918
1919         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1920                 ena_close(eth_dev);
1921
1922         ena_com_delete_debug_area(ena_dev);
1923         ena_com_delete_host_info(ena_dev);
1924
1925         ena_com_abort_admin_commands(ena_dev);
1926         ena_com_wait_for_abort_completion(ena_dev);
1927         ena_com_admin_destroy(ena_dev);
1928         ena_com_mmio_reg_read_request_destroy(ena_dev);
1929
1930         adapter->state = ENA_ADAPTER_STATE_FREE;
1931 }
1932
1933 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1934 {
1935         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1936                 return 0;
1937
1938         ena_destroy_device(eth_dev);
1939
1940         eth_dev->dev_ops = NULL;
1941         eth_dev->rx_pkt_burst = NULL;
1942         eth_dev->tx_pkt_burst = NULL;
1943         eth_dev->tx_pkt_prepare = NULL;
1944
1945         return 0;
1946 }
1947
1948 static int ena_dev_configure(struct rte_eth_dev *dev)
1949 {
1950         struct ena_adapter *adapter = dev->data->dev_private;
1951
1952         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1953
1954         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1955         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1956         return 0;
1957 }
1958
1959 static void ena_init_rings(struct ena_adapter *adapter,
1960                            bool disable_meta_caching)
1961 {
1962         size_t i;
1963
1964         for (i = 0; i < adapter->max_num_io_queues; i++) {
1965                 struct ena_ring *ring = &adapter->tx_ring[i];
1966
1967                 ring->configured = 0;
1968                 ring->type = ENA_RING_TYPE_TX;
1969                 ring->adapter = adapter;
1970                 ring->id = i;
1971                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1972                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1973                 ring->sgl_size = adapter->max_tx_sgl_size;
1974                 ring->disable_meta_caching = disable_meta_caching;
1975         }
1976
1977         for (i = 0; i < adapter->max_num_io_queues; i++) {
1978                 struct ena_ring *ring = &adapter->rx_ring[i];
1979
1980                 ring->configured = 0;
1981                 ring->type = ENA_RING_TYPE_RX;
1982                 ring->adapter = adapter;
1983                 ring->id = i;
1984                 ring->sgl_size = adapter->max_rx_sgl_size;
1985         }
1986 }
1987
1988 static int ena_infos_get(struct rte_eth_dev *dev,
1989                           struct rte_eth_dev_info *dev_info)
1990 {
1991         struct ena_adapter *adapter;
1992         struct ena_com_dev *ena_dev;
1993         uint64_t rx_feat = 0, tx_feat = 0;
1994
1995         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1996         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1997         adapter = dev->data->dev_private;
1998
1999         ena_dev = &adapter->ena_dev;
2000         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2001
2002         dev_info->speed_capa =
2003                         ETH_LINK_SPEED_1G   |
2004                         ETH_LINK_SPEED_2_5G |
2005                         ETH_LINK_SPEED_5G   |
2006                         ETH_LINK_SPEED_10G  |
2007                         ETH_LINK_SPEED_25G  |
2008                         ETH_LINK_SPEED_40G  |
2009                         ETH_LINK_SPEED_50G  |
2010                         ETH_LINK_SPEED_100G;
2011
2012         /* Set Tx & Rx features available for device */
2013         if (adapter->offloads.tso4_supported)
2014                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
2015
2016         if (adapter->offloads.tx_csum_supported)
2017                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
2018                         DEV_TX_OFFLOAD_UDP_CKSUM |
2019                         DEV_TX_OFFLOAD_TCP_CKSUM;
2020
2021         if (adapter->offloads.rx_csum_supported)
2022                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
2023                         DEV_RX_OFFLOAD_UDP_CKSUM  |
2024                         DEV_RX_OFFLOAD_TCP_CKSUM;
2025
2026         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2027
2028         /* Inform framework about available features */
2029         dev_info->rx_offload_capa = rx_feat;
2030         dev_info->rx_queue_offload_capa = rx_feat;
2031         dev_info->tx_offload_capa = tx_feat;
2032         dev_info->tx_queue_offload_capa = tx_feat;
2033
2034         dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
2035                                            ETH_RSS_UDP;
2036
2037         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2038         dev_info->max_rx_pktlen  = adapter->max_mtu;
2039         dev_info->max_mac_addrs = 1;
2040
2041         dev_info->max_rx_queues = adapter->max_num_io_queues;
2042         dev_info->max_tx_queues = adapter->max_num_io_queues;
2043         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2044
2045         adapter->tx_supported_offloads = tx_feat;
2046         adapter->rx_supported_offloads = rx_feat;
2047
2048         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2049         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2050         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2051                                         adapter->max_rx_sgl_size);
2052         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2053                                         adapter->max_rx_sgl_size);
2054
2055         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2056         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2057         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2058                                         adapter->max_tx_sgl_size);
2059         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2060                                         adapter->max_tx_sgl_size);
2061
2062         return 0;
2063 }
2064
2065 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2066 {
2067         mbuf->data_len = len;
2068         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2069         mbuf->refcnt = 1;
2070         mbuf->next = NULL;
2071 }
2072
2073 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2074                                     struct ena_com_rx_buf_info *ena_bufs,
2075                                     uint32_t descs,
2076                                     uint16_t *next_to_clean,
2077                                     uint8_t offset)
2078 {
2079         struct rte_mbuf *mbuf;
2080         struct rte_mbuf *mbuf_head;
2081         struct ena_rx_buffer *rx_info;
2082         uint16_t ntc, len, req_id, buf = 0;
2083
2084         if (unlikely(descs == 0))
2085                 return NULL;
2086
2087         ntc = *next_to_clean;
2088
2089         len = ena_bufs[buf].len;
2090         req_id = ena_bufs[buf].req_id;
2091         if (unlikely(validate_rx_req_id(rx_ring, req_id)))
2092                 return NULL;
2093
2094         rx_info = &rx_ring->rx_buffer_info[req_id];
2095
2096         mbuf = rx_info->mbuf;
2097         RTE_ASSERT(mbuf != NULL);
2098
2099         ena_init_rx_mbuf(mbuf, len);
2100
2101         /* Fill the mbuf head with the data specific for 1st segment. */
2102         mbuf_head = mbuf;
2103         mbuf_head->nb_segs = descs;
2104         mbuf_head->port = rx_ring->port_id;
2105         mbuf_head->pkt_len = len;
2106         mbuf_head->data_off += offset;
2107
2108         rx_info->mbuf = NULL;
2109         rx_ring->empty_rx_reqs[ntc] = req_id;
2110         ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2111
2112         while (--descs) {
2113                 ++buf;
2114                 len = ena_bufs[buf].len;
2115                 req_id = ena_bufs[buf].req_id;
2116                 if (unlikely(validate_rx_req_id(rx_ring, req_id))) {
2117                         rte_mbuf_raw_free(mbuf_head);
2118                         return NULL;
2119                 }
2120
2121                 rx_info = &rx_ring->rx_buffer_info[req_id];
2122                 RTE_ASSERT(rx_info->mbuf != NULL);
2123
2124                 /* Create an mbuf chain. */
2125                 mbuf->next = rx_info->mbuf;
2126                 mbuf = mbuf->next;
2127
2128                 ena_init_rx_mbuf(mbuf, len);
2129                 mbuf_head->pkt_len += len;
2130
2131                 rx_info->mbuf = NULL;
2132                 rx_ring->empty_rx_reqs[ntc] = req_id;
2133                 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2134         }
2135
2136         *next_to_clean = ntc;
2137
2138         return mbuf_head;
2139 }
2140
2141 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2142                                   uint16_t nb_pkts)
2143 {
2144         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2145         unsigned int free_queue_entries;
2146         unsigned int refill_threshold;
2147         uint16_t next_to_clean = rx_ring->next_to_clean;
2148         uint16_t descs_in_use;
2149         struct rte_mbuf *mbuf;
2150         uint16_t completed;
2151         struct ena_com_rx_ctx ena_rx_ctx;
2152         int i, rc = 0;
2153
2154         /* Check adapter state */
2155         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2156                 PMD_DRV_LOG(ALERT,
2157                         "Trying to receive pkts while device is NOT running\n");
2158                 return 0;
2159         }
2160
2161         descs_in_use = rx_ring->ring_size -
2162                 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2163         nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2164
2165         for (completed = 0; completed < nb_pkts; completed++) {
2166                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2167                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2168                 ena_rx_ctx.descs = 0;
2169                 ena_rx_ctx.pkt_offset = 0;
2170                 /* receive packet context */
2171                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2172                                     rx_ring->ena_com_io_sq,
2173                                     &ena_rx_ctx);
2174                 if (unlikely(rc)) {
2175                         PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2176                         rx_ring->adapter->reset_reason =
2177                                 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2178                         rx_ring->adapter->trigger_reset = true;
2179                         ++rx_ring->rx_stats.bad_desc_num;
2180                         return 0;
2181                 }
2182
2183                 mbuf = ena_rx_mbuf(rx_ring,
2184                         ena_rx_ctx.ena_bufs,
2185                         ena_rx_ctx.descs,
2186                         &next_to_clean,
2187                         ena_rx_ctx.pkt_offset);
2188                 if (unlikely(mbuf == NULL)) {
2189                         for (i = 0; i < ena_rx_ctx.descs; ++i) {
2190                                 rx_ring->empty_rx_reqs[next_to_clean] =
2191                                         rx_ring->ena_bufs[i].req_id;
2192                                 next_to_clean = ENA_IDX_NEXT_MASKED(
2193                                         next_to_clean, rx_ring->size_mask);
2194                         }
2195                         break;
2196                 }
2197
2198                 /* fill mbuf attributes if any */
2199                 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx);
2200
2201                 if (unlikely(mbuf->ol_flags &
2202                                 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2203                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2204                         ++rx_ring->rx_stats.bad_csum;
2205                 }
2206
2207                 mbuf->hash.rss = ena_rx_ctx.hash;
2208
2209                 rx_pkts[completed] = mbuf;
2210                 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2211         }
2212
2213         rx_ring->rx_stats.cnt += completed;
2214         rx_ring->next_to_clean = next_to_clean;
2215
2216         free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2217         refill_threshold =
2218                 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2219                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2220
2221         /* Burst refill to save doorbells, memory barriers, const interval */
2222         if (free_queue_entries > refill_threshold) {
2223                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2224                 ena_populate_rx_queue(rx_ring, free_queue_entries);
2225         }
2226
2227         return completed;
2228 }
2229
2230 static uint16_t
2231 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2232                 uint16_t nb_pkts)
2233 {
2234         int32_t ret;
2235         uint32_t i;
2236         struct rte_mbuf *m;
2237         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2238         struct rte_ipv4_hdr *ip_hdr;
2239         uint64_t ol_flags;
2240         uint16_t frag_field;
2241
2242         for (i = 0; i != nb_pkts; i++) {
2243                 m = tx_pkts[i];
2244                 ol_flags = m->ol_flags;
2245
2246                 if (!(ol_flags & PKT_TX_IPV4))
2247                         continue;
2248
2249                 /* If there was not L2 header length specified, assume it is
2250                  * length of the ethernet header.
2251                  */
2252                 if (unlikely(m->l2_len == 0))
2253                         m->l2_len = sizeof(struct rte_ether_hdr);
2254
2255                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2256                                                  m->l2_len);
2257                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2258
2259                 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2260                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2261
2262                         /* If IPv4 header has DF flag enabled and TSO support is
2263                          * disabled, partial chcecksum should not be calculated.
2264                          */
2265                         if (!tx_ring->adapter->offloads.tso4_supported)
2266                                 continue;
2267                 }
2268
2269                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2270                                 (ol_flags & PKT_TX_L4_MASK) ==
2271                                 PKT_TX_SCTP_CKSUM) {
2272                         rte_errno = ENOTSUP;
2273                         return i;
2274                 }
2275
2276 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2277                 ret = rte_validate_tx_offload(m);
2278                 if (ret != 0) {
2279                         rte_errno = -ret;
2280                         return i;
2281                 }
2282 #endif
2283
2284                 /* In case we are supposed to TSO and have DF not set (DF=0)
2285                  * hardware must be provided with partial checksum, otherwise
2286                  * it will take care of necessary calculations.
2287                  */
2288
2289                 ret = rte_net_intel_cksum_flags_prepare(m,
2290                         ol_flags & ~PKT_TX_TCP_SEG);
2291                 if (ret != 0) {
2292                         rte_errno = -ret;
2293                         return i;
2294                 }
2295         }
2296
2297         return i;
2298 }
2299
2300 static void ena_update_hints(struct ena_adapter *adapter,
2301                              struct ena_admin_ena_hw_hints *hints)
2302 {
2303         if (hints->admin_completion_tx_timeout)
2304                 adapter->ena_dev.admin_queue.completion_timeout =
2305                         hints->admin_completion_tx_timeout * 1000;
2306
2307         if (hints->mmio_read_timeout)
2308                 /* convert to usec */
2309                 adapter->ena_dev.mmio_read.reg_read_to =
2310                         hints->mmio_read_timeout * 1000;
2311
2312         if (hints->driver_watchdog_timeout) {
2313                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2314                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2315                 else
2316                         // Convert msecs to ticks
2317                         adapter->keep_alive_timeout =
2318                                 (hints->driver_watchdog_timeout *
2319                                 rte_get_timer_hz()) / 1000;
2320         }
2321 }
2322
2323 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2324                                         struct rte_mbuf *mbuf)
2325 {
2326         struct ena_com_dev *ena_dev;
2327         int num_segments, header_len, rc;
2328
2329         ena_dev = &tx_ring->adapter->ena_dev;
2330         num_segments = mbuf->nb_segs;
2331         header_len = mbuf->data_len;
2332
2333         if (likely(num_segments < tx_ring->sgl_size))
2334                 return 0;
2335
2336         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2337             (num_segments == tx_ring->sgl_size) &&
2338             (header_len < tx_ring->tx_max_header_size))
2339                 return 0;
2340
2341         ++tx_ring->tx_stats.linearize;
2342         rc = rte_pktmbuf_linearize(mbuf);
2343         if (unlikely(rc)) {
2344                 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2345                 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2346                 ++tx_ring->tx_stats.linearize_failed;
2347                 return rc;
2348         }
2349
2350         return rc;
2351 }
2352
2353 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2354         struct ena_tx_buffer *tx_info,
2355         struct rte_mbuf *mbuf,
2356         void **push_header,
2357         uint16_t *header_len)
2358 {
2359         struct ena_com_buf *ena_buf;
2360         uint16_t delta, seg_len, push_len;
2361
2362         delta = 0;
2363         seg_len = mbuf->data_len;
2364
2365         tx_info->mbuf = mbuf;
2366         ena_buf = tx_info->bufs;
2367
2368         if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2369                 /*
2370                  * Tx header might be (and will be in most cases) smaller than
2371                  * tx_max_header_size. But it's not an issue to send more data
2372                  * to the device, than actually needed if the mbuf size is
2373                  * greater than tx_max_header_size.
2374                  */
2375                 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2376                 *header_len = push_len;
2377
2378                 if (likely(push_len <= seg_len)) {
2379                         /* If the push header is in the single segment, then
2380                          * just point it to the 1st mbuf data.
2381                          */
2382                         *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2383                 } else {
2384                         /* If the push header lays in the several segments, copy
2385                          * it to the intermediate buffer.
2386                          */
2387                         rte_pktmbuf_read(mbuf, 0, push_len,
2388                                 tx_ring->push_buf_intermediate_buf);
2389                         *push_header = tx_ring->push_buf_intermediate_buf;
2390                         delta = push_len - seg_len;
2391                 }
2392         } else {
2393                 *push_header = NULL;
2394                 *header_len = 0;
2395                 push_len = 0;
2396         }
2397
2398         /* Process first segment taking into consideration pushed header */
2399         if (seg_len > push_len) {
2400                 ena_buf->paddr = mbuf->buf_iova +
2401                                 mbuf->data_off +
2402                                 push_len;
2403                 ena_buf->len = seg_len - push_len;
2404                 ena_buf++;
2405                 tx_info->num_of_bufs++;
2406         }
2407
2408         while ((mbuf = mbuf->next) != NULL) {
2409                 seg_len = mbuf->data_len;
2410
2411                 /* Skip mbufs if whole data is pushed as a header */
2412                 if (unlikely(delta > seg_len)) {
2413                         delta -= seg_len;
2414                         continue;
2415                 }
2416
2417                 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2418                 ena_buf->len = seg_len - delta;
2419                 ena_buf++;
2420                 tx_info->num_of_bufs++;
2421
2422                 delta = 0;
2423         }
2424 }
2425
2426 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2427 {
2428         struct ena_tx_buffer *tx_info;
2429         struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2430         uint16_t next_to_use;
2431         uint16_t header_len;
2432         uint16_t req_id;
2433         void *push_header;
2434         int nb_hw_desc;
2435         int rc;
2436
2437         rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2438         if (unlikely(rc))
2439                 return rc;
2440
2441         next_to_use = tx_ring->next_to_use;
2442
2443         req_id = tx_ring->empty_tx_reqs[next_to_use];
2444         tx_info = &tx_ring->tx_buffer_info[req_id];
2445         tx_info->num_of_bufs = 0;
2446
2447         ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2448
2449         ena_tx_ctx.ena_bufs = tx_info->bufs;
2450         ena_tx_ctx.push_header = push_header;
2451         ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2452         ena_tx_ctx.req_id = req_id;
2453         ena_tx_ctx.header_len = header_len;
2454
2455         /* Set Tx offloads flags, if applicable */
2456         ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2457                 tx_ring->disable_meta_caching);
2458
2459         if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2460                         &ena_tx_ctx))) {
2461                 PMD_DRV_LOG(DEBUG,
2462                         "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2463                         tx_ring->id);
2464                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2465         }
2466
2467         /* prepare the packet's descriptors to dma engine */
2468         rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2469                 &nb_hw_desc);
2470         if (unlikely(rc)) {
2471                 ++tx_ring->tx_stats.prepare_ctx_err;
2472                 return rc;
2473         }
2474
2475         tx_info->tx_descs = nb_hw_desc;
2476
2477         tx_ring->tx_stats.cnt++;
2478         tx_ring->tx_stats.bytes += mbuf->pkt_len;
2479
2480         tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2481                 tx_ring->size_mask);
2482
2483         return 0;
2484 }
2485
2486 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2487 {
2488         unsigned int cleanup_budget;
2489         unsigned int total_tx_descs = 0;
2490         uint16_t next_to_clean = tx_ring->next_to_clean;
2491
2492         cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2493                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2494
2495         while (likely(total_tx_descs < cleanup_budget)) {
2496                 struct rte_mbuf *mbuf;
2497                 struct ena_tx_buffer *tx_info;
2498                 uint16_t req_id;
2499
2500                 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2501                         break;
2502
2503                 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2504                         break;
2505
2506                 /* Get Tx info & store how many descs were processed  */
2507                 tx_info = &tx_ring->tx_buffer_info[req_id];
2508
2509                 mbuf = tx_info->mbuf;
2510                 rte_pktmbuf_free(mbuf);
2511
2512                 tx_info->mbuf = NULL;
2513                 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2514
2515                 total_tx_descs += tx_info->tx_descs;
2516
2517                 /* Put back descriptor to the ring for reuse */
2518                 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2519                         tx_ring->size_mask);
2520         }
2521
2522         if (likely(total_tx_descs > 0)) {
2523                 /* acknowledge completion of sent packets */
2524                 tx_ring->next_to_clean = next_to_clean;
2525                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2526                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2527         }
2528 }
2529
2530 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2531                                   uint16_t nb_pkts)
2532 {
2533         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2534         uint16_t sent_idx = 0;
2535
2536         /* Check adapter state */
2537         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2538                 PMD_DRV_LOG(ALERT,
2539                         "Trying to xmit pkts while device is NOT running\n");
2540                 return 0;
2541         }
2542
2543         nb_pkts = RTE_MIN(ena_com_free_q_entries(tx_ring->ena_com_io_sq),
2544                 nb_pkts);
2545
2546         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2547                 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2548                         break;
2549
2550                 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2551                         tx_ring->size_mask)]);
2552         }
2553
2554         tx_ring->tx_stats.available_desc =
2555                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2556
2557         /* If there are ready packets to be xmitted... */
2558         if (sent_idx > 0) {
2559                 /* ...let HW do its best :-) */
2560                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2561                 tx_ring->tx_stats.doorbells++;
2562         }
2563
2564         ena_tx_cleanup(tx_ring);
2565
2566         tx_ring->tx_stats.available_desc =
2567                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2568         tx_ring->tx_stats.tx_poll++;
2569
2570         return sent_idx;
2571 }
2572
2573 /**
2574  * DPDK callback to retrieve names of extended device statistics
2575  *
2576  * @param dev
2577  *   Pointer to Ethernet device structure.
2578  * @param[out] xstats_names
2579  *   Buffer to insert names into.
2580  * @param n
2581  *   Number of names.
2582  *
2583  * @return
2584  *   Number of xstats names.
2585  */
2586 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2587                                 struct rte_eth_xstat_name *xstats_names,
2588                                 unsigned int n)
2589 {
2590         unsigned int xstats_count = ena_xstats_calc_num(dev);
2591         unsigned int stat, i, count = 0;
2592
2593         if (n < xstats_count || !xstats_names)
2594                 return xstats_count;
2595
2596         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2597                 strcpy(xstats_names[count].name,
2598                         ena_stats_global_strings[stat].name);
2599
2600         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2601                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2602                         snprintf(xstats_names[count].name,
2603                                 sizeof(xstats_names[count].name),
2604                                 "rx_q%d_%s", i,
2605                                 ena_stats_rx_strings[stat].name);
2606
2607         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2608                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2609                         snprintf(xstats_names[count].name,
2610                                 sizeof(xstats_names[count].name),
2611                                 "tx_q%d_%s", i,
2612                                 ena_stats_tx_strings[stat].name);
2613
2614         return xstats_count;
2615 }
2616
2617 /**
2618  * DPDK callback to get extended device statistics.
2619  *
2620  * @param dev
2621  *   Pointer to Ethernet device structure.
2622  * @param[out] stats
2623  *   Stats table output buffer.
2624  * @param n
2625  *   The size of the stats table.
2626  *
2627  * @return
2628  *   Number of xstats on success, negative on failure.
2629  */
2630 static int ena_xstats_get(struct rte_eth_dev *dev,
2631                           struct rte_eth_xstat *xstats,
2632                           unsigned int n)
2633 {
2634         struct ena_adapter *adapter = dev->data->dev_private;
2635         unsigned int xstats_count = ena_xstats_calc_num(dev);
2636         unsigned int stat, i, count = 0;
2637         int stat_offset;
2638         void *stats_begin;
2639
2640         if (n < xstats_count)
2641                 return xstats_count;
2642
2643         if (!xstats)
2644                 return 0;
2645
2646         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2647                 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2648                 stats_begin = &adapter->dev_stats;
2649
2650                 xstats[count].id = count;
2651                 xstats[count].value = *((uint64_t *)
2652                         ((char *)stats_begin + stat_offset));
2653         }
2654
2655         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2656                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2657                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2658                         stats_begin = &adapter->rx_ring[i].rx_stats;
2659
2660                         xstats[count].id = count;
2661                         xstats[count].value = *((uint64_t *)
2662                                 ((char *)stats_begin + stat_offset));
2663                 }
2664         }
2665
2666         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2667                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2668                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2669                         stats_begin = &adapter->tx_ring[i].rx_stats;
2670
2671                         xstats[count].id = count;
2672                         xstats[count].value = *((uint64_t *)
2673                                 ((char *)stats_begin + stat_offset));
2674                 }
2675         }
2676
2677         return count;
2678 }
2679
2680 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2681                                 const uint64_t *ids,
2682                                 uint64_t *values,
2683                                 unsigned int n)
2684 {
2685         struct ena_adapter *adapter = dev->data->dev_private;
2686         uint64_t id;
2687         uint64_t rx_entries, tx_entries;
2688         unsigned int i;
2689         int qid;
2690         int valid = 0;
2691         for (i = 0; i < n; ++i) {
2692                 id = ids[i];
2693                 /* Check if id belongs to global statistics */
2694                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2695                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2696                         ++valid;
2697                         continue;
2698                 }
2699
2700                 /* Check if id belongs to rx queue statistics */
2701                 id -= ENA_STATS_ARRAY_GLOBAL;
2702                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2703                 if (id < rx_entries) {
2704                         qid = id % dev->data->nb_rx_queues;
2705                         id /= dev->data->nb_rx_queues;
2706                         values[i] = *((uint64_t *)
2707                                 &adapter->rx_ring[qid].rx_stats + id);
2708                         ++valid;
2709                         continue;
2710                 }
2711                                 /* Check if id belongs to rx queue statistics */
2712                 id -= rx_entries;
2713                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2714                 if (id < tx_entries) {
2715                         qid = id % dev->data->nb_tx_queues;
2716                         id /= dev->data->nb_tx_queues;
2717                         values[i] = *((uint64_t *)
2718                                 &adapter->tx_ring[qid].tx_stats + id);
2719                         ++valid;
2720                         continue;
2721                 }
2722         }
2723
2724         return valid;
2725 }
2726
2727 static int ena_process_bool_devarg(const char *key,
2728                                    const char *value,
2729                                    void *opaque)
2730 {
2731         struct ena_adapter *adapter = opaque;
2732         bool bool_value;
2733
2734         /* Parse the value. */
2735         if (strcmp(value, "1") == 0) {
2736                 bool_value = true;
2737         } else if (strcmp(value, "0") == 0) {
2738                 bool_value = false;
2739         } else {
2740                 PMD_INIT_LOG(ERR,
2741                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
2742                         value, key);
2743                 return -EINVAL;
2744         }
2745
2746         /* Now, assign it to the proper adapter field. */
2747         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR))
2748                 adapter->use_large_llq_hdr = bool_value;
2749
2750         return 0;
2751 }
2752
2753 static int ena_parse_devargs(struct ena_adapter *adapter,
2754                              struct rte_devargs *devargs)
2755 {
2756         static const char * const allowed_args[] = {
2757                 ENA_DEVARG_LARGE_LLQ_HDR,
2758         };
2759         struct rte_kvargs *kvlist;
2760         int rc;
2761
2762         if (devargs == NULL)
2763                 return 0;
2764
2765         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
2766         if (kvlist == NULL) {
2767                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
2768                         devargs->args);
2769                 return -EINVAL;
2770         }
2771
2772         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
2773                 ena_process_bool_devarg, adapter);
2774
2775         rte_kvargs_free(kvlist);
2776
2777         return rc;
2778 }
2779
2780 /*********************************************************************
2781  *  PMD configuration
2782  *********************************************************************/
2783 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2784         struct rte_pci_device *pci_dev)
2785 {
2786         return rte_eth_dev_pci_generic_probe(pci_dev,
2787                 sizeof(struct ena_adapter), eth_ena_dev_init);
2788 }
2789
2790 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2791 {
2792         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2793 }
2794
2795 static struct rte_pci_driver rte_ena_pmd = {
2796         .id_table = pci_id_ena_map,
2797         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2798                      RTE_PCI_DRV_WC_ACTIVATE,
2799         .probe = eth_ena_pci_probe,
2800         .remove = eth_ena_pci_remove,
2801 };
2802
2803 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2804 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2805 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2806 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
2807
2808 RTE_INIT(ena_init_log)
2809 {
2810         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2811         if (ena_logtype_init >= 0)
2812                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2813         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2814         if (ena_logtype_driver >= 0)
2815                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2816
2817 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2818         ena_logtype_rx = rte_log_register("pmd.net.ena.rx");
2819         if (ena_logtype_rx >= 0)
2820                 rte_log_set_level(ena_logtype_rx, RTE_LOG_NOTICE);
2821 #endif
2822
2823 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2824         ena_logtype_tx = rte_log_register("pmd.net.ena.tx");
2825         if (ena_logtype_tx >= 0)
2826                 rte_log_set_level(ena_logtype_tx, RTE_LOG_NOTICE);
2827 #endif
2828
2829 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2830         ena_logtype_tx_free = rte_log_register("pmd.net.ena.tx_free");
2831         if (ena_logtype_tx_free >= 0)
2832                 rte_log_set_level(ena_logtype_tx_free, RTE_LOG_NOTICE);
2833 #endif
2834
2835 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2836         ena_logtype_com = rte_log_register("pmd.net.ena.com");
2837         if (ena_logtype_com >= 0)
2838                 rte_log_set_level(ena_logtype_com, RTE_LOG_NOTICE);
2839 #endif
2840 }
2841
2842 /******************************************************************************
2843  ******************************** AENQ Handlers *******************************
2844  *****************************************************************************/
2845 static void ena_update_on_link_change(void *adapter_data,
2846                                       struct ena_admin_aenq_entry *aenq_e)
2847 {
2848         struct rte_eth_dev *eth_dev;
2849         struct ena_adapter *adapter;
2850         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2851         uint32_t status;
2852
2853         adapter = adapter_data;
2854         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2855         eth_dev = adapter->rte_dev;
2856
2857         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2858         adapter->link_status = status;
2859
2860         ena_link_update(eth_dev, 0);
2861         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2862 }
2863
2864 static void ena_notification(void *data,
2865                              struct ena_admin_aenq_entry *aenq_e)
2866 {
2867         struct ena_adapter *adapter = data;
2868         struct ena_admin_ena_hw_hints *hints;
2869
2870         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2871                 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2872                         aenq_e->aenq_common_desc.group,
2873                         ENA_ADMIN_NOTIFICATION);
2874
2875         switch (aenq_e->aenq_common_desc.syndrom) {
2876         case ENA_ADMIN_UPDATE_HINTS:
2877                 hints = (struct ena_admin_ena_hw_hints *)
2878                         (&aenq_e->inline_data_w4);
2879                 ena_update_hints(adapter, hints);
2880                 break;
2881         default:
2882                 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2883                         aenq_e->aenq_common_desc.syndrom);
2884         }
2885 }
2886
2887 static void ena_keep_alive(void *adapter_data,
2888                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2889 {
2890         struct ena_adapter *adapter = adapter_data;
2891         struct ena_admin_aenq_keep_alive_desc *desc;
2892         uint64_t rx_drops;
2893         uint64_t tx_drops;
2894
2895         adapter->timestamp_wd = rte_get_timer_cycles();
2896
2897         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2898         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2899         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
2900
2901         adapter->drv_stats->rx_drops = rx_drops;
2902         adapter->dev_stats.tx_drops = tx_drops;
2903 }
2904
2905 /**
2906  * This handler will called for unknown event group or unimplemented handlers
2907  **/
2908 static void unimplemented_aenq_handler(__rte_unused void *data,
2909                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2910 {
2911         PMD_DRV_LOG(ERR, "Unknown event was received or event with "
2912                           "unimplemented handler\n");
2913 }
2914
2915 static struct ena_aenq_handlers aenq_handlers = {
2916         .handlers = {
2917                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2918                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2919                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2920         },
2921         .unimplemented_handler = unimplemented_aenq_handler
2922 };