drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev.h>
  36 #include <rte_tcp.h>
  37 #include <rte_atomic.h>
  38 #include <rte_dev.h>
  39 #include <rte_errno.h>
  40 #include <rte_version.h>
  41
  42 #include "ena_ethdev.h"
  43 #include "ena_logs.h"
  44 #include "ena_platform.h"
  45 #include "ena_com.h"
  46 #include "ena_eth_com.h"
  47
  48 #include <ena_common_defs.h>
  49 #include <ena_regs_defs.h>
  50 #include <ena_admin_defs.h>
  51 #include <ena_eth_io_defs.h>
  52
  53 #define DRV_MODULE_VER_MAJOR    1
  54 #define DRV_MODULE_VER_MINOR    0
  55 #define DRV_MODULE_VER_SUBMINOR 0
  56
  57 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  58 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  59 /*reverse version of ENA_IO_RXQ_IDX*/
  60 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  61
  62 /* While processing submitted and completed descriptors (rx and tx path
  63  * respectively) in a loop it is desired to:
  64  *  - perform batch submissions while populating sumbissmion queue
  65  *  - avoid blocking transmission of other packets during cleanup phase
  66  * Hence the utilization ratio of 1/8 of a queue size.
  67  */
  68 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  69
  70 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  71 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  72
  73 #define GET_L4_HDR_LEN(mbuf)                                    \
  74         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  75                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  76
  77 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  78 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  79 #define ENA_HASH_KEY_SIZE       40
  80 #define ENA_ETH_SS_STATS        0xFF
  81 #define ETH_GSTRING_LEN 32
  82
  83 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  84
  85 enum ethtool_stringset {
  86         ETH_SS_TEST             = 0,
  87         ETH_SS_STATS,
  88 };
  89
  90 struct ena_stats {
  91         char name[ETH_GSTRING_LEN];
  92         int stat_offset;
  93 };
  94
  95 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
  96         .name = #stat, \
  97         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
  98 }
  99
 100 #define ENA_STAT_ENTRY(stat, stat_type) { \
 101         .name = #stat, \
 102         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 103 }
 104
 105 #define ENA_STAT_RX_ENTRY(stat) \
 106         ENA_STAT_ENTRY(stat, rx)
 107
 108 #define ENA_STAT_TX_ENTRY(stat) \
 109         ENA_STAT_ENTRY(stat, tx)
 110
 111 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, dev)
 113
 114 static const struct ena_stats ena_stats_global_strings[] = {
 115         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 116         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 117         ENA_STAT_GLOBAL_ENTRY(io_resume),
 118         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 119         ENA_STAT_GLOBAL_ENTRY(interface_up),
 120         ENA_STAT_GLOBAL_ENTRY(interface_down),
 121         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 122 };
 123
 124 static const struct ena_stats ena_stats_tx_strings[] = {
 125         ENA_STAT_TX_ENTRY(cnt),
 126         ENA_STAT_TX_ENTRY(bytes),
 127         ENA_STAT_TX_ENTRY(queue_stop),
 128         ENA_STAT_TX_ENTRY(queue_wakeup),
 129         ENA_STAT_TX_ENTRY(dma_mapping_err),
 130         ENA_STAT_TX_ENTRY(linearize),
 131         ENA_STAT_TX_ENTRY(linearize_failed),
 132         ENA_STAT_TX_ENTRY(tx_poll),
 133         ENA_STAT_TX_ENTRY(doorbells),
 134         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 135         ENA_STAT_TX_ENTRY(missing_tx_comp),
 136         ENA_STAT_TX_ENTRY(bad_req_id),
 137 };
 138
 139 static const struct ena_stats ena_stats_rx_strings[] = {
 140         ENA_STAT_RX_ENTRY(cnt),
 141         ENA_STAT_RX_ENTRY(bytes),
 142         ENA_STAT_RX_ENTRY(refil_partial),
 143         ENA_STAT_RX_ENTRY(bad_csum),
 144         ENA_STAT_RX_ENTRY(page_alloc_fail),
 145         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 146         ENA_STAT_RX_ENTRY(dma_mapping_err),
 147         ENA_STAT_RX_ENTRY(bad_desc_num),
 148         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 149 };
 150
 151 static const struct ena_stats ena_stats_ena_com_strings[] = {
 152         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 153         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 154         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 155         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 156         ENA_STAT_ENA_COM_ENTRY(no_completion),
 157 };
 158
 159 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 160 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 161 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 162 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 163
 164 /** Vendor ID used by Amazon devices */
 165 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 166 /** Amazon devices */
 167 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 168 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 169
 170 static struct rte_pci_id pci_id_ena_map[] = {
 171 #define RTE_PCI_DEV_ID_DECL_ENA(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 172         RTE_PCI_DEV_ID_DECL_ENA(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF)
 173         RTE_PCI_DEV_ID_DECL_ENA(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF)
 174         {.device_id = 0},
 175 };
 176
 177 static int ena_device_init(struct ena_com_dev *ena_dev,
 178                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 179 static int ena_dev_configure(struct rte_eth_dev *dev);
 180 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 181                                   uint16_t nb_pkts);
 182 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 183                               uint16_t nb_desc, unsigned int socket_id,
 184                               const struct rte_eth_txconf *tx_conf);
 185 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 186                               uint16_t nb_desc, unsigned int socket_id,
 187                               const struct rte_eth_rxconf *rx_conf,
 188                               struct rte_mempool *mp);
 189 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 190                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 191 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 192 static void ena_init_rings(struct ena_adapter *adapter);
 193 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 194 static int ena_start(struct rte_eth_dev *dev);
 195 static void ena_close(struct rte_eth_dev *dev);
 196 static void ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 197 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 198 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 199 static void ena_rx_queue_release(void *queue);
 200 static void ena_tx_queue_release(void *queue);
 201 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 202 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 203 static int ena_link_update(struct rte_eth_dev *dev,
 204                            __rte_unused int wait_to_complete);
 205 static int ena_queue_restart(struct ena_ring *ring);
 206 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 207                                  enum ena_ring_type ring_type);
 208 static void ena_stats_restart(struct rte_eth_dev *dev);
 209 static void ena_infos_get(__rte_unused struct rte_eth_dev *dev,
 210                           struct rte_eth_dev_info *dev_info);
 211 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 212                                struct rte_eth_rss_reta_entry64 *reta_conf,
 213                                uint16_t reta_size);
 214 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 215                               struct rte_eth_rss_reta_entry64 *reta_conf,
 216                               uint16_t reta_size);
 217 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 218
 219 static struct eth_dev_ops ena_dev_ops = {
 220         .dev_configure        = ena_dev_configure,
 221         .dev_infos_get        = ena_infos_get,
 222         .rx_queue_setup       = ena_rx_queue_setup,
 223         .tx_queue_setup       = ena_tx_queue_setup,
 224         .dev_start            = ena_start,
 225         .link_update          = ena_link_update,
 226         .stats_get            = ena_stats_get,
 227         .mtu_set              = ena_mtu_set,
 228         .rx_queue_release     = ena_rx_queue_release,
 229         .tx_queue_release     = ena_tx_queue_release,
 230         .dev_close            = ena_close,
 231         .reta_update          = ena_rss_reta_update,
 232         .reta_query           = ena_rss_reta_query,
 233 };
 234
 235 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 236                                        struct ena_com_rx_ctx *ena_rx_ctx)
 237 {
 238         uint64_t ol_flags = 0;
 239
 240         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 241                 ol_flags |= PKT_TX_TCP_CKSUM;
 242         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 243                 ol_flags |= PKT_TX_UDP_CKSUM;
 244
 245         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 246                 ol_flags |= PKT_TX_IPV4;
 247         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 248                 ol_flags |= PKT_TX_IPV6;
 249
 250         if (unlikely(ena_rx_ctx->l4_csum_err))
 251                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 252         if (unlikely(ena_rx_ctx->l3_csum_err))
 253                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 254
 255         mbuf->ol_flags = ol_flags;
 256 }
 257
 258 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 259                                        struct ena_com_tx_ctx *ena_tx_ctx)
 260 {
 261         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 262
 263         if (mbuf->ol_flags &
 264             (PKT_TX_L4_MASK | PKT_TX_IP_CKSUM | PKT_TX_TCP_SEG)) {
 265                 /* check if TSO is required */
 266                 if (mbuf->ol_flags & PKT_TX_TCP_SEG) {
 267                         ena_tx_ctx->tso_enable = true;
 268
 269                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 270                 }
 271
 272                 /* check if L3 checksum is needed */
 273                 if (mbuf->ol_flags & PKT_TX_IP_CKSUM)
 274                         ena_tx_ctx->l3_csum_enable = true;
 275
 276                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 277                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 278                 } else {
 279                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 280
 281                         /* set don't fragment (DF) flag */
 282                         if (mbuf->packet_type &
 283                                 (RTE_PTYPE_L4_NONFRAG
 284                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 285                                 ena_tx_ctx->df = true;
 286                 }
 287
 288                 /* check if L4 checksum is needed */
 289                 switch (mbuf->ol_flags & PKT_TX_L4_MASK) {
 290                 case PKT_TX_TCP_CKSUM:
 291                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 292                         ena_tx_ctx->l4_csum_enable = true;
 293                         break;
 294                 case PKT_TX_UDP_CKSUM:
 295                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 296                         ena_tx_ctx->l4_csum_enable = true;
 297                         break;
 298                 default:
 299                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 300                         ena_tx_ctx->l4_csum_enable = false;
 301                         break;
 302                 }
 303
 304                 ena_meta->mss = mbuf->tso_segsz;
 305                 ena_meta->l3_hdr_len = mbuf->l3_len;
 306                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 307                 /* this param needed only for TSO */
 308                 ena_meta->l3_outer_hdr_len = 0;
 309                 ena_meta->l3_outer_hdr_offset = 0;
 310
 311                 ena_tx_ctx->meta_valid = true;
 312         } else {
 313                 ena_tx_ctx->meta_valid = false;
 314         }
 315 }
 316
 317 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 318 {
 319         struct ena_admin_host_info *host_info;
 320         int rc;
 321
 322         /* Allocate only the host info */
 323         rc = ena_com_allocate_host_info(ena_dev);
 324         if (rc) {
 325                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 326                 return;
 327         }
 328
 329         host_info = ena_dev->host_attr.host_info;
 330
 331         host_info->os_type = ENA_ADMIN_OS_DPDK;
 332         host_info->kernel_ver = RTE_VERSION;
 333         strncpy((char *)host_info->kernel_ver_str, rte_version(),
 334                 strlen(rte_version()));
 335         host_info->os_dist = RTE_VERSION;
 336         strncpy((char *)host_info->os_dist_str, rte_version(),
 337                 strlen(rte_version()));
 338         host_info->driver_version =
 339                 (DRV_MODULE_VER_MAJOR) |
 340                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 341                 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 342
 343         rc = ena_com_set_host_attributes(ena_dev);
 344         if (rc) {
 345                 if (rc == -EPERM)
 346                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 347                 else
 348                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 349
 350                 goto err;
 351         }
 352
 353         return;
 354
 355 err:
 356         ena_com_delete_host_info(ena_dev);
 357 }
 358
 359 static int
 360 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 361 {
 362         if (sset != ETH_SS_STATS)
 363                 return -EOPNOTSUPP;
 364
 365          /* Workaround for clang:
 366          * touch internal structures to prevent
 367          * compiler error
 368          */
 369         ENA_TOUCH(ena_stats_global_strings);
 370         ENA_TOUCH(ena_stats_tx_strings);
 371         ENA_TOUCH(ena_stats_rx_strings);
 372         ENA_TOUCH(ena_stats_ena_com_strings);
 373
 374         return  dev->data->nb_tx_queues *
 375                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 376                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 377 }
 378
 379 static void ena_config_debug_area(struct ena_adapter *adapter)
 380 {
 381         u32 debug_area_size;
 382         int rc, ss_count;
 383
 384         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 385         if (ss_count <= 0) {
 386                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 387                 return;
 388         }
 389
 390         /* allocate 32 bytes for each string and 64bit for the value */
 391         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 392
 393         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 394         if (rc) {
 395                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 396                 return;
 397         }
 398
 399         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 400         if (rc) {
 401                 if (rc == -EPERM)
 402                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 403                 else
 404                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 405                 goto err;
 406         }
 407
 408         return;
 409 err:
 410         ena_com_delete_debug_area(&adapter->ena_dev);
 411 }
 412
 413 static void ena_close(struct rte_eth_dev *dev)
 414 {
 415         struct ena_adapter *adapter =
 416                 (struct ena_adapter *)(dev->data->dev_private);
 417
 418         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 419
 420         ena_rx_queue_release_all(dev);
 421         ena_tx_queue_release_all(dev);
 422 }
 423
 424 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 425                                struct rte_eth_rss_reta_entry64 *reta_conf,
 426                                uint16_t reta_size)
 427 {
 428         struct ena_adapter *adapter =
 429                 (struct ena_adapter *)(dev->data->dev_private);
 430         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 431         int ret, i;
 432         u16 entry_value;
 433         int conf_idx;
 434         int idx;
 435
 436         if ((reta_size == 0) || (reta_conf == NULL))
 437                 return -EINVAL;
 438
 439         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 440                 RTE_LOG(WARNING, PMD,
 441                         "indirection table %d is bigger than supported (%d)\n",
 442                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 443                 ret = -EINVAL;
 444                 goto err;
 445         }
 446
 447         for (i = 0 ; i < reta_size ; i++) {
 448                 /* each reta_conf is for 64 entries.
 449                  * to support 128 we use 2 conf of 64
 450                  */
 451                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 452                 idx = i % RTE_RETA_GROUP_SIZE;
 453                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 454                         entry_value =
 455                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 456                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 457                                                                 i,
 458                                                                 entry_value);
 459                         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 460                                 RTE_LOG(ERR, PMD,
 461                                         "Cannot fill indirect table\n");
 462                                 ret = -ENOTSUP;
 463                                 goto err;
 464                         }
 465                 }
 466         }
 467
 468         ret = ena_com_indirect_table_set(ena_dev);
 469         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 470                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 471                 ret = -ENOTSUP;
 472                 goto err;
 473         }
 474
 475         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 476                 __func__, reta_size, adapter->rte_dev->data->port_id);
 477 err:
 478         return ret;
 479 }
 480
 481 /* Query redirection table. */
 482 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 483                               struct rte_eth_rss_reta_entry64 *reta_conf,
 484                               uint16_t reta_size)
 485 {
 486         struct ena_adapter *adapter =
 487                 (struct ena_adapter *)(dev->data->dev_private);
 488         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 489         int ret;
 490         int i;
 491         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 492         int reta_conf_idx;
 493         int reta_idx;
 494
 495         if (reta_size == 0 || reta_conf == NULL ||
 496             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 497                 return -EINVAL;
 498
 499         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 500         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 501                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 502                 ret = -ENOTSUP;
 503                 goto err;
 504         }
 505
 506         for (i = 0 ; i < reta_size ; i++) {
 507                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 508                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 509                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 510                         reta_conf[reta_conf_idx].reta[reta_idx] =
 511                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 512         }
 513 err:
 514         return ret;
 515 }
 516
 517 static int ena_rss_init_default(struct ena_adapter *adapter)
 518 {
 519         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 520         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 521         int rc, i;
 522         u32 val;
 523
 524         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 525         if (unlikely(rc)) {
 526                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 527                 goto err_rss_init;
 528         }
 529
 530         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 531                 val = i % nb_rx_queues;
 532                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 533                                                        ENA_IO_RXQ_IDX(val));
 534                 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 535                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 536                         goto err_fill_indir;
 537                 }
 538         }
 539
 540         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 541                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 542         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 543                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 544                 goto err_fill_indir;
 545         }
 546
 547         rc = ena_com_set_default_hash_ctrl(ena_dev);
 548         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 549                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 550                 goto err_fill_indir;
 551         }
 552
 553         rc = ena_com_indirect_table_set(ena_dev);
 554         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 555                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 556                 goto err_fill_indir;
 557         }
 558         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 559                 adapter->rte_dev->data->port_id);
 560
 561         return 0;
 562
 563 err_fill_indir:
 564         ena_com_rss_destroy(ena_dev);
 565 err_rss_init:
 566
 567         return rc;
 568 }
 569
 570 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 571 {
 572         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 573         int nb_queues = dev->data->nb_rx_queues;
 574         int i;
 575
 576         for (i = 0; i < nb_queues; i++)
 577                 ena_rx_queue_release(queues[i]);
 578 }
 579
 580 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 581 {
 582         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 583         int nb_queues = dev->data->nb_tx_queues;
 584         int i;
 585
 586         for (i = 0; i < nb_queues; i++)
 587                 ena_tx_queue_release(queues[i]);
 588 }
 589
 590 static void ena_rx_queue_release(void *queue)
 591 {
 592         struct ena_ring *ring = (struct ena_ring *)queue;
 593         struct ena_adapter *adapter = ring->adapter;
 594         int ena_qid;
 595
 596         ena_assert_msg(ring->configured,
 597                        "API violation - releasing not configured queue");
 598         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 599                        "API violation");
 600
 601         /* Destroy HW queue */
 602         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 603         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 604
 605         /* Free all bufs */
 606         ena_rx_queue_release_bufs(ring);
 607
 608         /* Free ring resources */
 609         if (ring->rx_buffer_info)
 610                 rte_free(ring->rx_buffer_info);
 611         ring->rx_buffer_info = NULL;
 612
 613         ring->configured = 0;
 614
 615         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 616                 ring->port_id, ring->id);
 617 }
 618
 619 static void ena_tx_queue_release(void *queue)
 620 {
 621         struct ena_ring *ring = (struct ena_ring *)queue;
 622         struct ena_adapter *adapter = ring->adapter;
 623         int ena_qid;
 624
 625         ena_assert_msg(ring->configured,
 626                        "API violation. Releasing not configured queue");
 627         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 628                        "API violation");
 629
 630         /* Destroy HW queue */
 631         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 632         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 633
 634         /* Free all bufs */
 635         ena_tx_queue_release_bufs(ring);
 636
 637         /* Free ring resources */
 638         if (ring->tx_buffer_info)
 639                 rte_free(ring->tx_buffer_info);
 640
 641         if (ring->empty_tx_reqs)
 642                 rte_free(ring->empty_tx_reqs);
 643
 644         ring->empty_tx_reqs = NULL;
 645         ring->tx_buffer_info = NULL;
 646
 647         ring->configured = 0;
 648
 649         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 650                 ring->port_id, ring->id);
 651 }
 652
 653 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 654 {
 655         unsigned int ring_mask = ring->ring_size - 1;
 656
 657         while (ring->next_to_clean != ring->next_to_use) {
 658                 struct rte_mbuf *m =
 659                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 660
 661                 if (m)
 662                         __rte_mbuf_raw_free(m);
 663
 664                 ring->next_to_clean =
 665                         ENA_CIRC_INC(ring->next_to_clean, 1, ring->ring_size);
 666         }
 667 }
 668
 669 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 670 {
 671         unsigned int ring_mask = ring->ring_size - 1;
 672
 673         while (ring->next_to_clean != ring->next_to_use) {
 674                 struct ena_tx_buffer *tx_buf =
 675                         &ring->tx_buffer_info[ring->next_to_clean & ring_mask];
 676
 677                 if (tx_buf->mbuf)
 678                         rte_pktmbuf_free(tx_buf->mbuf);
 679
 680                 ring->next_to_clean =
 681                         ENA_CIRC_INC(ring->next_to_clean, 1, ring->ring_size);
 682         }
 683 }
 684
 685 static int ena_link_update(struct rte_eth_dev *dev,
 686                            __rte_unused int wait_to_complete)
 687 {
 688         struct rte_eth_link *link = &dev->data->dev_link;
 689
 690         link->link_status = 1;
 691         link->link_speed = ETH_SPEED_NUM_10G;
 692         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 693
 694         return 0;
 695 }
 696
 697 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 698                                  enum ena_ring_type ring_type)
 699 {
 700         struct ena_adapter *adapter =
 701                 (struct ena_adapter *)(dev->data->dev_private);
 702         struct ena_ring *queues = NULL;
 703         int i = 0;
 704         int rc = 0;
 705
 706         queues = (ring_type == ENA_RING_TYPE_RX) ?
 707                 adapter->rx_ring : adapter->tx_ring;
 708
 709         for (i = 0; i < adapter->num_queues; i++) {
 710                 if (queues[i].configured) {
 711                         if (ring_type == ENA_RING_TYPE_RX) {
 712                                 ena_assert_msg(
 713                                         dev->data->rx_queues[i] == &queues[i],
 714                                         "Inconsistent state of rx queues\n");
 715                         } else {
 716                                 ena_assert_msg(
 717                                         dev->data->tx_queues[i] == &queues[i],
 718                                         "Inconsistent state of tx queues\n");
 719                         }
 720
 721                         rc = ena_queue_restart(&queues[i]);
 722
 723                         if (rc) {
 724                                 PMD_INIT_LOG(ERR,
 725                                              "failed to restart queue %d type(%d)\n",
 726                                              i, ring_type);
 727                                 return -1;
 728                         }
 729                 }
 730         }
 731
 732         return 0;
 733 }
 734
 735 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 736 {
 737         uint32_t max_frame_len = adapter->max_mtu;
 738
 739         if (adapter->rte_eth_dev_data->dev_conf.rxmode.jumbo_frame == 1)
 740                 max_frame_len =
 741                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 742
 743         return max_frame_len;
 744 }
 745
 746 static int ena_check_valid_conf(struct ena_adapter *adapter)
 747 {
 748         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 749
 750         if (max_frame_len > adapter->max_mtu) {
 751                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d\n", max_frame_len);
 752                 return -1;
 753         }
 754
 755         return 0;
 756 }
 757
 758 static int
 759 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 760                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 761 {
 762         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 763
 764         queue_size = RTE_MIN(queue_size,
 765                              get_feat_ctx->max_queues.max_cq_depth);
 766         queue_size = RTE_MIN(queue_size,
 767                              get_feat_ctx->max_queues.max_sq_depth);
 768
 769         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 770                 queue_size = RTE_MIN(queue_size,
 771                                      get_feat_ctx->max_queues.max_llq_depth);
 772
 773         /* Round down to power of 2 */
 774         if (!rte_is_power_of_2(queue_size))
 775                 queue_size = rte_align32pow2(queue_size >> 1);
 776
 777         if (queue_size == 0) {
 778                 PMD_INIT_LOG(ERR, "Invalid queue size\n");
 779                 return -EFAULT;
 780         }
 781
 782         return queue_size;
 783 }
 784
 785 static void ena_stats_restart(struct rte_eth_dev *dev)
 786 {
 787         struct ena_adapter *adapter =
 788                 (struct ena_adapter *)(dev->data->dev_private);
 789
 790         rte_atomic64_init(&adapter->drv_stats->ierrors);
 791         rte_atomic64_init(&adapter->drv_stats->oerrors);
 792         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 793 }
 794
 795 static void ena_stats_get(struct rte_eth_dev *dev,
 796                           struct rte_eth_stats *stats)
 797 {
 798         struct ena_admin_basic_stats ena_stats;
 799         struct ena_adapter *adapter =
 800                 (struct ena_adapter *)(dev->data->dev_private);
 801         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 802         int rc;
 803
 804         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 805                 return;
 806
 807         memset(&ena_stats, 0, sizeof(ena_stats));
 808         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 809         if (unlikely(rc)) {
 810                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 811                 return;
 812         }
 813
 814         /* Set of basic statistics from ENA */
 815         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 816                                           ena_stats.rx_pkts_low);
 817         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 818                                           ena_stats.tx_pkts_low);
 819         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 820                                         ena_stats.rx_bytes_low);
 821         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 822                                         ena_stats.tx_bytes_low);
 823         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 824                                          ena_stats.rx_drops_low);
 825
 826         /* Driver related stats */
 827         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 828         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 829         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 830 }
 831
 832 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 833 {
 834         struct ena_adapter *adapter;
 835         struct ena_com_dev *ena_dev;
 836         int rc = 0;
 837
 838         ena_assert_msg(dev->data != NULL, "Uninitialized device");
 839         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
 840         adapter = (struct ena_adapter *)(dev->data->dev_private);
 841
 842         ena_dev = &adapter->ena_dev;
 843         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
 844
 845         if (mtu > ena_get_mtu_conf(adapter)) {
 846                 RTE_LOG(ERR, PMD,
 847                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
 848                         mtu, ena_get_mtu_conf(adapter));
 849                 rc = -EINVAL;
 850                 goto err;
 851         }
 852
 853         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 854         if (rc)
 855                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
 856         else
 857                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
 858
 859 err:
 860         return rc;
 861 }
 862
 863 static int ena_start(struct rte_eth_dev *dev)
 864 {
 865         struct ena_adapter *adapter =
 866                 (struct ena_adapter *)(dev->data->dev_private);
 867         int rc = 0;
 868
 869         if (!(adapter->state == ENA_ADAPTER_STATE_CONFIG ||
 870               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
 871                 PMD_INIT_LOG(ERR, "API violation");
 872                 return -1;
 873         }
 874
 875         rc = ena_check_valid_conf(adapter);
 876         if (rc)
 877                 return rc;
 878
 879         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
 880         if (rc)
 881                 return rc;
 882
 883         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
 884         if (rc)
 885                 return rc;
 886
 887         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
 888             ETH_MQ_RX_RSS_FLAG) {
 889                 rc = ena_rss_init_default(adapter);
 890                 if (rc)
 891                         return rc;
 892         }
 893
 894         ena_stats_restart(dev);
 895
 896         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 897
 898         return 0;
 899 }
 900
 901 static int ena_queue_restart(struct ena_ring *ring)
 902 {
 903         int rc;
 904
 905         ena_assert_msg(ring->configured == 1,
 906                        "Trying to restart unconfigured queue\n");
 907
 908         ring->next_to_clean = 0;
 909         ring->next_to_use = 0;
 910
 911         if (ring->type == ENA_RING_TYPE_TX)
 912                 return 0;
 913
 914         rc = ena_populate_rx_queue(ring, ring->ring_size - 1);
 915         if ((unsigned int)rc != ring->ring_size - 1) {
 916                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !\n");
 917                 return (-1);
 918         }
 919
 920         return 0;
 921 }
 922
 923 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
 924                               uint16_t queue_idx,
 925                               uint16_t nb_desc,
 926                               __rte_unused unsigned int socket_id,
 927                               __rte_unused const struct rte_eth_txconf *tx_conf)
 928 {
 929         struct ena_com_create_io_ctx ctx =
 930                 /* policy set to _HOST just to satisfy icc compiler */
 931                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
 932                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
 933         struct ena_ring *txq = NULL;
 934         struct ena_adapter *adapter =
 935                 (struct ena_adapter *)(dev->data->dev_private);
 936         unsigned int i;
 937         int ena_qid;
 938         int rc;
 939         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 940
 941         txq = &adapter->tx_ring[queue_idx];
 942
 943         if (txq->configured) {
 944                 RTE_LOG(CRIT, PMD,
 945                         "API violation. Queue %d is already configured\n",
 946                         queue_idx);
 947                 return -1;
 948         }
 949
 950         if (nb_desc > adapter->tx_ring_size) {
 951                 RTE_LOG(ERR, PMD,
 952                         "Unsupported size of TX queue (max size: %d)\n",
 953                         adapter->tx_ring_size);
 954                 return -EINVAL;
 955         }
 956
 957         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
 958
 959         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
 960         ctx.qid = ena_qid;
 961         ctx.msix_vector = -1; /* admin interrupts not used */
 962         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
 963         ctx.queue_size = adapter->tx_ring_size;
 964
 965         rc = ena_com_create_io_queue(ena_dev, &ctx);
 966         if (rc) {
 967                 RTE_LOG(ERR, PMD,
 968                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
 969                         queue_idx, ena_qid, rc);
 970         }
 971         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
 972         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
 973
 974         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
 975                                      &txq->ena_com_io_sq,
 976                                      &txq->ena_com_io_cq);
 977         if (rc) {
 978                 RTE_LOG(ERR, PMD,
 979                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
 980                         queue_idx, rc);
 981                 ena_com_destroy_io_queue(ena_dev, ena_qid);
 982                 goto err;
 983         }
 984
 985         txq->port_id = dev->data->port_id;
 986         txq->next_to_clean = 0;
 987         txq->next_to_use = 0;
 988         txq->ring_size = nb_desc;
 989
 990         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
 991                                           sizeof(struct ena_tx_buffer) *
 992                                           txq->ring_size,
 993                                           RTE_CACHE_LINE_SIZE);
 994         if (!txq->tx_buffer_info) {
 995                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
 996                 return -ENOMEM;
 997         }
 998
 999         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1000                                          sizeof(u16) * txq->ring_size,
1001                                          RTE_CACHE_LINE_SIZE);
1002         if (!txq->empty_tx_reqs) {
1003                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1004                 rte_free(txq->tx_buffer_info);
1005                 return -ENOMEM;
1006         }
1007         for (i = 0; i < txq->ring_size; i++)
1008                 txq->empty_tx_reqs[i] = i;
1009
1010         /* Store pointer to this queue in upper layer */
1011         txq->configured = 1;
1012         dev->data->tx_queues[queue_idx] = txq;
1013 err:
1014         return rc;
1015 }
1016
1017 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1018                               uint16_t queue_idx,
1019                               uint16_t nb_desc,
1020                               __rte_unused unsigned int socket_id,
1021                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1022                               struct rte_mempool *mp)
1023 {
1024         struct ena_com_create_io_ctx ctx =
1025                 /* policy set to _HOST just to satisfy icc compiler */
1026                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1027                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1028         struct ena_adapter *adapter =
1029                 (struct ena_adapter *)(dev->data->dev_private);
1030         struct ena_ring *rxq = NULL;
1031         uint16_t ena_qid = 0;
1032         int rc = 0;
1033         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1034
1035         rxq = &adapter->rx_ring[queue_idx];
1036         if (rxq->configured) {
1037                 RTE_LOG(CRIT, PMD,
1038                         "API violation. Queue %d is already configured\n",
1039                         queue_idx);
1040                 return -1;
1041         }
1042
1043         if (nb_desc > adapter->rx_ring_size) {
1044                 RTE_LOG(ERR, PMD,
1045                         "Unsupported size of RX queue (max size: %d)\n",
1046                         adapter->rx_ring_size);
1047                 return -EINVAL;
1048         }
1049
1050         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1051
1052         ctx.qid = ena_qid;
1053         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1054         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1055         ctx.msix_vector = -1; /* admin interrupts not used */
1056         ctx.queue_size = adapter->rx_ring_size;
1057
1058         rc = ena_com_create_io_queue(ena_dev, &ctx);
1059         if (rc)
1060                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1061                         queue_idx, rc);
1062
1063         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1064         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1065
1066         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1067                                      &rxq->ena_com_io_sq,
1068                                      &rxq->ena_com_io_cq);
1069         if (rc) {
1070                 RTE_LOG(ERR, PMD,
1071                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1072                         queue_idx, rc);
1073                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1074         }
1075
1076         rxq->port_id = dev->data->port_id;
1077         rxq->next_to_clean = 0;
1078         rxq->next_to_use = 0;
1079         rxq->ring_size = nb_desc;
1080         rxq->mb_pool = mp;
1081
1082         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1083                                           sizeof(struct rte_mbuf *) * nb_desc,
1084                                           RTE_CACHE_LINE_SIZE);
1085         if (!rxq->rx_buffer_info) {
1086                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1087                 return -ENOMEM;
1088         }
1089
1090         /* Store pointer to this queue in upper layer */
1091         rxq->configured = 1;
1092         dev->data->rx_queues[queue_idx] = rxq;
1093
1094         return rc;
1095 }
1096
1097 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1098 {
1099         unsigned int i;
1100         int rc;
1101         unsigned int ring_size = rxq->ring_size;
1102         unsigned int ring_mask = ring_size - 1;
1103         int next_to_use = rxq->next_to_use & ring_mask;
1104         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1105
1106         if (unlikely(!count))
1107                 return 0;
1108
1109         ena_assert_msg((((ENA_CIRC_COUNT(rxq->next_to_use, rxq->next_to_clean,
1110                                          rxq->ring_size)) +
1111                          count) < rxq->ring_size), "bad ring state");
1112
1113         count = RTE_MIN(count, ring_size - next_to_use);
1114
1115         /* get resources for incoming packets */
1116         rc = rte_mempool_get_bulk(rxq->mb_pool,
1117                                   (void **)(&mbufs[next_to_use]), count);
1118         if (unlikely(rc < 0)) {
1119                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1120                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1121                 return 0;
1122         }
1123
1124         for (i = 0; i < count; i++) {
1125                 struct rte_mbuf *mbuf = mbufs[next_to_use];
1126                 struct ena_com_buf ebuf;
1127
1128                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1129                 /* prepare physical address for DMA transaction */
1130                 ebuf.paddr = mbuf->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1131                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1132                 /* pass resource to device */
1133                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1134                                                 &ebuf, next_to_use);
1135                 if (unlikely(rc)) {
1136                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1137                         break;
1138                 }
1139                 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use, ring_size);
1140         }
1141
1142         rte_wmb();
1143         rxq->next_to_use = next_to_use;
1144         /* let HW know that it can fill buffers with data */
1145         ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1146
1147         return i;
1148 }
1149
1150 static int ena_device_init(struct ena_com_dev *ena_dev,
1151                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1152 {
1153         int rc;
1154
1155         /* Initialize mmio registers */
1156         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1157         if (rc) {
1158                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1159                 return rc;
1160         }
1161
1162         /* reset device */
1163         rc = ena_com_dev_reset(ena_dev);
1164         if (rc) {
1165                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1166                 goto err_mmio_read_less;
1167         }
1168
1169         /* check FW version */
1170         rc = ena_com_validate_version(ena_dev);
1171         if (rc) {
1172                 RTE_LOG(ERR, PMD, "device version is too low\n");
1173                 goto err_mmio_read_less;
1174         }
1175
1176         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1177
1178         /* ENA device administration layer init */
1179         rc = ena_com_admin_init(ena_dev, NULL, true);
1180         if (rc) {
1181                 RTE_LOG(ERR, PMD,
1182                         "cannot initialize ena admin queue with device\n");
1183                 goto err_mmio_read_less;
1184         }
1185
1186         ena_config_host_info(ena_dev);
1187
1188         /* To enable the msix interrupts the driver needs to know the number
1189          * of queues. So the driver uses polling mode to retrieve this
1190          * information.
1191          */
1192         ena_com_set_admin_polling_mode(ena_dev, true);
1193
1194         /* Get Device Attributes and features */
1195         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1196         if (rc) {
1197                 RTE_LOG(ERR, PMD,
1198                         "cannot get attribute for ena device rc= %d\n", rc);
1199                 goto err_admin_init;
1200         }
1201
1202         return 0;
1203
1204 err_admin_init:
1205         ena_com_admin_destroy(ena_dev);
1206
1207 err_mmio_read_less:
1208         ena_com_mmio_reg_read_request_destroy(ena_dev);
1209
1210         return rc;
1211 }
1212
1213 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1214 {
1215         struct rte_pci_device *pci_dev;
1216         struct ena_adapter *adapter =
1217                 (struct ena_adapter *)(eth_dev->data->dev_private);
1218         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1219         struct ena_com_dev_get_features_ctx get_feat_ctx;
1220         int queue_size, rc;
1221
1222         static int adapters_found;
1223
1224         memset(adapter, 0, sizeof(struct ena_adapter));
1225         ena_dev = &adapter->ena_dev;
1226
1227         eth_dev->dev_ops = &ena_dev_ops;
1228         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1229         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1230         adapter->rte_eth_dev_data = eth_dev->data;
1231         adapter->rte_dev = eth_dev;
1232
1233         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1234                 return 0;
1235
1236         pci_dev = eth_dev->pci_dev;
1237         adapter->pdev = pci_dev;
1238
1239         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
1240                      pci_dev->addr.domain,
1241                      pci_dev->addr.bus,
1242                      pci_dev->addr.devid,
1243                      pci_dev->addr.function);
1244
1245         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1246         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1247
1248         /* Present ENA_MEM_BAR indicates available LLQ mode.
1249          * Use corresponding policy
1250          */
1251         if (adapter->dev_mem_base)
1252                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
1253         else if (adapter->regs)
1254                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1255         else
1256                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
1257                              ENA_REGS_BAR);
1258
1259         ena_dev->reg_bar = adapter->regs;
1260         ena_dev->dmadev = adapter->pdev;
1261
1262         adapter->id_number = adapters_found;
1263
1264         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1265                  adapter->id_number);
1266
1267         /* device specific initialization routine */
1268         rc = ena_device_init(ena_dev, &get_feat_ctx);
1269         if (rc) {
1270                 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
1271                 return -1;
1272         }
1273
1274         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1275                 if (get_feat_ctx.max_queues.max_llq_num == 0) {
1276                         PMD_INIT_LOG(ERR,
1277                                      "Trying to use LLQ but llq_num is 0.\n"
1278                                      "Fall back into regular queues.\n");
1279                         ena_dev->tx_mem_queue_type =
1280                                 ENA_ADMIN_PLACEMENT_POLICY_HOST;
1281                         adapter->num_queues =
1282                                 get_feat_ctx.max_queues.max_sq_num;
1283                 } else {
1284                         adapter->num_queues =
1285                                 get_feat_ctx.max_queues.max_llq_num;
1286                 }
1287         } else {
1288                 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1289         }
1290
1291         queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1292         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1293                 return -EFAULT;
1294
1295         adapter->tx_ring_size = queue_size;
1296         adapter->rx_ring_size = queue_size;
1297
1298         /* prepare ring structures */
1299         ena_init_rings(adapter);
1300
1301         ena_config_debug_area(adapter);
1302
1303         /* Set max MTU for this device */
1304         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1305
1306         /* Copy MAC address and point DPDK to it */
1307         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1308         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1309                         (struct ether_addr *)adapter->mac_addr);
1310
1311         adapter->drv_stats = rte_zmalloc("adapter stats",
1312                                          sizeof(*adapter->drv_stats),
1313                                          RTE_CACHE_LINE_SIZE);
1314         if (!adapter->drv_stats) {
1315                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1316                 return -ENOMEM;
1317         }
1318
1319         adapters_found++;
1320         adapter->state = ENA_ADAPTER_STATE_INIT;
1321
1322         return 0;
1323 }
1324
1325 static int ena_dev_configure(struct rte_eth_dev *dev)
1326 {
1327         struct ena_adapter *adapter =
1328                 (struct ena_adapter *)(dev->data->dev_private);
1329
1330         if (!(adapter->state == ENA_ADAPTER_STATE_INIT ||
1331               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
1332                 PMD_INIT_LOG(ERR, "Illegal adapter state: %d\n",
1333                              adapter->state);
1334                 return -1;
1335         }
1336
1337         switch (adapter->state) {
1338         case ENA_ADAPTER_STATE_INIT:
1339         case ENA_ADAPTER_STATE_STOPPED:
1340                 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1341                 break;
1342         case ENA_ADAPTER_STATE_CONFIG:
1343                 RTE_LOG(WARNING, PMD,
1344                         "Ivalid driver state while trying to configure device\n");
1345                 break;
1346         default:
1347                 break;
1348         }
1349
1350         return 0;
1351 }
1352
1353 static void ena_init_rings(struct ena_adapter *adapter)
1354 {
1355         int i;
1356
1357         for (i = 0; i < adapter->num_queues; i++) {
1358                 struct ena_ring *ring = &adapter->tx_ring[i];
1359
1360                 ring->configured = 0;
1361                 ring->type = ENA_RING_TYPE_TX;
1362                 ring->adapter = adapter;
1363                 ring->id = i;
1364                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1365                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1366         }
1367
1368         for (i = 0; i < adapter->num_queues; i++) {
1369                 struct ena_ring *ring = &adapter->rx_ring[i];
1370
1371                 ring->configured = 0;
1372                 ring->type = ENA_RING_TYPE_RX;
1373                 ring->adapter = adapter;
1374                 ring->id = i;
1375         }
1376 }
1377
1378 static void ena_infos_get(struct rte_eth_dev *dev,
1379                           struct rte_eth_dev_info *dev_info)
1380 {
1381         struct ena_adapter *adapter;
1382         struct ena_com_dev *ena_dev;
1383         struct ena_com_dev_get_features_ctx feat;
1384         uint32_t rx_feat = 0, tx_feat = 0;
1385         int rc = 0;
1386
1387         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1388         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1389         adapter = (struct ena_adapter *)(dev->data->dev_private);
1390
1391         ena_dev = &adapter->ena_dev;
1392         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1393
1394         dev_info->speed_capa =
1395                         ETH_LINK_SPEED_1G   |
1396                         ETH_LINK_SPEED_2_5G |
1397                         ETH_LINK_SPEED_5G   |
1398                         ETH_LINK_SPEED_10G  |
1399                         ETH_LINK_SPEED_25G  |
1400                         ETH_LINK_SPEED_40G  |
1401                         ETH_LINK_SPEED_50G  |
1402                         ETH_LINK_SPEED_100G;
1403
1404         /* Get supported features from HW */
1405         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1406         if (unlikely(rc)) {
1407                 RTE_LOG(ERR, PMD,
1408                         "Cannot get attribute for ena device rc= %d\n", rc);
1409                 return;
1410         }
1411
1412         /* Set Tx & Rx features available for device */
1413         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1414                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1415
1416         if (feat.offload.tx &
1417             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1418                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1419                         DEV_TX_OFFLOAD_UDP_CKSUM |
1420                         DEV_TX_OFFLOAD_TCP_CKSUM;
1421
1422         if (feat.offload.tx &
1423             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1424                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1425                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1426                         DEV_RX_OFFLOAD_TCP_CKSUM;
1427
1428         /* Inform framework about available features */
1429         dev_info->rx_offload_capa = rx_feat;
1430         dev_info->tx_offload_capa = tx_feat;
1431
1432         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1433         dev_info->max_rx_pktlen  = adapter->max_mtu;
1434         dev_info->max_mac_addrs = 1;
1435
1436         dev_info->max_rx_queues = adapter->num_queues;
1437         dev_info->max_tx_queues = adapter->num_queues;
1438         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1439 }
1440
1441 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1442                                   uint16_t nb_pkts)
1443 {
1444         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1445         unsigned int ring_size = rx_ring->ring_size;
1446         unsigned int ring_mask = ring_size - 1;
1447         uint16_t next_to_clean = rx_ring->next_to_clean;
1448         int desc_in_use = 0;
1449         unsigned int recv_idx = 0;
1450         struct rte_mbuf *mbuf = NULL;
1451         struct rte_mbuf *mbuf_head = NULL;
1452         struct rte_mbuf *mbuf_prev = NULL;
1453         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1454         unsigned int completed;
1455
1456         struct ena_com_rx_ctx ena_rx_ctx;
1457         int rc = 0;
1458
1459         /* Check adapter state */
1460         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1461                 RTE_LOG(ALERT, PMD,
1462                         "Trying to receive pkts while device is NOT running\n");
1463                 return 0;
1464         }
1465
1466         desc_in_use = ENA_CIRC_COUNT(rx_ring->next_to_use,
1467                                      next_to_clean, ring_size);
1468         if (unlikely(nb_pkts > desc_in_use))
1469                 nb_pkts = desc_in_use;
1470
1471         for (completed = 0; completed < nb_pkts; completed++) {
1472                 int segments = 0;
1473
1474                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1475                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1476                 ena_rx_ctx.descs = 0;
1477                 /* receive packet context */
1478                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1479                                     rx_ring->ena_com_io_sq,
1480                                     &ena_rx_ctx);
1481                 if (unlikely(rc)) {
1482                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1483                         return 0;
1484                 }
1485
1486                 if (unlikely(ena_rx_ctx.descs == 0))
1487                         break;
1488
1489                 while (segments < ena_rx_ctx.descs) {
1490                         mbuf = rx_buff_info[next_to_clean & ring_mask];
1491                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1492                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1493                         mbuf->refcnt = 1;
1494                         mbuf->next = NULL;
1495                         if (segments == 0) {
1496                                 mbuf->nb_segs = ena_rx_ctx.descs;
1497                                 mbuf->port = rx_ring->port_id;
1498                                 mbuf->pkt_len = 0;
1499                                 mbuf_head = mbuf;
1500                         } else {
1501                                 /* for multi-segment pkts create mbuf chain */
1502                                 mbuf_prev->next = mbuf;
1503                         }
1504                         mbuf_head->pkt_len += mbuf->data_len;
1505
1506                         mbuf_prev = mbuf;
1507                         segments++;
1508                         next_to_clean =
1509                                 ENA_RX_RING_IDX_NEXT(next_to_clean, ring_size);
1510                 }
1511
1512                 /* fill mbuf attributes if any */
1513                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1514                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1515
1516                 /* pass to DPDK application head mbuf */
1517                 rx_pkts[recv_idx] = mbuf_head;
1518                 recv_idx++;
1519         }
1520
1521         /* Burst refill to save doorbells, memory barriers, const interval */
1522         if (ring_size - desc_in_use - 1 > ENA_RING_DESCS_RATIO(ring_size))
1523                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use - 1);
1524
1525         rx_ring->next_to_clean = next_to_clean & ring_mask;
1526
1527         return recv_idx;
1528 }
1529
1530 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1531                                   uint16_t nb_pkts)
1532 {
1533         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1534         unsigned int next_to_use = tx_ring->next_to_use;
1535         struct rte_mbuf *mbuf;
1536         unsigned int ring_size = tx_ring->ring_size;
1537         unsigned int ring_mask = ring_size - 1;
1538         struct ena_com_tx_ctx ena_tx_ctx;
1539         struct ena_tx_buffer *tx_info;
1540         struct ena_com_buf *ebuf;
1541         uint16_t rc, req_id, total_tx_descs = 0;
1542         int sent_idx = 0;
1543         int nb_hw_desc;
1544
1545         /* Check adapter state */
1546         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1547                 RTE_LOG(ALERT, PMD,
1548                         "Trying to xmit pkts while device is NOT running\n");
1549                 return 0;
1550         }
1551
1552         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1553                 mbuf = tx_pkts[sent_idx];
1554
1555                 req_id = tx_ring->empty_tx_reqs[next_to_use];
1556                 tx_info = &tx_ring->tx_buffer_info[req_id];
1557                 tx_info->mbuf = mbuf;
1558                 tx_info->num_of_bufs = 0;
1559                 ebuf = tx_info->bufs;
1560
1561                 /* Prepare TX context */
1562                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1563                 memset(&ena_tx_ctx.ena_meta, 0x0,
1564                        sizeof(struct ena_com_tx_meta));
1565                 ena_tx_ctx.ena_bufs = ebuf;
1566                 ena_tx_ctx.req_id = req_id;
1567                 if (tx_ring->tx_mem_queue_type ==
1568                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1569                         /* prepare the push buffer with
1570                          * virtual address of the data
1571                          */
1572                         ena_tx_ctx.header_len =
1573                                 RTE_MIN(mbuf->data_len,
1574                                         tx_ring->tx_max_header_size);
1575                         ena_tx_ctx.push_header =
1576                                 (void *)((char *)mbuf->buf_addr +
1577                                          mbuf->data_off);
1578                 } /* there's no else as we take advantage of memset zeroing */
1579
1580                 /* Set TX offloads flags, if applicable */
1581                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx);
1582
1583                 if (unlikely(mbuf->ol_flags &
1584                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1585                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1586
1587                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1588
1589                 /* Process first segment taking into
1590                  * consideration pushed header
1591                  */
1592                 if (mbuf->data_len > ena_tx_ctx.header_len) {
1593                         ebuf->paddr = mbuf->buf_physaddr +
1594                                       mbuf->data_off +
1595                                       ena_tx_ctx.header_len;
1596                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1597                         ebuf++;
1598                         tx_info->num_of_bufs++;
1599                 }
1600
1601                 while ((mbuf = mbuf->next) != NULL) {
1602                         ebuf->paddr = mbuf->buf_physaddr + mbuf->data_off;
1603                         ebuf->len = mbuf->data_len;
1604                         ebuf++;
1605                         tx_info->num_of_bufs++;
1606                 }
1607
1608                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1609
1610                 /* Write data to device */
1611                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1612                                         &ena_tx_ctx, &nb_hw_desc);
1613                 if (unlikely(rc))
1614                         break;
1615
1616                 tx_info->tx_descs = nb_hw_desc;
1617
1618                 next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use, ring_size);
1619         }
1620
1621         /* Let HW do it's best :-) */
1622         rte_wmb();
1623         ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1624
1625         /* Clear complete packets  */
1626         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1627                 /* Get Tx info & store how many descs were processed  */
1628                 tx_info = &tx_ring->tx_buffer_info[req_id];
1629                 total_tx_descs += tx_info->tx_descs;
1630
1631                 /* Free whole mbuf chain  */
1632                 mbuf = tx_info->mbuf;
1633                 rte_pktmbuf_free(mbuf);
1634
1635                 /* Put back descriptor to the ring for reuse */
1636                 tx_ring->empty_tx_reqs[tx_ring->next_to_clean] = req_id;
1637                 tx_ring->next_to_clean =
1638                         ENA_TX_RING_IDX_NEXT(tx_ring->next_to_clean,
1639                                              tx_ring->ring_size);
1640
1641                 /* If too many descs to clean, leave it for another run */
1642                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1643                         break;
1644         }
1645
1646         /* acknowledge completion of sent packets */
1647         ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1648         tx_ring->next_to_use = next_to_use;
1649         return sent_idx;
1650 }
1651
1652 static struct eth_driver rte_ena_pmd = {
1653         {
1654                 .name = "rte_ena_pmd",
1655                 .id_table = pci_id_ena_map,
1656                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1657         },
1658         .eth_dev_init = eth_ena_dev_init,
1659         .dev_private_size = sizeof(struct ena_adapter),
1660 };
1661
1662 static int
1663 rte_ena_pmd_init(const char *name __rte_unused,
1664                  const char *params __rte_unused)
1665 {
1666         rte_eth_driver_register(&rte_ena_pmd);
1667         return 0;
1668 };
1669
1670 struct rte_driver ena_pmd_drv = {
1671         .type = PMD_PDEV,
1672         .init = rte_ena_pmd_init,
1673 };
1674
1675 PMD_REGISTER_DRIVER(ena_pmd_drv, ena);
1676 DRIVER_REGISTER_PCI_TABLE(ena, pci_id_ena_map);