drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_string_fns.h>
  35 #include <rte_ether.h>
  36 #include <rte_ethdev_driver.h>
  37 #include <rte_ethdev_pci.h>
  38 #include <rte_tcp.h>
  39 #include <rte_atomic.h>
  40 #include <rte_dev.h>
  41 #include <rte_errno.h>
  42 #include <rte_version.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    2
  57 #define DRV_MODULE_VER_MINOR    0
  58 #define DRV_MODULE_VER_SUBMINOR 1
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ETH_GSTRING_LEN 32
  84
  85 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  86
  87 #define ENA_MIN_RING_DESC       128
  88
  89 enum ethtool_stringset {
  90         ETH_SS_TEST             = 0,
  91         ETH_SS_STATS,
  92 };
  93
  94 struct ena_stats {
  95         char name[ETH_GSTRING_LEN];
  96         int stat_offset;
  97 };
  98
  99 #define ENA_STAT_ENTRY(stat, stat_type) { \
 100         .name = #stat, \
 101         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 102 }
 103
 104 #define ENA_STAT_RX_ENTRY(stat) \
 105         ENA_STAT_ENTRY(stat, rx)
 106
 107 #define ENA_STAT_TX_ENTRY(stat) \
 108         ENA_STAT_ENTRY(stat, tx)
 109
 110 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 111         ENA_STAT_ENTRY(stat, dev)
 112
 113 #define ENA_MAX_RING_SIZE_RX 8192
 114 #define ENA_MAX_RING_SIZE_TX 1024
 115
 116 /*
 117  * Each rte_memzone should have unique name.
 118  * To satisfy it, count number of allocation and add it to name.
 119  */
 120 uint32_t ena_alloc_cnt;
 121
 122 static const struct ena_stats ena_stats_global_strings[] = {
 123         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 124         ENA_STAT_GLOBAL_ENTRY(dev_start),
 125         ENA_STAT_GLOBAL_ENTRY(dev_stop),
 126 };
 127
 128 static const struct ena_stats ena_stats_tx_strings[] = {
 129         ENA_STAT_TX_ENTRY(cnt),
 130         ENA_STAT_TX_ENTRY(bytes),
 131         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 132         ENA_STAT_TX_ENTRY(linearize),
 133         ENA_STAT_TX_ENTRY(linearize_failed),
 134         ENA_STAT_TX_ENTRY(tx_poll),
 135         ENA_STAT_TX_ENTRY(doorbells),
 136         ENA_STAT_TX_ENTRY(bad_req_id),
 137         ENA_STAT_TX_ENTRY(available_desc),
 138 };
 139
 140 static const struct ena_stats ena_stats_rx_strings[] = {
 141         ENA_STAT_RX_ENTRY(cnt),
 142         ENA_STAT_RX_ENTRY(bytes),
 143         ENA_STAT_RX_ENTRY(refill_partial),
 144         ENA_STAT_RX_ENTRY(bad_csum),
 145         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 146         ENA_STAT_RX_ENTRY(bad_desc_num),
 147         ENA_STAT_RX_ENTRY(bad_req_id),
 148 };
 149
 150 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 151 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 152 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 153
 154 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 155                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 156                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 157                         DEV_TX_OFFLOAD_TCP_TSO)
 158 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 159                        PKT_TX_IP_CKSUM |\
 160                        PKT_TX_TCP_SEG)
 161
 162 /** Vendor ID used by Amazon devices */
 163 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 164 /** Amazon devices */
 165 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 166 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 167
 168 #define ENA_TX_OFFLOAD_MASK     (\
 169         PKT_TX_L4_MASK |         \
 170         PKT_TX_IPV6 |            \
 171         PKT_TX_IPV4 |            \
 172         PKT_TX_IP_CKSUM |        \
 173         PKT_TX_TCP_SEG)
 174
 175 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 176         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 177
 178 int ena_logtype_init;
 179 int ena_logtype_driver;
 180
 181 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
 182 int ena_logtype_rx;
 183 #endif
 184 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
 185 int ena_logtype_tx;
 186 #endif
 187 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
 188 int ena_logtype_tx_free;
 189 #endif
 190 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
 191 int ena_logtype_com;
 192 #endif
 193
 194 static const struct rte_pci_id pci_id_ena_map[] = {
 195         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 196         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 197         { .device_id = 0 },
 198 };
 199
 200 static struct ena_aenq_handlers aenq_handlers;
 201
 202 static int ena_device_init(struct ena_com_dev *ena_dev,
 203                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 204                            bool *wd_state);
 205 static int ena_dev_configure(struct rte_eth_dev *dev);
 206 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 207                                   uint16_t nb_pkts);
 208 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 209                 uint16_t nb_pkts);
 210 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 211                               uint16_t nb_desc, unsigned int socket_id,
 212                               const struct rte_eth_txconf *tx_conf);
 213 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 214                               uint16_t nb_desc, unsigned int socket_id,
 215                               const struct rte_eth_rxconf *rx_conf,
 216                               struct rte_mempool *mp);
 217 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 218                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 219 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 220 static void ena_init_rings(struct ena_adapter *adapter);
 221 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 222 static int ena_start(struct rte_eth_dev *dev);
 223 static void ena_stop(struct rte_eth_dev *dev);
 224 static void ena_close(struct rte_eth_dev *dev);
 225 static int ena_dev_reset(struct rte_eth_dev *dev);
 226 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 227 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 228 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 229 static void ena_rx_queue_release(void *queue);
 230 static void ena_tx_queue_release(void *queue);
 231 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 232 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 233 static int ena_link_update(struct rte_eth_dev *dev,
 234                            int wait_to_complete);
 235 static int ena_create_io_queue(struct ena_ring *ring);
 236 static void ena_queue_stop(struct ena_ring *ring);
 237 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 238                               enum ena_ring_type ring_type);
 239 static int ena_queue_start(struct ena_ring *ring);
 240 static int ena_queue_start_all(struct rte_eth_dev *dev,
 241                                enum ena_ring_type ring_type);
 242 static void ena_stats_restart(struct rte_eth_dev *dev);
 243 static int ena_infos_get(struct rte_eth_dev *dev,
 244                          struct rte_eth_dev_info *dev_info);
 245 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 246                                struct rte_eth_rss_reta_entry64 *reta_conf,
 247                                uint16_t reta_size);
 248 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 249                               struct rte_eth_rss_reta_entry64 *reta_conf,
 250                               uint16_t reta_size);
 251 static void ena_interrupt_handler_rte(void *cb_arg);
 252 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 253 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 254 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 255 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 256                                 struct rte_eth_xstat_name *xstats_names,
 257                                 unsigned int n);
 258 static int ena_xstats_get(struct rte_eth_dev *dev,
 259                           struct rte_eth_xstat *stats,
 260                           unsigned int n);
 261 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 262                                 const uint64_t *ids,
 263                                 uint64_t *values,
 264                                 unsigned int n);
 265
 266 static const struct eth_dev_ops ena_dev_ops = {
 267         .dev_configure        = ena_dev_configure,
 268         .dev_infos_get        = ena_infos_get,
 269         .rx_queue_setup       = ena_rx_queue_setup,
 270         .tx_queue_setup       = ena_tx_queue_setup,
 271         .dev_start            = ena_start,
 272         .dev_stop             = ena_stop,
 273         .link_update          = ena_link_update,
 274         .stats_get            = ena_stats_get,
 275         .xstats_get_names     = ena_xstats_get_names,
 276         .xstats_get           = ena_xstats_get,
 277         .xstats_get_by_id     = ena_xstats_get_by_id,
 278         .mtu_set              = ena_mtu_set,
 279         .rx_queue_release     = ena_rx_queue_release,
 280         .tx_queue_release     = ena_tx_queue_release,
 281         .dev_close            = ena_close,
 282         .dev_reset            = ena_dev_reset,
 283         .reta_update          = ena_rss_reta_update,
 284         .reta_query           = ena_rss_reta_query,
 285 };
 286
 287 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 288                                        struct ena_com_rx_ctx *ena_rx_ctx)
 289 {
 290         uint64_t ol_flags = 0;
 291         uint32_t packet_type = 0;
 292
 293         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 294                 packet_type |= RTE_PTYPE_L4_TCP;
 295         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 296                 packet_type |= RTE_PTYPE_L4_UDP;
 297
 298         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 299                 packet_type |= RTE_PTYPE_L3_IPV4;
 300         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 301                 packet_type |= RTE_PTYPE_L3_IPV6;
 302
 303         if (unlikely(ena_rx_ctx->l4_csum_err))
 304                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 305         if (unlikely(ena_rx_ctx->l3_csum_err))
 306                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 307
 308         mbuf->ol_flags = ol_flags;
 309         mbuf->packet_type = packet_type;
 310 }
 311
 312 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 313                                        struct ena_com_tx_ctx *ena_tx_ctx,
 314                                        uint64_t queue_offloads)
 315 {
 316         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 317
 318         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 319             (queue_offloads & QUEUE_OFFLOADS)) {
 320                 /* check if TSO is required */
 321                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 322                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 323                         ena_tx_ctx->tso_enable = true;
 324
 325                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 326                 }
 327
 328                 /* check if L3 checksum is needed */
 329                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 330                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 331                         ena_tx_ctx->l3_csum_enable = true;
 332
 333                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 334                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 335                 } else {
 336                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 337
 338                         /* set don't fragment (DF) flag */
 339                         if (mbuf->packet_type &
 340                                 (RTE_PTYPE_L4_NONFRAG
 341                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 342                                 ena_tx_ctx->df = true;
 343                 }
 344
 345                 /* check if L4 checksum is needed */
 346                 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
 347                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 348                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 349                         ena_tx_ctx->l4_csum_enable = true;
 350                 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
 351                                 PKT_TX_UDP_CKSUM) &&
 352                                 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 353                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 354                         ena_tx_ctx->l4_csum_enable = true;
 355                 } else {
 356                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 357                         ena_tx_ctx->l4_csum_enable = false;
 358                 }
 359
 360                 ena_meta->mss = mbuf->tso_segsz;
 361                 ena_meta->l3_hdr_len = mbuf->l3_len;
 362                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 363
 364                 ena_tx_ctx->meta_valid = true;
 365         } else {
 366                 ena_tx_ctx->meta_valid = false;
 367         }
 368 }
 369
 370 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 371 {
 372         if (likely(req_id < rx_ring->ring_size))
 373                 return 0;
 374
 375         PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id);
 376
 377         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 378         rx_ring->adapter->trigger_reset = true;
 379         ++rx_ring->rx_stats.bad_req_id;
 380
 381         return -EFAULT;
 382 }
 383
 384 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 385 {
 386         struct ena_tx_buffer *tx_info = NULL;
 387
 388         if (likely(req_id < tx_ring->ring_size)) {
 389                 tx_info = &tx_ring->tx_buffer_info[req_id];
 390                 if (likely(tx_info->mbuf))
 391                         return 0;
 392         }
 393
 394         if (tx_info)
 395                 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 396         else
 397                 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 398
 399         /* Trigger device reset */
 400         ++tx_ring->tx_stats.bad_req_id;
 401         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 402         tx_ring->adapter->trigger_reset = true;
 403         return -EFAULT;
 404 }
 405
 406 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 407 {
 408         struct ena_admin_host_info *host_info;
 409         int rc;
 410
 411         /* Allocate only the host info */
 412         rc = ena_com_allocate_host_info(ena_dev);
 413         if (rc) {
 414                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 415                 return;
 416         }
 417
 418         host_info = ena_dev->host_attr.host_info;
 419
 420         host_info->os_type = ENA_ADMIN_OS_DPDK;
 421         host_info->kernel_ver = RTE_VERSION;
 422         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 423                 sizeof(host_info->kernel_ver_str));
 424         host_info->os_dist = RTE_VERSION;
 425         strlcpy((char *)host_info->os_dist_str, rte_version(),
 426                 sizeof(host_info->os_dist_str));
 427         host_info->driver_version =
 428                 (DRV_MODULE_VER_MAJOR) |
 429                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 430                 (DRV_MODULE_VER_SUBMINOR <<
 431                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 432         host_info->num_cpus = rte_lcore_count();
 433
 434         rc = ena_com_set_host_attributes(ena_dev);
 435         if (rc) {
 436                 if (rc == -ENA_COM_UNSUPPORTED)
 437                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 438                 else
 439                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 440
 441                 goto err;
 442         }
 443
 444         return;
 445
 446 err:
 447         ena_com_delete_host_info(ena_dev);
 448 }
 449
 450 /* This function calculates the number of xstats based on the current config */
 451 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
 452 {
 453         return ENA_STATS_ARRAY_GLOBAL +
 454                 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 455                 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 456 }
 457
 458 static void ena_config_debug_area(struct ena_adapter *adapter)
 459 {
 460         u32 debug_area_size;
 461         int rc, ss_count;
 462
 463         ss_count = ena_xstats_calc_num(adapter->rte_dev);
 464
 465         /* allocate 32 bytes for each string and 64bit for the value */
 466         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 467
 468         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 469         if (rc) {
 470                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 471                 return;
 472         }
 473
 474         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 475         if (rc) {
 476                 if (rc == -ENA_COM_UNSUPPORTED)
 477                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 478                 else
 479                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 480
 481                 goto err;
 482         }
 483
 484         return;
 485 err:
 486         ena_com_delete_debug_area(&adapter->ena_dev);
 487 }
 488
 489 static void ena_close(struct rte_eth_dev *dev)
 490 {
 491         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 492         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 493         struct ena_adapter *adapter = dev->data->dev_private;
 494
 495         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 496                 ena_stop(dev);
 497         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 498
 499         ena_rx_queue_release_all(dev);
 500         ena_tx_queue_release_all(dev);
 501
 502         rte_free(adapter->drv_stats);
 503         adapter->drv_stats = NULL;
 504
 505         rte_intr_disable(intr_handle);
 506         rte_intr_callback_unregister(intr_handle,
 507                                      ena_interrupt_handler_rte,
 508                                      adapter);
 509
 510         /*
 511          * MAC is not allocated dynamically. Setting NULL should prevent from
 512          * release of the resource in the rte_eth_dev_release_port().
 513          */
 514         dev->data->mac_addrs = NULL;
 515 }
 516
 517 static int
 518 ena_dev_reset(struct rte_eth_dev *dev)
 519 {
 520         int rc = 0;
 521
 522         ena_destroy_device(dev);
 523         rc = eth_ena_dev_init(dev);
 524         if (rc)
 525                 PMD_INIT_LOG(CRIT, "Cannot initialize device");
 526
 527         return rc;
 528 }
 529
 530 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 531                                struct rte_eth_rss_reta_entry64 *reta_conf,
 532                                uint16_t reta_size)
 533 {
 534         struct ena_adapter *adapter = dev->data->dev_private;
 535         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 536         int rc, i;
 537         u16 entry_value;
 538         int conf_idx;
 539         int idx;
 540
 541         if ((reta_size == 0) || (reta_conf == NULL))
 542                 return -EINVAL;
 543
 544         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 545                 PMD_DRV_LOG(WARNING,
 546                         "indirection table %d is bigger than supported (%d)\n",
 547                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 548                 return -EINVAL;
 549         }
 550
 551         for (i = 0 ; i < reta_size ; i++) {
 552                 /* each reta_conf is for 64 entries.
 553                  * to support 128 we use 2 conf of 64
 554                  */
 555                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 556                 idx = i % RTE_RETA_GROUP_SIZE;
 557                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 558                         entry_value =
 559                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 560
 561                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 562                                                                i,
 563                                                                entry_value);
 564                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 565                                 PMD_DRV_LOG(ERR,
 566                                         "Cannot fill indirect table\n");
 567                                 return rc;
 568                         }
 569                 }
 570         }
 571
 572         rc = ena_com_indirect_table_set(ena_dev);
 573         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 574                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 575                 return rc;
 576         }
 577
 578         PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries  for port %d\n",
 579                 __func__, reta_size, adapter->rte_dev->data->port_id);
 580
 581         return 0;
 582 }
 583
 584 /* Query redirection table. */
 585 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 586                               struct rte_eth_rss_reta_entry64 *reta_conf,
 587                               uint16_t reta_size)
 588 {
 589         struct ena_adapter *adapter = dev->data->dev_private;
 590         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 591         int rc;
 592         int i;
 593         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 594         int reta_conf_idx;
 595         int reta_idx;
 596
 597         if (reta_size == 0 || reta_conf == NULL ||
 598             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 599                 return -EINVAL;
 600
 601         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 602         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 603                 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
 604                 return -ENOTSUP;
 605         }
 606
 607         for (i = 0 ; i < reta_size ; i++) {
 608                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 609                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 610                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 611                         reta_conf[reta_conf_idx].reta[reta_idx] =
 612                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 613         }
 614
 615         return 0;
 616 }
 617
 618 static int ena_rss_init_default(struct ena_adapter *adapter)
 619 {
 620         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 621         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 622         int rc, i;
 623         u32 val;
 624
 625         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 626         if (unlikely(rc)) {
 627                 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
 628                 goto err_rss_init;
 629         }
 630
 631         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 632                 val = i % nb_rx_queues;
 633                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 634                                                        ENA_IO_RXQ_IDX(val));
 635                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 636                         PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
 637                         goto err_fill_indir;
 638                 }
 639         }
 640
 641         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 642                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 643         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 644                 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
 645                 goto err_fill_indir;
 646         }
 647
 648         rc = ena_com_set_default_hash_ctrl(ena_dev);
 649         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 650                 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
 651                 goto err_fill_indir;
 652         }
 653
 654         rc = ena_com_indirect_table_set(ena_dev);
 655         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 656                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 657                 goto err_fill_indir;
 658         }
 659         PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
 660                 adapter->rte_dev->data->port_id);
 661
 662         return 0;
 663
 664 err_fill_indir:
 665         ena_com_rss_destroy(ena_dev);
 666 err_rss_init:
 667
 668         return rc;
 669 }
 670
 671 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 672 {
 673         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 674         int nb_queues = dev->data->nb_rx_queues;
 675         int i;
 676
 677         for (i = 0; i < nb_queues; i++)
 678                 ena_rx_queue_release(queues[i]);
 679 }
 680
 681 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 682 {
 683         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 684         int nb_queues = dev->data->nb_tx_queues;
 685         int i;
 686
 687         for (i = 0; i < nb_queues; i++)
 688                 ena_tx_queue_release(queues[i]);
 689 }
 690
 691 static void ena_rx_queue_release(void *queue)
 692 {
 693         struct ena_ring *ring = (struct ena_ring *)queue;
 694
 695         /* Free ring resources */
 696         if (ring->rx_buffer_info)
 697                 rte_free(ring->rx_buffer_info);
 698         ring->rx_buffer_info = NULL;
 699
 700         if (ring->rx_refill_buffer)
 701                 rte_free(ring->rx_refill_buffer);
 702         ring->rx_refill_buffer = NULL;
 703
 704         if (ring->empty_rx_reqs)
 705                 rte_free(ring->empty_rx_reqs);
 706         ring->empty_rx_reqs = NULL;
 707
 708         ring->configured = 0;
 709
 710         PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
 711                 ring->port_id, ring->id);
 712 }
 713
 714 static void ena_tx_queue_release(void *queue)
 715 {
 716         struct ena_ring *ring = (struct ena_ring *)queue;
 717
 718         /* Free ring resources */
 719         if (ring->push_buf_intermediate_buf)
 720                 rte_free(ring->push_buf_intermediate_buf);
 721
 722         if (ring->tx_buffer_info)
 723                 rte_free(ring->tx_buffer_info);
 724
 725         if (ring->empty_tx_reqs)
 726                 rte_free(ring->empty_tx_reqs);
 727
 728         ring->empty_tx_reqs = NULL;
 729         ring->tx_buffer_info = NULL;
 730         ring->push_buf_intermediate_buf = NULL;
 731
 732         ring->configured = 0;
 733
 734         PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
 735                 ring->port_id, ring->id);
 736 }
 737
 738 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 739 {
 740         unsigned int i;
 741
 742         for (i = 0; i < ring->ring_size; ++i)
 743                 if (ring->rx_buffer_info[i]) {
 744                         rte_mbuf_raw_free(ring->rx_buffer_info[i]);
 745                         ring->rx_buffer_info[i] = NULL;
 746                 }
 747 }
 748
 749 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 750 {
 751         unsigned int i;
 752
 753         for (i = 0; i < ring->ring_size; ++i) {
 754                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 755
 756                 if (tx_buf->mbuf)
 757                         rte_pktmbuf_free(tx_buf->mbuf);
 758         }
 759 }
 760
 761 static int ena_link_update(struct rte_eth_dev *dev,
 762                            __rte_unused int wait_to_complete)
 763 {
 764         struct rte_eth_link *link = &dev->data->dev_link;
 765         struct ena_adapter *adapter = dev->data->dev_private;
 766
 767         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 768         link->link_speed = ETH_SPEED_NUM_NONE;
 769         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 770
 771         return 0;
 772 }
 773
 774 static int ena_queue_start_all(struct rte_eth_dev *dev,
 775                                enum ena_ring_type ring_type)
 776 {
 777         struct ena_adapter *adapter = dev->data->dev_private;
 778         struct ena_ring *queues = NULL;
 779         int nb_queues;
 780         int i = 0;
 781         int rc = 0;
 782
 783         if (ring_type == ENA_RING_TYPE_RX) {
 784                 queues = adapter->rx_ring;
 785                 nb_queues = dev->data->nb_rx_queues;
 786         } else {
 787                 queues = adapter->tx_ring;
 788                 nb_queues = dev->data->nb_tx_queues;
 789         }
 790         for (i = 0; i < nb_queues; i++) {
 791                 if (queues[i].configured) {
 792                         if (ring_type == ENA_RING_TYPE_RX) {
 793                                 ena_assert_msg(
 794                                         dev->data->rx_queues[i] == &queues[i],
 795                                         "Inconsistent state of rx queues\n");
 796                         } else {
 797                                 ena_assert_msg(
 798                                         dev->data->tx_queues[i] == &queues[i],
 799                                         "Inconsistent state of tx queues\n");
 800                         }
 801
 802                         rc = ena_queue_start(&queues[i]);
 803
 804                         if (rc) {
 805                                 PMD_INIT_LOG(ERR,
 806                                              "failed to start queue %d type(%d)",
 807                                              i, ring_type);
 808                                 goto err;
 809                         }
 810                 }
 811         }
 812
 813         return 0;
 814
 815 err:
 816         while (i--)
 817                 if (queues[i].configured)
 818                         ena_queue_stop(&queues[i]);
 819
 820         return rc;
 821 }
 822
 823 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 824 {
 825         uint32_t max_frame_len = adapter->max_mtu;
 826
 827         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 828             DEV_RX_OFFLOAD_JUMBO_FRAME)
 829                 max_frame_len =
 830                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 831
 832         return max_frame_len;
 833 }
 834
 835 static int ena_check_valid_conf(struct ena_adapter *adapter)
 836 {
 837         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 838
 839         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 840                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 841                                   "max mtu: %d, min mtu: %d",
 842                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 843                 return ENA_COM_UNSUPPORTED;
 844         }
 845
 846         return 0;
 847 }
 848
 849 static int
 850 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)
 851 {
 852         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 853         struct ena_com_dev *ena_dev = ctx->ena_dev;
 854         uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX;
 855         uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX;
 856
 857         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 858                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 859                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 860                 rx_queue_size = RTE_MIN(rx_queue_size,
 861                         max_queue_ext->max_rx_cq_depth);
 862                 rx_queue_size = RTE_MIN(rx_queue_size,
 863                         max_queue_ext->max_rx_sq_depth);
 864                 tx_queue_size = RTE_MIN(tx_queue_size,
 865                         max_queue_ext->max_tx_cq_depth);
 866
 867                 if (ena_dev->tx_mem_queue_type ==
 868                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 869                         tx_queue_size = RTE_MIN(tx_queue_size,
 870                                 llq->max_llq_depth);
 871                 } else {
 872                         tx_queue_size = RTE_MIN(tx_queue_size,
 873                                 max_queue_ext->max_tx_sq_depth);
 874                 }
 875
 876                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 877                         max_queue_ext->max_per_packet_rx_descs);
 878                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 879                         max_queue_ext->max_per_packet_tx_descs);
 880         } else {
 881                 struct ena_admin_queue_feature_desc *max_queues =
 882                         &ctx->get_feat_ctx->max_queues;
 883                 rx_queue_size = RTE_MIN(rx_queue_size,
 884                         max_queues->max_cq_depth);
 885                 rx_queue_size = RTE_MIN(rx_queue_size,
 886                         max_queues->max_sq_depth);
 887                 tx_queue_size = RTE_MIN(tx_queue_size,
 888                         max_queues->max_cq_depth);
 889
 890                 if (ena_dev->tx_mem_queue_type ==
 891                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 892                         tx_queue_size = RTE_MIN(tx_queue_size,
 893                                 llq->max_llq_depth);
 894                 } else {
 895                         tx_queue_size = RTE_MIN(tx_queue_size,
 896                                 max_queues->max_sq_depth);
 897                 }
 898
 899                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 900                         max_queues->max_packet_tx_descs);
 901                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 902                         max_queues->max_packet_rx_descs);
 903         }
 904
 905         /* Round down to the nearest power of 2 */
 906         rx_queue_size = rte_align32prevpow2(rx_queue_size);
 907         tx_queue_size = rte_align32prevpow2(tx_queue_size);
 908
 909         if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) {
 910                 PMD_INIT_LOG(ERR, "Invalid queue size");
 911                 return -EFAULT;
 912         }
 913
 914         ctx->rx_queue_size = rx_queue_size;
 915         ctx->tx_queue_size = tx_queue_size;
 916
 917         return 0;
 918 }
 919
 920 static void ena_stats_restart(struct rte_eth_dev *dev)
 921 {
 922         struct ena_adapter *adapter = dev->data->dev_private;
 923
 924         rte_atomic64_init(&adapter->drv_stats->ierrors);
 925         rte_atomic64_init(&adapter->drv_stats->oerrors);
 926         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 927         rte_atomic64_init(&adapter->drv_stats->rx_drops);
 928 }
 929
 930 static int ena_stats_get(struct rte_eth_dev *dev,
 931                           struct rte_eth_stats *stats)
 932 {
 933         struct ena_admin_basic_stats ena_stats;
 934         struct ena_adapter *adapter = dev->data->dev_private;
 935         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 936         int rc;
 937         int i;
 938         int max_rings_stats;
 939
 940         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 941                 return -ENOTSUP;
 942
 943         memset(&ena_stats, 0, sizeof(ena_stats));
 944         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 945         if (unlikely(rc)) {
 946                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 947                 return rc;
 948         }
 949
 950         /* Set of basic statistics from ENA */
 951         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 952                                           ena_stats.rx_pkts_low);
 953         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 954                                           ena_stats.tx_pkts_low);
 955         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 956                                         ena_stats.rx_bytes_low);
 957         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 958                                         ena_stats.tx_bytes_low);
 959
 960         /* Driver related stats */
 961         stats->imissed = rte_atomic64_read(&adapter->drv_stats->rx_drops);
 962         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 963         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 964         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 965
 966         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
 967                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 968         for (i = 0; i < max_rings_stats; ++i) {
 969                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
 970
 971                 stats->q_ibytes[i] = rx_stats->bytes;
 972                 stats->q_ipackets[i] = rx_stats->cnt;
 973                 stats->q_errors[i] = rx_stats->bad_desc_num +
 974                         rx_stats->bad_req_id;
 975         }
 976
 977         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
 978                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 979         for (i = 0; i < max_rings_stats; ++i) {
 980                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
 981
 982                 stats->q_obytes[i] = tx_stats->bytes;
 983                 stats->q_opackets[i] = tx_stats->cnt;
 984         }
 985
 986         return 0;
 987 }
 988
 989 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 990 {
 991         struct ena_adapter *adapter;
 992         struct ena_com_dev *ena_dev;
 993         int rc = 0;
 994
 995         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
 996         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
 997         adapter = dev->data->dev_private;
 998
 999         ena_dev = &adapter->ena_dev;
1000         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1001
1002         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1003                 PMD_DRV_LOG(ERR,
1004                         "Invalid MTU setting. new_mtu: %d "
1005                         "max mtu: %d min mtu: %d\n",
1006                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1007                 return -EINVAL;
1008         }
1009
1010         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1011         if (rc)
1012                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1013         else
1014                 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
1015
1016         return rc;
1017 }
1018
1019 static int ena_start(struct rte_eth_dev *dev)
1020 {
1021         struct ena_adapter *adapter = dev->data->dev_private;
1022         uint64_t ticks;
1023         int rc = 0;
1024
1025         rc = ena_check_valid_conf(adapter);
1026         if (rc)
1027                 return rc;
1028
1029         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1030         if (rc)
1031                 return rc;
1032
1033         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1034         if (rc)
1035                 goto err_start_tx;
1036
1037         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1038             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1039                 rc = ena_rss_init_default(adapter);
1040                 if (rc)
1041                         goto err_rss_init;
1042         }
1043
1044         ena_stats_restart(dev);
1045
1046         adapter->timestamp_wd = rte_get_timer_cycles();
1047         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1048
1049         ticks = rte_get_timer_hz();
1050         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1051                         ena_timer_wd_callback, adapter);
1052
1053         ++adapter->dev_stats.dev_start;
1054         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1055
1056         return 0;
1057
1058 err_rss_init:
1059         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1060 err_start_tx:
1061         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1062         return rc;
1063 }
1064
1065 static void ena_stop(struct rte_eth_dev *dev)
1066 {
1067         struct ena_adapter *adapter = dev->data->dev_private;
1068         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1069         int rc;
1070
1071         rte_timer_stop_sync(&adapter->timer_wd);
1072         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1073         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1074
1075         if (adapter->trigger_reset) {
1076                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1077                 if (rc)
1078                         PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1079         }
1080
1081         ++adapter->dev_stats.dev_stop;
1082         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1083 }
1084
1085 static int ena_create_io_queue(struct ena_ring *ring)
1086 {
1087         struct ena_adapter *adapter;
1088         struct ena_com_dev *ena_dev;
1089         struct ena_com_create_io_ctx ctx =
1090                 /* policy set to _HOST just to satisfy icc compiler */
1091                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1092                   0, 0, 0, 0, 0 };
1093         uint16_t ena_qid;
1094         unsigned int i;
1095         int rc;
1096
1097         adapter = ring->adapter;
1098         ena_dev = &adapter->ena_dev;
1099
1100         if (ring->type == ENA_RING_TYPE_TX) {
1101                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1102                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1103                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1104                 ctx.queue_size = adapter->tx_ring_size;
1105                 for (i = 0; i < ring->ring_size; i++)
1106                         ring->empty_tx_reqs[i] = i;
1107         } else {
1108                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1109                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1110                 ctx.queue_size = adapter->rx_ring_size;
1111                 for (i = 0; i < ring->ring_size; i++)
1112                         ring->empty_rx_reqs[i] = i;
1113         }
1114         ctx.qid = ena_qid;
1115         ctx.msix_vector = -1; /* interrupts not used */
1116         ctx.numa_node = ring->numa_socket_id;
1117
1118         rc = ena_com_create_io_queue(ena_dev, &ctx);
1119         if (rc) {
1120                 PMD_DRV_LOG(ERR,
1121                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1122                         ring->id, ena_qid, rc);
1123                 return rc;
1124         }
1125
1126         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1127                                      &ring->ena_com_io_sq,
1128                                      &ring->ena_com_io_cq);
1129         if (rc) {
1130                 PMD_DRV_LOG(ERR,
1131                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1132                         ring->id, rc);
1133                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1134                 return rc;
1135         }
1136
1137         if (ring->type == ENA_RING_TYPE_TX)
1138                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1139
1140         return 0;
1141 }
1142
1143 static void ena_queue_stop(struct ena_ring *ring)
1144 {
1145         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1146
1147         if (ring->type == ENA_RING_TYPE_RX) {
1148                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1149                 ena_rx_queue_release_bufs(ring);
1150         } else {
1151                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1152                 ena_tx_queue_release_bufs(ring);
1153         }
1154 }
1155
1156 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1157                               enum ena_ring_type ring_type)
1158 {
1159         struct ena_adapter *adapter = dev->data->dev_private;
1160         struct ena_ring *queues = NULL;
1161         uint16_t nb_queues, i;
1162
1163         if (ring_type == ENA_RING_TYPE_RX) {
1164                 queues = adapter->rx_ring;
1165                 nb_queues = dev->data->nb_rx_queues;
1166         } else {
1167                 queues = adapter->tx_ring;
1168                 nb_queues = dev->data->nb_tx_queues;
1169         }
1170
1171         for (i = 0; i < nb_queues; ++i)
1172                 if (queues[i].configured)
1173                         ena_queue_stop(&queues[i]);
1174 }
1175
1176 static int ena_queue_start(struct ena_ring *ring)
1177 {
1178         int rc, bufs_num;
1179
1180         ena_assert_msg(ring->configured == 1,
1181                        "Trying to start unconfigured queue\n");
1182
1183         rc = ena_create_io_queue(ring);
1184         if (rc) {
1185                 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1186                 return rc;
1187         }
1188
1189         ring->next_to_clean = 0;
1190         ring->next_to_use = 0;
1191
1192         if (ring->type == ENA_RING_TYPE_TX) {
1193                 ring->tx_stats.available_desc =
1194                         ena_com_free_desc(ring->ena_com_io_sq);
1195                 return 0;
1196         }
1197
1198         bufs_num = ring->ring_size - 1;
1199         rc = ena_populate_rx_queue(ring, bufs_num);
1200         if (rc != bufs_num) {
1201                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1202                                          ENA_IO_RXQ_IDX(ring->id));
1203                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1204                 return ENA_COM_FAULT;
1205         }
1206
1207         return 0;
1208 }
1209
1210 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1211                               uint16_t queue_idx,
1212                               uint16_t nb_desc,
1213                               unsigned int socket_id,
1214                               const struct rte_eth_txconf *tx_conf)
1215 {
1216         struct ena_ring *txq = NULL;
1217         struct ena_adapter *adapter = dev->data->dev_private;
1218         unsigned int i;
1219
1220         txq = &adapter->tx_ring[queue_idx];
1221
1222         if (txq->configured) {
1223                 PMD_DRV_LOG(CRIT,
1224                         "API violation. Queue %d is already configured\n",
1225                         queue_idx);
1226                 return ENA_COM_FAULT;
1227         }
1228
1229         if (!rte_is_power_of_2(nb_desc)) {
1230                 PMD_DRV_LOG(ERR,
1231                         "Unsupported size of TX queue: %d is not a power of 2.\n",
1232                         nb_desc);
1233                 return -EINVAL;
1234         }
1235
1236         if (nb_desc > adapter->tx_ring_size) {
1237                 PMD_DRV_LOG(ERR,
1238                         "Unsupported size of TX queue (max size: %d)\n",
1239                         adapter->tx_ring_size);
1240                 return -EINVAL;
1241         }
1242
1243         if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1244                 nb_desc = adapter->tx_ring_size;
1245
1246         txq->port_id = dev->data->port_id;
1247         txq->next_to_clean = 0;
1248         txq->next_to_use = 0;
1249         txq->ring_size = nb_desc;
1250         txq->numa_socket_id = socket_id;
1251
1252         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1253                                           sizeof(struct ena_tx_buffer) *
1254                                           txq->ring_size,
1255                                           RTE_CACHE_LINE_SIZE);
1256         if (!txq->tx_buffer_info) {
1257                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1258                 return -ENOMEM;
1259         }
1260
1261         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1262                                          sizeof(u16) * txq->ring_size,
1263                                          RTE_CACHE_LINE_SIZE);
1264         if (!txq->empty_tx_reqs) {
1265                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1266                 rte_free(txq->tx_buffer_info);
1267                 return -ENOMEM;
1268         }
1269
1270         txq->push_buf_intermediate_buf =
1271                 rte_zmalloc("txq->push_buf_intermediate_buf",
1272                             txq->tx_max_header_size,
1273                             RTE_CACHE_LINE_SIZE);
1274         if (!txq->push_buf_intermediate_buf) {
1275                 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1276                 rte_free(txq->tx_buffer_info);
1277                 rte_free(txq->empty_tx_reqs);
1278                 return -ENOMEM;
1279         }
1280
1281         for (i = 0; i < txq->ring_size; i++)
1282                 txq->empty_tx_reqs[i] = i;
1283
1284         if (tx_conf != NULL) {
1285                 txq->offloads =
1286                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1287         }
1288         /* Store pointer to this queue in upper layer */
1289         txq->configured = 1;
1290         dev->data->tx_queues[queue_idx] = txq;
1291
1292         return 0;
1293 }
1294
1295 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1296                               uint16_t queue_idx,
1297                               uint16_t nb_desc,
1298                               unsigned int socket_id,
1299                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1300                               struct rte_mempool *mp)
1301 {
1302         struct ena_adapter *adapter = dev->data->dev_private;
1303         struct ena_ring *rxq = NULL;
1304         int i;
1305
1306         rxq = &adapter->rx_ring[queue_idx];
1307         if (rxq->configured) {
1308                 PMD_DRV_LOG(CRIT,
1309                         "API violation. Queue %d is already configured\n",
1310                         queue_idx);
1311                 return ENA_COM_FAULT;
1312         }
1313
1314         if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1315                 nb_desc = adapter->rx_ring_size;
1316
1317         if (!rte_is_power_of_2(nb_desc)) {
1318                 PMD_DRV_LOG(ERR,
1319                         "Unsupported size of RX queue: %d is not a power of 2.\n",
1320                         nb_desc);
1321                 return -EINVAL;
1322         }
1323
1324         if (nb_desc > adapter->rx_ring_size) {
1325                 PMD_DRV_LOG(ERR,
1326                         "Unsupported size of RX queue (max size: %d)\n",
1327                         adapter->rx_ring_size);
1328                 return -EINVAL;
1329         }
1330
1331         rxq->port_id = dev->data->port_id;
1332         rxq->next_to_clean = 0;
1333         rxq->next_to_use = 0;
1334         rxq->ring_size = nb_desc;
1335         rxq->numa_socket_id = socket_id;
1336         rxq->mb_pool = mp;
1337
1338         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1339                                           sizeof(struct rte_mbuf *) * nb_desc,
1340                                           RTE_CACHE_LINE_SIZE);
1341         if (!rxq->rx_buffer_info) {
1342                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1343                 return -ENOMEM;
1344         }
1345
1346         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1347                                             sizeof(struct rte_mbuf *) * nb_desc,
1348                                             RTE_CACHE_LINE_SIZE);
1349
1350         if (!rxq->rx_refill_buffer) {
1351                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1352                 rte_free(rxq->rx_buffer_info);
1353                 rxq->rx_buffer_info = NULL;
1354                 return -ENOMEM;
1355         }
1356
1357         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1358                                          sizeof(uint16_t) * nb_desc,
1359                                          RTE_CACHE_LINE_SIZE);
1360         if (!rxq->empty_rx_reqs) {
1361                 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1362                 rte_free(rxq->rx_buffer_info);
1363                 rxq->rx_buffer_info = NULL;
1364                 rte_free(rxq->rx_refill_buffer);
1365                 rxq->rx_refill_buffer = NULL;
1366                 return -ENOMEM;
1367         }
1368
1369         for (i = 0; i < nb_desc; i++)
1370                 rxq->empty_rx_reqs[i] = i;
1371
1372         /* Store pointer to this queue in upper layer */
1373         rxq->configured = 1;
1374         dev->data->rx_queues[queue_idx] = rxq;
1375
1376         return 0;
1377 }
1378
1379 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1380 {
1381         unsigned int i;
1382         int rc;
1383         uint16_t ring_size = rxq->ring_size;
1384         uint16_t ring_mask = ring_size - 1;
1385         uint16_t next_to_use = rxq->next_to_use;
1386         uint16_t in_use, req_id;
1387         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1388
1389         if (unlikely(!count))
1390                 return 0;
1391
1392         in_use = rxq->next_to_use - rxq->next_to_clean;
1393         ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n");
1394
1395         /* get resources for incoming packets */
1396         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1397         if (unlikely(rc < 0)) {
1398                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1399                 ++rxq->rx_stats.mbuf_alloc_fail;
1400                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1401                 return 0;
1402         }
1403
1404         for (i = 0; i < count; i++) {
1405                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1406                 struct rte_mbuf *mbuf = mbufs[i];
1407                 struct ena_com_buf ebuf;
1408
1409                 if (likely((i + 4) < count))
1410                         rte_prefetch0(mbufs[i + 4]);
1411
1412                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1413                 rc = validate_rx_req_id(rxq, req_id);
1414                 if (unlikely(rc < 0))
1415                         break;
1416                 rxq->rx_buffer_info[req_id] = mbuf;
1417
1418                 /* prepare physical address for DMA transaction */
1419                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1420                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1421                 /* pass resource to device */
1422                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1423                                                 &ebuf, req_id);
1424                 if (unlikely(rc)) {
1425                         PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1426                         rxq->rx_buffer_info[req_id] = NULL;
1427                         break;
1428                 }
1429                 next_to_use++;
1430         }
1431
1432         if (unlikely(i < count)) {
1433                 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1434                         "buffers (from %d)\n", rxq->id, i, count);
1435                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1436                                      count - i);
1437                 ++rxq->rx_stats.refill_partial;
1438         }
1439
1440         /* When we submitted free recources to device... */
1441         if (likely(i > 0)) {
1442                 /* ...let HW know that it can fill buffers with data
1443                  *
1444                  * Add memory barrier to make sure the desc were written before
1445                  * issue a doorbell
1446                  */
1447                 rte_wmb();
1448                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1449
1450                 rxq->next_to_use = next_to_use;
1451         }
1452
1453         return i;
1454 }
1455
1456 static int ena_device_init(struct ena_com_dev *ena_dev,
1457                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1458                            bool *wd_state)
1459 {
1460         uint32_t aenq_groups;
1461         int rc;
1462         bool readless_supported;
1463
1464         /* Initialize mmio registers */
1465         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1466         if (rc) {
1467                 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1468                 return rc;
1469         }
1470
1471         /* The PCIe configuration space revision id indicate if mmio reg
1472          * read is disabled.
1473          */
1474         readless_supported =
1475                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1476                                & ENA_MMIO_DISABLE_REG_READ);
1477         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1478
1479         /* reset device */
1480         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1481         if (rc) {
1482                 PMD_DRV_LOG(ERR, "cannot reset device\n");
1483                 goto err_mmio_read_less;
1484         }
1485
1486         /* check FW version */
1487         rc = ena_com_validate_version(ena_dev);
1488         if (rc) {
1489                 PMD_DRV_LOG(ERR, "device version is too low\n");
1490                 goto err_mmio_read_less;
1491         }
1492
1493         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1494
1495         /* ENA device administration layer init */
1496         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1497         if (rc) {
1498                 PMD_DRV_LOG(ERR,
1499                         "cannot initialize ena admin queue with device\n");
1500                 goto err_mmio_read_less;
1501         }
1502
1503         /* To enable the msix interrupts the driver needs to know the number
1504          * of queues. So the driver uses polling mode to retrieve this
1505          * information.
1506          */
1507         ena_com_set_admin_polling_mode(ena_dev, true);
1508
1509         ena_config_host_info(ena_dev);
1510
1511         /* Get Device Attributes and features */
1512         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1513         if (rc) {
1514                 PMD_DRV_LOG(ERR,
1515                         "cannot get attribute for ena device rc= %d\n", rc);
1516                 goto err_admin_init;
1517         }
1518
1519         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1520                       BIT(ENA_ADMIN_NOTIFICATION) |
1521                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1522                       BIT(ENA_ADMIN_FATAL_ERROR) |
1523                       BIT(ENA_ADMIN_WARNING);
1524
1525         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1526         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1527         if (rc) {
1528                 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1529                 goto err_admin_init;
1530         }
1531
1532         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1533
1534         return 0;
1535
1536 err_admin_init:
1537         ena_com_admin_destroy(ena_dev);
1538
1539 err_mmio_read_less:
1540         ena_com_mmio_reg_read_request_destroy(ena_dev);
1541
1542         return rc;
1543 }
1544
1545 static void ena_interrupt_handler_rte(void *cb_arg)
1546 {
1547         struct ena_adapter *adapter = cb_arg;
1548         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1549
1550         ena_com_admin_q_comp_intr_handler(ena_dev);
1551         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1552                 ena_com_aenq_intr_handler(ena_dev, adapter);
1553 }
1554
1555 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1556 {
1557         if (!adapter->wd_state)
1558                 return;
1559
1560         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1561                 return;
1562
1563         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1564             adapter->keep_alive_timeout)) {
1565                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1566                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1567                 adapter->trigger_reset = true;
1568                 ++adapter->dev_stats.wd_expired;
1569         }
1570 }
1571
1572 /* Check if admin queue is enabled */
1573 static void check_for_admin_com_state(struct ena_adapter *adapter)
1574 {
1575         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1576                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1577                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1578                 adapter->trigger_reset = true;
1579         }
1580 }
1581
1582 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1583                                   void *arg)
1584 {
1585         struct ena_adapter *adapter = arg;
1586         struct rte_eth_dev *dev = adapter->rte_dev;
1587
1588         check_for_missing_keep_alive(adapter);
1589         check_for_admin_com_state(adapter);
1590
1591         if (unlikely(adapter->trigger_reset)) {
1592                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1593                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1594                         NULL);
1595         }
1596 }
1597
1598 static inline void
1599 set_default_llq_configurations(struct ena_llq_configurations *llq_config)
1600 {
1601         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1602         llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1603         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1604         llq_config->llq_num_decs_before_header =
1605                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1606         llq_config->llq_ring_entry_size_value = 128;
1607 }
1608
1609 static int
1610 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1611                                 struct ena_com_dev *ena_dev,
1612                                 struct ena_admin_feature_llq_desc *llq,
1613                                 struct ena_llq_configurations *llq_default_configurations)
1614 {
1615         int rc;
1616         u32 llq_feature_mask;
1617
1618         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1619         if (!(ena_dev->supported_features & llq_feature_mask)) {
1620                 PMD_DRV_LOG(INFO,
1621                         "LLQ is not supported. Fallback to host mode policy.\n");
1622                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1623                 return 0;
1624         }
1625
1626         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1627         if (unlikely(rc)) {
1628                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1629                         "Fallback to host mode policy.");
1630                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1631                 return 0;
1632         }
1633
1634         /* Nothing to config, exit */
1635         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1636                 return 0;
1637
1638         if (!adapter->dev_mem_base) {
1639                 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1640                         "Fallback to host mode policy.\n.");
1641                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1642                 return 0;
1643         }
1644
1645         ena_dev->mem_bar = adapter->dev_mem_base;
1646
1647         return 0;
1648 }
1649
1650 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,
1651                                  struct ena_com_dev_get_features_ctx *get_feat_ctx)
1652 {
1653         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num;
1654
1655         /* Regular queues capabilities */
1656         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1657                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1658                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1659                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1660                                     max_queue_ext->max_rx_cq_num);
1661                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1662                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1663         } else {
1664                 struct ena_admin_queue_feature_desc *max_queues =
1665                         &get_feat_ctx->max_queues;
1666                 io_tx_sq_num = max_queues->max_sq_num;
1667                 io_tx_cq_num = max_queues->max_cq_num;
1668                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1669         }
1670
1671         /* In case of LLQ use the llq number in the get feature cmd */
1672         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1673                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1674
1675         io_queue_num = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1676         io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num);
1677         io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num);
1678
1679         if (unlikely(io_queue_num == 0)) {
1680                 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1681                 return -EFAULT;
1682         }
1683
1684         return io_queue_num;
1685 }
1686
1687 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1688 {
1689         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1690         struct rte_pci_device *pci_dev;
1691         struct rte_intr_handle *intr_handle;
1692         struct ena_adapter *adapter = eth_dev->data->dev_private;
1693         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1694         struct ena_com_dev_get_features_ctx get_feat_ctx;
1695         struct ena_llq_configurations llq_config;
1696         const char *queue_type_str;
1697         int rc;
1698
1699         static int adapters_found;
1700         bool wd_state;
1701
1702         eth_dev->dev_ops = &ena_dev_ops;
1703         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1704         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1705         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1706
1707         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1708                 return 0;
1709
1710         memset(adapter, 0, sizeof(struct ena_adapter));
1711         ena_dev = &adapter->ena_dev;
1712
1713         adapter->rte_eth_dev_data = eth_dev->data;
1714         adapter->rte_dev = eth_dev;
1715
1716         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1717         adapter->pdev = pci_dev;
1718
1719         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1720                      pci_dev->addr.domain,
1721                      pci_dev->addr.bus,
1722                      pci_dev->addr.devid,
1723                      pci_dev->addr.function);
1724
1725         intr_handle = &pci_dev->intr_handle;
1726
1727         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1728         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1729
1730         if (!adapter->regs) {
1731                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1732                              ENA_REGS_BAR);
1733                 return -ENXIO;
1734         }
1735
1736         ena_dev->reg_bar = adapter->regs;
1737         ena_dev->dmadev = adapter->pdev;
1738
1739         adapter->id_number = adapters_found;
1740
1741         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1742                  adapter->id_number);
1743
1744         /* device specific initialization routine */
1745         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1746         if (rc) {
1747                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1748                 goto err;
1749         }
1750         adapter->wd_state = wd_state;
1751
1752         set_default_llq_configurations(&llq_config);
1753         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1754                                              &get_feat_ctx.llq, &llq_config);
1755         if (unlikely(rc)) {
1756                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1757                 return rc;
1758         }
1759
1760         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1761                 queue_type_str = "Regular";
1762         else
1763                 queue_type_str = "Low latency";
1764         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1765
1766         calc_queue_ctx.ena_dev = ena_dev;
1767         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1768         adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1769                                                     &get_feat_ctx);
1770
1771         rc = ena_calc_queue_size(&calc_queue_ctx);
1772         if (unlikely((rc != 0) || (adapter->num_queues <= 0))) {
1773                 rc = -EFAULT;
1774                 goto err_device_destroy;
1775         }
1776
1777         adapter->tx_ring_size = calc_queue_ctx.tx_queue_size;
1778         adapter->rx_ring_size = calc_queue_ctx.rx_queue_size;
1779
1780         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1781         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1782
1783         /* prepare ring structures */
1784         ena_init_rings(adapter);
1785
1786         ena_config_debug_area(adapter);
1787
1788         /* Set max MTU for this device */
1789         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1790
1791         /* set device support for offloads */
1792         adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1793                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1794         adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1795                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1796         adapter->offloads.rx_csum_supported =
1797                 (get_feat_ctx.offload.rx_supported &
1798                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1799
1800         /* Copy MAC address and point DPDK to it */
1801         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1802         rte_ether_addr_copy((struct rte_ether_addr *)
1803                         get_feat_ctx.dev_attr.mac_addr,
1804                         (struct rte_ether_addr *)adapter->mac_addr);
1805
1806         /*
1807          * Pass the information to the rte_eth_dev_close() that it should also
1808          * release the private port resources.
1809          */
1810         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1811
1812         adapter->drv_stats = rte_zmalloc("adapter stats",
1813                                          sizeof(*adapter->drv_stats),
1814                                          RTE_CACHE_LINE_SIZE);
1815         if (!adapter->drv_stats) {
1816                 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1817                 rc = -ENOMEM;
1818                 goto err_delete_debug_area;
1819         }
1820
1821         rte_intr_callback_register(intr_handle,
1822                                    ena_interrupt_handler_rte,
1823                                    adapter);
1824         rte_intr_enable(intr_handle);
1825         ena_com_set_admin_polling_mode(ena_dev, false);
1826         ena_com_admin_aenq_enable(ena_dev);
1827
1828         if (adapters_found == 0)
1829                 rte_timer_subsystem_init();
1830         rte_timer_init(&adapter->timer_wd);
1831
1832         adapters_found++;
1833         adapter->state = ENA_ADAPTER_STATE_INIT;
1834
1835         return 0;
1836
1837 err_delete_debug_area:
1838         ena_com_delete_debug_area(ena_dev);
1839
1840 err_device_destroy:
1841         ena_com_delete_host_info(ena_dev);
1842         ena_com_admin_destroy(ena_dev);
1843
1844 err:
1845         return rc;
1846 }
1847
1848 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1849 {
1850         struct ena_adapter *adapter = eth_dev->data->dev_private;
1851         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1852
1853         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1854                 return;
1855
1856         ena_com_set_admin_running_state(ena_dev, false);
1857
1858         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1859                 ena_close(eth_dev);
1860
1861         ena_com_delete_debug_area(ena_dev);
1862         ena_com_delete_host_info(ena_dev);
1863
1864         ena_com_abort_admin_commands(ena_dev);
1865         ena_com_wait_for_abort_completion(ena_dev);
1866         ena_com_admin_destroy(ena_dev);
1867         ena_com_mmio_reg_read_request_destroy(ena_dev);
1868
1869         adapter->state = ENA_ADAPTER_STATE_FREE;
1870 }
1871
1872 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1873 {
1874         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1875                 return 0;
1876
1877         ena_destroy_device(eth_dev);
1878
1879         eth_dev->dev_ops = NULL;
1880         eth_dev->rx_pkt_burst = NULL;
1881         eth_dev->tx_pkt_burst = NULL;
1882         eth_dev->tx_pkt_prepare = NULL;
1883
1884         return 0;
1885 }
1886
1887 static int ena_dev_configure(struct rte_eth_dev *dev)
1888 {
1889         struct ena_adapter *adapter = dev->data->dev_private;
1890
1891         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1892
1893         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1894         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1895         return 0;
1896 }
1897
1898 static void ena_init_rings(struct ena_adapter *adapter)
1899 {
1900         int i;
1901
1902         for (i = 0; i < adapter->num_queues; i++) {
1903                 struct ena_ring *ring = &adapter->tx_ring[i];
1904
1905                 ring->configured = 0;
1906                 ring->type = ENA_RING_TYPE_TX;
1907                 ring->adapter = adapter;
1908                 ring->id = i;
1909                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1910                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1911                 ring->sgl_size = adapter->max_tx_sgl_size;
1912         }
1913
1914         for (i = 0; i < adapter->num_queues; i++) {
1915                 struct ena_ring *ring = &adapter->rx_ring[i];
1916
1917                 ring->configured = 0;
1918                 ring->type = ENA_RING_TYPE_RX;
1919                 ring->adapter = adapter;
1920                 ring->id = i;
1921                 ring->sgl_size = adapter->max_rx_sgl_size;
1922         }
1923 }
1924
1925 static int ena_infos_get(struct rte_eth_dev *dev,
1926                           struct rte_eth_dev_info *dev_info)
1927 {
1928         struct ena_adapter *adapter;
1929         struct ena_com_dev *ena_dev;
1930         uint64_t rx_feat = 0, tx_feat = 0;
1931
1932         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1933         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1934         adapter = dev->data->dev_private;
1935
1936         ena_dev = &adapter->ena_dev;
1937         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1938
1939         dev_info->speed_capa =
1940                         ETH_LINK_SPEED_1G   |
1941                         ETH_LINK_SPEED_2_5G |
1942                         ETH_LINK_SPEED_5G   |
1943                         ETH_LINK_SPEED_10G  |
1944                         ETH_LINK_SPEED_25G  |
1945                         ETH_LINK_SPEED_40G  |
1946                         ETH_LINK_SPEED_50G  |
1947                         ETH_LINK_SPEED_100G;
1948
1949         /* Set Tx & Rx features available for device */
1950         if (adapter->offloads.tso4_supported)
1951                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1952
1953         if (adapter->offloads.tx_csum_supported)
1954                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1955                         DEV_TX_OFFLOAD_UDP_CKSUM |
1956                         DEV_TX_OFFLOAD_TCP_CKSUM;
1957
1958         if (adapter->offloads.rx_csum_supported)
1959                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1960                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1961                         DEV_RX_OFFLOAD_TCP_CKSUM;
1962
1963         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1964
1965         /* Inform framework about available features */
1966         dev_info->rx_offload_capa = rx_feat;
1967         dev_info->rx_queue_offload_capa = rx_feat;
1968         dev_info->tx_offload_capa = tx_feat;
1969         dev_info->tx_queue_offload_capa = tx_feat;
1970
1971         dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
1972                                            ETH_RSS_UDP;
1973
1974         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1975         dev_info->max_rx_pktlen  = adapter->max_mtu;
1976         dev_info->max_mac_addrs = 1;
1977
1978         dev_info->max_rx_queues = adapter->num_queues;
1979         dev_info->max_tx_queues = adapter->num_queues;
1980         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1981
1982         adapter->tx_supported_offloads = tx_feat;
1983         adapter->rx_supported_offloads = rx_feat;
1984
1985         dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size;
1986         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1987         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1988                                         adapter->max_rx_sgl_size);
1989         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1990                                         adapter->max_rx_sgl_size);
1991
1992         dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size;
1993         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1994         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1995                                         adapter->max_tx_sgl_size);
1996         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1997                                         adapter->max_tx_sgl_size);
1998
1999         return 0;
2000 }
2001
2002 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2003                                   uint16_t nb_pkts)
2004 {
2005         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2006         unsigned int ring_size = rx_ring->ring_size;
2007         unsigned int ring_mask = ring_size - 1;
2008         uint16_t next_to_clean = rx_ring->next_to_clean;
2009         uint16_t desc_in_use = 0;
2010         uint16_t req_id;
2011         unsigned int recv_idx = 0;
2012         struct rte_mbuf *mbuf = NULL;
2013         struct rte_mbuf *mbuf_head = NULL;
2014         struct rte_mbuf *mbuf_prev = NULL;
2015         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
2016         unsigned int completed;
2017
2018         struct ena_com_rx_ctx ena_rx_ctx;
2019         int rc = 0;
2020
2021         /* Check adapter state */
2022         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2023                 PMD_DRV_LOG(ALERT,
2024                         "Trying to receive pkts while device is NOT running\n");
2025                 return 0;
2026         }
2027
2028         desc_in_use = rx_ring->next_to_use - next_to_clean;
2029         if (unlikely(nb_pkts > desc_in_use))
2030                 nb_pkts = desc_in_use;
2031
2032         for (completed = 0; completed < nb_pkts; completed++) {
2033                 int segments = 0;
2034
2035                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2036                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2037                 ena_rx_ctx.descs = 0;
2038                 /* receive packet context */
2039                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2040                                     rx_ring->ena_com_io_sq,
2041                                     &ena_rx_ctx);
2042                 if (unlikely(rc)) {
2043                         PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2044                         rx_ring->adapter->reset_reason =
2045                                 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2046                         rx_ring->adapter->trigger_reset = true;
2047                         ++rx_ring->rx_stats.bad_desc_num;
2048                         return 0;
2049                 }
2050
2051                 if (unlikely(ena_rx_ctx.descs == 0))
2052                         break;
2053
2054                 while (segments < ena_rx_ctx.descs) {
2055                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
2056                         rc = validate_rx_req_id(rx_ring, req_id);
2057                         if (unlikely(rc)) {
2058                                 if (segments != 0)
2059                                         rte_mbuf_raw_free(mbuf_head);
2060                                 break;
2061                         }
2062
2063                         mbuf = rx_buff_info[req_id];
2064                         rx_buff_info[req_id] = NULL;
2065                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
2066                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2067                         mbuf->refcnt = 1;
2068                         mbuf->next = NULL;
2069                         if (unlikely(segments == 0)) {
2070                                 mbuf->nb_segs = ena_rx_ctx.descs;
2071                                 mbuf->port = rx_ring->port_id;
2072                                 mbuf->pkt_len = 0;
2073                                 mbuf_head = mbuf;
2074                         } else {
2075                                 /* for multi-segment pkts create mbuf chain */
2076                                 mbuf_prev->next = mbuf;
2077                         }
2078                         mbuf_head->pkt_len += mbuf->data_len;
2079
2080                         mbuf_prev = mbuf;
2081                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
2082                                 req_id;
2083                         segments++;
2084                         next_to_clean++;
2085                 }
2086                 if (unlikely(rc))
2087                         break;
2088
2089                 /* fill mbuf attributes if any */
2090                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
2091
2092                 if (unlikely(mbuf_head->ol_flags &
2093                                 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2094                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2095                         ++rx_ring->rx_stats.bad_csum;
2096                 }
2097
2098                 mbuf_head->hash.rss = ena_rx_ctx.hash;
2099
2100                 /* pass to DPDK application head mbuf */
2101                 rx_pkts[recv_idx] = mbuf_head;
2102                 recv_idx++;
2103                 rx_ring->rx_stats.bytes += mbuf_head->pkt_len;
2104         }
2105
2106         rx_ring->rx_stats.cnt += recv_idx;
2107         rx_ring->next_to_clean = next_to_clean;
2108
2109         desc_in_use = desc_in_use - completed + 1;
2110         /* Burst refill to save doorbells, memory barriers, const interval */
2111         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size)) {
2112                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2113                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
2114         }
2115
2116         return recv_idx;
2117 }
2118
2119 static uint16_t
2120 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2121                 uint16_t nb_pkts)
2122 {
2123         int32_t ret;
2124         uint32_t i;
2125         struct rte_mbuf *m;
2126         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2127         struct rte_ipv4_hdr *ip_hdr;
2128         uint64_t ol_flags;
2129         uint16_t frag_field;
2130
2131         for (i = 0; i != nb_pkts; i++) {
2132                 m = tx_pkts[i];
2133                 ol_flags = m->ol_flags;
2134
2135                 if (!(ol_flags & PKT_TX_IPV4))
2136                         continue;
2137
2138                 /* If there was not L2 header length specified, assume it is
2139                  * length of the ethernet header.
2140                  */
2141                 if (unlikely(m->l2_len == 0))
2142                         m->l2_len = sizeof(struct rte_ether_hdr);
2143
2144                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2145                                                  m->l2_len);
2146                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2147
2148                 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2149                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2150
2151                         /* If IPv4 header has DF flag enabled and TSO support is
2152                          * disabled, partial chcecksum should not be calculated.
2153                          */
2154                         if (!tx_ring->adapter->offloads.tso4_supported)
2155                                 continue;
2156                 }
2157
2158                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2159                                 (ol_flags & PKT_TX_L4_MASK) ==
2160                                 PKT_TX_SCTP_CKSUM) {
2161                         rte_errno = ENOTSUP;
2162                         return i;
2163                 }
2164
2165 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2166                 ret = rte_validate_tx_offload(m);
2167                 if (ret != 0) {
2168                         rte_errno = -ret;
2169                         return i;
2170                 }
2171 #endif
2172
2173                 /* In case we are supposed to TSO and have DF not set (DF=0)
2174                  * hardware must be provided with partial checksum, otherwise
2175                  * it will take care of necessary calculations.
2176                  */
2177
2178                 ret = rte_net_intel_cksum_flags_prepare(m,
2179                         ol_flags & ~PKT_TX_TCP_SEG);
2180                 if (ret != 0) {
2181                         rte_errno = -ret;
2182                         return i;
2183                 }
2184         }
2185
2186         return i;
2187 }
2188
2189 static void ena_update_hints(struct ena_adapter *adapter,
2190                              struct ena_admin_ena_hw_hints *hints)
2191 {
2192         if (hints->admin_completion_tx_timeout)
2193                 adapter->ena_dev.admin_queue.completion_timeout =
2194                         hints->admin_completion_tx_timeout * 1000;
2195
2196         if (hints->mmio_read_timeout)
2197                 /* convert to usec */
2198                 adapter->ena_dev.mmio_read.reg_read_to =
2199                         hints->mmio_read_timeout * 1000;
2200
2201         if (hints->driver_watchdog_timeout) {
2202                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2203                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2204                 else
2205                         // Convert msecs to ticks
2206                         adapter->keep_alive_timeout =
2207                                 (hints->driver_watchdog_timeout *
2208                                 rte_get_timer_hz()) / 1000;
2209         }
2210 }
2211
2212 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2213                                         struct rte_mbuf *mbuf)
2214 {
2215         struct ena_com_dev *ena_dev;
2216         int num_segments, header_len, rc;
2217
2218         ena_dev = &tx_ring->adapter->ena_dev;
2219         num_segments = mbuf->nb_segs;
2220         header_len = mbuf->data_len;
2221
2222         if (likely(num_segments < tx_ring->sgl_size))
2223                 return 0;
2224
2225         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2226             (num_segments == tx_ring->sgl_size) &&
2227             (header_len < tx_ring->tx_max_header_size))
2228                 return 0;
2229
2230         ++tx_ring->tx_stats.linearize;
2231         rc = rte_pktmbuf_linearize(mbuf);
2232         if (unlikely(rc)) {
2233                 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2234                 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2235                 ++tx_ring->tx_stats.linearize_failed;
2236                 return rc;
2237         }
2238
2239         return rc;
2240 }
2241
2242 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2243                                   uint16_t nb_pkts)
2244 {
2245         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2246         uint16_t next_to_use = tx_ring->next_to_use;
2247         uint16_t next_to_clean = tx_ring->next_to_clean;
2248         struct rte_mbuf *mbuf;
2249         uint16_t seg_len;
2250         unsigned int ring_size = tx_ring->ring_size;
2251         unsigned int ring_mask = ring_size - 1;
2252         struct ena_com_tx_ctx ena_tx_ctx;
2253         struct ena_tx_buffer *tx_info;
2254         struct ena_com_buf *ebuf;
2255         uint16_t rc, req_id, total_tx_descs = 0;
2256         uint16_t sent_idx = 0, empty_tx_reqs;
2257         uint16_t push_len = 0;
2258         uint16_t delta = 0;
2259         int nb_hw_desc;
2260         uint32_t total_length;
2261
2262         /* Check adapter state */
2263         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2264                 PMD_DRV_LOG(ALERT,
2265                         "Trying to xmit pkts while device is NOT running\n");
2266                 return 0;
2267         }
2268
2269         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2270         if (nb_pkts > empty_tx_reqs)
2271                 nb_pkts = empty_tx_reqs;
2272
2273         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2274                 mbuf = tx_pkts[sent_idx];
2275                 total_length = 0;
2276
2277                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2278                 if (unlikely(rc))
2279                         break;
2280
2281                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2282                 tx_info = &tx_ring->tx_buffer_info[req_id];
2283                 tx_info->mbuf = mbuf;
2284                 tx_info->num_of_bufs = 0;
2285                 ebuf = tx_info->bufs;
2286
2287                 /* Prepare TX context */
2288                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2289                 memset(&ena_tx_ctx.ena_meta, 0x0,
2290                        sizeof(struct ena_com_tx_meta));
2291                 ena_tx_ctx.ena_bufs = ebuf;
2292                 ena_tx_ctx.req_id = req_id;
2293
2294                 delta = 0;
2295                 seg_len = mbuf->data_len;
2296
2297                 if (tx_ring->tx_mem_queue_type ==
2298                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2299                         push_len = RTE_MIN(mbuf->pkt_len,
2300                                            tx_ring->tx_max_header_size);
2301                         ena_tx_ctx.header_len = push_len;
2302
2303                         if (likely(push_len <= seg_len)) {
2304                                 /* If the push header is in the single segment,
2305                                  * then just point it to the 1st mbuf data.
2306                                  */
2307                                 ena_tx_ctx.push_header =
2308                                         rte_pktmbuf_mtod(mbuf, uint8_t *);
2309                         } else {
2310                                 /* If the push header lays in the several
2311                                  * segments, copy it to the intermediate buffer.
2312                                  */
2313                                 rte_pktmbuf_read(mbuf, 0, push_len,
2314                                         tx_ring->push_buf_intermediate_buf);
2315                                 ena_tx_ctx.push_header =
2316                                         tx_ring->push_buf_intermediate_buf;
2317                                 delta = push_len - seg_len;
2318                         }
2319                 } /* there's no else as we take advantage of memset zeroing */
2320
2321                 /* Set TX offloads flags, if applicable */
2322                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2323
2324                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2325
2326                 /* Process first segment taking into
2327                  * consideration pushed header
2328                  */
2329                 if (seg_len > push_len) {
2330                         ebuf->paddr = mbuf->buf_iova +
2331                                       mbuf->data_off +
2332                                       push_len;
2333                         ebuf->len = seg_len - push_len;
2334                         ebuf++;
2335                         tx_info->num_of_bufs++;
2336                 }
2337                 total_length += mbuf->data_len;
2338
2339                 while ((mbuf = mbuf->next) != NULL) {
2340                         seg_len = mbuf->data_len;
2341
2342                         /* Skip mbufs if whole data is pushed as a header */
2343                         if (unlikely(delta > seg_len)) {
2344                                 delta -= seg_len;
2345                                 continue;
2346                         }
2347
2348                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2349                         ebuf->len = seg_len - delta;
2350                         total_length += ebuf->len;
2351                         ebuf++;
2352                         tx_info->num_of_bufs++;
2353
2354                         delta = 0;
2355                 }
2356
2357                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2358
2359                 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2360                                                &ena_tx_ctx)) {
2361                         PMD_DRV_LOG(DEBUG, "llq tx max burst size of queue %d"
2362                                 " achieved, writing doorbell to send burst\n",
2363                                 tx_ring->id);
2364                         rte_wmb();
2365                         ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2366                 }
2367
2368                 /* prepare the packet's descriptors to dma engine */
2369                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2370                                         &ena_tx_ctx, &nb_hw_desc);
2371                 if (unlikely(rc)) {
2372                         ++tx_ring->tx_stats.prepare_ctx_err;
2373                         break;
2374                 }
2375                 tx_info->tx_descs = nb_hw_desc;
2376
2377                 next_to_use++;
2378                 tx_ring->tx_stats.cnt++;
2379                 tx_ring->tx_stats.bytes += total_length;
2380         }
2381         tx_ring->tx_stats.available_desc =
2382                 ena_com_free_desc(tx_ring->ena_com_io_sq);
2383
2384         /* If there are ready packets to be xmitted... */
2385         if (sent_idx > 0) {
2386                 /* ...let HW do its best :-) */
2387                 rte_wmb();
2388                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2389                 tx_ring->tx_stats.doorbells++;
2390                 tx_ring->next_to_use = next_to_use;
2391         }
2392
2393         /* Clear complete packets  */
2394         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2395                 rc = validate_tx_req_id(tx_ring, req_id);
2396                 if (rc)
2397                         break;
2398
2399                 /* Get Tx info & store how many descs were processed  */
2400                 tx_info = &tx_ring->tx_buffer_info[req_id];
2401                 total_tx_descs += tx_info->tx_descs;
2402
2403                 /* Free whole mbuf chain  */
2404                 mbuf = tx_info->mbuf;
2405                 rte_pktmbuf_free(mbuf);
2406                 tx_info->mbuf = NULL;
2407
2408                 /* Put back descriptor to the ring for reuse */
2409                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2410                 next_to_clean++;
2411
2412                 /* If too many descs to clean, leave it for another run */
2413                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2414                         break;
2415         }
2416         tx_ring->tx_stats.available_desc =
2417                 ena_com_free_desc(tx_ring->ena_com_io_sq);
2418
2419         if (total_tx_descs > 0) {
2420                 /* acknowledge completion of sent packets */
2421                 tx_ring->next_to_clean = next_to_clean;
2422                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2423                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2424         }
2425
2426         tx_ring->tx_stats.tx_poll++;
2427
2428         return sent_idx;
2429 }
2430
2431 /**
2432  * DPDK callback to retrieve names of extended device statistics
2433  *
2434  * @param dev
2435  *   Pointer to Ethernet device structure.
2436  * @param[out] xstats_names
2437  *   Buffer to insert names into.
2438  * @param n
2439  *   Number of names.
2440  *
2441  * @return
2442  *   Number of xstats names.
2443  */
2444 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2445                                 struct rte_eth_xstat_name *xstats_names,
2446                                 unsigned int n)
2447 {
2448         unsigned int xstats_count = ena_xstats_calc_num(dev);
2449         unsigned int stat, i, count = 0;
2450
2451         if (n < xstats_count || !xstats_names)
2452                 return xstats_count;
2453
2454         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2455                 strcpy(xstats_names[count].name,
2456                         ena_stats_global_strings[stat].name);
2457
2458         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2459                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2460                         snprintf(xstats_names[count].name,
2461                                 sizeof(xstats_names[count].name),
2462                                 "rx_q%d_%s", i,
2463                                 ena_stats_rx_strings[stat].name);
2464
2465         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2466                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2467                         snprintf(xstats_names[count].name,
2468                                 sizeof(xstats_names[count].name),
2469                                 "tx_q%d_%s", i,
2470                                 ena_stats_tx_strings[stat].name);
2471
2472         return xstats_count;
2473 }
2474
2475 /**
2476  * DPDK callback to get extended device statistics.
2477  *
2478  * @param dev
2479  *   Pointer to Ethernet device structure.
2480  * @param[out] stats
2481  *   Stats table output buffer.
2482  * @param n
2483  *   The size of the stats table.
2484  *
2485  * @return
2486  *   Number of xstats on success, negative on failure.
2487  */
2488 static int ena_xstats_get(struct rte_eth_dev *dev,
2489                           struct rte_eth_xstat *xstats,
2490                           unsigned int n)
2491 {
2492         struct ena_adapter *adapter = dev->data->dev_private;
2493         unsigned int xstats_count = ena_xstats_calc_num(dev);
2494         unsigned int stat, i, count = 0;
2495         int stat_offset;
2496         void *stats_begin;
2497
2498         if (n < xstats_count)
2499                 return xstats_count;
2500
2501         if (!xstats)
2502                 return 0;
2503
2504         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2505                 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2506                 stats_begin = &adapter->dev_stats;
2507
2508                 xstats[count].id = count;
2509                 xstats[count].value = *((uint64_t *)
2510                         ((char *)stats_begin + stat_offset));
2511         }
2512
2513         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2514                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2515                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2516                         stats_begin = &adapter->rx_ring[i].rx_stats;
2517
2518                         xstats[count].id = count;
2519                         xstats[count].value = *((uint64_t *)
2520                                 ((char *)stats_begin + stat_offset));
2521                 }
2522         }
2523
2524         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2525                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2526                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2527                         stats_begin = &adapter->tx_ring[i].rx_stats;
2528
2529                         xstats[count].id = count;
2530                         xstats[count].value = *((uint64_t *)
2531                                 ((char *)stats_begin + stat_offset));
2532                 }
2533         }
2534
2535         return count;
2536 }
2537
2538 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2539                                 const uint64_t *ids,
2540                                 uint64_t *values,
2541                                 unsigned int n)
2542 {
2543         struct ena_adapter *adapter = dev->data->dev_private;
2544         uint64_t id;
2545         uint64_t rx_entries, tx_entries;
2546         unsigned int i;
2547         int qid;
2548         int valid = 0;
2549         for (i = 0; i < n; ++i) {
2550                 id = ids[i];
2551                 /* Check if id belongs to global statistics */
2552                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2553                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2554                         ++valid;
2555                         continue;
2556                 }
2557
2558                 /* Check if id belongs to rx queue statistics */
2559                 id -= ENA_STATS_ARRAY_GLOBAL;
2560                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2561                 if (id < rx_entries) {
2562                         qid = id % dev->data->nb_rx_queues;
2563                         id /= dev->data->nb_rx_queues;
2564                         values[i] = *((uint64_t *)
2565                                 &adapter->rx_ring[qid].rx_stats + id);
2566                         ++valid;
2567                         continue;
2568                 }
2569                                 /* Check if id belongs to rx queue statistics */
2570                 id -= rx_entries;
2571                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2572                 if (id < tx_entries) {
2573                         qid = id % dev->data->nb_tx_queues;
2574                         id /= dev->data->nb_tx_queues;
2575                         values[i] = *((uint64_t *)
2576                                 &adapter->tx_ring[qid].tx_stats + id);
2577                         ++valid;
2578                         continue;
2579                 }
2580         }
2581
2582         return valid;
2583 }
2584
2585 /*********************************************************************
2586  *  PMD configuration
2587  *********************************************************************/
2588 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2589         struct rte_pci_device *pci_dev)
2590 {
2591         return rte_eth_dev_pci_generic_probe(pci_dev,
2592                 sizeof(struct ena_adapter), eth_ena_dev_init);
2593 }
2594
2595 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2596 {
2597         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2598 }
2599
2600 static struct rte_pci_driver rte_ena_pmd = {
2601         .id_table = pci_id_ena_map,
2602         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2603                      RTE_PCI_DRV_WC_ACTIVATE,
2604         .probe = eth_ena_pci_probe,
2605         .remove = eth_ena_pci_remove,
2606 };
2607
2608 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2609 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2610 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2611
2612 RTE_INIT(ena_init_log)
2613 {
2614         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2615         if (ena_logtype_init >= 0)
2616                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2617         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2618         if (ena_logtype_driver >= 0)
2619                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2620
2621 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2622         ena_logtype_rx = rte_log_register("pmd.net.ena.rx");
2623         if (ena_logtype_rx >= 0)
2624                 rte_log_set_level(ena_logtype_rx, RTE_LOG_NOTICE);
2625 #endif
2626
2627 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2628         ena_logtype_tx = rte_log_register("pmd.net.ena.tx");
2629         if (ena_logtype_tx >= 0)
2630                 rte_log_set_level(ena_logtype_tx, RTE_LOG_NOTICE);
2631 #endif
2632
2633 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2634         ena_logtype_tx_free = rte_log_register("pmd.net.ena.tx_free");
2635         if (ena_logtype_tx_free >= 0)
2636                 rte_log_set_level(ena_logtype_tx_free, RTE_LOG_NOTICE);
2637 #endif
2638
2639 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2640         ena_logtype_com = rte_log_register("pmd.net.ena.com");
2641         if (ena_logtype_com >= 0)
2642                 rte_log_set_level(ena_logtype_com, RTE_LOG_NOTICE);
2643 #endif
2644 }
2645
2646 /******************************************************************************
2647  ******************************** AENQ Handlers *******************************
2648  *****************************************************************************/
2649 static void ena_update_on_link_change(void *adapter_data,
2650                                       struct ena_admin_aenq_entry *aenq_e)
2651 {
2652         struct rte_eth_dev *eth_dev;
2653         struct ena_adapter *adapter;
2654         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2655         uint32_t status;
2656
2657         adapter = adapter_data;
2658         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2659         eth_dev = adapter->rte_dev;
2660
2661         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2662         adapter->link_status = status;
2663
2664         ena_link_update(eth_dev, 0);
2665         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2666 }
2667
2668 static void ena_notification(void *data,
2669                              struct ena_admin_aenq_entry *aenq_e)
2670 {
2671         struct ena_adapter *adapter = data;
2672         struct ena_admin_ena_hw_hints *hints;
2673
2674         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2675                 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2676                         aenq_e->aenq_common_desc.group,
2677                         ENA_ADMIN_NOTIFICATION);
2678
2679         switch (aenq_e->aenq_common_desc.syndrom) {
2680         case ENA_ADMIN_UPDATE_HINTS:
2681                 hints = (struct ena_admin_ena_hw_hints *)
2682                         (&aenq_e->inline_data_w4);
2683                 ena_update_hints(adapter, hints);
2684                 break;
2685         default:
2686                 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2687                         aenq_e->aenq_common_desc.syndrom);
2688         }
2689 }
2690
2691 static void ena_keep_alive(void *adapter_data,
2692                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2693 {
2694         struct ena_adapter *adapter = adapter_data;
2695         struct ena_admin_aenq_keep_alive_desc *desc;
2696         uint64_t rx_drops;
2697
2698         adapter->timestamp_wd = rte_get_timer_cycles();
2699
2700         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2701         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2702         rte_atomic64_set(&adapter->drv_stats->rx_drops, rx_drops);
2703 }
2704
2705 /**
2706  * This handler will called for unknown event group or unimplemented handlers
2707  **/
2708 static void unimplemented_aenq_handler(__rte_unused void *data,
2709                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2710 {
2711         PMD_DRV_LOG(ERR, "Unknown event was received or event with "
2712                           "unimplemented handler\n");
2713 }
2714
2715 static struct ena_aenq_handlers aenq_handlers = {
2716         .handlers = {
2717                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2718                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2719                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2720         },
2721         .unimplemented_handler = unimplemented_aenq_handler
2722 };