drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 1
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 #define ENA_MIN_RING_DESC       128
  89
  90 enum ethtool_stringset {
  91         ETH_SS_TEST             = 0,
  92         ETH_SS_STATS,
  93 };
  94
  95 struct ena_stats {
  96         char name[ETH_GSTRING_LEN];
  97         int stat_offset;
  98 };
  99
 100 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
 101         .name = #stat, \
 102         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 103 }
 104
 105 #define ENA_STAT_ENTRY(stat, stat_type) { \
 106         .name = #stat, \
 107         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 108 }
 109
 110 #define ENA_STAT_RX_ENTRY(stat) \
 111         ENA_STAT_ENTRY(stat, rx)
 112
 113 #define ENA_STAT_TX_ENTRY(stat) \
 114         ENA_STAT_ENTRY(stat, tx)
 115
 116 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 117         ENA_STAT_ENTRY(stat, dev)
 118
 119 #define ENA_MAX_RING_SIZE_RX 8192
 120 #define ENA_MAX_RING_SIZE_TX 1024
 121
 122 /*
 123  * Each rte_memzone should have unique name.
 124  * To satisfy it, count number of allocation and add it to name.
 125  */
 126 uint32_t ena_alloc_cnt;
 127
 128 static const struct ena_stats ena_stats_global_strings[] = {
 129         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 130         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 131         ENA_STAT_GLOBAL_ENTRY(io_resume),
 132         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 133         ENA_STAT_GLOBAL_ENTRY(interface_up),
 134         ENA_STAT_GLOBAL_ENTRY(interface_down),
 135         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 136 };
 137
 138 static const struct ena_stats ena_stats_tx_strings[] = {
 139         ENA_STAT_TX_ENTRY(cnt),
 140         ENA_STAT_TX_ENTRY(bytes),
 141         ENA_STAT_TX_ENTRY(queue_stop),
 142         ENA_STAT_TX_ENTRY(queue_wakeup),
 143         ENA_STAT_TX_ENTRY(dma_mapping_err),
 144         ENA_STAT_TX_ENTRY(linearize),
 145         ENA_STAT_TX_ENTRY(linearize_failed),
 146         ENA_STAT_TX_ENTRY(tx_poll),
 147         ENA_STAT_TX_ENTRY(doorbells),
 148         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 149         ENA_STAT_TX_ENTRY(missing_tx_comp),
 150         ENA_STAT_TX_ENTRY(bad_req_id),
 151 };
 152
 153 static const struct ena_stats ena_stats_rx_strings[] = {
 154         ENA_STAT_RX_ENTRY(cnt),
 155         ENA_STAT_RX_ENTRY(bytes),
 156         ENA_STAT_RX_ENTRY(refil_partial),
 157         ENA_STAT_RX_ENTRY(bad_csum),
 158         ENA_STAT_RX_ENTRY(page_alloc_fail),
 159         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 160         ENA_STAT_RX_ENTRY(dma_mapping_err),
 161         ENA_STAT_RX_ENTRY(bad_desc_num),
 162         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 163 };
 164
 165 static const struct ena_stats ena_stats_ena_com_strings[] = {
 166         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 167         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 168         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 169         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 170         ENA_STAT_ENA_COM_ENTRY(no_completion),
 171 };
 172
 173 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 174 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 175 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 176 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 177
 178 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 179                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 180                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 181                         DEV_TX_OFFLOAD_TCP_TSO)
 182 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 183                        PKT_TX_IP_CKSUM |\
 184                        PKT_TX_TCP_SEG)
 185
 186 /** Vendor ID used by Amazon devices */
 187 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 188 /** Amazon devices */
 189 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 190 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 191
 192 #define ENA_TX_OFFLOAD_MASK     (\
 193         PKT_TX_L4_MASK |         \
 194         PKT_TX_IPV6 |            \
 195         PKT_TX_IPV4 |            \
 196         PKT_TX_IP_CKSUM |        \
 197         PKT_TX_TCP_SEG)
 198
 199 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 200         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 201
 202 int ena_logtype_init;
 203 int ena_logtype_driver;
 204
 205 static const struct rte_pci_id pci_id_ena_map[] = {
 206         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 207         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 208         { .device_id = 0 },
 209 };
 210
 211 static struct ena_aenq_handlers aenq_handlers;
 212
 213 static int ena_device_init(struct ena_com_dev *ena_dev,
 214                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 215                            bool *wd_state);
 216 static int ena_dev_configure(struct rte_eth_dev *dev);
 217 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 218                                   uint16_t nb_pkts);
 219 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 220                 uint16_t nb_pkts);
 221 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 222                               uint16_t nb_desc, unsigned int socket_id,
 223                               const struct rte_eth_txconf *tx_conf);
 224 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 225                               uint16_t nb_desc, unsigned int socket_id,
 226                               const struct rte_eth_rxconf *rx_conf,
 227                               struct rte_mempool *mp);
 228 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 229                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 230 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 231 static void ena_init_rings(struct ena_adapter *adapter);
 232 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 233 static int ena_start(struct rte_eth_dev *dev);
 234 static void ena_stop(struct rte_eth_dev *dev);
 235 static void ena_close(struct rte_eth_dev *dev);
 236 static int ena_dev_reset(struct rte_eth_dev *dev);
 237 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 238 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 239 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 240 static void ena_rx_queue_release(void *queue);
 241 static void ena_tx_queue_release(void *queue);
 242 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 243 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 244 static int ena_link_update(struct rte_eth_dev *dev,
 245                            int wait_to_complete);
 246 static int ena_create_io_queue(struct ena_ring *ring);
 247 static void ena_queue_stop(struct ena_ring *ring);
 248 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 249                               enum ena_ring_type ring_type);
 250 static int ena_queue_start(struct ena_ring *ring);
 251 static int ena_queue_start_all(struct rte_eth_dev *dev,
 252                                enum ena_ring_type ring_type);
 253 static void ena_stats_restart(struct rte_eth_dev *dev);
 254 static void ena_infos_get(struct rte_eth_dev *dev,
 255                           struct rte_eth_dev_info *dev_info);
 256 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 257                                struct rte_eth_rss_reta_entry64 *reta_conf,
 258                                uint16_t reta_size);
 259 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 260                               struct rte_eth_rss_reta_entry64 *reta_conf,
 261                               uint16_t reta_size);
 262 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 263 static void ena_interrupt_handler_rte(void *cb_arg);
 264 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 265 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 266 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 267
 268 static const struct eth_dev_ops ena_dev_ops = {
 269         .dev_configure        = ena_dev_configure,
 270         .dev_infos_get        = ena_infos_get,
 271         .rx_queue_setup       = ena_rx_queue_setup,
 272         .tx_queue_setup       = ena_tx_queue_setup,
 273         .dev_start            = ena_start,
 274         .dev_stop             = ena_stop,
 275         .link_update          = ena_link_update,
 276         .stats_get            = ena_stats_get,
 277         .mtu_set              = ena_mtu_set,
 278         .rx_queue_release     = ena_rx_queue_release,
 279         .tx_queue_release     = ena_tx_queue_release,
 280         .dev_close            = ena_close,
 281         .dev_reset            = ena_dev_reset,
 282         .reta_update          = ena_rss_reta_update,
 283         .reta_query           = ena_rss_reta_query,
 284 };
 285
 286 #define NUMA_NO_NODE    SOCKET_ID_ANY
 287
 288 static inline int ena_cpu_to_node(int cpu)
 289 {
 290         struct rte_config *config = rte_eal_get_configuration();
 291         struct rte_fbarray *arr = &config->mem_config->memzones;
 292         const struct rte_memzone *mz;
 293
 294         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 295                 return NUMA_NO_NODE;
 296
 297         mz = rte_fbarray_get(arr, cpu);
 298
 299         return mz->socket_id;
 300 }
 301
 302 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 303                                        struct ena_com_rx_ctx *ena_rx_ctx)
 304 {
 305         uint64_t ol_flags = 0;
 306         uint32_t packet_type = 0;
 307
 308         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 309                 packet_type |= RTE_PTYPE_L4_TCP;
 310         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 311                 packet_type |= RTE_PTYPE_L4_UDP;
 312
 313         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 314                 packet_type |= RTE_PTYPE_L3_IPV4;
 315         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 316                 packet_type |= RTE_PTYPE_L3_IPV6;
 317
 318         if (unlikely(ena_rx_ctx->l4_csum_err))
 319                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 320         if (unlikely(ena_rx_ctx->l3_csum_err))
 321                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 322
 323         mbuf->ol_flags = ol_flags;
 324         mbuf->packet_type = packet_type;
 325 }
 326
 327 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 328                                        struct ena_com_tx_ctx *ena_tx_ctx,
 329                                        uint64_t queue_offloads)
 330 {
 331         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 332
 333         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 334             (queue_offloads & QUEUE_OFFLOADS)) {
 335                 /* check if TSO is required */
 336                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 337                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 338                         ena_tx_ctx->tso_enable = true;
 339
 340                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 341                 }
 342
 343                 /* check if L3 checksum is needed */
 344                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 345                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 346                         ena_tx_ctx->l3_csum_enable = true;
 347
 348                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 349                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 350                 } else {
 351                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 352
 353                         /* set don't fragment (DF) flag */
 354                         if (mbuf->packet_type &
 355                                 (RTE_PTYPE_L4_NONFRAG
 356                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 357                                 ena_tx_ctx->df = true;
 358                 }
 359
 360                 /* check if L4 checksum is needed */
 361                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 362                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 363                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 364                         ena_tx_ctx->l4_csum_enable = true;
 365                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 366                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 367                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 368                         ena_tx_ctx->l4_csum_enable = true;
 369                 } else {
 370                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 371                         ena_tx_ctx->l4_csum_enable = false;
 372                 }
 373
 374                 ena_meta->mss = mbuf->tso_segsz;
 375                 ena_meta->l3_hdr_len = mbuf->l3_len;
 376                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 377
 378                 ena_tx_ctx->meta_valid = true;
 379         } else {
 380                 ena_tx_ctx->meta_valid = false;
 381         }
 382 }
 383
 384 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 385 {
 386         if (likely(req_id < rx_ring->ring_size))
 387                 return 0;
 388
 389         RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
 390
 391         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 392         rx_ring->adapter->trigger_reset = true;
 393
 394         return -EFAULT;
 395 }
 396
 397 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 398 {
 399         struct ena_tx_buffer *tx_info = NULL;
 400
 401         if (likely(req_id < tx_ring->ring_size)) {
 402                 tx_info = &tx_ring->tx_buffer_info[req_id];
 403                 if (likely(tx_info->mbuf))
 404                         return 0;
 405         }
 406
 407         if (tx_info)
 408                 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n");
 409         else
 410                 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id);
 411
 412         /* Trigger device reset */
 413         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 414         tx_ring->adapter->trigger_reset = true;
 415         return -EFAULT;
 416 }
 417
 418 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 419 {
 420         struct ena_admin_host_info *host_info;
 421         int rc;
 422
 423         /* Allocate only the host info */
 424         rc = ena_com_allocate_host_info(ena_dev);
 425         if (rc) {
 426                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 427                 return;
 428         }
 429
 430         host_info = ena_dev->host_attr.host_info;
 431
 432         host_info->os_type = ENA_ADMIN_OS_DPDK;
 433         host_info->kernel_ver = RTE_VERSION;
 434         snprintf((char *)host_info->kernel_ver_str,
 435                  sizeof(host_info->kernel_ver_str),
 436                  "%s", rte_version());
 437         host_info->os_dist = RTE_VERSION;
 438         snprintf((char *)host_info->os_dist_str,
 439                  sizeof(host_info->os_dist_str),
 440                  "%s", rte_version());
 441         host_info->driver_version =
 442                 (DRV_MODULE_VER_MAJOR) |
 443                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 444                 (DRV_MODULE_VER_SUBMINOR <<
 445                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 446         host_info->num_cpus = rte_lcore_count();
 447
 448         rc = ena_com_set_host_attributes(ena_dev);
 449         if (rc) {
 450                 if (rc == -ENA_COM_UNSUPPORTED)
 451                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 452                 else
 453                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 454
 455                 goto err;
 456         }
 457
 458         return;
 459
 460 err:
 461         ena_com_delete_host_info(ena_dev);
 462 }
 463
 464 static int
 465 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 466 {
 467         if (sset != ETH_SS_STATS)
 468                 return -EOPNOTSUPP;
 469
 470          /* Workaround for clang:
 471          * touch internal structures to prevent
 472          * compiler error
 473          */
 474         ENA_TOUCH(ena_stats_global_strings);
 475         ENA_TOUCH(ena_stats_tx_strings);
 476         ENA_TOUCH(ena_stats_rx_strings);
 477         ENA_TOUCH(ena_stats_ena_com_strings);
 478
 479         return  dev->data->nb_tx_queues *
 480                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 481                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 482 }
 483
 484 static void ena_config_debug_area(struct ena_adapter *adapter)
 485 {
 486         u32 debug_area_size;
 487         int rc, ss_count;
 488
 489         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 490         if (ss_count <= 0) {
 491                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 492                 return;
 493         }
 494
 495         /* allocate 32 bytes for each string and 64bit for the value */
 496         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 497
 498         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 499         if (rc) {
 500                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 501                 return;
 502         }
 503
 504         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 505         if (rc) {
 506                 if (rc == -ENA_COM_UNSUPPORTED)
 507                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 508                 else
 509                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 510
 511                 goto err;
 512         }
 513
 514         return;
 515 err:
 516         ena_com_delete_debug_area(&adapter->ena_dev);
 517 }
 518
 519 static void ena_close(struct rte_eth_dev *dev)
 520 {
 521         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 522         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 523         struct ena_adapter *adapter =
 524                 (struct ena_adapter *)(dev->data->dev_private);
 525
 526         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 527                 ena_stop(dev);
 528         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 529
 530         ena_rx_queue_release_all(dev);
 531         ena_tx_queue_release_all(dev);
 532
 533         rte_free(adapter->drv_stats);
 534         adapter->drv_stats = NULL;
 535
 536         rte_intr_disable(intr_handle);
 537         rte_intr_callback_unregister(intr_handle,
 538                                      ena_interrupt_handler_rte,
 539                                      adapter);
 540
 541         /*
 542          * MAC is not allocated dynamically. Setting NULL should prevent from
 543          * release of the resource in the rte_eth_dev_release_port().
 544          */
 545         dev->data->mac_addrs = NULL;
 546 }
 547
 548 static int
 549 ena_dev_reset(struct rte_eth_dev *dev)
 550 {
 551         int rc = 0;
 552
 553         ena_destroy_device(dev);
 554         rc = eth_ena_dev_init(dev);
 555         if (rc)
 556                 PMD_INIT_LOG(CRIT, "Cannot initialize device");
 557
 558         return rc;
 559 }
 560
 561 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 562                                struct rte_eth_rss_reta_entry64 *reta_conf,
 563                                uint16_t reta_size)
 564 {
 565         struct ena_adapter *adapter =
 566                 (struct ena_adapter *)(dev->data->dev_private);
 567         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 568         int rc, i;
 569         u16 entry_value;
 570         int conf_idx;
 571         int idx;
 572
 573         if ((reta_size == 0) || (reta_conf == NULL))
 574                 return -EINVAL;
 575
 576         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 577                 RTE_LOG(WARNING, PMD,
 578                         "indirection table %d is bigger than supported (%d)\n",
 579                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 580                 return -EINVAL;
 581         }
 582
 583         for (i = 0 ; i < reta_size ; i++) {
 584                 /* each reta_conf is for 64 entries.
 585                  * to support 128 we use 2 conf of 64
 586                  */
 587                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 588                 idx = i % RTE_RETA_GROUP_SIZE;
 589                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 590                         entry_value =
 591                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 592
 593                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 594                                                                i,
 595                                                                entry_value);
 596                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 597                                 RTE_LOG(ERR, PMD,
 598                                         "Cannot fill indirect table\n");
 599                                 return rc;
 600                         }
 601                 }
 602         }
 603
 604         rc = ena_com_indirect_table_set(ena_dev);
 605         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 606                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 607                 return rc;
 608         }
 609
 610         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 611                 __func__, reta_size, adapter->rte_dev->data->port_id);
 612
 613         return 0;
 614 }
 615
 616 /* Query redirection table. */
 617 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 618                               struct rte_eth_rss_reta_entry64 *reta_conf,
 619                               uint16_t reta_size)
 620 {
 621         struct ena_adapter *adapter =
 622                 (struct ena_adapter *)(dev->data->dev_private);
 623         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 624         int rc;
 625         int i;
 626         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 627         int reta_conf_idx;
 628         int reta_idx;
 629
 630         if (reta_size == 0 || reta_conf == NULL ||
 631             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 632                 return -EINVAL;
 633
 634         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 635         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 636                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 637                 return -ENOTSUP;
 638         }
 639
 640         for (i = 0 ; i < reta_size ; i++) {
 641                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 642                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 643                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 644                         reta_conf[reta_conf_idx].reta[reta_idx] =
 645                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 646         }
 647
 648         return 0;
 649 }
 650
 651 static int ena_rss_init_default(struct ena_adapter *adapter)
 652 {
 653         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 654         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 655         int rc, i;
 656         u32 val;
 657
 658         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 659         if (unlikely(rc)) {
 660                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 661                 goto err_rss_init;
 662         }
 663
 664         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 665                 val = i % nb_rx_queues;
 666                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 667                                                        ENA_IO_RXQ_IDX(val));
 668                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 669                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 670                         goto err_fill_indir;
 671                 }
 672         }
 673
 674         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 675                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 676         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 677                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 678                 goto err_fill_indir;
 679         }
 680
 681         rc = ena_com_set_default_hash_ctrl(ena_dev);
 682         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 683                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 684                 goto err_fill_indir;
 685         }
 686
 687         rc = ena_com_indirect_table_set(ena_dev);
 688         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 689                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 690                 goto err_fill_indir;
 691         }
 692         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 693                 adapter->rte_dev->data->port_id);
 694
 695         return 0;
 696
 697 err_fill_indir:
 698         ena_com_rss_destroy(ena_dev);
 699 err_rss_init:
 700
 701         return rc;
 702 }
 703
 704 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 705 {
 706         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 707         int nb_queues = dev->data->nb_rx_queues;
 708         int i;
 709
 710         for (i = 0; i < nb_queues; i++)
 711                 ena_rx_queue_release(queues[i]);
 712 }
 713
 714 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 715 {
 716         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 717         int nb_queues = dev->data->nb_tx_queues;
 718         int i;
 719
 720         for (i = 0; i < nb_queues; i++)
 721                 ena_tx_queue_release(queues[i]);
 722 }
 723
 724 static void ena_rx_queue_release(void *queue)
 725 {
 726         struct ena_ring *ring = (struct ena_ring *)queue;
 727
 728         /* Free ring resources */
 729         if (ring->rx_buffer_info)
 730                 rte_free(ring->rx_buffer_info);
 731         ring->rx_buffer_info = NULL;
 732
 733         if (ring->rx_refill_buffer)
 734                 rte_free(ring->rx_refill_buffer);
 735         ring->rx_refill_buffer = NULL;
 736
 737         if (ring->empty_rx_reqs)
 738                 rte_free(ring->empty_rx_reqs);
 739         ring->empty_rx_reqs = NULL;
 740
 741         ring->configured = 0;
 742
 743         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 744                 ring->port_id, ring->id);
 745 }
 746
 747 static void ena_tx_queue_release(void *queue)
 748 {
 749         struct ena_ring *ring = (struct ena_ring *)queue;
 750
 751         /* Free ring resources */
 752         if (ring->push_buf_intermediate_buf)
 753                 rte_free(ring->push_buf_intermediate_buf);
 754
 755         if (ring->tx_buffer_info)
 756                 rte_free(ring->tx_buffer_info);
 757
 758         if (ring->empty_tx_reqs)
 759                 rte_free(ring->empty_tx_reqs);
 760
 761         ring->empty_tx_reqs = NULL;
 762         ring->tx_buffer_info = NULL;
 763         ring->push_buf_intermediate_buf = NULL;
 764
 765         ring->configured = 0;
 766
 767         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 768                 ring->port_id, ring->id);
 769 }
 770
 771 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 772 {
 773         unsigned int i;
 774
 775         for (i = 0; i < ring->ring_size; ++i)
 776                 if (ring->rx_buffer_info[i]) {
 777                         rte_mbuf_raw_free(ring->rx_buffer_info[i]);
 778                         ring->rx_buffer_info[i] = NULL;
 779                 }
 780 }
 781
 782 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 783 {
 784         unsigned int i;
 785
 786         for (i = 0; i < ring->ring_size; ++i) {
 787                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 788
 789                 if (tx_buf->mbuf)
 790                         rte_pktmbuf_free(tx_buf->mbuf);
 791         }
 792 }
 793
 794 static int ena_link_update(struct rte_eth_dev *dev,
 795                            __rte_unused int wait_to_complete)
 796 {
 797         struct rte_eth_link *link = &dev->data->dev_link;
 798         struct ena_adapter *adapter;
 799
 800         adapter = (struct ena_adapter *)(dev->data->dev_private);
 801
 802         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 803         link->link_speed = ETH_SPEED_NUM_NONE;
 804         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 805
 806         return 0;
 807 }
 808
 809 static int ena_queue_start_all(struct rte_eth_dev *dev,
 810                                enum ena_ring_type ring_type)
 811 {
 812         struct ena_adapter *adapter =
 813                 (struct ena_adapter *)(dev->data->dev_private);
 814         struct ena_ring *queues = NULL;
 815         int nb_queues;
 816         int i = 0;
 817         int rc = 0;
 818
 819         if (ring_type == ENA_RING_TYPE_RX) {
 820                 queues = adapter->rx_ring;
 821                 nb_queues = dev->data->nb_rx_queues;
 822         } else {
 823                 queues = adapter->tx_ring;
 824                 nb_queues = dev->data->nb_tx_queues;
 825         }
 826         for (i = 0; i < nb_queues; i++) {
 827                 if (queues[i].configured) {
 828                         if (ring_type == ENA_RING_TYPE_RX) {
 829                                 ena_assert_msg(
 830                                         dev->data->rx_queues[i] == &queues[i],
 831                                         "Inconsistent state of rx queues\n");
 832                         } else {
 833                                 ena_assert_msg(
 834                                         dev->data->tx_queues[i] == &queues[i],
 835                                         "Inconsistent state of tx queues\n");
 836                         }
 837
 838                         rc = ena_queue_start(&queues[i]);
 839
 840                         if (rc) {
 841                                 PMD_INIT_LOG(ERR,
 842                                              "failed to start queue %d type(%d)",
 843                                              i, ring_type);
 844                                 goto err;
 845                         }
 846                 }
 847         }
 848
 849         return 0;
 850
 851 err:
 852         while (i--)
 853                 if (queues[i].configured)
 854                         ena_queue_stop(&queues[i]);
 855
 856         return rc;
 857 }
 858
 859 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 860 {
 861         uint32_t max_frame_len = adapter->max_mtu;
 862
 863         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 864             DEV_RX_OFFLOAD_JUMBO_FRAME)
 865                 max_frame_len =
 866                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 867
 868         return max_frame_len;
 869 }
 870
 871 static int ena_check_valid_conf(struct ena_adapter *adapter)
 872 {
 873         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 874
 875         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 876                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 877                                   "max mtu: %d, min mtu: %d",
 878                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 879                 return ENA_COM_UNSUPPORTED;
 880         }
 881
 882         return 0;
 883 }
 884
 885 static int
 886 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)
 887 {
 888         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 889         struct ena_com_dev *ena_dev = ctx->ena_dev;
 890         uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX;
 891         uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX;
 892
 893         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 894                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 895                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 896                 rx_queue_size = RTE_MIN(rx_queue_size,
 897                         max_queue_ext->max_rx_cq_depth);
 898                 rx_queue_size = RTE_MIN(rx_queue_size,
 899                         max_queue_ext->max_rx_sq_depth);
 900                 tx_queue_size = RTE_MIN(tx_queue_size,
 901                         max_queue_ext->max_tx_cq_depth);
 902
 903                 if (ena_dev->tx_mem_queue_type ==
 904                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 905                         tx_queue_size = RTE_MIN(tx_queue_size,
 906                                 llq->max_llq_depth);
 907                 } else {
 908                         tx_queue_size = RTE_MIN(tx_queue_size,
 909                                 max_queue_ext->max_tx_sq_depth);
 910                 }
 911
 912                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 913                         max_queue_ext->max_per_packet_rx_descs);
 914                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 915                         max_queue_ext->max_per_packet_tx_descs);
 916         } else {
 917                 struct ena_admin_queue_feature_desc *max_queues =
 918                         &ctx->get_feat_ctx->max_queues;
 919                 rx_queue_size = RTE_MIN(rx_queue_size,
 920                         max_queues->max_cq_depth);
 921                 rx_queue_size = RTE_MIN(rx_queue_size,
 922                         max_queues->max_sq_depth);
 923                 tx_queue_size = RTE_MIN(tx_queue_size,
 924                         max_queues->max_cq_depth);
 925
 926                 if (ena_dev->tx_mem_queue_type ==
 927                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 928                         tx_queue_size = RTE_MIN(tx_queue_size,
 929                                 llq->max_llq_depth);
 930                 } else {
 931                         tx_queue_size = RTE_MIN(tx_queue_size,
 932                                 max_queues->max_sq_depth);
 933                 }
 934
 935                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 936                         max_queues->max_packet_tx_descs);
 937                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 938                         max_queues->max_packet_rx_descs);
 939         }
 940
 941         /* Round down to the nearest power of 2 */
 942         rx_queue_size = rte_align32prevpow2(rx_queue_size);
 943         tx_queue_size = rte_align32prevpow2(tx_queue_size);
 944
 945         if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) {
 946                 PMD_INIT_LOG(ERR, "Invalid queue size");
 947                 return -EFAULT;
 948         }
 949
 950         ctx->rx_queue_size = rx_queue_size;
 951         ctx->tx_queue_size = tx_queue_size;
 952
 953         return 0;
 954 }
 955
 956 static void ena_stats_restart(struct rte_eth_dev *dev)
 957 {
 958         struct ena_adapter *adapter =
 959                 (struct ena_adapter *)(dev->data->dev_private);
 960
 961         rte_atomic64_init(&adapter->drv_stats->ierrors);
 962         rte_atomic64_init(&adapter->drv_stats->oerrors);
 963         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 964 }
 965
 966 static int ena_stats_get(struct rte_eth_dev *dev,
 967                           struct rte_eth_stats *stats)
 968 {
 969         struct ena_admin_basic_stats ena_stats;
 970         struct ena_adapter *adapter =
 971                 (struct ena_adapter *)(dev->data->dev_private);
 972         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 973         int rc;
 974
 975         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 976                 return -ENOTSUP;
 977
 978         memset(&ena_stats, 0, sizeof(ena_stats));
 979         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 980         if (unlikely(rc)) {
 981                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA\n");
 982                 return rc;
 983         }
 984
 985         /* Set of basic statistics from ENA */
 986         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 987                                           ena_stats.rx_pkts_low);
 988         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 989                                           ena_stats.tx_pkts_low);
 990         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 991                                         ena_stats.rx_bytes_low);
 992         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 993                                         ena_stats.tx_bytes_low);
 994         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 995                                          ena_stats.rx_drops_low);
 996
 997         /* Driver related stats */
 998         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 999         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1000         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1001         return 0;
1002 }
1003
1004 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1005 {
1006         struct ena_adapter *adapter;
1007         struct ena_com_dev *ena_dev;
1008         int rc = 0;
1009
1010         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1011         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1012         adapter = (struct ena_adapter *)(dev->data->dev_private);
1013
1014         ena_dev = &adapter->ena_dev;
1015         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1016
1017         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1018                 RTE_LOG(ERR, PMD,
1019                         "Invalid MTU setting. new_mtu: %d "
1020                         "max mtu: %d min mtu: %d\n",
1021                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1022                 return -EINVAL;
1023         }
1024
1025         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1026         if (rc)
1027                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
1028         else
1029                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1030
1031         return rc;
1032 }
1033
1034 static int ena_start(struct rte_eth_dev *dev)
1035 {
1036         struct ena_adapter *adapter =
1037                 (struct ena_adapter *)(dev->data->dev_private);
1038         uint64_t ticks;
1039         int rc = 0;
1040
1041         rc = ena_check_valid_conf(adapter);
1042         if (rc)
1043                 return rc;
1044
1045         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1046         if (rc)
1047                 return rc;
1048
1049         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1050         if (rc)
1051                 goto err_start_tx;
1052
1053         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1054             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1055                 rc = ena_rss_init_default(adapter);
1056                 if (rc)
1057                         goto err_rss_init;
1058         }
1059
1060         ena_stats_restart(dev);
1061
1062         adapter->timestamp_wd = rte_get_timer_cycles();
1063         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1064
1065         ticks = rte_get_timer_hz();
1066         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1067                         ena_timer_wd_callback, adapter);
1068
1069         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1070
1071         return 0;
1072
1073 err_rss_init:
1074         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1075 err_start_tx:
1076         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1077         return rc;
1078 }
1079
1080 static void ena_stop(struct rte_eth_dev *dev)
1081 {
1082         struct ena_adapter *adapter =
1083                 (struct ena_adapter *)(dev->data->dev_private);
1084         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1085         int rc;
1086
1087         rte_timer_stop_sync(&adapter->timer_wd);
1088         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1089         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1090
1091         if (adapter->trigger_reset) {
1092                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1093                 if (rc)
1094                         RTE_LOG(ERR, PMD, "Device reset failed rc=%d\n", rc);
1095         }
1096
1097         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1098 }
1099
1100 static int ena_create_io_queue(struct ena_ring *ring)
1101 {
1102         struct ena_adapter *adapter;
1103         struct ena_com_dev *ena_dev;
1104         struct ena_com_create_io_ctx ctx =
1105                 /* policy set to _HOST just to satisfy icc compiler */
1106                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1107                   0, 0, 0, 0, 0 };
1108         uint16_t ena_qid;
1109         unsigned int i;
1110         int rc;
1111
1112         adapter = ring->adapter;
1113         ena_dev = &adapter->ena_dev;
1114
1115         if (ring->type == ENA_RING_TYPE_TX) {
1116                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1117                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1118                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1119                 ctx.queue_size = adapter->tx_ring_size;
1120                 for (i = 0; i < ring->ring_size; i++)
1121                         ring->empty_tx_reqs[i] = i;
1122         } else {
1123                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1124                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1125                 ctx.queue_size = adapter->rx_ring_size;
1126                 for (i = 0; i < ring->ring_size; i++)
1127                         ring->empty_rx_reqs[i] = i;
1128         }
1129         ctx.qid = ena_qid;
1130         ctx.msix_vector = -1; /* interrupts not used */
1131         ctx.numa_node = ena_cpu_to_node(ring->id);
1132
1133         rc = ena_com_create_io_queue(ena_dev, &ctx);
1134         if (rc) {
1135                 RTE_LOG(ERR, PMD,
1136                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1137                         ring->id, ena_qid, rc);
1138                 return rc;
1139         }
1140
1141         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1142                                      &ring->ena_com_io_sq,
1143                                      &ring->ena_com_io_cq);
1144         if (rc) {
1145                 RTE_LOG(ERR, PMD,
1146                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1147                         ring->id, rc);
1148                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1149                 return rc;
1150         }
1151
1152         if (ring->type == ENA_RING_TYPE_TX)
1153                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1154
1155         return 0;
1156 }
1157
1158 static void ena_queue_stop(struct ena_ring *ring)
1159 {
1160         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1161
1162         if (ring->type == ENA_RING_TYPE_RX) {
1163                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1164                 ena_rx_queue_release_bufs(ring);
1165         } else {
1166                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1167                 ena_tx_queue_release_bufs(ring);
1168         }
1169 }
1170
1171 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1172                               enum ena_ring_type ring_type)
1173 {
1174         struct ena_adapter *adapter =
1175                 (struct ena_adapter *)(dev->data->dev_private);
1176         struct ena_ring *queues = NULL;
1177         uint16_t nb_queues, i;
1178
1179         if (ring_type == ENA_RING_TYPE_RX) {
1180                 queues = adapter->rx_ring;
1181                 nb_queues = dev->data->nb_rx_queues;
1182         } else {
1183                 queues = adapter->tx_ring;
1184                 nb_queues = dev->data->nb_tx_queues;
1185         }
1186
1187         for (i = 0; i < nb_queues; ++i)
1188                 if (queues[i].configured)
1189                         ena_queue_stop(&queues[i]);
1190 }
1191
1192 static int ena_queue_start(struct ena_ring *ring)
1193 {
1194         int rc, bufs_num;
1195
1196         ena_assert_msg(ring->configured == 1,
1197                        "Trying to start unconfigured queue\n");
1198
1199         rc = ena_create_io_queue(ring);
1200         if (rc) {
1201                 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1202                 return rc;
1203         }
1204
1205         ring->next_to_clean = 0;
1206         ring->next_to_use = 0;
1207
1208         if (ring->type == ENA_RING_TYPE_TX)
1209                 return 0;
1210
1211         bufs_num = ring->ring_size - 1;
1212         rc = ena_populate_rx_queue(ring, bufs_num);
1213         if (rc != bufs_num) {
1214                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1215                                          ENA_IO_RXQ_IDX(ring->id));
1216                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1217                 return ENA_COM_FAULT;
1218         }
1219
1220         return 0;
1221 }
1222
1223 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1224                               uint16_t queue_idx,
1225                               uint16_t nb_desc,
1226                               __rte_unused unsigned int socket_id,
1227                               const struct rte_eth_txconf *tx_conf)
1228 {
1229         struct ena_ring *txq = NULL;
1230         struct ena_adapter *adapter =
1231                 (struct ena_adapter *)(dev->data->dev_private);
1232         unsigned int i;
1233
1234         txq = &adapter->tx_ring[queue_idx];
1235
1236         if (txq->configured) {
1237                 RTE_LOG(CRIT, PMD,
1238                         "API violation. Queue %d is already configured\n",
1239                         queue_idx);
1240                 return ENA_COM_FAULT;
1241         }
1242
1243         if (!rte_is_power_of_2(nb_desc)) {
1244                 RTE_LOG(ERR, PMD,
1245                         "Unsupported size of TX queue: %d is not a power of 2.\n",
1246                         nb_desc);
1247                 return -EINVAL;
1248         }
1249
1250         if (nb_desc > adapter->tx_ring_size) {
1251                 RTE_LOG(ERR, PMD,
1252                         "Unsupported size of TX queue (max size: %d)\n",
1253                         adapter->tx_ring_size);
1254                 return -EINVAL;
1255         }
1256
1257         if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1258                 nb_desc = adapter->tx_ring_size;
1259
1260         txq->port_id = dev->data->port_id;
1261         txq->next_to_clean = 0;
1262         txq->next_to_use = 0;
1263         txq->ring_size = nb_desc;
1264
1265         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1266                                           sizeof(struct ena_tx_buffer) *
1267                                           txq->ring_size,
1268                                           RTE_CACHE_LINE_SIZE);
1269         if (!txq->tx_buffer_info) {
1270                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1271                 return -ENOMEM;
1272         }
1273
1274         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1275                                          sizeof(u16) * txq->ring_size,
1276                                          RTE_CACHE_LINE_SIZE);
1277         if (!txq->empty_tx_reqs) {
1278                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1279                 rte_free(txq->tx_buffer_info);
1280                 return -ENOMEM;
1281         }
1282
1283         txq->push_buf_intermediate_buf =
1284                 rte_zmalloc("txq->push_buf_intermediate_buf",
1285                             txq->tx_max_header_size,
1286                             RTE_CACHE_LINE_SIZE);
1287         if (!txq->push_buf_intermediate_buf) {
1288                 RTE_LOG(ERR, PMD, "failed to alloc push buff for LLQ\n");
1289                 rte_free(txq->tx_buffer_info);
1290                 rte_free(txq->empty_tx_reqs);
1291                 return -ENOMEM;
1292         }
1293
1294         for (i = 0; i < txq->ring_size; i++)
1295                 txq->empty_tx_reqs[i] = i;
1296
1297         if (tx_conf != NULL) {
1298                 txq->offloads =
1299                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1300         }
1301
1302         /* Store pointer to this queue in upper layer */
1303         txq->configured = 1;
1304         dev->data->tx_queues[queue_idx] = txq;
1305
1306         return 0;
1307 }
1308
1309 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1310                               uint16_t queue_idx,
1311                               uint16_t nb_desc,
1312                               __rte_unused unsigned int socket_id,
1313                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1314                               struct rte_mempool *mp)
1315 {
1316         struct ena_adapter *adapter =
1317                 (struct ena_adapter *)(dev->data->dev_private);
1318         struct ena_ring *rxq = NULL;
1319         int i;
1320
1321         rxq = &adapter->rx_ring[queue_idx];
1322         if (rxq->configured) {
1323                 RTE_LOG(CRIT, PMD,
1324                         "API violation. Queue %d is already configured\n",
1325                         queue_idx);
1326                 return ENA_COM_FAULT;
1327         }
1328
1329         if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1330                 nb_desc = adapter->rx_ring_size;
1331
1332         if (!rte_is_power_of_2(nb_desc)) {
1333                 RTE_LOG(ERR, PMD,
1334                         "Unsupported size of RX queue: %d is not a power of 2.\n",
1335                         nb_desc);
1336                 return -EINVAL;
1337         }
1338
1339         if (nb_desc > adapter->rx_ring_size) {
1340                 RTE_LOG(ERR, PMD,
1341                         "Unsupported size of RX queue (max size: %d)\n",
1342                         adapter->rx_ring_size);
1343                 return -EINVAL;
1344         }
1345
1346         rxq->port_id = dev->data->port_id;
1347         rxq->next_to_clean = 0;
1348         rxq->next_to_use = 0;
1349         rxq->ring_size = nb_desc;
1350         rxq->mb_pool = mp;
1351
1352         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1353                                           sizeof(struct rte_mbuf *) * nb_desc,
1354                                           RTE_CACHE_LINE_SIZE);
1355         if (!rxq->rx_buffer_info) {
1356                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1357                 return -ENOMEM;
1358         }
1359
1360         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1361                                             sizeof(struct rte_mbuf *) * nb_desc,
1362                                             RTE_CACHE_LINE_SIZE);
1363
1364         if (!rxq->rx_refill_buffer) {
1365                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n");
1366                 rte_free(rxq->rx_buffer_info);
1367                 rxq->rx_buffer_info = NULL;
1368                 return -ENOMEM;
1369         }
1370
1371         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1372                                          sizeof(uint16_t) * nb_desc,
1373                                          RTE_CACHE_LINE_SIZE);
1374         if (!rxq->empty_rx_reqs) {
1375                 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1376                 rte_free(rxq->rx_buffer_info);
1377                 rxq->rx_buffer_info = NULL;
1378                 rte_free(rxq->rx_refill_buffer);
1379                 rxq->rx_refill_buffer = NULL;
1380                 return -ENOMEM;
1381         }
1382
1383         for (i = 0; i < nb_desc; i++)
1384                 rxq->empty_rx_reqs[i] = i;
1385
1386         /* Store pointer to this queue in upper layer */
1387         rxq->configured = 1;
1388         dev->data->rx_queues[queue_idx] = rxq;
1389
1390         return 0;
1391 }
1392
1393 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1394 {
1395         unsigned int i;
1396         int rc;
1397         uint16_t ring_size = rxq->ring_size;
1398         uint16_t ring_mask = ring_size - 1;
1399         uint16_t next_to_use = rxq->next_to_use;
1400         uint16_t in_use, req_id;
1401         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1402
1403         if (unlikely(!count))
1404                 return 0;
1405
1406         in_use = rxq->next_to_use - rxq->next_to_clean;
1407         ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n");
1408
1409         /* get resources for incoming packets */
1410         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1411         if (unlikely(rc < 0)) {
1412                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1413                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1414                 return 0;
1415         }
1416
1417         for (i = 0; i < count; i++) {
1418                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1419                 struct rte_mbuf *mbuf = mbufs[i];
1420                 struct ena_com_buf ebuf;
1421
1422                 if (likely((i + 4) < count))
1423                         rte_prefetch0(mbufs[i + 4]);
1424
1425                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1426                 rc = validate_rx_req_id(rxq, req_id);
1427                 if (unlikely(rc < 0))
1428                         break;
1429                 rxq->rx_buffer_info[req_id] = mbuf;
1430
1431                 /* prepare physical address for DMA transaction */
1432                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1433                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1434                 /* pass resource to device */
1435                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1436                                                 &ebuf, req_id);
1437                 if (unlikely(rc)) {
1438                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1439                         rxq->rx_buffer_info[req_id] = NULL;
1440                         break;
1441                 }
1442                 next_to_use++;
1443         }
1444
1445         if (unlikely(i < count)) {
1446                 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d "
1447                         "buffers (from %d)\n", rxq->id, i, count);
1448                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1449                                      count - i);
1450         }
1451
1452         /* When we submitted free recources to device... */
1453         if (likely(i > 0)) {
1454                 /* ...let HW know that it can fill buffers with data
1455                  *
1456                  * Add memory barrier to make sure the desc were written before
1457                  * issue a doorbell
1458                  */
1459                 rte_wmb();
1460                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1461
1462                 rxq->next_to_use = next_to_use;
1463         }
1464
1465         return i;
1466 }
1467
1468 static int ena_device_init(struct ena_com_dev *ena_dev,
1469                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1470                            bool *wd_state)
1471 {
1472         uint32_t aenq_groups;
1473         int rc;
1474         bool readless_supported;
1475
1476         /* Initialize mmio registers */
1477         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1478         if (rc) {
1479                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1480                 return rc;
1481         }
1482
1483         /* The PCIe configuration space revision id indicate if mmio reg
1484          * read is disabled.
1485          */
1486         readless_supported =
1487                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1488                                & ENA_MMIO_DISABLE_REG_READ);
1489         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1490
1491         /* reset device */
1492         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1493         if (rc) {
1494                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1495                 goto err_mmio_read_less;
1496         }
1497
1498         /* check FW version */
1499         rc = ena_com_validate_version(ena_dev);
1500         if (rc) {
1501                 RTE_LOG(ERR, PMD, "device version is too low\n");
1502                 goto err_mmio_read_less;
1503         }
1504
1505         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1506
1507         /* ENA device administration layer init */
1508         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1509         if (rc) {
1510                 RTE_LOG(ERR, PMD,
1511                         "cannot initialize ena admin queue with device\n");
1512                 goto err_mmio_read_less;
1513         }
1514
1515         /* To enable the msix interrupts the driver needs to know the number
1516          * of queues. So the driver uses polling mode to retrieve this
1517          * information.
1518          */
1519         ena_com_set_admin_polling_mode(ena_dev, true);
1520
1521         ena_config_host_info(ena_dev);
1522
1523         /* Get Device Attributes and features */
1524         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1525         if (rc) {
1526                 RTE_LOG(ERR, PMD,
1527                         "cannot get attribute for ena device rc= %d\n", rc);
1528                 goto err_admin_init;
1529         }
1530
1531         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1532                       BIT(ENA_ADMIN_NOTIFICATION) |
1533                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1534                       BIT(ENA_ADMIN_FATAL_ERROR) |
1535                       BIT(ENA_ADMIN_WARNING);
1536
1537         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1538         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1539         if (rc) {
1540                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1541                 goto err_admin_init;
1542         }
1543
1544         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1545
1546         return 0;
1547
1548 err_admin_init:
1549         ena_com_admin_destroy(ena_dev);
1550
1551 err_mmio_read_less:
1552         ena_com_mmio_reg_read_request_destroy(ena_dev);
1553
1554         return rc;
1555 }
1556
1557 static void ena_interrupt_handler_rte(void *cb_arg)
1558 {
1559         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1560         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1561
1562         ena_com_admin_q_comp_intr_handler(ena_dev);
1563         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1564                 ena_com_aenq_intr_handler(ena_dev, adapter);
1565 }
1566
1567 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1568 {
1569         if (!adapter->wd_state)
1570                 return;
1571
1572         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1573                 return;
1574
1575         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1576             adapter->keep_alive_timeout)) {
1577                 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1578                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1579                 adapter->trigger_reset = true;
1580         }
1581 }
1582
1583 /* Check if admin queue is enabled */
1584 static void check_for_admin_com_state(struct ena_adapter *adapter)
1585 {
1586         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1587                 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1588                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1589                 adapter->trigger_reset = true;
1590         }
1591 }
1592
1593 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1594                                   void *arg)
1595 {
1596         struct ena_adapter *adapter = (struct ena_adapter *)arg;
1597         struct rte_eth_dev *dev = adapter->rte_dev;
1598
1599         check_for_missing_keep_alive(adapter);
1600         check_for_admin_com_state(adapter);
1601
1602         if (unlikely(adapter->trigger_reset)) {
1603                 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1604                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1605                         NULL);
1606         }
1607 }
1608
1609 static inline void
1610 set_default_llq_configurations(struct ena_llq_configurations *llq_config)
1611 {
1612         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1613         llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1614         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1615         llq_config->llq_num_decs_before_header =
1616                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1617         llq_config->llq_ring_entry_size_value = 128;
1618 }
1619
1620 static int
1621 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1622                                 struct ena_com_dev *ena_dev,
1623                                 struct ena_admin_feature_llq_desc *llq,
1624                                 struct ena_llq_configurations *llq_default_configurations)
1625 {
1626         int rc;
1627         u32 llq_feature_mask;
1628
1629         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1630         if (!(ena_dev->supported_features & llq_feature_mask)) {
1631                 RTE_LOG(INFO, PMD,
1632                         "LLQ is not supported. Fallback to host mode policy.\n");
1633                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1634                 return 0;
1635         }
1636
1637         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1638         if (unlikely(rc)) {
1639                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1640                         "Fallback to host mode policy.");
1641                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1642                 return 0;
1643         }
1644
1645         /* Nothing to config, exit */
1646         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1647                 return 0;
1648
1649         if (!adapter->dev_mem_base) {
1650                 RTE_LOG(ERR, PMD, "Unable to access LLQ bar resource. "
1651                         "Fallback to host mode policy.\n.");
1652                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1653                 return 0;
1654         }
1655
1656         ena_dev->mem_bar = adapter->dev_mem_base;
1657
1658         return 0;
1659 }
1660
1661 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,
1662                                  struct ena_com_dev_get_features_ctx *get_feat_ctx)
1663 {
1664         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num;
1665
1666         /* Regular queues capabilities */
1667         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1668                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1669                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1670                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1671                                     max_queue_ext->max_rx_cq_num);
1672                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1673                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1674         } else {
1675                 struct ena_admin_queue_feature_desc *max_queues =
1676                         &get_feat_ctx->max_queues;
1677                 io_tx_sq_num = max_queues->max_sq_num;
1678                 io_tx_cq_num = max_queues->max_cq_num;
1679                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1680         }
1681
1682         /* In case of LLQ use the llq number in the get feature cmd */
1683         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1684                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1685
1686         io_queue_num = RTE_MIN(rte_lcore_count(), ENA_MAX_NUM_IO_QUEUES);
1687         io_queue_num = RTE_MIN(io_queue_num, io_rx_num);
1688         io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num);
1689         io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num);
1690
1691         if (unlikely(io_queue_num == 0)) {
1692                 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n");
1693                 return -EFAULT;
1694         }
1695
1696         return io_queue_num;
1697 }
1698
1699 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1700 {
1701         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1702         struct rte_pci_device *pci_dev;
1703         struct rte_intr_handle *intr_handle;
1704         struct ena_adapter *adapter =
1705                 (struct ena_adapter *)(eth_dev->data->dev_private);
1706         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1707         struct ena_com_dev_get_features_ctx get_feat_ctx;
1708         struct ena_llq_configurations llq_config;
1709         const char *queue_type_str;
1710         int rc;
1711
1712         static int adapters_found;
1713         bool wd_state;
1714
1715         memset(adapter, 0, sizeof(struct ena_adapter));
1716         ena_dev = &adapter->ena_dev;
1717
1718         eth_dev->dev_ops = &ena_dev_ops;
1719         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1720         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1721         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1722         adapter->rte_eth_dev_data = eth_dev->data;
1723         adapter->rte_dev = eth_dev;
1724
1725         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1726                 return 0;
1727
1728         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1729         adapter->pdev = pci_dev;
1730
1731         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1732                      pci_dev->addr.domain,
1733                      pci_dev->addr.bus,
1734                      pci_dev->addr.devid,
1735                      pci_dev->addr.function);
1736
1737         intr_handle = &pci_dev->intr_handle;
1738
1739         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1740         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1741
1742         if (!adapter->regs) {
1743                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1744                              ENA_REGS_BAR);
1745                 return -ENXIO;
1746         }
1747
1748         ena_dev->reg_bar = adapter->regs;
1749         ena_dev->dmadev = adapter->pdev;
1750
1751         adapter->id_number = adapters_found;
1752
1753         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1754                  adapter->id_number);
1755
1756         /* device specific initialization routine */
1757         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1758         if (rc) {
1759                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1760                 goto err;
1761         }
1762         adapter->wd_state = wd_state;
1763
1764         set_default_llq_configurations(&llq_config);
1765         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1766                                              &get_feat_ctx.llq, &llq_config);
1767         if (unlikely(rc)) {
1768                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1769                 return rc;
1770         }
1771
1772         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1773                 queue_type_str = "Regular";
1774         else
1775                 queue_type_str = "Low latency";
1776         RTE_LOG(INFO, PMD, "Placement policy: %s\n", queue_type_str);
1777
1778         calc_queue_ctx.ena_dev = ena_dev;
1779         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1780         adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1781                                                     &get_feat_ctx);
1782
1783         rc = ena_calc_queue_size(&calc_queue_ctx);
1784         if (unlikely((rc != 0) || (adapter->num_queues <= 0))) {
1785                 rc = -EFAULT;
1786                 goto err_device_destroy;
1787         }
1788
1789         adapter->tx_ring_size = calc_queue_ctx.tx_queue_size;
1790         adapter->rx_ring_size = calc_queue_ctx.rx_queue_size;
1791
1792         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1793         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1794
1795         /* prepare ring structures */
1796         ena_init_rings(adapter);
1797
1798         ena_config_debug_area(adapter);
1799
1800         /* Set max MTU for this device */
1801         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1802
1803         /* set device support for TSO */
1804         adapter->tso4_supported = get_feat_ctx.offload.tx &
1805                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1806
1807         /* Copy MAC address and point DPDK to it */
1808         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1809         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1810                         (struct ether_addr *)adapter->mac_addr);
1811
1812         /*
1813          * Pass the information to the rte_eth_dev_close() that it should also
1814          * release the private port resources.
1815          */
1816         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1817
1818         adapter->drv_stats = rte_zmalloc("adapter stats",
1819                                          sizeof(*adapter->drv_stats),
1820                                          RTE_CACHE_LINE_SIZE);
1821         if (!adapter->drv_stats) {
1822                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1823                 rc = -ENOMEM;
1824                 goto err_delete_debug_area;
1825         }
1826
1827         rte_intr_callback_register(intr_handle,
1828                                    ena_interrupt_handler_rte,
1829                                    adapter);
1830         rte_intr_enable(intr_handle);
1831         ena_com_set_admin_polling_mode(ena_dev, false);
1832         ena_com_admin_aenq_enable(ena_dev);
1833
1834         if (adapters_found == 0)
1835                 rte_timer_subsystem_init();
1836         rte_timer_init(&adapter->timer_wd);
1837
1838         adapters_found++;
1839         adapter->state = ENA_ADAPTER_STATE_INIT;
1840
1841         return 0;
1842
1843 err_delete_debug_area:
1844         ena_com_delete_debug_area(ena_dev);
1845
1846 err_device_destroy:
1847         ena_com_delete_host_info(ena_dev);
1848         ena_com_admin_destroy(ena_dev);
1849
1850 err:
1851         return rc;
1852 }
1853
1854 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1855 {
1856         struct ena_adapter *adapter =
1857                 (struct ena_adapter *)(eth_dev->data->dev_private);
1858         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1859
1860         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1861                 return;
1862
1863         ena_com_set_admin_running_state(ena_dev, false);
1864
1865         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1866                 ena_close(eth_dev);
1867
1868         ena_com_delete_debug_area(ena_dev);
1869         ena_com_delete_host_info(ena_dev);
1870
1871         ena_com_abort_admin_commands(ena_dev);
1872         ena_com_wait_for_abort_completion(ena_dev);
1873         ena_com_admin_destroy(ena_dev);
1874         ena_com_mmio_reg_read_request_destroy(ena_dev);
1875
1876         adapter->state = ENA_ADAPTER_STATE_FREE;
1877 }
1878
1879 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1880 {
1881         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1882                 return 0;
1883
1884         ena_destroy_device(eth_dev);
1885
1886         eth_dev->dev_ops = NULL;
1887         eth_dev->rx_pkt_burst = NULL;
1888         eth_dev->tx_pkt_burst = NULL;
1889         eth_dev->tx_pkt_prepare = NULL;
1890
1891         return 0;
1892 }
1893
1894 static int ena_dev_configure(struct rte_eth_dev *dev)
1895 {
1896         struct ena_adapter *adapter =
1897                 (struct ena_adapter *)(dev->data->dev_private);
1898
1899         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1900
1901         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1902         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1903         return 0;
1904 }
1905
1906 static void ena_init_rings(struct ena_adapter *adapter)
1907 {
1908         int i;
1909
1910         for (i = 0; i < adapter->num_queues; i++) {
1911                 struct ena_ring *ring = &adapter->tx_ring[i];
1912
1913                 ring->configured = 0;
1914                 ring->type = ENA_RING_TYPE_TX;
1915                 ring->adapter = adapter;
1916                 ring->id = i;
1917                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1918                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1919                 ring->sgl_size = adapter->max_tx_sgl_size;
1920         }
1921
1922         for (i = 0; i < adapter->num_queues; i++) {
1923                 struct ena_ring *ring = &adapter->rx_ring[i];
1924
1925                 ring->configured = 0;
1926                 ring->type = ENA_RING_TYPE_RX;
1927                 ring->adapter = adapter;
1928                 ring->id = i;
1929                 ring->sgl_size = adapter->max_rx_sgl_size;
1930         }
1931 }
1932
1933 static void ena_infos_get(struct rte_eth_dev *dev,
1934                           struct rte_eth_dev_info *dev_info)
1935 {
1936         struct ena_adapter *adapter;
1937         struct ena_com_dev *ena_dev;
1938         struct ena_com_dev_get_features_ctx feat;
1939         uint64_t rx_feat = 0, tx_feat = 0;
1940         int rc = 0;
1941
1942         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1943         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1944         adapter = (struct ena_adapter *)(dev->data->dev_private);
1945
1946         ena_dev = &adapter->ena_dev;
1947         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1948
1949         dev_info->speed_capa =
1950                         ETH_LINK_SPEED_1G   |
1951                         ETH_LINK_SPEED_2_5G |
1952                         ETH_LINK_SPEED_5G   |
1953                         ETH_LINK_SPEED_10G  |
1954                         ETH_LINK_SPEED_25G  |
1955                         ETH_LINK_SPEED_40G  |
1956                         ETH_LINK_SPEED_50G  |
1957                         ETH_LINK_SPEED_100G;
1958
1959         /* Get supported features from HW */
1960         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1961         if (unlikely(rc)) {
1962                 RTE_LOG(ERR, PMD,
1963                         "Cannot get attribute for ena device rc= %d\n", rc);
1964                 return;
1965         }
1966
1967         /* Set Tx & Rx features available for device */
1968         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1969                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1970
1971         if (feat.offload.tx &
1972             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1973                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1974                         DEV_TX_OFFLOAD_UDP_CKSUM |
1975                         DEV_TX_OFFLOAD_TCP_CKSUM;
1976
1977         if (feat.offload.rx_supported &
1978             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1979                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1980                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1981                         DEV_RX_OFFLOAD_TCP_CKSUM;
1982
1983         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1984
1985         /* Inform framework about available features */
1986         dev_info->rx_offload_capa = rx_feat;
1987         dev_info->rx_queue_offload_capa = rx_feat;
1988         dev_info->tx_offload_capa = tx_feat;
1989         dev_info->tx_queue_offload_capa = tx_feat;
1990
1991         dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
1992                                            ETH_RSS_UDP;
1993
1994         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1995         dev_info->max_rx_pktlen  = adapter->max_mtu;
1996         dev_info->max_mac_addrs = 1;
1997
1998         dev_info->max_rx_queues = adapter->num_queues;
1999         dev_info->max_tx_queues = adapter->num_queues;
2000         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2001
2002         adapter->tx_supported_offloads = tx_feat;
2003         adapter->rx_supported_offloads = rx_feat;
2004
2005         dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size;
2006         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2007         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2008                                         adapter->max_rx_sgl_size);
2009         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2010                                         adapter->max_rx_sgl_size);
2011
2012         dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size;
2013         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2014         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2015                                         adapter->max_tx_sgl_size);
2016         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2017                                         adapter->max_tx_sgl_size);
2018 }
2019
2020 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2021                                   uint16_t nb_pkts)
2022 {
2023         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2024         unsigned int ring_size = rx_ring->ring_size;
2025         unsigned int ring_mask = ring_size - 1;
2026         uint16_t next_to_clean = rx_ring->next_to_clean;
2027         uint16_t desc_in_use = 0;
2028         uint16_t req_id;
2029         unsigned int recv_idx = 0;
2030         struct rte_mbuf *mbuf = NULL;
2031         struct rte_mbuf *mbuf_head = NULL;
2032         struct rte_mbuf *mbuf_prev = NULL;
2033         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
2034         unsigned int completed;
2035
2036         struct ena_com_rx_ctx ena_rx_ctx;
2037         int rc = 0;
2038
2039         /* Check adapter state */
2040         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2041                 RTE_LOG(ALERT, PMD,
2042                         "Trying to receive pkts while device is NOT running\n");
2043                 return 0;
2044         }
2045
2046         desc_in_use = rx_ring->next_to_use - next_to_clean;
2047         if (unlikely(nb_pkts > desc_in_use))
2048                 nb_pkts = desc_in_use;
2049
2050         for (completed = 0; completed < nb_pkts; completed++) {
2051                 int segments = 0;
2052
2053                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2054                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2055                 ena_rx_ctx.descs = 0;
2056                 /* receive packet context */
2057                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2058                                     rx_ring->ena_com_io_sq,
2059                                     &ena_rx_ctx);
2060                 if (unlikely(rc)) {
2061                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
2062                         rx_ring->adapter->reset_reason =
2063                                 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2064                         rx_ring->adapter->trigger_reset = true;
2065                         return 0;
2066                 }
2067
2068                 if (unlikely(ena_rx_ctx.descs == 0))
2069                         break;
2070
2071                 while (segments < ena_rx_ctx.descs) {
2072                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
2073                         rc = validate_rx_req_id(rx_ring, req_id);
2074                         if (unlikely(rc)) {
2075                                 if (segments != 0)
2076                                         rte_mbuf_raw_free(mbuf_head);
2077                                 break;
2078                         }
2079
2080                         mbuf = rx_buff_info[req_id];
2081                         rx_buff_info[req_id] = NULL;
2082                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
2083                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2084                         mbuf->refcnt = 1;
2085                         mbuf->next = NULL;
2086                         if (unlikely(segments == 0)) {
2087                                 mbuf->nb_segs = ena_rx_ctx.descs;
2088                                 mbuf->port = rx_ring->port_id;
2089                                 mbuf->pkt_len = 0;
2090                                 mbuf_head = mbuf;
2091                         } else {
2092                                 /* for multi-segment pkts create mbuf chain */
2093                                 mbuf_prev->next = mbuf;
2094                         }
2095                         mbuf_head->pkt_len += mbuf->data_len;
2096
2097                         mbuf_prev = mbuf;
2098                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
2099                                 req_id;
2100                         segments++;
2101                         next_to_clean++;
2102                 }
2103                 if (unlikely(rc))
2104                         break;
2105
2106                 /* fill mbuf attributes if any */
2107                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
2108                 mbuf_head->hash.rss = ena_rx_ctx.hash;
2109
2110                 /* pass to DPDK application head mbuf */
2111                 rx_pkts[recv_idx] = mbuf_head;
2112                 recv_idx++;
2113         }
2114
2115         rx_ring->next_to_clean = next_to_clean;
2116
2117         desc_in_use = desc_in_use - completed + 1;
2118         /* Burst refill to save doorbells, memory barriers, const interval */
2119         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
2120                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
2121
2122         return recv_idx;
2123 }
2124
2125 static uint16_t
2126 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2127                 uint16_t nb_pkts)
2128 {
2129         int32_t ret;
2130         uint32_t i;
2131         struct rte_mbuf *m;
2132         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2133         struct ipv4_hdr *ip_hdr;
2134         uint64_t ol_flags;
2135         uint16_t frag_field;
2136
2137         for (i = 0; i != nb_pkts; i++) {
2138                 m = tx_pkts[i];
2139                 ol_flags = m->ol_flags;
2140
2141                 if (!(ol_flags & PKT_TX_IPV4))
2142                         continue;
2143
2144                 /* If there was not L2 header length specified, assume it is
2145                  * length of the ethernet header.
2146                  */
2147                 if (unlikely(m->l2_len == 0))
2148                         m->l2_len = sizeof(struct ether_hdr);
2149
2150                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
2151                                                  m->l2_len);
2152                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2153
2154                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
2155                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2156
2157                         /* If IPv4 header has DF flag enabled and TSO support is
2158                          * disabled, partial chcecksum should not be calculated.
2159                          */
2160                         if (!tx_ring->adapter->tso4_supported)
2161                                 continue;
2162                 }
2163
2164                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2165                                 (ol_flags & PKT_TX_L4_MASK) ==
2166                                 PKT_TX_SCTP_CKSUM) {
2167                         rte_errno = -ENOTSUP;
2168                         return i;
2169                 }
2170
2171 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2172                 ret = rte_validate_tx_offload(m);
2173                 if (ret != 0) {
2174                         rte_errno = ret;
2175                         return i;
2176                 }
2177 #endif
2178
2179                 /* In case we are supposed to TSO and have DF not set (DF=0)
2180                  * hardware must be provided with partial checksum, otherwise
2181                  * it will take care of necessary calculations.
2182                  */
2183
2184                 ret = rte_net_intel_cksum_flags_prepare(m,
2185                         ol_flags & ~PKT_TX_TCP_SEG);
2186                 if (ret != 0) {
2187                         rte_errno = ret;
2188                         return i;
2189                 }
2190         }
2191
2192         return i;
2193 }
2194
2195 static void ena_update_hints(struct ena_adapter *adapter,
2196                              struct ena_admin_ena_hw_hints *hints)
2197 {
2198         if (hints->admin_completion_tx_timeout)
2199                 adapter->ena_dev.admin_queue.completion_timeout =
2200                         hints->admin_completion_tx_timeout * 1000;
2201
2202         if (hints->mmio_read_timeout)
2203                 /* convert to usec */
2204                 adapter->ena_dev.mmio_read.reg_read_to =
2205                         hints->mmio_read_timeout * 1000;
2206
2207         if (hints->driver_watchdog_timeout) {
2208                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2209                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2210                 else
2211                         // Convert msecs to ticks
2212                         adapter->keep_alive_timeout =
2213                                 (hints->driver_watchdog_timeout *
2214                                 rte_get_timer_hz()) / 1000;
2215         }
2216 }
2217
2218 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2219                                         struct rte_mbuf *mbuf)
2220 {
2221         struct ena_com_dev *ena_dev;
2222         int num_segments, header_len, rc;
2223
2224         ena_dev = &tx_ring->adapter->ena_dev;
2225         num_segments = mbuf->nb_segs;
2226         header_len = mbuf->data_len;
2227
2228         if (likely(num_segments < tx_ring->sgl_size))
2229                 return 0;
2230
2231         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2232             (num_segments == tx_ring->sgl_size) &&
2233             (header_len < tx_ring->tx_max_header_size))
2234                 return 0;
2235
2236         rc = rte_pktmbuf_linearize(mbuf);
2237         if (unlikely(rc))
2238                 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
2239
2240         return rc;
2241 }
2242
2243 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2244                                   uint16_t nb_pkts)
2245 {
2246         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2247         uint16_t next_to_use = tx_ring->next_to_use;
2248         uint16_t next_to_clean = tx_ring->next_to_clean;
2249         struct rte_mbuf *mbuf;
2250         uint16_t seg_len;
2251         unsigned int ring_size = tx_ring->ring_size;
2252         unsigned int ring_mask = ring_size - 1;
2253         struct ena_com_tx_ctx ena_tx_ctx;
2254         struct ena_tx_buffer *tx_info;
2255         struct ena_com_buf *ebuf;
2256         uint16_t rc, req_id, total_tx_descs = 0;
2257         uint16_t sent_idx = 0, empty_tx_reqs;
2258         uint16_t push_len = 0;
2259         uint16_t delta = 0;
2260         int nb_hw_desc;
2261
2262         /* Check adapter state */
2263         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2264                 RTE_LOG(ALERT, PMD,
2265                         "Trying to xmit pkts while device is NOT running\n");
2266                 return 0;
2267         }
2268
2269         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2270         if (nb_pkts > empty_tx_reqs)
2271                 nb_pkts = empty_tx_reqs;
2272
2273         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2274                 mbuf = tx_pkts[sent_idx];
2275
2276                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2277                 if (unlikely(rc))
2278                         break;
2279
2280                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2281                 tx_info = &tx_ring->tx_buffer_info[req_id];
2282                 tx_info->mbuf = mbuf;
2283                 tx_info->num_of_bufs = 0;
2284                 ebuf = tx_info->bufs;
2285
2286                 /* Prepare TX context */
2287                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2288                 memset(&ena_tx_ctx.ena_meta, 0x0,
2289                        sizeof(struct ena_com_tx_meta));
2290                 ena_tx_ctx.ena_bufs = ebuf;
2291                 ena_tx_ctx.req_id = req_id;
2292
2293                 delta = 0;
2294                 seg_len = mbuf->data_len;
2295
2296                 if (tx_ring->tx_mem_queue_type ==
2297                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2298                         push_len = RTE_MIN(mbuf->pkt_len,
2299                                            tx_ring->tx_max_header_size);
2300                         ena_tx_ctx.header_len = push_len;
2301
2302                         if (likely(push_len <= seg_len)) {
2303                                 /* If the push header is in the single segment,
2304                                  * then just point it to the 1st mbuf data.
2305                                  */
2306                                 ena_tx_ctx.push_header =
2307                                         rte_pktmbuf_mtod(mbuf, uint8_t *);
2308                         } else {
2309                                 /* If the push header lays in the several
2310                                  * segments, copy it to the intermediate buffer.
2311                                  */
2312                                 rte_pktmbuf_read(mbuf, 0, push_len,
2313                                         tx_ring->push_buf_intermediate_buf);
2314                                 ena_tx_ctx.push_header =
2315                                         tx_ring->push_buf_intermediate_buf;
2316                                 delta = push_len - seg_len;
2317                         }
2318                 } /* there's no else as we take advantage of memset zeroing */
2319
2320                 /* Set TX offloads flags, if applicable */
2321                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2322
2323                 if (unlikely(mbuf->ol_flags &
2324                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2325                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2326
2327                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2328
2329                 /* Process first segment taking into
2330                  * consideration pushed header
2331                  */
2332                 if (seg_len > push_len) {
2333                         ebuf->paddr = mbuf->buf_iova +
2334                                       mbuf->data_off +
2335                                       push_len;
2336                         ebuf->len = seg_len - push_len;
2337                         ebuf++;
2338                         tx_info->num_of_bufs++;
2339                 }
2340
2341                 while ((mbuf = mbuf->next) != NULL) {
2342                         seg_len = mbuf->data_len;
2343
2344                         /* Skip mbufs if whole data is pushed as a header */
2345                         if (unlikely(delta > seg_len)) {
2346                                 delta -= seg_len;
2347                                 continue;
2348                         }
2349
2350                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2351                         ebuf->len = seg_len - delta;
2352                         ebuf++;
2353                         tx_info->num_of_bufs++;
2354
2355                         delta = 0;
2356                 }
2357
2358                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2359
2360                 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2361                                                &ena_tx_ctx)) {
2362                         RTE_LOG(DEBUG, PMD, "llq tx max burst size of queue %d"
2363                                 " achieved, writing doorbell to send burst\n",
2364                                 tx_ring->id);
2365                         rte_wmb();
2366                         ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2367                 }
2368
2369                 /* prepare the packet's descriptors to dma engine */
2370                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2371                                         &ena_tx_ctx, &nb_hw_desc);
2372                 if (unlikely(rc))
2373                         break;
2374
2375                 tx_info->tx_descs = nb_hw_desc;
2376
2377                 next_to_use++;
2378         }
2379
2380         /* If there are ready packets to be xmitted... */
2381         if (sent_idx > 0) {
2382                 /* ...let HW do its best :-) */
2383                 rte_wmb();
2384                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2385
2386                 tx_ring->next_to_use = next_to_use;
2387         }
2388
2389         /* Clear complete packets  */
2390         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2391                 rc = validate_tx_req_id(tx_ring, req_id);
2392                 if (rc)
2393                         break;
2394
2395                 /* Get Tx info & store how many descs were processed  */
2396                 tx_info = &tx_ring->tx_buffer_info[req_id];
2397                 total_tx_descs += tx_info->tx_descs;
2398
2399                 /* Free whole mbuf chain  */
2400                 mbuf = tx_info->mbuf;
2401                 rte_pktmbuf_free(mbuf);
2402                 tx_info->mbuf = NULL;
2403
2404                 /* Put back descriptor to the ring for reuse */
2405                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2406                 next_to_clean++;
2407
2408                 /* If too many descs to clean, leave it for another run */
2409                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2410                         break;
2411         }
2412
2413         if (total_tx_descs > 0) {
2414                 /* acknowledge completion of sent packets */
2415                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2416                 tx_ring->next_to_clean = next_to_clean;
2417         }
2418
2419         return sent_idx;
2420 }
2421
2422 /*********************************************************************
2423  *  PMD configuration
2424  *********************************************************************/
2425 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2426         struct rte_pci_device *pci_dev)
2427 {
2428         return rte_eth_dev_pci_generic_probe(pci_dev,
2429                 sizeof(struct ena_adapter), eth_ena_dev_init);
2430 }
2431
2432 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2433 {
2434         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2435 }
2436
2437 static struct rte_pci_driver rte_ena_pmd = {
2438         .id_table = pci_id_ena_map,
2439         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2440                      RTE_PCI_DRV_WC_ACTIVATE,
2441         .probe = eth_ena_pci_probe,
2442         .remove = eth_ena_pci_remove,
2443 };
2444
2445 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2446 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2447 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2448
2449 RTE_INIT(ena_init_log)
2450 {
2451         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2452         if (ena_logtype_init >= 0)
2453                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2454         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2455         if (ena_logtype_driver >= 0)
2456                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2457 }
2458
2459 /******************************************************************************
2460  ******************************** AENQ Handlers *******************************
2461  *****************************************************************************/
2462 static void ena_update_on_link_change(void *adapter_data,
2463                                       struct ena_admin_aenq_entry *aenq_e)
2464 {
2465         struct rte_eth_dev *eth_dev;
2466         struct ena_adapter *adapter;
2467         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2468         uint32_t status;
2469
2470         adapter = (struct ena_adapter *)adapter_data;
2471         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2472         eth_dev = adapter->rte_dev;
2473
2474         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2475         adapter->link_status = status;
2476
2477         ena_link_update(eth_dev, 0);
2478         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2479 }
2480
2481 static void ena_notification(void *data,
2482                              struct ena_admin_aenq_entry *aenq_e)
2483 {
2484         struct ena_adapter *adapter = (struct ena_adapter *)data;
2485         struct ena_admin_ena_hw_hints *hints;
2486
2487         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2488                 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2489                         aenq_e->aenq_common_desc.group,
2490                         ENA_ADMIN_NOTIFICATION);
2491
2492         switch (aenq_e->aenq_common_desc.syndrom) {
2493         case ENA_ADMIN_UPDATE_HINTS:
2494                 hints = (struct ena_admin_ena_hw_hints *)
2495                         (&aenq_e->inline_data_w4);
2496                 ena_update_hints(adapter, hints);
2497                 break;
2498         default:
2499                 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2500                         aenq_e->aenq_common_desc.syndrom);
2501         }
2502 }
2503
2504 static void ena_keep_alive(void *adapter_data,
2505                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2506 {
2507         struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2508
2509         adapter->timestamp_wd = rte_get_timer_cycles();
2510 }
2511
2512 /**
2513  * This handler will called for unknown event group or unimplemented handlers
2514  **/
2515 static void unimplemented_aenq_handler(__rte_unused void *data,
2516                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2517 {
2518         RTE_LOG(ERR, PMD, "Unknown event was received or event with "
2519                           "unimplemented handler\n");
2520 }
2521
2522 static struct ena_aenq_handlers aenq_handlers = {
2523         .handlers = {
2524                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2525                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2526                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2527         },
2528         .unimplemented_handler = unimplemented_aenq_handler
2529 };