drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_ether.h>
   8 #include <rte_ethdev_driver.h>
   9 #include <rte_ethdev_pci.h>
  10 #include <rte_tcp.h>
  11 #include <rte_atomic.h>
  12 #include <rte_dev.h>
  13 #include <rte_errno.h>
  14 #include <rte_version.h>
  15 #include <rte_net.h>
  16 #include <rte_kvargs.h>
  17
  18 #include "ena_ethdev.h"
  19 #include "ena_logs.h"
  20 #include "ena_platform.h"
  21 #include "ena_com.h"
  22 #include "ena_eth_com.h"
  23
  24 #include <ena_common_defs.h>
  25 #include <ena_regs_defs.h>
  26 #include <ena_admin_defs.h>
  27 #include <ena_eth_io_defs.h>
  28
  29 #define DRV_MODULE_VER_MAJOR    2
  30 #define DRV_MODULE_VER_MINOR    0
  31 #define DRV_MODULE_VER_SUBMINOR 3
  32
  33 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  34 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  35 /*reverse version of ENA_IO_RXQ_IDX*/
  36 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  37
  38 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  39 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  40
  41 #define GET_L4_HDR_LEN(mbuf)                                    \
  42         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  43                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  44
  45 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  46 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  47 #define ENA_HASH_KEY_SIZE       40
  48 #define ETH_GSTRING_LEN 32
  49
  50 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  51
  52 #define ENA_MIN_RING_DESC       128
  53
  54 enum ethtool_stringset {
  55         ETH_SS_TEST             = 0,
  56         ETH_SS_STATS,
  57 };
  58
  59 struct ena_stats {
  60         char name[ETH_GSTRING_LEN];
  61         int stat_offset;
  62 };
  63
  64 #define ENA_STAT_ENTRY(stat, stat_type) { \
  65         .name = #stat, \
  66         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  67 }
  68
  69 #define ENA_STAT_RX_ENTRY(stat) \
  70         ENA_STAT_ENTRY(stat, rx)
  71
  72 #define ENA_STAT_TX_ENTRY(stat) \
  73         ENA_STAT_ENTRY(stat, tx)
  74
  75 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  76         ENA_STAT_ENTRY(stat, dev)
  77
  78 /* Device arguments */
  79 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  80
  81 /*
  82  * Each rte_memzone should have unique name.
  83  * To satisfy it, count number of allocation and add it to name.
  84  */
  85 rte_atomic32_t ena_alloc_cnt;
  86
  87 static const struct ena_stats ena_stats_global_strings[] = {
  88         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  89         ENA_STAT_GLOBAL_ENTRY(dev_start),
  90         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  91         ENA_STAT_GLOBAL_ENTRY(tx_drops),
  92 };
  93
  94 static const struct ena_stats ena_stats_tx_strings[] = {
  95         ENA_STAT_TX_ENTRY(cnt),
  96         ENA_STAT_TX_ENTRY(bytes),
  97         ENA_STAT_TX_ENTRY(prepare_ctx_err),
  98         ENA_STAT_TX_ENTRY(linearize),
  99         ENA_STAT_TX_ENTRY(linearize_failed),
 100         ENA_STAT_TX_ENTRY(tx_poll),
 101         ENA_STAT_TX_ENTRY(doorbells),
 102         ENA_STAT_TX_ENTRY(bad_req_id),
 103         ENA_STAT_TX_ENTRY(available_desc),
 104 };
 105
 106 static const struct ena_stats ena_stats_rx_strings[] = {
 107         ENA_STAT_RX_ENTRY(cnt),
 108         ENA_STAT_RX_ENTRY(bytes),
 109         ENA_STAT_RX_ENTRY(refill_partial),
 110         ENA_STAT_RX_ENTRY(bad_csum),
 111         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 112         ENA_STAT_RX_ENTRY(bad_desc_num),
 113         ENA_STAT_RX_ENTRY(bad_req_id),
 114 };
 115
 116 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 117 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 118 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 119
 120 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 121                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 122                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 123                         DEV_TX_OFFLOAD_TCP_TSO)
 124 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 125                        PKT_TX_IP_CKSUM |\
 126                        PKT_TX_TCP_SEG)
 127
 128 /** Vendor ID used by Amazon devices */
 129 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 130 /** Amazon devices */
 131 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 132 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 133
 134 #define ENA_TX_OFFLOAD_MASK     (\
 135         PKT_TX_L4_MASK |         \
 136         PKT_TX_IPV6 |            \
 137         PKT_TX_IPV4 |            \
 138         PKT_TX_IP_CKSUM |        \
 139         PKT_TX_TCP_SEG)
 140
 141 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 142         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 143
 144 int ena_logtype_init;
 145 int ena_logtype_driver;
 146
 147 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
 148 int ena_logtype_rx;
 149 #endif
 150 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
 151 int ena_logtype_tx;
 152 #endif
 153 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
 154 int ena_logtype_tx_free;
 155 #endif
 156 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
 157 int ena_logtype_com;
 158 #endif
 159
 160 static const struct rte_pci_id pci_id_ena_map[] = {
 161         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 162         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 163         { .device_id = 0 },
 164 };
 165
 166 static struct ena_aenq_handlers aenq_handlers;
 167
 168 static int ena_device_init(struct ena_com_dev *ena_dev,
 169                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 170                            bool *wd_state);
 171 static int ena_dev_configure(struct rte_eth_dev *dev);
 172 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 173                                   uint16_t nb_pkts);
 174 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 175                 uint16_t nb_pkts);
 176 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 177                               uint16_t nb_desc, unsigned int socket_id,
 178                               const struct rte_eth_txconf *tx_conf);
 179 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 180                               uint16_t nb_desc, unsigned int socket_id,
 181                               const struct rte_eth_rxconf *rx_conf,
 182                               struct rte_mempool *mp);
 183 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
 184 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
 185                                     struct ena_com_rx_buf_info *ena_bufs,
 186                                     uint32_t descs,
 187                                     uint16_t *next_to_clean,
 188                                     uint8_t offset);
 189 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 190                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 191 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 192 static void ena_init_rings(struct ena_adapter *adapter,
 193                            bool disable_meta_caching);
 194 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 195 static int ena_start(struct rte_eth_dev *dev);
 196 static void ena_stop(struct rte_eth_dev *dev);
 197 static void ena_close(struct rte_eth_dev *dev);
 198 static int ena_dev_reset(struct rte_eth_dev *dev);
 199 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 200 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 201 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 202 static void ena_rx_queue_release(void *queue);
 203 static void ena_tx_queue_release(void *queue);
 204 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 205 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 206 static int ena_link_update(struct rte_eth_dev *dev,
 207                            int wait_to_complete);
 208 static int ena_create_io_queue(struct ena_ring *ring);
 209 static void ena_queue_stop(struct ena_ring *ring);
 210 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 211                               enum ena_ring_type ring_type);
 212 static int ena_queue_start(struct ena_ring *ring);
 213 static int ena_queue_start_all(struct rte_eth_dev *dev,
 214                                enum ena_ring_type ring_type);
 215 static void ena_stats_restart(struct rte_eth_dev *dev);
 216 static int ena_infos_get(struct rte_eth_dev *dev,
 217                          struct rte_eth_dev_info *dev_info);
 218 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 219                                struct rte_eth_rss_reta_entry64 *reta_conf,
 220                                uint16_t reta_size);
 221 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 222                               struct rte_eth_rss_reta_entry64 *reta_conf,
 223                               uint16_t reta_size);
 224 static void ena_interrupt_handler_rte(void *cb_arg);
 225 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 226 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 227 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 228 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 229                                 struct rte_eth_xstat_name *xstats_names,
 230                                 unsigned int n);
 231 static int ena_xstats_get(struct rte_eth_dev *dev,
 232                           struct rte_eth_xstat *stats,
 233                           unsigned int n);
 234 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 235                                 const uint64_t *ids,
 236                                 uint64_t *values,
 237                                 unsigned int n);
 238 static int ena_process_bool_devarg(const char *key,
 239                                    const char *value,
 240                                    void *opaque);
 241 static int ena_parse_devargs(struct ena_adapter *adapter,
 242                              struct rte_devargs *devargs);
 243
 244 static const struct eth_dev_ops ena_dev_ops = {
 245         .dev_configure        = ena_dev_configure,
 246         .dev_infos_get        = ena_infos_get,
 247         .rx_queue_setup       = ena_rx_queue_setup,
 248         .tx_queue_setup       = ena_tx_queue_setup,
 249         .dev_start            = ena_start,
 250         .dev_stop             = ena_stop,
 251         .link_update          = ena_link_update,
 252         .stats_get            = ena_stats_get,
 253         .xstats_get_names     = ena_xstats_get_names,
 254         .xstats_get           = ena_xstats_get,
 255         .xstats_get_by_id     = ena_xstats_get_by_id,
 256         .mtu_set              = ena_mtu_set,
 257         .rx_queue_release     = ena_rx_queue_release,
 258         .tx_queue_release     = ena_tx_queue_release,
 259         .dev_close            = ena_close,
 260         .dev_reset            = ena_dev_reset,
 261         .reta_update          = ena_rss_reta_update,
 262         .reta_query           = ena_rss_reta_query,
 263 };
 264
 265 void ena_rss_key_fill(void *key, size_t size)
 266 {
 267         static bool key_generated;
 268         static uint8_t default_key[ENA_HASH_KEY_SIZE];
 269         size_t i;
 270
 271         RTE_ASSERT(size <= ENA_HASH_KEY_SIZE);
 272
 273         if (!key_generated) {
 274                 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i)
 275                         default_key[i] = rte_rand() & 0xff;
 276                 key_generated = true;
 277         }
 278
 279         rte_memcpy(key, default_key, size);
 280 }
 281
 282 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 283                                        struct ena_com_rx_ctx *ena_rx_ctx)
 284 {
 285         uint64_t ol_flags = 0;
 286         uint32_t packet_type = 0;
 287
 288         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 289                 packet_type |= RTE_PTYPE_L4_TCP;
 290         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 291                 packet_type |= RTE_PTYPE_L4_UDP;
 292
 293         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 294                 packet_type |= RTE_PTYPE_L3_IPV4;
 295         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 296                 packet_type |= RTE_PTYPE_L3_IPV6;
 297
 298         if (!ena_rx_ctx->l4_csum_checked)
 299                 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 300         else
 301                 if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag)
 302                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
 303                 else
 304                         ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 305
 306         if (unlikely(ena_rx_ctx->l3_csum_err))
 307                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 308
 309         mbuf->ol_flags = ol_flags;
 310         mbuf->packet_type = packet_type;
 311 }
 312
 313 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 314                                        struct ena_com_tx_ctx *ena_tx_ctx,
 315                                        uint64_t queue_offloads,
 316                                        bool disable_meta_caching)
 317 {
 318         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 319
 320         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 321             (queue_offloads & QUEUE_OFFLOADS)) {
 322                 /* check if TSO is required */
 323                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 324                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 325                         ena_tx_ctx->tso_enable = true;
 326
 327                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 328                 }
 329
 330                 /* check if L3 checksum is needed */
 331                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 332                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 333                         ena_tx_ctx->l3_csum_enable = true;
 334
 335                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 336                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 337                 } else {
 338                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 339
 340                         /* set don't fragment (DF) flag */
 341                         if (mbuf->packet_type &
 342                                 (RTE_PTYPE_L4_NONFRAG
 343                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 344                                 ena_tx_ctx->df = true;
 345                 }
 346
 347                 /* check if L4 checksum is needed */
 348                 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
 349                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 350                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 351                         ena_tx_ctx->l4_csum_enable = true;
 352                 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
 353                                 PKT_TX_UDP_CKSUM) &&
 354                                 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 355                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 356                         ena_tx_ctx->l4_csum_enable = true;
 357                 } else {
 358                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 359                         ena_tx_ctx->l4_csum_enable = false;
 360                 }
 361
 362                 ena_meta->mss = mbuf->tso_segsz;
 363                 ena_meta->l3_hdr_len = mbuf->l3_len;
 364                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 365
 366                 ena_tx_ctx->meta_valid = true;
 367         } else if (disable_meta_caching) {
 368                 memset(ena_meta, 0, sizeof(*ena_meta));
 369                 ena_tx_ctx->meta_valid = true;
 370         } else {
 371                 ena_tx_ctx->meta_valid = false;
 372         }
 373 }
 374
 375 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 376 {
 377         if (likely(req_id < rx_ring->ring_size))
 378                 return 0;
 379
 380         PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id);
 381
 382         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 383         rx_ring->adapter->trigger_reset = true;
 384         ++rx_ring->rx_stats.bad_req_id;
 385
 386         return -EFAULT;
 387 }
 388
 389 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 390 {
 391         struct ena_tx_buffer *tx_info = NULL;
 392
 393         if (likely(req_id < tx_ring->ring_size)) {
 394                 tx_info = &tx_ring->tx_buffer_info[req_id];
 395                 if (likely(tx_info->mbuf))
 396                         return 0;
 397         }
 398
 399         if (tx_info)
 400                 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 401         else
 402                 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 403
 404         /* Trigger device reset */
 405         ++tx_ring->tx_stats.bad_req_id;
 406         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 407         tx_ring->adapter->trigger_reset = true;
 408         return -EFAULT;
 409 }
 410
 411 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 412 {
 413         struct ena_admin_host_info *host_info;
 414         int rc;
 415
 416         /* Allocate only the host info */
 417         rc = ena_com_allocate_host_info(ena_dev);
 418         if (rc) {
 419                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 420                 return;
 421         }
 422
 423         host_info = ena_dev->host_attr.host_info;
 424
 425         host_info->os_type = ENA_ADMIN_OS_DPDK;
 426         host_info->kernel_ver = RTE_VERSION;
 427         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 428                 sizeof(host_info->kernel_ver_str));
 429         host_info->os_dist = RTE_VERSION;
 430         strlcpy((char *)host_info->os_dist_str, rte_version(),
 431                 sizeof(host_info->os_dist_str));
 432         host_info->driver_version =
 433                 (DRV_MODULE_VER_MAJOR) |
 434                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 435                 (DRV_MODULE_VER_SUBMINOR <<
 436                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 437         host_info->num_cpus = rte_lcore_count();
 438
 439         host_info->driver_supported_features =
 440                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
 441
 442         rc = ena_com_set_host_attributes(ena_dev);
 443         if (rc) {
 444                 if (rc == -ENA_COM_UNSUPPORTED)
 445                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 446                 else
 447                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 448
 449                 goto err;
 450         }
 451
 452         return;
 453
 454 err:
 455         ena_com_delete_host_info(ena_dev);
 456 }
 457
 458 /* This function calculates the number of xstats based on the current config */
 459 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
 460 {
 461         return ENA_STATS_ARRAY_GLOBAL +
 462                 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 463                 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 464 }
 465
 466 static void ena_config_debug_area(struct ena_adapter *adapter)
 467 {
 468         u32 debug_area_size;
 469         int rc, ss_count;
 470
 471         ss_count = ena_xstats_calc_num(adapter->rte_dev);
 472
 473         /* allocate 32 bytes for each string and 64bit for the value */
 474         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 475
 476         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 477         if (rc) {
 478                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 479                 return;
 480         }
 481
 482         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 483         if (rc) {
 484                 if (rc == -ENA_COM_UNSUPPORTED)
 485                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 486                 else
 487                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 488
 489                 goto err;
 490         }
 491
 492         return;
 493 err:
 494         ena_com_delete_debug_area(&adapter->ena_dev);
 495 }
 496
 497 static void ena_close(struct rte_eth_dev *dev)
 498 {
 499         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 500         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 501         struct ena_adapter *adapter = dev->data->dev_private;
 502
 503         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 504                 ena_stop(dev);
 505         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 506
 507         ena_rx_queue_release_all(dev);
 508         ena_tx_queue_release_all(dev);
 509
 510         rte_free(adapter->drv_stats);
 511         adapter->drv_stats = NULL;
 512
 513         rte_intr_disable(intr_handle);
 514         rte_intr_callback_unregister(intr_handle,
 515                                      ena_interrupt_handler_rte,
 516                                      adapter);
 517
 518         /*
 519          * MAC is not allocated dynamically. Setting NULL should prevent from
 520          * release of the resource in the rte_eth_dev_release_port().
 521          */
 522         dev->data->mac_addrs = NULL;
 523 }
 524
 525 static int
 526 ena_dev_reset(struct rte_eth_dev *dev)
 527 {
 528         int rc = 0;
 529
 530         ena_destroy_device(dev);
 531         rc = eth_ena_dev_init(dev);
 532         if (rc)
 533                 PMD_INIT_LOG(CRIT, "Cannot initialize device");
 534
 535         return rc;
 536 }
 537
 538 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 539                                struct rte_eth_rss_reta_entry64 *reta_conf,
 540                                uint16_t reta_size)
 541 {
 542         struct ena_adapter *adapter = dev->data->dev_private;
 543         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 544         int rc, i;
 545         u16 entry_value;
 546         int conf_idx;
 547         int idx;
 548
 549         if ((reta_size == 0) || (reta_conf == NULL))
 550                 return -EINVAL;
 551
 552         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 553                 PMD_DRV_LOG(WARNING,
 554                         "indirection table %d is bigger than supported (%d)\n",
 555                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 556                 return -EINVAL;
 557         }
 558
 559         for (i = 0 ; i < reta_size ; i++) {
 560                 /* each reta_conf is for 64 entries.
 561                  * to support 128 we use 2 conf of 64
 562                  */
 563                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 564                 idx = i % RTE_RETA_GROUP_SIZE;
 565                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 566                         entry_value =
 567                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 568
 569                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 570                                                                i,
 571                                                                entry_value);
 572                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 573                                 PMD_DRV_LOG(ERR,
 574                                         "Cannot fill indirect table\n");
 575                                 return rc;
 576                         }
 577                 }
 578         }
 579
 580         rc = ena_com_indirect_table_set(ena_dev);
 581         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 582                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 583                 return rc;
 584         }
 585
 586         PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries  for port %d\n",
 587                 __func__, reta_size, adapter->rte_dev->data->port_id);
 588
 589         return 0;
 590 }
 591
 592 /* Query redirection table. */
 593 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 594                               struct rte_eth_rss_reta_entry64 *reta_conf,
 595                               uint16_t reta_size)
 596 {
 597         struct ena_adapter *adapter = dev->data->dev_private;
 598         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 599         int rc;
 600         int i;
 601         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 602         int reta_conf_idx;
 603         int reta_idx;
 604
 605         if (reta_size == 0 || reta_conf == NULL ||
 606             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 607                 return -EINVAL;
 608
 609         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 610         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 611                 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
 612                 return -ENOTSUP;
 613         }
 614
 615         for (i = 0 ; i < reta_size ; i++) {
 616                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 617                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 618                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 619                         reta_conf[reta_conf_idx].reta[reta_idx] =
 620                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 621         }
 622
 623         return 0;
 624 }
 625
 626 static int ena_rss_init_default(struct ena_adapter *adapter)
 627 {
 628         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 629         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 630         int rc, i;
 631         u32 val;
 632
 633         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 634         if (unlikely(rc)) {
 635                 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
 636                 goto err_rss_init;
 637         }
 638
 639         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 640                 val = i % nb_rx_queues;
 641                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 642                                                        ENA_IO_RXQ_IDX(val));
 643                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 644                         PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
 645                         goto err_fill_indir;
 646                 }
 647         }
 648
 649         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 650                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 651         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 652                 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
 653                 goto err_fill_indir;
 654         }
 655
 656         rc = ena_com_set_default_hash_ctrl(ena_dev);
 657         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 658                 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
 659                 goto err_fill_indir;
 660         }
 661
 662         rc = ena_com_indirect_table_set(ena_dev);
 663         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 664                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 665                 goto err_fill_indir;
 666         }
 667         PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
 668                 adapter->rte_dev->data->port_id);
 669
 670         return 0;
 671
 672 err_fill_indir:
 673         ena_com_rss_destroy(ena_dev);
 674 err_rss_init:
 675
 676         return rc;
 677 }
 678
 679 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 680 {
 681         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 682         int nb_queues = dev->data->nb_rx_queues;
 683         int i;
 684
 685         for (i = 0; i < nb_queues; i++)
 686                 ena_rx_queue_release(queues[i]);
 687 }
 688
 689 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 690 {
 691         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 692         int nb_queues = dev->data->nb_tx_queues;
 693         int i;
 694
 695         for (i = 0; i < nb_queues; i++)
 696                 ena_tx_queue_release(queues[i]);
 697 }
 698
 699 static void ena_rx_queue_release(void *queue)
 700 {
 701         struct ena_ring *ring = (struct ena_ring *)queue;
 702
 703         /* Free ring resources */
 704         if (ring->rx_buffer_info)
 705                 rte_free(ring->rx_buffer_info);
 706         ring->rx_buffer_info = NULL;
 707
 708         if (ring->rx_refill_buffer)
 709                 rte_free(ring->rx_refill_buffer);
 710         ring->rx_refill_buffer = NULL;
 711
 712         if (ring->empty_rx_reqs)
 713                 rte_free(ring->empty_rx_reqs);
 714         ring->empty_rx_reqs = NULL;
 715
 716         ring->configured = 0;
 717
 718         PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
 719                 ring->port_id, ring->id);
 720 }
 721
 722 static void ena_tx_queue_release(void *queue)
 723 {
 724         struct ena_ring *ring = (struct ena_ring *)queue;
 725
 726         /* Free ring resources */
 727         if (ring->push_buf_intermediate_buf)
 728                 rte_free(ring->push_buf_intermediate_buf);
 729
 730         if (ring->tx_buffer_info)
 731                 rte_free(ring->tx_buffer_info);
 732
 733         if (ring->empty_tx_reqs)
 734                 rte_free(ring->empty_tx_reqs);
 735
 736         ring->empty_tx_reqs = NULL;
 737         ring->tx_buffer_info = NULL;
 738         ring->push_buf_intermediate_buf = NULL;
 739
 740         ring->configured = 0;
 741
 742         PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
 743                 ring->port_id, ring->id);
 744 }
 745
 746 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 747 {
 748         unsigned int i;
 749
 750         for (i = 0; i < ring->ring_size; ++i) {
 751                 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
 752                 if (rx_info->mbuf) {
 753                         rte_mbuf_raw_free(rx_info->mbuf);
 754                         rx_info->mbuf = NULL;
 755                 }
 756         }
 757 }
 758
 759 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 760 {
 761         unsigned int i;
 762
 763         for (i = 0; i < ring->ring_size; ++i) {
 764                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 765
 766                 if (tx_buf->mbuf)
 767                         rte_pktmbuf_free(tx_buf->mbuf);
 768         }
 769 }
 770
 771 static int ena_link_update(struct rte_eth_dev *dev,
 772                            __rte_unused int wait_to_complete)
 773 {
 774         struct rte_eth_link *link = &dev->data->dev_link;
 775         struct ena_adapter *adapter = dev->data->dev_private;
 776
 777         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 778         link->link_speed = ETH_SPEED_NUM_NONE;
 779         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 780
 781         return 0;
 782 }
 783
 784 static int ena_queue_start_all(struct rte_eth_dev *dev,
 785                                enum ena_ring_type ring_type)
 786 {
 787         struct ena_adapter *adapter = dev->data->dev_private;
 788         struct ena_ring *queues = NULL;
 789         int nb_queues;
 790         int i = 0;
 791         int rc = 0;
 792
 793         if (ring_type == ENA_RING_TYPE_RX) {
 794                 queues = adapter->rx_ring;
 795                 nb_queues = dev->data->nb_rx_queues;
 796         } else {
 797                 queues = adapter->tx_ring;
 798                 nb_queues = dev->data->nb_tx_queues;
 799         }
 800         for (i = 0; i < nb_queues; i++) {
 801                 if (queues[i].configured) {
 802                         if (ring_type == ENA_RING_TYPE_RX) {
 803                                 ena_assert_msg(
 804                                         dev->data->rx_queues[i] == &queues[i],
 805                                         "Inconsistent state of rx queues\n");
 806                         } else {
 807                                 ena_assert_msg(
 808                                         dev->data->tx_queues[i] == &queues[i],
 809                                         "Inconsistent state of tx queues\n");
 810                         }
 811
 812                         rc = ena_queue_start(&queues[i]);
 813
 814                         if (rc) {
 815                                 PMD_INIT_LOG(ERR,
 816                                              "failed to start queue %d type(%d)",
 817                                              i, ring_type);
 818                                 goto err;
 819                         }
 820                 }
 821         }
 822
 823         return 0;
 824
 825 err:
 826         while (i--)
 827                 if (queues[i].configured)
 828                         ena_queue_stop(&queues[i]);
 829
 830         return rc;
 831 }
 832
 833 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 834 {
 835         uint32_t max_frame_len = adapter->max_mtu;
 836
 837         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 838             DEV_RX_OFFLOAD_JUMBO_FRAME)
 839                 max_frame_len =
 840                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 841
 842         return max_frame_len;
 843 }
 844
 845 static int ena_check_valid_conf(struct ena_adapter *adapter)
 846 {
 847         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 848
 849         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 850                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 851                                   "max mtu: %d, min mtu: %d",
 852                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 853                 return ENA_COM_UNSUPPORTED;
 854         }
 855
 856         return 0;
 857 }
 858
 859 static int
 860 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 861                        bool use_large_llq_hdr)
 862 {
 863         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 864         struct ena_com_dev *ena_dev = ctx->ena_dev;
 865         uint32_t max_tx_queue_size;
 866         uint32_t max_rx_queue_size;
 867
 868         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 869                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 870                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 871                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 872                         max_queue_ext->max_rx_sq_depth);
 873                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
 874
 875                 if (ena_dev->tx_mem_queue_type ==
 876                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 877                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 878                                 llq->max_llq_depth);
 879                 } else {
 880                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 881                                 max_queue_ext->max_tx_sq_depth);
 882                 }
 883
 884                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 885                         max_queue_ext->max_per_packet_rx_descs);
 886                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 887                         max_queue_ext->max_per_packet_tx_descs);
 888         } else {
 889                 struct ena_admin_queue_feature_desc *max_queues =
 890                         &ctx->get_feat_ctx->max_queues;
 891                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
 892                         max_queues->max_sq_depth);
 893                 max_tx_queue_size = max_queues->max_cq_depth;
 894
 895                 if (ena_dev->tx_mem_queue_type ==
 896                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 897                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 898                                 llq->max_llq_depth);
 899                 } else {
 900                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 901                                 max_queues->max_sq_depth);
 902                 }
 903
 904                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 905                         max_queues->max_packet_rx_descs);
 906                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 907                         max_queues->max_packet_tx_descs);
 908         }
 909
 910         /* Round down to the nearest power of 2 */
 911         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
 912         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
 913
 914         if (use_large_llq_hdr) {
 915                 if ((llq->entry_size_ctrl_supported &
 916                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
 917                     (ena_dev->tx_mem_queue_type ==
 918                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
 919                         max_tx_queue_size /= 2;
 920                         PMD_INIT_LOG(INFO,
 921                                 "Forcing large headers and decreasing maximum TX queue size to %d\n",
 922                                 max_tx_queue_size);
 923                 } else {
 924                         PMD_INIT_LOG(ERR,
 925                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
 926                 }
 927         }
 928
 929         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
 930                 PMD_INIT_LOG(ERR, "Invalid queue size");
 931                 return -EFAULT;
 932         }
 933
 934         ctx->max_tx_queue_size = max_tx_queue_size;
 935         ctx->max_rx_queue_size = max_rx_queue_size;
 936
 937         return 0;
 938 }
 939
 940 static void ena_stats_restart(struct rte_eth_dev *dev)
 941 {
 942         struct ena_adapter *adapter = dev->data->dev_private;
 943
 944         rte_atomic64_init(&adapter->drv_stats->ierrors);
 945         rte_atomic64_init(&adapter->drv_stats->oerrors);
 946         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 947         adapter->drv_stats->rx_drops = 0;
 948 }
 949
 950 static int ena_stats_get(struct rte_eth_dev *dev,
 951                           struct rte_eth_stats *stats)
 952 {
 953         struct ena_admin_basic_stats ena_stats;
 954         struct ena_adapter *adapter = dev->data->dev_private;
 955         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 956         int rc;
 957         int i;
 958         int max_rings_stats;
 959
 960         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 961                 return -ENOTSUP;
 962
 963         memset(&ena_stats, 0, sizeof(ena_stats));
 964         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 965         if (unlikely(rc)) {
 966                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 967                 return rc;
 968         }
 969
 970         /* Set of basic statistics from ENA */
 971         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 972                                           ena_stats.rx_pkts_low);
 973         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 974                                           ena_stats.tx_pkts_low);
 975         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 976                                         ena_stats.rx_bytes_low);
 977         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 978                                         ena_stats.tx_bytes_low);
 979
 980         /* Driver related stats */
 981         stats->imissed = adapter->drv_stats->rx_drops;
 982         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 983         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 984         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 985
 986         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
 987                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 988         for (i = 0; i < max_rings_stats; ++i) {
 989                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
 990
 991                 stats->q_ibytes[i] = rx_stats->bytes;
 992                 stats->q_ipackets[i] = rx_stats->cnt;
 993                 stats->q_errors[i] = rx_stats->bad_desc_num +
 994                         rx_stats->bad_req_id;
 995         }
 996
 997         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
 998                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 999         for (i = 0; i < max_rings_stats; ++i) {
1000                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1001
1002                 stats->q_obytes[i] = tx_stats->bytes;
1003                 stats->q_opackets[i] = tx_stats->cnt;
1004         }
1005
1006         return 0;
1007 }
1008
1009 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1010 {
1011         struct ena_adapter *adapter;
1012         struct ena_com_dev *ena_dev;
1013         int rc = 0;
1014
1015         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1016         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1017         adapter = dev->data->dev_private;
1018
1019         ena_dev = &adapter->ena_dev;
1020         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1021
1022         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1023                 PMD_DRV_LOG(ERR,
1024                         "Invalid MTU setting. new_mtu: %d "
1025                         "max mtu: %d min mtu: %d\n",
1026                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1027                 return -EINVAL;
1028         }
1029
1030         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1031         if (rc)
1032                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1033         else
1034                 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
1035
1036         return rc;
1037 }
1038
1039 static int ena_start(struct rte_eth_dev *dev)
1040 {
1041         struct ena_adapter *adapter = dev->data->dev_private;
1042         uint64_t ticks;
1043         int rc = 0;
1044
1045         rc = ena_check_valid_conf(adapter);
1046         if (rc)
1047                 return rc;
1048
1049         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1050         if (rc)
1051                 return rc;
1052
1053         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1054         if (rc)
1055                 goto err_start_tx;
1056
1057         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1058             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1059                 rc = ena_rss_init_default(adapter);
1060                 if (rc)
1061                         goto err_rss_init;
1062         }
1063
1064         ena_stats_restart(dev);
1065
1066         adapter->timestamp_wd = rte_get_timer_cycles();
1067         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1068
1069         ticks = rte_get_timer_hz();
1070         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1071                         ena_timer_wd_callback, adapter);
1072
1073         ++adapter->dev_stats.dev_start;
1074         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1075
1076         return 0;
1077
1078 err_rss_init:
1079         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1080 err_start_tx:
1081         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1082         return rc;
1083 }
1084
1085 static void ena_stop(struct rte_eth_dev *dev)
1086 {
1087         struct ena_adapter *adapter = dev->data->dev_private;
1088         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1089         int rc;
1090
1091         rte_timer_stop_sync(&adapter->timer_wd);
1092         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1093         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1094
1095         if (adapter->trigger_reset) {
1096                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1097                 if (rc)
1098                         PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1099         }
1100
1101         ++adapter->dev_stats.dev_stop;
1102         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1103 }
1104
1105 static int ena_create_io_queue(struct ena_ring *ring)
1106 {
1107         struct ena_adapter *adapter;
1108         struct ena_com_dev *ena_dev;
1109         struct ena_com_create_io_ctx ctx =
1110                 /* policy set to _HOST just to satisfy icc compiler */
1111                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1112                   0, 0, 0, 0, 0 };
1113         uint16_t ena_qid;
1114         unsigned int i;
1115         int rc;
1116
1117         adapter = ring->adapter;
1118         ena_dev = &adapter->ena_dev;
1119
1120         if (ring->type == ENA_RING_TYPE_TX) {
1121                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1122                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1123                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1124                 for (i = 0; i < ring->ring_size; i++)
1125                         ring->empty_tx_reqs[i] = i;
1126         } else {
1127                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1128                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1129                 for (i = 0; i < ring->ring_size; i++)
1130                         ring->empty_rx_reqs[i] = i;
1131         }
1132         ctx.queue_size = ring->ring_size;
1133         ctx.qid = ena_qid;
1134         ctx.msix_vector = -1; /* interrupts not used */
1135         ctx.numa_node = ring->numa_socket_id;
1136
1137         rc = ena_com_create_io_queue(ena_dev, &ctx);
1138         if (rc) {
1139                 PMD_DRV_LOG(ERR,
1140                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1141                         ring->id, ena_qid, rc);
1142                 return rc;
1143         }
1144
1145         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1146                                      &ring->ena_com_io_sq,
1147                                      &ring->ena_com_io_cq);
1148         if (rc) {
1149                 PMD_DRV_LOG(ERR,
1150                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1151                         ring->id, rc);
1152                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1153                 return rc;
1154         }
1155
1156         if (ring->type == ENA_RING_TYPE_TX)
1157                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1158
1159         return 0;
1160 }
1161
1162 static void ena_queue_stop(struct ena_ring *ring)
1163 {
1164         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1165
1166         if (ring->type == ENA_RING_TYPE_RX) {
1167                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1168                 ena_rx_queue_release_bufs(ring);
1169         } else {
1170                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1171                 ena_tx_queue_release_bufs(ring);
1172         }
1173 }
1174
1175 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1176                               enum ena_ring_type ring_type)
1177 {
1178         struct ena_adapter *adapter = dev->data->dev_private;
1179         struct ena_ring *queues = NULL;
1180         uint16_t nb_queues, i;
1181
1182         if (ring_type == ENA_RING_TYPE_RX) {
1183                 queues = adapter->rx_ring;
1184                 nb_queues = dev->data->nb_rx_queues;
1185         } else {
1186                 queues = adapter->tx_ring;
1187                 nb_queues = dev->data->nb_tx_queues;
1188         }
1189
1190         for (i = 0; i < nb_queues; ++i)
1191                 if (queues[i].configured)
1192                         ena_queue_stop(&queues[i]);
1193 }
1194
1195 static int ena_queue_start(struct ena_ring *ring)
1196 {
1197         int rc, bufs_num;
1198
1199         ena_assert_msg(ring->configured == 1,
1200                        "Trying to start unconfigured queue\n");
1201
1202         rc = ena_create_io_queue(ring);
1203         if (rc) {
1204                 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1205                 return rc;
1206         }
1207
1208         ring->next_to_clean = 0;
1209         ring->next_to_use = 0;
1210
1211         if (ring->type == ENA_RING_TYPE_TX) {
1212                 ring->tx_stats.available_desc =
1213                         ena_com_free_q_entries(ring->ena_com_io_sq);
1214                 return 0;
1215         }
1216
1217         bufs_num = ring->ring_size - 1;
1218         rc = ena_populate_rx_queue(ring, bufs_num);
1219         if (rc != bufs_num) {
1220                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1221                                          ENA_IO_RXQ_IDX(ring->id));
1222                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1223                 return ENA_COM_FAULT;
1224         }
1225
1226         return 0;
1227 }
1228
1229 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1230                               uint16_t queue_idx,
1231                               uint16_t nb_desc,
1232                               unsigned int socket_id,
1233                               const struct rte_eth_txconf *tx_conf)
1234 {
1235         struct ena_ring *txq = NULL;
1236         struct ena_adapter *adapter = dev->data->dev_private;
1237         unsigned int i;
1238
1239         txq = &adapter->tx_ring[queue_idx];
1240
1241         if (txq->configured) {
1242                 PMD_DRV_LOG(CRIT,
1243                         "API violation. Queue %d is already configured\n",
1244                         queue_idx);
1245                 return ENA_COM_FAULT;
1246         }
1247
1248         if (!rte_is_power_of_2(nb_desc)) {
1249                 PMD_DRV_LOG(ERR,
1250                         "Unsupported size of TX queue: %d is not a power of 2.\n",
1251                         nb_desc);
1252                 return -EINVAL;
1253         }
1254
1255         if (nb_desc > adapter->max_tx_ring_size) {
1256                 PMD_DRV_LOG(ERR,
1257                         "Unsupported size of TX queue (max size: %d)\n",
1258                         adapter->max_tx_ring_size);
1259                 return -EINVAL;
1260         }
1261
1262         if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1263                 nb_desc = adapter->max_tx_ring_size;
1264
1265         txq->port_id = dev->data->port_id;
1266         txq->next_to_clean = 0;
1267         txq->next_to_use = 0;
1268         txq->ring_size = nb_desc;
1269         txq->numa_socket_id = socket_id;
1270
1271         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1272                                           sizeof(struct ena_tx_buffer) *
1273                                           txq->ring_size,
1274                                           RTE_CACHE_LINE_SIZE);
1275         if (!txq->tx_buffer_info) {
1276                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1277                 return -ENOMEM;
1278         }
1279
1280         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1281                                          sizeof(u16) * txq->ring_size,
1282                                          RTE_CACHE_LINE_SIZE);
1283         if (!txq->empty_tx_reqs) {
1284                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1285                 rte_free(txq->tx_buffer_info);
1286                 return -ENOMEM;
1287         }
1288
1289         txq->push_buf_intermediate_buf =
1290                 rte_zmalloc("txq->push_buf_intermediate_buf",
1291                             txq->tx_max_header_size,
1292                             RTE_CACHE_LINE_SIZE);
1293         if (!txq->push_buf_intermediate_buf) {
1294                 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1295                 rte_free(txq->tx_buffer_info);
1296                 rte_free(txq->empty_tx_reqs);
1297                 return -ENOMEM;
1298         }
1299
1300         for (i = 0; i < txq->ring_size; i++)
1301                 txq->empty_tx_reqs[i] = i;
1302
1303         if (tx_conf != NULL) {
1304                 txq->offloads =
1305                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1306         }
1307         /* Store pointer to this queue in upper layer */
1308         txq->configured = 1;
1309         dev->data->tx_queues[queue_idx] = txq;
1310
1311         return 0;
1312 }
1313
1314 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1315                               uint16_t queue_idx,
1316                               uint16_t nb_desc,
1317                               unsigned int socket_id,
1318                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1319                               struct rte_mempool *mp)
1320 {
1321         struct ena_adapter *adapter = dev->data->dev_private;
1322         struct ena_ring *rxq = NULL;
1323         size_t buffer_size;
1324         int i;
1325
1326         rxq = &adapter->rx_ring[queue_idx];
1327         if (rxq->configured) {
1328                 PMD_DRV_LOG(CRIT,
1329                         "API violation. Queue %d is already configured\n",
1330                         queue_idx);
1331                 return ENA_COM_FAULT;
1332         }
1333
1334         if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1335                 nb_desc = adapter->max_rx_ring_size;
1336
1337         if (!rte_is_power_of_2(nb_desc)) {
1338                 PMD_DRV_LOG(ERR,
1339                         "Unsupported size of RX queue: %d is not a power of 2.\n",
1340                         nb_desc);
1341                 return -EINVAL;
1342         }
1343
1344         if (nb_desc > adapter->max_rx_ring_size) {
1345                 PMD_DRV_LOG(ERR,
1346                         "Unsupported size of RX queue (max size: %d)\n",
1347                         adapter->max_rx_ring_size);
1348                 return -EINVAL;
1349         }
1350
1351         /* ENA isn't supporting buffers smaller than 1400 bytes */
1352         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1353         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1354                 PMD_DRV_LOG(ERR,
1355                         "Unsupported size of RX buffer: %zu (min size: %d)\n",
1356                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1357                 return -EINVAL;
1358         }
1359
1360         rxq->port_id = dev->data->port_id;
1361         rxq->next_to_clean = 0;
1362         rxq->next_to_use = 0;
1363         rxq->ring_size = nb_desc;
1364         rxq->numa_socket_id = socket_id;
1365         rxq->mb_pool = mp;
1366
1367         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1368                 sizeof(struct ena_rx_buffer) * nb_desc,
1369                 RTE_CACHE_LINE_SIZE);
1370         if (!rxq->rx_buffer_info) {
1371                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1372                 return -ENOMEM;
1373         }
1374
1375         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1376                                             sizeof(struct rte_mbuf *) * nb_desc,
1377                                             RTE_CACHE_LINE_SIZE);
1378
1379         if (!rxq->rx_refill_buffer) {
1380                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1381                 rte_free(rxq->rx_buffer_info);
1382                 rxq->rx_buffer_info = NULL;
1383                 return -ENOMEM;
1384         }
1385
1386         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1387                                          sizeof(uint16_t) * nb_desc,
1388                                          RTE_CACHE_LINE_SIZE);
1389         if (!rxq->empty_rx_reqs) {
1390                 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1391                 rte_free(rxq->rx_buffer_info);
1392                 rxq->rx_buffer_info = NULL;
1393                 rte_free(rxq->rx_refill_buffer);
1394                 rxq->rx_refill_buffer = NULL;
1395                 return -ENOMEM;
1396         }
1397
1398         for (i = 0; i < nb_desc; i++)
1399                 rxq->empty_rx_reqs[i] = i;
1400
1401         /* Store pointer to this queue in upper layer */
1402         rxq->configured = 1;
1403         dev->data->rx_queues[queue_idx] = rxq;
1404
1405         return 0;
1406 }
1407
1408 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1409 {
1410         unsigned int i;
1411         int rc;
1412         uint16_t ring_size = rxq->ring_size;
1413         uint16_t ring_mask = ring_size - 1;
1414         uint16_t next_to_use = rxq->next_to_use;
1415         uint16_t in_use, req_id;
1416         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1417
1418         if (unlikely(!count))
1419                 return 0;
1420
1421         in_use = ring_size - ena_com_free_q_entries(rxq->ena_com_io_sq) - 1;
1422
1423         ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n");
1424
1425         /* get resources for incoming packets */
1426         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1427         if (unlikely(rc < 0)) {
1428                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1429                 ++rxq->rx_stats.mbuf_alloc_fail;
1430                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1431                 return 0;
1432         }
1433
1434         for (i = 0; i < count; i++) {
1435                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1436                 struct rte_mbuf *mbuf = mbufs[i];
1437                 struct ena_com_buf ebuf;
1438                 struct ena_rx_buffer *rx_info;
1439
1440                 if (likely((i + 4) < count))
1441                         rte_prefetch0(mbufs[i + 4]);
1442
1443                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1444                 rc = validate_rx_req_id(rxq, req_id);
1445                 if (unlikely(rc))
1446                         break;
1447
1448                 rx_info = &rxq->rx_buffer_info[req_id];
1449
1450                 /* prepare physical address for DMA transaction */
1451                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1452                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1453                 /* pass resource to device */
1454                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1455                                                 &ebuf, req_id);
1456                 if (unlikely(rc)) {
1457                         PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1458                         break;
1459                 }
1460                 rx_info->mbuf = mbuf;
1461                 next_to_use++;
1462         }
1463
1464         if (unlikely(i < count)) {
1465                 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1466                         "buffers (from %d)\n", rxq->id, i, count);
1467                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1468                                      count - i);
1469                 ++rxq->rx_stats.refill_partial;
1470         }
1471
1472         /* When we submitted free recources to device... */
1473         if (likely(i > 0)) {
1474                 /* ...let HW know that it can fill buffers with data. */
1475                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1476
1477                 rxq->next_to_use = next_to_use;
1478         }
1479
1480         return i;
1481 }
1482
1483 static int ena_device_init(struct ena_com_dev *ena_dev,
1484                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1485                            bool *wd_state)
1486 {
1487         uint32_t aenq_groups;
1488         int rc;
1489         bool readless_supported;
1490
1491         /* Initialize mmio registers */
1492         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1493         if (rc) {
1494                 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1495                 return rc;
1496         }
1497
1498         /* The PCIe configuration space revision id indicate if mmio reg
1499          * read is disabled.
1500          */
1501         readless_supported =
1502                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1503                                & ENA_MMIO_DISABLE_REG_READ);
1504         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1505
1506         /* reset device */
1507         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1508         if (rc) {
1509                 PMD_DRV_LOG(ERR, "cannot reset device\n");
1510                 goto err_mmio_read_less;
1511         }
1512
1513         /* check FW version */
1514         rc = ena_com_validate_version(ena_dev);
1515         if (rc) {
1516                 PMD_DRV_LOG(ERR, "device version is too low\n");
1517                 goto err_mmio_read_less;
1518         }
1519
1520         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1521
1522         /* ENA device administration layer init */
1523         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1524         if (rc) {
1525                 PMD_DRV_LOG(ERR,
1526                         "cannot initialize ena admin queue with device\n");
1527                 goto err_mmio_read_less;
1528         }
1529
1530         /* To enable the msix interrupts the driver needs to know the number
1531          * of queues. So the driver uses polling mode to retrieve this
1532          * information.
1533          */
1534         ena_com_set_admin_polling_mode(ena_dev, true);
1535
1536         ena_config_host_info(ena_dev);
1537
1538         /* Get Device Attributes and features */
1539         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1540         if (rc) {
1541                 PMD_DRV_LOG(ERR,
1542                         "cannot get attribute for ena device rc= %d\n", rc);
1543                 goto err_admin_init;
1544         }
1545
1546         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1547                       BIT(ENA_ADMIN_NOTIFICATION) |
1548                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1549                       BIT(ENA_ADMIN_FATAL_ERROR) |
1550                       BIT(ENA_ADMIN_WARNING);
1551
1552         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1553         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1554         if (rc) {
1555                 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1556                 goto err_admin_init;
1557         }
1558
1559         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1560
1561         return 0;
1562
1563 err_admin_init:
1564         ena_com_admin_destroy(ena_dev);
1565
1566 err_mmio_read_less:
1567         ena_com_mmio_reg_read_request_destroy(ena_dev);
1568
1569         return rc;
1570 }
1571
1572 static void ena_interrupt_handler_rte(void *cb_arg)
1573 {
1574         struct ena_adapter *adapter = cb_arg;
1575         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1576
1577         ena_com_admin_q_comp_intr_handler(ena_dev);
1578         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1579                 ena_com_aenq_intr_handler(ena_dev, adapter);
1580 }
1581
1582 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1583 {
1584         if (!adapter->wd_state)
1585                 return;
1586
1587         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1588                 return;
1589
1590         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1591             adapter->keep_alive_timeout)) {
1592                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1593                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1594                 adapter->trigger_reset = true;
1595                 ++adapter->dev_stats.wd_expired;
1596         }
1597 }
1598
1599 /* Check if admin queue is enabled */
1600 static void check_for_admin_com_state(struct ena_adapter *adapter)
1601 {
1602         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1603                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1604                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1605                 adapter->trigger_reset = true;
1606         }
1607 }
1608
1609 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1610                                   void *arg)
1611 {
1612         struct ena_adapter *adapter = arg;
1613         struct rte_eth_dev *dev = adapter->rte_dev;
1614
1615         check_for_missing_keep_alive(adapter);
1616         check_for_admin_com_state(adapter);
1617
1618         if (unlikely(adapter->trigger_reset)) {
1619                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1620                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1621                         NULL);
1622         }
1623 }
1624
1625 static inline void
1626 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1627                                struct ena_admin_feature_llq_desc *llq,
1628                                bool use_large_llq_hdr)
1629 {
1630         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1631         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1632         llq_config->llq_num_decs_before_header =
1633                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1634
1635         if (use_large_llq_hdr &&
1636             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1637                 llq_config->llq_ring_entry_size =
1638                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1639                 llq_config->llq_ring_entry_size_value = 256;
1640         } else {
1641                 llq_config->llq_ring_entry_size =
1642                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1643                 llq_config->llq_ring_entry_size_value = 128;
1644         }
1645 }
1646
1647 static int
1648 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1649                                 struct ena_com_dev *ena_dev,
1650                                 struct ena_admin_feature_llq_desc *llq,
1651                                 struct ena_llq_configurations *llq_default_configurations)
1652 {
1653         int rc;
1654         u32 llq_feature_mask;
1655
1656         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1657         if (!(ena_dev->supported_features & llq_feature_mask)) {
1658                 PMD_DRV_LOG(INFO,
1659                         "LLQ is not supported. Fallback to host mode policy.\n");
1660                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1661                 return 0;
1662         }
1663
1664         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1665         if (unlikely(rc)) {
1666                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1667                         "Fallback to host mode policy.");
1668                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1669                 return 0;
1670         }
1671
1672         /* Nothing to config, exit */
1673         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1674                 return 0;
1675
1676         if (!adapter->dev_mem_base) {
1677                 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1678                         "Fallback to host mode policy.\n.");
1679                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1680                 return 0;
1681         }
1682
1683         ena_dev->mem_bar = adapter->dev_mem_base;
1684
1685         return 0;
1686 }
1687
1688 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1689         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1690 {
1691         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1692
1693         /* Regular queues capabilities */
1694         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1695                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1696                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1697                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1698                                     max_queue_ext->max_rx_cq_num);
1699                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1700                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1701         } else {
1702                 struct ena_admin_queue_feature_desc *max_queues =
1703                         &get_feat_ctx->max_queues;
1704                 io_tx_sq_num = max_queues->max_sq_num;
1705                 io_tx_cq_num = max_queues->max_cq_num;
1706                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1707         }
1708
1709         /* In case of LLQ use the llq number in the get feature cmd */
1710         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1711                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1712
1713         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1714         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1715         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1716
1717         if (unlikely(max_num_io_queues == 0)) {
1718                 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1719                 return -EFAULT;
1720         }
1721
1722         return max_num_io_queues;
1723 }
1724
1725 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1726 {
1727         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1728         struct rte_pci_device *pci_dev;
1729         struct rte_intr_handle *intr_handle;
1730         struct ena_adapter *adapter = eth_dev->data->dev_private;
1731         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1732         struct ena_com_dev_get_features_ctx get_feat_ctx;
1733         struct ena_llq_configurations llq_config;
1734         const char *queue_type_str;
1735         uint32_t max_num_io_queues;
1736         int rc;
1737         static int adapters_found;
1738         bool disable_meta_caching;
1739         bool wd_state;
1740
1741         eth_dev->dev_ops = &ena_dev_ops;
1742         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1743         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1744         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1745
1746         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1747                 return 0;
1748
1749         memset(adapter, 0, sizeof(struct ena_adapter));
1750         ena_dev = &adapter->ena_dev;
1751
1752         adapter->rte_eth_dev_data = eth_dev->data;
1753         adapter->rte_dev = eth_dev;
1754
1755         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1756         adapter->pdev = pci_dev;
1757
1758         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1759                      pci_dev->addr.domain,
1760                      pci_dev->addr.bus,
1761                      pci_dev->addr.devid,
1762                      pci_dev->addr.function);
1763
1764         intr_handle = &pci_dev->intr_handle;
1765
1766         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1767         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1768
1769         if (!adapter->regs) {
1770                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1771                              ENA_REGS_BAR);
1772                 return -ENXIO;
1773         }
1774
1775         ena_dev->reg_bar = adapter->regs;
1776         ena_dev->dmadev = adapter->pdev;
1777
1778         adapter->id_number = adapters_found;
1779
1780         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1781                  adapter->id_number);
1782
1783         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1784         if (rc != 0) {
1785                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1786                 goto err;
1787         }
1788
1789         /* device specific initialization routine */
1790         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1791         if (rc) {
1792                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1793                 goto err;
1794         }
1795         adapter->wd_state = wd_state;
1796
1797         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1798                 adapter->use_large_llq_hdr);
1799         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1800                                              &get_feat_ctx.llq, &llq_config);
1801         if (unlikely(rc)) {
1802                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1803                 return rc;
1804         }
1805
1806         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1807                 queue_type_str = "Regular";
1808         else
1809                 queue_type_str = "Low latency";
1810         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1811
1812         calc_queue_ctx.ena_dev = ena_dev;
1813         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1814
1815         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1816         rc = ena_calc_io_queue_size(&calc_queue_ctx,
1817                 adapter->use_large_llq_hdr);
1818         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1819                 rc = -EFAULT;
1820                 goto err_device_destroy;
1821         }
1822
1823         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1824         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1825         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1826         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1827         adapter->max_num_io_queues = max_num_io_queues;
1828
1829         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1830                 disable_meta_caching =
1831                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1832                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
1833         } else {
1834                 disable_meta_caching = false;
1835         }
1836
1837         /* prepare ring structures */
1838         ena_init_rings(adapter, disable_meta_caching);
1839
1840         ena_config_debug_area(adapter);
1841
1842         /* Set max MTU for this device */
1843         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1844
1845         /* set device support for offloads */
1846         adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1847                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1848         adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1849                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1850         adapter->offloads.rx_csum_supported =
1851                 (get_feat_ctx.offload.rx_supported &
1852                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1853
1854         /* Copy MAC address and point DPDK to it */
1855         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1856         rte_ether_addr_copy((struct rte_ether_addr *)
1857                         get_feat_ctx.dev_attr.mac_addr,
1858                         (struct rte_ether_addr *)adapter->mac_addr);
1859
1860         /*
1861          * Pass the information to the rte_eth_dev_close() that it should also
1862          * release the private port resources.
1863          */
1864         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1865
1866         adapter->drv_stats = rte_zmalloc("adapter stats",
1867                                          sizeof(*adapter->drv_stats),
1868                                          RTE_CACHE_LINE_SIZE);
1869         if (!adapter->drv_stats) {
1870                 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1871                 rc = -ENOMEM;
1872                 goto err_delete_debug_area;
1873         }
1874
1875         rte_intr_callback_register(intr_handle,
1876                                    ena_interrupt_handler_rte,
1877                                    adapter);
1878         rte_intr_enable(intr_handle);
1879         ena_com_set_admin_polling_mode(ena_dev, false);
1880         ena_com_admin_aenq_enable(ena_dev);
1881
1882         if (adapters_found == 0)
1883                 rte_timer_subsystem_init();
1884         rte_timer_init(&adapter->timer_wd);
1885
1886         adapters_found++;
1887         adapter->state = ENA_ADAPTER_STATE_INIT;
1888
1889         return 0;
1890
1891 err_delete_debug_area:
1892         ena_com_delete_debug_area(ena_dev);
1893
1894 err_device_destroy:
1895         ena_com_delete_host_info(ena_dev);
1896         ena_com_admin_destroy(ena_dev);
1897
1898 err:
1899         return rc;
1900 }
1901
1902 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1903 {
1904         struct ena_adapter *adapter = eth_dev->data->dev_private;
1905         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1906
1907         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1908                 return;
1909
1910         ena_com_set_admin_running_state(ena_dev, false);
1911
1912         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1913                 ena_close(eth_dev);
1914
1915         ena_com_delete_debug_area(ena_dev);
1916         ena_com_delete_host_info(ena_dev);
1917
1918         ena_com_abort_admin_commands(ena_dev);
1919         ena_com_wait_for_abort_completion(ena_dev);
1920         ena_com_admin_destroy(ena_dev);
1921         ena_com_mmio_reg_read_request_destroy(ena_dev);
1922
1923         adapter->state = ENA_ADAPTER_STATE_FREE;
1924 }
1925
1926 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1927 {
1928         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1929                 return 0;
1930
1931         ena_destroy_device(eth_dev);
1932
1933         eth_dev->dev_ops = NULL;
1934         eth_dev->rx_pkt_burst = NULL;
1935         eth_dev->tx_pkt_burst = NULL;
1936         eth_dev->tx_pkt_prepare = NULL;
1937
1938         return 0;
1939 }
1940
1941 static int ena_dev_configure(struct rte_eth_dev *dev)
1942 {
1943         struct ena_adapter *adapter = dev->data->dev_private;
1944
1945         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1946
1947         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1948         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1949         return 0;
1950 }
1951
1952 static void ena_init_rings(struct ena_adapter *adapter,
1953                            bool disable_meta_caching)
1954 {
1955         size_t i;
1956
1957         for (i = 0; i < adapter->max_num_io_queues; i++) {
1958                 struct ena_ring *ring = &adapter->tx_ring[i];
1959
1960                 ring->configured = 0;
1961                 ring->type = ENA_RING_TYPE_TX;
1962                 ring->adapter = adapter;
1963                 ring->id = i;
1964                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1965                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1966                 ring->sgl_size = adapter->max_tx_sgl_size;
1967                 ring->disable_meta_caching = disable_meta_caching;
1968         }
1969
1970         for (i = 0; i < adapter->max_num_io_queues; i++) {
1971                 struct ena_ring *ring = &adapter->rx_ring[i];
1972
1973                 ring->configured = 0;
1974                 ring->type = ENA_RING_TYPE_RX;
1975                 ring->adapter = adapter;
1976                 ring->id = i;
1977                 ring->sgl_size = adapter->max_rx_sgl_size;
1978         }
1979 }
1980
1981 static int ena_infos_get(struct rte_eth_dev *dev,
1982                           struct rte_eth_dev_info *dev_info)
1983 {
1984         struct ena_adapter *adapter;
1985         struct ena_com_dev *ena_dev;
1986         uint64_t rx_feat = 0, tx_feat = 0;
1987
1988         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1989         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1990         adapter = dev->data->dev_private;
1991
1992         ena_dev = &adapter->ena_dev;
1993         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1994
1995         dev_info->speed_capa =
1996                         ETH_LINK_SPEED_1G   |
1997                         ETH_LINK_SPEED_2_5G |
1998                         ETH_LINK_SPEED_5G   |
1999                         ETH_LINK_SPEED_10G  |
2000                         ETH_LINK_SPEED_25G  |
2001                         ETH_LINK_SPEED_40G  |
2002                         ETH_LINK_SPEED_50G  |
2003                         ETH_LINK_SPEED_100G;
2004
2005         /* Set Tx & Rx features available for device */
2006         if (adapter->offloads.tso4_supported)
2007                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
2008
2009         if (adapter->offloads.tx_csum_supported)
2010                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
2011                         DEV_TX_OFFLOAD_UDP_CKSUM |
2012                         DEV_TX_OFFLOAD_TCP_CKSUM;
2013
2014         if (adapter->offloads.rx_csum_supported)
2015                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
2016                         DEV_RX_OFFLOAD_UDP_CKSUM  |
2017                         DEV_RX_OFFLOAD_TCP_CKSUM;
2018
2019         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2020
2021         /* Inform framework about available features */
2022         dev_info->rx_offload_capa = rx_feat;
2023         dev_info->rx_queue_offload_capa = rx_feat;
2024         dev_info->tx_offload_capa = tx_feat;
2025         dev_info->tx_queue_offload_capa = tx_feat;
2026
2027         dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
2028                                            ETH_RSS_UDP;
2029
2030         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2031         dev_info->max_rx_pktlen  = adapter->max_mtu;
2032         dev_info->max_mac_addrs = 1;
2033
2034         dev_info->max_rx_queues = adapter->max_num_io_queues;
2035         dev_info->max_tx_queues = adapter->max_num_io_queues;
2036         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2037
2038         adapter->tx_supported_offloads = tx_feat;
2039         adapter->rx_supported_offloads = rx_feat;
2040
2041         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2042         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2043         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2044                                         adapter->max_rx_sgl_size);
2045         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2046                                         adapter->max_rx_sgl_size);
2047
2048         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2049         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2050         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2051                                         adapter->max_tx_sgl_size);
2052         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2053                                         adapter->max_tx_sgl_size);
2054
2055         return 0;
2056 }
2057
2058 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2059 {
2060         mbuf->data_len = len;
2061         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2062         mbuf->refcnt = 1;
2063         mbuf->next = NULL;
2064 }
2065
2066 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2067                                     struct ena_com_rx_buf_info *ena_bufs,
2068                                     uint32_t descs,
2069                                     uint16_t *next_to_clean,
2070                                     uint8_t offset)
2071 {
2072         struct rte_mbuf *mbuf;
2073         struct rte_mbuf *mbuf_head;
2074         struct ena_rx_buffer *rx_info;
2075         unsigned int ring_mask = rx_ring->ring_size - 1;
2076         uint16_t ntc, len, req_id, buf = 0;
2077
2078         if (unlikely(descs == 0))
2079                 return NULL;
2080
2081         ntc = *next_to_clean;
2082
2083         len = ena_bufs[buf].len;
2084         req_id = ena_bufs[buf].req_id;
2085         if (unlikely(validate_rx_req_id(rx_ring, req_id)))
2086                 return NULL;
2087
2088         rx_info = &rx_ring->rx_buffer_info[req_id];
2089
2090         mbuf = rx_info->mbuf;
2091         RTE_ASSERT(mbuf != NULL);
2092
2093         ena_init_rx_mbuf(mbuf, len);
2094
2095         /* Fill the mbuf head with the data specific for 1st segment. */
2096         mbuf_head = mbuf;
2097         mbuf_head->nb_segs = descs;
2098         mbuf_head->port = rx_ring->port_id;
2099         mbuf_head->pkt_len = len;
2100         mbuf_head->data_off += offset;
2101
2102         rx_info->mbuf = NULL;
2103         rx_ring->empty_rx_reqs[ntc & ring_mask] = req_id;
2104         ++ntc;
2105
2106         while (--descs) {
2107                 ++buf;
2108                 len = ena_bufs[buf].len;
2109                 req_id = ena_bufs[buf].req_id;
2110                 if (unlikely(validate_rx_req_id(rx_ring, req_id))) {
2111                         rte_mbuf_raw_free(mbuf_head);
2112                         return NULL;
2113                 }
2114
2115                 rx_info = &rx_ring->rx_buffer_info[req_id];
2116                 RTE_ASSERT(rx_info->mbuf != NULL);
2117
2118                 /* Create an mbuf chain. */
2119                 mbuf->next = rx_info->mbuf;
2120                 mbuf = mbuf->next;
2121
2122                 ena_init_rx_mbuf(mbuf, len);
2123                 mbuf_head->pkt_len += len;
2124
2125                 rx_info->mbuf = NULL;
2126                 rx_ring->empty_rx_reqs[ntc & ring_mask] = req_id;
2127                 ++ntc;
2128         }
2129
2130         *next_to_clean = ntc;
2131
2132         return mbuf_head;
2133 }
2134
2135 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2136                                   uint16_t nb_pkts)
2137 {
2138         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2139         unsigned int ring_size = rx_ring->ring_size;
2140         unsigned int ring_mask = ring_size - 1;
2141         unsigned int free_queue_entries;
2142         unsigned int refill_threshold;
2143         uint16_t next_to_clean = rx_ring->next_to_clean;
2144         uint16_t descs_in_use;
2145         struct rte_mbuf *mbuf;
2146         uint16_t completed;
2147         struct ena_com_rx_ctx ena_rx_ctx;
2148         int i, rc = 0;
2149
2150         /* Check adapter state */
2151         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2152                 PMD_DRV_LOG(ALERT,
2153                         "Trying to receive pkts while device is NOT running\n");
2154                 return 0;
2155         }
2156
2157         descs_in_use = ring_size -
2158                 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2159         nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2160
2161         for (completed = 0; completed < nb_pkts; completed++) {
2162                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2163                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2164                 ena_rx_ctx.descs = 0;
2165                 ena_rx_ctx.pkt_offset = 0;
2166                 /* receive packet context */
2167                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2168                                     rx_ring->ena_com_io_sq,
2169                                     &ena_rx_ctx);
2170                 if (unlikely(rc)) {
2171                         PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2172                         rx_ring->adapter->reset_reason =
2173                                 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2174                         rx_ring->adapter->trigger_reset = true;
2175                         ++rx_ring->rx_stats.bad_desc_num;
2176                         return 0;
2177                 }
2178
2179                 mbuf = ena_rx_mbuf(rx_ring,
2180                         ena_rx_ctx.ena_bufs,
2181                         ena_rx_ctx.descs,
2182                         &next_to_clean,
2183                         ena_rx_ctx.pkt_offset);
2184                 if (unlikely(mbuf == NULL)) {
2185                         for (i = 0; i < ena_rx_ctx.descs; ++i) {
2186                                 rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
2187                                         rx_ring->ena_bufs[i].req_id;
2188                                 ++next_to_clean;
2189                         }
2190                         break;
2191                 }
2192
2193                 /* fill mbuf attributes if any */
2194                 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx);
2195
2196                 if (unlikely(mbuf->ol_flags &
2197                                 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2198                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2199                         ++rx_ring->rx_stats.bad_csum;
2200                 }
2201
2202                 mbuf->hash.rss = ena_rx_ctx.hash;
2203
2204                 rx_pkts[completed] = mbuf;
2205                 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2206         }
2207
2208         rx_ring->rx_stats.cnt += completed;
2209         rx_ring->next_to_clean = next_to_clean;
2210
2211         free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2212         refill_threshold =
2213                 RTE_MIN(ring_size / ENA_REFILL_THRESH_DIVIDER,
2214                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2215
2216         /* Burst refill to save doorbells, memory barriers, const interval */
2217         if (free_queue_entries > refill_threshold) {
2218                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2219                 ena_populate_rx_queue(rx_ring, free_queue_entries);
2220         }
2221
2222         return completed;
2223 }
2224
2225 static uint16_t
2226 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2227                 uint16_t nb_pkts)
2228 {
2229         int32_t ret;
2230         uint32_t i;
2231         struct rte_mbuf *m;
2232         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2233         struct rte_ipv4_hdr *ip_hdr;
2234         uint64_t ol_flags;
2235         uint16_t frag_field;
2236
2237         for (i = 0; i != nb_pkts; i++) {
2238                 m = tx_pkts[i];
2239                 ol_flags = m->ol_flags;
2240
2241                 if (!(ol_flags & PKT_TX_IPV4))
2242                         continue;
2243
2244                 /* If there was not L2 header length specified, assume it is
2245                  * length of the ethernet header.
2246                  */
2247                 if (unlikely(m->l2_len == 0))
2248                         m->l2_len = sizeof(struct rte_ether_hdr);
2249
2250                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2251                                                  m->l2_len);
2252                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2253
2254                 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2255                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2256
2257                         /* If IPv4 header has DF flag enabled and TSO support is
2258                          * disabled, partial chcecksum should not be calculated.
2259                          */
2260                         if (!tx_ring->adapter->offloads.tso4_supported)
2261                                 continue;
2262                 }
2263
2264                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2265                                 (ol_flags & PKT_TX_L4_MASK) ==
2266                                 PKT_TX_SCTP_CKSUM) {
2267                         rte_errno = ENOTSUP;
2268                         return i;
2269                 }
2270
2271 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2272                 ret = rte_validate_tx_offload(m);
2273                 if (ret != 0) {
2274                         rte_errno = -ret;
2275                         return i;
2276                 }
2277 #endif
2278
2279                 /* In case we are supposed to TSO and have DF not set (DF=0)
2280                  * hardware must be provided with partial checksum, otherwise
2281                  * it will take care of necessary calculations.
2282                  */
2283
2284                 ret = rte_net_intel_cksum_flags_prepare(m,
2285                         ol_flags & ~PKT_TX_TCP_SEG);
2286                 if (ret != 0) {
2287                         rte_errno = -ret;
2288                         return i;
2289                 }
2290         }
2291
2292         return i;
2293 }
2294
2295 static void ena_update_hints(struct ena_adapter *adapter,
2296                              struct ena_admin_ena_hw_hints *hints)
2297 {
2298         if (hints->admin_completion_tx_timeout)
2299                 adapter->ena_dev.admin_queue.completion_timeout =
2300                         hints->admin_completion_tx_timeout * 1000;
2301
2302         if (hints->mmio_read_timeout)
2303                 /* convert to usec */
2304                 adapter->ena_dev.mmio_read.reg_read_to =
2305                         hints->mmio_read_timeout * 1000;
2306
2307         if (hints->driver_watchdog_timeout) {
2308                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2309                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2310                 else
2311                         // Convert msecs to ticks
2312                         adapter->keep_alive_timeout =
2313                                 (hints->driver_watchdog_timeout *
2314                                 rte_get_timer_hz()) / 1000;
2315         }
2316 }
2317
2318 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2319                                         struct rte_mbuf *mbuf)
2320 {
2321         struct ena_com_dev *ena_dev;
2322         int num_segments, header_len, rc;
2323
2324         ena_dev = &tx_ring->adapter->ena_dev;
2325         num_segments = mbuf->nb_segs;
2326         header_len = mbuf->data_len;
2327
2328         if (likely(num_segments < tx_ring->sgl_size))
2329                 return 0;
2330
2331         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2332             (num_segments == tx_ring->sgl_size) &&
2333             (header_len < tx_ring->tx_max_header_size))
2334                 return 0;
2335
2336         ++tx_ring->tx_stats.linearize;
2337         rc = rte_pktmbuf_linearize(mbuf);
2338         if (unlikely(rc)) {
2339                 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2340                 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2341                 ++tx_ring->tx_stats.linearize_failed;
2342                 return rc;
2343         }
2344
2345         return rc;
2346 }
2347
2348 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2349                                   uint16_t nb_pkts)
2350 {
2351         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2352         uint16_t next_to_use = tx_ring->next_to_use;
2353         uint16_t next_to_clean = tx_ring->next_to_clean;
2354         struct rte_mbuf *mbuf;
2355         uint16_t seg_len;
2356         unsigned int ring_size = tx_ring->ring_size;
2357         unsigned int ring_mask = ring_size - 1;
2358         unsigned int cleanup_budget;
2359         struct ena_com_tx_ctx ena_tx_ctx;
2360         struct ena_tx_buffer *tx_info;
2361         struct ena_com_buf *ebuf;
2362         uint16_t rc, req_id, total_tx_descs = 0;
2363         uint16_t sent_idx = 0;
2364         uint16_t push_len = 0;
2365         uint16_t delta = 0;
2366         int nb_hw_desc;
2367         uint32_t total_length;
2368
2369         /* Check adapter state */
2370         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2371                 PMD_DRV_LOG(ALERT,
2372                         "Trying to xmit pkts while device is NOT running\n");
2373                 return 0;
2374         }
2375
2376         nb_pkts = RTE_MIN(ena_com_free_q_entries(tx_ring->ena_com_io_sq),
2377                 nb_pkts);
2378
2379         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2380                 mbuf = tx_pkts[sent_idx];
2381                 total_length = 0;
2382
2383                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2384                 if (unlikely(rc))
2385                         break;
2386
2387                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2388                 tx_info = &tx_ring->tx_buffer_info[req_id];
2389                 tx_info->mbuf = mbuf;
2390                 tx_info->num_of_bufs = 0;
2391                 ebuf = tx_info->bufs;
2392
2393                 /* Prepare TX context */
2394                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2395                 memset(&ena_tx_ctx.ena_meta, 0x0,
2396                        sizeof(struct ena_com_tx_meta));
2397                 ena_tx_ctx.ena_bufs = ebuf;
2398                 ena_tx_ctx.req_id = req_id;
2399
2400                 delta = 0;
2401                 seg_len = mbuf->data_len;
2402
2403                 if (tx_ring->tx_mem_queue_type ==
2404                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2405                         push_len = RTE_MIN(mbuf->pkt_len,
2406                                            tx_ring->tx_max_header_size);
2407                         ena_tx_ctx.header_len = push_len;
2408
2409                         if (likely(push_len <= seg_len)) {
2410                                 /* If the push header is in the single segment,
2411                                  * then just point it to the 1st mbuf data.
2412                                  */
2413                                 ena_tx_ctx.push_header =
2414                                         rte_pktmbuf_mtod(mbuf, uint8_t *);
2415                         } else {
2416                                 /* If the push header lays in the several
2417                                  * segments, copy it to the intermediate buffer.
2418                                  */
2419                                 rte_pktmbuf_read(mbuf, 0, push_len,
2420                                         tx_ring->push_buf_intermediate_buf);
2421                                 ena_tx_ctx.push_header =
2422                                         tx_ring->push_buf_intermediate_buf;
2423                                 delta = push_len - seg_len;
2424                         }
2425                 } /* there's no else as we take advantage of memset zeroing */
2426
2427                 /* Set TX offloads flags, if applicable */
2428                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2429                         tx_ring->disable_meta_caching);
2430
2431                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2432
2433                 /* Process first segment taking into
2434                  * consideration pushed header
2435                  */
2436                 if (seg_len > push_len) {
2437                         ebuf->paddr = mbuf->buf_iova +
2438                                       mbuf->data_off +
2439                                       push_len;
2440                         ebuf->len = seg_len - push_len;
2441                         ebuf++;
2442                         tx_info->num_of_bufs++;
2443                 }
2444                 total_length += mbuf->data_len;
2445
2446                 while ((mbuf = mbuf->next) != NULL) {
2447                         seg_len = mbuf->data_len;
2448
2449                         /* Skip mbufs if whole data is pushed as a header */
2450                         if (unlikely(delta > seg_len)) {
2451                                 delta -= seg_len;
2452                                 continue;
2453                         }
2454
2455                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2456                         ebuf->len = seg_len - delta;
2457                         total_length += ebuf->len;
2458                         ebuf++;
2459                         tx_info->num_of_bufs++;
2460
2461                         delta = 0;
2462                 }
2463
2464                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2465
2466                 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2467                                                &ena_tx_ctx)) {
2468                         PMD_DRV_LOG(DEBUG, "llq tx max burst size of queue %d"
2469                                 " achieved, writing doorbell to send burst\n",
2470                                 tx_ring->id);
2471                         ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2472                 }
2473
2474                 /* prepare the packet's descriptors to dma engine */
2475                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2476                                         &ena_tx_ctx, &nb_hw_desc);
2477                 if (unlikely(rc)) {
2478                         ++tx_ring->tx_stats.prepare_ctx_err;
2479                         break;
2480                 }
2481                 tx_info->tx_descs = nb_hw_desc;
2482
2483                 next_to_use++;
2484                 tx_ring->tx_stats.cnt++;
2485                 tx_ring->tx_stats.bytes += total_length;
2486         }
2487         tx_ring->tx_stats.available_desc =
2488                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2489
2490         /* If there are ready packets to be xmitted... */
2491         if (sent_idx > 0) {
2492                 /* ...let HW do its best :-) */
2493                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2494                 tx_ring->tx_stats.doorbells++;
2495                 tx_ring->next_to_use = next_to_use;
2496         }
2497
2498         /* Clear complete packets  */
2499         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2500                 rc = validate_tx_req_id(tx_ring, req_id);
2501                 if (rc)
2502                         break;
2503
2504                 /* Get Tx info & store how many descs were processed  */
2505                 tx_info = &tx_ring->tx_buffer_info[req_id];
2506                 total_tx_descs += tx_info->tx_descs;
2507
2508                 /* Free whole mbuf chain  */
2509                 mbuf = tx_info->mbuf;
2510                 rte_pktmbuf_free(mbuf);
2511                 tx_info->mbuf = NULL;
2512
2513                 /* Put back descriptor to the ring for reuse */
2514                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2515                 next_to_clean++;
2516                 cleanup_budget =
2517                         RTE_MIN(ring_size / ENA_REFILL_THRESH_DIVIDER,
2518                         (unsigned int)ENA_REFILL_THRESH_PACKET);
2519
2520                 /* If too many descs to clean, leave it for another run */
2521                 if (unlikely(total_tx_descs > cleanup_budget))
2522                         break;
2523         }
2524         tx_ring->tx_stats.available_desc =
2525                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2526
2527         if (total_tx_descs > 0) {
2528                 /* acknowledge completion of sent packets */
2529                 tx_ring->next_to_clean = next_to_clean;
2530                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2531                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2532         }
2533
2534         tx_ring->tx_stats.tx_poll++;
2535
2536         return sent_idx;
2537 }
2538
2539 /**
2540  * DPDK callback to retrieve names of extended device statistics
2541  *
2542  * @param dev
2543  *   Pointer to Ethernet device structure.
2544  * @param[out] xstats_names
2545  *   Buffer to insert names into.
2546  * @param n
2547  *   Number of names.
2548  *
2549  * @return
2550  *   Number of xstats names.
2551  */
2552 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2553                                 struct rte_eth_xstat_name *xstats_names,
2554                                 unsigned int n)
2555 {
2556         unsigned int xstats_count = ena_xstats_calc_num(dev);
2557         unsigned int stat, i, count = 0;
2558
2559         if (n < xstats_count || !xstats_names)
2560                 return xstats_count;
2561
2562         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2563                 strcpy(xstats_names[count].name,
2564                         ena_stats_global_strings[stat].name);
2565
2566         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2567                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2568                         snprintf(xstats_names[count].name,
2569                                 sizeof(xstats_names[count].name),
2570                                 "rx_q%d_%s", i,
2571                                 ena_stats_rx_strings[stat].name);
2572
2573         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2574                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2575                         snprintf(xstats_names[count].name,
2576                                 sizeof(xstats_names[count].name),
2577                                 "tx_q%d_%s", i,
2578                                 ena_stats_tx_strings[stat].name);
2579
2580         return xstats_count;
2581 }
2582
2583 /**
2584  * DPDK callback to get extended device statistics.
2585  *
2586  * @param dev
2587  *   Pointer to Ethernet device structure.
2588  * @param[out] stats
2589  *   Stats table output buffer.
2590  * @param n
2591  *   The size of the stats table.
2592  *
2593  * @return
2594  *   Number of xstats on success, negative on failure.
2595  */
2596 static int ena_xstats_get(struct rte_eth_dev *dev,
2597                           struct rte_eth_xstat *xstats,
2598                           unsigned int n)
2599 {
2600         struct ena_adapter *adapter = dev->data->dev_private;
2601         unsigned int xstats_count = ena_xstats_calc_num(dev);
2602         unsigned int stat, i, count = 0;
2603         int stat_offset;
2604         void *stats_begin;
2605
2606         if (n < xstats_count)
2607                 return xstats_count;
2608
2609         if (!xstats)
2610                 return 0;
2611
2612         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2613                 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2614                 stats_begin = &adapter->dev_stats;
2615
2616                 xstats[count].id = count;
2617                 xstats[count].value = *((uint64_t *)
2618                         ((char *)stats_begin + stat_offset));
2619         }
2620
2621         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2622                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2623                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2624                         stats_begin = &adapter->rx_ring[i].rx_stats;
2625
2626                         xstats[count].id = count;
2627                         xstats[count].value = *((uint64_t *)
2628                                 ((char *)stats_begin + stat_offset));
2629                 }
2630         }
2631
2632         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2633                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2634                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2635                         stats_begin = &adapter->tx_ring[i].rx_stats;
2636
2637                         xstats[count].id = count;
2638                         xstats[count].value = *((uint64_t *)
2639                                 ((char *)stats_begin + stat_offset));
2640                 }
2641         }
2642
2643         return count;
2644 }
2645
2646 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2647                                 const uint64_t *ids,
2648                                 uint64_t *values,
2649                                 unsigned int n)
2650 {
2651         struct ena_adapter *adapter = dev->data->dev_private;
2652         uint64_t id;
2653         uint64_t rx_entries, tx_entries;
2654         unsigned int i;
2655         int qid;
2656         int valid = 0;
2657         for (i = 0; i < n; ++i) {
2658                 id = ids[i];
2659                 /* Check if id belongs to global statistics */
2660                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2661                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2662                         ++valid;
2663                         continue;
2664                 }
2665
2666                 /* Check if id belongs to rx queue statistics */
2667                 id -= ENA_STATS_ARRAY_GLOBAL;
2668                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2669                 if (id < rx_entries) {
2670                         qid = id % dev->data->nb_rx_queues;
2671                         id /= dev->data->nb_rx_queues;
2672                         values[i] = *((uint64_t *)
2673                                 &adapter->rx_ring[qid].rx_stats + id);
2674                         ++valid;
2675                         continue;
2676                 }
2677                                 /* Check if id belongs to rx queue statistics */
2678                 id -= rx_entries;
2679                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2680                 if (id < tx_entries) {
2681                         qid = id % dev->data->nb_tx_queues;
2682                         id /= dev->data->nb_tx_queues;
2683                         values[i] = *((uint64_t *)
2684                                 &adapter->tx_ring[qid].tx_stats + id);
2685                         ++valid;
2686                         continue;
2687                 }
2688         }
2689
2690         return valid;
2691 }
2692
2693 static int ena_process_bool_devarg(const char *key,
2694                                    const char *value,
2695                                    void *opaque)
2696 {
2697         struct ena_adapter *adapter = opaque;
2698         bool bool_value;
2699
2700         /* Parse the value. */
2701         if (strcmp(value, "1") == 0) {
2702                 bool_value = true;
2703         } else if (strcmp(value, "0") == 0) {
2704                 bool_value = false;
2705         } else {
2706                 PMD_INIT_LOG(ERR,
2707                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
2708                         value, key);
2709                 return -EINVAL;
2710         }
2711
2712         /* Now, assign it to the proper adapter field. */
2713         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR))
2714                 adapter->use_large_llq_hdr = bool_value;
2715
2716         return 0;
2717 }
2718
2719 static int ena_parse_devargs(struct ena_adapter *adapter,
2720                              struct rte_devargs *devargs)
2721 {
2722         static const char * const allowed_args[] = {
2723                 ENA_DEVARG_LARGE_LLQ_HDR,
2724         };
2725         struct rte_kvargs *kvlist;
2726         int rc;
2727
2728         if (devargs == NULL)
2729                 return 0;
2730
2731         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
2732         if (kvlist == NULL) {
2733                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
2734                         devargs->args);
2735                 return -EINVAL;
2736         }
2737
2738         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
2739                 ena_process_bool_devarg, adapter);
2740
2741         rte_kvargs_free(kvlist);
2742
2743         return rc;
2744 }
2745
2746 /*********************************************************************
2747  *  PMD configuration
2748  *********************************************************************/
2749 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2750         struct rte_pci_device *pci_dev)
2751 {
2752         return rte_eth_dev_pci_generic_probe(pci_dev,
2753                 sizeof(struct ena_adapter), eth_ena_dev_init);
2754 }
2755
2756 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2757 {
2758         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2759 }
2760
2761 static struct rte_pci_driver rte_ena_pmd = {
2762         .id_table = pci_id_ena_map,
2763         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2764                      RTE_PCI_DRV_WC_ACTIVATE,
2765         .probe = eth_ena_pci_probe,
2766         .remove = eth_ena_pci_remove,
2767 };
2768
2769 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2770 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2771 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2772 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
2773
2774 RTE_INIT(ena_init_log)
2775 {
2776         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2777         if (ena_logtype_init >= 0)
2778                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2779         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2780         if (ena_logtype_driver >= 0)
2781                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2782
2783 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2784         ena_logtype_rx = rte_log_register("pmd.net.ena.rx");
2785         if (ena_logtype_rx >= 0)
2786                 rte_log_set_level(ena_logtype_rx, RTE_LOG_NOTICE);
2787 #endif
2788
2789 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2790         ena_logtype_tx = rte_log_register("pmd.net.ena.tx");
2791         if (ena_logtype_tx >= 0)
2792                 rte_log_set_level(ena_logtype_tx, RTE_LOG_NOTICE);
2793 #endif
2794
2795 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2796         ena_logtype_tx_free = rte_log_register("pmd.net.ena.tx_free");
2797         if (ena_logtype_tx_free >= 0)
2798                 rte_log_set_level(ena_logtype_tx_free, RTE_LOG_NOTICE);
2799 #endif
2800
2801 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2802         ena_logtype_com = rte_log_register("pmd.net.ena.com");
2803         if (ena_logtype_com >= 0)
2804                 rte_log_set_level(ena_logtype_com, RTE_LOG_NOTICE);
2805 #endif
2806 }
2807
2808 /******************************************************************************
2809  ******************************** AENQ Handlers *******************************
2810  *****************************************************************************/
2811 static void ena_update_on_link_change(void *adapter_data,
2812                                       struct ena_admin_aenq_entry *aenq_e)
2813 {
2814         struct rte_eth_dev *eth_dev;
2815         struct ena_adapter *adapter;
2816         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2817         uint32_t status;
2818
2819         adapter = adapter_data;
2820         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2821         eth_dev = adapter->rte_dev;
2822
2823         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2824         adapter->link_status = status;
2825
2826         ena_link_update(eth_dev, 0);
2827         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2828 }
2829
2830 static void ena_notification(void *data,
2831                              struct ena_admin_aenq_entry *aenq_e)
2832 {
2833         struct ena_adapter *adapter = data;
2834         struct ena_admin_ena_hw_hints *hints;
2835
2836         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2837                 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2838                         aenq_e->aenq_common_desc.group,
2839                         ENA_ADMIN_NOTIFICATION);
2840
2841         switch (aenq_e->aenq_common_desc.syndrom) {
2842         case ENA_ADMIN_UPDATE_HINTS:
2843                 hints = (struct ena_admin_ena_hw_hints *)
2844                         (&aenq_e->inline_data_w4);
2845                 ena_update_hints(adapter, hints);
2846                 break;
2847         default:
2848                 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2849                         aenq_e->aenq_common_desc.syndrom);
2850         }
2851 }
2852
2853 static void ena_keep_alive(void *adapter_data,
2854                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2855 {
2856         struct ena_adapter *adapter = adapter_data;
2857         struct ena_admin_aenq_keep_alive_desc *desc;
2858         uint64_t rx_drops;
2859         uint64_t tx_drops;
2860
2861         adapter->timestamp_wd = rte_get_timer_cycles();
2862
2863         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2864         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2865         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
2866
2867         adapter->drv_stats->rx_drops = rx_drops;
2868         adapter->dev_stats.tx_drops = tx_drops;
2869 }
2870
2871 /**
2872  * This handler will called for unknown event group or unimplemented handlers
2873  **/
2874 static void unimplemented_aenq_handler(__rte_unused void *data,
2875                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2876 {
2877         PMD_DRV_LOG(ERR, "Unknown event was received or event with "
2878                           "unimplemented handler\n");
2879 }
2880
2881 static struct ena_aenq_handlers aenq_handlers = {
2882         .handlers = {
2883                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2884                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2885                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2886         },
2887         .unimplemented_handler = unimplemented_aenq_handler
2888 };