drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 0
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 enum ethtool_stringset {
  89         ETH_SS_TEST             = 0,
  90         ETH_SS_STATS,
  91 };
  92
  93 struct ena_stats {
  94         char name[ETH_GSTRING_LEN];
  95         int stat_offset;
  96 };
  97
  98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
  99         .name = #stat, \
 100         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 101 }
 102
 103 #define ENA_STAT_ENTRY(stat, stat_type) { \
 104         .name = #stat, \
 105         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 106 }
 107
 108 #define ENA_STAT_RX_ENTRY(stat) \
 109         ENA_STAT_ENTRY(stat, rx)
 110
 111 #define ENA_STAT_TX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, tx)
 113
 114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, dev)
 116
 117 /*
 118  * Each rte_memzone should have unique name.
 119  * To satisfy it, count number of allocation and add it to name.
 120  */
 121 uint32_t ena_alloc_cnt;
 122
 123 static const struct ena_stats ena_stats_global_strings[] = {
 124         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 125         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 126         ENA_STAT_GLOBAL_ENTRY(io_resume),
 127         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 128         ENA_STAT_GLOBAL_ENTRY(interface_up),
 129         ENA_STAT_GLOBAL_ENTRY(interface_down),
 130         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 131 };
 132
 133 static const struct ena_stats ena_stats_tx_strings[] = {
 134         ENA_STAT_TX_ENTRY(cnt),
 135         ENA_STAT_TX_ENTRY(bytes),
 136         ENA_STAT_TX_ENTRY(queue_stop),
 137         ENA_STAT_TX_ENTRY(queue_wakeup),
 138         ENA_STAT_TX_ENTRY(dma_mapping_err),
 139         ENA_STAT_TX_ENTRY(linearize),
 140         ENA_STAT_TX_ENTRY(linearize_failed),
 141         ENA_STAT_TX_ENTRY(tx_poll),
 142         ENA_STAT_TX_ENTRY(doorbells),
 143         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 144         ENA_STAT_TX_ENTRY(missing_tx_comp),
 145         ENA_STAT_TX_ENTRY(bad_req_id),
 146 };
 147
 148 static const struct ena_stats ena_stats_rx_strings[] = {
 149         ENA_STAT_RX_ENTRY(cnt),
 150         ENA_STAT_RX_ENTRY(bytes),
 151         ENA_STAT_RX_ENTRY(refil_partial),
 152         ENA_STAT_RX_ENTRY(bad_csum),
 153         ENA_STAT_RX_ENTRY(page_alloc_fail),
 154         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 155         ENA_STAT_RX_ENTRY(dma_mapping_err),
 156         ENA_STAT_RX_ENTRY(bad_desc_num),
 157         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 158 };
 159
 160 static const struct ena_stats ena_stats_ena_com_strings[] = {
 161         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 162         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 163         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 164         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 165         ENA_STAT_ENA_COM_ENTRY(no_completion),
 166 };
 167
 168 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 169 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 170 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 171 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 172
 173 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 174                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 175                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 176                         DEV_TX_OFFLOAD_TCP_TSO)
 177 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 178                        PKT_TX_IP_CKSUM |\
 179                        PKT_TX_TCP_SEG)
 180
 181 /** Vendor ID used by Amazon devices */
 182 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 183 /** Amazon devices */
 184 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 185 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 186
 187 #define ENA_TX_OFFLOAD_MASK     (\
 188         PKT_TX_L4_MASK |         \
 189         PKT_TX_IP_CKSUM |        \
 190         PKT_TX_TCP_SEG)
 191
 192 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 193         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 194
 195 int ena_logtype_init;
 196 int ena_logtype_driver;
 197
 198 static const struct rte_pci_id pci_id_ena_map[] = {
 199         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 200         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 201         { .device_id = 0 },
 202 };
 203
 204 static struct ena_aenq_handlers aenq_handlers;
 205
 206 static int ena_device_init(struct ena_com_dev *ena_dev,
 207                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 208 static int ena_dev_configure(struct rte_eth_dev *dev);
 209 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 210                                   uint16_t nb_pkts);
 211 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 212                 uint16_t nb_pkts);
 213 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 214                               uint16_t nb_desc, unsigned int socket_id,
 215                               const struct rte_eth_txconf *tx_conf);
 216 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 217                               uint16_t nb_desc, unsigned int socket_id,
 218                               const struct rte_eth_rxconf *rx_conf,
 219                               struct rte_mempool *mp);
 220 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 221                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 222 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 223 static void ena_init_rings(struct ena_adapter *adapter);
 224 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 225 static int ena_start(struct rte_eth_dev *dev);
 226 static void ena_stop(struct rte_eth_dev *dev);
 227 static void ena_close(struct rte_eth_dev *dev);
 228 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 229 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 230 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 231 static void ena_rx_queue_release(void *queue);
 232 static void ena_tx_queue_release(void *queue);
 233 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 234 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 235 static int ena_link_update(struct rte_eth_dev *dev,
 236                            int wait_to_complete);
 237 static int ena_queue_restart(struct ena_ring *ring);
 238 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 239                                  enum ena_ring_type ring_type);
 240 static void ena_stats_restart(struct rte_eth_dev *dev);
 241 static void ena_infos_get(struct rte_eth_dev *dev,
 242                           struct rte_eth_dev_info *dev_info);
 243 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 244                                struct rte_eth_rss_reta_entry64 *reta_conf,
 245                                uint16_t reta_size);
 246 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 247                               struct rte_eth_rss_reta_entry64 *reta_conf,
 248                               uint16_t reta_size);
 249 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 250 static void ena_interrupt_handler_rte(void *cb_arg);
 251
 252 static const struct eth_dev_ops ena_dev_ops = {
 253         .dev_configure        = ena_dev_configure,
 254         .dev_infos_get        = ena_infos_get,
 255         .rx_queue_setup       = ena_rx_queue_setup,
 256         .tx_queue_setup       = ena_tx_queue_setup,
 257         .dev_start            = ena_start,
 258         .dev_stop             = ena_stop,
 259         .link_update          = ena_link_update,
 260         .stats_get            = ena_stats_get,
 261         .mtu_set              = ena_mtu_set,
 262         .rx_queue_release     = ena_rx_queue_release,
 263         .tx_queue_release     = ena_tx_queue_release,
 264         .dev_close            = ena_close,
 265         .reta_update          = ena_rss_reta_update,
 266         .reta_query           = ena_rss_reta_query,
 267 };
 268
 269 #define NUMA_NO_NODE    SOCKET_ID_ANY
 270
 271 static inline int ena_cpu_to_node(int cpu)
 272 {
 273         struct rte_config *config = rte_eal_get_configuration();
 274         struct rte_fbarray *arr = &config->mem_config->memzones;
 275         const struct rte_memzone *mz;
 276
 277         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 278                 return NUMA_NO_NODE;
 279
 280         mz = rte_fbarray_get(arr, cpu);
 281
 282         return mz->socket_id;
 283 }
 284
 285 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 286                                        struct ena_com_rx_ctx *ena_rx_ctx)
 287 {
 288         uint64_t ol_flags = 0;
 289         uint32_t packet_type = 0;
 290
 291         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 292                 packet_type |= RTE_PTYPE_L4_TCP;
 293         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 294                 packet_type |= RTE_PTYPE_L4_UDP;
 295
 296         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 297                 packet_type |= RTE_PTYPE_L3_IPV4;
 298         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 299                 packet_type |= RTE_PTYPE_L3_IPV6;
 300
 301         if (unlikely(ena_rx_ctx->l4_csum_err))
 302                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 303         if (unlikely(ena_rx_ctx->l3_csum_err))
 304                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 305
 306         mbuf->ol_flags = ol_flags;
 307         mbuf->packet_type = packet_type;
 308 }
 309
 310 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 311                                        struct ena_com_tx_ctx *ena_tx_ctx,
 312                                        uint64_t queue_offloads)
 313 {
 314         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 315
 316         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 317             (queue_offloads & QUEUE_OFFLOADS)) {
 318                 /* check if TSO is required */
 319                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 320                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 321                         ena_tx_ctx->tso_enable = true;
 322
 323                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 324                 }
 325
 326                 /* check if L3 checksum is needed */
 327                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 328                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 329                         ena_tx_ctx->l3_csum_enable = true;
 330
 331                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 332                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 333                 } else {
 334                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 335
 336                         /* set don't fragment (DF) flag */
 337                         if (mbuf->packet_type &
 338                                 (RTE_PTYPE_L4_NONFRAG
 339                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 340                                 ena_tx_ctx->df = true;
 341                 }
 342
 343                 /* check if L4 checksum is needed */
 344                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 345                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 346                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 347                         ena_tx_ctx->l4_csum_enable = true;
 348                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 349                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 350                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 351                         ena_tx_ctx->l4_csum_enable = true;
 352                 } else {
 353                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 354                         ena_tx_ctx->l4_csum_enable = false;
 355                 }
 356
 357                 ena_meta->mss = mbuf->tso_segsz;
 358                 ena_meta->l3_hdr_len = mbuf->l3_len;
 359                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 360
 361                 ena_tx_ctx->meta_valid = true;
 362         } else {
 363                 ena_tx_ctx->meta_valid = false;
 364         }
 365 }
 366
 367 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 368 {
 369         struct ena_admin_host_info *host_info;
 370         int rc;
 371
 372         /* Allocate only the host info */
 373         rc = ena_com_allocate_host_info(ena_dev);
 374         if (rc) {
 375                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 376                 return;
 377         }
 378
 379         host_info = ena_dev->host_attr.host_info;
 380
 381         host_info->os_type = ENA_ADMIN_OS_DPDK;
 382         host_info->kernel_ver = RTE_VERSION;
 383         snprintf((char *)host_info->kernel_ver_str,
 384                  sizeof(host_info->kernel_ver_str),
 385                  "%s", rte_version());
 386         host_info->os_dist = RTE_VERSION;
 387         snprintf((char *)host_info->os_dist_str,
 388                  sizeof(host_info->os_dist_str),
 389                  "%s", rte_version());
 390         host_info->driver_version =
 391                 (DRV_MODULE_VER_MAJOR) |
 392                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 393                 (DRV_MODULE_VER_SUBMINOR <<
 394                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 395
 396         rc = ena_com_set_host_attributes(ena_dev);
 397         if (rc) {
 398                 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 399                 if (rc != -ENA_COM_UNSUPPORTED)
 400                         goto err;
 401         }
 402
 403         return;
 404
 405 err:
 406         ena_com_delete_host_info(ena_dev);
 407 }
 408
 409 static int
 410 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 411 {
 412         if (sset != ETH_SS_STATS)
 413                 return -EOPNOTSUPP;
 414
 415          /* Workaround for clang:
 416          * touch internal structures to prevent
 417          * compiler error
 418          */
 419         ENA_TOUCH(ena_stats_global_strings);
 420         ENA_TOUCH(ena_stats_tx_strings);
 421         ENA_TOUCH(ena_stats_rx_strings);
 422         ENA_TOUCH(ena_stats_ena_com_strings);
 423
 424         return  dev->data->nb_tx_queues *
 425                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 426                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 427 }
 428
 429 static void ena_config_debug_area(struct ena_adapter *adapter)
 430 {
 431         u32 debug_area_size;
 432         int rc, ss_count;
 433
 434         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 435         if (ss_count <= 0) {
 436                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 437                 return;
 438         }
 439
 440         /* allocate 32 bytes for each string and 64bit for the value */
 441         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 442
 443         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 444         if (rc) {
 445                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 446                 return;
 447         }
 448
 449         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 450         if (rc) {
 451                 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 452                 if (rc != -ENA_COM_UNSUPPORTED)
 453                         goto err;
 454         }
 455
 456         return;
 457 err:
 458         ena_com_delete_debug_area(&adapter->ena_dev);
 459 }
 460
 461 static void ena_close(struct rte_eth_dev *dev)
 462 {
 463         struct ena_adapter *adapter =
 464                 (struct ena_adapter *)(dev->data->dev_private);
 465
 466         ena_stop(dev);
 467         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 468
 469         ena_rx_queue_release_all(dev);
 470         ena_tx_queue_release_all(dev);
 471 }
 472
 473 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 474                                struct rte_eth_rss_reta_entry64 *reta_conf,
 475                                uint16_t reta_size)
 476 {
 477         struct ena_adapter *adapter =
 478                 (struct ena_adapter *)(dev->data->dev_private);
 479         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 480         int ret, i;
 481         u16 entry_value;
 482         int conf_idx;
 483         int idx;
 484
 485         if ((reta_size == 0) || (reta_conf == NULL))
 486                 return -EINVAL;
 487
 488         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 489                 RTE_LOG(WARNING, PMD,
 490                         "indirection table %d is bigger than supported (%d)\n",
 491                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 492                 ret = -EINVAL;
 493                 goto err;
 494         }
 495
 496         for (i = 0 ; i < reta_size ; i++) {
 497                 /* each reta_conf is for 64 entries.
 498                  * to support 128 we use 2 conf of 64
 499                  */
 500                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 501                 idx = i % RTE_RETA_GROUP_SIZE;
 502                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 503                         entry_value =
 504                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 505                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 506                                                                 i,
 507                                                                 entry_value);
 508                         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 509                                 RTE_LOG(ERR, PMD,
 510                                         "Cannot fill indirect table\n");
 511                                 ret = -ENOTSUP;
 512                                 goto err;
 513                         }
 514                 }
 515         }
 516
 517         ret = ena_com_indirect_table_set(ena_dev);
 518         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 519                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 520                 ret = -ENOTSUP;
 521                 goto err;
 522         }
 523
 524         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 525                 __func__, reta_size, adapter->rte_dev->data->port_id);
 526 err:
 527         return ret;
 528 }
 529
 530 /* Query redirection table. */
 531 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 532                               struct rte_eth_rss_reta_entry64 *reta_conf,
 533                               uint16_t reta_size)
 534 {
 535         struct ena_adapter *adapter =
 536                 (struct ena_adapter *)(dev->data->dev_private);
 537         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 538         int ret;
 539         int i;
 540         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 541         int reta_conf_idx;
 542         int reta_idx;
 543
 544         if (reta_size == 0 || reta_conf == NULL ||
 545             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 546                 return -EINVAL;
 547
 548         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 549         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 550                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 551                 ret = -ENOTSUP;
 552                 goto err;
 553         }
 554
 555         for (i = 0 ; i < reta_size ; i++) {
 556                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 557                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 558                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 559                         reta_conf[reta_conf_idx].reta[reta_idx] =
 560                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 561         }
 562 err:
 563         return ret;
 564 }
 565
 566 static int ena_rss_init_default(struct ena_adapter *adapter)
 567 {
 568         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 569         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 570         int rc, i;
 571         u32 val;
 572
 573         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 574         if (unlikely(rc)) {
 575                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 576                 goto err_rss_init;
 577         }
 578
 579         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 580                 val = i % nb_rx_queues;
 581                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 582                                                        ENA_IO_RXQ_IDX(val));
 583                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 584                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 585                         goto err_fill_indir;
 586                 }
 587         }
 588
 589         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 590                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 591         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 592                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 593                 goto err_fill_indir;
 594         }
 595
 596         rc = ena_com_set_default_hash_ctrl(ena_dev);
 597         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 598                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 599                 goto err_fill_indir;
 600         }
 601
 602         rc = ena_com_indirect_table_set(ena_dev);
 603         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 604                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 605                 goto err_fill_indir;
 606         }
 607         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 608                 adapter->rte_dev->data->port_id);
 609
 610         return 0;
 611
 612 err_fill_indir:
 613         ena_com_rss_destroy(ena_dev);
 614 err_rss_init:
 615
 616         return rc;
 617 }
 618
 619 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 620 {
 621         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 622         int nb_queues = dev->data->nb_rx_queues;
 623         int i;
 624
 625         for (i = 0; i < nb_queues; i++)
 626                 ena_rx_queue_release(queues[i]);
 627 }
 628
 629 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 630 {
 631         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 632         int nb_queues = dev->data->nb_tx_queues;
 633         int i;
 634
 635         for (i = 0; i < nb_queues; i++)
 636                 ena_tx_queue_release(queues[i]);
 637 }
 638
 639 static void ena_rx_queue_release(void *queue)
 640 {
 641         struct ena_ring *ring = (struct ena_ring *)queue;
 642         struct ena_adapter *adapter = ring->adapter;
 643         int ena_qid;
 644
 645         ena_assert_msg(ring->configured,
 646                        "API violation - releasing not configured queue");
 647         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 648                        "API violation");
 649
 650         /* Destroy HW queue */
 651         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 652         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 653
 654         /* Free all bufs */
 655         ena_rx_queue_release_bufs(ring);
 656
 657         /* Free ring resources */
 658         if (ring->rx_buffer_info)
 659                 rte_free(ring->rx_buffer_info);
 660         ring->rx_buffer_info = NULL;
 661
 662         ring->configured = 0;
 663
 664         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 665                 ring->port_id, ring->id);
 666 }
 667
 668 static void ena_tx_queue_release(void *queue)
 669 {
 670         struct ena_ring *ring = (struct ena_ring *)queue;
 671         struct ena_adapter *adapter = ring->adapter;
 672         int ena_qid;
 673
 674         ena_assert_msg(ring->configured,
 675                        "API violation. Releasing not configured queue");
 676         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 677                        "API violation");
 678
 679         /* Destroy HW queue */
 680         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 681         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 682
 683         /* Free all bufs */
 684         ena_tx_queue_release_bufs(ring);
 685
 686         /* Free ring resources */
 687         if (ring->tx_buffer_info)
 688                 rte_free(ring->tx_buffer_info);
 689
 690         if (ring->empty_tx_reqs)
 691                 rte_free(ring->empty_tx_reqs);
 692
 693         ring->empty_tx_reqs = NULL;
 694         ring->tx_buffer_info = NULL;
 695
 696         ring->configured = 0;
 697
 698         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 699                 ring->port_id, ring->id);
 700 }
 701
 702 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 703 {
 704         unsigned int ring_mask = ring->ring_size - 1;
 705
 706         while (ring->next_to_clean != ring->next_to_use) {
 707                 struct rte_mbuf *m =
 708                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 709
 710                 if (m)
 711                         rte_mbuf_raw_free(m);
 712
 713                 ring->next_to_clean++;
 714         }
 715 }
 716
 717 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 718 {
 719         unsigned int i;
 720
 721         for (i = 0; i < ring->ring_size; ++i) {
 722                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 723
 724                 if (tx_buf->mbuf)
 725                         rte_pktmbuf_free(tx_buf->mbuf);
 726
 727                 ring->next_to_clean++;
 728         }
 729 }
 730
 731 static int ena_link_update(struct rte_eth_dev *dev,
 732                            __rte_unused int wait_to_complete)
 733 {
 734         struct rte_eth_link *link = &dev->data->dev_link;
 735         struct ena_adapter *adapter;
 736
 737         adapter = (struct ena_adapter *)(dev->data->dev_private);
 738
 739         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 740         link->link_speed = ETH_SPEED_NUM_10G;
 741         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 742
 743         return 0;
 744 }
 745
 746 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 747                                  enum ena_ring_type ring_type)
 748 {
 749         struct ena_adapter *adapter =
 750                 (struct ena_adapter *)(dev->data->dev_private);
 751         struct ena_ring *queues = NULL;
 752         int i = 0;
 753         int rc = 0;
 754
 755         queues = (ring_type == ENA_RING_TYPE_RX) ?
 756                 adapter->rx_ring : adapter->tx_ring;
 757
 758         for (i = 0; i < adapter->num_queues; i++) {
 759                 if (queues[i].configured) {
 760                         if (ring_type == ENA_RING_TYPE_RX) {
 761                                 ena_assert_msg(
 762                                         dev->data->rx_queues[i] == &queues[i],
 763                                         "Inconsistent state of rx queues\n");
 764                         } else {
 765                                 ena_assert_msg(
 766                                         dev->data->tx_queues[i] == &queues[i],
 767                                         "Inconsistent state of tx queues\n");
 768                         }
 769
 770                         rc = ena_queue_restart(&queues[i]);
 771
 772                         if (rc) {
 773                                 PMD_INIT_LOG(ERR,
 774                                              "failed to restart queue %d type(%d)",
 775                                              i, ring_type);
 776                                 return -1;
 777                         }
 778                 }
 779         }
 780
 781         return 0;
 782 }
 783
 784 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 785 {
 786         uint32_t max_frame_len = adapter->max_mtu;
 787
 788         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 789             DEV_RX_OFFLOAD_JUMBO_FRAME)
 790                 max_frame_len =
 791                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 792
 793         return max_frame_len;
 794 }
 795
 796 static int ena_check_valid_conf(struct ena_adapter *adapter)
 797 {
 798         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 799
 800         if (max_frame_len > adapter->max_mtu) {
 801                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
 802                 return -1;
 803         }
 804
 805         return 0;
 806 }
 807
 808 static int
 809 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 810                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 811 {
 812         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 813
 814         queue_size = RTE_MIN(queue_size,
 815                              get_feat_ctx->max_queues.max_cq_depth);
 816         queue_size = RTE_MIN(queue_size,
 817                              get_feat_ctx->max_queues.max_sq_depth);
 818
 819         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 820                 queue_size = RTE_MIN(queue_size,
 821                                      get_feat_ctx->max_queues.max_llq_depth);
 822
 823         /* Round down to power of 2 */
 824         if (!rte_is_power_of_2(queue_size))
 825                 queue_size = rte_align32pow2(queue_size >> 1);
 826
 827         if (queue_size == 0) {
 828                 PMD_INIT_LOG(ERR, "Invalid queue size");
 829                 return -EFAULT;
 830         }
 831
 832         return queue_size;
 833 }
 834
 835 static void ena_stats_restart(struct rte_eth_dev *dev)
 836 {
 837         struct ena_adapter *adapter =
 838                 (struct ena_adapter *)(dev->data->dev_private);
 839
 840         rte_atomic64_init(&adapter->drv_stats->ierrors);
 841         rte_atomic64_init(&adapter->drv_stats->oerrors);
 842         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 843 }
 844
 845 static int ena_stats_get(struct rte_eth_dev *dev,
 846                           struct rte_eth_stats *stats)
 847 {
 848         struct ena_admin_basic_stats ena_stats;
 849         struct ena_adapter *adapter =
 850                 (struct ena_adapter *)(dev->data->dev_private);
 851         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 852         int rc;
 853
 854         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 855                 return -ENOTSUP;
 856
 857         memset(&ena_stats, 0, sizeof(ena_stats));
 858         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 859         if (unlikely(rc)) {
 860                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 861                 return rc;
 862         }
 863
 864         /* Set of basic statistics from ENA */
 865         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 866                                           ena_stats.rx_pkts_low);
 867         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 868                                           ena_stats.tx_pkts_low);
 869         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 870                                         ena_stats.rx_bytes_low);
 871         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 872                                         ena_stats.tx_bytes_low);
 873         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 874                                          ena_stats.rx_drops_low);
 875
 876         /* Driver related stats */
 877         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 878         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 879         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 880         return 0;
 881 }
 882
 883 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 884 {
 885         struct ena_adapter *adapter;
 886         struct ena_com_dev *ena_dev;
 887         int rc = 0;
 888
 889         ena_assert_msg(dev->data != NULL, "Uninitialized device");
 890         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
 891         adapter = (struct ena_adapter *)(dev->data->dev_private);
 892
 893         ena_dev = &adapter->ena_dev;
 894         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
 895
 896         if (mtu > ena_get_mtu_conf(adapter)) {
 897                 RTE_LOG(ERR, PMD,
 898                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
 899                         mtu, ena_get_mtu_conf(adapter));
 900                 rc = -EINVAL;
 901                 goto err;
 902         }
 903
 904         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 905         if (rc)
 906                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
 907         else
 908                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
 909
 910 err:
 911         return rc;
 912 }
 913
 914 static int ena_start(struct rte_eth_dev *dev)
 915 {
 916         struct ena_adapter *adapter =
 917                 (struct ena_adapter *)(dev->data->dev_private);
 918         int rc = 0;
 919
 920         rc = ena_check_valid_conf(adapter);
 921         if (rc)
 922                 return rc;
 923
 924         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
 925         if (rc)
 926                 return rc;
 927
 928         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
 929         if (rc)
 930                 return rc;
 931
 932         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
 933             ETH_MQ_RX_RSS_FLAG) {
 934                 rc = ena_rss_init_default(adapter);
 935                 if (rc)
 936                         return rc;
 937         }
 938
 939         ena_stats_restart(dev);
 940
 941         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 942
 943         return 0;
 944 }
 945
 946 static void ena_stop(struct rte_eth_dev *dev)
 947 {
 948         struct ena_adapter *adapter =
 949                 (struct ena_adapter *)(dev->data->dev_private);
 950
 951         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 952 }
 953
 954 static int ena_queue_restart(struct ena_ring *ring)
 955 {
 956         int rc, bufs_num;
 957
 958         ena_assert_msg(ring->configured == 1,
 959                        "Trying to restart unconfigured queue\n");
 960
 961         ring->next_to_clean = 0;
 962         ring->next_to_use = 0;
 963
 964         if (ring->type == ENA_RING_TYPE_TX)
 965                 return 0;
 966
 967         bufs_num = ring->ring_size - 1;
 968         rc = ena_populate_rx_queue(ring, bufs_num);
 969         if (rc != bufs_num) {
 970                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
 971                 return (-1);
 972         }
 973
 974         return 0;
 975 }
 976
 977 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
 978                               uint16_t queue_idx,
 979                               uint16_t nb_desc,
 980                               __rte_unused unsigned int socket_id,
 981                               const struct rte_eth_txconf *tx_conf)
 982 {
 983         struct ena_com_create_io_ctx ctx =
 984                 /* policy set to _HOST just to satisfy icc compiler */
 985                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
 986                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
 987         struct ena_ring *txq = NULL;
 988         struct ena_adapter *adapter =
 989                 (struct ena_adapter *)(dev->data->dev_private);
 990         unsigned int i;
 991         int ena_qid;
 992         int rc;
 993         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 994
 995         txq = &adapter->tx_ring[queue_idx];
 996
 997         if (txq->configured) {
 998                 RTE_LOG(CRIT, PMD,
 999                         "API violation. Queue %d is already configured\n",
1000                         queue_idx);
1001                 return -1;
1002         }
1003
1004         if (!rte_is_power_of_2(nb_desc)) {
1005                 RTE_LOG(ERR, PMD,
1006                         "Unsupported size of RX queue: %d is not a power of 2.",
1007                         nb_desc);
1008                 return -EINVAL;
1009         }
1010
1011         if (nb_desc > adapter->tx_ring_size) {
1012                 RTE_LOG(ERR, PMD,
1013                         "Unsupported size of TX queue (max size: %d)\n",
1014                         adapter->tx_ring_size);
1015                 return -EINVAL;
1016         }
1017
1018         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1019
1020         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1021         ctx.qid = ena_qid;
1022         ctx.msix_vector = -1; /* admin interrupts not used */
1023         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1024         ctx.queue_size = adapter->tx_ring_size;
1025         ctx.numa_node = ena_cpu_to_node(queue_idx);
1026
1027         rc = ena_com_create_io_queue(ena_dev, &ctx);
1028         if (rc) {
1029                 RTE_LOG(ERR, PMD,
1030                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1031                         queue_idx, ena_qid, rc);
1032         }
1033         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1034         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1035
1036         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1037                                      &txq->ena_com_io_sq,
1038                                      &txq->ena_com_io_cq);
1039         if (rc) {
1040                 RTE_LOG(ERR, PMD,
1041                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1042                         queue_idx, rc);
1043                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1044                 goto err;
1045         }
1046
1047         txq->port_id = dev->data->port_id;
1048         txq->next_to_clean = 0;
1049         txq->next_to_use = 0;
1050         txq->ring_size = nb_desc;
1051
1052         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1053                                           sizeof(struct ena_tx_buffer) *
1054                                           txq->ring_size,
1055                                           RTE_CACHE_LINE_SIZE);
1056         if (!txq->tx_buffer_info) {
1057                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1058                 return -ENOMEM;
1059         }
1060
1061         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1062                                          sizeof(u16) * txq->ring_size,
1063                                          RTE_CACHE_LINE_SIZE);
1064         if (!txq->empty_tx_reqs) {
1065                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1066                 rte_free(txq->tx_buffer_info);
1067                 return -ENOMEM;
1068         }
1069         for (i = 0; i < txq->ring_size; i++)
1070                 txq->empty_tx_reqs[i] = i;
1071
1072         txq->offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1073
1074         /* Store pointer to this queue in upper layer */
1075         txq->configured = 1;
1076         dev->data->tx_queues[queue_idx] = txq;
1077 err:
1078         return rc;
1079 }
1080
1081 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1082                               uint16_t queue_idx,
1083                               uint16_t nb_desc,
1084                               __rte_unused unsigned int socket_id,
1085                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1086                               struct rte_mempool *mp)
1087 {
1088         struct ena_com_create_io_ctx ctx =
1089                 /* policy set to _HOST just to satisfy icc compiler */
1090                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1091                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1092         struct ena_adapter *adapter =
1093                 (struct ena_adapter *)(dev->data->dev_private);
1094         struct ena_ring *rxq = NULL;
1095         uint16_t ena_qid = 0;
1096         int rc = 0;
1097         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1098
1099         rxq = &adapter->rx_ring[queue_idx];
1100         if (rxq->configured) {
1101                 RTE_LOG(CRIT, PMD,
1102                         "API violation. Queue %d is already configured\n",
1103                         queue_idx);
1104                 return -1;
1105         }
1106
1107         if (!rte_is_power_of_2(nb_desc)) {
1108                 RTE_LOG(ERR, PMD,
1109                         "Unsupported size of TX queue: %d is not a power of 2.",
1110                         nb_desc);
1111                 return -EINVAL;
1112         }
1113
1114         if (nb_desc > adapter->rx_ring_size) {
1115                 RTE_LOG(ERR, PMD,
1116                         "Unsupported size of RX queue (max size: %d)\n",
1117                         adapter->rx_ring_size);
1118                 return -EINVAL;
1119         }
1120
1121         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1122
1123         ctx.qid = ena_qid;
1124         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1125         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1126         ctx.msix_vector = -1; /* admin interrupts not used */
1127         ctx.queue_size = adapter->rx_ring_size;
1128         ctx.numa_node = ena_cpu_to_node(queue_idx);
1129
1130         rc = ena_com_create_io_queue(ena_dev, &ctx);
1131         if (rc)
1132                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1133                         queue_idx, rc);
1134
1135         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1136         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1137
1138         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1139                                      &rxq->ena_com_io_sq,
1140                                      &rxq->ena_com_io_cq);
1141         if (rc) {
1142                 RTE_LOG(ERR, PMD,
1143                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1144                         queue_idx, rc);
1145                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1146         }
1147
1148         rxq->port_id = dev->data->port_id;
1149         rxq->next_to_clean = 0;
1150         rxq->next_to_use = 0;
1151         rxq->ring_size = nb_desc;
1152         rxq->mb_pool = mp;
1153
1154         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1155                                           sizeof(struct rte_mbuf *) * nb_desc,
1156                                           RTE_CACHE_LINE_SIZE);
1157         if (!rxq->rx_buffer_info) {
1158                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1159                 return -ENOMEM;
1160         }
1161
1162         /* Store pointer to this queue in upper layer */
1163         rxq->configured = 1;
1164         dev->data->rx_queues[queue_idx] = rxq;
1165
1166         return rc;
1167 }
1168
1169 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1170 {
1171         unsigned int i;
1172         int rc;
1173         uint16_t ring_size = rxq->ring_size;
1174         uint16_t ring_mask = ring_size - 1;
1175         uint16_t next_to_use = rxq->next_to_use;
1176         uint16_t in_use;
1177         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1178
1179         if (unlikely(!count))
1180                 return 0;
1181
1182         in_use = rxq->next_to_use - rxq->next_to_clean;
1183         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1184
1185         count = RTE_MIN(count,
1186                         (uint16_t)(ring_size - (next_to_use & ring_mask)));
1187
1188         /* get resources for incoming packets */
1189         rc = rte_mempool_get_bulk(rxq->mb_pool,
1190                                   (void **)(&mbufs[next_to_use & ring_mask]),
1191                                   count);
1192         if (unlikely(rc < 0)) {
1193                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1194                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1195                 return 0;
1196         }
1197
1198         for (i = 0; i < count; i++) {
1199                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1200                 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1201                 struct ena_com_buf ebuf;
1202
1203                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1204                 /* prepare physical address for DMA transaction */
1205                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1206                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1207                 /* pass resource to device */
1208                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1209                                                 &ebuf, next_to_use_masked);
1210                 if (unlikely(rc)) {
1211                         rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1212                                              count - i);
1213                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1214                         break;
1215                 }
1216                 next_to_use++;
1217         }
1218
1219         /* When we submitted free recources to device... */
1220         if (i > 0) {
1221                 /* ...let HW know that it can fill buffers with data */
1222                 rte_wmb();
1223                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1224
1225                 rxq->next_to_use = next_to_use;
1226         }
1227
1228         return i;
1229 }
1230
1231 static int ena_device_init(struct ena_com_dev *ena_dev,
1232                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1233 {
1234         uint32_t aenq_groups;
1235         int rc;
1236         bool readless_supported;
1237
1238         /* Initialize mmio registers */
1239         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1240         if (rc) {
1241                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1242                 return rc;
1243         }
1244
1245         /* The PCIe configuration space revision id indicate if mmio reg
1246          * read is disabled.
1247          */
1248         readless_supported =
1249                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1250                                & ENA_MMIO_DISABLE_REG_READ);
1251         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1252
1253         /* reset device */
1254         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1255         if (rc) {
1256                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1257                 goto err_mmio_read_less;
1258         }
1259
1260         /* check FW version */
1261         rc = ena_com_validate_version(ena_dev);
1262         if (rc) {
1263                 RTE_LOG(ERR, PMD, "device version is too low\n");
1264                 goto err_mmio_read_less;
1265         }
1266
1267         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1268
1269         /* ENA device administration layer init */
1270         rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
1271         if (rc) {
1272                 RTE_LOG(ERR, PMD,
1273                         "cannot initialize ena admin queue with device\n");
1274                 goto err_mmio_read_less;
1275         }
1276
1277         /* To enable the msix interrupts the driver needs to know the number
1278          * of queues. So the driver uses polling mode to retrieve this
1279          * information.
1280          */
1281         ena_com_set_admin_polling_mode(ena_dev, true);
1282
1283         ena_config_host_info(ena_dev);
1284
1285         /* Get Device Attributes and features */
1286         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1287         if (rc) {
1288                 RTE_LOG(ERR, PMD,
1289                         "cannot get attribute for ena device rc= %d\n", rc);
1290                 goto err_admin_init;
1291         }
1292
1293         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE);
1294
1295         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1296         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1297         if (rc) {
1298                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1299                 goto err_admin_init;
1300         }
1301
1302         return 0;
1303
1304 err_admin_init:
1305         ena_com_admin_destroy(ena_dev);
1306
1307 err_mmio_read_less:
1308         ena_com_mmio_reg_read_request_destroy(ena_dev);
1309
1310         return rc;
1311 }
1312
1313 static void ena_interrupt_handler_rte(void *cb_arg)
1314 {
1315         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1316         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1317
1318         ena_com_admin_q_comp_intr_handler(ena_dev);
1319         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1320                 ena_com_aenq_intr_handler(ena_dev, adapter);
1321 }
1322
1323 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1324 {
1325         struct rte_pci_device *pci_dev;
1326         struct rte_intr_handle *intr_handle;
1327         struct ena_adapter *adapter =
1328                 (struct ena_adapter *)(eth_dev->data->dev_private);
1329         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1330         struct ena_com_dev_get_features_ctx get_feat_ctx;
1331         int queue_size, rc;
1332
1333         static int adapters_found;
1334
1335         memset(adapter, 0, sizeof(struct ena_adapter));
1336         ena_dev = &adapter->ena_dev;
1337
1338         eth_dev->dev_ops = &ena_dev_ops;
1339         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1340         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1341         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1342         adapter->rte_eth_dev_data = eth_dev->data;
1343         adapter->rte_dev = eth_dev;
1344
1345         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1346                 return 0;
1347
1348         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1349         adapter->pdev = pci_dev;
1350
1351         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1352                      pci_dev->addr.domain,
1353                      pci_dev->addr.bus,
1354                      pci_dev->addr.devid,
1355                      pci_dev->addr.function);
1356
1357         intr_handle = &pci_dev->intr_handle;
1358
1359         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1360         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1361
1362         if (!adapter->regs) {
1363                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1364                              ENA_REGS_BAR);
1365                 return -ENXIO;
1366         }
1367
1368         ena_dev->reg_bar = adapter->regs;
1369         ena_dev->dmadev = adapter->pdev;
1370
1371         adapter->id_number = adapters_found;
1372
1373         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1374                  adapter->id_number);
1375
1376         /* device specific initialization routine */
1377         rc = ena_device_init(ena_dev, &get_feat_ctx);
1378         if (rc) {
1379                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1380                 return -1;
1381         }
1382
1383         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1384         adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1385
1386         queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1387         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1388                 return -EFAULT;
1389
1390         adapter->tx_ring_size = queue_size;
1391         adapter->rx_ring_size = queue_size;
1392
1393         /* prepare ring structures */
1394         ena_init_rings(adapter);
1395
1396         ena_config_debug_area(adapter);
1397
1398         /* Set max MTU for this device */
1399         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1400
1401         /* set device support for TSO */
1402         adapter->tso4_supported = get_feat_ctx.offload.tx &
1403                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1404
1405         /* Copy MAC address and point DPDK to it */
1406         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1407         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1408                         (struct ether_addr *)adapter->mac_addr);
1409
1410         adapter->drv_stats = rte_zmalloc("adapter stats",
1411                                          sizeof(*adapter->drv_stats),
1412                                          RTE_CACHE_LINE_SIZE);
1413         if (!adapter->drv_stats) {
1414                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1415                 return -ENOMEM;
1416         }
1417
1418         rte_intr_callback_register(intr_handle,
1419                                    ena_interrupt_handler_rte,
1420                                    adapter);
1421         rte_intr_enable(intr_handle);
1422         ena_com_set_admin_polling_mode(ena_dev, false);
1423         ena_com_admin_aenq_enable(ena_dev);
1424
1425         adapters_found++;
1426         adapter->state = ENA_ADAPTER_STATE_INIT;
1427
1428         return 0;
1429 }
1430
1431 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1432 {
1433         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1434         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1435         struct ena_adapter *adapter =
1436                 (struct ena_adapter *)(eth_dev->data->dev_private);
1437
1438         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1439                 return -EPERM;
1440
1441         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1442                 ena_close(eth_dev);
1443
1444         eth_dev->dev_ops = NULL;
1445         eth_dev->rx_pkt_burst = NULL;
1446         eth_dev->tx_pkt_burst = NULL;
1447         eth_dev->tx_pkt_prepare = NULL;
1448
1449         rte_free(adapter->drv_stats);
1450         adapter->drv_stats = NULL;
1451
1452         rte_intr_disable(intr_handle);
1453         rte_intr_callback_unregister(intr_handle,
1454                                      ena_interrupt_handler_rte,
1455                                      adapter);
1456
1457         adapter->state = ENA_ADAPTER_STATE_FREE;
1458
1459         return 0;
1460 }
1461
1462 static int ena_dev_configure(struct rte_eth_dev *dev)
1463 {
1464         struct ena_adapter *adapter =
1465                 (struct ena_adapter *)(dev->data->dev_private);
1466
1467         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1468
1469         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1470         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1471         return 0;
1472 }
1473
1474 static void ena_init_rings(struct ena_adapter *adapter)
1475 {
1476         int i;
1477
1478         for (i = 0; i < adapter->num_queues; i++) {
1479                 struct ena_ring *ring = &adapter->tx_ring[i];
1480
1481                 ring->configured = 0;
1482                 ring->type = ENA_RING_TYPE_TX;
1483                 ring->adapter = adapter;
1484                 ring->id = i;
1485                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1486                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1487         }
1488
1489         for (i = 0; i < adapter->num_queues; i++) {
1490                 struct ena_ring *ring = &adapter->rx_ring[i];
1491
1492                 ring->configured = 0;
1493                 ring->type = ENA_RING_TYPE_RX;
1494                 ring->adapter = adapter;
1495                 ring->id = i;
1496         }
1497 }
1498
1499 static void ena_infos_get(struct rte_eth_dev *dev,
1500                           struct rte_eth_dev_info *dev_info)
1501 {
1502         struct ena_adapter *adapter;
1503         struct ena_com_dev *ena_dev;
1504         struct ena_com_dev_get_features_ctx feat;
1505         uint64_t rx_feat = 0, tx_feat = 0;
1506         int rc = 0;
1507
1508         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1509         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1510         adapter = (struct ena_adapter *)(dev->data->dev_private);
1511
1512         ena_dev = &adapter->ena_dev;
1513         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1514
1515         dev_info->speed_capa =
1516                         ETH_LINK_SPEED_1G   |
1517                         ETH_LINK_SPEED_2_5G |
1518                         ETH_LINK_SPEED_5G   |
1519                         ETH_LINK_SPEED_10G  |
1520                         ETH_LINK_SPEED_25G  |
1521                         ETH_LINK_SPEED_40G  |
1522                         ETH_LINK_SPEED_50G  |
1523                         ETH_LINK_SPEED_100G;
1524
1525         /* Get supported features from HW */
1526         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1527         if (unlikely(rc)) {
1528                 RTE_LOG(ERR, PMD,
1529                         "Cannot get attribute for ena device rc= %d\n", rc);
1530                 return;
1531         }
1532
1533         /* Set Tx & Rx features available for device */
1534         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1535                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1536
1537         if (feat.offload.tx &
1538             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1539                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1540                         DEV_TX_OFFLOAD_UDP_CKSUM |
1541                         DEV_TX_OFFLOAD_TCP_CKSUM;
1542
1543         if (feat.offload.rx_supported &
1544             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1545                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1546                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1547                         DEV_RX_OFFLOAD_TCP_CKSUM;
1548
1549         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1550
1551         /* Inform framework about available features */
1552         dev_info->rx_offload_capa = rx_feat;
1553         dev_info->rx_queue_offload_capa = rx_feat;
1554         dev_info->tx_offload_capa = tx_feat;
1555         dev_info->tx_queue_offload_capa = tx_feat;
1556
1557         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1558         dev_info->max_rx_pktlen  = adapter->max_mtu;
1559         dev_info->max_mac_addrs = 1;
1560
1561         dev_info->max_rx_queues = adapter->num_queues;
1562         dev_info->max_tx_queues = adapter->num_queues;
1563         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1564
1565         adapter->tx_supported_offloads = tx_feat;
1566         adapter->rx_supported_offloads = rx_feat;
1567 }
1568
1569 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1570                                   uint16_t nb_pkts)
1571 {
1572         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1573         unsigned int ring_size = rx_ring->ring_size;
1574         unsigned int ring_mask = ring_size - 1;
1575         uint16_t next_to_clean = rx_ring->next_to_clean;
1576         uint16_t desc_in_use = 0;
1577         unsigned int recv_idx = 0;
1578         struct rte_mbuf *mbuf = NULL;
1579         struct rte_mbuf *mbuf_head = NULL;
1580         struct rte_mbuf *mbuf_prev = NULL;
1581         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1582         unsigned int completed;
1583
1584         struct ena_com_rx_ctx ena_rx_ctx;
1585         int rc = 0;
1586
1587         /* Check adapter state */
1588         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1589                 RTE_LOG(ALERT, PMD,
1590                         "Trying to receive pkts while device is NOT running\n");
1591                 return 0;
1592         }
1593
1594         desc_in_use = rx_ring->next_to_use - next_to_clean;
1595         if (unlikely(nb_pkts > desc_in_use))
1596                 nb_pkts = desc_in_use;
1597
1598         for (completed = 0; completed < nb_pkts; completed++) {
1599                 int segments = 0;
1600
1601                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1602                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1603                 ena_rx_ctx.descs = 0;
1604                 /* receive packet context */
1605                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1606                                     rx_ring->ena_com_io_sq,
1607                                     &ena_rx_ctx);
1608                 if (unlikely(rc)) {
1609                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1610                         return 0;
1611                 }
1612
1613                 if (unlikely(ena_rx_ctx.descs == 0))
1614                         break;
1615
1616                 while (segments < ena_rx_ctx.descs) {
1617                         mbuf = rx_buff_info[next_to_clean & ring_mask];
1618                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1619                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1620                         mbuf->refcnt = 1;
1621                         mbuf->next = NULL;
1622                         if (segments == 0) {
1623                                 mbuf->nb_segs = ena_rx_ctx.descs;
1624                                 mbuf->port = rx_ring->port_id;
1625                                 mbuf->pkt_len = 0;
1626                                 mbuf_head = mbuf;
1627                         } else {
1628                                 /* for multi-segment pkts create mbuf chain */
1629                                 mbuf_prev->next = mbuf;
1630                         }
1631                         mbuf_head->pkt_len += mbuf->data_len;
1632
1633                         mbuf_prev = mbuf;
1634                         segments++;
1635                         next_to_clean++;
1636                 }
1637
1638                 /* fill mbuf attributes if any */
1639                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1640                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1641
1642                 /* pass to DPDK application head mbuf */
1643                 rx_pkts[recv_idx] = mbuf_head;
1644                 recv_idx++;
1645         }
1646
1647         rx_ring->next_to_clean = next_to_clean;
1648
1649         desc_in_use = desc_in_use - completed + 1;
1650         /* Burst refill to save doorbells, memory barriers, const interval */
1651         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1652                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1653
1654         return recv_idx;
1655 }
1656
1657 static uint16_t
1658 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1659                 uint16_t nb_pkts)
1660 {
1661         int32_t ret;
1662         uint32_t i;
1663         struct rte_mbuf *m;
1664         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1665         struct ipv4_hdr *ip_hdr;
1666         uint64_t ol_flags;
1667         uint16_t frag_field;
1668
1669         for (i = 0; i != nb_pkts; i++) {
1670                 m = tx_pkts[i];
1671                 ol_flags = m->ol_flags;
1672
1673                 if (!(ol_flags & PKT_TX_IPV4))
1674                         continue;
1675
1676                 /* If there was not L2 header length specified, assume it is
1677                  * length of the ethernet header.
1678                  */
1679                 if (unlikely(m->l2_len == 0))
1680                         m->l2_len = sizeof(struct ether_hdr);
1681
1682                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1683                                                  m->l2_len);
1684                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1685
1686                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1687                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1688
1689                         /* If IPv4 header has DF flag enabled and TSO support is
1690                          * disabled, partial chcecksum should not be calculated.
1691                          */
1692                         if (!tx_ring->adapter->tso4_supported)
1693                                 continue;
1694                 }
1695
1696                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1697                                 (ol_flags & PKT_TX_L4_MASK) ==
1698                                 PKT_TX_SCTP_CKSUM) {
1699                         rte_errno = -ENOTSUP;
1700                         return i;
1701                 }
1702
1703 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1704                 ret = rte_validate_tx_offload(m);
1705                 if (ret != 0) {
1706                         rte_errno = ret;
1707                         return i;
1708                 }
1709 #endif
1710
1711                 /* In case we are supposed to TSO and have DF not set (DF=0)
1712                  * hardware must be provided with partial checksum, otherwise
1713                  * it will take care of necessary calculations.
1714                  */
1715
1716                 ret = rte_net_intel_cksum_flags_prepare(m,
1717                         ol_flags & ~PKT_TX_TCP_SEG);
1718                 if (ret != 0) {
1719                         rte_errno = ret;
1720                         return i;
1721                 }
1722         }
1723
1724         return i;
1725 }
1726
1727 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1728                                   uint16_t nb_pkts)
1729 {
1730         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1731         uint16_t next_to_use = tx_ring->next_to_use;
1732         uint16_t next_to_clean = tx_ring->next_to_clean;
1733         struct rte_mbuf *mbuf;
1734         unsigned int ring_size = tx_ring->ring_size;
1735         unsigned int ring_mask = ring_size - 1;
1736         struct ena_com_tx_ctx ena_tx_ctx;
1737         struct ena_tx_buffer *tx_info;
1738         struct ena_com_buf *ebuf;
1739         uint16_t rc, req_id, total_tx_descs = 0;
1740         uint16_t sent_idx = 0, empty_tx_reqs;
1741         int nb_hw_desc;
1742
1743         /* Check adapter state */
1744         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1745                 RTE_LOG(ALERT, PMD,
1746                         "Trying to xmit pkts while device is NOT running\n");
1747                 return 0;
1748         }
1749
1750         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1751         if (nb_pkts > empty_tx_reqs)
1752                 nb_pkts = empty_tx_reqs;
1753
1754         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1755                 mbuf = tx_pkts[sent_idx];
1756
1757                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1758                 tx_info = &tx_ring->tx_buffer_info[req_id];
1759                 tx_info->mbuf = mbuf;
1760                 tx_info->num_of_bufs = 0;
1761                 ebuf = tx_info->bufs;
1762
1763                 /* Prepare TX context */
1764                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1765                 memset(&ena_tx_ctx.ena_meta, 0x0,
1766                        sizeof(struct ena_com_tx_meta));
1767                 ena_tx_ctx.ena_bufs = ebuf;
1768                 ena_tx_ctx.req_id = req_id;
1769                 if (tx_ring->tx_mem_queue_type ==
1770                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1771                         /* prepare the push buffer with
1772                          * virtual address of the data
1773                          */
1774                         ena_tx_ctx.header_len =
1775                                 RTE_MIN(mbuf->data_len,
1776                                         tx_ring->tx_max_header_size);
1777                         ena_tx_ctx.push_header =
1778                                 (void *)((char *)mbuf->buf_addr +
1779                                          mbuf->data_off);
1780                 } /* there's no else as we take advantage of memset zeroing */
1781
1782                 /* Set TX offloads flags, if applicable */
1783                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
1784
1785                 if (unlikely(mbuf->ol_flags &
1786                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1787                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1788
1789                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1790
1791                 /* Process first segment taking into
1792                  * consideration pushed header
1793                  */
1794                 if (mbuf->data_len > ena_tx_ctx.header_len) {
1795                         ebuf->paddr = mbuf->buf_iova +
1796                                       mbuf->data_off +
1797                                       ena_tx_ctx.header_len;
1798                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1799                         ebuf++;
1800                         tx_info->num_of_bufs++;
1801                 }
1802
1803                 while ((mbuf = mbuf->next) != NULL) {
1804                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
1805                         ebuf->len = mbuf->data_len;
1806                         ebuf++;
1807                         tx_info->num_of_bufs++;
1808                 }
1809
1810                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1811
1812                 /* Write data to device */
1813                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1814                                         &ena_tx_ctx, &nb_hw_desc);
1815                 if (unlikely(rc))
1816                         break;
1817
1818                 tx_info->tx_descs = nb_hw_desc;
1819
1820                 next_to_use++;
1821         }
1822
1823         /* If there are ready packets to be xmitted... */
1824         if (sent_idx > 0) {
1825                 /* ...let HW do its best :-) */
1826                 rte_wmb();
1827                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1828
1829                 tx_ring->next_to_use = next_to_use;
1830         }
1831
1832         /* Clear complete packets  */
1833         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1834                 /* Get Tx info & store how many descs were processed  */
1835                 tx_info = &tx_ring->tx_buffer_info[req_id];
1836                 total_tx_descs += tx_info->tx_descs;
1837
1838                 /* Free whole mbuf chain  */
1839                 mbuf = tx_info->mbuf;
1840                 rte_pktmbuf_free(mbuf);
1841                 tx_info->mbuf = NULL;
1842
1843                 /* Put back descriptor to the ring for reuse */
1844                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
1845                 next_to_clean++;
1846
1847                 /* If too many descs to clean, leave it for another run */
1848                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1849                         break;
1850         }
1851
1852         if (total_tx_descs > 0) {
1853                 /* acknowledge completion of sent packets */
1854                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1855                 tx_ring->next_to_clean = next_to_clean;
1856         }
1857
1858         return sent_idx;
1859 }
1860
1861 /*********************************************************************
1862  *  PMD configuration
1863  *********************************************************************/
1864 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1865         struct rte_pci_device *pci_dev)
1866 {
1867         return rte_eth_dev_pci_generic_probe(pci_dev,
1868                 sizeof(struct ena_adapter), eth_ena_dev_init);
1869 }
1870
1871 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
1872 {
1873         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
1874 }
1875
1876 static struct rte_pci_driver rte_ena_pmd = {
1877         .id_table = pci_id_ena_map,
1878         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1879         .probe = eth_ena_pci_probe,
1880         .remove = eth_ena_pci_remove,
1881 };
1882
1883 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
1884 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
1885 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
1886
1887 RTE_INIT(ena_init_log);
1888 static void
1889 ena_init_log(void)
1890 {
1891         ena_logtype_init = rte_log_register("pmd.net.ena.init");
1892         if (ena_logtype_init >= 0)
1893                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
1894         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
1895         if (ena_logtype_driver >= 0)
1896                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
1897 }
1898
1899 /******************************************************************************
1900  ******************************** AENQ Handlers *******************************
1901  *****************************************************************************/
1902 static void ena_update_on_link_change(void *adapter_data,
1903                                       struct ena_admin_aenq_entry *aenq_e)
1904 {
1905         struct rte_eth_dev *eth_dev;
1906         struct ena_adapter *adapter;
1907         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
1908         uint32_t status;
1909
1910         adapter = (struct ena_adapter *)adapter_data;
1911         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
1912         eth_dev = adapter->rte_dev;
1913
1914         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
1915         adapter->link_status = status;
1916
1917         ena_link_update(eth_dev, 0);
1918         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1919 }
1920
1921 /**
1922  * This handler will called for unknown event group or unimplemented handlers
1923  **/
1924 static void unimplemented_aenq_handler(__rte_unused void *data,
1925                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
1926 {
1927         // Unimplemented handler
1928 }
1929
1930 static struct ena_aenq_handlers aenq_handlers = {
1931         .handlers = {
1932                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
1933                 [ENA_ADMIN_NOTIFICATION] = unimplemented_aenq_handler,
1934                 [ENA_ADMIN_KEEP_ALIVE] = unimplemented_aenq_handler
1935         },
1936         .unimplemented_handler = unimplemented_aenq_handler
1937 };