drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 0
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 enum ethtool_stringset {
  89         ETH_SS_TEST             = 0,
  90         ETH_SS_STATS,
  91 };
  92
  93 struct ena_stats {
  94         char name[ETH_GSTRING_LEN];
  95         int stat_offset;
  96 };
  97
  98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
  99         .name = #stat, \
 100         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 101 }
 102
 103 #define ENA_STAT_ENTRY(stat, stat_type) { \
 104         .name = #stat, \
 105         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 106 }
 107
 108 #define ENA_STAT_RX_ENTRY(stat) \
 109         ENA_STAT_ENTRY(stat, rx)
 110
 111 #define ENA_STAT_TX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, tx)
 113
 114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, dev)
 116
 117 /*
 118  * Each rte_memzone should have unique name.
 119  * To satisfy it, count number of allocation and add it to name.
 120  */
 121 uint32_t ena_alloc_cnt;
 122
 123 static const struct ena_stats ena_stats_global_strings[] = {
 124         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 125         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 126         ENA_STAT_GLOBAL_ENTRY(io_resume),
 127         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 128         ENA_STAT_GLOBAL_ENTRY(interface_up),
 129         ENA_STAT_GLOBAL_ENTRY(interface_down),
 130         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 131 };
 132
 133 static const struct ena_stats ena_stats_tx_strings[] = {
 134         ENA_STAT_TX_ENTRY(cnt),
 135         ENA_STAT_TX_ENTRY(bytes),
 136         ENA_STAT_TX_ENTRY(queue_stop),
 137         ENA_STAT_TX_ENTRY(queue_wakeup),
 138         ENA_STAT_TX_ENTRY(dma_mapping_err),
 139         ENA_STAT_TX_ENTRY(linearize),
 140         ENA_STAT_TX_ENTRY(linearize_failed),
 141         ENA_STAT_TX_ENTRY(tx_poll),
 142         ENA_STAT_TX_ENTRY(doorbells),
 143         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 144         ENA_STAT_TX_ENTRY(missing_tx_comp),
 145         ENA_STAT_TX_ENTRY(bad_req_id),
 146 };
 147
 148 static const struct ena_stats ena_stats_rx_strings[] = {
 149         ENA_STAT_RX_ENTRY(cnt),
 150         ENA_STAT_RX_ENTRY(bytes),
 151         ENA_STAT_RX_ENTRY(refil_partial),
 152         ENA_STAT_RX_ENTRY(bad_csum),
 153         ENA_STAT_RX_ENTRY(page_alloc_fail),
 154         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 155         ENA_STAT_RX_ENTRY(dma_mapping_err),
 156         ENA_STAT_RX_ENTRY(bad_desc_num),
 157         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 158 };
 159
 160 static const struct ena_stats ena_stats_ena_com_strings[] = {
 161         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 162         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 163         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 164         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 165         ENA_STAT_ENA_COM_ENTRY(no_completion),
 166 };
 167
 168 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 169 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 170 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 171 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 172
 173 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 174                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 175                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 176                         DEV_TX_OFFLOAD_TCP_TSO)
 177 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 178                        PKT_TX_IP_CKSUM |\
 179                        PKT_TX_TCP_SEG)
 180
 181 /** Vendor ID used by Amazon devices */
 182 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 183 /** Amazon devices */
 184 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 185 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 186
 187 #define ENA_TX_OFFLOAD_MASK     (\
 188         PKT_TX_L4_MASK |         \
 189         PKT_TX_IP_CKSUM |        \
 190         PKT_TX_TCP_SEG)
 191
 192 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 193         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 194
 195 int ena_logtype_init;
 196 int ena_logtype_driver;
 197
 198 static const struct rte_pci_id pci_id_ena_map[] = {
 199         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 200         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 201         { .device_id = 0 },
 202 };
 203
 204 static struct ena_aenq_handlers aenq_handlers;
 205
 206 static int ena_device_init(struct ena_com_dev *ena_dev,
 207                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 208 static int ena_dev_configure(struct rte_eth_dev *dev);
 209 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 210                                   uint16_t nb_pkts);
 211 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 212                 uint16_t nb_pkts);
 213 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 214                               uint16_t nb_desc, unsigned int socket_id,
 215                               const struct rte_eth_txconf *tx_conf);
 216 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 217                               uint16_t nb_desc, unsigned int socket_id,
 218                               const struct rte_eth_rxconf *rx_conf,
 219                               struct rte_mempool *mp);
 220 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 221                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 222 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 223 static void ena_init_rings(struct ena_adapter *adapter);
 224 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 225 static int ena_start(struct rte_eth_dev *dev);
 226 static void ena_stop(struct rte_eth_dev *dev);
 227 static void ena_close(struct rte_eth_dev *dev);
 228 static int ena_dev_reset(struct rte_eth_dev *dev);
 229 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 230 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 231 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 232 static void ena_rx_queue_release(void *queue);
 233 static void ena_tx_queue_release(void *queue);
 234 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 235 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 236 static int ena_link_update(struct rte_eth_dev *dev,
 237                            int wait_to_complete);
 238 static int ena_queue_restart(struct ena_ring *ring);
 239 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 240                                  enum ena_ring_type ring_type);
 241 static void ena_stats_restart(struct rte_eth_dev *dev);
 242 static void ena_infos_get(struct rte_eth_dev *dev,
 243                           struct rte_eth_dev_info *dev_info);
 244 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 245                                struct rte_eth_rss_reta_entry64 *reta_conf,
 246                                uint16_t reta_size);
 247 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 248                               struct rte_eth_rss_reta_entry64 *reta_conf,
 249                               uint16_t reta_size);
 250 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 251 static void ena_interrupt_handler_rte(void *cb_arg);
 252 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 253
 254 static const struct eth_dev_ops ena_dev_ops = {
 255         .dev_configure        = ena_dev_configure,
 256         .dev_infos_get        = ena_infos_get,
 257         .rx_queue_setup       = ena_rx_queue_setup,
 258         .tx_queue_setup       = ena_tx_queue_setup,
 259         .dev_start            = ena_start,
 260         .dev_stop             = ena_stop,
 261         .link_update          = ena_link_update,
 262         .stats_get            = ena_stats_get,
 263         .mtu_set              = ena_mtu_set,
 264         .rx_queue_release     = ena_rx_queue_release,
 265         .tx_queue_release     = ena_tx_queue_release,
 266         .dev_close            = ena_close,
 267         .dev_reset            = ena_dev_reset,
 268         .reta_update          = ena_rss_reta_update,
 269         .reta_query           = ena_rss_reta_query,
 270 };
 271
 272 #define NUMA_NO_NODE    SOCKET_ID_ANY
 273
 274 static inline int ena_cpu_to_node(int cpu)
 275 {
 276         struct rte_config *config = rte_eal_get_configuration();
 277         struct rte_fbarray *arr = &config->mem_config->memzones;
 278         const struct rte_memzone *mz;
 279
 280         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 281                 return NUMA_NO_NODE;
 282
 283         mz = rte_fbarray_get(arr, cpu);
 284
 285         return mz->socket_id;
 286 }
 287
 288 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 289                                        struct ena_com_rx_ctx *ena_rx_ctx)
 290 {
 291         uint64_t ol_flags = 0;
 292         uint32_t packet_type = 0;
 293
 294         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 295                 packet_type |= RTE_PTYPE_L4_TCP;
 296         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 297                 packet_type |= RTE_PTYPE_L4_UDP;
 298
 299         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 300                 packet_type |= RTE_PTYPE_L3_IPV4;
 301         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 302                 packet_type |= RTE_PTYPE_L3_IPV6;
 303
 304         if (unlikely(ena_rx_ctx->l4_csum_err))
 305                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 306         if (unlikely(ena_rx_ctx->l3_csum_err))
 307                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 308
 309         mbuf->ol_flags = ol_flags;
 310         mbuf->packet_type = packet_type;
 311 }
 312
 313 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 314                                        struct ena_com_tx_ctx *ena_tx_ctx,
 315                                        uint64_t queue_offloads)
 316 {
 317         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 318
 319         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 320             (queue_offloads & QUEUE_OFFLOADS)) {
 321                 /* check if TSO is required */
 322                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 323                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 324                         ena_tx_ctx->tso_enable = true;
 325
 326                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 327                 }
 328
 329                 /* check if L3 checksum is needed */
 330                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 331                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 332                         ena_tx_ctx->l3_csum_enable = true;
 333
 334                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 335                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 336                 } else {
 337                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 338
 339                         /* set don't fragment (DF) flag */
 340                         if (mbuf->packet_type &
 341                                 (RTE_PTYPE_L4_NONFRAG
 342                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 343                                 ena_tx_ctx->df = true;
 344                 }
 345
 346                 /* check if L4 checksum is needed */
 347                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 348                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 349                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 350                         ena_tx_ctx->l4_csum_enable = true;
 351                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 352                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 353                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 354                         ena_tx_ctx->l4_csum_enable = true;
 355                 } else {
 356                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 357                         ena_tx_ctx->l4_csum_enable = false;
 358                 }
 359
 360                 ena_meta->mss = mbuf->tso_segsz;
 361                 ena_meta->l3_hdr_len = mbuf->l3_len;
 362                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 363
 364                 ena_tx_ctx->meta_valid = true;
 365         } else {
 366                 ena_tx_ctx->meta_valid = false;
 367         }
 368 }
 369
 370 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 371 {
 372         struct ena_admin_host_info *host_info;
 373         int rc;
 374
 375         /* Allocate only the host info */
 376         rc = ena_com_allocate_host_info(ena_dev);
 377         if (rc) {
 378                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 379                 return;
 380         }
 381
 382         host_info = ena_dev->host_attr.host_info;
 383
 384         host_info->os_type = ENA_ADMIN_OS_DPDK;
 385         host_info->kernel_ver = RTE_VERSION;
 386         snprintf((char *)host_info->kernel_ver_str,
 387                  sizeof(host_info->kernel_ver_str),
 388                  "%s", rte_version());
 389         host_info->os_dist = RTE_VERSION;
 390         snprintf((char *)host_info->os_dist_str,
 391                  sizeof(host_info->os_dist_str),
 392                  "%s", rte_version());
 393         host_info->driver_version =
 394                 (DRV_MODULE_VER_MAJOR) |
 395                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 396                 (DRV_MODULE_VER_SUBMINOR <<
 397                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 398
 399         rc = ena_com_set_host_attributes(ena_dev);
 400         if (rc) {
 401                 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 402                 if (rc != -ENA_COM_UNSUPPORTED)
 403                         goto err;
 404         }
 405
 406         return;
 407
 408 err:
 409         ena_com_delete_host_info(ena_dev);
 410 }
 411
 412 static int
 413 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 414 {
 415         if (sset != ETH_SS_STATS)
 416                 return -EOPNOTSUPP;
 417
 418          /* Workaround for clang:
 419          * touch internal structures to prevent
 420          * compiler error
 421          */
 422         ENA_TOUCH(ena_stats_global_strings);
 423         ENA_TOUCH(ena_stats_tx_strings);
 424         ENA_TOUCH(ena_stats_rx_strings);
 425         ENA_TOUCH(ena_stats_ena_com_strings);
 426
 427         return  dev->data->nb_tx_queues *
 428                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 429                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 430 }
 431
 432 static void ena_config_debug_area(struct ena_adapter *adapter)
 433 {
 434         u32 debug_area_size;
 435         int rc, ss_count;
 436
 437         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 438         if (ss_count <= 0) {
 439                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 440                 return;
 441         }
 442
 443         /* allocate 32 bytes for each string and 64bit for the value */
 444         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 445
 446         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 447         if (rc) {
 448                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 449                 return;
 450         }
 451
 452         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 453         if (rc) {
 454                 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 455                 if (rc != -ENA_COM_UNSUPPORTED)
 456                         goto err;
 457         }
 458
 459         return;
 460 err:
 461         ena_com_delete_debug_area(&adapter->ena_dev);
 462 }
 463
 464 static void ena_close(struct rte_eth_dev *dev)
 465 {
 466         struct ena_adapter *adapter =
 467                 (struct ena_adapter *)(dev->data->dev_private);
 468
 469         ena_stop(dev);
 470         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 471
 472         ena_rx_queue_release_all(dev);
 473         ena_tx_queue_release_all(dev);
 474 }
 475
 476 static int
 477 ena_dev_reset(struct rte_eth_dev *dev)
 478 {
 479         struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
 480         struct rte_eth_dev *eth_dev;
 481         struct rte_pci_device *pci_dev;
 482         struct rte_intr_handle *intr_handle;
 483         struct ena_com_dev *ena_dev;
 484         struct ena_com_dev_get_features_ctx get_feat_ctx;
 485         struct ena_adapter *adapter;
 486         int nb_queues;
 487         int rc, i;
 488
 489         adapter = (struct ena_adapter *)(dev->data->dev_private);
 490         ena_dev = &adapter->ena_dev;
 491         eth_dev = adapter->rte_dev;
 492         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 493         intr_handle = &pci_dev->intr_handle;
 494         nb_queues = eth_dev->data->nb_rx_queues;
 495
 496         ena_com_set_admin_running_state(ena_dev, false);
 497
 498         ena_com_dev_reset(ena_dev, adapter->reset_reason);
 499
 500         for (i = 0; i < nb_queues; i++)
 501                 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
 502
 503         ena_rx_queue_release_all(eth_dev);
 504         ena_tx_queue_release_all(eth_dev);
 505
 506         rte_intr_disable(intr_handle);
 507
 508         ena_com_abort_admin_commands(ena_dev);
 509         ena_com_wait_for_abort_completion(ena_dev);
 510         ena_com_admin_destroy(ena_dev);
 511         ena_com_mmio_reg_read_request_destroy(ena_dev);
 512
 513         rc = ena_device_init(ena_dev, &get_feat_ctx);
 514         if (rc) {
 515                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 516                 return rc;
 517         }
 518
 519         rte_intr_enable(intr_handle);
 520         ena_com_set_admin_polling_mode(ena_dev, false);
 521         ena_com_admin_aenq_enable(ena_dev);
 522
 523         for (i = 0; i < nb_queues; ++i)
 524                 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring_size, 0, NULL,
 525                         mb_pool_rx[i]);
 526
 527         for (i = 0; i < nb_queues; ++i)
 528                 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring_size, 0, NULL);
 529
 530         return 0;
 531 }
 532
 533 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 534                                struct rte_eth_rss_reta_entry64 *reta_conf,
 535                                uint16_t reta_size)
 536 {
 537         struct ena_adapter *adapter =
 538                 (struct ena_adapter *)(dev->data->dev_private);
 539         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 540         int ret, i;
 541         u16 entry_value;
 542         int conf_idx;
 543         int idx;
 544
 545         if ((reta_size == 0) || (reta_conf == NULL))
 546                 return -EINVAL;
 547
 548         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 549                 RTE_LOG(WARNING, PMD,
 550                         "indirection table %d is bigger than supported (%d)\n",
 551                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 552                 ret = -EINVAL;
 553                 goto err;
 554         }
 555
 556         for (i = 0 ; i < reta_size ; i++) {
 557                 /* each reta_conf is for 64 entries.
 558                  * to support 128 we use 2 conf of 64
 559                  */
 560                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 561                 idx = i % RTE_RETA_GROUP_SIZE;
 562                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 563                         entry_value =
 564                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 565                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 566                                                                 i,
 567                                                                 entry_value);
 568                         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 569                                 RTE_LOG(ERR, PMD,
 570                                         "Cannot fill indirect table\n");
 571                                 ret = -ENOTSUP;
 572                                 goto err;
 573                         }
 574                 }
 575         }
 576
 577         ret = ena_com_indirect_table_set(ena_dev);
 578         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 579                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 580                 ret = -ENOTSUP;
 581                 goto err;
 582         }
 583
 584         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 585                 __func__, reta_size, adapter->rte_dev->data->port_id);
 586 err:
 587         return ret;
 588 }
 589
 590 /* Query redirection table. */
 591 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 592                               struct rte_eth_rss_reta_entry64 *reta_conf,
 593                               uint16_t reta_size)
 594 {
 595         struct ena_adapter *adapter =
 596                 (struct ena_adapter *)(dev->data->dev_private);
 597         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 598         int ret;
 599         int i;
 600         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 601         int reta_conf_idx;
 602         int reta_idx;
 603
 604         if (reta_size == 0 || reta_conf == NULL ||
 605             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 606                 return -EINVAL;
 607
 608         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 609         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 610                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 611                 ret = -ENOTSUP;
 612                 goto err;
 613         }
 614
 615         for (i = 0 ; i < reta_size ; i++) {
 616                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 617                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 618                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 619                         reta_conf[reta_conf_idx].reta[reta_idx] =
 620                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 621         }
 622 err:
 623         return ret;
 624 }
 625
 626 static int ena_rss_init_default(struct ena_adapter *adapter)
 627 {
 628         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 629         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 630         int rc, i;
 631         u32 val;
 632
 633         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 634         if (unlikely(rc)) {
 635                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 636                 goto err_rss_init;
 637         }
 638
 639         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 640                 val = i % nb_rx_queues;
 641                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 642                                                        ENA_IO_RXQ_IDX(val));
 643                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 644                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 645                         goto err_fill_indir;
 646                 }
 647         }
 648
 649         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 650                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 651         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 652                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 653                 goto err_fill_indir;
 654         }
 655
 656         rc = ena_com_set_default_hash_ctrl(ena_dev);
 657         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 658                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 659                 goto err_fill_indir;
 660         }
 661
 662         rc = ena_com_indirect_table_set(ena_dev);
 663         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 664                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 665                 goto err_fill_indir;
 666         }
 667         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 668                 adapter->rte_dev->data->port_id);
 669
 670         return 0;
 671
 672 err_fill_indir:
 673         ena_com_rss_destroy(ena_dev);
 674 err_rss_init:
 675
 676         return rc;
 677 }
 678
 679 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 680 {
 681         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 682         int nb_queues = dev->data->nb_rx_queues;
 683         int i;
 684
 685         for (i = 0; i < nb_queues; i++)
 686                 ena_rx_queue_release(queues[i]);
 687 }
 688
 689 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 690 {
 691         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 692         int nb_queues = dev->data->nb_tx_queues;
 693         int i;
 694
 695         for (i = 0; i < nb_queues; i++)
 696                 ena_tx_queue_release(queues[i]);
 697 }
 698
 699 static void ena_rx_queue_release(void *queue)
 700 {
 701         struct ena_ring *ring = (struct ena_ring *)queue;
 702         struct ena_adapter *adapter = ring->adapter;
 703         int ena_qid;
 704
 705         ena_assert_msg(ring->configured,
 706                        "API violation - releasing not configured queue");
 707         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 708                        "API violation");
 709
 710         /* Destroy HW queue */
 711         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 712         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 713
 714         /* Free all bufs */
 715         ena_rx_queue_release_bufs(ring);
 716
 717         /* Free ring resources */
 718         if (ring->rx_buffer_info)
 719                 rte_free(ring->rx_buffer_info);
 720         ring->rx_buffer_info = NULL;
 721
 722         ring->configured = 0;
 723
 724         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 725                 ring->port_id, ring->id);
 726 }
 727
 728 static void ena_tx_queue_release(void *queue)
 729 {
 730         struct ena_ring *ring = (struct ena_ring *)queue;
 731         struct ena_adapter *adapter = ring->adapter;
 732         int ena_qid;
 733
 734         ena_assert_msg(ring->configured,
 735                        "API violation. Releasing not configured queue");
 736         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 737                        "API violation");
 738
 739         /* Destroy HW queue */
 740         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 741         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 742
 743         /* Free all bufs */
 744         ena_tx_queue_release_bufs(ring);
 745
 746         /* Free ring resources */
 747         if (ring->tx_buffer_info)
 748                 rte_free(ring->tx_buffer_info);
 749
 750         if (ring->empty_tx_reqs)
 751                 rte_free(ring->empty_tx_reqs);
 752
 753         ring->empty_tx_reqs = NULL;
 754         ring->tx_buffer_info = NULL;
 755
 756         ring->configured = 0;
 757
 758         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 759                 ring->port_id, ring->id);
 760 }
 761
 762 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 763 {
 764         unsigned int ring_mask = ring->ring_size - 1;
 765
 766         while (ring->next_to_clean != ring->next_to_use) {
 767                 struct rte_mbuf *m =
 768                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 769
 770                 if (m)
 771                         rte_mbuf_raw_free(m);
 772
 773                 ring->next_to_clean++;
 774         }
 775 }
 776
 777 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 778 {
 779         unsigned int i;
 780
 781         for (i = 0; i < ring->ring_size; ++i) {
 782                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 783
 784                 if (tx_buf->mbuf)
 785                         rte_pktmbuf_free(tx_buf->mbuf);
 786
 787                 ring->next_to_clean++;
 788         }
 789 }
 790
 791 static int ena_link_update(struct rte_eth_dev *dev,
 792                            __rte_unused int wait_to_complete)
 793 {
 794         struct rte_eth_link *link = &dev->data->dev_link;
 795         struct ena_adapter *adapter;
 796
 797         adapter = (struct ena_adapter *)(dev->data->dev_private);
 798
 799         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 800         link->link_speed = ETH_SPEED_NUM_10G;
 801         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 802
 803         return 0;
 804 }
 805
 806 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 807                                  enum ena_ring_type ring_type)
 808 {
 809         struct ena_adapter *adapter =
 810                 (struct ena_adapter *)(dev->data->dev_private);
 811         struct ena_ring *queues = NULL;
 812         int nb_queues;
 813         int i = 0;
 814         int rc = 0;
 815
 816         if (ring_type == ENA_RING_TYPE_RX) {
 817                 queues = adapter->rx_ring;
 818                 nb_queues = dev->data->nb_rx_queues;
 819         } else {
 820                 queues = adapter->tx_ring;
 821                 nb_queues = dev->data->nb_tx_queues;
 822         }
 823         for (i = 0; i < nb_queues; i++) {
 824                 if (queues[i].configured) {
 825                         if (ring_type == ENA_RING_TYPE_RX) {
 826                                 ena_assert_msg(
 827                                         dev->data->rx_queues[i] == &queues[i],
 828                                         "Inconsistent state of rx queues\n");
 829                         } else {
 830                                 ena_assert_msg(
 831                                         dev->data->tx_queues[i] == &queues[i],
 832                                         "Inconsistent state of tx queues\n");
 833                         }
 834
 835                         rc = ena_queue_restart(&queues[i]);
 836
 837                         if (rc) {
 838                                 PMD_INIT_LOG(ERR,
 839                                              "failed to restart queue %d type(%d)",
 840                                              i, ring_type);
 841                                 return -1;
 842                         }
 843                 }
 844         }
 845
 846         return 0;
 847 }
 848
 849 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 850 {
 851         uint32_t max_frame_len = adapter->max_mtu;
 852
 853         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 854             DEV_RX_OFFLOAD_JUMBO_FRAME)
 855                 max_frame_len =
 856                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 857
 858         return max_frame_len;
 859 }
 860
 861 static int ena_check_valid_conf(struct ena_adapter *adapter)
 862 {
 863         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 864
 865         if (max_frame_len > adapter->max_mtu) {
 866                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
 867                 return -1;
 868         }
 869
 870         return 0;
 871 }
 872
 873 static int
 874 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 875                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 876 {
 877         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 878
 879         queue_size = RTE_MIN(queue_size,
 880                              get_feat_ctx->max_queues.max_cq_depth);
 881         queue_size = RTE_MIN(queue_size,
 882                              get_feat_ctx->max_queues.max_sq_depth);
 883
 884         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 885                 queue_size = RTE_MIN(queue_size,
 886                                      get_feat_ctx->max_queues.max_llq_depth);
 887
 888         /* Round down to power of 2 */
 889         if (!rte_is_power_of_2(queue_size))
 890                 queue_size = rte_align32pow2(queue_size >> 1);
 891
 892         if (queue_size == 0) {
 893                 PMD_INIT_LOG(ERR, "Invalid queue size");
 894                 return -EFAULT;
 895         }
 896
 897         return queue_size;
 898 }
 899
 900 static void ena_stats_restart(struct rte_eth_dev *dev)
 901 {
 902         struct ena_adapter *adapter =
 903                 (struct ena_adapter *)(dev->data->dev_private);
 904
 905         rte_atomic64_init(&adapter->drv_stats->ierrors);
 906         rte_atomic64_init(&adapter->drv_stats->oerrors);
 907         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 908 }
 909
 910 static int ena_stats_get(struct rte_eth_dev *dev,
 911                           struct rte_eth_stats *stats)
 912 {
 913         struct ena_admin_basic_stats ena_stats;
 914         struct ena_adapter *adapter =
 915                 (struct ena_adapter *)(dev->data->dev_private);
 916         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 917         int rc;
 918
 919         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 920                 return -ENOTSUP;
 921
 922         memset(&ena_stats, 0, sizeof(ena_stats));
 923         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 924         if (unlikely(rc)) {
 925                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 926                 return rc;
 927         }
 928
 929         /* Set of basic statistics from ENA */
 930         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 931                                           ena_stats.rx_pkts_low);
 932         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 933                                           ena_stats.tx_pkts_low);
 934         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 935                                         ena_stats.rx_bytes_low);
 936         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 937                                         ena_stats.tx_bytes_low);
 938         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 939                                          ena_stats.rx_drops_low);
 940
 941         /* Driver related stats */
 942         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 943         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 944         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 945         return 0;
 946 }
 947
 948 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 949 {
 950         struct ena_adapter *adapter;
 951         struct ena_com_dev *ena_dev;
 952         int rc = 0;
 953
 954         ena_assert_msg(dev->data != NULL, "Uninitialized device");
 955         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
 956         adapter = (struct ena_adapter *)(dev->data->dev_private);
 957
 958         ena_dev = &adapter->ena_dev;
 959         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
 960
 961         if (mtu > ena_get_mtu_conf(adapter)) {
 962                 RTE_LOG(ERR, PMD,
 963                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
 964                         mtu, ena_get_mtu_conf(adapter));
 965                 rc = -EINVAL;
 966                 goto err;
 967         }
 968
 969         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 970         if (rc)
 971                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
 972         else
 973                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
 974
 975 err:
 976         return rc;
 977 }
 978
 979 static int ena_start(struct rte_eth_dev *dev)
 980 {
 981         struct ena_adapter *adapter =
 982                 (struct ena_adapter *)(dev->data->dev_private);
 983         uint64_t ticks;
 984         int rc = 0;
 985
 986         rc = ena_check_valid_conf(adapter);
 987         if (rc)
 988                 return rc;
 989
 990         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
 991         if (rc)
 992                 return rc;
 993
 994         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
 995         if (rc)
 996                 return rc;
 997
 998         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
 999             ETH_MQ_RX_RSS_FLAG) {
1000                 rc = ena_rss_init_default(adapter);
1001                 if (rc)
1002                         return rc;
1003         }
1004
1005         ena_stats_restart(dev);
1006
1007         adapter->timestamp_wd = rte_get_timer_cycles();
1008         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1009
1010         ticks = rte_get_timer_hz();
1011         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1012                         ena_timer_wd_callback, adapter);
1013
1014         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1015
1016         return 0;
1017 }
1018
1019 static void ena_stop(struct rte_eth_dev *dev)
1020 {
1021         struct ena_adapter *adapter =
1022                 (struct ena_adapter *)(dev->data->dev_private);
1023
1024         rte_timer_stop_sync(&adapter->timer_wd);
1025
1026         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1027 }
1028
1029 static int ena_queue_restart(struct ena_ring *ring)
1030 {
1031         int rc, bufs_num;
1032
1033         ena_assert_msg(ring->configured == 1,
1034                        "Trying to restart unconfigured queue\n");
1035
1036         ring->next_to_clean = 0;
1037         ring->next_to_use = 0;
1038
1039         if (ring->type == ENA_RING_TYPE_TX)
1040                 return 0;
1041
1042         bufs_num = ring->ring_size - 1;
1043         rc = ena_populate_rx_queue(ring, bufs_num);
1044         if (rc != bufs_num) {
1045                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1046                 return (-1);
1047         }
1048
1049         return 0;
1050 }
1051
1052 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1053                               uint16_t queue_idx,
1054                               uint16_t nb_desc,
1055                               __rte_unused unsigned int socket_id,
1056                               const struct rte_eth_txconf *tx_conf)
1057 {
1058         struct ena_com_create_io_ctx ctx =
1059                 /* policy set to _HOST just to satisfy icc compiler */
1060                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1061                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
1062         struct ena_ring *txq = NULL;
1063         struct ena_adapter *adapter =
1064                 (struct ena_adapter *)(dev->data->dev_private);
1065         unsigned int i;
1066         int ena_qid;
1067         int rc;
1068         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1069
1070         txq = &adapter->tx_ring[queue_idx];
1071
1072         if (txq->configured) {
1073                 RTE_LOG(CRIT, PMD,
1074                         "API violation. Queue %d is already configured\n",
1075                         queue_idx);
1076                 return -1;
1077         }
1078
1079         if (!rte_is_power_of_2(nb_desc)) {
1080                 RTE_LOG(ERR, PMD,
1081                         "Unsupported size of RX queue: %d is not a power of 2.",
1082                         nb_desc);
1083                 return -EINVAL;
1084         }
1085
1086         if (nb_desc > adapter->tx_ring_size) {
1087                 RTE_LOG(ERR, PMD,
1088                         "Unsupported size of TX queue (max size: %d)\n",
1089                         adapter->tx_ring_size);
1090                 return -EINVAL;
1091         }
1092
1093         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1094
1095         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1096         ctx.qid = ena_qid;
1097         ctx.msix_vector = -1; /* admin interrupts not used */
1098         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1099         ctx.queue_size = adapter->tx_ring_size;
1100         ctx.numa_node = ena_cpu_to_node(queue_idx);
1101
1102         rc = ena_com_create_io_queue(ena_dev, &ctx);
1103         if (rc) {
1104                 RTE_LOG(ERR, PMD,
1105                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1106                         queue_idx, ena_qid, rc);
1107         }
1108         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1109         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1110
1111         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1112                                      &txq->ena_com_io_sq,
1113                                      &txq->ena_com_io_cq);
1114         if (rc) {
1115                 RTE_LOG(ERR, PMD,
1116                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1117                         queue_idx, rc);
1118                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1119                 goto err;
1120         }
1121
1122         txq->port_id = dev->data->port_id;
1123         txq->next_to_clean = 0;
1124         txq->next_to_use = 0;
1125         txq->ring_size = nb_desc;
1126
1127         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1128                                           sizeof(struct ena_tx_buffer) *
1129                                           txq->ring_size,
1130                                           RTE_CACHE_LINE_SIZE);
1131         if (!txq->tx_buffer_info) {
1132                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1133                 return -ENOMEM;
1134         }
1135
1136         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1137                                          sizeof(u16) * txq->ring_size,
1138                                          RTE_CACHE_LINE_SIZE);
1139         if (!txq->empty_tx_reqs) {
1140                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1141                 rte_free(txq->tx_buffer_info);
1142                 return -ENOMEM;
1143         }
1144         for (i = 0; i < txq->ring_size; i++)
1145                 txq->empty_tx_reqs[i] = i;
1146
1147         if (tx_conf != NULL) {
1148                 txq->offloads =
1149                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1150         }
1151
1152         /* Store pointer to this queue in upper layer */
1153         txq->configured = 1;
1154         dev->data->tx_queues[queue_idx] = txq;
1155 err:
1156         return rc;
1157 }
1158
1159 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1160                               uint16_t queue_idx,
1161                               uint16_t nb_desc,
1162                               __rte_unused unsigned int socket_id,
1163                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1164                               struct rte_mempool *mp)
1165 {
1166         struct ena_com_create_io_ctx ctx =
1167                 /* policy set to _HOST just to satisfy icc compiler */
1168                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1169                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1170         struct ena_adapter *adapter =
1171                 (struct ena_adapter *)(dev->data->dev_private);
1172         struct ena_ring *rxq = NULL;
1173         uint16_t ena_qid = 0;
1174         int rc = 0;
1175         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1176
1177         rxq = &adapter->rx_ring[queue_idx];
1178         if (rxq->configured) {
1179                 RTE_LOG(CRIT, PMD,
1180                         "API violation. Queue %d is already configured\n",
1181                         queue_idx);
1182                 return -1;
1183         }
1184
1185         if (!rte_is_power_of_2(nb_desc)) {
1186                 RTE_LOG(ERR, PMD,
1187                         "Unsupported size of TX queue: %d is not a power of 2.",
1188                         nb_desc);
1189                 return -EINVAL;
1190         }
1191
1192         if (nb_desc > adapter->rx_ring_size) {
1193                 RTE_LOG(ERR, PMD,
1194                         "Unsupported size of RX queue (max size: %d)\n",
1195                         adapter->rx_ring_size);
1196                 return -EINVAL;
1197         }
1198
1199         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1200
1201         ctx.qid = ena_qid;
1202         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1203         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1204         ctx.msix_vector = -1; /* admin interrupts not used */
1205         ctx.queue_size = adapter->rx_ring_size;
1206         ctx.numa_node = ena_cpu_to_node(queue_idx);
1207
1208         rc = ena_com_create_io_queue(ena_dev, &ctx);
1209         if (rc)
1210                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1211                         queue_idx, rc);
1212
1213         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1214         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1215
1216         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1217                                      &rxq->ena_com_io_sq,
1218                                      &rxq->ena_com_io_cq);
1219         if (rc) {
1220                 RTE_LOG(ERR, PMD,
1221                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1222                         queue_idx, rc);
1223                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1224         }
1225
1226         rxq->port_id = dev->data->port_id;
1227         rxq->next_to_clean = 0;
1228         rxq->next_to_use = 0;
1229         rxq->ring_size = nb_desc;
1230         rxq->mb_pool = mp;
1231
1232         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1233                                           sizeof(struct rte_mbuf *) * nb_desc,
1234                                           RTE_CACHE_LINE_SIZE);
1235         if (!rxq->rx_buffer_info) {
1236                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1237                 return -ENOMEM;
1238         }
1239
1240         /* Store pointer to this queue in upper layer */
1241         rxq->configured = 1;
1242         dev->data->rx_queues[queue_idx] = rxq;
1243
1244         return rc;
1245 }
1246
1247 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1248 {
1249         unsigned int i;
1250         int rc;
1251         uint16_t ring_size = rxq->ring_size;
1252         uint16_t ring_mask = ring_size - 1;
1253         uint16_t next_to_use = rxq->next_to_use;
1254         uint16_t in_use;
1255         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1256
1257         if (unlikely(!count))
1258                 return 0;
1259
1260         in_use = rxq->next_to_use - rxq->next_to_clean;
1261         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1262
1263         count = RTE_MIN(count,
1264                         (uint16_t)(ring_size - (next_to_use & ring_mask)));
1265
1266         /* get resources for incoming packets */
1267         rc = rte_mempool_get_bulk(rxq->mb_pool,
1268                                   (void **)(&mbufs[next_to_use & ring_mask]),
1269                                   count);
1270         if (unlikely(rc < 0)) {
1271                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1272                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1273                 return 0;
1274         }
1275
1276         for (i = 0; i < count; i++) {
1277                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1278                 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1279                 struct ena_com_buf ebuf;
1280
1281                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1282                 /* prepare physical address for DMA transaction */
1283                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1284                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1285                 /* pass resource to device */
1286                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1287                                                 &ebuf, next_to_use_masked);
1288                 if (unlikely(rc)) {
1289                         rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1290                                              count - i);
1291                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1292                         break;
1293                 }
1294                 next_to_use++;
1295         }
1296
1297         /* When we submitted free recources to device... */
1298         if (i > 0) {
1299                 /* ...let HW know that it can fill buffers with data */
1300                 rte_wmb();
1301                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1302
1303                 rxq->next_to_use = next_to_use;
1304         }
1305
1306         return i;
1307 }
1308
1309 static int ena_device_init(struct ena_com_dev *ena_dev,
1310                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1311 {
1312         uint32_t aenq_groups;
1313         int rc;
1314         bool readless_supported;
1315
1316         /* Initialize mmio registers */
1317         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1318         if (rc) {
1319                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1320                 return rc;
1321         }
1322
1323         /* The PCIe configuration space revision id indicate if mmio reg
1324          * read is disabled.
1325          */
1326         readless_supported =
1327                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1328                                & ENA_MMIO_DISABLE_REG_READ);
1329         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1330
1331         /* reset device */
1332         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1333         if (rc) {
1334                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1335                 goto err_mmio_read_less;
1336         }
1337
1338         /* check FW version */
1339         rc = ena_com_validate_version(ena_dev);
1340         if (rc) {
1341                 RTE_LOG(ERR, PMD, "device version is too low\n");
1342                 goto err_mmio_read_less;
1343         }
1344
1345         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1346
1347         /* ENA device administration layer init */
1348         rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
1349         if (rc) {
1350                 RTE_LOG(ERR, PMD,
1351                         "cannot initialize ena admin queue with device\n");
1352                 goto err_mmio_read_less;
1353         }
1354
1355         /* To enable the msix interrupts the driver needs to know the number
1356          * of queues. So the driver uses polling mode to retrieve this
1357          * information.
1358          */
1359         ena_com_set_admin_polling_mode(ena_dev, true);
1360
1361         ena_config_host_info(ena_dev);
1362
1363         /* Get Device Attributes and features */
1364         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1365         if (rc) {
1366                 RTE_LOG(ERR, PMD,
1367                         "cannot get attribute for ena device rc= %d\n", rc);
1368                 goto err_admin_init;
1369         }
1370
1371         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1372                       BIT(ENA_ADMIN_NOTIFICATION) |
1373                       BIT(ENA_ADMIN_KEEP_ALIVE);
1374
1375         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1376         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1377         if (rc) {
1378                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1379                 goto err_admin_init;
1380         }
1381
1382         return 0;
1383
1384 err_admin_init:
1385         ena_com_admin_destroy(ena_dev);
1386
1387 err_mmio_read_less:
1388         ena_com_mmio_reg_read_request_destroy(ena_dev);
1389
1390         return rc;
1391 }
1392
1393 static void ena_interrupt_handler_rte(void *cb_arg)
1394 {
1395         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1396         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1397
1398         ena_com_admin_q_comp_intr_handler(ena_dev);
1399         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1400                 ena_com_aenq_intr_handler(ena_dev, adapter);
1401 }
1402
1403 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1404                                   void *arg)
1405 {
1406         struct ena_adapter *adapter = (struct ena_adapter *)arg;
1407         struct rte_eth_dev *dev = adapter->rte_dev;
1408
1409         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1410                 return;
1411
1412         /* Within reasonable timing range no memory barriers are needed */
1413         if ((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1414             adapter->keep_alive_timeout) {
1415                 RTE_LOG(ERR, PMD, "The ENA device is not responding - "
1416                         "performing device reset...");
1417                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1418                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1419                         NULL);
1420         }
1421 }
1422
1423 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1424 {
1425         struct rte_pci_device *pci_dev;
1426         struct rte_intr_handle *intr_handle;
1427         struct ena_adapter *adapter =
1428                 (struct ena_adapter *)(eth_dev->data->dev_private);
1429         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1430         struct ena_com_dev_get_features_ctx get_feat_ctx;
1431         int queue_size, rc;
1432
1433         static int adapters_found;
1434
1435         memset(adapter, 0, sizeof(struct ena_adapter));
1436         ena_dev = &adapter->ena_dev;
1437
1438         eth_dev->dev_ops = &ena_dev_ops;
1439         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1440         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1441         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1442         adapter->rte_eth_dev_data = eth_dev->data;
1443         adapter->rte_dev = eth_dev;
1444
1445         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1446                 return 0;
1447
1448         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1449         adapter->pdev = pci_dev;
1450
1451         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1452                      pci_dev->addr.domain,
1453                      pci_dev->addr.bus,
1454                      pci_dev->addr.devid,
1455                      pci_dev->addr.function);
1456
1457         intr_handle = &pci_dev->intr_handle;
1458
1459         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1460         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1461
1462         if (!adapter->regs) {
1463                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1464                              ENA_REGS_BAR);
1465                 return -ENXIO;
1466         }
1467
1468         ena_dev->reg_bar = adapter->regs;
1469         ena_dev->dmadev = adapter->pdev;
1470
1471         adapter->id_number = adapters_found;
1472
1473         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1474                  adapter->id_number);
1475
1476         /* device specific initialization routine */
1477         rc = ena_device_init(ena_dev, &get_feat_ctx);
1478         if (rc) {
1479                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1480                 return -1;
1481         }
1482
1483         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1484         adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1485
1486         queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1487         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1488                 return -EFAULT;
1489
1490         adapter->tx_ring_size = queue_size;
1491         adapter->rx_ring_size = queue_size;
1492
1493         /* prepare ring structures */
1494         ena_init_rings(adapter);
1495
1496         ena_config_debug_area(adapter);
1497
1498         /* Set max MTU for this device */
1499         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1500
1501         /* set device support for TSO */
1502         adapter->tso4_supported = get_feat_ctx.offload.tx &
1503                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1504
1505         /* Copy MAC address and point DPDK to it */
1506         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1507         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1508                         (struct ether_addr *)adapter->mac_addr);
1509
1510         adapter->drv_stats = rte_zmalloc("adapter stats",
1511                                          sizeof(*adapter->drv_stats),
1512                                          RTE_CACHE_LINE_SIZE);
1513         if (!adapter->drv_stats) {
1514                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1515                 return -ENOMEM;
1516         }
1517
1518         rte_intr_callback_register(intr_handle,
1519                                    ena_interrupt_handler_rte,
1520                                    adapter);
1521         rte_intr_enable(intr_handle);
1522         ena_com_set_admin_polling_mode(ena_dev, false);
1523         ena_com_admin_aenq_enable(ena_dev);
1524
1525         if (adapters_found == 0)
1526                 rte_timer_subsystem_init();
1527         rte_timer_init(&adapter->timer_wd);
1528
1529         adapters_found++;
1530         adapter->state = ENA_ADAPTER_STATE_INIT;
1531
1532         return 0;
1533 }
1534
1535 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1536 {
1537         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1538         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1539         struct ena_adapter *adapter =
1540                 (struct ena_adapter *)(eth_dev->data->dev_private);
1541
1542         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1543                 return -EPERM;
1544
1545         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1546                 ena_close(eth_dev);
1547
1548         eth_dev->dev_ops = NULL;
1549         eth_dev->rx_pkt_burst = NULL;
1550         eth_dev->tx_pkt_burst = NULL;
1551         eth_dev->tx_pkt_prepare = NULL;
1552
1553         rte_free(adapter->drv_stats);
1554         adapter->drv_stats = NULL;
1555
1556         rte_intr_disable(intr_handle);
1557         rte_intr_callback_unregister(intr_handle,
1558                                      ena_interrupt_handler_rte,
1559                                      adapter);
1560
1561         adapter->state = ENA_ADAPTER_STATE_FREE;
1562
1563         return 0;
1564 }
1565
1566 static int ena_dev_configure(struct rte_eth_dev *dev)
1567 {
1568         struct ena_adapter *adapter =
1569                 (struct ena_adapter *)(dev->data->dev_private);
1570
1571         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1572
1573         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1574         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1575         return 0;
1576 }
1577
1578 static void ena_init_rings(struct ena_adapter *adapter)
1579 {
1580         int i;
1581
1582         for (i = 0; i < adapter->num_queues; i++) {
1583                 struct ena_ring *ring = &adapter->tx_ring[i];
1584
1585                 ring->configured = 0;
1586                 ring->type = ENA_RING_TYPE_TX;
1587                 ring->adapter = adapter;
1588                 ring->id = i;
1589                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1590                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1591         }
1592
1593         for (i = 0; i < adapter->num_queues; i++) {
1594                 struct ena_ring *ring = &adapter->rx_ring[i];
1595
1596                 ring->configured = 0;
1597                 ring->type = ENA_RING_TYPE_RX;
1598                 ring->adapter = adapter;
1599                 ring->id = i;
1600         }
1601 }
1602
1603 static void ena_infos_get(struct rte_eth_dev *dev,
1604                           struct rte_eth_dev_info *dev_info)
1605 {
1606         struct ena_adapter *adapter;
1607         struct ena_com_dev *ena_dev;
1608         struct ena_com_dev_get_features_ctx feat;
1609         uint64_t rx_feat = 0, tx_feat = 0;
1610         int rc = 0;
1611
1612         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1613         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1614         adapter = (struct ena_adapter *)(dev->data->dev_private);
1615
1616         ena_dev = &adapter->ena_dev;
1617         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1618
1619         dev_info->speed_capa =
1620                         ETH_LINK_SPEED_1G   |
1621                         ETH_LINK_SPEED_2_5G |
1622                         ETH_LINK_SPEED_5G   |
1623                         ETH_LINK_SPEED_10G  |
1624                         ETH_LINK_SPEED_25G  |
1625                         ETH_LINK_SPEED_40G  |
1626                         ETH_LINK_SPEED_50G  |
1627                         ETH_LINK_SPEED_100G;
1628
1629         /* Get supported features from HW */
1630         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1631         if (unlikely(rc)) {
1632                 RTE_LOG(ERR, PMD,
1633                         "Cannot get attribute for ena device rc= %d\n", rc);
1634                 return;
1635         }
1636
1637         /* Set Tx & Rx features available for device */
1638         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1639                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1640
1641         if (feat.offload.tx &
1642             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1643                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1644                         DEV_TX_OFFLOAD_UDP_CKSUM |
1645                         DEV_TX_OFFLOAD_TCP_CKSUM;
1646
1647         if (feat.offload.rx_supported &
1648             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1649                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1650                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1651                         DEV_RX_OFFLOAD_TCP_CKSUM;
1652
1653         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1654
1655         /* Inform framework about available features */
1656         dev_info->rx_offload_capa = rx_feat;
1657         dev_info->rx_queue_offload_capa = rx_feat;
1658         dev_info->tx_offload_capa = tx_feat;
1659         dev_info->tx_queue_offload_capa = tx_feat;
1660
1661         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1662         dev_info->max_rx_pktlen  = adapter->max_mtu;
1663         dev_info->max_mac_addrs = 1;
1664
1665         dev_info->max_rx_queues = adapter->num_queues;
1666         dev_info->max_tx_queues = adapter->num_queues;
1667         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1668
1669         adapter->tx_supported_offloads = tx_feat;
1670         adapter->rx_supported_offloads = rx_feat;
1671 }
1672
1673 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1674                                   uint16_t nb_pkts)
1675 {
1676         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1677         unsigned int ring_size = rx_ring->ring_size;
1678         unsigned int ring_mask = ring_size - 1;
1679         uint16_t next_to_clean = rx_ring->next_to_clean;
1680         uint16_t desc_in_use = 0;
1681         unsigned int recv_idx = 0;
1682         struct rte_mbuf *mbuf = NULL;
1683         struct rte_mbuf *mbuf_head = NULL;
1684         struct rte_mbuf *mbuf_prev = NULL;
1685         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1686         unsigned int completed;
1687
1688         struct ena_com_rx_ctx ena_rx_ctx;
1689         int rc = 0;
1690
1691         /* Check adapter state */
1692         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1693                 RTE_LOG(ALERT, PMD,
1694                         "Trying to receive pkts while device is NOT running\n");
1695                 return 0;
1696         }
1697
1698         desc_in_use = rx_ring->next_to_use - next_to_clean;
1699         if (unlikely(nb_pkts > desc_in_use))
1700                 nb_pkts = desc_in_use;
1701
1702         for (completed = 0; completed < nb_pkts; completed++) {
1703                 int segments = 0;
1704
1705                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1706                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1707                 ena_rx_ctx.descs = 0;
1708                 /* receive packet context */
1709                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1710                                     rx_ring->ena_com_io_sq,
1711                                     &ena_rx_ctx);
1712                 if (unlikely(rc)) {
1713                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1714                         return 0;
1715                 }
1716
1717                 if (unlikely(ena_rx_ctx.descs == 0))
1718                         break;
1719
1720                 while (segments < ena_rx_ctx.descs) {
1721                         mbuf = rx_buff_info[next_to_clean & ring_mask];
1722                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1723                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1724                         mbuf->refcnt = 1;
1725                         mbuf->next = NULL;
1726                         if (segments == 0) {
1727                                 mbuf->nb_segs = ena_rx_ctx.descs;
1728                                 mbuf->port = rx_ring->port_id;
1729                                 mbuf->pkt_len = 0;
1730                                 mbuf_head = mbuf;
1731                         } else {
1732                                 /* for multi-segment pkts create mbuf chain */
1733                                 mbuf_prev->next = mbuf;
1734                         }
1735                         mbuf_head->pkt_len += mbuf->data_len;
1736
1737                         mbuf_prev = mbuf;
1738                         segments++;
1739                         next_to_clean++;
1740                 }
1741
1742                 /* fill mbuf attributes if any */
1743                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1744                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1745
1746                 /* pass to DPDK application head mbuf */
1747                 rx_pkts[recv_idx] = mbuf_head;
1748                 recv_idx++;
1749         }
1750
1751         rx_ring->next_to_clean = next_to_clean;
1752
1753         desc_in_use = desc_in_use - completed + 1;
1754         /* Burst refill to save doorbells, memory barriers, const interval */
1755         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1756                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1757
1758         return recv_idx;
1759 }
1760
1761 static uint16_t
1762 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1763                 uint16_t nb_pkts)
1764 {
1765         int32_t ret;
1766         uint32_t i;
1767         struct rte_mbuf *m;
1768         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1769         struct ipv4_hdr *ip_hdr;
1770         uint64_t ol_flags;
1771         uint16_t frag_field;
1772
1773         for (i = 0; i != nb_pkts; i++) {
1774                 m = tx_pkts[i];
1775                 ol_flags = m->ol_flags;
1776
1777                 if (!(ol_flags & PKT_TX_IPV4))
1778                         continue;
1779
1780                 /* If there was not L2 header length specified, assume it is
1781                  * length of the ethernet header.
1782                  */
1783                 if (unlikely(m->l2_len == 0))
1784                         m->l2_len = sizeof(struct ether_hdr);
1785
1786                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1787                                                  m->l2_len);
1788                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1789
1790                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1791                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1792
1793                         /* If IPv4 header has DF flag enabled and TSO support is
1794                          * disabled, partial chcecksum should not be calculated.
1795                          */
1796                         if (!tx_ring->adapter->tso4_supported)
1797                                 continue;
1798                 }
1799
1800                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1801                                 (ol_flags & PKT_TX_L4_MASK) ==
1802                                 PKT_TX_SCTP_CKSUM) {
1803                         rte_errno = -ENOTSUP;
1804                         return i;
1805                 }
1806
1807 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1808                 ret = rte_validate_tx_offload(m);
1809                 if (ret != 0) {
1810                         rte_errno = ret;
1811                         return i;
1812                 }
1813 #endif
1814
1815                 /* In case we are supposed to TSO and have DF not set (DF=0)
1816                  * hardware must be provided with partial checksum, otherwise
1817                  * it will take care of necessary calculations.
1818                  */
1819
1820                 ret = rte_net_intel_cksum_flags_prepare(m,
1821                         ol_flags & ~PKT_TX_TCP_SEG);
1822                 if (ret != 0) {
1823                         rte_errno = ret;
1824                         return i;
1825                 }
1826         }
1827
1828         return i;
1829 }
1830
1831 static void ena_update_hints(struct ena_adapter *adapter,
1832                              struct ena_admin_ena_hw_hints *hints)
1833 {
1834         if (hints->admin_completion_tx_timeout)
1835                 adapter->ena_dev.admin_queue.completion_timeout =
1836                         hints->admin_completion_tx_timeout * 1000;
1837
1838         if (hints->mmio_read_timeout)
1839                 /* convert to usec */
1840                 adapter->ena_dev.mmio_read.reg_read_to =
1841                         hints->mmio_read_timeout * 1000;
1842
1843         if (hints->driver_watchdog_timeout) {
1844                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1845                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
1846                 else
1847                         // Convert msecs to ticks
1848                         adapter->keep_alive_timeout =
1849                                 (hints->driver_watchdog_timeout *
1850                                 rte_get_timer_hz()) / 1000;
1851         }
1852 }
1853
1854 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1855                                   uint16_t nb_pkts)
1856 {
1857         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1858         uint16_t next_to_use = tx_ring->next_to_use;
1859         uint16_t next_to_clean = tx_ring->next_to_clean;
1860         struct rte_mbuf *mbuf;
1861         unsigned int ring_size = tx_ring->ring_size;
1862         unsigned int ring_mask = ring_size - 1;
1863         struct ena_com_tx_ctx ena_tx_ctx;
1864         struct ena_tx_buffer *tx_info;
1865         struct ena_com_buf *ebuf;
1866         uint16_t rc, req_id, total_tx_descs = 0;
1867         uint16_t sent_idx = 0, empty_tx_reqs;
1868         int nb_hw_desc;
1869
1870         /* Check adapter state */
1871         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1872                 RTE_LOG(ALERT, PMD,
1873                         "Trying to xmit pkts while device is NOT running\n");
1874                 return 0;
1875         }
1876
1877         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1878         if (nb_pkts > empty_tx_reqs)
1879                 nb_pkts = empty_tx_reqs;
1880
1881         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1882                 mbuf = tx_pkts[sent_idx];
1883
1884                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1885                 tx_info = &tx_ring->tx_buffer_info[req_id];
1886                 tx_info->mbuf = mbuf;
1887                 tx_info->num_of_bufs = 0;
1888                 ebuf = tx_info->bufs;
1889
1890                 /* Prepare TX context */
1891                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1892                 memset(&ena_tx_ctx.ena_meta, 0x0,
1893                        sizeof(struct ena_com_tx_meta));
1894                 ena_tx_ctx.ena_bufs = ebuf;
1895                 ena_tx_ctx.req_id = req_id;
1896                 if (tx_ring->tx_mem_queue_type ==
1897                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1898                         /* prepare the push buffer with
1899                          * virtual address of the data
1900                          */
1901                         ena_tx_ctx.header_len =
1902                                 RTE_MIN(mbuf->data_len,
1903                                         tx_ring->tx_max_header_size);
1904                         ena_tx_ctx.push_header =
1905                                 (void *)((char *)mbuf->buf_addr +
1906                                          mbuf->data_off);
1907                 } /* there's no else as we take advantage of memset zeroing */
1908
1909                 /* Set TX offloads flags, if applicable */
1910                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
1911
1912                 if (unlikely(mbuf->ol_flags &
1913                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1914                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1915
1916                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1917
1918                 /* Process first segment taking into
1919                  * consideration pushed header
1920                  */
1921                 if (mbuf->data_len > ena_tx_ctx.header_len) {
1922                         ebuf->paddr = mbuf->buf_iova +
1923                                       mbuf->data_off +
1924                                       ena_tx_ctx.header_len;
1925                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1926                         ebuf++;
1927                         tx_info->num_of_bufs++;
1928                 }
1929
1930                 while ((mbuf = mbuf->next) != NULL) {
1931                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
1932                         ebuf->len = mbuf->data_len;
1933                         ebuf++;
1934                         tx_info->num_of_bufs++;
1935                 }
1936
1937                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1938
1939                 /* Write data to device */
1940                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1941                                         &ena_tx_ctx, &nb_hw_desc);
1942                 if (unlikely(rc))
1943                         break;
1944
1945                 tx_info->tx_descs = nb_hw_desc;
1946
1947                 next_to_use++;
1948         }
1949
1950         /* If there are ready packets to be xmitted... */
1951         if (sent_idx > 0) {
1952                 /* ...let HW do its best :-) */
1953                 rte_wmb();
1954                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1955
1956                 tx_ring->next_to_use = next_to_use;
1957         }
1958
1959         /* Clear complete packets  */
1960         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1961                 /* Get Tx info & store how many descs were processed  */
1962                 tx_info = &tx_ring->tx_buffer_info[req_id];
1963                 total_tx_descs += tx_info->tx_descs;
1964
1965                 /* Free whole mbuf chain  */
1966                 mbuf = tx_info->mbuf;
1967                 rte_pktmbuf_free(mbuf);
1968                 tx_info->mbuf = NULL;
1969
1970                 /* Put back descriptor to the ring for reuse */
1971                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
1972                 next_to_clean++;
1973
1974                 /* If too many descs to clean, leave it for another run */
1975                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1976                         break;
1977         }
1978
1979         if (total_tx_descs > 0) {
1980                 /* acknowledge completion of sent packets */
1981                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1982                 tx_ring->next_to_clean = next_to_clean;
1983         }
1984
1985         return sent_idx;
1986 }
1987
1988 /*********************************************************************
1989  *  PMD configuration
1990  *********************************************************************/
1991 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1992         struct rte_pci_device *pci_dev)
1993 {
1994         return rte_eth_dev_pci_generic_probe(pci_dev,
1995                 sizeof(struct ena_adapter), eth_ena_dev_init);
1996 }
1997
1998 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
1999 {
2000         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2001 }
2002
2003 static struct rte_pci_driver rte_ena_pmd = {
2004         .id_table = pci_id_ena_map,
2005         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2006         .probe = eth_ena_pci_probe,
2007         .remove = eth_ena_pci_remove,
2008 };
2009
2010 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2011 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2012 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2013
2014 RTE_INIT(ena_init_log);
2015 static void
2016 ena_init_log(void)
2017 {
2018         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2019         if (ena_logtype_init >= 0)
2020                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2021         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2022         if (ena_logtype_driver >= 0)
2023                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2024 }
2025
2026 /******************************************************************************
2027  ******************************** AENQ Handlers *******************************
2028  *****************************************************************************/
2029 static void ena_update_on_link_change(void *adapter_data,
2030                                       struct ena_admin_aenq_entry *aenq_e)
2031 {
2032         struct rte_eth_dev *eth_dev;
2033         struct ena_adapter *adapter;
2034         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2035         uint32_t status;
2036
2037         adapter = (struct ena_adapter *)adapter_data;
2038         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2039         eth_dev = adapter->rte_dev;
2040
2041         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2042         adapter->link_status = status;
2043
2044         ena_link_update(eth_dev, 0);
2045         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2046 }
2047
2048 static void ena_notification(void *data,
2049                              struct ena_admin_aenq_entry *aenq_e)
2050 {
2051         struct ena_adapter *adapter = (struct ena_adapter *)data;
2052         struct ena_admin_ena_hw_hints *hints;
2053
2054         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2055                 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2056                         aenq_e->aenq_common_desc.group,
2057                         ENA_ADMIN_NOTIFICATION);
2058
2059         switch (aenq_e->aenq_common_desc.syndrom) {
2060         case ENA_ADMIN_UPDATE_HINTS:
2061                 hints = (struct ena_admin_ena_hw_hints *)
2062                         (&aenq_e->inline_data_w4);
2063                 ena_update_hints(adapter, hints);
2064                 break;
2065         default:
2066                 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2067                         aenq_e->aenq_common_desc.syndrom);
2068         }
2069 }
2070
2071 static void ena_keep_alive(void *adapter_data,
2072                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2073 {
2074         struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2075
2076         adapter->timestamp_wd = rte_get_timer_cycles();
2077 }
2078
2079 /**
2080  * This handler will called for unknown event group or unimplemented handlers
2081  **/
2082 static void unimplemented_aenq_handler(__rte_unused void *data,
2083                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2084 {
2085         // Unimplemented handler
2086 }
2087
2088 static struct ena_aenq_handlers aenq_handlers = {
2089         .handlers = {
2090                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2091                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2092                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2093         },
2094         .unimplemented_handler = unimplemented_aenq_handler
2095 };