drivers/net/enetc/enetc_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018-2020 NXP
   3  */
   4
   5 #include <stdbool.h>
   6 #include <ethdev_pci.h>
   7 #include <rte_random.h>
   8 #include <dpaax_iova_table.h>
   9
  10 #include "enetc_logs.h"
  11 #include "enetc.h"
  12
  13 static int
  14 enetc_dev_start(struct rte_eth_dev *dev)
  15 {
  16         struct enetc_eth_hw *hw =
  17                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
  18         struct enetc_hw *enetc_hw = &hw->hw;
  19         uint32_t val;
  20
  21         PMD_INIT_FUNC_TRACE();
  22         val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG);
  23         enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG,
  24                       val | ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
  25
  26         /* Enable port */
  27         val = enetc_port_rd(enetc_hw, ENETC_PMR);
  28         enetc_port_wr(enetc_hw, ENETC_PMR, val | ENETC_PMR_EN);
  29
  30         /* set auto-speed for RGMII */
  31         if (enetc_port_rd(enetc_hw, ENETC_PM0_IF_MODE) & ENETC_PMO_IFM_RG) {
  32                 enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE,
  33                               ENETC_PM0_IFM_RGAUTO);
  34                 enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE,
  35                               ENETC_PM0_IFM_RGAUTO);
  36         }
  37         if (enetc_global_rd(enetc_hw,
  38                             ENETC_G_EPFBLPR(1)) == ENETC_G_EPFBLPR1_XGMII) {
  39                 enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE,
  40                               ENETC_PM0_IFM_XGMII);
  41                 enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE,
  42                               ENETC_PM0_IFM_XGMII);
  43         }
  44
  45         return 0;
  46 }
  47
  48 static int
  49 enetc_dev_stop(struct rte_eth_dev *dev)
  50 {
  51         struct enetc_eth_hw *hw =
  52                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
  53         struct enetc_hw *enetc_hw = &hw->hw;
  54         uint32_t val;
  55
  56         PMD_INIT_FUNC_TRACE();
  57         dev->data->dev_started = 0;
  58         /* Disable port */
  59         val = enetc_port_rd(enetc_hw, ENETC_PMR);
  60         enetc_port_wr(enetc_hw, ENETC_PMR, val & (~ENETC_PMR_EN));
  61
  62         val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG);
  63         enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG,
  64                       val & (~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN)));
  65
  66         return 0;
  67 }
  68
  69 static const uint32_t *
  70 enetc_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
  71 {
  72         static const uint32_t ptypes[] = {
  73                 RTE_PTYPE_L2_ETHER,
  74                 RTE_PTYPE_L3_IPV4,
  75                 RTE_PTYPE_L3_IPV6,
  76                 RTE_PTYPE_L4_TCP,
  77                 RTE_PTYPE_L4_UDP,
  78                 RTE_PTYPE_L4_SCTP,
  79                 RTE_PTYPE_L4_ICMP,
  80                 RTE_PTYPE_UNKNOWN
  81         };
  82
  83         return ptypes;
  84 }
  85
  86 /* return 0 means link status changed, -1 means not changed */
  87 static int
  88 enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
  89 {
  90         struct enetc_eth_hw *hw =
  91                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
  92         struct enetc_hw *enetc_hw = &hw->hw;
  93         struct rte_eth_link link;
  94         uint32_t status;
  95
  96         PMD_INIT_FUNC_TRACE();
  97
  98         memset(&link, 0, sizeof(link));
  99
 100         status = enetc_port_rd(enetc_hw, ENETC_PM0_STATUS);
 101
 102         if (status & ENETC_LINK_MODE)
 103                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
 104         else
 105                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
 106
 107         if (status & ENETC_LINK_STATUS)
 108                 link.link_status = ETH_LINK_UP;
 109         else
 110                 link.link_status = ETH_LINK_DOWN;
 111
 112         switch (status & ENETC_LINK_SPEED_MASK) {
 113         case ENETC_LINK_SPEED_1G:
 114                 link.link_speed = ETH_SPEED_NUM_1G;
 115                 break;
 116
 117         case ENETC_LINK_SPEED_100M:
 118                 link.link_speed = ETH_SPEED_NUM_100M;
 119                 break;
 120
 121         default:
 122         case ENETC_LINK_SPEED_10M:
 123                 link.link_speed = ETH_SPEED_NUM_10M;
 124         }
 125
 126         return rte_eth_linkstatus_set(dev, &link);
 127 }
 128
 129 static void
 130 print_ethaddr(const char *name, const struct rte_ether_addr *eth_addr)
 131 {
 132         char buf[RTE_ETHER_ADDR_FMT_SIZE];
 133
 134         rte_ether_format_addr(buf, RTE_ETHER_ADDR_FMT_SIZE, eth_addr);
 135         ENETC_PMD_NOTICE("%s%s\n", name, buf);
 136 }
 137
 138 static int
 139 enetc_hardware_init(struct enetc_eth_hw *hw)
 140 {
 141         struct enetc_hw *enetc_hw = &hw->hw;
 142         uint32_t *mac = (uint32_t *)hw->mac.addr;
 143         uint32_t high_mac = 0;
 144         uint16_t low_mac = 0;
 145
 146         PMD_INIT_FUNC_TRACE();
 147         /* Calculating and storing the base HW addresses */
 148         hw->hw.port = (void *)((size_t)hw->hw.reg + ENETC_PORT_BASE);
 149         hw->hw.global = (void *)((size_t)hw->hw.reg + ENETC_GLOBAL_BASE);
 150
 151         /* WA for Rx lock-up HW erratum */
 152         enetc_port_wr(enetc_hw, ENETC_PM0_RX_FIFO, 1);
 153
 154         /* set ENETC transaction flags to coherent, don't allocate.
 155          * BD writes merge with surrounding cache line data, frame data writes
 156          * overwrite cache line.
 157          */
 158         enetc_wr(enetc_hw, ENETC_SICAR0, ENETC_SICAR0_COHERENT);
 159
 160         /* Enabling Station Interface */
 161         enetc_wr(enetc_hw, ENETC_SIMR, ENETC_SIMR_EN);
 162
 163         *mac = (uint32_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR0(0));
 164         high_mac = (uint32_t)*mac;
 165         mac++;
 166         *mac = (uint16_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR1(0));
 167         low_mac = (uint16_t)*mac;
 168
 169         if ((high_mac | low_mac) == 0) {
 170                 char *first_byte;
 171
 172                 ENETC_PMD_NOTICE("MAC is not available for this SI, "
 173                                 "set random MAC\n");
 174                 mac = (uint32_t *)hw->mac.addr;
 175                 *mac = (uint32_t)rte_rand();
 176                 first_byte = (char *)mac;
 177                 *first_byte &= 0xfe;    /* clear multicast bit */
 178                 *first_byte |= 0x02;    /* set local assignment bit (IEEE802) */
 179
 180                 enetc_port_wr(enetc_hw, ENETC_PSIPMAR0(0), *mac);
 181                 mac++;
 182                 *mac = (uint16_t)rte_rand();
 183                 enetc_port_wr(enetc_hw, ENETC_PSIPMAR1(0), *mac);
 184                 print_ethaddr("New address: ",
 185                               (const struct rte_ether_addr *)hw->mac.addr);
 186         }
 187
 188         return 0;
 189 }
 190
 191 static int
 192 enetc_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
 193                     struct rte_eth_dev_info *dev_info)
 194 {
 195         PMD_INIT_FUNC_TRACE();
 196         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
 197                 .nb_max = MAX_BD_COUNT,
 198                 .nb_min = MIN_BD_COUNT,
 199                 .nb_align = BD_ALIGN,
 200         };
 201         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
 202                 .nb_max = MAX_BD_COUNT,
 203                 .nb_min = MIN_BD_COUNT,
 204                 .nb_align = BD_ALIGN,
 205         };
 206         dev_info->max_rx_queues = MAX_RX_RINGS;
 207         dev_info->max_tx_queues = MAX_TX_RINGS;
 208         dev_info->max_rx_pktlen = ENETC_MAC_MAXFRM_SIZE;
 209         dev_info->rx_offload_capa =
 210                 (DEV_RX_OFFLOAD_IPV4_CKSUM |
 211                  DEV_RX_OFFLOAD_UDP_CKSUM |
 212                  DEV_RX_OFFLOAD_TCP_CKSUM |
 213                  DEV_RX_OFFLOAD_KEEP_CRC |
 214                  DEV_RX_OFFLOAD_JUMBO_FRAME);
 215
 216         return 0;
 217 }
 218
 219 static int
 220 enetc_alloc_txbdr(struct enetc_bdr *txr, uint16_t nb_desc)
 221 {
 222         int size;
 223
 224         size = nb_desc * sizeof(struct enetc_swbd);
 225         txr->q_swbd = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN);
 226         if (txr->q_swbd == NULL)
 227                 return -ENOMEM;
 228
 229         size = nb_desc * sizeof(struct enetc_tx_bd);
 230         txr->bd_base = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN);
 231         if (txr->bd_base == NULL) {
 232                 rte_free(txr->q_swbd);
 233                 txr->q_swbd = NULL;
 234                 return -ENOMEM;
 235         }
 236
 237         txr->bd_count = nb_desc;
 238         txr->next_to_clean = 0;
 239         txr->next_to_use = 0;
 240
 241         return 0;
 242 }
 243
 244 static void
 245 enetc_free_bdr(struct enetc_bdr *rxr)
 246 {
 247         rte_free(rxr->q_swbd);
 248         rte_free(rxr->bd_base);
 249         rxr->q_swbd = NULL;
 250         rxr->bd_base = NULL;
 251 }
 252
 253 static void
 254 enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
 255 {
 256         int idx = tx_ring->index;
 257         phys_addr_t bd_address;
 258
 259         bd_address = (phys_addr_t)
 260                      rte_mem_virt2iova((const void *)tx_ring->bd_base);
 261         enetc_txbdr_wr(hw, idx, ENETC_TBBAR0,
 262                        lower_32_bits((uint64_t)bd_address));
 263         enetc_txbdr_wr(hw, idx, ENETC_TBBAR1,
 264                        upper_32_bits((uint64_t)bd_address));
 265         enetc_txbdr_wr(hw, idx, ENETC_TBLENR,
 266                        ENETC_RTBLENR_LEN(tx_ring->bd_count));
 267
 268         enetc_txbdr_wr(hw, idx, ENETC_TBCIR, 0);
 269         enetc_txbdr_wr(hw, idx, ENETC_TBCISR, 0);
 270         tx_ring->tcir = (void *)((size_t)hw->reg +
 271                         ENETC_BDR(TX, idx, ENETC_TBCIR));
 272         tx_ring->tcisr = (void *)((size_t)hw->reg +
 273                          ENETC_BDR(TX, idx, ENETC_TBCISR));
 274 }
 275
 276 static int
 277 enetc_tx_queue_setup(struct rte_eth_dev *dev,
 278                      uint16_t queue_idx,
 279                      uint16_t nb_desc,
 280                      unsigned int socket_id __rte_unused,
 281                      const struct rte_eth_txconf *tx_conf)
 282 {
 283         int err = 0;
 284         struct enetc_bdr *tx_ring;
 285         struct rte_eth_dev_data *data = dev->data;
 286         struct enetc_eth_adapter *priv =
 287                         ENETC_DEV_PRIVATE(data->dev_private);
 288
 289         PMD_INIT_FUNC_TRACE();
 290         if (nb_desc > MAX_BD_COUNT)
 291                 return -1;
 292
 293         tx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0);
 294         if (tx_ring == NULL) {
 295                 ENETC_PMD_ERR("Failed to allocate TX ring memory");
 296                 err = -ENOMEM;
 297                 return -1;
 298         }
 299
 300         err = enetc_alloc_txbdr(tx_ring, nb_desc);
 301         if (err)
 302                 goto fail;
 303
 304         tx_ring->index = queue_idx;
 305         tx_ring->ndev = dev;
 306         enetc_setup_txbdr(&priv->hw.hw, tx_ring);
 307         data->tx_queues[queue_idx] = tx_ring;
 308
 309         if (!tx_conf->tx_deferred_start) {
 310                 /* enable ring */
 311                 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index,
 312                                ENETC_TBMR, ENETC_TBMR_EN);
 313                 dev->data->tx_queue_state[tx_ring->index] =
 314                                RTE_ETH_QUEUE_STATE_STARTED;
 315         } else {
 316                 dev->data->tx_queue_state[tx_ring->index] =
 317                                RTE_ETH_QUEUE_STATE_STOPPED;
 318         }
 319
 320         return 0;
 321 fail:
 322         rte_free(tx_ring);
 323
 324         return err;
 325 }
 326
 327 static void
 328 enetc_tx_queue_release(void *txq)
 329 {
 330         if (txq == NULL)
 331                 return;
 332
 333         struct enetc_bdr *tx_ring = (struct enetc_bdr *)txq;
 334         struct enetc_eth_hw *eth_hw =
 335                 ENETC_DEV_PRIVATE_TO_HW(tx_ring->ndev->data->dev_private);
 336         struct enetc_hw *hw;
 337         struct enetc_swbd *tx_swbd;
 338         int i;
 339         uint32_t val;
 340
 341         /* Disable the ring */
 342         hw = &eth_hw->hw;
 343         val = enetc_txbdr_rd(hw, tx_ring->index, ENETC_TBMR);
 344         val &= (~ENETC_TBMR_EN);
 345         enetc_txbdr_wr(hw, tx_ring->index, ENETC_TBMR, val);
 346
 347         /* clean the ring*/
 348         i = tx_ring->next_to_clean;
 349         tx_swbd = &tx_ring->q_swbd[i];
 350         while (tx_swbd->buffer_addr != NULL) {
 351                 rte_pktmbuf_free(tx_swbd->buffer_addr);
 352                 tx_swbd->buffer_addr = NULL;
 353                 tx_swbd++;
 354                 i++;
 355                 if (unlikely(i == tx_ring->bd_count)) {
 356                         i = 0;
 357                         tx_swbd = &tx_ring->q_swbd[i];
 358                 }
 359         }
 360
 361         enetc_free_bdr(tx_ring);
 362         rte_free(tx_ring);
 363 }
 364
 365 static int
 366 enetc_alloc_rxbdr(struct enetc_bdr *rxr,
 367                   uint16_t nb_rx_desc)
 368 {
 369         int size;
 370
 371         size = nb_rx_desc * sizeof(struct enetc_swbd);
 372         rxr->q_swbd = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN);
 373         if (rxr->q_swbd == NULL)
 374                 return -ENOMEM;
 375
 376         size = nb_rx_desc * sizeof(union enetc_rx_bd);
 377         rxr->bd_base = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN);
 378         if (rxr->bd_base == NULL) {
 379                 rte_free(rxr->q_swbd);
 380                 rxr->q_swbd = NULL;
 381                 return -ENOMEM;
 382         }
 383
 384         rxr->bd_count = nb_rx_desc;
 385         rxr->next_to_clean = 0;
 386         rxr->next_to_use = 0;
 387         rxr->next_to_alloc = 0;
 388
 389         return 0;
 390 }
 391
 392 static void
 393 enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring,
 394                   struct rte_mempool *mb_pool)
 395 {
 396         int idx = rx_ring->index;
 397         uint16_t buf_size;
 398         phys_addr_t bd_address;
 399
 400         bd_address = (phys_addr_t)
 401                      rte_mem_virt2iova((const void *)rx_ring->bd_base);
 402         enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0,
 403                        lower_32_bits((uint64_t)bd_address));
 404         enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1,
 405                        upper_32_bits((uint64_t)bd_address));
 406         enetc_rxbdr_wr(hw, idx, ENETC_RBLENR,
 407                        ENETC_RTBLENR_LEN(rx_ring->bd_count));
 408
 409         rx_ring->mb_pool = mb_pool;
 410         rx_ring->rcir = (void *)((size_t)hw->reg +
 411                         ENETC_BDR(RX, idx, ENETC_RBCIR));
 412         enetc_refill_rx_ring(rx_ring, (enetc_bd_unused(rx_ring)));
 413         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rx_ring->mb_pool) -
 414                    RTE_PKTMBUF_HEADROOM);
 415         enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, buf_size);
 416         enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0);
 417 }
 418
 419 static int
 420 enetc_rx_queue_setup(struct rte_eth_dev *dev,
 421                      uint16_t rx_queue_id,
 422                      uint16_t nb_rx_desc,
 423                      unsigned int socket_id __rte_unused,
 424                      const struct rte_eth_rxconf *rx_conf,
 425                      struct rte_mempool *mb_pool)
 426 {
 427         int err = 0;
 428         struct enetc_bdr *rx_ring;
 429         struct rte_eth_dev_data *data =  dev->data;
 430         struct enetc_eth_adapter *adapter =
 431                         ENETC_DEV_PRIVATE(data->dev_private);
 432         uint64_t rx_offloads = data->dev_conf.rxmode.offloads;
 433
 434         PMD_INIT_FUNC_TRACE();
 435         if (nb_rx_desc > MAX_BD_COUNT)
 436                 return -1;
 437
 438         rx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0);
 439         if (rx_ring == NULL) {
 440                 ENETC_PMD_ERR("Failed to allocate RX ring memory");
 441                 err = -ENOMEM;
 442                 return err;
 443         }
 444
 445         err = enetc_alloc_rxbdr(rx_ring, nb_rx_desc);
 446         if (err)
 447                 goto fail;
 448
 449         rx_ring->index = rx_queue_id;
 450         rx_ring->ndev = dev;
 451         enetc_setup_rxbdr(&adapter->hw.hw, rx_ring, mb_pool);
 452         data->rx_queues[rx_queue_id] = rx_ring;
 453
 454         if (!rx_conf->rx_deferred_start) {
 455                 /* enable ring */
 456                 enetc_rxbdr_wr(&adapter->hw.hw, rx_ring->index, ENETC_RBMR,
 457                                ENETC_RBMR_EN);
 458                 dev->data->rx_queue_state[rx_ring->index] =
 459                                RTE_ETH_QUEUE_STATE_STARTED;
 460         } else {
 461                 dev->data->rx_queue_state[rx_ring->index] =
 462                                RTE_ETH_QUEUE_STATE_STOPPED;
 463         }
 464
 465         rx_ring->crc_len = (uint8_t)((rx_offloads & DEV_RX_OFFLOAD_KEEP_CRC) ?
 466                                      RTE_ETHER_CRC_LEN : 0);
 467
 468         return 0;
 469 fail:
 470         rte_free(rx_ring);
 471
 472         return err;
 473 }
 474
 475 static void
 476 enetc_rx_queue_release(void *rxq)
 477 {
 478         if (rxq == NULL)
 479                 return;
 480
 481         struct enetc_bdr *rx_ring = (struct enetc_bdr *)rxq;
 482         struct enetc_eth_hw *eth_hw =
 483                 ENETC_DEV_PRIVATE_TO_HW(rx_ring->ndev->data->dev_private);
 484         struct enetc_swbd *q_swbd;
 485         struct enetc_hw *hw;
 486         uint32_t val;
 487         int i;
 488
 489         /* Disable the ring */
 490         hw = &eth_hw->hw;
 491         val = enetc_rxbdr_rd(hw, rx_ring->index, ENETC_RBMR);
 492         val &= (~ENETC_RBMR_EN);
 493         enetc_rxbdr_wr(hw, rx_ring->index, ENETC_RBMR, val);
 494
 495         /* Clean the ring */
 496         i = rx_ring->next_to_clean;
 497         q_swbd = &rx_ring->q_swbd[i];
 498         while (i != rx_ring->next_to_use) {
 499                 rte_pktmbuf_free(q_swbd->buffer_addr);
 500                 q_swbd->buffer_addr = NULL;
 501                 q_swbd++;
 502                 i++;
 503                 if (unlikely(i == rx_ring->bd_count)) {
 504                         i = 0;
 505                         q_swbd = &rx_ring->q_swbd[i];
 506                 }
 507         }
 508
 509         enetc_free_bdr(rx_ring);
 510         rte_free(rx_ring);
 511 }
 512
 513 static
 514 int enetc_stats_get(struct rte_eth_dev *dev,
 515                     struct rte_eth_stats *stats)
 516 {
 517         struct enetc_eth_hw *hw =
 518                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 519         struct enetc_hw *enetc_hw = &hw->hw;
 520
 521         /* Total received packets, bad + good, if we want to get counters of
 522          * only good received packets then use ENETC_PM0_RFRM,
 523          * ENETC_PM0_TFRM registers.
 524          */
 525         stats->ipackets = enetc_port_rd(enetc_hw, ENETC_PM0_RPKT);
 526         stats->opackets = enetc_port_rd(enetc_hw, ENETC_PM0_TPKT);
 527         stats->ibytes =  enetc_port_rd(enetc_hw, ENETC_PM0_REOCT);
 528         stats->obytes = enetc_port_rd(enetc_hw, ENETC_PM0_TEOCT);
 529         /* Dropped + Truncated packets, use ENETC_PM0_RDRNTP for without
 530          * truncated packets
 531          */
 532         stats->imissed = enetc_port_rd(enetc_hw, ENETC_PM0_RDRP);
 533         stats->ierrors = enetc_port_rd(enetc_hw, ENETC_PM0_RERR);
 534         stats->oerrors = enetc_port_rd(enetc_hw, ENETC_PM0_TERR);
 535
 536         return 0;
 537 }
 538
 539 static int
 540 enetc_stats_reset(struct rte_eth_dev *dev)
 541 {
 542         struct enetc_eth_hw *hw =
 543                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 544         struct enetc_hw *enetc_hw = &hw->hw;
 545
 546         enetc_port_wr(enetc_hw, ENETC_PM0_STAT_CONFIG, ENETC_CLEAR_STATS);
 547
 548         return 0;
 549 }
 550
 551 static int
 552 enetc_dev_close(struct rte_eth_dev *dev)
 553 {
 554         uint16_t i;
 555         int ret;
 556
 557         PMD_INIT_FUNC_TRACE();
 558         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 559                 return 0;
 560
 561         ret = enetc_dev_stop(dev);
 562
 563         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 564                 enetc_rx_queue_release(dev->data->rx_queues[i]);
 565                 dev->data->rx_queues[i] = NULL;
 566         }
 567         dev->data->nb_rx_queues = 0;
 568
 569         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 570                 enetc_tx_queue_release(dev->data->tx_queues[i]);
 571                 dev->data->tx_queues[i] = NULL;
 572         }
 573         dev->data->nb_tx_queues = 0;
 574
 575         if (rte_eal_iova_mode() == RTE_IOVA_PA)
 576                 dpaax_iova_table_depopulate();
 577
 578         return ret;
 579 }
 580
 581 static int
 582 enetc_promiscuous_enable(struct rte_eth_dev *dev)
 583 {
 584         struct enetc_eth_hw *hw =
 585                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 586         struct enetc_hw *enetc_hw = &hw->hw;
 587         uint32_t psipmr = 0;
 588
 589         psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR);
 590
 591         /* Setting to enable promiscuous mode*/
 592         psipmr |= ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
 593
 594         enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
 595
 596         return 0;
 597 }
 598
 599 static int
 600 enetc_promiscuous_disable(struct rte_eth_dev *dev)
 601 {
 602         struct enetc_eth_hw *hw =
 603                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 604         struct enetc_hw *enetc_hw = &hw->hw;
 605         uint32_t psipmr = 0;
 606
 607         /* Setting to disable promiscuous mode for SI0*/
 608         psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR);
 609         psipmr &= (~ENETC_PSIPMR_SET_UP(0));
 610
 611         if (dev->data->all_multicast == 0)
 612                 psipmr &= (~ENETC_PSIPMR_SET_MP(0));
 613
 614         enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
 615
 616         return 0;
 617 }
 618
 619 static int
 620 enetc_allmulticast_enable(struct rte_eth_dev *dev)
 621 {
 622         struct enetc_eth_hw *hw =
 623                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 624         struct enetc_hw *enetc_hw = &hw->hw;
 625         uint32_t psipmr = 0;
 626
 627         psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR);
 628
 629         /* Setting to enable allmulticast mode for SI0*/
 630         psipmr |= ENETC_PSIPMR_SET_MP(0);
 631
 632         enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
 633
 634         return 0;
 635 }
 636
 637 static int
 638 enetc_allmulticast_disable(struct rte_eth_dev *dev)
 639 {
 640         struct enetc_eth_hw *hw =
 641                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 642         struct enetc_hw *enetc_hw = &hw->hw;
 643         uint32_t psipmr = 0;
 644
 645         if (dev->data->promiscuous == 1)
 646                 return 0; /* must remain in all_multicast mode */
 647
 648         /* Setting to disable all multicast mode for SI0*/
 649         psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR) &
 650                                ~(ENETC_PSIPMR_SET_MP(0));
 651
 652         enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
 653
 654         return 0;
 655 }
 656
 657 static int
 658 enetc_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 659 {
 660         struct enetc_eth_hw *hw =
 661                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 662         struct enetc_hw *enetc_hw = &hw->hw;
 663         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
 664
 665         /* check that mtu is within the allowed range */
 666         if (mtu < ENETC_MAC_MINFRM_SIZE || frame_size > ENETC_MAC_MAXFRM_SIZE)
 667                 return -EINVAL;
 668
 669         /*
 670          * Refuse mtu that requires the support of scattered packets
 671          * when this feature has not been enabled before.
 672          */
 673         if (dev->data->min_rx_buf_size &&
 674                 !dev->data->scattered_rx && frame_size >
 675                 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
 676                 ENETC_PMD_ERR("SG not enabled, will not fit in one buffer");
 677                 return -EINVAL;
 678         }
 679
 680         if (frame_size > ENETC_ETH_MAX_LEN)
 681                 dev->data->dev_conf.rxmode.offloads &=
 682                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 683         else
 684                 dev->data->dev_conf.rxmode.offloads &=
 685                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 686
 687         enetc_port_wr(enetc_hw, ENETC_PTCMSDUR(0), ENETC_MAC_MAXFRM_SIZE);
 688         enetc_port_wr(enetc_hw, ENETC_PTXMBAR, 2 * ENETC_MAC_MAXFRM_SIZE);
 689
 690         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 691
 692         /*setting the MTU*/
 693         enetc_port_wr(enetc_hw, ENETC_PM0_MAXFRM, ENETC_SET_MAXFRM(frame_size) |
 694                       ENETC_SET_TX_MTU(ENETC_MAC_MAXFRM_SIZE));
 695
 696         return 0;
 697 }
 698
 699 static int
 700 enetc_dev_configure(struct rte_eth_dev *dev)
 701 {
 702         struct enetc_eth_hw *hw =
 703                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 704         struct enetc_hw *enetc_hw = &hw->hw;
 705         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 706         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 707         uint32_t checksum = L3_CKSUM | L4_CKSUM;
 708
 709         PMD_INIT_FUNC_TRACE();
 710
 711         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 712                 uint32_t max_len;
 713
 714                 max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 715
 716                 enetc_port_wr(enetc_hw, ENETC_PM0_MAXFRM,
 717                               ENETC_SET_MAXFRM(max_len));
 718                 enetc_port_wr(enetc_hw, ENETC_PTCMSDUR(0),
 719                               ENETC_MAC_MAXFRM_SIZE);
 720                 enetc_port_wr(enetc_hw, ENETC_PTXMBAR,
 721                               2 * ENETC_MAC_MAXFRM_SIZE);
 722                 dev->data->mtu = RTE_ETHER_MAX_LEN - RTE_ETHER_HDR_LEN -
 723                         RTE_ETHER_CRC_LEN;
 724         }
 725
 726         if (rx_offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
 727                 int config;
 728
 729                 config = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG);
 730                 config |= ENETC_PM0_CRC;
 731                 enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG, config);
 732         }
 733
 734         if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
 735                 checksum &= ~L3_CKSUM;
 736
 737         if (rx_offloads & (DEV_RX_OFFLOAD_UDP_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM))
 738                 checksum &= ~L4_CKSUM;
 739
 740         enetc_port_wr(enetc_hw, ENETC_PAR_PORT_CFG, checksum);
 741
 742
 743         return 0;
 744 }
 745
 746 static int
 747 enetc_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
 748 {
 749         struct enetc_eth_adapter *priv =
 750                         ENETC_DEV_PRIVATE(dev->data->dev_private);
 751         struct enetc_bdr *rx_ring;
 752         uint32_t rx_data;
 753
 754         rx_ring = dev->data->rx_queues[qidx];
 755         if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) {
 756                 rx_data = enetc_rxbdr_rd(&priv->hw.hw, rx_ring->index,
 757                                          ENETC_RBMR);
 758                 rx_data = rx_data | ENETC_RBMR_EN;
 759                 enetc_rxbdr_wr(&priv->hw.hw, rx_ring->index, ENETC_RBMR,
 760                                rx_data);
 761                 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
 762         }
 763
 764         return 0;
 765 }
 766
 767 static int
 768 enetc_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
 769 {
 770         struct enetc_eth_adapter *priv =
 771                         ENETC_DEV_PRIVATE(dev->data->dev_private);
 772         struct enetc_bdr *rx_ring;
 773         uint32_t rx_data;
 774
 775         rx_ring = dev->data->rx_queues[qidx];
 776         if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) {
 777                 rx_data = enetc_rxbdr_rd(&priv->hw.hw, rx_ring->index,
 778                                          ENETC_RBMR);
 779                 rx_data = rx_data & (~ENETC_RBMR_EN);
 780                 enetc_rxbdr_wr(&priv->hw.hw, rx_ring->index, ENETC_RBMR,
 781                                rx_data);
 782                 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
 783         }
 784
 785         return 0;
 786 }
 787
 788 static int
 789 enetc_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
 790 {
 791         struct enetc_eth_adapter *priv =
 792                         ENETC_DEV_PRIVATE(dev->data->dev_private);
 793         struct enetc_bdr *tx_ring;
 794         uint32_t tx_data;
 795
 796         tx_ring = dev->data->tx_queues[qidx];
 797         if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) {
 798                 tx_data = enetc_txbdr_rd(&priv->hw.hw, tx_ring->index,
 799                                          ENETC_TBMR);
 800                 tx_data = tx_data | ENETC_TBMR_EN;
 801                 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, ENETC_TBMR,
 802                                tx_data);
 803                 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
 804         }
 805
 806         return 0;
 807 }
 808
 809 static int
 810 enetc_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
 811 {
 812         struct enetc_eth_adapter *priv =
 813                         ENETC_DEV_PRIVATE(dev->data->dev_private);
 814         struct enetc_bdr *tx_ring;
 815         uint32_t tx_data;
 816
 817         tx_ring = dev->data->tx_queues[qidx];
 818         if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) {
 819                 tx_data = enetc_txbdr_rd(&priv->hw.hw, tx_ring->index,
 820                                          ENETC_TBMR);
 821                 tx_data = tx_data & (~ENETC_TBMR_EN);
 822                 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, ENETC_TBMR,
 823                                tx_data);
 824                 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
 825         }
 826
 827         return 0;
 828 }
 829
 830 /*
 831  * The set of PCI devices this driver supports
 832  */
 833 static const struct rte_pci_id pci_id_enetc_map[] = {
 834         { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID) },
 835         { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_VF) },
 836         { .vendor_id = 0, /* sentinel */ },
 837 };
 838
 839 /* Features supported by this driver */
 840 static const struct eth_dev_ops enetc_ops = {
 841         .dev_configure        = enetc_dev_configure,
 842         .dev_start            = enetc_dev_start,
 843         .dev_stop             = enetc_dev_stop,
 844         .dev_close            = enetc_dev_close,
 845         .link_update          = enetc_link_update,
 846         .stats_get            = enetc_stats_get,
 847         .stats_reset          = enetc_stats_reset,
 848         .promiscuous_enable   = enetc_promiscuous_enable,
 849         .promiscuous_disable  = enetc_promiscuous_disable,
 850         .allmulticast_enable  = enetc_allmulticast_enable,
 851         .allmulticast_disable = enetc_allmulticast_disable,
 852         .dev_infos_get        = enetc_dev_infos_get,
 853         .mtu_set              = enetc_mtu_set,
 854         .rx_queue_setup       = enetc_rx_queue_setup,
 855         .rx_queue_start       = enetc_rx_queue_start,
 856         .rx_queue_stop        = enetc_rx_queue_stop,
 857         .rx_queue_release     = enetc_rx_queue_release,
 858         .tx_queue_setup       = enetc_tx_queue_setup,
 859         .tx_queue_start       = enetc_tx_queue_start,
 860         .tx_queue_stop        = enetc_tx_queue_stop,
 861         .tx_queue_release     = enetc_tx_queue_release,
 862         .dev_supported_ptypes_get = enetc_supported_ptypes_get,
 863 };
 864
 865 /**
 866  * Initialisation of the enetc device
 867  *
 868  * @param eth_dev
 869  *   - Pointer to the structure rte_eth_dev
 870  *
 871  * @return
 872  *   - On success, zero.
 873  *   - On failure, negative value.
 874  */
 875 static int
 876 enetc_dev_init(struct rte_eth_dev *eth_dev)
 877 {
 878         int error = 0;
 879         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 880         struct enetc_eth_hw *hw =
 881                 ENETC_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 882
 883         PMD_INIT_FUNC_TRACE();
 884         eth_dev->dev_ops = &enetc_ops;
 885         eth_dev->rx_pkt_burst = &enetc_recv_pkts;
 886         eth_dev->tx_pkt_burst = &enetc_xmit_pkts;
 887
 888         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 889
 890         /* Retrieving and storing the HW base address of device */
 891         hw->hw.reg = (void *)pci_dev->mem_resource[0].addr;
 892         hw->device_id = pci_dev->id.device_id;
 893
 894         error = enetc_hardware_init(hw);
 895         if (error != 0) {
 896                 ENETC_PMD_ERR("Hardware initialization failed");
 897                 return -1;
 898         }
 899
 900         /* Allocate memory for storing MAC addresses */
 901         eth_dev->data->mac_addrs = rte_zmalloc("enetc_eth",
 902                                         RTE_ETHER_ADDR_LEN, 0);
 903         if (!eth_dev->data->mac_addrs) {
 904                 ENETC_PMD_ERR("Failed to allocate %d bytes needed to "
 905                               "store MAC addresses",
 906                               RTE_ETHER_ADDR_LEN * 1);
 907                 error = -ENOMEM;
 908                 return -1;
 909         }
 910
 911         /* Copy the permanent MAC address */
 912         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 913                         &eth_dev->data->mac_addrs[0]);
 914
 915         /* Set MTU */
 916         enetc_port_wr(&hw->hw, ENETC_PM0_MAXFRM,
 917                       ENETC_SET_MAXFRM(RTE_ETHER_MAX_LEN));
 918         eth_dev->data->mtu = RTE_ETHER_MAX_LEN - RTE_ETHER_HDR_LEN -
 919                 RTE_ETHER_CRC_LEN;
 920
 921         if (rte_eal_iova_mode() == RTE_IOVA_PA)
 922                 dpaax_iova_table_populate();
 923
 924         ENETC_PMD_DEBUG("port_id %d vendorID=0x%x deviceID=0x%x",
 925                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 926                         pci_dev->id.device_id);
 927         return 0;
 928 }
 929
 930 static int
 931 enetc_dev_uninit(struct rte_eth_dev *eth_dev)
 932 {
 933         PMD_INIT_FUNC_TRACE();
 934
 935         return enetc_dev_close(eth_dev);
 936 }
 937
 938 static int
 939 enetc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 940                            struct rte_pci_device *pci_dev)
 941 {
 942         return rte_eth_dev_pci_generic_probe(pci_dev,
 943                                              sizeof(struct enetc_eth_adapter),
 944                                              enetc_dev_init);
 945 }
 946
 947 static int
 948 enetc_pci_remove(struct rte_pci_device *pci_dev)
 949 {
 950         return rte_eth_dev_pci_generic_remove(pci_dev, enetc_dev_uninit);
 951 }
 952
 953 static struct rte_pci_driver rte_enetc_pmd = {
 954         .id_table = pci_id_enetc_map,
 955         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 956         .probe = enetc_pci_probe,
 957         .remove = enetc_pci_remove,
 958 };
 959
 960 RTE_PMD_REGISTER_PCI(net_enetc, rte_enetc_pmd);
 961 RTE_PMD_REGISTER_PCI_TABLE(net_enetc, pci_id_enetc_map);
 962 RTE_PMD_REGISTER_KMOD_DEP(net_enetc, "* vfio-pci");
 963 RTE_LOG_REGISTER_DEFAULT(enetc_logtype_pmd, NOTICE);