drivers/net/enetfec/enet_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2020-2021 NXP
   3  */
   4
   5 #ifndef __ENETFEC_ETHDEV_H__
   6 #define __ENETFEC_ETHDEV_H__
   7
   8 #include <rte_ethdev.h>
   9
  10 /* full duplex */
  11 #define FULL_DUPLEX             0x00
  12
  13 #define PKT_MAX_BUF_SIZE        1984
  14 #define OPT_FRAME_SIZE          (PKT_MAX_BUF_SIZE << 16)
  15
  16 /*
  17  * ENETFEC can support 1 rx and tx queue..
  18  */
  19
  20 #define ENETFEC_MAX_Q           1
  21
  22 #define writel(v, p) ({*(volatile unsigned int *)(p) = (v); })
  23 #define readl(p) rte_read32(p)
  24
  25 struct enetfec_private {
  26         struct rte_eth_dev      *dev;
  27         int                     full_duplex;
  28         int                     flag_pause;
  29         uint32_t                quirks;
  30         uint32_t                cbus_size;
  31         uint32_t                enetfec_e_cntl;
  32         uint16_t                max_rx_queues;
  33         uint16_t                max_tx_queues;
  34         unsigned int            reg_size;
  35         unsigned int            bd_size;
  36         bool                    bufdesc_ex;
  37         bool                    rgmii_txc_delay;
  38         bool                    rgmii_rxc_delay;
  39         void                    *hw_baseaddr_v;
  40         void                    *bd_addr_v;
  41         uint32_t                hw_baseaddr_p;
  42         uint32_t                bd_addr_p;
  43         uint32_t                bd_addr_p_r[ENETFEC_MAX_Q];
  44         uint32_t                bd_addr_p_t[ENETFEC_MAX_Q];
  45         void                    *dma_baseaddr_r[ENETFEC_MAX_Q];
  46         void                    *dma_baseaddr_t[ENETFEC_MAX_Q];
  47 };
  48
  49 #endif /*__ENETFEC_ETHDEV_H__*/