52e0402bdf0d92dbb110888e99a8b3768b1f4def
[dpdk.git] / drivers / net / enic / base / cq_desc.h
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright 2008-2017 Cisco Systems, Inc.  All rights reserved.
3  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
4  */
5
6 #ifndef _CQ_DESC_H_
7 #define _CQ_DESC_H_
8 #include <rte_byteorder.h>
9
10 /*
11  * Completion queue descriptor types
12  */
13 enum cq_desc_types {
14         CQ_DESC_TYPE_WQ_ENET = 0,
15         CQ_DESC_TYPE_DESC_COPY = 1,
16         CQ_DESC_TYPE_WQ_EXCH = 2,
17         CQ_DESC_TYPE_RQ_ENET = 3,
18         CQ_DESC_TYPE_RQ_FCP = 4,
19         CQ_DESC_TYPE_IOMMU_MISS = 5,
20         CQ_DESC_TYPE_SGL = 6,
21         CQ_DESC_TYPE_CLASSIFIER = 7,
22         CQ_DESC_TYPE_TEST = 127,
23 };
24
25 /* Completion queue descriptor: 16B
26  *
27  * All completion queues have this basic layout.  The
28  * type_specfic area is unique for each completion
29  * queue type.
30  */
31 struct cq_desc {
32         __le16 completed_index;
33         __le16 q_number;
34         u8 type_specfic[11];
35         u8 type_color;
36 };
37
38 #define CQ_DESC_TYPE_BITS        4
39 #define CQ_DESC_TYPE_MASK        ((1 << CQ_DESC_TYPE_BITS) - 1)
40 #define CQ_DESC_COLOR_MASK       1
41 #define CQ_DESC_COLOR_SHIFT      7
42 #define CQ_DESC_COLOR_MASK_NOSHIFT 0x80
43 #define CQ_DESC_Q_NUM_BITS       10
44 #define CQ_DESC_Q_NUM_MASK       ((1 << CQ_DESC_Q_NUM_BITS) - 1)
45 #define CQ_DESC_COMP_NDX_BITS    12
46 #define CQ_DESC_COMP_NDX_MASK    ((1 << CQ_DESC_COMP_NDX_BITS) - 1)
47
48 static inline void cq_color_enc(struct cq_desc *desc, const u8 color)
49 {
50         if (color)
51                 desc->type_color |=  (1 << CQ_DESC_COLOR_SHIFT);
52         else
53                 desc->type_color &= ~(1 << CQ_DESC_COLOR_SHIFT);
54 }
55
56 static inline void cq_desc_enc(struct cq_desc *desc,
57         const u8 type, const u8 color, const u16 q_number,
58         const u16 completed_index)
59 {
60         desc->type_color = (type & CQ_DESC_TYPE_MASK) |
61                 ((color & CQ_DESC_COLOR_MASK) << CQ_DESC_COLOR_SHIFT);
62         desc->q_number = rte_cpu_to_le_16(q_number & CQ_DESC_Q_NUM_MASK);
63         desc->completed_index = rte_cpu_to_le_16(completed_index &
64                 CQ_DESC_COMP_NDX_MASK);
65 }
66
67 static inline void cq_desc_dec(const struct cq_desc *desc_arg,
68         u8 *type, u8 *color, u16 *q_number, u16 *completed_index)
69 {
70         const struct cq_desc *desc = desc_arg;
71         const u8 type_color = desc->type_color;
72
73         *color = (type_color >> CQ_DESC_COLOR_SHIFT) & CQ_DESC_COLOR_MASK;
74
75         /*
76          * Make sure color bit is read from desc *before* other fields
77          * are read from desc.  Hardware guarantees color bit is last
78          * bit (byte) written.  Adding the rmb() prevents the compiler
79          * and/or CPU from reordering the reads which would potentially
80          * result in reading stale values.
81          */
82
83         rmb();
84
85         *type = type_color & CQ_DESC_TYPE_MASK;
86         *q_number = rte_le_to_cpu_16(desc->q_number) & CQ_DESC_Q_NUM_MASK;
87         *completed_index = rte_le_to_cpu_16(desc->completed_index) &
88                 CQ_DESC_COMP_NDX_MASK;
89 }
90
91 static inline void cq_color_dec(const struct cq_desc *desc_arg, u8 *color)
92 {
93         volatile const struct cq_desc *desc = desc_arg;
94
95         *color = (desc->type_color >> CQ_DESC_COLOR_SHIFT) & CQ_DESC_COLOR_MASK;
96 }
97
98 #endif /* _CQ_DESC_H_ */