drivers/net/enic/enic_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2008-2017 Cisco Systems, Inc.  All rights reserved.
   3  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
   4  */
   5
   6 #include <stdio.h>
   7 #include <stdint.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_pci.h>
  11 #include <rte_bus_pci.h>
  12 #include <ethdev_driver.h>
  13 #include <ethdev_pci.h>
  14 #include <rte_kvargs.h>
  15 #include <rte_string_fns.h>
  16
  17 #include "vnic_intr.h"
  18 #include "vnic_cq.h"
  19 #include "vnic_wq.h"
  20 #include "vnic_rq.h"
  21 #include "vnic_enet.h"
  22 #include "enic.h"
  23
  24 /*
  25  * The set of PCI devices this driver supports
  26  */
  27 #define CISCO_PCI_VENDOR_ID 0x1137
  28 static const struct rte_pci_id pci_id_enic_map[] = {
  29         {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET)},
  30         {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_VF)},
  31         {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_SN)},
  32         {.vendor_id = 0, /* sentinel */},
  33 };
  34
  35 /* Supported link speeds of production VIC models */
  36 static const struct vic_speed_capa {
  37         uint16_t sub_devid;
  38         uint32_t capa;
  39 } vic_speed_capa_map[] = {
  40         { 0x0043, ETH_LINK_SPEED_10G }, /* VIC */
  41         { 0x0047, ETH_LINK_SPEED_10G }, /* P81E PCIe */
  42         { 0x0048, ETH_LINK_SPEED_10G }, /* M81KR Mezz */
  43         { 0x004f, ETH_LINK_SPEED_10G }, /* 1280 Mezz */
  44         { 0x0084, ETH_LINK_SPEED_10G }, /* 1240 MLOM */
  45         { 0x0085, ETH_LINK_SPEED_10G }, /* 1225 PCIe */
  46         { 0x00cd, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1285 PCIe */
  47         { 0x00ce, ETH_LINK_SPEED_10G }, /* 1225T PCIe */
  48         { 0x012a, ETH_LINK_SPEED_40G }, /* M4308 */
  49         { 0x012c, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1340 MLOM */
  50         { 0x012e, ETH_LINK_SPEED_10G }, /* 1227 PCIe */
  51         { 0x0137, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1380 Mezz */
  52         { 0x014d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1385 PCIe */
  53         { 0x015d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1387 MLOM */
  54         { 0x0215, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
  55                   ETH_LINK_SPEED_40G }, /* 1440 Mezz */
  56         { 0x0216, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
  57                   ETH_LINK_SPEED_40G }, /* 1480 MLOM */
  58         { 0x0217, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1455 PCIe */
  59         { 0x0218, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1457 MLOM */
  60         { 0x0219, ETH_LINK_SPEED_40G }, /* 1485 PCIe */
  61         { 0x021a, ETH_LINK_SPEED_40G }, /* 1487 MLOM */
  62         { 0x024a, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1495 PCIe */
  63         { 0x024b, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1497 MLOM */
  64         { 0, 0 }, /* End marker */
  65 };
  66
  67 #define ENIC_DEVARG_CQ64 "cq64"
  68 #define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay"
  69 #define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx"
  70 #define ENIC_DEVARG_GENEVE_OPT "geneve-opt"
  71 #define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite"
  72 #define ENIC_DEVARG_REPRESENTOR "representor"
  73
  74 RTE_LOG_REGISTER(enic_pmd_logtype, pmd.net.enic, INFO);
  75
  76 static int
  77 enicpmd_dev_filter_ctrl(struct rte_eth_dev *dev,
  78                      enum rte_filter_type filter_type,
  79                      enum rte_filter_op filter_op,
  80                      void *arg)
  81 {
  82         struct enic *enic = pmd_priv(dev);
  83         int ret = 0;
  84
  85         ENICPMD_FUNC_TRACE();
  86
  87         /*
  88          * Currently, when Geneve with options offload is enabled, host
  89          * cannot insert match-action rules.
  90          */
  91         if (enic->geneve_opt_enabled)
  92                 return -ENOTSUP;
  93         switch (filter_type) {
  94         case RTE_ETH_FILTER_GENERIC:
  95                 if (filter_op != RTE_ETH_FILTER_GET)
  96                         return -EINVAL;
  97                 if (enic->flow_filter_mode == FILTER_FLOWMAN)
  98                         *(const void **)arg = &enic_fm_flow_ops;
  99                 else
 100                         *(const void **)arg = &enic_flow_ops;
 101                 break;
 102         default:
 103                 dev_warning(enic, "Filter type (%d) not supported",
 104                         filter_type);
 105                 ret = -EINVAL;
 106                 break;
 107         }
 108
 109         return ret;
 110 }
 111
 112 static void enicpmd_dev_tx_queue_release(void *txq)
 113 {
 114         ENICPMD_FUNC_TRACE();
 115
 116         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 117                 return;
 118
 119         enic_free_wq(txq);
 120 }
 121
 122 static int enicpmd_dev_setup_intr(struct enic *enic)
 123 {
 124         int ret;
 125         unsigned int index;
 126
 127         ENICPMD_FUNC_TRACE();
 128
 129         /* Are we done with the init of all the queues? */
 130         for (index = 0; index < enic->cq_count; index++) {
 131                 if (!enic->cq[index].ctrl)
 132                         break;
 133         }
 134         if (enic->cq_count != index)
 135                 return 0;
 136         for (index = 0; index < enic->wq_count; index++) {
 137                 if (!enic->wq[index].ctrl)
 138                         break;
 139         }
 140         if (enic->wq_count != index)
 141                 return 0;
 142         /* check start of packet (SOP) RQs only in case scatter is disabled. */
 143         for (index = 0; index < enic->rq_count; index++) {
 144                 if (!enic->rq[enic_rte_rq_idx_to_sop_idx(index)].ctrl)
 145                         break;
 146         }
 147         if (enic->rq_count != index)
 148                 return 0;
 149
 150         ret = enic_alloc_intr_resources(enic);
 151         if (ret) {
 152                 dev_err(enic, "alloc intr failed\n");
 153                 return ret;
 154         }
 155         enic_init_vnic_resources(enic);
 156
 157         ret = enic_setup_finish(enic);
 158         if (ret)
 159                 dev_err(enic, "setup could not be finished\n");
 160
 161         return ret;
 162 }
 163
 164 static int enicpmd_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
 165         uint16_t queue_idx,
 166         uint16_t nb_desc,
 167         unsigned int socket_id,
 168         const struct rte_eth_txconf *tx_conf)
 169 {
 170         int ret;
 171         struct enic *enic = pmd_priv(eth_dev);
 172         struct vnic_wq *wq;
 173
 174         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 175                 return -E_RTE_SECONDARY;
 176
 177         ENICPMD_FUNC_TRACE();
 178         RTE_ASSERT(queue_idx < enic->conf_wq_count);
 179         wq = &enic->wq[queue_idx];
 180         wq->offloads = tx_conf->offloads |
 181                 eth_dev->data->dev_conf.txmode.offloads;
 182         eth_dev->data->tx_queues[queue_idx] = (void *)wq;
 183
 184         ret = enic_alloc_wq(enic, queue_idx, socket_id, nb_desc);
 185         if (ret) {
 186                 dev_err(enic, "error in allocating wq\n");
 187                 return ret;
 188         }
 189
 190         return enicpmd_dev_setup_intr(enic);
 191 }
 192
 193 static int enicpmd_dev_tx_queue_start(struct rte_eth_dev *eth_dev,
 194         uint16_t queue_idx)
 195 {
 196         struct enic *enic = pmd_priv(eth_dev);
 197
 198         ENICPMD_FUNC_TRACE();
 199
 200         enic_start_wq(enic, queue_idx);
 201
 202         return 0;
 203 }
 204
 205 static int enicpmd_dev_tx_queue_stop(struct rte_eth_dev *eth_dev,
 206         uint16_t queue_idx)
 207 {
 208         int ret;
 209         struct enic *enic = pmd_priv(eth_dev);
 210
 211         ENICPMD_FUNC_TRACE();
 212
 213         ret = enic_stop_wq(enic, queue_idx);
 214         if (ret)
 215                 dev_err(enic, "error in stopping wq %d\n", queue_idx);
 216
 217         return ret;
 218 }
 219
 220 static int enicpmd_dev_rx_queue_start(struct rte_eth_dev *eth_dev,
 221         uint16_t queue_idx)
 222 {
 223         struct enic *enic = pmd_priv(eth_dev);
 224
 225         ENICPMD_FUNC_TRACE();
 226
 227         enic_start_rq(enic, queue_idx);
 228
 229         return 0;
 230 }
 231
 232 static int enicpmd_dev_rx_queue_stop(struct rte_eth_dev *eth_dev,
 233         uint16_t queue_idx)
 234 {
 235         int ret;
 236         struct enic *enic = pmd_priv(eth_dev);
 237
 238         ENICPMD_FUNC_TRACE();
 239
 240         ret = enic_stop_rq(enic, queue_idx);
 241         if (ret)
 242                 dev_err(enic, "error in stopping rq %d\n", queue_idx);
 243
 244         return ret;
 245 }
 246
 247 static void enicpmd_dev_rx_queue_release(void *rxq)
 248 {
 249         ENICPMD_FUNC_TRACE();
 250
 251         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 252                 return;
 253
 254         enic_free_rq(rxq);
 255 }
 256
 257 static uint32_t enicpmd_dev_rx_queue_count(struct rte_eth_dev *dev,
 258                                            uint16_t rx_queue_id)
 259 {
 260         struct enic *enic = pmd_priv(dev);
 261         uint32_t queue_count = 0;
 262         struct vnic_cq *cq;
 263         uint32_t cq_tail;
 264         uint16_t cq_idx;
 265         int rq_num;
 266
 267         rq_num = enic_rte_rq_idx_to_sop_idx(rx_queue_id);
 268         cq = &enic->cq[enic_cq_rq(enic, rq_num)];
 269         cq_idx = cq->to_clean;
 270
 271         cq_tail = ioread32(&cq->ctrl->cq_tail);
 272
 273         if (cq_tail < cq_idx)
 274                 cq_tail += cq->ring.desc_count;
 275
 276         queue_count = cq_tail - cq_idx;
 277
 278         return queue_count;
 279 }
 280
 281 static int enicpmd_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
 282         uint16_t queue_idx,
 283         uint16_t nb_desc,
 284         unsigned int socket_id,
 285         const struct rte_eth_rxconf *rx_conf,
 286         struct rte_mempool *mp)
 287 {
 288         int ret;
 289         struct enic *enic = pmd_priv(eth_dev);
 290
 291         ENICPMD_FUNC_TRACE();
 292
 293         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 294                 return -E_RTE_SECONDARY;
 295         RTE_ASSERT(enic_rte_rq_idx_to_sop_idx(queue_idx) < enic->conf_rq_count);
 296         eth_dev->data->rx_queues[queue_idx] =
 297                 (void *)&enic->rq[enic_rte_rq_idx_to_sop_idx(queue_idx)];
 298
 299         ret = enic_alloc_rq(enic, queue_idx, socket_id, mp, nb_desc,
 300                             rx_conf->rx_free_thresh);
 301         if (ret) {
 302                 dev_err(enic, "error in allocating rq\n");
 303                 return ret;
 304         }
 305
 306         return enicpmd_dev_setup_intr(enic);
 307 }
 308
 309 static int enicpmd_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 310 {
 311         struct enic *enic = pmd_priv(eth_dev);
 312         uint64_t offloads;
 313
 314         ENICPMD_FUNC_TRACE();
 315
 316         offloads = eth_dev->data->dev_conf.rxmode.offloads;
 317         if (mask & ETH_VLAN_STRIP_MASK) {
 318                 if (offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 319                         enic->ig_vlan_strip_en = 1;
 320                 else
 321                         enic->ig_vlan_strip_en = 0;
 322         }
 323
 324         return enic_set_vlan_strip(enic);
 325 }
 326
 327 static int enicpmd_dev_configure(struct rte_eth_dev *eth_dev)
 328 {
 329         int ret;
 330         int mask;
 331         struct enic *enic = pmd_priv(eth_dev);
 332
 333         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 334                 return -E_RTE_SECONDARY;
 335
 336         ENICPMD_FUNC_TRACE();
 337         ret = enic_set_vnic_res(enic);
 338         if (ret) {
 339                 dev_err(enic, "Set vNIC resource num  failed, aborting\n");
 340                 return ret;
 341         }
 342
 343         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 344                 eth_dev->data->dev_conf.rxmode.offloads |=
 345                         DEV_RX_OFFLOAD_RSS_HASH;
 346
 347         enic->mc_count = 0;
 348         enic->hw_ip_checksum = !!(eth_dev->data->dev_conf.rxmode.offloads &
 349                                   DEV_RX_OFFLOAD_CHECKSUM);
 350         /* All vlan offload masks to apply the current settings */
 351         mask = ETH_VLAN_STRIP_MASK |
 352                 ETH_VLAN_FILTER_MASK |
 353                 ETH_VLAN_EXTEND_MASK;
 354         ret = enicpmd_vlan_offload_set(eth_dev, mask);
 355         if (ret) {
 356                 dev_err(enic, "Failed to configure VLAN offloads\n");
 357                 return ret;
 358         }
 359         /*
 360          * Initialize RSS with the default reta and key. If the user key is
 361          * given (rx_adv_conf.rss_conf.rss_key), will use that instead of the
 362          * default key.
 363          */
 364         return enic_init_rss_nic_cfg(enic);
 365 }
 366
 367 /* Start the device.
 368  * It returns 0 on success.
 369  */
 370 static int enicpmd_dev_start(struct rte_eth_dev *eth_dev)
 371 {
 372         struct enic *enic = pmd_priv(eth_dev);
 373
 374         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 375                 return -E_RTE_SECONDARY;
 376
 377         ENICPMD_FUNC_TRACE();
 378         return enic_enable(enic);
 379 }
 380
 381 /*
 382  * Stop device: disable rx and tx functions to allow for reconfiguring.
 383  */
 384 static int enicpmd_dev_stop(struct rte_eth_dev *eth_dev)
 385 {
 386         struct rte_eth_link link;
 387         struct enic *enic = pmd_priv(eth_dev);
 388
 389         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 390                 return 0;
 391
 392         ENICPMD_FUNC_TRACE();
 393         enic_disable(enic);
 394
 395         memset(&link, 0, sizeof(link));
 396         rte_eth_linkstatus_set(eth_dev, &link);
 397
 398         return 0;
 399 }
 400
 401 /*
 402  * Stop device.
 403  */
 404 static int enicpmd_dev_close(struct rte_eth_dev *eth_dev)
 405 {
 406         struct enic *enic = pmd_priv(eth_dev);
 407
 408         ENICPMD_FUNC_TRACE();
 409         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 410                 return 0;
 411
 412         enic_remove(enic);
 413
 414         return 0;
 415 }
 416
 417 static int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev,
 418         __rte_unused int wait_to_complete)
 419 {
 420         ENICPMD_FUNC_TRACE();
 421         return enic_link_update(eth_dev);
 422 }
 423
 424 static int enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev,
 425         struct rte_eth_stats *stats)
 426 {
 427         struct enic *enic = pmd_priv(eth_dev);
 428
 429         ENICPMD_FUNC_TRACE();
 430         return enic_dev_stats_get(enic, stats);
 431 }
 432
 433 static int enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev)
 434 {
 435         struct enic *enic = pmd_priv(eth_dev);
 436
 437         ENICPMD_FUNC_TRACE();
 438         return enic_dev_stats_clear(enic);
 439 }
 440
 441 static uint32_t speed_capa_from_pci_id(struct rte_eth_dev *eth_dev)
 442 {
 443         const struct vic_speed_capa *m;
 444         struct rte_pci_device *pdev;
 445         uint16_t id;
 446
 447         pdev = RTE_ETH_DEV_TO_PCI(eth_dev);
 448         id = pdev->id.subsystem_device_id;
 449         for (m = vic_speed_capa_map; m->sub_devid != 0; m++) {
 450                 if (m->sub_devid == id)
 451                         return m->capa;
 452         }
 453         /* 1300 and later models are at least 40G */
 454         if (id >= 0x0100)
 455                 return ETH_LINK_SPEED_40G;
 456         /* VFs have subsystem id 0, check device id */
 457         if (id == 0) {
 458                 /* Newer VF implies at least 40G model */
 459                 if (pdev->id.device_id == PCI_DEVICE_ID_CISCO_VIC_ENET_SN)
 460                         return ETH_LINK_SPEED_40G;
 461         }
 462         return ETH_LINK_SPEED_10G;
 463 }
 464
 465 static int enicpmd_dev_info_get(struct rte_eth_dev *eth_dev,
 466         struct rte_eth_dev_info *device_info)
 467 {
 468         struct enic *enic = pmd_priv(eth_dev);
 469
 470         ENICPMD_FUNC_TRACE();
 471         /* Scattered Rx uses two receive queues per rx queue exposed to dpdk */
 472         device_info->max_rx_queues = enic->conf_rq_count / 2;
 473         device_info->max_tx_queues = enic->conf_wq_count;
 474         device_info->min_rx_bufsize = ENIC_MIN_MTU;
 475         /* "Max" mtu is not a typo. HW receives packet sizes up to the
 476          * max mtu regardless of the current mtu (vNIC's mtu). vNIC mtu is
 477          * a hint to the driver to size receive buffers accordingly so that
 478          * larger-than-vnic-mtu packets get truncated.. For DPDK, we let
 479          * the user decide the buffer size via rxmode.max_rx_pkt_len, basically
 480          * ignoring vNIC mtu.
 481          */
 482         device_info->max_rx_pktlen = enic_mtu_to_max_rx_pktlen(enic->max_mtu);
 483         device_info->max_mac_addrs = ENIC_UNICAST_PERFECT_FILTERS;
 484         device_info->min_mtu = ENIC_MIN_MTU;
 485         device_info->max_mtu = enic->max_mtu;
 486         device_info->rx_offload_capa = enic->rx_offload_capa;
 487         device_info->tx_offload_capa = enic->tx_offload_capa;
 488         device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa;
 489         device_info->default_rxconf = (struct rte_eth_rxconf) {
 490                 .rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH
 491         };
 492         device_info->reta_size = enic->reta_size;
 493         device_info->hash_key_size = enic->hash_key_size;
 494         device_info->flow_type_rss_offloads = enic->flow_type_rss_offloads;
 495         device_info->rx_desc_lim = (struct rte_eth_desc_lim) {
 496                 .nb_max = enic->config.rq_desc_count,
 497                 .nb_min = ENIC_MIN_RQ_DESCS,
 498                 .nb_align = ENIC_ALIGN_DESCS,
 499         };
 500         device_info->tx_desc_lim = (struct rte_eth_desc_lim) {
 501                 .nb_max = enic->config.wq_desc_count,
 502                 .nb_min = ENIC_MIN_WQ_DESCS,
 503                 .nb_align = ENIC_ALIGN_DESCS,
 504                 .nb_seg_max = ENIC_TX_XMIT_MAX,
 505                 .nb_mtu_seg_max = ENIC_NON_TSO_MAX_DESC,
 506         };
 507         device_info->default_rxportconf = (struct rte_eth_dev_portconf) {
 508                 .burst_size = ENIC_DEFAULT_RX_BURST,
 509                 .ring_size = RTE_MIN(device_info->rx_desc_lim.nb_max,
 510                         ENIC_DEFAULT_RX_RING_SIZE),
 511                 .nb_queues = ENIC_DEFAULT_RX_RINGS,
 512         };
 513         device_info->default_txportconf = (struct rte_eth_dev_portconf) {
 514                 .burst_size = ENIC_DEFAULT_TX_BURST,
 515                 .ring_size = RTE_MIN(device_info->tx_desc_lim.nb_max,
 516                         ENIC_DEFAULT_TX_RING_SIZE),
 517                 .nb_queues = ENIC_DEFAULT_TX_RINGS,
 518         };
 519         device_info->speed_capa = speed_capa_from_pci_id(eth_dev);
 520
 521         return 0;
 522 }
 523
 524 static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 525 {
 526         static const uint32_t ptypes[] = {
 527                 RTE_PTYPE_L2_ETHER,
 528                 RTE_PTYPE_L2_ETHER_VLAN,
 529                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 530                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 531                 RTE_PTYPE_L4_TCP,
 532                 RTE_PTYPE_L4_UDP,
 533                 RTE_PTYPE_L4_FRAG,
 534                 RTE_PTYPE_L4_NONFRAG,
 535                 RTE_PTYPE_UNKNOWN
 536         };
 537         static const uint32_t ptypes_overlay[] = {
 538                 RTE_PTYPE_L2_ETHER,
 539                 RTE_PTYPE_L2_ETHER_VLAN,
 540                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 541                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 542                 RTE_PTYPE_L4_TCP,
 543                 RTE_PTYPE_L4_UDP,
 544                 RTE_PTYPE_L4_FRAG,
 545                 RTE_PTYPE_L4_NONFRAG,
 546                 RTE_PTYPE_TUNNEL_GRENAT,
 547                 RTE_PTYPE_INNER_L2_ETHER,
 548                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 549                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 550                 RTE_PTYPE_INNER_L4_TCP,
 551                 RTE_PTYPE_INNER_L4_UDP,
 552                 RTE_PTYPE_INNER_L4_FRAG,
 553                 RTE_PTYPE_INNER_L4_NONFRAG,
 554                 RTE_PTYPE_UNKNOWN
 555         };
 556
 557         if (dev->rx_pkt_burst != enic_dummy_recv_pkts &&
 558             dev->rx_pkt_burst != NULL) {
 559                 struct enic *enic = pmd_priv(dev);
 560                 if (enic->overlay_offload)
 561                         return ptypes_overlay;
 562                 else
 563                         return ptypes;
 564         }
 565         return NULL;
 566 }
 567
 568 static int enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 569 {
 570         struct enic *enic = pmd_priv(eth_dev);
 571         int ret;
 572
 573         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 574                 return -E_RTE_SECONDARY;
 575
 576         ENICPMD_FUNC_TRACE();
 577
 578         enic->promisc = 1;
 579         ret = enic_add_packet_filter(enic);
 580         if (ret != 0)
 581                 enic->promisc = 0;
 582
 583         return ret;
 584 }
 585
 586 static int enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 587 {
 588         struct enic *enic = pmd_priv(eth_dev);
 589         int ret;
 590
 591         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 592                 return -E_RTE_SECONDARY;
 593
 594         ENICPMD_FUNC_TRACE();
 595         enic->promisc = 0;
 596         ret = enic_add_packet_filter(enic);
 597         if (ret != 0)
 598                 enic->promisc = 1;
 599
 600         return ret;
 601 }
 602
 603 static int enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 604 {
 605         struct enic *enic = pmd_priv(eth_dev);
 606         int ret;
 607
 608         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 609                 return -E_RTE_SECONDARY;
 610
 611         ENICPMD_FUNC_TRACE();
 612         enic->allmulti = 1;
 613         ret = enic_add_packet_filter(enic);
 614         if (ret != 0)
 615                 enic->allmulti = 0;
 616
 617         return ret;
 618 }
 619
 620 static int enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 621 {
 622         struct enic *enic = pmd_priv(eth_dev);
 623         int ret;
 624
 625         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 626                 return -E_RTE_SECONDARY;
 627
 628         ENICPMD_FUNC_TRACE();
 629         enic->allmulti = 0;
 630         ret = enic_add_packet_filter(enic);
 631         if (ret != 0)
 632                 enic->allmulti = 1;
 633
 634         return ret;
 635 }
 636
 637 static int enicpmd_add_mac_addr(struct rte_eth_dev *eth_dev,
 638         struct rte_ether_addr *mac_addr,
 639         __rte_unused uint32_t index, __rte_unused uint32_t pool)
 640 {
 641         struct enic *enic = pmd_priv(eth_dev);
 642
 643         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 644                 return -E_RTE_SECONDARY;
 645
 646         ENICPMD_FUNC_TRACE();
 647         return enic_set_mac_address(enic, mac_addr->addr_bytes);
 648 }
 649
 650 static void enicpmd_remove_mac_addr(struct rte_eth_dev *eth_dev, uint32_t index)
 651 {
 652         struct enic *enic = pmd_priv(eth_dev);
 653
 654         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 655                 return;
 656
 657         ENICPMD_FUNC_TRACE();
 658         if (enic_del_mac_address(enic, index))
 659                 dev_err(enic, "del mac addr failed\n");
 660 }
 661
 662 static int enicpmd_set_mac_addr(struct rte_eth_dev *eth_dev,
 663                                 struct rte_ether_addr *addr)
 664 {
 665         struct enic *enic = pmd_priv(eth_dev);
 666         int ret;
 667
 668         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 669                 return -E_RTE_SECONDARY;
 670
 671         ENICPMD_FUNC_TRACE();
 672         ret = enic_del_mac_address(enic, 0);
 673         if (ret)
 674                 return ret;
 675         return enic_set_mac_address(enic, addr->addr_bytes);
 676 }
 677
 678 static void debug_log_add_del_addr(struct rte_ether_addr *addr, bool add)
 679 {
 680         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 681
 682         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr);
 683         ENICPMD_LOG(DEBUG, " %s address %s\n",
 684                      add ? "add" : "remove", mac_str);
 685 }
 686
 687 static int enicpmd_set_mc_addr_list(struct rte_eth_dev *eth_dev,
 688                                     struct rte_ether_addr *mc_addr_set,
 689                                     uint32_t nb_mc_addr)
 690 {
 691         struct enic *enic = pmd_priv(eth_dev);
 692         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 693         struct rte_ether_addr *addr;
 694         uint32_t i, j;
 695         int ret;
 696
 697         ENICPMD_FUNC_TRACE();
 698
 699         /* Validate the given addresses first */
 700         for (i = 0; i < nb_mc_addr && mc_addr_set != NULL; i++) {
 701                 addr = &mc_addr_set[i];
 702                 if (!rte_is_multicast_ether_addr(addr) ||
 703                     rte_is_broadcast_ether_addr(addr)) {
 704                         rte_ether_format_addr(mac_str,
 705                                         RTE_ETHER_ADDR_FMT_SIZE, addr);
 706                         ENICPMD_LOG(ERR, " invalid multicast address %s\n",
 707                                      mac_str);
 708                         return -EINVAL;
 709                 }
 710         }
 711
 712         /* Flush all if requested */
 713         if (nb_mc_addr == 0 || mc_addr_set == NULL) {
 714                 ENICPMD_LOG(DEBUG, " flush multicast addresses\n");
 715                 for (i = 0; i < enic->mc_count; i++) {
 716                         addr = &enic->mc_addrs[i];
 717                         debug_log_add_del_addr(addr, false);
 718                         ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes);
 719                         if (ret)
 720                                 return ret;
 721                 }
 722                 enic->mc_count = 0;
 723                 return 0;
 724         }
 725
 726         if (nb_mc_addr > ENIC_MULTICAST_PERFECT_FILTERS) {
 727                 ENICPMD_LOG(ERR, " too many multicast addresses: max=%d\n",
 728                              ENIC_MULTICAST_PERFECT_FILTERS);
 729                 return -ENOSPC;
 730         }
 731         /*
 732          * devcmd is slow, so apply the difference instead of flushing and
 733          * adding everything.
 734          * 1. Delete addresses on the NIC but not on the host
 735          */
 736         for (i = 0; i < enic->mc_count; i++) {
 737                 addr = &enic->mc_addrs[i];
 738                 for (j = 0; j < nb_mc_addr; j++) {
 739                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j]))
 740                                 break;
 741                 }
 742                 if (j < nb_mc_addr)
 743                         continue;
 744                 debug_log_add_del_addr(addr, false);
 745                 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes);
 746                 if (ret)
 747                         return ret;
 748         }
 749         /* 2. Add addresses on the host but not on the NIC */
 750         for (i = 0; i < nb_mc_addr; i++) {
 751                 addr = &mc_addr_set[i];
 752                 for (j = 0; j < enic->mc_count; j++) {
 753                         if (rte_is_same_ether_addr(addr, &enic->mc_addrs[j]))
 754                                 break;
 755                 }
 756                 if (j < enic->mc_count)
 757                         continue;
 758                 debug_log_add_del_addr(addr, true);
 759                 ret = vnic_dev_add_addr(enic->vdev, addr->addr_bytes);
 760                 if (ret)
 761                         return ret;
 762         }
 763         /* Keep a copy so we can flush/apply later on.. */
 764         memcpy(enic->mc_addrs, mc_addr_set,
 765                nb_mc_addr * sizeof(struct rte_ether_addr));
 766         enic->mc_count = nb_mc_addr;
 767         return 0;
 768 }
 769
 770 static int enicpmd_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 771 {
 772         struct enic *enic = pmd_priv(eth_dev);
 773
 774         ENICPMD_FUNC_TRACE();
 775         return enic_set_mtu(enic, mtu);
 776 }
 777
 778 static int enicpmd_dev_rss_reta_query(struct rte_eth_dev *dev,
 779                                       struct rte_eth_rss_reta_entry64
 780                                       *reta_conf,
 781                                       uint16_t reta_size)
 782 {
 783         struct enic *enic = pmd_priv(dev);
 784         uint16_t i, idx, shift;
 785
 786         ENICPMD_FUNC_TRACE();
 787         if (reta_size != ENIC_RSS_RETA_SIZE) {
 788                 dev_err(enic, "reta_query: wrong reta_size. given=%u expected=%u\n",
 789                         reta_size, ENIC_RSS_RETA_SIZE);
 790                 return -EINVAL;
 791         }
 792
 793         for (i = 0; i < reta_size; i++) {
 794                 idx = i / RTE_RETA_GROUP_SIZE;
 795                 shift = i % RTE_RETA_GROUP_SIZE;
 796                 if (reta_conf[idx].mask & (1ULL << shift))
 797                         reta_conf[idx].reta[shift] = enic_sop_rq_idx_to_rte_idx(
 798                                 enic->rss_cpu.cpu[i / 4].b[i % 4]);
 799         }
 800
 801         return 0;
 802 }
 803
 804 static int enicpmd_dev_rss_reta_update(struct rte_eth_dev *dev,
 805                                        struct rte_eth_rss_reta_entry64
 806                                        *reta_conf,
 807                                        uint16_t reta_size)
 808 {
 809         struct enic *enic = pmd_priv(dev);
 810         union vnic_rss_cpu rss_cpu;
 811         uint16_t i, idx, shift;
 812
 813         ENICPMD_FUNC_TRACE();
 814         if (reta_size != ENIC_RSS_RETA_SIZE) {
 815                 dev_err(enic, "reta_update: wrong reta_size. given=%u"
 816                         " expected=%u\n",
 817                         reta_size, ENIC_RSS_RETA_SIZE);
 818                 return -EINVAL;
 819         }
 820         /*
 821          * Start with the current reta and modify it per reta_conf, as we
 822          * need to push the entire reta even if we only modify one entry.
 823          */
 824         rss_cpu = enic->rss_cpu;
 825         for (i = 0; i < reta_size; i++) {
 826                 idx = i / RTE_RETA_GROUP_SIZE;
 827                 shift = i % RTE_RETA_GROUP_SIZE;
 828                 if (reta_conf[idx].mask & (1ULL << shift))
 829                         rss_cpu.cpu[i / 4].b[i % 4] =
 830                                 enic_rte_rq_idx_to_sop_idx(
 831                                         reta_conf[idx].reta[shift]);
 832         }
 833         return enic_set_rss_reta(enic, &rss_cpu);
 834 }
 835
 836 static int enicpmd_dev_rss_hash_update(struct rte_eth_dev *dev,
 837                                        struct rte_eth_rss_conf *rss_conf)
 838 {
 839         struct enic *enic = pmd_priv(dev);
 840
 841         ENICPMD_FUNC_TRACE();
 842         return enic_set_rss_conf(enic, rss_conf);
 843 }
 844
 845 static int enicpmd_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 846                                          struct rte_eth_rss_conf *rss_conf)
 847 {
 848         struct enic *enic = pmd_priv(dev);
 849
 850         ENICPMD_FUNC_TRACE();
 851         if (rss_conf == NULL)
 852                 return -EINVAL;
 853         if (rss_conf->rss_key != NULL &&
 854             rss_conf->rss_key_len < ENIC_RSS_HASH_KEY_SIZE) {
 855                 dev_err(enic, "rss_hash_conf_get: wrong rss_key_len. given=%u"
 856                         " expected=%u+\n",
 857                         rss_conf->rss_key_len, ENIC_RSS_HASH_KEY_SIZE);
 858                 return -EINVAL;
 859         }
 860         rss_conf->rss_hf = enic->rss_hf;
 861         if (rss_conf->rss_key != NULL) {
 862                 int i;
 863                 for (i = 0; i < ENIC_RSS_HASH_KEY_SIZE; i++) {
 864                         rss_conf->rss_key[i] =
 865                                 enic->rss_key.key[i / 10].b[i % 10];
 866                 }
 867                 rss_conf->rss_key_len = ENIC_RSS_HASH_KEY_SIZE;
 868         }
 869         return 0;
 870 }
 871
 872 static void enicpmd_dev_rxq_info_get(struct rte_eth_dev *dev,
 873                                      uint16_t rx_queue_id,
 874                                      struct rte_eth_rxq_info *qinfo)
 875 {
 876         struct enic *enic = pmd_priv(dev);
 877         struct vnic_rq *rq_sop;
 878         struct vnic_rq *rq_data;
 879         struct rte_eth_rxconf *conf;
 880         uint16_t sop_queue_idx;
 881         uint16_t data_queue_idx;
 882
 883         ENICPMD_FUNC_TRACE();
 884         sop_queue_idx = enic_rte_rq_idx_to_sop_idx(rx_queue_id);
 885         data_queue_idx = enic_rte_rq_idx_to_data_idx(rx_queue_id, enic);
 886         rq_sop = &enic->rq[sop_queue_idx];
 887         rq_data = &enic->rq[data_queue_idx]; /* valid if data_queue_enable */
 888         qinfo->mp = rq_sop->mp;
 889         qinfo->scattered_rx = rq_sop->data_queue_enable;
 890         qinfo->nb_desc = rq_sop->ring.desc_count;
 891         if (qinfo->scattered_rx)
 892                 qinfo->nb_desc += rq_data->ring.desc_count;
 893         conf = &qinfo->conf;
 894         memset(conf, 0, sizeof(*conf));
 895         conf->rx_free_thresh = rq_sop->rx_free_thresh;
 896         conf->rx_drop_en = 1;
 897         /*
 898          * Except VLAN stripping (port setting), all the checksum offloads
 899          * are always enabled.
 900          */
 901         conf->offloads = enic->rx_offload_capa;
 902         if (!enic->ig_vlan_strip_en)
 903                 conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
 904         /* rx_thresh and other fields are not applicable for enic */
 905 }
 906
 907 static void enicpmd_dev_txq_info_get(struct rte_eth_dev *dev,
 908                                      uint16_t tx_queue_id,
 909                                      struct rte_eth_txq_info *qinfo)
 910 {
 911         struct enic *enic = pmd_priv(dev);
 912         struct vnic_wq *wq = &enic->wq[tx_queue_id];
 913
 914         ENICPMD_FUNC_TRACE();
 915         qinfo->nb_desc = wq->ring.desc_count;
 916         memset(&qinfo->conf, 0, sizeof(qinfo->conf));
 917         qinfo->conf.offloads = wq->offloads;
 918         /* tx_thresh, and all the other fields are not applicable for enic */
 919 }
 920
 921 static int enicpmd_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 922                                          __rte_unused uint16_t queue_id,
 923                                          struct rte_eth_burst_mode *mode)
 924 {
 925         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
 926         struct enic *enic = pmd_priv(dev);
 927         const char *info_str = NULL;
 928         int ret = -EINVAL;
 929
 930         ENICPMD_FUNC_TRACE();
 931         if (enic->use_noscatter_vec_rx_handler)
 932                 info_str = "Vector AVX2 No Scatter";
 933         else if (pkt_burst == enic_noscatter_recv_pkts)
 934                 info_str = "Scalar No Scatter";
 935         else if (pkt_burst == enic_recv_pkts)
 936                 info_str = "Scalar";
 937         else if (pkt_burst == enic_recv_pkts_64)
 938                 info_str = "Scalar 64B Completion";
 939         if (info_str) {
 940                 strlcpy(mode->info, info_str, sizeof(mode->info));
 941                 ret = 0;
 942         }
 943         return ret;
 944 }
 945
 946 static int enicpmd_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 947                                          __rte_unused uint16_t queue_id,
 948                                          struct rte_eth_burst_mode *mode)
 949 {
 950         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
 951         const char *info_str = NULL;
 952         int ret = -EINVAL;
 953
 954         ENICPMD_FUNC_TRACE();
 955         if (pkt_burst == enic_simple_xmit_pkts)
 956                 info_str = "Scalar Simplified";
 957         else if (pkt_burst == enic_xmit_pkts)
 958                 info_str = "Scalar";
 959         if (info_str) {
 960                 strlcpy(mode->info, info_str, sizeof(mode->info));
 961                 ret = 0;
 962         }
 963         return ret;
 964 }
 965
 966 static int enicpmd_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
 967                                             uint16_t rx_queue_id)
 968 {
 969         struct enic *enic = pmd_priv(eth_dev);
 970
 971         ENICPMD_FUNC_TRACE();
 972         vnic_intr_unmask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]);
 973         return 0;
 974 }
 975
 976 static int enicpmd_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
 977                                              uint16_t rx_queue_id)
 978 {
 979         struct enic *enic = pmd_priv(eth_dev);
 980
 981         ENICPMD_FUNC_TRACE();
 982         vnic_intr_mask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]);
 983         return 0;
 984 }
 985
 986 static int udp_tunnel_common_check(struct enic *enic,
 987                                    struct rte_eth_udp_tunnel *tnl)
 988 {
 989         if (tnl->prot_type != RTE_TUNNEL_TYPE_VXLAN)
 990                 return -ENOTSUP;
 991         if (!enic->overlay_offload) {
 992                 ENICPMD_LOG(DEBUG, " vxlan (overlay offload) is not "
 993                              "supported\n");
 994                 return -ENOTSUP;
 995         }
 996         return 0;
 997 }
 998
 999 static int update_vxlan_port(struct enic *enic, uint16_t port)
1000 {
1001         if (vnic_dev_overlay_offload_cfg(enic->vdev,
1002                                          OVERLAY_CFG_VXLAN_PORT_UPDATE,
1003                                          port)) {
1004                 ENICPMD_LOG(DEBUG, " failed to update vxlan port\n");
1005                 return -EINVAL;
1006         }
1007         ENICPMD_LOG(DEBUG, " updated vxlan port to %u\n", port);
1008         enic->vxlan_port = port;
1009         return 0;
1010 }
1011
1012 static int enicpmd_dev_udp_tunnel_port_add(struct rte_eth_dev *eth_dev,
1013                                            struct rte_eth_udp_tunnel *tnl)
1014 {
1015         struct enic *enic = pmd_priv(eth_dev);
1016         int ret;
1017
1018         ENICPMD_FUNC_TRACE();
1019         ret = udp_tunnel_common_check(enic, tnl);
1020         if (ret)
1021                 return ret;
1022         /*
1023          * The NIC has 1 configurable VXLAN port number. "Adding" a new port
1024          * number replaces it.
1025          */
1026         if (tnl->udp_port == enic->vxlan_port || tnl->udp_port == 0) {
1027                 ENICPMD_LOG(DEBUG, " %u is already configured or invalid\n",
1028                              tnl->udp_port);
1029                 return -EINVAL;
1030         }
1031         return update_vxlan_port(enic, tnl->udp_port);
1032 }
1033
1034 static int enicpmd_dev_udp_tunnel_port_del(struct rte_eth_dev *eth_dev,
1035                                            struct rte_eth_udp_tunnel *tnl)
1036 {
1037         struct enic *enic = pmd_priv(eth_dev);
1038         int ret;
1039
1040         ENICPMD_FUNC_TRACE();
1041         ret = udp_tunnel_common_check(enic, tnl);
1042         if (ret)
1043                 return ret;
1044         /*
1045          * Clear the previously set port number and restore the
1046          * hardware default port number. Some drivers disable VXLAN
1047          * offloads when there are no configured port numbers. But
1048          * enic does not do that as VXLAN is part of overlay offload,
1049          * which is tied to inner RSS and TSO.
1050          */
1051         if (tnl->udp_port != enic->vxlan_port) {
1052                 ENICPMD_LOG(DEBUG, " %u is not a configured vxlan port\n",
1053                              tnl->udp_port);
1054                 return -EINVAL;
1055         }
1056         return update_vxlan_port(enic, RTE_VXLAN_DEFAULT_PORT);
1057 }
1058
1059 static int enicpmd_dev_fw_version_get(struct rte_eth_dev *eth_dev,
1060                                       char *fw_version, size_t fw_size)
1061 {
1062         struct vnic_devcmd_fw_info *info;
1063         struct enic *enic;
1064         int ret;
1065
1066         ENICPMD_FUNC_TRACE();
1067         if (fw_version == NULL || fw_size <= 0)
1068                 return -EINVAL;
1069         enic = pmd_priv(eth_dev);
1070         ret = vnic_dev_fw_info(enic->vdev, &info);
1071         if (ret)
1072                 return ret;
1073         snprintf(fw_version, fw_size, "%s %s",
1074                  info->fw_version, info->fw_build);
1075         fw_version[fw_size - 1] = '\0';
1076         return 0;
1077 }
1078
1079 static const struct eth_dev_ops enicpmd_eth_dev_ops = {
1080         .dev_configure        = enicpmd_dev_configure,
1081         .dev_start            = enicpmd_dev_start,
1082         .dev_stop             = enicpmd_dev_stop,
1083         .dev_set_link_up      = NULL,
1084         .dev_set_link_down    = NULL,
1085         .dev_close            = enicpmd_dev_close,
1086         .promiscuous_enable   = enicpmd_dev_promiscuous_enable,
1087         .promiscuous_disable  = enicpmd_dev_promiscuous_disable,
1088         .allmulticast_enable  = enicpmd_dev_allmulticast_enable,
1089         .allmulticast_disable = enicpmd_dev_allmulticast_disable,
1090         .link_update          = enicpmd_dev_link_update,
1091         .stats_get            = enicpmd_dev_stats_get,
1092         .stats_reset          = enicpmd_dev_stats_reset,
1093         .queue_stats_mapping_set = NULL,
1094         .dev_infos_get        = enicpmd_dev_info_get,
1095         .dev_supported_ptypes_get = enicpmd_dev_supported_ptypes_get,
1096         .mtu_set              = enicpmd_mtu_set,
1097         .vlan_filter_set      = NULL,
1098         .vlan_tpid_set        = NULL,
1099         .vlan_offload_set     = enicpmd_vlan_offload_set,
1100         .vlan_strip_queue_set = NULL,
1101         .rx_queue_start       = enicpmd_dev_rx_queue_start,
1102         .rx_queue_stop        = enicpmd_dev_rx_queue_stop,
1103         .tx_queue_start       = enicpmd_dev_tx_queue_start,
1104         .tx_queue_stop        = enicpmd_dev_tx_queue_stop,
1105         .rx_queue_setup       = enicpmd_dev_rx_queue_setup,
1106         .rx_queue_release     = enicpmd_dev_rx_queue_release,
1107         .tx_queue_setup       = enicpmd_dev_tx_queue_setup,
1108         .tx_queue_release     = enicpmd_dev_tx_queue_release,
1109         .rx_queue_intr_enable = enicpmd_dev_rx_queue_intr_enable,
1110         .rx_queue_intr_disable = enicpmd_dev_rx_queue_intr_disable,
1111         .rxq_info_get         = enicpmd_dev_rxq_info_get,
1112         .txq_info_get         = enicpmd_dev_txq_info_get,
1113         .rx_burst_mode_get    = enicpmd_dev_rx_burst_mode_get,
1114         .tx_burst_mode_get    = enicpmd_dev_tx_burst_mode_get,
1115         .dev_led_on           = NULL,
1116         .dev_led_off          = NULL,
1117         .flow_ctrl_get        = NULL,
1118         .flow_ctrl_set        = NULL,
1119         .priority_flow_ctrl_set = NULL,
1120         .mac_addr_add         = enicpmd_add_mac_addr,
1121         .mac_addr_remove      = enicpmd_remove_mac_addr,
1122         .mac_addr_set         = enicpmd_set_mac_addr,
1123         .set_mc_addr_list     = enicpmd_set_mc_addr_list,
1124         .filter_ctrl          = enicpmd_dev_filter_ctrl,
1125         .reta_query           = enicpmd_dev_rss_reta_query,
1126         .reta_update          = enicpmd_dev_rss_reta_update,
1127         .rss_hash_conf_get    = enicpmd_dev_rss_hash_conf_get,
1128         .rss_hash_update      = enicpmd_dev_rss_hash_update,
1129         .udp_tunnel_port_add  = enicpmd_dev_udp_tunnel_port_add,
1130         .udp_tunnel_port_del  = enicpmd_dev_udp_tunnel_port_del,
1131         .fw_version_get       = enicpmd_dev_fw_version_get,
1132 };
1133
1134 static int enic_parse_zero_one(const char *key,
1135                                const char *value,
1136                                void *opaque)
1137 {
1138         struct enic *enic;
1139         bool b;
1140
1141         enic = (struct enic *)opaque;
1142         if (strcmp(value, "0") == 0) {
1143                 b = false;
1144         } else if (strcmp(value, "1") == 0) {
1145                 b = true;
1146         } else {
1147                 dev_err(enic, "Invalid value for %s"
1148                         ": expected=0|1 given=%s\n", key, value);
1149                 return -EINVAL;
1150         }
1151         if (strcmp(key, ENIC_DEVARG_CQ64) == 0)
1152                 enic->cq64_request = b;
1153         if (strcmp(key, ENIC_DEVARG_DISABLE_OVERLAY) == 0)
1154                 enic->disable_overlay = b;
1155         if (strcmp(key, ENIC_DEVARG_ENABLE_AVX2_RX) == 0)
1156                 enic->enable_avx2_rx = b;
1157         if (strcmp(key, ENIC_DEVARG_GENEVE_OPT) == 0)
1158                 enic->geneve_opt_request = b;
1159         return 0;
1160 }
1161
1162 static int enic_parse_ig_vlan_rewrite(__rte_unused const char *key,
1163                                       const char *value,
1164                                       void *opaque)
1165 {
1166         struct enic *enic;
1167
1168         enic = (struct enic *)opaque;
1169         if (strcmp(value, "trunk") == 0) {
1170                 /* Trunk mode: always tag */
1171                 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK;
1172         } else if (strcmp(value, "untag") == 0) {
1173                 /* Untag default VLAN mode: untag if VLAN = default VLAN */
1174                 enic->ig_vlan_rewrite_mode =
1175                         IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN;
1176         } else if (strcmp(value, "priority") == 0) {
1177                 /*
1178                  * Priority-tag default VLAN mode: priority tag (VLAN header
1179                  * with ID=0) if VLAN = default
1180                  */
1181                 enic->ig_vlan_rewrite_mode =
1182                         IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN;
1183         } else if (strcmp(value, "pass") == 0) {
1184                 /* Pass through mode: do not touch tags */
1185                 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU;
1186         } else {
1187                 dev_err(enic, "Invalid value for " ENIC_DEVARG_IG_VLAN_REWRITE
1188                         ": expected=trunk|untag|priority|pass given=%s\n",
1189                         value);
1190                 return -EINVAL;
1191         }
1192         return 0;
1193 }
1194
1195 static int enic_check_devargs(struct rte_eth_dev *dev)
1196 {
1197         static const char *const valid_keys[] = {
1198                 ENIC_DEVARG_CQ64,
1199                 ENIC_DEVARG_DISABLE_OVERLAY,
1200                 ENIC_DEVARG_ENABLE_AVX2_RX,
1201                 ENIC_DEVARG_GENEVE_OPT,
1202                 ENIC_DEVARG_IG_VLAN_REWRITE,
1203                 ENIC_DEVARG_REPRESENTOR,
1204                 NULL};
1205         struct enic *enic = pmd_priv(dev);
1206         struct rte_kvargs *kvlist;
1207
1208         ENICPMD_FUNC_TRACE();
1209
1210         enic->cq64_request = true; /* Use 64B entry if available */
1211         enic->disable_overlay = false;
1212         enic->enable_avx2_rx = false;
1213         enic->geneve_opt_request = false;
1214         enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU;
1215         if (!dev->device->devargs)
1216                 return 0;
1217         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1218         if (!kvlist)
1219                 return -EINVAL;
1220         if (rte_kvargs_process(kvlist, ENIC_DEVARG_CQ64,
1221                                enic_parse_zero_one, enic) < 0 ||
1222             rte_kvargs_process(kvlist, ENIC_DEVARG_DISABLE_OVERLAY,
1223                                enic_parse_zero_one, enic) < 0 ||
1224             rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX,
1225                                enic_parse_zero_one, enic) < 0 ||
1226             rte_kvargs_process(kvlist, ENIC_DEVARG_GENEVE_OPT,
1227                                enic_parse_zero_one, enic) < 0 ||
1228             rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE,
1229                                enic_parse_ig_vlan_rewrite, enic) < 0) {
1230                 rte_kvargs_free(kvlist);
1231                 return -EINVAL;
1232         }
1233         rte_kvargs_free(kvlist);
1234         return 0;
1235 }
1236
1237 /* Initialize the driver for PF */
1238 static int eth_enic_dev_init(struct rte_eth_dev *eth_dev,
1239                              void *init_params __rte_unused)
1240 {
1241         struct rte_pci_device *pdev;
1242         struct rte_pci_addr *addr;
1243         struct enic *enic = pmd_priv(eth_dev);
1244         int err;
1245
1246         ENICPMD_FUNC_TRACE();
1247         eth_dev->dev_ops = &enicpmd_eth_dev_ops;
1248         eth_dev->rx_queue_count = enicpmd_dev_rx_queue_count;
1249         eth_dev->rx_pkt_burst = &enic_recv_pkts;
1250         eth_dev->tx_pkt_burst = &enic_xmit_pkts;
1251         eth_dev->tx_pkt_prepare = &enic_prep_pkts;
1252         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1253                 enic_pick_tx_handler(eth_dev);
1254                 enic_pick_rx_handler(eth_dev);
1255                 return 0;
1256         }
1257         /* Only the primary sets up adapter and other data in shared memory */
1258         enic->port_id = eth_dev->data->port_id;
1259         enic->rte_dev = eth_dev;
1260         enic->dev_data = eth_dev->data;
1261
1262         pdev = RTE_ETH_DEV_TO_PCI(eth_dev);
1263         rte_eth_copy_pci_info(eth_dev, pdev);
1264         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1265         enic->pdev = pdev;
1266         addr = &pdev->addr;
1267
1268         snprintf(enic->bdf_name, ENICPMD_BDF_LENGTH, "%04x:%02x:%02x.%x",
1269                 addr->domain, addr->bus, addr->devid, addr->function);
1270
1271         err = enic_check_devargs(eth_dev);
1272         if (err)
1273                 return err;
1274         err = enic_probe(enic);
1275         if (!err && enic->fm) {
1276                 err = enic_fm_allocate_switch_domain(enic);
1277                 if (err)
1278                         ENICPMD_LOG(ERR, "failed to allocate switch domain id");
1279         }
1280         return err;
1281 }
1282
1283 static int eth_enic_dev_uninit(struct rte_eth_dev *eth_dev)
1284 {
1285         struct enic *enic = pmd_priv(eth_dev);
1286         int err;
1287
1288         ENICPMD_FUNC_TRACE();
1289         eth_dev->device = NULL;
1290         eth_dev->intr_handle = NULL;
1291         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1292                 return 0;
1293         err = rte_eth_switch_domain_free(enic->switch_domain_id);
1294         if (err)
1295                 ENICPMD_LOG(WARNING, "failed to free switch domain: %d", err);
1296         return 0;
1297 }
1298
1299 static int eth_enic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1300         struct rte_pci_device *pci_dev)
1301 {
1302         char name[RTE_ETH_NAME_MAX_LEN];
1303         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
1304         struct rte_eth_dev *pf_ethdev;
1305         struct enic *pf_enic;
1306         int i, retval;
1307
1308         ENICPMD_FUNC_TRACE();
1309         if (pci_dev->device.devargs) {
1310                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1311                                 &eth_da);
1312                 if (retval)
1313                         return retval;
1314         }
1315         if (eth_da.nb_representor_ports > 0 &&
1316             eth_da.type != RTE_ETH_REPRESENTOR_VF) {
1317                 ENICPMD_LOG(ERR, "unsupported representor type: %s\n",
1318                             pci_dev->device.devargs->args);
1319                 return -ENOTSUP;
1320         }
1321         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1322                 sizeof(struct enic),
1323                 eth_dev_pci_specific_init, pci_dev,
1324                 eth_enic_dev_init, NULL);
1325         if (retval || eth_da.nb_representor_ports < 1)
1326                 return retval;
1327
1328         /* Probe VF representor */
1329         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1330         if (pf_ethdev == NULL)
1331                 return -ENODEV;
1332         /* Representors require flowman */
1333         pf_enic = pmd_priv(pf_ethdev);
1334         if (pf_enic->fm == NULL) {
1335                 ENICPMD_LOG(ERR, "VF representors require flowman");
1336                 return -ENOTSUP;
1337         }
1338         /*
1339          * For now representors imply switchdev, as firmware does not support
1340          * legacy mode SR-IOV
1341          */
1342         pf_enic->switchdev_mode = 1;
1343         /* Calculate max VF ID before initializing representor*/
1344         pf_enic->max_vf_id = 0;
1345         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1346                 pf_enic->max_vf_id = RTE_MAX(pf_enic->max_vf_id,
1347                                              eth_da.representor_ports[i]);
1348         }
1349         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1350                 struct enic_vf_representor representor;
1351
1352                 representor.vf_id = eth_da.representor_ports[i];
1353                                 representor.switch_domain_id =
1354                         pmd_priv(pf_ethdev)->switch_domain_id;
1355                 representor.pf = pmd_priv(pf_ethdev);
1356                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1357                         pci_dev->device.name, eth_da.representor_ports[i]);
1358                 retval = rte_eth_dev_create(&pci_dev->device, name,
1359                         sizeof(struct enic_vf_representor), NULL, NULL,
1360                         enic_vf_representor_init, &representor);
1361                 if (retval) {
1362                         ENICPMD_LOG(ERR, "failed to create enic vf representor %s",
1363                                     name);
1364                         return retval;
1365                 }
1366         }
1367         return 0;
1368 }
1369
1370 static int eth_enic_pci_remove(struct rte_pci_device *pci_dev)
1371 {
1372         struct rte_eth_dev *ethdev;
1373
1374         ENICPMD_FUNC_TRACE();
1375         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1376         if (!ethdev)
1377                 return -ENODEV;
1378         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1379                 return rte_eth_dev_destroy(ethdev, enic_vf_representor_uninit);
1380         else
1381                 return rte_eth_dev_destroy(ethdev, eth_enic_dev_uninit);
1382 }
1383
1384 static struct rte_pci_driver rte_enic_pmd = {
1385         .id_table = pci_id_enic_map,
1386         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1387         .probe = eth_enic_pci_probe,
1388         .remove = eth_enic_pci_remove,
1389 };
1390
1391 int dev_is_enic(struct rte_eth_dev *dev)
1392 {
1393         return dev->device->driver == &rte_enic_pmd.driver;
1394 }
1395
1396 RTE_PMD_REGISTER_PCI(net_enic, rte_enic_pmd);
1397 RTE_PMD_REGISTER_PCI_TABLE(net_enic, pci_id_enic_map);
1398 RTE_PMD_REGISTER_KMOD_DEP(net_enic, "* igb_uio | uio_pci_generic | vfio-pci");
1399 RTE_PMD_REGISTER_PARAM_STRING(net_enic,
1400         ENIC_DEVARG_CQ64 "=0|1"
1401         ENIC_DEVARG_DISABLE_OVERLAY "=0|1 "
1402         ENIC_DEVARG_ENABLE_AVX2_RX "=0|1 "
1403         ENIC_DEVARG_GENEVE_OPT "=0|1 "
1404         ENIC_DEVARG_IG_VLAN_REWRITE "=trunk|untag|priority|pass");