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39 #include <rte_mempool.h>
40 #include <rte_malloc.h>
41 #include <rte_spinlock.h>
42 #include "fm10k_logs.h"
43 #include "base/fm10k_type.h"
45 /* descriptor ring base addresses must be aligned to the following */
46 #define FM10K_ALIGN_RX_DESC 128
47 #define FM10K_ALIGN_TX_DESC 128
49 /* The maximum packet size that FM10K supports */
50 #define FM10K_MAX_PKT_SIZE (15 * 1024)
52 /* Minimum size of RX buffer FM10K supported */
53 #define FM10K_MIN_RX_BUF_SIZE 256
55 /* The maximum of SRIOV VFs per port supported */
56 #define FM10K_MAX_VF_NUM 64
58 /* number of descriptors must be a multiple of the following */
59 #define FM10K_MULT_RX_DESC FM10K_REQ_RX_DESCRIPTOR_MULTIPLE
60 #define FM10K_MULT_TX_DESC FM10K_REQ_TX_DESCRIPTOR_MULTIPLE
62 /* maximum size of descriptor rings */
63 #define FM10K_MAX_RX_RING_SZ (512 * 1024)
64 #define FM10K_MAX_TX_RING_SZ (512 * 1024)
66 /* minimum and maximum number of descriptors in a ring */
67 #define FM10K_MIN_RX_DESC 32
68 #define FM10K_MIN_TX_DESC 32
69 #define FM10K_MAX_RX_DESC (FM10K_MAX_RX_RING_SZ / sizeof(union fm10k_rx_desc))
70 #define FM10K_MAX_TX_DESC (FM10K_MAX_TX_RING_SZ / sizeof(struct fm10k_tx_desc))
73 * byte aligment for HW RX data buffer
74 * Datasheet requires RX buffer addresses shall either be 512-byte aligned or
75 * be 8-byte aligned but without crossing host memory pages (4KB alignment
76 * boundaries). Satisfy first option.
78 #define FM10K_RX_DATABUF_ALIGN 512
81 * threshold default, min, max, and divisor constraints
82 * the configured values must satisfy the following:
86 #define FM10K_RX_FREE_THRESH_DEFAULT(rxq) 32
87 #define FM10K_RX_FREE_THRESH_MIN(rxq) 1
88 #define FM10K_RX_FREE_THRESH_MAX(rxq) ((rxq)->nb_desc - 1)
89 #define FM10K_RX_FREE_THRESH_DIV(rxq) ((rxq)->nb_desc)
91 #define FM10K_TX_FREE_THRESH_DEFAULT(txq) 32
92 #define FM10K_TX_FREE_THRESH_MIN(txq) 1
93 #define FM10K_TX_FREE_THRESH_MAX(txq) ((txq)->nb_desc - 3)
94 #define FM10K_TX_FREE_THRESH_DIV(txq) 0
96 #define FM10K_DEFAULT_RX_PTHRESH 8
97 #define FM10K_DEFAULT_RX_HTHRESH 8
98 #define FM10K_DEFAULT_RX_WTHRESH 0
100 #define FM10K_DEFAULT_TX_PTHRESH 32
101 #define FM10K_DEFAULT_TX_HTHRESH 0
102 #define FM10K_DEFAULT_TX_WTHRESH 0
104 #define FM10K_TX_RS_THRESH_DEFAULT(txq) 32
105 #define FM10K_TX_RS_THRESH_MIN(txq) 1
106 #define FM10K_TX_RS_THRESH_MAX(txq) \
107 RTE_MIN(((txq)->nb_desc - 2), (txq)->free_thresh)
108 #define FM10K_TX_RS_THRESH_DIV(txq) ((txq)->nb_desc)
110 #define FM10K_VLAN_TAG_SIZE 4
112 /* Maximum number of MAC addresses per PF/VF */
113 #define FM10K_MAX_MACADDR_NUM 64
115 #define FM10K_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
116 #define FM10K_VFTA_SIZE (4096 / FM10K_UINT32_BIT_SIZE)
118 /* vlan_id is a 12 bit number.
119 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
120 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
121 * The higher 7 bit val specifies VFTA array index.
123 #define FM10K_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
124 #define FM10K_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
126 #define RTE_FM10K_RXQ_REARM_THRESH 32
127 #define RTE_FM10K_VPMD_TX_BURST 32
128 #define RTE_FM10K_MAX_RX_BURST RTE_FM10K_RXQ_REARM_THRESH
129 #define RTE_FM10K_TX_MAX_FREE_BUF_SZ 64
130 #define RTE_FM10K_DESCS_PER_LOOP 4
132 struct fm10k_macvlan_filter_info {
133 uint16_t vlan_num; /* Total VLAN number */
134 uint16_t mac_num; /* Total mac number */
135 uint16_t nb_queue_pools; /* Active queue pools number */
136 /* VMDQ ID for each MAC address */
137 uint8_t mac_vmdq_id[FM10K_MAX_MACADDR_NUM];
138 uint32_t vfta[FM10K_VFTA_SIZE]; /* VLAN bitmap */
141 struct fm10k_dev_info {
142 volatile uint32_t enable;
143 volatile uint32_t glort;
144 /* Protect the mailbox to avoid race condition */
145 rte_spinlock_t mbx_lock;
146 struct fm10k_macvlan_filter_info macvlan;
147 /* Flag to indicate if RX vector conditions satisfied */
152 * Structure to store private data for each driver instance.
154 struct fm10k_adapter {
156 struct fm10k_hw_stats stats;
157 struct fm10k_dev_info info;
160 #define FM10K_DEV_PRIVATE_TO_HW(adapter) \
161 (&((struct fm10k_adapter *)adapter)->hw)
163 #define FM10K_DEV_PRIVATE_TO_STATS(adapter) \
164 (&((struct fm10k_adapter *)adapter)->stats)
166 #define FM10K_DEV_PRIVATE_TO_INFO(adapter) \
167 (&((struct fm10k_adapter *)adapter)->info)
169 #define FM10K_DEV_PRIVATE_TO_MBXLOCK(adapter) \
170 (&(((struct fm10k_adapter *)adapter)->info.mbx_lock))
172 #define FM10K_DEV_PRIVATE_TO_MACVLAN(adapter) \
173 (&(((struct fm10k_adapter *)adapter)->info.macvlan))
175 struct fm10k_rx_queue {
176 struct rte_mempool *mp;
177 struct rte_mbuf **sw_ring;
178 volatile union fm10k_rx_desc *hw_ring;
179 struct rte_mbuf *pkt_first_seg; /* First segment of current packet. */
180 struct rte_mbuf *pkt_last_seg; /* Last segment of current packet. */
181 uint64_t hw_ring_phys_addr;
182 uint64_t mbuf_initializer; /* value to init mbufs */
183 /* need to alloc dummy mbuf, for wraparound when scanning hw ring */
184 struct rte_mbuf fake_mbuf;
187 uint16_t next_trigger;
188 uint16_t alloc_thresh;
189 volatile uint32_t *tail_ptr;
191 /* Number of faked desc added at the tail for Vector RX function */
192 uint16_t nb_fake_desc;
194 /* Below 2 fields only valid in case vPMD is applied. */
195 uint16_t rxrearm_nb; /* number of remaining to be re-armed */
196 uint16_t rxrearm_start; /* the idx we start the re-arming from */
197 uint16_t rx_using_sse; /* indicates that vector RX is in use */
200 uint8_t rx_deferred_start; /* don't start this queue in dev start. */
204 * a FIFO is used to track which descriptors have their RS bit set for Tx
205 * queues which are configured to allow multiple descriptors per packet
214 struct fm10k_txq_ops;
216 struct fm10k_tx_queue {
217 struct rte_mbuf **sw_ring;
218 struct fm10k_tx_desc *hw_ring;
219 uint64_t hw_ring_phys_addr;
220 struct fifo rs_tracker;
221 const struct fm10k_txq_ops *ops; /* txq ops */
226 uint16_t free_thresh;
228 /* Below 2 fields only valid in case vPMD is applied. */
229 uint16_t next_rs; /* Next pos to set RS flag */
230 uint16_t next_dd; /* Next pos to check DD flag */
231 volatile uint32_t *tail_ptr;
232 uint32_t txq_flags; /* Holds flags for this TXq */
235 uint8_t tx_deferred_start; /** don't start this queue in dev start. */
239 struct fm10k_txq_ops {
240 void (*release_mbufs)(struct fm10k_tx_queue *txq);
241 void (*reset)(struct fm10k_tx_queue *txq);
244 #define MBUF_DMA_ADDR(mb) \
245 ((uint64_t) ((mb)->buf_physaddr + (mb)->data_off))
247 /* enforce 512B alignment on default Rx DMA addresses */
248 #define MBUF_DMA_ADDR_DEFAULT(mb) \
249 ((uint64_t) RTE_ALIGN(((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM),\
250 FM10K_RX_DATABUF_ALIGN))
252 static inline void fifo_reset(struct fifo *fifo, uint32_t len)
254 fifo->head = fifo->tail = fifo->list;
255 fifo->endp = fifo->list + len;
258 static inline void fifo_insert(struct fifo *fifo, uint16_t val)
261 if (++fifo->head == fifo->endp)
262 fifo->head = fifo->list;
265 /* do not worry about list being empty since we only check it once we know
266 * we have used enough descriptors to set the RS bit at least once */
267 static inline uint16_t fifo_peek(struct fifo *fifo)
272 static inline uint16_t fifo_remove(struct fifo *fifo)
276 if (++fifo->tail == fifo->endp)
277 fifo->tail = fifo->list;
282 fm10k_pktmbuf_reset(struct rte_mbuf *mb, uint8_t in_port)
284 rte_mbuf_refcnt_set(mb, 1);
288 /* enforce 512B alignment on default Rx virtual addresses */
289 mb->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb->buf_addr +
290 RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
291 - (char *)mb->buf_addr);
296 * Verify Rx packet buffer alignment is valid.
298 * Hardware requires specific alignment for Rx packet buffers. At
299 * least one of the following two conditions must be satisfied.
300 * 1. Address is 512B aligned
301 * 2. Address is 8B aligned and buffer does not cross 4K boundary.
303 * Return 1 if buffer alignment satisfies at least one condition,
304 * otherwise return 0.
306 * Note: Alignment is checked by the driver when the Rx queue is reset. It
307 * is assumed that if an entire descriptor ring can be filled with
308 * buffers containing valid alignment, then all buffers in that mempool
309 * have valid address alignment. It is the responsibility of the user
310 * to ensure all buffers have valid alignment, as it is the user who
311 * creates the mempool.
312 * Note: It is assumed the buffer needs only to store a maximum size Ethernet
316 fm10k_addr_alignment_valid(struct rte_mbuf *mb)
318 uint64_t addr = MBUF_DMA_ADDR_DEFAULT(mb);
319 uint64_t boundary1, boundary2;
322 if (RTE_ALIGN(addr, FM10K_RX_DATABUF_ALIGN) == addr)
325 /* 8B aligned, and max Ethernet frame would not cross a 4KB boundary? */
326 if (RTE_ALIGN(addr, 8) == addr) {
327 boundary1 = RTE_ALIGN_FLOOR(addr, 4096);
328 boundary2 = RTE_ALIGN_FLOOR(addr + ETHER_MAX_VLAN_FRAME_LEN,
330 if (boundary1 == boundary2)
334 PMD_INIT_LOG(ERR, "Error: Invalid buffer alignment!");
339 /* Rx and Tx prototypes */
340 uint16_t fm10k_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
343 uint16_t fm10k_recv_scattered_pkts(void *rx_queue,
344 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
346 uint16_t fm10k_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
349 int fm10k_rxq_vec_setup(struct fm10k_rx_queue *rxq);
350 int fm10k_rx_vec_condition_check(struct rte_eth_dev *);
351 void fm10k_rx_queue_release_mbufs_vec(struct fm10k_rx_queue *rxq);
352 uint16_t fm10k_recv_pkts_vec(void *, struct rte_mbuf **, uint16_t);
353 uint16_t fm10k_recv_scattered_pkts_vec(void *, struct rte_mbuf **,
355 uint16_t fm10k_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
357 void fm10k_txq_vec_setup(struct fm10k_tx_queue *txq);