4 * Copyright(c) 2013-2016 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_ethdev.h>
35 #include <rte_malloc.h>
36 #include <rte_memzone.h>
37 #include <rte_string_fns.h>
39 #include <rte_spinlock.h>
40 #include <rte_kvargs.h>
43 #include "base/fm10k_api.h"
45 /* Default delay to acquire mailbox lock */
46 #define FM10K_MBXLOCK_DELAY_US 20
47 #define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL
49 #define MAIN_VSI_POOL_NUMBER 0
51 /* Max try times to acquire switch status */
52 #define MAX_QUERY_SWITCH_STATE_TIMES 10
53 /* Wait interval to get switch status */
54 #define WAIT_SWITCH_MSG_US 100000
55 /* A period of quiescence for switch */
56 #define FM10K_SWITCH_QUIESCE_US 10000
57 /* Number of chars per uint32 type */
58 #define CHARS_PER_UINT32 (sizeof(uint32_t))
59 #define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
61 /* default 1:1 map from queue ID to interrupt vector ID */
62 #define Q2V(pci_dev, queue_id) ((pci_dev)->intr_handle.intr_vec[queue_id])
64 /* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
65 #define MAX_LPORT_NUM 128
66 #define GLORT_FD_Q_BASE 0x40
67 #define GLORT_PF_MASK 0xFFC0
68 #define GLORT_FD_MASK GLORT_PF_MASK
69 #define GLORT_FD_INDEX GLORT_FD_Q_BASE
71 static void fm10k_close_mbx_service(struct fm10k_hw *hw);
72 static void fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev);
73 static void fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev);
74 static void fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev);
75 static void fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev);
76 static inline int fm10k_glort_valid(struct fm10k_hw *hw);
78 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
79 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
80 const u8 *mac, bool add, uint32_t pool);
81 static void fm10k_tx_queue_release(void *queue);
82 static void fm10k_rx_queue_release(void *queue);
83 static void fm10k_set_rx_function(struct rte_eth_dev *dev);
84 static void fm10k_set_tx_function(struct rte_eth_dev *dev);
85 static int fm10k_check_ftag(struct rte_devargs *devargs);
87 struct fm10k_xstats_name_off {
88 char name[RTE_ETH_XSTATS_NAME_SIZE];
92 struct fm10k_xstats_name_off fm10k_hw_stats_strings[] = {
93 {"completion_timeout_count", offsetof(struct fm10k_hw_stats, timeout)},
94 {"unsupported_requests_count", offsetof(struct fm10k_hw_stats, ur)},
95 {"completer_abort_count", offsetof(struct fm10k_hw_stats, ca)},
96 {"unsupported_message_count", offsetof(struct fm10k_hw_stats, um)},
97 {"checksum_error_count", offsetof(struct fm10k_hw_stats, xec)},
98 {"vlan_dropped", offsetof(struct fm10k_hw_stats, vlan_drop)},
99 {"loopback_dropped", offsetof(struct fm10k_hw_stats, loopback_drop)},
100 {"rx_mbuf_allocation_errors", offsetof(struct fm10k_hw_stats,
104 #define FM10K_NB_HW_XSTATS (sizeof(fm10k_hw_stats_strings) / \
105 sizeof(fm10k_hw_stats_strings[0]))
107 struct fm10k_xstats_name_off fm10k_hw_stats_rx_q_strings[] = {
108 {"packets", offsetof(struct fm10k_hw_stats_q, rx_packets)},
109 {"bytes", offsetof(struct fm10k_hw_stats_q, rx_bytes)},
110 {"dropped", offsetof(struct fm10k_hw_stats_q, rx_drops)},
113 #define FM10K_NB_RX_Q_XSTATS (sizeof(fm10k_hw_stats_rx_q_strings) / \
114 sizeof(fm10k_hw_stats_rx_q_strings[0]))
116 struct fm10k_xstats_name_off fm10k_hw_stats_tx_q_strings[] = {
117 {"packets", offsetof(struct fm10k_hw_stats_q, tx_packets)},
118 {"bytes", offsetof(struct fm10k_hw_stats_q, tx_bytes)},
121 #define FM10K_NB_TX_Q_XSTATS (sizeof(fm10k_hw_stats_tx_q_strings) / \
122 sizeof(fm10k_hw_stats_tx_q_strings[0]))
124 #define FM10K_NB_XSTATS (FM10K_NB_HW_XSTATS + FM10K_MAX_QUEUES_PF * \
125 (FM10K_NB_RX_Q_XSTATS + FM10K_NB_TX_Q_XSTATS))
127 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
130 fm10k_mbx_initlock(struct fm10k_hw *hw)
132 rte_spinlock_init(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
136 fm10k_mbx_lock(struct fm10k_hw *hw)
138 while (!rte_spinlock_trylock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back)))
139 rte_delay_us(FM10K_MBXLOCK_DELAY_US);
143 fm10k_mbx_unlock(struct fm10k_hw *hw)
145 rte_spinlock_unlock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
148 /* Stubs needed for linkage when vPMD is disabled */
149 int __attribute__((weak))
150 fm10k_rx_vec_condition_check(__rte_unused struct rte_eth_dev *dev)
155 uint16_t __attribute__((weak))
157 __rte_unused void *rx_queue,
158 __rte_unused struct rte_mbuf **rx_pkts,
159 __rte_unused uint16_t nb_pkts)
164 uint16_t __attribute__((weak))
165 fm10k_recv_scattered_pkts_vec(
166 __rte_unused void *rx_queue,
167 __rte_unused struct rte_mbuf **rx_pkts,
168 __rte_unused uint16_t nb_pkts)
173 int __attribute__((weak))
174 fm10k_rxq_vec_setup(__rte_unused struct fm10k_rx_queue *rxq)
180 void __attribute__((weak))
181 fm10k_rx_queue_release_mbufs_vec(
182 __rte_unused struct fm10k_rx_queue *rxq)
187 void __attribute__((weak))
188 fm10k_txq_vec_setup(__rte_unused struct fm10k_tx_queue *txq)
193 int __attribute__((weak))
194 fm10k_tx_vec_condition_check(__rte_unused struct fm10k_tx_queue *txq)
199 uint16_t __attribute__((weak))
200 fm10k_xmit_pkts_vec(__rte_unused void *tx_queue,
201 __rte_unused struct rte_mbuf **tx_pkts,
202 __rte_unused uint16_t nb_pkts)
208 * reset queue to initial state, allocate software buffers used when starting
210 * return 0 on success
211 * return -ENOMEM if buffers cannot be allocated
212 * return -EINVAL if buffers do not satisfy alignment condition
215 rx_queue_reset(struct fm10k_rx_queue *q)
217 static const union fm10k_rx_desc zero = {{0} };
220 PMD_INIT_FUNC_TRACE();
222 diag = rte_mempool_get_bulk(q->mp, (void **)q->sw_ring, q->nb_desc);
226 for (i = 0; i < q->nb_desc; ++i) {
227 fm10k_pktmbuf_reset(q->sw_ring[i], q->port_id);
228 if (!fm10k_addr_alignment_valid(q->sw_ring[i])) {
229 rte_mempool_put_bulk(q->mp, (void **)q->sw_ring,
233 dma_addr = MBUF_DMA_ADDR_DEFAULT(q->sw_ring[i]);
234 q->hw_ring[i].q.pkt_addr = dma_addr;
235 q->hw_ring[i].q.hdr_addr = dma_addr;
238 /* initialize extra software ring entries. Space for these extra
239 * entries is always allocated.
241 memset(&q->fake_mbuf, 0x0, sizeof(q->fake_mbuf));
242 for (i = 0; i < q->nb_fake_desc; ++i) {
243 q->sw_ring[q->nb_desc + i] = &q->fake_mbuf;
244 q->hw_ring[q->nb_desc + i] = zero;
249 q->next_trigger = q->alloc_thresh - 1;
250 FM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);
251 q->rxrearm_start = 0;
258 * clean queue, descriptor rings, free software buffers used when stopping
262 rx_queue_clean(struct fm10k_rx_queue *q)
264 union fm10k_rx_desc zero = {.q = {0, 0, 0, 0} };
266 PMD_INIT_FUNC_TRACE();
268 /* zero descriptor rings */
269 for (i = 0; i < q->nb_desc; ++i)
270 q->hw_ring[i] = zero;
272 /* zero faked descriptors */
273 for (i = 0; i < q->nb_fake_desc; ++i)
274 q->hw_ring[q->nb_desc + i] = zero;
276 /* vPMD driver has a different way of releasing mbufs. */
277 if (q->rx_using_sse) {
278 fm10k_rx_queue_release_mbufs_vec(q);
282 /* free software buffers */
283 for (i = 0; i < q->nb_desc; ++i) {
285 rte_pktmbuf_free_seg(q->sw_ring[i]);
286 q->sw_ring[i] = NULL;
292 * free all queue memory used when releasing the queue (i.e. configure)
295 rx_queue_free(struct fm10k_rx_queue *q)
297 PMD_INIT_FUNC_TRACE();
299 PMD_INIT_LOG(DEBUG, "Freeing rx queue %p", q);
302 rte_free(q->sw_ring);
311 * disable RX queue, wait unitl HW finished necessary flush operation
314 rx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
318 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
319 FM10K_WRITE_REG(hw, FM10K_RXQCTL(qnum),
320 reg & ~FM10K_RXQCTL_ENABLE);
322 /* Wait 100us at most */
323 for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
325 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
326 if (!(reg & FM10K_RXQCTL_ENABLE))
330 if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
337 * reset queue to initial state, allocate software buffers used when starting
341 tx_queue_reset(struct fm10k_tx_queue *q)
343 PMD_INIT_FUNC_TRACE();
347 q->nb_free = q->nb_desc - 1;
348 fifo_reset(&q->rs_tracker, (q->nb_desc + 1) / q->rs_thresh);
349 FM10K_PCI_REG_WRITE(q->tail_ptr, 0);
353 * clean queue, descriptor rings, free software buffers used when stopping
357 tx_queue_clean(struct fm10k_tx_queue *q)
359 struct fm10k_tx_desc zero = {0, 0, 0, 0, 0, 0};
361 PMD_INIT_FUNC_TRACE();
363 /* zero descriptor rings */
364 for (i = 0; i < q->nb_desc; ++i)
365 q->hw_ring[i] = zero;
367 /* free software buffers */
368 for (i = 0; i < q->nb_desc; ++i) {
370 rte_pktmbuf_free_seg(q->sw_ring[i]);
371 q->sw_ring[i] = NULL;
377 * free all queue memory used when releasing the queue (i.e. configure)
380 tx_queue_free(struct fm10k_tx_queue *q)
382 PMD_INIT_FUNC_TRACE();
384 PMD_INIT_LOG(DEBUG, "Freeing tx queue %p", q);
386 if (q->rs_tracker.list) {
387 rte_free(q->rs_tracker.list);
388 q->rs_tracker.list = NULL;
391 rte_free(q->sw_ring);
400 * disable TX queue, wait unitl HW finished necessary flush operation
403 tx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
407 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
408 FM10K_WRITE_REG(hw, FM10K_TXDCTL(qnum),
409 reg & ~FM10K_TXDCTL_ENABLE);
411 /* Wait 100us at most */
412 for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
414 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
415 if (!(reg & FM10K_TXDCTL_ENABLE))
419 if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
426 fm10k_check_mq_mode(struct rte_eth_dev *dev)
428 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
429 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
430 struct rte_eth_vmdq_rx_conf *vmdq_conf;
431 uint16_t nb_rx_q = dev->data->nb_rx_queues;
433 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
435 if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
436 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
440 if (!(rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG))
443 if (hw->mac.type == fm10k_mac_vf) {
444 PMD_INIT_LOG(ERR, "VMDQ mode is not supported in VF.");
448 /* Check VMDQ queue pool number */
449 if (vmdq_conf->nb_queue_pools >
450 sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT ||
451 vmdq_conf->nb_queue_pools > nb_rx_q) {
452 PMD_INIT_LOG(ERR, "Too many of queue pools: %d",
453 vmdq_conf->nb_queue_pools);
460 static const struct fm10k_txq_ops def_txq_ops = {
461 .reset = tx_queue_reset,
465 fm10k_dev_configure(struct rte_eth_dev *dev)
469 PMD_INIT_FUNC_TRACE();
471 if (dev->data->dev_conf.rxmode.hw_strip_crc == 0)
472 PMD_INIT_LOG(WARNING, "fm10k always strip CRC");
473 /* multipe queue mode checking */
474 ret = fm10k_check_mq_mode(dev);
476 PMD_DRV_LOG(ERR, "fm10k_check_mq_mode fails with %d.",
484 /* fls = find last set bit = 32 minus the number of leading zeros */
486 #define fls(x) (((x) == 0) ? 0 : (32 - __builtin_clz((x))))
490 fm10k_dev_vmdq_rx_configure(struct rte_eth_dev *dev)
492 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
493 struct rte_eth_vmdq_rx_conf *vmdq_conf;
496 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
498 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
499 if (!vmdq_conf->pool_map[i].pools)
502 fm10k_update_vlan(hw, vmdq_conf->pool_map[i].vlan_id, 0, true);
503 fm10k_mbx_unlock(hw);
508 fm10k_dev_pf_main_vsi_reset(struct rte_eth_dev *dev)
510 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
512 /* Add default mac address */
513 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
514 MAIN_VSI_POOL_NUMBER);
518 fm10k_dev_rss_configure(struct rte_eth_dev *dev)
520 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
521 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
522 uint32_t mrqc, *key, i, reta, j;
525 #define RSS_KEY_SIZE 40
526 static uint8_t rss_intel_key[RSS_KEY_SIZE] = {
527 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
528 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
529 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
530 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
531 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
534 if (dev->data->nb_rx_queues == 1 ||
535 dev_conf->rxmode.mq_mode != ETH_MQ_RX_RSS ||
536 dev_conf->rx_adv_conf.rss_conf.rss_hf == 0) {
537 FM10K_WRITE_REG(hw, FM10K_MRQC(0), 0);
541 /* random key is rss_intel_key (default) or user provided (rss_key) */
542 if (dev_conf->rx_adv_conf.rss_conf.rss_key == NULL)
543 key = (uint32_t *)rss_intel_key;
545 key = (uint32_t *)dev_conf->rx_adv_conf.rss_conf.rss_key;
547 /* Now fill our hash function seeds, 4 bytes at a time */
548 for (i = 0; i < RSS_KEY_SIZE / sizeof(*key); ++i)
549 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
552 * Fill in redirection table
553 * The byte-swap is needed because NIC registers are in
554 * little-endian order.
557 for (i = 0, j = 0; i < FM10K_MAX_RSS_INDICES; i++, j++) {
558 if (j == dev->data->nb_rx_queues)
560 reta = (reta << CHAR_BIT) | j;
562 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2),
567 * Generate RSS hash based on packet types, TCP/UDP
568 * port numbers and/or IPv4/v6 src and dst addresses
570 hf = dev_conf->rx_adv_conf.rss_conf.rss_hf;
572 mrqc |= (hf & ETH_RSS_IPV4) ? FM10K_MRQC_IPV4 : 0;
573 mrqc |= (hf & ETH_RSS_IPV6) ? FM10K_MRQC_IPV6 : 0;
574 mrqc |= (hf & ETH_RSS_IPV6_EX) ? FM10K_MRQC_IPV6 : 0;
575 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? FM10K_MRQC_TCP_IPV4 : 0;
576 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? FM10K_MRQC_TCP_IPV6 : 0;
577 mrqc |= (hf & ETH_RSS_IPV6_TCP_EX) ? FM10K_MRQC_TCP_IPV6 : 0;
578 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? FM10K_MRQC_UDP_IPV4 : 0;
579 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? FM10K_MRQC_UDP_IPV6 : 0;
580 mrqc |= (hf & ETH_RSS_IPV6_UDP_EX) ? FM10K_MRQC_UDP_IPV6 : 0;
583 PMD_INIT_LOG(ERR, "Specified RSS mode 0x%"PRIx64"is not"
588 FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
592 fm10k_dev_logic_port_update(struct rte_eth_dev *dev, uint16_t nb_lport_new)
594 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
597 for (i = 0; i < nb_lport_new; i++) {
598 /* Set unicast mode by default. App can change
599 * to other mode in other API func.
602 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map + i,
603 FM10K_XCAST_MODE_NONE);
604 fm10k_mbx_unlock(hw);
609 fm10k_dev_mq_rx_configure(struct rte_eth_dev *dev)
611 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
612 struct rte_eth_vmdq_rx_conf *vmdq_conf;
613 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
614 struct fm10k_macvlan_filter_info *macvlan;
615 uint16_t nb_queue_pools = 0; /* pool number in configuration */
616 uint16_t nb_lport_new;
618 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
619 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
621 fm10k_dev_rss_configure(dev);
623 /* only PF supports VMDQ */
624 if (hw->mac.type != fm10k_mac_pf)
627 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
628 nb_queue_pools = vmdq_conf->nb_queue_pools;
630 /* no pool number change, no need to update logic port and VLAN/MAC */
631 if (macvlan->nb_queue_pools == nb_queue_pools)
634 nb_lport_new = nb_queue_pools ? nb_queue_pools : 1;
635 fm10k_dev_logic_port_update(dev, nb_lport_new);
637 /* reset MAC/VLAN as it's based on VMDQ or PF main VSI */
638 memset(dev->data->mac_addrs, 0,
639 ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM);
640 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
641 &dev->data->mac_addrs[0]);
642 memset(macvlan, 0, sizeof(*macvlan));
643 macvlan->nb_queue_pools = nb_queue_pools;
646 fm10k_dev_vmdq_rx_configure(dev);
648 fm10k_dev_pf_main_vsi_reset(dev);
652 fm10k_dev_tx_init(struct rte_eth_dev *dev)
654 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
656 struct fm10k_tx_queue *txq;
660 /* Disable TXINT to avoid possible interrupt */
661 for (i = 0; i < hw->mac.max_queues; i++)
662 FM10K_WRITE_REG(hw, FM10K_TXINT(i),
663 3 << FM10K_TXINT_TIMER_SHIFT);
666 for (i = 0; i < dev->data->nb_tx_queues; ++i) {
667 txq = dev->data->tx_queues[i];
668 base_addr = txq->hw_ring_phys_addr;
669 size = txq->nb_desc * sizeof(struct fm10k_tx_desc);
671 /* disable queue to avoid issues while updating state */
672 ret = tx_queue_disable(hw, i);
674 PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
677 /* Enable use of FTAG bit in TX descriptor, PFVTCTL
678 * register is read-only for VF.
680 if (fm10k_check_ftag(dev->device->devargs)) {
681 if (hw->mac.type == fm10k_mac_pf) {
682 FM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),
683 FM10K_PFVTCTL_FTAG_DESC_ENABLE);
684 PMD_INIT_LOG(DEBUG, "FTAG mode is enabled");
686 PMD_INIT_LOG(ERR, "VF FTAG is not supported.");
691 /* set location and size for descriptor ring */
692 FM10K_WRITE_REG(hw, FM10K_TDBAL(i),
693 base_addr & UINT64_LOWER_32BITS_MASK);
694 FM10K_WRITE_REG(hw, FM10K_TDBAH(i),
695 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
696 FM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);
698 /* assign default SGLORT for each TX queue by PF */
699 if (hw->mac.type == fm10k_mac_pf)
700 FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);
703 /* set up vector or scalar TX function as appropriate */
704 fm10k_set_tx_function(dev);
710 fm10k_dev_rx_init(struct rte_eth_dev *dev)
712 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
713 struct fm10k_macvlan_filter_info *macvlan;
714 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
715 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
717 struct fm10k_rx_queue *rxq;
720 uint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
721 uint32_t logic_port = hw->mac.dglort_map;
723 uint16_t queue_stride = 0;
725 /* enable RXINT for interrupt mode */
727 if (rte_intr_dp_is_en(intr_handle)) {
728 for (; i < dev->data->nb_rx_queues; i++) {
729 FM10K_WRITE_REG(hw, FM10K_RXINT(i), Q2V(pdev, i));
730 if (hw->mac.type == fm10k_mac_pf)
731 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
733 FM10K_ITR_MASK_CLEAR);
735 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
737 FM10K_ITR_MASK_CLEAR);
740 /* Disable other RXINT to avoid possible interrupt */
741 for (; i < hw->mac.max_queues; i++)
742 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
743 3 << FM10K_RXINT_TIMER_SHIFT);
745 /* Setup RX queues */
746 for (i = 0; i < dev->data->nb_rx_queues; ++i) {
747 rxq = dev->data->rx_queues[i];
748 base_addr = rxq->hw_ring_phys_addr;
749 size = rxq->nb_desc * sizeof(union fm10k_rx_desc);
751 /* disable queue to avoid issues while updating state */
752 ret = rx_queue_disable(hw, i);
754 PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
758 /* Setup the Base and Length of the Rx Descriptor Ring */
759 FM10K_WRITE_REG(hw, FM10K_RDBAL(i),
760 base_addr & UINT64_LOWER_32BITS_MASK);
761 FM10K_WRITE_REG(hw, FM10K_RDBAH(i),
762 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
763 FM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);
765 /* Configure the Rx buffer size for one buff without split */
766 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
767 RTE_PKTMBUF_HEADROOM);
768 /* As RX buffer is aligned to 512B within mbuf, some bytes are
769 * reserved for this purpose, and the worst case could be 511B.
770 * But SRR reg assumes all buffers have the same size. In order
771 * to fill the gap, we'll have to consider the worst case and
772 * assume 512B is reserved. If we don't do so, it's possible
773 * for HW to overwrite data to next mbuf.
775 buf_size -= FM10K_RX_DATABUF_ALIGN;
777 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i),
778 (buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |
779 FM10K_SRRCTL_LOOPBACK_SUPPRESS);
781 /* It adds dual VLAN length for supporting dual VLAN */
782 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
783 2 * FM10K_VLAN_TAG_SIZE) > buf_size ||
784 dev->data->dev_conf.rxmode.enable_scatter) {
786 dev->data->scattered_rx = 1;
787 reg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));
788 reg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;
789 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);
792 /* Enable drop on empty, it's RO for VF */
793 if (hw->mac.type == fm10k_mac_pf && rxq->drop_en)
794 rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
796 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i), rxdctl);
797 FM10K_WRITE_FLUSH(hw);
800 /* Configure VMDQ/RSS if applicable */
801 fm10k_dev_mq_rx_configure(dev);
803 /* Decide the best RX function */
804 fm10k_set_rx_function(dev);
806 /* update RX_SGLORT for loopback suppress*/
807 if (hw->mac.type != fm10k_mac_pf)
809 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
810 if (macvlan->nb_queue_pools)
811 queue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;
812 for (i = 0; i < dev->data->nb_rx_queues; ++i) {
813 if (i && queue_stride && !(i % queue_stride))
815 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);
822 fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
824 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
827 struct fm10k_rx_queue *rxq;
829 PMD_INIT_FUNC_TRACE();
831 if (rx_queue_id < dev->data->nb_rx_queues) {
832 rxq = dev->data->rx_queues[rx_queue_id];
833 err = rx_queue_reset(rxq);
834 if (err == -ENOMEM) {
835 PMD_INIT_LOG(ERR, "Failed to alloc memory : %d", err);
837 } else if (err == -EINVAL) {
838 PMD_INIT_LOG(ERR, "Invalid buffer address alignment :"
843 /* Setup the HW Rx Head and Tail Descriptor Pointers
844 * Note: this must be done AFTER the queue is enabled on real
845 * hardware, but BEFORE the queue is enabled when using the
846 * emulation platform. Do it in both places for now and remove
847 * this comment and the following two register writes when the
848 * emulation platform is no longer being used.
850 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
851 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
853 /* Set PF ownership flag for PF devices */
854 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));
855 if (hw->mac.type == fm10k_mac_pf)
856 reg |= FM10K_RXQCTL_PF;
857 reg |= FM10K_RXQCTL_ENABLE;
858 /* enable RX queue */
859 FM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);
860 FM10K_WRITE_FLUSH(hw);
862 /* Setup the HW Rx Head and Tail Descriptor Pointers
863 * Note: this must be done AFTER the queue is enabled
865 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
866 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
867 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
874 fm10k_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
876 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
878 PMD_INIT_FUNC_TRACE();
880 if (rx_queue_id < dev->data->nb_rx_queues) {
881 /* Disable RX queue */
882 rx_queue_disable(hw, rx_queue_id);
884 /* Free mbuf and clean HW ring */
885 rx_queue_clean(dev->data->rx_queues[rx_queue_id]);
886 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
893 fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
895 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
896 /** @todo - this should be defined in the shared code */
897 #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY 0x00010000
898 uint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;
901 PMD_INIT_FUNC_TRACE();
903 if (tx_queue_id < dev->data->nb_tx_queues) {
904 struct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];
908 /* reset head and tail pointers */
909 FM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);
910 FM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);
912 /* enable TX queue */
913 FM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),
914 FM10K_TXDCTL_ENABLE | txdctl);
915 FM10K_WRITE_FLUSH(hw);
916 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
924 fm10k_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
926 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
928 PMD_INIT_FUNC_TRACE();
930 if (tx_queue_id < dev->data->nb_tx_queues) {
931 tx_queue_disable(hw, tx_queue_id);
932 tx_queue_clean(dev->data->tx_queues[tx_queue_id]);
933 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
939 static inline int fm10k_glort_valid(struct fm10k_hw *hw)
941 return ((hw->mac.dglort_map & FM10K_DGLORTMAP_NONE)
942 != FM10K_DGLORTMAP_NONE);
946 fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev)
948 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
951 PMD_INIT_FUNC_TRACE();
953 /* Return if it didn't acquire valid glort range */
954 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
958 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
959 FM10K_XCAST_MODE_PROMISC);
960 fm10k_mbx_unlock(hw);
962 if (status != FM10K_SUCCESS)
963 PMD_INIT_LOG(ERR, "Failed to enable promiscuous mode");
967 fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev)
969 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
973 PMD_INIT_FUNC_TRACE();
975 /* Return if it didn't acquire valid glort range */
976 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
979 if (dev->data->all_multicast == 1)
980 mode = FM10K_XCAST_MODE_ALLMULTI;
982 mode = FM10K_XCAST_MODE_NONE;
985 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
987 fm10k_mbx_unlock(hw);
989 if (status != FM10K_SUCCESS)
990 PMD_INIT_LOG(ERR, "Failed to disable promiscuous mode");
994 fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev)
996 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
999 PMD_INIT_FUNC_TRACE();
1001 /* Return if it didn't acquire valid glort range */
1002 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1005 /* If promiscuous mode is enabled, it doesn't make sense to enable
1006 * allmulticast and disable promiscuous since fm10k only can select
1009 if (dev->data->promiscuous) {
1010 PMD_INIT_LOG(INFO, "Promiscuous mode is enabled, "\
1011 "needn't enable allmulticast");
1016 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1017 FM10K_XCAST_MODE_ALLMULTI);
1018 fm10k_mbx_unlock(hw);
1020 if (status != FM10K_SUCCESS)
1021 PMD_INIT_LOG(ERR, "Failed to enable allmulticast mode");
1025 fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev)
1027 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1030 PMD_INIT_FUNC_TRACE();
1032 /* Return if it didn't acquire valid glort range */
1033 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1036 if (dev->data->promiscuous) {
1037 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode "\
1038 "since promisc mode is enabled");
1043 /* Change mode to unicast mode */
1044 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1045 FM10K_XCAST_MODE_NONE);
1046 fm10k_mbx_unlock(hw);
1048 if (status != FM10K_SUCCESS)
1049 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode");
1053 fm10k_dev_dglort_map_configure(struct rte_eth_dev *dev)
1055 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1056 uint32_t dglortdec, pool_len, rss_len, i, dglortmask;
1057 uint16_t nb_queue_pools;
1058 struct fm10k_macvlan_filter_info *macvlan;
1060 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1061 nb_queue_pools = macvlan->nb_queue_pools;
1062 pool_len = nb_queue_pools ? fls(nb_queue_pools - 1) : 0;
1063 rss_len = fls(dev->data->nb_rx_queues - 1) - pool_len;
1065 /* GLORT 0x0-0x3F are used by PF and VMDQ, 0x40-0x7F used by FD */
1066 dglortdec = (rss_len << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | pool_len;
1067 dglortmask = (GLORT_PF_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1069 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(0), dglortmask);
1070 /* Configure VMDQ/RSS DGlort Decoder */
1071 FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(0), dglortdec);
1073 /* Flow Director configurations, only queue number is valid. */
1074 dglortdec = fls(dev->data->nb_rx_queues - 1);
1075 dglortmask = (GLORT_FD_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1076 (hw->mac.dglort_map + GLORT_FD_Q_BASE);
1077 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(1), dglortmask);
1078 FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(1), dglortdec);
1080 /* Invalidate all other GLORT entries */
1081 for (i = 2; i < FM10K_DGLORT_COUNT; i++)
1082 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i),
1083 FM10K_DGLORTMAP_NONE);
1086 #define BSIZEPKT_ROUNDUP ((1 << FM10K_SRRCTL_BSIZEPKT_SHIFT) - 1)
1088 fm10k_dev_start(struct rte_eth_dev *dev)
1090 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1093 PMD_INIT_FUNC_TRACE();
1095 /* stop, init, then start the hw */
1096 diag = fm10k_stop_hw(hw);
1097 if (diag != FM10K_SUCCESS) {
1098 PMD_INIT_LOG(ERR, "Hardware stop failed: %d", diag);
1102 diag = fm10k_init_hw(hw);
1103 if (diag != FM10K_SUCCESS) {
1104 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
1108 diag = fm10k_start_hw(hw);
1109 if (diag != FM10K_SUCCESS) {
1110 PMD_INIT_LOG(ERR, "Hardware start failed: %d", diag);
1114 diag = fm10k_dev_tx_init(dev);
1116 PMD_INIT_LOG(ERR, "TX init failed: %d", diag);
1120 if (fm10k_dev_rxq_interrupt_setup(dev))
1123 diag = fm10k_dev_rx_init(dev);
1125 PMD_INIT_LOG(ERR, "RX init failed: %d", diag);
1129 if (hw->mac.type == fm10k_mac_pf)
1130 fm10k_dev_dglort_map_configure(dev);
1132 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1133 struct fm10k_rx_queue *rxq;
1134 rxq = dev->data->rx_queues[i];
1136 if (rxq->rx_deferred_start)
1138 diag = fm10k_dev_rx_queue_start(dev, i);
1141 for (j = 0; j < i; ++j)
1142 rx_queue_clean(dev->data->rx_queues[j]);
1147 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1148 struct fm10k_tx_queue *txq;
1149 txq = dev->data->tx_queues[i];
1151 if (txq->tx_deferred_start)
1153 diag = fm10k_dev_tx_queue_start(dev, i);
1156 for (j = 0; j < i; ++j)
1157 tx_queue_clean(dev->data->tx_queues[j]);
1158 for (j = 0; j < dev->data->nb_rx_queues; ++j)
1159 rx_queue_clean(dev->data->rx_queues[j]);
1164 /* Update default vlan when not in VMDQ mode */
1165 if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
1166 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
1172 fm10k_dev_stop(struct rte_eth_dev *dev)
1174 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1175 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
1176 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
1179 PMD_INIT_FUNC_TRACE();
1181 if (dev->data->tx_queues)
1182 for (i = 0; i < dev->data->nb_tx_queues; i++)
1183 fm10k_dev_tx_queue_stop(dev, i);
1185 if (dev->data->rx_queues)
1186 for (i = 0; i < dev->data->nb_rx_queues; i++)
1187 fm10k_dev_rx_queue_stop(dev, i);
1189 /* Disable datapath event */
1190 if (rte_intr_dp_is_en(intr_handle)) {
1191 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1192 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
1193 3 << FM10K_RXINT_TIMER_SHIFT);
1194 if (hw->mac.type == fm10k_mac_pf)
1195 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
1196 FM10K_ITR_MASK_SET);
1198 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
1199 FM10K_ITR_MASK_SET);
1202 /* Clean datapath event and queue/vec mapping */
1203 rte_intr_efd_disable(intr_handle);
1204 rte_free(intr_handle->intr_vec);
1205 intr_handle->intr_vec = NULL;
1209 fm10k_dev_queue_release(struct rte_eth_dev *dev)
1213 PMD_INIT_FUNC_TRACE();
1215 if (dev->data->tx_queues) {
1216 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1217 struct fm10k_tx_queue *txq = dev->data->tx_queues[i];
1223 if (dev->data->rx_queues) {
1224 for (i = 0; i < dev->data->nb_rx_queues; i++)
1225 fm10k_rx_queue_release(dev->data->rx_queues[i]);
1230 fm10k_dev_close(struct rte_eth_dev *dev)
1232 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1234 PMD_INIT_FUNC_TRACE();
1237 hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
1238 MAX_LPORT_NUM, false);
1239 fm10k_mbx_unlock(hw);
1241 /* allow 10ms for device to quiesce */
1242 rte_delay_us(FM10K_SWITCH_QUIESCE_US);
1244 /* Stop mailbox service first */
1245 fm10k_close_mbx_service(hw);
1246 fm10k_dev_stop(dev);
1247 fm10k_dev_queue_release(dev);
1252 fm10k_link_update(struct rte_eth_dev *dev,
1253 __rte_unused int wait_to_complete)
1255 PMD_INIT_FUNC_TRACE();
1257 /* The host-interface link is always up. The speed is ~50Gbps per Gen3
1258 * x8 PCIe interface. For now, we leave the speed undefined since there
1259 * is no 50Gbps Ethernet. */
1260 dev->data->dev_link.link_speed = 0;
1261 dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
1262 dev->data->dev_link.link_status = ETH_LINK_UP;
1267 static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1268 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
1273 if (xstats_names != NULL) {
1274 /* Note: limit checked in rte_eth_xstats_names() */
1277 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1278 snprintf(xstats_names[count].name,
1279 sizeof(xstats_names[count].name),
1280 "%s", fm10k_hw_stats_strings[count].name);
1284 /* PF queue stats */
1285 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1286 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1287 snprintf(xstats_names[count].name,
1288 sizeof(xstats_names[count].name),
1290 fm10k_hw_stats_rx_q_strings[i].name);
1293 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1294 snprintf(xstats_names[count].name,
1295 sizeof(xstats_names[count].name),
1297 fm10k_hw_stats_tx_q_strings[i].name);
1302 return FM10K_NB_XSTATS;
1306 fm10k_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1309 struct fm10k_hw_stats *hw_stats =
1310 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1311 unsigned i, q, count = 0;
1313 if (n < FM10K_NB_XSTATS)
1314 return FM10K_NB_XSTATS;
1317 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1318 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1319 fm10k_hw_stats_strings[count].offset);
1323 /* PF queue stats */
1324 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1325 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1326 xstats[count].value =
1327 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1328 fm10k_hw_stats_rx_q_strings[i].offset);
1331 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1332 xstats[count].value =
1333 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1334 fm10k_hw_stats_tx_q_strings[i].offset);
1339 return FM10K_NB_XSTATS;
1343 fm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1345 uint64_t ipackets, opackets, ibytes, obytes;
1346 struct fm10k_hw *hw =
1347 FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348 struct fm10k_hw_stats *hw_stats =
1349 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1352 PMD_INIT_FUNC_TRACE();
1354 fm10k_update_hw_stats(hw, hw_stats);
1356 ipackets = opackets = ibytes = obytes = 0;
1357 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1358 (i < hw->mac.max_queues); ++i) {
1359 stats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;
1360 stats->q_opackets[i] = hw_stats->q[i].tx_packets.count;
1361 stats->q_ibytes[i] = hw_stats->q[i].rx_bytes.count;
1362 stats->q_obytes[i] = hw_stats->q[i].tx_bytes.count;
1363 ipackets += stats->q_ipackets[i];
1364 opackets += stats->q_opackets[i];
1365 ibytes += stats->q_ibytes[i];
1366 obytes += stats->q_obytes[i];
1368 stats->ipackets = ipackets;
1369 stats->opackets = opackets;
1370 stats->ibytes = ibytes;
1371 stats->obytes = obytes;
1375 fm10k_stats_reset(struct rte_eth_dev *dev)
1377 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1378 struct fm10k_hw_stats *hw_stats =
1379 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1381 PMD_INIT_FUNC_TRACE();
1383 memset(hw_stats, 0, sizeof(*hw_stats));
1384 fm10k_rebind_hw_stats(hw, hw_stats);
1388 fm10k_dev_infos_get(struct rte_eth_dev *dev,
1389 struct rte_eth_dev_info *dev_info)
1391 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1392 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
1394 PMD_INIT_FUNC_TRACE();
1396 dev_info->pci_dev = pdev;
1397 dev_info->min_rx_bufsize = FM10K_MIN_RX_BUF_SIZE;
1398 dev_info->max_rx_pktlen = FM10K_MAX_PKT_SIZE;
1399 dev_info->max_rx_queues = hw->mac.max_queues;
1400 dev_info->max_tx_queues = hw->mac.max_queues;
1401 dev_info->max_mac_addrs = FM10K_MAX_MACADDR_NUM;
1402 dev_info->max_hash_mac_addrs = 0;
1403 dev_info->max_vfs = pdev->max_vfs;
1404 dev_info->vmdq_pool_base = 0;
1405 dev_info->vmdq_queue_base = 0;
1406 dev_info->max_vmdq_pools = ETH_32_POOLS;
1407 dev_info->vmdq_queue_num = FM10K_MAX_QUEUES_PF;
1408 dev_info->rx_offload_capa =
1409 DEV_RX_OFFLOAD_VLAN_STRIP |
1410 DEV_RX_OFFLOAD_IPV4_CKSUM |
1411 DEV_RX_OFFLOAD_UDP_CKSUM |
1412 DEV_RX_OFFLOAD_TCP_CKSUM;
1413 dev_info->tx_offload_capa =
1414 DEV_TX_OFFLOAD_VLAN_INSERT |
1415 DEV_TX_OFFLOAD_IPV4_CKSUM |
1416 DEV_TX_OFFLOAD_UDP_CKSUM |
1417 DEV_TX_OFFLOAD_TCP_CKSUM |
1418 DEV_TX_OFFLOAD_TCP_TSO;
1420 dev_info->hash_key_size = FM10K_RSSRK_SIZE * sizeof(uint32_t);
1421 dev_info->reta_size = FM10K_MAX_RSS_INDICES;
1423 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1425 .pthresh = FM10K_DEFAULT_RX_PTHRESH,
1426 .hthresh = FM10K_DEFAULT_RX_HTHRESH,
1427 .wthresh = FM10K_DEFAULT_RX_WTHRESH,
1429 .rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(0),
1433 dev_info->default_txconf = (struct rte_eth_txconf) {
1435 .pthresh = FM10K_DEFAULT_TX_PTHRESH,
1436 .hthresh = FM10K_DEFAULT_TX_HTHRESH,
1437 .wthresh = FM10K_DEFAULT_TX_WTHRESH,
1439 .tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(0),
1440 .tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(0),
1441 .txq_flags = FM10K_SIMPLE_TX_FLAG,
1444 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1445 .nb_max = FM10K_MAX_RX_DESC,
1446 .nb_min = FM10K_MIN_RX_DESC,
1447 .nb_align = FM10K_MULT_RX_DESC,
1450 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1451 .nb_max = FM10K_MAX_TX_DESC,
1452 .nb_min = FM10K_MIN_TX_DESC,
1453 .nb_align = FM10K_MULT_TX_DESC,
1456 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
1457 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
1458 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1461 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
1462 static const uint32_t *
1463 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1465 if (dev->rx_pkt_burst == fm10k_recv_pkts ||
1466 dev->rx_pkt_burst == fm10k_recv_scattered_pkts) {
1467 static uint32_t ptypes[] = {
1468 /* refers to rx_desc_to_ol_flags() */
1471 RTE_PTYPE_L3_IPV4_EXT,
1473 RTE_PTYPE_L3_IPV6_EXT,
1480 } else if (dev->rx_pkt_burst == fm10k_recv_pkts_vec ||
1481 dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec) {
1482 static uint32_t ptypes_vec[] = {
1483 /* refers to fm10k_desc_to_pktype_v() */
1485 RTE_PTYPE_L3_IPV4_EXT,
1487 RTE_PTYPE_L3_IPV6_EXT,
1490 RTE_PTYPE_TUNNEL_GENEVE,
1491 RTE_PTYPE_TUNNEL_NVGRE,
1492 RTE_PTYPE_TUNNEL_VXLAN,
1493 RTE_PTYPE_TUNNEL_GRE,
1503 static const uint32_t *
1504 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1511 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1514 uint16_t mac_num = 0;
1515 uint32_t vid_idx, vid_bit, mac_index;
1516 struct fm10k_hw *hw;
1517 struct fm10k_macvlan_filter_info *macvlan;
1518 struct rte_eth_dev_data *data = dev->data;
1520 hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1521 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1523 if (macvlan->nb_queue_pools > 0) { /* VMDQ mode */
1524 PMD_INIT_LOG(ERR, "Cannot change VLAN filter in VMDQ mode");
1528 if (vlan_id > ETH_VLAN_ID_MAX) {
1529 PMD_INIT_LOG(ERR, "Invalid vlan_id: must be < 4096");
1533 vid_idx = FM10K_VFTA_IDX(vlan_id);
1534 vid_bit = FM10K_VFTA_BIT(vlan_id);
1535 /* this VLAN ID is already in the VLAN filter table, return SUCCESS */
1536 if (on && (macvlan->vfta[vid_idx] & vid_bit))
1538 /* this VLAN ID is NOT in the VLAN filter table, cannot remove */
1539 if (!on && !(macvlan->vfta[vid_idx] & vid_bit)) {
1540 PMD_INIT_LOG(ERR, "Invalid vlan_id: not existing "
1541 "in the VLAN filter table");
1546 result = fm10k_update_vlan(hw, vlan_id, 0, on);
1547 fm10k_mbx_unlock(hw);
1548 if (result != FM10K_SUCCESS) {
1549 PMD_INIT_LOG(ERR, "VLAN update failed: %d", result);
1553 for (mac_index = 0; (mac_index < FM10K_MAX_MACADDR_NUM) &&
1554 (result == FM10K_SUCCESS); mac_index++) {
1555 if (is_zero_ether_addr(&data->mac_addrs[mac_index]))
1557 if (mac_num > macvlan->mac_num - 1) {
1558 PMD_INIT_LOG(ERR, "MAC address number "
1563 result = fm10k_update_uc_addr(hw, hw->mac.dglort_map,
1564 data->mac_addrs[mac_index].addr_bytes,
1566 fm10k_mbx_unlock(hw);
1569 if (result != FM10K_SUCCESS) {
1570 PMD_INIT_LOG(ERR, "MAC address update failed: %d", result);
1575 macvlan->vlan_num++;
1576 macvlan->vfta[vid_idx] |= vid_bit;
1578 macvlan->vlan_num--;
1579 macvlan->vfta[vid_idx] &= ~vid_bit;
1585 fm10k_vlan_offload_set(__rte_unused struct rte_eth_dev *dev, int mask)
1587 if (mask & ETH_VLAN_STRIP_MASK) {
1588 if (!dev->data->dev_conf.rxmode.hw_vlan_strip)
1589 PMD_INIT_LOG(ERR, "VLAN stripping is "
1590 "always on in fm10k");
1593 if (mask & ETH_VLAN_EXTEND_MASK) {
1594 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1595 PMD_INIT_LOG(ERR, "VLAN QinQ is not "
1596 "supported in fm10k");
1599 if (mask & ETH_VLAN_FILTER_MASK) {
1600 if (!dev->data->dev_conf.rxmode.hw_vlan_filter)
1601 PMD_INIT_LOG(ERR, "VLAN filter is always on in fm10k");
1605 /* Add/Remove a MAC address, and update filters to main VSI */
1606 static void fm10k_MAC_filter_set_main_vsi(struct rte_eth_dev *dev,
1607 const u8 *mac, bool add, uint32_t pool)
1609 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1610 struct fm10k_macvlan_filter_info *macvlan;
1613 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1615 if (pool != MAIN_VSI_POOL_NUMBER) {
1616 PMD_DRV_LOG(ERR, "VMDQ not enabled, can't set "
1617 "mac to pool %u", pool);
1620 for (i = 0, j = 0; j < FM10K_VFTA_SIZE; j++) {
1621 if (!macvlan->vfta[j])
1623 for (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {
1624 if (!(macvlan->vfta[j] & (1 << k)))
1626 if (i + 1 > macvlan->vlan_num) {
1627 PMD_INIT_LOG(ERR, "vlan number not match");
1631 fm10k_update_uc_addr(hw, hw->mac.dglort_map, mac,
1632 j * FM10K_UINT32_BIT_SIZE + k, add, 0);
1633 fm10k_mbx_unlock(hw);
1639 /* Add/Remove a MAC address, and update filters to VMDQ */
1640 static void fm10k_MAC_filter_set_vmdq(struct rte_eth_dev *dev,
1641 const u8 *mac, bool add, uint32_t pool)
1643 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1644 struct fm10k_macvlan_filter_info *macvlan;
1645 struct rte_eth_vmdq_rx_conf *vmdq_conf;
1648 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1649 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1651 if (pool > macvlan->nb_queue_pools) {
1652 PMD_DRV_LOG(ERR, "Pool number %u invalid."
1654 pool, macvlan->nb_queue_pools);
1657 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
1658 if (!(vmdq_conf->pool_map[i].pools & (1UL << pool)))
1661 fm10k_update_uc_addr(hw, hw->mac.dglort_map + pool, mac,
1662 vmdq_conf->pool_map[i].vlan_id, add, 0);
1663 fm10k_mbx_unlock(hw);
1667 /* Add/Remove a MAC address, and update filters */
1668 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
1669 const u8 *mac, bool add, uint32_t pool)
1671 struct fm10k_macvlan_filter_info *macvlan;
1673 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1675 if (macvlan->nb_queue_pools > 0) /* VMDQ mode */
1676 fm10k_MAC_filter_set_vmdq(dev, mac, add, pool);
1678 fm10k_MAC_filter_set_main_vsi(dev, mac, add, pool);
1686 /* Add a MAC address, and update filters */
1688 fm10k_macaddr_add(struct rte_eth_dev *dev,
1689 struct ether_addr *mac_addr,
1693 struct fm10k_macvlan_filter_info *macvlan;
1695 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1696 fm10k_MAC_filter_set(dev, mac_addr->addr_bytes, TRUE, pool);
1697 macvlan->mac_vmdq_id[index] = pool;
1700 /* Remove a MAC address, and update filters */
1702 fm10k_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1704 struct rte_eth_dev_data *data = dev->data;
1705 struct fm10k_macvlan_filter_info *macvlan;
1707 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1708 fm10k_MAC_filter_set(dev, data->mac_addrs[index].addr_bytes,
1709 FALSE, macvlan->mac_vmdq_id[index]);
1710 macvlan->mac_vmdq_id[index] = 0;
1714 check_nb_desc(uint16_t min, uint16_t max, uint16_t mult, uint16_t request)
1716 if ((request < min) || (request > max) || ((request % mult) != 0))
1724 check_thresh(uint16_t min, uint16_t max, uint16_t div, uint16_t request)
1726 if ((request < min) || (request > max) || ((div % request) != 0))
1733 handle_rxconf(struct fm10k_rx_queue *q, const struct rte_eth_rxconf *conf)
1735 uint16_t rx_free_thresh;
1737 if (conf->rx_free_thresh == 0)
1738 rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(q);
1740 rx_free_thresh = conf->rx_free_thresh;
1742 /* make sure the requested threshold satisfies the constraints */
1743 if (check_thresh(FM10K_RX_FREE_THRESH_MIN(q),
1744 FM10K_RX_FREE_THRESH_MAX(q),
1745 FM10K_RX_FREE_THRESH_DIV(q),
1747 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be "
1748 "less than or equal to %u, "
1749 "greater than or equal to %u, "
1750 "and a divisor of %u",
1751 rx_free_thresh, FM10K_RX_FREE_THRESH_MAX(q),
1752 FM10K_RX_FREE_THRESH_MIN(q),
1753 FM10K_RX_FREE_THRESH_DIV(q));
1757 q->alloc_thresh = rx_free_thresh;
1758 q->drop_en = conf->rx_drop_en;
1759 q->rx_deferred_start = conf->rx_deferred_start;
1765 * Hardware requires specific alignment for Rx packet buffers. At
1766 * least one of the following two conditions must be satisfied.
1767 * 1. Address is 512B aligned
1768 * 2. Address is 8B aligned and buffer does not cross 4K boundary.
1770 * As such, the driver may need to adjust the DMA address within the
1771 * buffer by up to 512B.
1773 * return 1 if the element size is valid, otherwise return 0.
1776 mempool_element_size_valid(struct rte_mempool *mp)
1780 /* elt_size includes mbuf header and headroom */
1781 min_size = mp->elt_size - sizeof(struct rte_mbuf) -
1782 RTE_PKTMBUF_HEADROOM;
1784 /* account for up to 512B of alignment */
1785 min_size -= FM10K_RX_DATABUF_ALIGN;
1787 /* sanity check for overflow */
1788 if (min_size > mp->elt_size)
1796 fm10k_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1797 uint16_t nb_desc, unsigned int socket_id,
1798 const struct rte_eth_rxconf *conf, struct rte_mempool *mp)
1800 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1801 struct fm10k_dev_info *dev_info = FM10K_DEV_PRIVATE_TO_INFO(dev);
1802 struct fm10k_rx_queue *q;
1803 const struct rte_memzone *mz;
1805 PMD_INIT_FUNC_TRACE();
1807 /* make sure the mempool element size can account for alignment. */
1808 if (!mempool_element_size_valid(mp)) {
1809 PMD_INIT_LOG(ERR, "Error : Mempool element size is too small");
1813 /* make sure a valid number of descriptors have been requested */
1814 if (check_nb_desc(FM10K_MIN_RX_DESC, FM10K_MAX_RX_DESC,
1815 FM10K_MULT_RX_DESC, nb_desc)) {
1816 PMD_INIT_LOG(ERR, "Number of Rx descriptors (%u) must be "
1817 "less than or equal to %"PRIu32", "
1818 "greater than or equal to %u, "
1819 "and a multiple of %u",
1820 nb_desc, (uint32_t)FM10K_MAX_RX_DESC, FM10K_MIN_RX_DESC,
1821 FM10K_MULT_RX_DESC);
1826 * if this queue existed already, free the associated memory. The
1827 * queue cannot be reused in case we need to allocate memory on
1828 * different socket than was previously used.
1830 if (dev->data->rx_queues[queue_id] != NULL) {
1831 rx_queue_free(dev->data->rx_queues[queue_id]);
1832 dev->data->rx_queues[queue_id] = NULL;
1835 /* allocate memory for the queue structure */
1836 q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1839 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1845 q->nb_desc = nb_desc;
1846 q->nb_fake_desc = FM10K_MULT_RX_DESC;
1847 q->port_id = dev->data->port_id;
1848 q->queue_id = queue_id;
1849 q->tail_ptr = (volatile uint32_t *)
1850 &((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];
1851 if (handle_rxconf(q, conf))
1854 /* allocate memory for the software ring */
1855 q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1856 (nb_desc + q->nb_fake_desc) * sizeof(struct rte_mbuf *),
1857 RTE_CACHE_LINE_SIZE, socket_id);
1858 if (q->sw_ring == NULL) {
1859 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1865 * allocate memory for the hardware descriptor ring. A memzone large
1866 * enough to hold the maximum ring size is requested to allow for
1867 * resizing in later calls to the queue setup function.
1869 mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_id,
1870 FM10K_MAX_RX_RING_SZ, FM10K_ALIGN_RX_DESC,
1873 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1874 rte_free(q->sw_ring);
1878 q->hw_ring = mz->addr;
1879 q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1881 /* Check if number of descs satisfied Vector requirement */
1882 if (!rte_is_power_of_2(nb_desc)) {
1883 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
1884 "preconditions - canceling the feature for "
1885 "the whole port[%d]",
1886 q->queue_id, q->port_id);
1887 dev_info->rx_vec_allowed = false;
1889 fm10k_rxq_vec_setup(q);
1891 dev->data->rx_queues[queue_id] = q;
1896 fm10k_rx_queue_release(void *queue)
1898 PMD_INIT_FUNC_TRACE();
1900 rx_queue_free(queue);
1904 handle_txconf(struct fm10k_tx_queue *q, const struct rte_eth_txconf *conf)
1906 uint16_t tx_free_thresh;
1907 uint16_t tx_rs_thresh;
1909 /* constraint MACROs require that tx_free_thresh is configured
1910 * before tx_rs_thresh */
1911 if (conf->tx_free_thresh == 0)
1912 tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(q);
1914 tx_free_thresh = conf->tx_free_thresh;
1916 /* make sure the requested threshold satisfies the constraints */
1917 if (check_thresh(FM10K_TX_FREE_THRESH_MIN(q),
1918 FM10K_TX_FREE_THRESH_MAX(q),
1919 FM10K_TX_FREE_THRESH_DIV(q),
1921 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be "
1922 "less than or equal to %u, "
1923 "greater than or equal to %u, "
1924 "and a divisor of %u",
1925 tx_free_thresh, FM10K_TX_FREE_THRESH_MAX(q),
1926 FM10K_TX_FREE_THRESH_MIN(q),
1927 FM10K_TX_FREE_THRESH_DIV(q));
1931 q->free_thresh = tx_free_thresh;
1933 if (conf->tx_rs_thresh == 0)
1934 tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(q);
1936 tx_rs_thresh = conf->tx_rs_thresh;
1938 q->tx_deferred_start = conf->tx_deferred_start;
1940 /* make sure the requested threshold satisfies the constraints */
1941 if (check_thresh(FM10K_TX_RS_THRESH_MIN(q),
1942 FM10K_TX_RS_THRESH_MAX(q),
1943 FM10K_TX_RS_THRESH_DIV(q),
1945 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be "
1946 "less than or equal to %u, "
1947 "greater than or equal to %u, "
1948 "and a divisor of %u",
1949 tx_rs_thresh, FM10K_TX_RS_THRESH_MAX(q),
1950 FM10K_TX_RS_THRESH_MIN(q),
1951 FM10K_TX_RS_THRESH_DIV(q));
1955 q->rs_thresh = tx_rs_thresh;
1961 fm10k_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1962 uint16_t nb_desc, unsigned int socket_id,
1963 const struct rte_eth_txconf *conf)
1965 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1966 struct fm10k_tx_queue *q;
1967 const struct rte_memzone *mz;
1969 PMD_INIT_FUNC_TRACE();
1971 /* make sure a valid number of descriptors have been requested */
1972 if (check_nb_desc(FM10K_MIN_TX_DESC, FM10K_MAX_TX_DESC,
1973 FM10K_MULT_TX_DESC, nb_desc)) {
1974 PMD_INIT_LOG(ERR, "Number of Tx descriptors (%u) must be "
1975 "less than or equal to %"PRIu32", "
1976 "greater than or equal to %u, "
1977 "and a multiple of %u",
1978 nb_desc, (uint32_t)FM10K_MAX_TX_DESC, FM10K_MIN_TX_DESC,
1979 FM10K_MULT_TX_DESC);
1984 * if this queue existed already, free the associated memory. The
1985 * queue cannot be reused in case we need to allocate memory on
1986 * different socket than was previously used.
1988 if (dev->data->tx_queues[queue_id] != NULL) {
1989 struct fm10k_tx_queue *txq = dev->data->tx_queues[queue_id];
1992 dev->data->tx_queues[queue_id] = NULL;
1995 /* allocate memory for the queue structure */
1996 q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1999 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
2004 q->nb_desc = nb_desc;
2005 q->port_id = dev->data->port_id;
2006 q->queue_id = queue_id;
2007 q->txq_flags = conf->txq_flags;
2008 q->ops = &def_txq_ops;
2009 q->tail_ptr = (volatile uint32_t *)
2010 &((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];
2011 if (handle_txconf(q, conf))
2014 /* allocate memory for the software ring */
2015 q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
2016 nb_desc * sizeof(struct rte_mbuf *),
2017 RTE_CACHE_LINE_SIZE, socket_id);
2018 if (q->sw_ring == NULL) {
2019 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
2025 * allocate memory for the hardware descriptor ring. A memzone large
2026 * enough to hold the maximum ring size is requested to allow for
2027 * resizing in later calls to the queue setup function.
2029 mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_id,
2030 FM10K_MAX_TX_RING_SZ, FM10K_ALIGN_TX_DESC,
2033 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
2034 rte_free(q->sw_ring);
2038 q->hw_ring = mz->addr;
2039 q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2042 * allocate memory for the RS bit tracker. Enough slots to hold the
2043 * descriptor index for each RS bit needing to be set are required.
2045 q->rs_tracker.list = rte_zmalloc_socket("fm10k rs tracker",
2046 ((nb_desc + 1) / q->rs_thresh) *
2048 RTE_CACHE_LINE_SIZE, socket_id);
2049 if (q->rs_tracker.list == NULL) {
2050 PMD_INIT_LOG(ERR, "Cannot allocate RS bit tracker");
2051 rte_free(q->sw_ring);
2056 dev->data->tx_queues[queue_id] = q;
2061 fm10k_tx_queue_release(void *queue)
2063 struct fm10k_tx_queue *q = queue;
2064 PMD_INIT_FUNC_TRACE();
2070 fm10k_reta_update(struct rte_eth_dev *dev,
2071 struct rte_eth_rss_reta_entry64 *reta_conf,
2074 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2075 uint16_t i, j, idx, shift;
2079 PMD_INIT_FUNC_TRACE();
2081 if (reta_size > FM10K_MAX_RSS_INDICES) {
2082 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2083 "(%d) doesn't match the number hardware can supported "
2084 "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2089 * Update Redirection Table RETA[n], n=0..31. The redirection table has
2090 * 128-entries in 32 registers
2092 for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2093 idx = i / RTE_RETA_GROUP_SIZE;
2094 shift = i % RTE_RETA_GROUP_SIZE;
2095 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2096 BIT_MASK_PER_UINT32);
2101 if (mask != BIT_MASK_PER_UINT32)
2102 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2104 for (j = 0; j < CHARS_PER_UINT32; j++) {
2105 if (mask & (0x1 << j)) {
2107 reta &= ~(UINT8_MAX << CHAR_BIT * j);
2108 reta |= reta_conf[idx].reta[shift + j] <<
2112 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2), reta);
2119 fm10k_reta_query(struct rte_eth_dev *dev,
2120 struct rte_eth_rss_reta_entry64 *reta_conf,
2123 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2124 uint16_t i, j, idx, shift;
2128 PMD_INIT_FUNC_TRACE();
2130 if (reta_size < FM10K_MAX_RSS_INDICES) {
2131 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2132 "(%d) doesn't match the number hardware can supported "
2133 "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2138 * Read Redirection Table RETA[n], n=0..31. The redirection table has
2139 * 128-entries in 32 registers
2141 for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2142 idx = i / RTE_RETA_GROUP_SIZE;
2143 shift = i % RTE_RETA_GROUP_SIZE;
2144 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2145 BIT_MASK_PER_UINT32);
2149 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2150 for (j = 0; j < CHARS_PER_UINT32; j++) {
2151 if (mask & (0x1 << j))
2152 reta_conf[idx].reta[shift + j] = ((reta >>
2153 CHAR_BIT * j) & UINT8_MAX);
2161 fm10k_rss_hash_update(struct rte_eth_dev *dev,
2162 struct rte_eth_rss_conf *rss_conf)
2164 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2165 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2167 uint64_t hf = rss_conf->rss_hf;
2170 PMD_INIT_FUNC_TRACE();
2172 if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2173 FM10K_RSSRK_ENTRIES_PER_REG))
2180 mrqc |= (hf & ETH_RSS_IPV4) ? FM10K_MRQC_IPV4 : 0;
2181 mrqc |= (hf & ETH_RSS_IPV6) ? FM10K_MRQC_IPV6 : 0;
2182 mrqc |= (hf & ETH_RSS_IPV6_EX) ? FM10K_MRQC_IPV6 : 0;
2183 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? FM10K_MRQC_TCP_IPV4 : 0;
2184 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? FM10K_MRQC_TCP_IPV6 : 0;
2185 mrqc |= (hf & ETH_RSS_IPV6_TCP_EX) ? FM10K_MRQC_TCP_IPV6 : 0;
2186 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? FM10K_MRQC_UDP_IPV4 : 0;
2187 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? FM10K_MRQC_UDP_IPV6 : 0;
2188 mrqc |= (hf & ETH_RSS_IPV6_UDP_EX) ? FM10K_MRQC_UDP_IPV6 : 0;
2190 /* If the mapping doesn't fit any supported, return */
2195 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2196 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
2198 FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
2204 fm10k_rss_hash_conf_get(struct rte_eth_dev *dev,
2205 struct rte_eth_rss_conf *rss_conf)
2207 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2208 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2213 PMD_INIT_FUNC_TRACE();
2215 if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2216 FM10K_RSSRK_ENTRIES_PER_REG))
2220 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2221 key[i] = FM10K_READ_REG(hw, FM10K_RSSRK(0, i));
2223 mrqc = FM10K_READ_REG(hw, FM10K_MRQC(0));
2225 hf |= (mrqc & FM10K_MRQC_IPV4) ? ETH_RSS_IPV4 : 0;
2226 hf |= (mrqc & FM10K_MRQC_IPV6) ? ETH_RSS_IPV6 : 0;
2227 hf |= (mrqc & FM10K_MRQC_IPV6) ? ETH_RSS_IPV6_EX : 0;
2228 hf |= (mrqc & FM10K_MRQC_TCP_IPV4) ? ETH_RSS_NONFRAG_IPV4_TCP : 0;
2229 hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_NONFRAG_IPV6_TCP : 0;
2230 hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_IPV6_TCP_EX : 0;
2231 hf |= (mrqc & FM10K_MRQC_UDP_IPV4) ? ETH_RSS_NONFRAG_IPV4_UDP : 0;
2232 hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_NONFRAG_IPV6_UDP : 0;
2233 hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_IPV6_UDP_EX : 0;
2235 rss_conf->rss_hf = hf;
2241 fm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)
2243 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2244 uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2246 /* Bind all local non-queue interrupt to vector 0 */
2247 int_map |= FM10K_MISC_VEC_ID;
2249 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2250 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2251 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2252 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2253 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2254 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2256 /* Enable misc causes */
2257 FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
2258 FM10K_EIMR_ENABLE(THI_FAULT) |
2259 FM10K_EIMR_ENABLE(FUM_FAULT) |
2260 FM10K_EIMR_ENABLE(MAILBOX) |
2261 FM10K_EIMR_ENABLE(SWITCHREADY) |
2262 FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
2263 FM10K_EIMR_ENABLE(SRAMERROR) |
2264 FM10K_EIMR_ENABLE(VFLR));
2267 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2268 FM10K_ITR_MASK_CLEAR);
2269 FM10K_WRITE_FLUSH(hw);
2273 fm10k_dev_disable_intr_pf(struct rte_eth_dev *dev)
2275 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2276 uint32_t int_map = FM10K_INT_MAP_DISABLE;
2278 int_map |= FM10K_MISC_VEC_ID;
2280 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2281 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2282 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2283 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2284 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2285 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2287 /* Disable misc causes */
2288 FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(PCA_FAULT) |
2289 FM10K_EIMR_DISABLE(THI_FAULT) |
2290 FM10K_EIMR_DISABLE(FUM_FAULT) |
2291 FM10K_EIMR_DISABLE(MAILBOX) |
2292 FM10K_EIMR_DISABLE(SWITCHREADY) |
2293 FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
2294 FM10K_EIMR_DISABLE(SRAMERROR) |
2295 FM10K_EIMR_DISABLE(VFLR));
2298 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_MASK_SET);
2299 FM10K_WRITE_FLUSH(hw);
2303 fm10k_dev_enable_intr_vf(struct rte_eth_dev *dev)
2305 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2306 uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2308 /* Bind all local non-queue interrupt to vector 0 */
2309 int_map |= FM10K_MISC_VEC_ID;
2311 /* Only INT 0 available, other 15 are reserved. */
2312 FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2315 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2316 FM10K_ITR_MASK_CLEAR);
2317 FM10K_WRITE_FLUSH(hw);
2321 fm10k_dev_disable_intr_vf(struct rte_eth_dev *dev)
2323 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2324 uint32_t int_map = FM10K_INT_MAP_DISABLE;
2326 int_map |= FM10K_MISC_VEC_ID;
2328 /* Only INT 0 available, other 15 are reserved. */
2329 FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2332 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_MASK_SET);
2333 FM10K_WRITE_FLUSH(hw);
2337 fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2339 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2340 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
2343 if (hw->mac.type == fm10k_mac_pf)
2344 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2345 FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2347 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2348 FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2349 rte_intr_enable(&pdev->intr_handle);
2354 fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2356 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2357 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
2360 if (hw->mac.type == fm10k_mac_pf)
2361 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2362 FM10K_ITR_MASK_SET);
2364 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2365 FM10K_ITR_MASK_SET);
2370 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2372 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2373 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
2374 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
2375 uint32_t intr_vector, vec;
2379 /* fm10k needs one separate interrupt for mailbox,
2380 * so only drivers which support multiple interrupt vectors
2381 * e.g. vfio-pci can work for fm10k interrupt mode
2383 if (!rte_intr_cap_multiple(intr_handle) ||
2384 dev->data->dev_conf.intr_conf.rxq == 0)
2387 intr_vector = dev->data->nb_rx_queues;
2389 /* disable interrupt first */
2390 rte_intr_disable(intr_handle);
2391 if (hw->mac.type == fm10k_mac_pf)
2392 fm10k_dev_disable_intr_pf(dev);
2394 fm10k_dev_disable_intr_vf(dev);
2396 if (rte_intr_efd_enable(intr_handle, intr_vector)) {
2397 PMD_INIT_LOG(ERR, "Failed to init event fd");
2401 if (rte_intr_dp_is_en(intr_handle) && !result) {
2402 intr_handle->intr_vec = rte_zmalloc("intr_vec",
2403 dev->data->nb_rx_queues * sizeof(int), 0);
2404 if (intr_handle->intr_vec) {
2405 for (queue_id = 0, vec = FM10K_RX_VEC_START;
2406 queue_id < dev->data->nb_rx_queues;
2408 intr_handle->intr_vec[queue_id] = vec;
2409 if (vec < intr_handle->nb_efd - 1
2410 + FM10K_RX_VEC_START)
2414 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2415 " intr_vec", dev->data->nb_rx_queues);
2416 rte_intr_efd_disable(intr_handle);
2421 if (hw->mac.type == fm10k_mac_pf)
2422 fm10k_dev_enable_intr_pf(dev);
2424 fm10k_dev_enable_intr_vf(dev);
2425 rte_intr_enable(intr_handle);
2426 hw->mac.ops.update_int_moderator(hw);
2431 fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr)
2433 struct fm10k_fault fault;
2435 const char *estr = "Unknown error";
2437 /* Process PCA fault */
2438 if (eicr & FM10K_EICR_PCA_FAULT) {
2439 err = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault);
2442 switch (fault.type) {
2444 estr = "PCA_NO_FAULT"; break;
2445 case PCA_UNMAPPED_ADDR:
2446 estr = "PCA_UNMAPPED_ADDR"; break;
2447 case PCA_BAD_QACCESS_PF:
2448 estr = "PCA_BAD_QACCESS_PF"; break;
2449 case PCA_BAD_QACCESS_VF:
2450 estr = "PCA_BAD_QACCESS_VF"; break;
2451 case PCA_MALICIOUS_REQ:
2452 estr = "PCA_MALICIOUS_REQ"; break;
2453 case PCA_POISONED_TLP:
2454 estr = "PCA_POISONED_TLP"; break;
2456 estr = "PCA_TLP_ABORT"; break;
2460 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2461 estr, fault.func ? "VF" : "PF", fault.func,
2462 fault.address, fault.specinfo);
2465 /* Process THI fault */
2466 if (eicr & FM10K_EICR_THI_FAULT) {
2467 err = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault);
2470 switch (fault.type) {
2472 estr = "THI_NO_FAULT"; break;
2473 case THI_MAL_DIS_Q_FAULT:
2474 estr = "THI_MAL_DIS_Q_FAULT"; break;
2478 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2479 estr, fault.func ? "VF" : "PF", fault.func,
2480 fault.address, fault.specinfo);
2483 /* Process FUM fault */
2484 if (eicr & FM10K_EICR_FUM_FAULT) {
2485 err = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault);
2488 switch (fault.type) {
2490 estr = "FUM_NO_FAULT"; break;
2491 case FUM_UNMAPPED_ADDR:
2492 estr = "FUM_UNMAPPED_ADDR"; break;
2493 case FUM_POISONED_TLP:
2494 estr = "FUM_POISONED_TLP"; break;
2495 case FUM_BAD_VF_QACCESS:
2496 estr = "FUM_BAD_VF_QACCESS"; break;
2497 case FUM_ADD_DECODE_ERR:
2498 estr = "FUM_ADD_DECODE_ERR"; break;
2500 estr = "FUM_RO_ERROR"; break;
2501 case FUM_QPRC_CRC_ERROR:
2502 estr = "FUM_QPRC_CRC_ERROR"; break;
2503 case FUM_CSR_TIMEOUT:
2504 estr = "FUM_CSR_TIMEOUT"; break;
2505 case FUM_INVALID_TYPE:
2506 estr = "FUM_INVALID_TYPE"; break;
2507 case FUM_INVALID_LENGTH:
2508 estr = "FUM_INVALID_LENGTH"; break;
2509 case FUM_INVALID_BE:
2510 estr = "FUM_INVALID_BE"; break;
2511 case FUM_INVALID_ALIGN:
2512 estr = "FUM_INVALID_ALIGN"; break;
2516 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2517 estr, fault.func ? "VF" : "PF", fault.func,
2518 fault.address, fault.specinfo);
2523 PMD_INIT_LOG(ERR, "Failed to handle fault event.");
2528 * PF interrupt handler triggered by NIC for handling specific interrupt.
2531 * Pointer to interrupt handle.
2533 * The address of parameter (struct rte_eth_dev *) regsitered before.
2539 fm10k_dev_interrupt_handler_pf(
2540 struct rte_intr_handle *handle,
2543 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2544 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2545 uint32_t cause, status;
2547 if (hw->mac.type != fm10k_mac_pf)
2550 cause = FM10K_READ_REG(hw, FM10K_EICR);
2552 /* Handle PCI fault cases */
2553 if (cause & FM10K_EICR_FAULT_MASK) {
2554 PMD_INIT_LOG(ERR, "INT: find fault!");
2555 fm10k_dev_handle_fault(hw, cause);
2558 /* Handle switch up/down */
2559 if (cause & FM10K_EICR_SWITCHNOTREADY)
2560 PMD_INIT_LOG(ERR, "INT: Switch is not ready");
2562 if (cause & FM10K_EICR_SWITCHREADY)
2563 PMD_INIT_LOG(INFO, "INT: Switch is ready");
2565 /* Handle mailbox message */
2567 hw->mbx.ops.process(hw, &hw->mbx);
2568 fm10k_mbx_unlock(hw);
2570 /* Handle SRAM error */
2571 if (cause & FM10K_EICR_SRAMERROR) {
2572 PMD_INIT_LOG(ERR, "INT: SRAM error on PEP");
2574 status = FM10K_READ_REG(hw, FM10K_SRAM_IP);
2575 /* Write to clear pending bits */
2576 FM10K_WRITE_REG(hw, FM10K_SRAM_IP, status);
2578 /* Todo: print out error message after shared code updates */
2581 /* Clear these 3 events if having any */
2582 cause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |
2583 FM10K_EICR_SWITCHREADY;
2585 FM10K_WRITE_REG(hw, FM10K_EICR, cause);
2587 /* Re-enable interrupt from device side */
2588 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2589 FM10K_ITR_MASK_CLEAR);
2590 /* Re-enable interrupt from host side */
2591 rte_intr_enable(handle);
2595 * VF interrupt handler triggered by NIC for handling specific interrupt.
2598 * Pointer to interrupt handle.
2600 * The address of parameter (struct rte_eth_dev *) regsitered before.
2606 fm10k_dev_interrupt_handler_vf(
2607 struct rte_intr_handle *handle,
2610 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2611 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2613 if (hw->mac.type != fm10k_mac_vf)
2616 /* Handle mailbox message if lock is acquired */
2618 hw->mbx.ops.process(hw, &hw->mbx);
2619 fm10k_mbx_unlock(hw);
2621 /* Re-enable interrupt from device side */
2622 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2623 FM10K_ITR_MASK_CLEAR);
2624 /* Re-enable interrupt from host side */
2625 rte_intr_enable(handle);
2628 /* Mailbox message handler in VF */
2629 static const struct fm10k_msg_data fm10k_msgdata_vf[] = {
2630 FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
2631 FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
2632 FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
2633 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
2637 fm10k_setup_mbx_service(struct fm10k_hw *hw)
2641 /* Initialize mailbox lock */
2642 fm10k_mbx_initlock(hw);
2644 /* Replace default message handler with new ones */
2645 if (hw->mac.type == fm10k_mac_vf)
2646 err = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_vf);
2649 PMD_INIT_LOG(ERR, "Failed to register mailbox handler.err:%d",
2653 /* Connect to SM for PF device or PF for VF device */
2654 return hw->mbx.ops.connect(hw, &hw->mbx);
2658 fm10k_close_mbx_service(struct fm10k_hw *hw)
2660 /* Disconnect from SM for PF device or PF for VF device */
2661 hw->mbx.ops.disconnect(hw, &hw->mbx);
2664 static const struct eth_dev_ops fm10k_eth_dev_ops = {
2665 .dev_configure = fm10k_dev_configure,
2666 .dev_start = fm10k_dev_start,
2667 .dev_stop = fm10k_dev_stop,
2668 .dev_close = fm10k_dev_close,
2669 .promiscuous_enable = fm10k_dev_promiscuous_enable,
2670 .promiscuous_disable = fm10k_dev_promiscuous_disable,
2671 .allmulticast_enable = fm10k_dev_allmulticast_enable,
2672 .allmulticast_disable = fm10k_dev_allmulticast_disable,
2673 .stats_get = fm10k_stats_get,
2674 .xstats_get = fm10k_xstats_get,
2675 .xstats_get_names = fm10k_xstats_get_names,
2676 .stats_reset = fm10k_stats_reset,
2677 .xstats_reset = fm10k_stats_reset,
2678 .link_update = fm10k_link_update,
2679 .dev_infos_get = fm10k_dev_infos_get,
2680 .dev_supported_ptypes_get = fm10k_dev_supported_ptypes_get,
2681 .vlan_filter_set = fm10k_vlan_filter_set,
2682 .vlan_offload_set = fm10k_vlan_offload_set,
2683 .mac_addr_add = fm10k_macaddr_add,
2684 .mac_addr_remove = fm10k_macaddr_remove,
2685 .rx_queue_start = fm10k_dev_rx_queue_start,
2686 .rx_queue_stop = fm10k_dev_rx_queue_stop,
2687 .tx_queue_start = fm10k_dev_tx_queue_start,
2688 .tx_queue_stop = fm10k_dev_tx_queue_stop,
2689 .rx_queue_setup = fm10k_rx_queue_setup,
2690 .rx_queue_release = fm10k_rx_queue_release,
2691 .tx_queue_setup = fm10k_tx_queue_setup,
2692 .tx_queue_release = fm10k_tx_queue_release,
2693 .rx_descriptor_done = fm10k_dev_rx_descriptor_done,
2694 .rx_queue_intr_enable = fm10k_dev_rx_queue_intr_enable,
2695 .rx_queue_intr_disable = fm10k_dev_rx_queue_intr_disable,
2696 .reta_update = fm10k_reta_update,
2697 .reta_query = fm10k_reta_query,
2698 .rss_hash_update = fm10k_rss_hash_update,
2699 .rss_hash_conf_get = fm10k_rss_hash_conf_get,
2702 static int ftag_check_handler(__rte_unused const char *key,
2703 const char *value, __rte_unused void *opaque)
2705 if (strcmp(value, "1"))
2712 fm10k_check_ftag(struct rte_devargs *devargs)
2714 struct rte_kvargs *kvlist;
2715 const char *ftag_key = "enable_ftag";
2717 if (devargs == NULL)
2720 kvlist = rte_kvargs_parse(devargs->args, NULL);
2724 if (!rte_kvargs_count(kvlist, ftag_key)) {
2725 rte_kvargs_free(kvlist);
2728 /* FTAG is enabled when there's key-value pair: enable_ftag=1 */
2729 if (rte_kvargs_process(kvlist, ftag_key,
2730 ftag_check_handler, NULL) < 0) {
2731 rte_kvargs_free(kvlist);
2734 rte_kvargs_free(kvlist);
2739 static void __attribute__((cold))
2740 fm10k_set_tx_function(struct rte_eth_dev *dev)
2742 struct fm10k_tx_queue *txq;
2745 uint16_t tx_ftag_en = 0;
2747 if (fm10k_check_ftag(dev->device->devargs))
2750 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2751 txq = dev->data->tx_queues[i];
2752 txq->tx_ftag_en = tx_ftag_en;
2753 /* Check if Vector Tx is satisfied */
2754 if (fm10k_tx_vec_condition_check(txq))
2759 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2760 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2761 txq = dev->data->tx_queues[i];
2762 fm10k_txq_vec_setup(txq);
2764 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2766 dev->tx_pkt_burst = fm10k_xmit_pkts;
2767 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2771 static void __attribute__((cold))
2772 fm10k_set_rx_function(struct rte_eth_dev *dev)
2774 struct fm10k_dev_info *dev_info = FM10K_DEV_PRIVATE_TO_INFO(dev);
2775 uint16_t i, rx_using_sse;
2776 uint16_t rx_ftag_en = 0;
2778 if (fm10k_check_ftag(dev->device->devargs))
2781 /* In order to allow Vector Rx there are a few configuration
2782 * conditions to be met.
2784 if (!fm10k_rx_vec_condition_check(dev) &&
2785 dev_info->rx_vec_allowed && !rx_ftag_en) {
2786 if (dev->data->scattered_rx)
2787 dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec;
2789 dev->rx_pkt_burst = fm10k_recv_pkts_vec;
2790 } else if (dev->data->scattered_rx)
2791 dev->rx_pkt_burst = fm10k_recv_scattered_pkts;
2793 dev->rx_pkt_burst = fm10k_recv_pkts;
2796 (dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec ||
2797 dev->rx_pkt_burst == fm10k_recv_pkts_vec);
2800 PMD_INIT_LOG(DEBUG, "Use vector Rx func");
2802 PMD_INIT_LOG(DEBUG, "Use regular Rx func");
2804 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2805 struct fm10k_rx_queue *rxq = dev->data->rx_queues[i];
2807 rxq->rx_using_sse = rx_using_sse;
2808 rxq->rx_ftag_en = rx_ftag_en;
2813 fm10k_params_init(struct rte_eth_dev *dev)
2815 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2816 struct fm10k_dev_info *info = FM10K_DEV_PRIVATE_TO_INFO(dev);
2818 /* Inialize bus info. Normally we would call fm10k_get_bus_info(), but
2819 * there is no way to get link status without reading BAR4. Until this
2820 * works, assume we have maximum bandwidth.
2821 * @todo - fix bus info
2823 hw->bus_caps.speed = fm10k_bus_speed_8000;
2824 hw->bus_caps.width = fm10k_bus_width_pcie_x8;
2825 hw->bus_caps.payload = fm10k_bus_payload_512;
2826 hw->bus.speed = fm10k_bus_speed_8000;
2827 hw->bus.width = fm10k_bus_width_pcie_x8;
2828 hw->bus.payload = fm10k_bus_payload_256;
2830 info->rx_vec_allowed = true;
2834 eth_fm10k_dev_init(struct rte_eth_dev *dev)
2836 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2837 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
2838 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
2840 struct fm10k_macvlan_filter_info *macvlan;
2842 PMD_INIT_FUNC_TRACE();
2844 dev->dev_ops = &fm10k_eth_dev_ops;
2845 dev->rx_pkt_burst = &fm10k_recv_pkts;
2846 dev->tx_pkt_burst = &fm10k_xmit_pkts;
2848 /* only initialize in the primary process */
2849 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2852 rte_eth_copy_pci_info(dev, pdev);
2854 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
2855 memset(macvlan, 0, sizeof(*macvlan));
2856 /* Vendor and Device ID need to be set before init of shared code */
2857 memset(hw, 0, sizeof(*hw));
2858 hw->device_id = pdev->id.device_id;
2859 hw->vendor_id = pdev->id.vendor_id;
2860 hw->subsystem_device_id = pdev->id.subsystem_device_id;
2861 hw->subsystem_vendor_id = pdev->id.subsystem_vendor_id;
2862 hw->revision_id = 0;
2863 hw->hw_addr = (void *)pdev->mem_resource[0].addr;
2864 if (hw->hw_addr == NULL) {
2865 PMD_INIT_LOG(ERR, "Bad mem resource."
2866 " Try to blacklist unused devices.");
2870 /* Store fm10k_adapter pointer */
2871 hw->back = dev->data->dev_private;
2873 /* Initialize the shared code */
2874 diag = fm10k_init_shared_code(hw);
2875 if (diag != FM10K_SUCCESS) {
2876 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
2880 /* Initialize parameters */
2881 fm10k_params_init(dev);
2883 /* Initialize the hw */
2884 diag = fm10k_init_hw(hw);
2885 if (diag != FM10K_SUCCESS) {
2886 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
2890 /* Initialize MAC address(es) */
2891 dev->data->mac_addrs = rte_zmalloc("fm10k",
2892 ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM, 0);
2893 if (dev->data->mac_addrs == NULL) {
2894 PMD_INIT_LOG(ERR, "Cannot allocate memory for MAC addresses");
2898 diag = fm10k_read_mac_addr(hw);
2900 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2901 &dev->data->mac_addrs[0]);
2903 if (diag != FM10K_SUCCESS ||
2904 !is_valid_assigned_ether_addr(dev->data->mac_addrs)) {
2906 /* Generate a random addr */
2907 eth_random_addr(hw->mac.addr);
2908 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
2909 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2910 &dev->data->mac_addrs[0]);
2913 /* Reset the hw statistics */
2914 fm10k_stats_reset(dev);
2917 diag = fm10k_reset_hw(hw);
2918 if (diag != FM10K_SUCCESS) {
2919 PMD_INIT_LOG(ERR, "Hardware reset failed: %d", diag);
2923 /* Setup mailbox service */
2924 diag = fm10k_setup_mbx_service(hw);
2925 if (diag != FM10K_SUCCESS) {
2926 PMD_INIT_LOG(ERR, "Failed to setup mailbox: %d", diag);
2930 /*PF/VF has different interrupt handling mechanism */
2931 if (hw->mac.type == fm10k_mac_pf) {
2932 /* register callback func to eal lib */
2933 rte_intr_callback_register(intr_handle,
2934 fm10k_dev_interrupt_handler_pf, (void *)dev);
2936 /* enable MISC interrupt */
2937 fm10k_dev_enable_intr_pf(dev);
2939 rte_intr_callback_register(intr_handle,
2940 fm10k_dev_interrupt_handler_vf, (void *)dev);
2942 fm10k_dev_enable_intr_vf(dev);
2945 /* Enable intr after callback registered */
2946 rte_intr_enable(intr_handle);
2948 hw->mac.ops.update_int_moderator(hw);
2950 /* Make sure Switch Manager is ready before going forward. */
2951 if (hw->mac.type == fm10k_mac_pf) {
2952 int switch_ready = 0;
2954 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2956 hw->mac.ops.get_host_state(hw, &switch_ready);
2957 fm10k_mbx_unlock(hw);
2960 /* Delay some time to acquire async LPORT_MAP info. */
2961 rte_delay_us(WAIT_SWITCH_MSG_US);
2964 if (switch_ready == 0) {
2965 PMD_INIT_LOG(ERR, "switch is not ready");
2971 * Below function will trigger operations on mailbox, acquire lock to
2972 * avoid race condition from interrupt handler. Operations on mailbox
2973 * FIFO will trigger interrupt to PF/SM, in which interrupt handler
2974 * will handle and generate an interrupt to our side. Then, FIFO in
2975 * mailbox will be touched.
2978 /* Enable port first */
2979 hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2982 /* Set unicast mode by default. App can change to other mode in other
2985 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
2986 FM10K_XCAST_MODE_NONE);
2988 fm10k_mbx_unlock(hw);
2990 /* Make sure default VID is ready before going forward. */
2991 if (hw->mac.type == fm10k_mac_pf) {
2992 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2993 if (hw->mac.default_vid)
2995 /* Delay some time to acquire async port VLAN info. */
2996 rte_delay_us(WAIT_SWITCH_MSG_US);
2999 if (!hw->mac.default_vid) {
3000 PMD_INIT_LOG(ERR, "default VID is not ready");
3005 /* Add default mac address */
3006 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
3007 MAIN_VSI_POOL_NUMBER);
3013 eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
3015 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3016 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
3017 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
3018 PMD_INIT_FUNC_TRACE();
3020 /* only uninitialize in the primary process */
3021 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3024 /* safe to close dev here */
3025 fm10k_dev_close(dev);
3027 dev->dev_ops = NULL;
3028 dev->rx_pkt_burst = NULL;
3029 dev->tx_pkt_burst = NULL;
3031 /* disable uio/vfio intr */
3032 rte_intr_disable(intr_handle);
3034 /*PF/VF has different interrupt handling mechanism */
3035 if (hw->mac.type == fm10k_mac_pf) {
3036 /* disable interrupt */
3037 fm10k_dev_disable_intr_pf(dev);
3039 /* unregister callback func to eal lib */
3040 rte_intr_callback_unregister(intr_handle,
3041 fm10k_dev_interrupt_handler_pf, (void *)dev);
3043 /* disable interrupt */
3044 fm10k_dev_disable_intr_vf(dev);
3046 rte_intr_callback_unregister(intr_handle,
3047 fm10k_dev_interrupt_handler_vf, (void *)dev);
3050 /* free mac memory */
3051 if (dev->data->mac_addrs) {
3052 rte_free(dev->data->mac_addrs);
3053 dev->data->mac_addrs = NULL;
3056 memset(hw, 0, sizeof(*hw));
3062 * The set of PCI devices this driver supports. This driver will enable both PF
3063 * and SRIOV-VF devices.
3065 static const struct rte_pci_id pci_id_fm10k_map[] = {
3066 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_PF) },
3067 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_SDI_FM10420_QDA2) },
3068 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_VF) },
3069 { .vendor_id = 0, /* sentinel */ },
3072 static struct eth_driver rte_pmd_fm10k = {
3074 .id_table = pci_id_fm10k_map,
3075 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3076 RTE_PCI_DRV_DETACHABLE,
3077 .probe = rte_eth_dev_pci_probe,
3078 .remove = rte_eth_dev_pci_remove,
3080 .eth_dev_init = eth_fm10k_dev_init,
3081 .eth_dev_uninit = eth_fm10k_dev_uninit,
3082 .dev_private_size = sizeof(struct fm10k_adapter),
3085 RTE_PMD_REGISTER_PCI(net_fm10k, rte_pmd_fm10k.pci_drv);
3086 RTE_PMD_REGISTER_PCI_TABLE(net_fm10k, pci_id_fm10k_map);
3087 RTE_PMD_REGISTER_KMOD_DEP(net_fm10k, "* igb_uio | uio_pci_generic | vfio");