1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Huawei Technologies Co., Ltd
5 #ifndef _HINIC_PORT_CMD_H_
6 #define _HINIC_PORT_CMD_H_
13 enum hinic_resp_aeq_num {
21 HINIC_MOD_COMM = 0, /* HW communication module */
22 HINIC_MOD_L2NIC = 1, /* L2NIC module */
23 HINIC_MOD_CFGM = 7, /* Configuration module */
24 HINIC_MOD_HILINK = 14,
28 /* only used by VFD communicating with PFD to register or unregister,
29 * command mode type is HINIC_MOD_L2NIC
31 #define HINIC_PORT_CMD_VF_REGISTER 0x0
32 #define HINIC_PORT_CMD_VF_UNREGISTER 0x1
34 /* cmd of mgmt CPU message for NIC module */
36 HINIC_PORT_CMD_MGMT_RESET = 0x0,
38 HINIC_PORT_CMD_CHANGE_MTU = 0x2,
40 HINIC_PORT_CMD_ADD_VLAN = 0x3,
41 HINIC_PORT_CMD_DEL_VLAN,
43 HINIC_PORT_CMD_SET_ETS = 0x7,
44 HINIC_PORT_CMD_GET_ETS,
46 HINIC_PORT_CMD_SET_MAC = 0x9,
47 HINIC_PORT_CMD_GET_MAC,
48 HINIC_PORT_CMD_DEL_MAC,
50 HINIC_PORT_CMD_SET_RX_MODE = 0xc,
51 HINIC_PORT_CMD_SET_ANTI_ATTACK_RATE = 0xd,
53 HINIC_PORT_CMD_GET_PAUSE_INFO = 0x14,
54 HINIC_PORT_CMD_SET_PAUSE_INFO,
56 HINIC_PORT_CMD_GET_LINK_STATE = 0x18,
57 HINIC_PORT_CMD_SET_LRO = 0x19,
58 HINIC_PORT_CMD_SET_RX_CSUM = 0x1a,
59 HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 0x1b,
61 HINIC_PORT_CMD_GET_PORT_STATISTICS = 0x1c,
62 HINIC_PORT_CMD_CLEAR_PORT_STATISTICS,
63 HINIC_PORT_CMD_GET_VPORT_STAT,
64 HINIC_PORT_CMD_CLEAN_VPORT_STAT,
66 HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 0x25,
67 HINIC_PORT_CMD_SET_RSS_TEMPLATE_INDIR_TBL,
69 HINIC_PORT_CMD_SET_PORT_ENABLE = 0x29,
70 HINIC_PORT_CMD_GET_PORT_ENABLE,
72 HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 0x2b,
73 HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL,
74 HINIC_PORT_CMD_SET_RSS_HASH_ENGINE,
75 HINIC_PORT_CMD_GET_RSS_HASH_ENGINE,
76 HINIC_PORT_CMD_GET_RSS_CTX_TBL,
77 HINIC_PORT_CMD_SET_RSS_CTX_TBL,
78 HINIC_PORT_CMD_RSS_TEMP_MGR,
80 HINIC_PORT_CMD_RSS_CFG = 0x42,
82 HINIC_PORT_CMD_GET_PHY_TYPE = 0x44,
83 HINIC_PORT_CMD_INIT_FUNC = 0x45,
85 HINIC_PORT_CMD_GET_JUMBO_FRAME_SIZE = 0x4a,
86 HINIC_PORT_CMD_SET_JUMBO_FRAME_SIZE,
88 HINIC_PORT_CMD_GET_PORT_TYPE = 0x5b,
90 HINIC_PORT_CMD_GET_VPORT_ENABLE = 0x5c,
91 HINIC_PORT_CMD_SET_VPORT_ENABLE,
93 HINIC_PORT_CMD_GET_PORT_ID_BY_FUNC_ID = 0x5e,
95 HINIC_PORT_CMD_GET_LRO = 0x63,
97 HINIC_PORT_CMD_GET_DMA_CS = 0x64,
98 HINIC_PORT_CMD_SET_DMA_CS,
100 HINIC_PORT_CMD_GET_GLOBAL_QPN = 0x66,
102 HINIC_PORT_CMD_SET_PFC_MISC = 0x67,
103 HINIC_PORT_CMD_GET_PFC_MISC,
105 HINIC_PORT_CMD_SET_VF_RATE = 0x69,
106 HINIC_PORT_CMD_SET_VF_VLAN,
107 HINIC_PORT_CMD_CLR_VF_VLAN,
109 HINIC_PORT_CMD_SET_RQ_IQ_MAP = 0x73,
110 HINIC_PORT_CMD_SET_PFC_THD = 0x75,
112 HINIC_PORT_CMD_LINK_STATUS_REPORT = 0xa0,
114 HINIC_PORT_CMD_SET_LOSSLESS_ETH = 0xa3,
115 HINIC_PORT_CMD_UPDATE_MAC = 0xa4,
117 HINIC_PORT_CMD_GET_PORT_INFO = 0xaa,
119 HINIC_PORT_CMD_SET_IPSU_MAC = 0xcb,
120 HINIC_PORT_CMD_GET_IPSU_MAC = 0xcc,
122 HINIC_PORT_CMD_SET_XSFP_STATUS = 0xD4,
124 HINIC_PORT_CMD_GET_LINK_MODE = 0xD9,
125 HINIC_PORT_CMD_SET_SPEED = 0xDA,
126 HINIC_PORT_CMD_SET_AUTONEG = 0xDB,
128 HINIC_PORT_CMD_CLEAR_QP_RES = 0xDD,
129 HINIC_PORT_CMD_SET_SUPER_CQE = 0xDE,
130 HINIC_PORT_CMD_SET_VF_COS = 0xDF,
131 HINIC_PORT_CMD_GET_VF_COS = 0xE1,
133 HINIC_PORT_CMD_CABLE_PLUG_EVENT = 0xE5,
134 HINIC_PORT_CMD_LINK_ERR_EVENT = 0xE6,
136 HINIC_PORT_CMD_SET_COS_UP_MAP = 0xE8,
138 HINIC_PORT_CMD_RESET_LINK_CFG = 0xEB,
140 HINIC_PORT_CMD_FORCE_PKT_DROP = 0xF3,
141 HINIC_PORT_CMD_SET_LRO_TIMER = 0xF4,
143 HINIC_PORT_CMD_SET_VHD_CFG = 0xF7,
144 HINIC_PORT_CMD_SET_LINK_FOLLOW = 0xF8,
145 HINIC_PORT_CMD_Q_FILTER = 0xFC,
146 HINIC_PORT_CMD_TCAM_FILTER = 0xFE,
147 HINIC_PORT_CMD_SET_VLAN_FILTER = 0xFF
150 /* cmd of mgmt CPU message for HW module */
151 enum hinic_mgmt_cmd {
152 HINIC_MGMT_CMD_RESET_MGMT = 0x0,
153 HINIC_MGMT_CMD_START_FLR = 0x1,
154 HINIC_MGMT_CMD_FLUSH_DOORBELL = 0x2,
155 HINIC_MGMT_CMD_GET_IO_STATUS = 0x3,
156 HINIC_MGMT_CMD_DMA_ATTR_SET = 0x4,
158 HINIC_MGMT_CMD_CMDQ_CTXT_SET = 0x10,
159 HINIC_MGMT_CMD_CMDQ_CTXT_GET,
161 HINIC_MGMT_CMD_VAT_SET = 0x12,
162 HINIC_MGMT_CMD_VAT_GET,
164 HINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_SET = 0x14,
165 HINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_GET,
167 HINIC_MGMT_CMD_PPF_HT_GPA_SET = 0x23,
168 HINIC_MGMT_CMD_RES_STATE_SET = 0x24,
169 HINIC_MGMT_CMD_FUNC_CACHE_OUT = 0x25,
170 HINIC_MGMT_CMD_FFM_SET = 0x26,
172 HINIC_MGMT_CMD_FUNC_RES_CLEAR = 0x29,
174 HINIC_MGMT_CMD_CEQ_CTRL_REG_WR_BY_UP = 0x33,
175 HINIC_MGMT_CMD_MSI_CTRL_REG_WR_BY_UP,
176 HINIC_MGMT_CMD_MSI_CTRL_REG_RD_BY_UP,
178 HINIC_MGMT_CMD_VF_RANDOM_ID_SET = 0x36,
179 HINIC_MGMT_CMD_FAULT_REPORT = 0x37,
181 HINIC_MGMT_CMD_VPD_SET = 0x40,
182 HINIC_MGMT_CMD_VPD_GET,
183 HINIC_MGMT_CMD_LABEL_SET,
184 HINIC_MGMT_CMD_LABEL_GET,
185 HINIC_MGMT_CMD_SATIC_MAC_SET,
186 HINIC_MGMT_CMD_SATIC_MAC_GET,
187 HINIC_MGMT_CMD_SYNC_TIME = 0x46,
188 HINIC_MGMT_CMD_SET_LED_STATUS = 0x4A,
189 HINIC_MGMT_CMD_L2NIC_RESET = 0x4b,
190 HINIC_MGMT_CMD_FAST_RECYCLE_MODE_SET = 0x4d,
191 HINIC_MGMT_CMD_BIOS_NV_DATA_MGMT = 0x4E,
192 HINIC_MGMT_CMD_ACTIVATE_FW = 0x4F,
193 HINIC_MGMT_CMD_PAGESIZE_SET = 0x50,
194 HINIC_MGMT_CMD_PAGESIZE_GET = 0x51,
195 HINIC_MGMT_CMD_GET_BOARD_INFO = 0x52,
196 HINIC_MGMT_CMD_WATCHDOG_INFO = 0x56,
197 HINIC_MGMT_CMD_FMW_ACT_NTC = 0x57,
198 HINIC_MGMT_CMD_SET_VF_RANDOM_ID = 0x61,
199 HINIC_MGMT_CMD_GET_PPF_STATE = 0x63,
200 HINIC_MGMT_CMD_PCIE_DFX_NTC = 0x65,
201 HINIC_MGMT_CMD_PCIE_DFX_GET = 0x66,
204 /* cmd of mgmt CPU message for HILINK module */
205 enum hinic_hilink_cmd {
206 HINIC_HILINK_CMD_GET_LINK_INFO = 0x3,
207 HINIC_HILINK_CMD_SET_LINK_SETTINGS = 0x8,
210 /* uCode related commands */
211 enum hinic_ucode_cmd {
212 HINIC_UCODE_CMD_MDY_QUEUE_CONTEXT = 0,
213 HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT,
214 HINIC_UCODE_CMD_ARM_SQ,
215 HINIC_UCODE_CMD_ARM_RQ,
216 HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE,
217 HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE,
218 HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE,
219 HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE,
220 HINIC_UCODE_CMD_SET_IQ_ENABLE,
221 HINIC_UCODE_CMD_SET_RQ_FLUSH = 10
226 HINIC_CFG_NIC_CAP = 0,
229 HINIC_CFG_MBOX_CAP = 6
232 enum hinic_ack_type {
234 HINIC_ACK_TYPE_SHARE_CQN,
235 HINIC_ACK_TYPE_APP_CQN,
237 HINIC_MOD_ACK_MAX = 15,
240 enum sq_l4offload_type {
242 TCP_OFFLOAD_ENABLE = 1,
243 SCTP_OFFLOAD_ENABLE = 2,
244 UDP_OFFLOAD_ENABLE = 3,
247 enum sq_vlan_offload_flag {
248 VLAN_OFFLOAD_DISABLE = 0,
249 VLAN_OFFLOAD_ENABLE = 1,
252 enum sq_pkt_parsed_flag {
260 IPV4_PKT_NO_CHKSUM_OFFLOAD = 2,
261 IPV4_PKT_WITH_CHKSUM_OFFLOAD = 3,
272 enum sq_tunnel_l4_type {
278 #define NIC_RSS_CMD_TEMP_ALLOC 0x01
279 #define NIC_RSS_CMD_TEMP_FREE 0x02
281 #define HINIC_RSS_TYPE_VALID_SHIFT 23
282 #define HINIC_RSS_TYPE_TCP_IPV6_EXT_SHIFT 24
283 #define HINIC_RSS_TYPE_IPV6_EXT_SHIFT 25
284 #define HINIC_RSS_TYPE_TCP_IPV6_SHIFT 26
285 #define HINIC_RSS_TYPE_IPV6_SHIFT 27
286 #define HINIC_RSS_TYPE_TCP_IPV4_SHIFT 28
287 #define HINIC_RSS_TYPE_IPV4_SHIFT 29
288 #define HINIC_RSS_TYPE_UDP_IPV6_SHIFT 30
289 #define HINIC_RSS_TYPE_UDP_IPV4_SHIFT 31
291 #define HINIC_RSS_TYPE_SET(val, member) \
292 (((u32)(val) & 0x1) << HINIC_RSS_TYPE_##member##_SHIFT)
294 #define HINIC_RSS_TYPE_GET(val, member) \
295 (((u32)(val) >> HINIC_RSS_TYPE_##member##_SHIFT) & 0x1)
298 HINIC_SPEED_10MB_LINK = 0,
299 HINIC_SPEED_100MB_LINK,
300 HINIC_SPEED_1000MB_LINK,
301 HINIC_SPEED_10GB_LINK,
302 HINIC_SPEED_25GB_LINK,
303 HINIC_SPEED_40GB_LINK,
304 HINIC_SPEED_100GB_LINK,
305 HINIC_SPEED_UNKNOWN = 0xFF,
309 HINIC_IFLA_VF_LINK_STATE_AUTO, /* link state of the uplink */
310 HINIC_IFLA_VF_LINK_STATE_ENABLE, /* link always up */
311 HINIC_IFLA_VF_LINK_STATE_DISABLE, /* link always down */
314 #define HINIC_AF0_FUNC_GLOBAL_IDX_SHIFT 0
315 #define HINIC_AF0_P2P_IDX_SHIFT 10
316 #define HINIC_AF0_PCI_INTF_IDX_SHIFT 14
317 #define HINIC_AF0_VF_IN_PF_SHIFT 16
318 #define HINIC_AF0_FUNC_TYPE_SHIFT 24
320 #define HINIC_AF0_FUNC_GLOBAL_IDX_MASK 0x3FF
321 #define HINIC_AF0_P2P_IDX_MASK 0xF
322 #define HINIC_AF0_PCI_INTF_IDX_MASK 0x3
323 #define HINIC_AF0_VF_IN_PF_MASK 0xFF
324 #define HINIC_AF0_FUNC_TYPE_MASK 0x1
326 #define HINIC_AF0_GET(val, member) \
327 (((val) >> HINIC_AF0_##member##_SHIFT) & HINIC_AF0_##member##_MASK)
329 #define HINIC_AF1_PPF_IDX_SHIFT 0
330 #define HINIC_AF1_AEQS_PER_FUNC_SHIFT 8
331 #define HINIC_AF1_CEQS_PER_FUNC_SHIFT 12
332 #define HINIC_AF1_IRQS_PER_FUNC_SHIFT 20
333 #define HINIC_AF1_DMA_ATTR_PER_FUNC_SHIFT 24
334 #define HINIC_AF1_MGMT_INIT_STATUS_SHIFT 30
335 #define HINIC_AF1_PF_INIT_STATUS_SHIFT 31
337 #define HINIC_AF1_PPF_IDX_MASK 0x1F
338 #define HINIC_AF1_AEQS_PER_FUNC_MASK 0x3
339 #define HINIC_AF1_CEQS_PER_FUNC_MASK 0x7
340 #define HINIC_AF1_IRQS_PER_FUNC_MASK 0xF
341 #define HINIC_AF1_DMA_ATTR_PER_FUNC_MASK 0x7
342 #define HINIC_AF1_MGMT_INIT_STATUS_MASK 0x1
343 #define HINIC_AF1_PF_INIT_STATUS_MASK 0x1
345 #define HINIC_AF1_GET(val, member) \
346 (((val) >> HINIC_AF1_##member##_SHIFT) & HINIC_AF1_##member##_MASK)
348 #define HINIC_AF2_GLOBAL_VF_ID_OF_PF_SHIFT 16
349 #define HINIC_AF2_GLOBAL_VF_ID_OF_PF_MASK 0x3FF
351 #define HINIC_AF2_GET(val, member) \
352 (((val) >> HINIC_AF2_##member##_SHIFT) & HINIC_AF2_##member##_MASK)
354 #define HINIC_AF4_OUTBOUND_CTRL_SHIFT 0
355 #define HINIC_AF4_DOORBELL_CTRL_SHIFT 1
356 #define HINIC_AF4_OUTBOUND_CTRL_MASK 0x1
357 #define HINIC_AF4_DOORBELL_CTRL_MASK 0x1
359 #define HINIC_AF4_GET(val, member) \
360 (((val) >> HINIC_AF4_##member##_SHIFT) & HINIC_AF4_##member##_MASK)
362 #define HINIC_AF4_SET(val, member) \
363 (((val) & HINIC_AF4_##member##_MASK) << HINIC_AF4_##member##_SHIFT)
365 #define HINIC_AF4_CLEAR(val, member) \
366 ((val) & (~(HINIC_AF4_##member##_MASK << \
367 HINIC_AF4_##member##_SHIFT)))
369 #define HINIC_AF5_PF_STATUS_SHIFT 0
370 #define HINIC_AF5_PF_STATUS_MASK 0xFFFF
372 #define HINIC_AF5_SET(val, member) \
373 (((val) & HINIC_AF5_##member##_MASK) << HINIC_AF5_##member##_SHIFT)
375 #define HINIC_AF5_GET(val, member) \
376 (((val) >> HINIC_AF5_##member##_SHIFT) & HINIC_AF5_##member##_MASK)
378 #define HINIC_AF5_CLEAR(val, member) \
379 ((val) & (~(HINIC_AF5_##member##_MASK << \
380 HINIC_AF5_##member##_SHIFT)))
382 #define HINIC_PPF_ELECTION_IDX_SHIFT 0
384 #define HINIC_PPF_ELECTION_IDX_MASK 0x1F
386 #define HINIC_PPF_ELECTION_SET(val, member) \
387 (((val) & HINIC_PPF_ELECTION_##member##_MASK) << \
388 HINIC_PPF_ELECTION_##member##_SHIFT)
390 #define HINIC_PPF_ELECTION_GET(val, member) \
391 (((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) & \
392 HINIC_PPF_ELECTION_##member##_MASK)
394 #define HINIC_PPF_ELECTION_CLEAR(val, member) \
395 ((val) & (~(HINIC_PPF_ELECTION_##member##_MASK \
396 << HINIC_PPF_ELECTION_##member##_SHIFT)))
398 #define DB_IDX(db, db_base) \
399 ((u32)(((unsigned long)(db) - (unsigned long)(db_base)) / \
402 enum hinic_pcie_nosnoop {
403 HINIC_PCIE_SNOOP = 0,
404 HINIC_PCIE_NO_SNOOP = 1,
407 enum hinic_pcie_tph {
408 HINIC_PCIE_TPH_DISABLE = 0,
409 HINIC_PCIE_TPH_ENABLE = 1,
412 enum hinic_outbound_ctrl {
413 ENABLE_OUTBOUND = 0x0,
414 DISABLE_OUTBOUND = 0x1,
417 enum hinic_doorbell_ctrl {
418 ENABLE_DOORBELL = 0x0,
419 DISABLE_DOORBELL = 0x1,
422 enum hinic_pf_status {
423 HINIC_PF_STATUS_INIT = 0X0,
424 HINIC_PF_STATUS_ACTIVE_FLAG = 0x11,
425 HINIC_PF_STATUS_FLR_START_FLAG = 0x12,
426 HINIC_PF_STATUS_FLR_FINISH_FLAG = 0x13,
429 /* total doorbell or direct wqe size is 512kB, db num: 128, dwqe: 128 */
430 #define HINIC_DB_DWQE_SIZE 0x00080000
432 /* db page size: 4K */
433 #define HINIC_DB_PAGE_SIZE 0x00001000ULL
435 #define HINIC_DB_MAX_AREAS (HINIC_DB_DWQE_SIZE / HINIC_DB_PAGE_SIZE)
437 #define HINIC_PCI_MSIX_ENTRY_SIZE 16
438 #define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL 12
439 #define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT 1
441 struct hinic_mgmt_msg_head {
448 struct hinic_root_ctxt {
449 struct hinic_mgmt_msg_head mgmt_msg_head;
464 #endif /* _HINIC_PORT_CMD_H_ */