drivers/net/hinic/base/hinic_pmd_eqs.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Huawei Technologies Co., Ltd
   3  */
   4
   5 #ifndef _HINIC_PMD_EQS_H_
   6 #define _HINIC_PMD_EQS_H_
   7
   8 #define HINIC_EQ_PAGE_SIZE              0x00001000
   9
  10 #define HINIC_AEQN_START                0
  11 #define HINIC_MAX_AEQS                  4
  12
  13 #define HINIC_EQ_MAX_PAGES              8
  14
  15 #define HINIC_AEQE_SIZE                 64
  16 #define HINIC_CEQE_SIZE                 4
  17
  18 #define HINIC_AEQE_DESC_SIZE            4
  19 #define HINIC_AEQE_DATA_SIZE            \
  20                         (HINIC_AEQE_SIZE - HINIC_AEQE_DESC_SIZE)
  21
  22 #define HINIC_DEFAULT_AEQ_LEN           64
  23
  24 #define GET_EQ_ELEMENT(eq, idx)         \
  25                 (((u8 *)(eq)->virt_addr[(idx) / (eq)->num_elem_in_pg]) + \
  26                 (((u32)(idx) & ((eq)->num_elem_in_pg - 1)) * (eq)->elem_size))
  27
  28 #define GET_AEQ_ELEM(eq, idx)           \
  29                         ((struct hinic_aeq_elem *)GET_EQ_ELEMENT((eq), (idx)))
  30
  31 #define GET_CEQ_ELEM(eq, idx)   ((u32 *)GET_EQ_ELEMENT((eq), (idx)))
  32
  33 enum hinic_eq_intr_mode {
  34         HINIC_INTR_MODE_ARMED,
  35         HINIC_INTR_MODE_ALWAYS,
  36 };
  37
  38 enum hinic_eq_ci_arm_state {
  39         HINIC_EQ_NOT_ARMED,
  40         HINIC_EQ_ARMED,
  41 };
  42
  43 enum hinic_aeq_type {
  44         HINIC_HW_INTER_INT = 0,
  45         HINIC_MBX_FROM_FUNC = 1,
  46         HINIC_MSG_FROM_MGMT_CPU = 2,
  47         HINIC_API_RSP = 3,
  48         HINIC_API_CHAIN_STS = 4,
  49         HINIC_MBX_SEND_RSLT = 5,
  50         HINIC_MAX_AEQ_EVENTS
  51 };
  52
  53 #define HINIC_RETRY_NUM (10)
  54
  55 struct hinic_eq {
  56         struct hinic_hwdev              *hwdev;
  57         u16                             q_id;
  58         u16                             type;
  59         u32                             page_size;
  60         u16                             eq_len;
  61
  62         u16                             cons_idx;
  63         u16                             wrapped;
  64
  65         u16                             elem_size;
  66         u16                             num_pages;
  67         u32                             num_elem_in_pg;
  68
  69         struct irq_info                 eq_irq;
  70
  71         dma_addr_t                      *dma_addr;
  72         u8                              **virt_addr;
  73
  74         u16                             poll_retry_nr;
  75 };
  76
  77 struct hinic_aeq_elem {
  78         u8      aeqe_data[HINIC_AEQE_DATA_SIZE];
  79         u32     desc;
  80 };
  81
  82 struct hinic_aeqs {
  83         struct hinic_hwdev      *hwdev;
  84         u16                     poll_retry_nr;
  85
  86         struct hinic_eq         aeq[HINIC_MAX_AEQS];
  87         u16                     num_aeqs;
  88 };
  89
  90 void eq_update_ci(struct hinic_eq *eq);
  91
  92 void hinic_dump_aeq_info(struct hinic_hwdev *hwdev);
  93
  94 int hinic_comm_aeqs_init(struct hinic_hwdev *hwdev);
  95
  96 void hinic_comm_aeqs_free(struct hinic_hwdev *hwdev);
  97
  98 #endif /* _HINIC_PMD_EQS_H_ */